diff options
Diffstat (limited to 'include/configs')
| -rw-r--r-- | include/configs/at91rm9200dk.h | 2 | ||||
| -rw-r--r-- | include/configs/cmc_pu2.h | 2 | ||||
| -rw-r--r-- | include/configs/csb637.h | 2 | ||||
| -rw-r--r-- | include/configs/mp2usb.h | 2 |
4 files changed, 4 insertions, 4 deletions
diff --git a/include/configs/at91rm9200dk.h b/include/configs/at91rm9200dk.h index 5b7212a68f..951ce160a4 100644 --- a/include/configs/at91rm9200dk.h +++ b/include/configs/at91rm9200dk.h @@ -51,7 +51,7 @@ #define MC_ASR_VAL 0x00000000 #define MC_AASR_VAL 0x00000000 #define EBI_CFGR_VAL 0x00000000 -#define SMC2_CSR_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ +#define SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ /* clocks */ #define PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */ diff --git a/include/configs/cmc_pu2.h b/include/configs/cmc_pu2.h index d22d350579..bce5fcd82f 100644 --- a/include/configs/cmc_pu2.h +++ b/include/configs/cmc_pu2.h @@ -50,7 +50,7 @@ #define MC_ASR_VAL 0x00000000 #define MC_AASR_VAL 0x00000000 #define EBI_CFGR_VAL 0x00000000 -#define SMC2_CSR_VAL 0x100032ad /* 16bit, 2 TDF, 4 WS */ +#define SMC_CSR0_VAL 0x100032ad /* 16bit, 2 TDF, 4 WS */ /* clocks */ #define PLLAR_VAL 0x2026BE04 /* 179,712 MHz for PCK */ diff --git a/include/configs/csb637.h b/include/configs/csb637.h index f93c3bcd6f..e9c6d8e7ae 100644 --- a/include/configs/csb637.h +++ b/include/configs/csb637.h @@ -51,7 +51,7 @@ #define MC_ASR_VAL 0x00000000 #define MC_AASR_VAL 0x00000000 #define EBI_CFGR_VAL 0x00000000 -#define SMC2_CSR_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ +#define SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ /* clocks */ #define PLLAR_VAL 0x2031BE01 /* 184.320000 MHz for PCK */ diff --git a/include/configs/mp2usb.h b/include/configs/mp2usb.h index 294221f941..2eb4af1554 100644 --- a/include/configs/mp2usb.h +++ b/include/configs/mp2usb.h @@ -55,7 +55,7 @@ #define MC_ASR_VAL 0x00000000 #define MC_AASR_VAL 0x00000000 #define EBI_CFGR_VAL 0x00000000 -#define SMC2_CSR_VAL 0x00003084 /* 16bit, 2 TDF, 4 WS */ +#define SMC_CSR0_VAL 0x00003084 /* 16bit, 2 TDF, 4 WS */ /* clocks */ #define PLLAR_VAL 0x20263E04 /* 180 MHz for PCK */ |