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-rw-r--r--include/configs/devkit3250.h6
-rw-r--r--include/configs/ea-lpc3250devkitv2.h37
-rw-r--r--include/configs/openpiton-riscv64.h61
-rw-r--r--include/configs/sifive-unleashed.h1
-rw-r--r--include/configs/sifive-unmatched.h7
-rw-r--r--include/configs/synquacer.h115
-rw-r--r--include/configs/work_92105.h6
7 files changed, 221 insertions, 12 deletions
diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h
index 5d2b77b4a37..465d9ce8e99 100644
--- a/include/configs/devkit3250.h
+++ b/include/configs/devkit3250.h
@@ -31,11 +31,6 @@
- GENERATED_GBL_DATA_SIZE)
/*
- * Serial Driver
- */
-#define CONFIG_SYS_LPC32XX_UART 5 /* UART5 */
-
-/*
* DMA
*/
#if !defined(CONFIG_SPL_BUILD)
@@ -46,7 +41,6 @@
* I2C
*/
#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_LPC32XX
#define CONFIG_SYS_I2C_SPEED 100000
/*
diff --git a/include/configs/ea-lpc3250devkitv2.h b/include/configs/ea-lpc3250devkitv2.h
new file mode 100644
index 00000000000..c1a37c8a790
--- /dev/null
+++ b/include/configs/ea-lpc3250devkitv2.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Embedded Artists LPC3250 DevKit v2
+ * Copyright (C) 2021 Trevor Woerner <twoerner@gmail.com>
+ */
+
+#ifndef __CONFIG_EA_LPC3250DEVKITV2_H__
+#define __CONFIG_EA_LPC3250DEVKITV2_H__
+
+#include <linux/sizes.h>
+#include <asm/arch/cpu.h>
+
+/*
+ * SoC and board defines
+ */
+#define CONFIG_MACH_TYPE MACH_TYPE_LPC3XXX
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_SIZE_LIMIT 0x000fffff /* maximum allowable size for full U-Boot binary */
+
+/*
+ * RAM
+ */
+#define CONFIG_SYS_MALLOC_LEN SZ_4M
+#define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE
+
+/*
+ * cmd
+ */
+#define CONFIG_SYS_LOAD_ADDR 0x80100000
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K - GENERATED_GBL_DATA_SIZE)
+
+/*
+ * SoC-specific config
+ */
+#include <asm/arch/config.h>
+
+#endif
diff --git a/include/configs/openpiton-riscv64.h b/include/configs/openpiton-riscv64.h
new file mode 100644
index 00000000000..42c64f3ca5e
--- /dev/null
+++ b/include/configs/openpiton-riscv64.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
+ * Copyright (c) 2021 Tianrui Wei
+ *
+ * Authors:
+ * Anup Patel <anup.patel@wdc.com>
+ * Tianrui Wei <tianrui-wei@outlook.com>
+ */
+
+#ifndef __OPENPITON_RISCV64_CONFIG_H
+#define __OPENPITON_RISCV64_CONFIG_H
+
+#include <linux/sizes.h>
+
+/* Environment options */
+#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32M)
+#define CONFIG_SYS_LOAD_ADDR 0x87000000
+#define CONFIG_SYS_MALLOC_LEN SZ_256M
+#define CONFIG_SYS_BOOTM_LEN SZ_256M
+
+#ifdef CONFIG_SPL
+#define CONFIG_SPL_MAX_SIZE 0x00100000
+#define CONFIG_SPL_BSS_START_ADDR 0x82000000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
+#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
+ CONFIG_SPL_BSS_MAX_SIZE)
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x0100000
+#define CONFIG_SPL_STACK (0x80000000 + 0x04000000 - \
+ GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "boot/fw_payload.bin"
+#define CONFIG_SPL_GD_ADDR 0x85000000
+#endif
+
+/* -------------------------------------------------
+ * Environment
+ */
+//Disable persistent environment variable storage
+#define CONFIG_ENV_IS_NOWHERE 1
+
+/* ---------------------------------------------------------------------
+ * Board boot configuration
+ */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "fdt_addr_r=0x86000000\0" \
+ "kernel_addr_r=0x80200000\0" \
+ "image=boot/Image\0" \
+ "mmcdev=0\0" \
+ "mmcpart=1\0"
+
+#define CONFIG_USE_BOOTCOMMAND
+#define CONFIG_BOOTCOMMAND \
+ "fdt addr ${fdtcontroladdr}; " \
+ "fdt move ${fdtcontroladdr} ${fdt_addr_r}; " \
+ "load mmc ${mmcdev}:${mmcpart} ${kernel_addr_r} ${image}; " \
+ "booti ${kernel_addr_r} - ${fdt_addr_r}; "
+
+#endif/* __CONFIG_H */
diff --git a/include/configs/sifive-unleashed.h b/include/configs/sifive-unleashed.h
index 0d69d1c5482..b6c29f8c604 100644
--- a/include/configs/sifive-unleashed.h
+++ b/include/configs/sifive-unleashed.h
@@ -75,6 +75,7 @@
"type_guid_gpt_loader2=" TYPE_GUID_LOADER2 "\0" \
"type_guid_gpt_system=" TYPE_GUID_SYSTEM "\0" \
"partitions=" PARTS_DEFAULT "\0" \
+ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
BOOTENV \
BOOTENV_SF
diff --git a/include/configs/sifive-unmatched.h b/include/configs/sifive-unmatched.h
index 4fad69bb199..d63a5f62fbc 100644
--- a/include/configs/sifive-unmatched.h
+++ b/include/configs/sifive-unmatched.h
@@ -73,6 +73,7 @@
"type_guid_gpt_loader2=" TYPE_GUID_LOADER2 "\0" \
"type_guid_gpt_system=" TYPE_GUID_SYSTEM "\0" \
"partitions=" PARTS_DEFAULT "\0" \
+ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
BOOTENV
#define CONFIG_PREBOOT \
@@ -80,4 +81,10 @@
"fdt addr ${fdtcontroladdr};"
#endif /* CONFIG_SPL_BUILD */
+#define CONFIG_SYS_EEPROM_BUS_NUM 0
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 0x1
+
+#define CONFIG_ID_EEPROM
+
#endif /* __SIFIVE_UNMATCHED_H */
diff --git a/include/configs/synquacer.h b/include/configs/synquacer.h
new file mode 100644
index 00000000000..8fe10d74853
--- /dev/null
+++ b/include/configs/synquacer.h
@@ -0,0 +1,115 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2016-2017 Socionext Inc.
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* Timers for fasp(TIMCLK) */
+#define CONFIG_SYS_HZ 1000 /* 1 msec */
+#define CONFIG_SYS_TIMERBASE 0x31080000 /* AP Timer 1 (ARM-SP804) */
+
+/*
+ * SDRAM (for initialize)
+ */
+#define CONFIG_SYS_SDRAM_BASE (0x80000000) /* Start address of DDR3 */
+#define PHYS_SDRAM_SIZE (0x7c000000) /* Default size (2GB - Secure memory) */
+
+#define CONFIG_VERY_BIG_RAM /* SynQuacer supports up to 64GB */
+#define CONFIG_MAX_MEM_MAPPED PHYS_SDRAM_SIZE
+
+#define SQ_DRAMINFO_BASE (0x2e00ffc0) /* DRAM info from TF-A */
+
+/*
+ * Boot info
+ */
+#define CONFIG_SYS_INIT_SP_ADDR (0xe0000000) /* stack of init proccess */
+#define CONFIG_SYS_MALLOC_LEN (0x01000000) /* 16Mbyte size of malloc() */
+#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* default kernel load address */
+
+/*
+ * Hardware drivers support
+ */
+
+/* RTC */
+#define CONFIG_SYS_I2C_RTC_ADDR 0x51
+
+/* Serial (pl011) */
+#define UART_CLK (62500000)
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_PL011_SERIAL
+#define CONFIG_PL011_CLOCK UART_CLK
+#define CONFIG_PL01x_PORTS {(void *)(0x2a400000)}
+
+#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
+
+/* Support MTD */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_FLASH_BASE (0x08000000)
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
+
+#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + (512 * 1024))
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + PHYS_SDRAM_SIZE)
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {115200, 19200, 38400, 57600, 9600 }
+
+#define CONFIG_SYS_CBSIZE 1024
+#define CONFIG_SYS_MAXARGS 128
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* Since U-Boot 64bit PCIe support is limited, disable 64bit MMIO support */
+/* #define CONFIG_SYS_PCI_64BIT 1 */
+
+#define DEFAULT_DFU_ALT_INFO "dfu_alt_info=" \
+ "mtd nor1=u-boot.bin raw 200000 100000;" \
+ "fip.bin raw 180000 78000;" \
+ "optee.bin raw 500000 100000\0"
+
+/* Distro boot settings */
+#ifndef CONFIG_SPL_BUILD
+#ifdef CONFIG_CMD_USB
+#define BOOT_TARGET_DEVICE_USB(func) func(USB, usb, 0)
+#else
+#define BOOT_TARGET_DEVICE_USB(func)
+#endif
+
+#ifdef CONFIG_CMD_MMC
+#define BOOT_TARGET_DEVICE_MMC(func) func(MMC, mmc, 0)
+#else
+#define BOOT_TARGET_DEVICE_MMC(func)
+#endif
+
+#ifdef CONFIG_CMD_NVME
+#define BOOT_TARGET_DEVICE_NVME(func) func(NVME, nvme, 0)
+#else
+#define BOOT_TARGET_DEVICE_NVME(func)
+#endif
+
+#ifdef CONFIG_CMD_SCSI
+#define BOOT_TARGET_DEVICE_SCSI(func) func(SCSI, scsi, 0) func(SCSI, scsi, 1)
+#else
+#define BOOT_TARGET_DEVICE_SCSI(func)
+#endif
+
+#define BOOT_TARGET_DEVICES(func) \
+ BOOT_TARGET_DEVICE_USB(func) \
+ BOOT_TARGET_DEVICE_MMC(func) \
+ BOOT_TARGET_DEVICE_SCSI(func) \
+ BOOT_TARGET_DEVICE_NVME(func) \
+
+#include <config_distro_bootcmd.h>
+#else /* CONFIG_SPL_BUILD */
+#define BOOTENV
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "fdt_addr_r=0x9fe00000\0" \
+ "kernel_addr_r=0x90000000\0" \
+ "ramdisk_addr_r=0xa0000000\0" \
+ "scriptaddr=0x88000000\0" \
+ "pxefile_addr_r=0x88100000\0" \
+ DEFAULT_DFU_ALT_INFO \
+ BOOTENV
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h
index 7874b77f3f8..d498c8f3bc6 100644
--- a/include/configs/work_92105.h
+++ b/include/configs/work_92105.h
@@ -36,11 +36,6 @@
- GENERATED_GBL_DATA_SIZE)
/*
- * Serial Driver
- */
-#define CONFIG_SYS_LPC32XX_UART 5 /* UART5 - NS16550 */
-
-/*
* Ethernet Driver
*/
@@ -52,7 +47,6 @@
* I2C driver
*/
-#define CONFIG_SYS_I2C_LPC32XX
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_SPEED 350000
generated by cgit v1.2.3 (git 2.0.4) at 2025-07-24 07:54:15 +0000