diff options
Diffstat (limited to 'include/configs')
158 files changed, 194 insertions, 485 deletions
diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h index 49ed668f17c..f214dc90bc7 100644 --- a/include/configs/M5249EVB.h +++ b/include/configs/M5249EVB.h @@ -36,7 +36,6 @@ */ #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ #define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index b37601c794b..3a8c074dc55 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -18,8 +18,6 @@ #define CONFIG_PCI1 /* PCI controller 1 */ #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ #undef CONFIG_PCI2 -#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ -#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ #define CONFIG_ENV_OVERWRITE @@ -289,7 +287,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ /* Serial Port */ @@ -343,24 +341,18 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ #ifdef CONFIG_PCIE1 -#define CONFIG_SYS_PCIE1_NAME "Slot" #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull #else -#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 #endif -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_IO_PHYS 0xfe3000000ull #else #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 #endif -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ #endif /* @@ -386,6 +378,20 @@ extern unsigned long get_clock_freq(void); #undef CONFIG_EEPRO100 #undef CONFIG_TULIP +#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ +#define CONFIG_PCI_INDIRECT_BRIDGE 1 +#define CONFIG_SYS_PCIE1_NAME "Slot" +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#else +#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 +#endif +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ +#endif + #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif /* CONFIG_PCI */ diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index e196f3ce33a..f8cfef7b2d7 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -37,7 +37,6 @@ #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE3 /* PCIE controller 3 */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ #define CONFIG_SYS_SRIO @@ -354,60 +353,21 @@ unsigned long get_board_sys_clk(unsigned long dummy); /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#else -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 -#endif -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull -#else -#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 -#endif -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ /* controller 2, Slot 2, tgtid 2, Base address 201000 */ #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull -#else -#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 -#endif -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull -#else -#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 -#endif -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull -#else -#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 -#endif -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull -#else -#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 -#endif -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ /* Qman/Bman */ #define CONFIG_SYS_BMAN_NUM_PORTALS 10 @@ -483,7 +443,22 @@ unsigned long get_board_sys_clk(unsigned long dummy); #endif #ifdef CONFIG_PCI +#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ +#endif #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif /* CONFIG_PCI */ diff --git a/include/configs/SBx81LIFKW.h b/include/configs/SBx81LIFKW.h index 1539e8fabb5..f24cd23af22 100644 --- a/include/configs/SBx81LIFKW.h +++ b/include/configs/SBx81LIFKW.h @@ -83,7 +83,6 @@ /* * Other required minimal configurations */ -#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ #define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */ #define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */ #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ diff --git a/include/configs/SBx81LIFXCAT.h b/include/configs/SBx81LIFXCAT.h index af191930527..b6023232627 100644 --- a/include/configs/SBx81LIFXCAT.h +++ b/include/configs/SBx81LIFXCAT.h @@ -83,7 +83,6 @@ /* * Other required minimal configurations */ -#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ #define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */ #define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */ #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 5ab51e32338..8c1434fb10e 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -494,96 +494,48 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE3 /* PCIE controller 3 */ -#ifdef CONFIG_ARCH_T1040 -#define CONFIG_PCIE4 /* PCIE controller 4 */ -#endif -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ -#define CONFIG_PCI_INDIRECT_BRIDGE #ifdef CONFIG_PCI /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #ifdef CONFIG_PCIE1 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#else -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 -#endif -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull -#else -#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 -#endif -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ #endif /* controller 2, Slot 2, tgtid 2, Base address 201000 */ #ifdef CONFIG_PCIE2 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull -#else -#define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 -#endif -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull -#else -#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 -#endif -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ #endif /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #ifdef CONFIG_PCIE3 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull -#else -#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 -#endif -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull -#else -#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 -#endif -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ #endif -/* controller 4, Base address 203000, to be removed */ -#ifdef CONFIG_PCIE4 -#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull -#else -#define CONFIG_SYS_PCIE4_MEM_BUS 0xb0000000 -#define CONFIG_SYS_PCIE4_MEM_PHYS 0xb0000000 -#endif -#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 -#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull -#else -#define CONFIG_SYS_PCIE4_IO_PHYS 0xf8030000 -#endif -#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ +#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_PCI_INDIRECT_BRIDGE #endif #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 56ddef07f5e..53ee1484d05 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -145,13 +145,11 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_PCI_INDIRECT_BRIDGE #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE3 /* PCIE controller 3 */ #define CONFIG_PCIE4 /* PCIE controller 4 */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ #define CONFIG_ENV_OVERWRITE @@ -524,51 +522,55 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #ifdef CONFIG_PCIE1 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ #endif /* controller 2, Slot 2, tgtid 2, Base address 201000 */ #ifdef CONFIG_PCIE2 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ #endif /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #ifdef CONFIG_PCIE3 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ #endif /* controller 4, Base address 203000 */ #ifdef CONFIG_PCIE4 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 -#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull -#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 -#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull -#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ #endif +#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_PCI_INDIRECT_BRIDGE +#endif #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif /* CONFIG_PCI */ diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index ab92ca3b686..3d95c4afa26 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -433,49 +433,51 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE3 /* PCIE controller 3 */ #define CONFIG_PCIE4 /* PCIE controller 4 */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ /* controller 2, Slot 2, tgtid 2, Base address 201000 */ #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ /* controller 4, Base address 203000 */ #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 -#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull -#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull -#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ #ifdef CONFIG_PCI +#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ #define CONFIG_PCI_INDIRECT_BRIDGE +#endif #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 0accdc61194..57d8d171a7d 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -61,7 +61,6 @@ #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE3 /* PCIE controller 3 */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ #define CONFIG_ENV_OVERWRITE @@ -176,44 +175,48 @@ /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ /* controller 2, Slot 2, tgtid 2, Base address 201000 */ #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ /* controller 4, Base address 203000 */ #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull -#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull -#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ #ifdef CONFIG_PCI +#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ #define CONFIG_PCI_INDIRECT_BRIDGE +#endif #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif /* CONFIG_PCI */ diff --git a/include/configs/advantech_dms-ba16.h b/include/configs/advantech_dms-ba16.h index a0373491627..12988598121 100644 --- a/include/configs/advantech_dms-ba16.h +++ b/include/configs/advantech_dms-ba16.h @@ -39,7 +39,6 @@ #define CONFIG_LBA48 /* MMC Configs */ -#define CONFIG_FSL_USDHC #define CONFIG_SYS_FSL_ESDHC_ADDR 0 /* USB Configs */ diff --git a/include/configs/alt.h b/include/configs/alt.h index eb7eb551aef..bb5267517cb 100644 --- a/include/configs/alt.h +++ b/include/configs/alt.h @@ -45,7 +45,6 @@ /* SPL support */ #define CONFIG_SPL_STACK 0xe6340000 #define CONFIG_SPL_MAX_SIZE 0x4000 -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000 #ifdef CONFIG_SPL_BUILD #define CONFIG_CONS_SCIF2 #define CONFIG_SH_SCIF_CLK_FREQ 65000000 diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 1885ac8e368..be571066f28 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -274,7 +274,6 @@ */ #if defined(CONFIG_SPI_BOOT) /* SPL related */ -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT #define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */ diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index 63489133a88..3e5f0b1992f 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -26,8 +26,11 @@ * Enable CONFIG_USB_MUSB_HOST for Host functionalities MSC, keyboard * Enable CONFIG_USB_MUSB_GADGET for Device functionalities. */ - +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_USB_EHCI_OMAP +#else #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 57 +#endif /* I2C */ diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index b0d95599629..d355b80c2f5 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -8,7 +8,6 @@ #ifndef __CONFIG_AM43XX_EVM_H #define __CONFIG_AM43XX_EVM_H -#define CONFIG_ARCH_CPU_INIT #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 21) /* 2GB */ #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h index e181b30564c..531f79ee702 100644 --- a/include/configs/am57xx_evm.h +++ b/include/configs/am57xx_evm.h @@ -90,6 +90,5 @@ #define CONFIG_SYS_SPI_ARGS_SIZE 0x80000 /* SPI SPL */ -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 #endif /* __CONFIG_AM57XX_EVM_H */ diff --git a/include/configs/amcore.h b/include/configs/amcore.h index 4daa0bafe8c..26d6fef290b 100644 --- a/include/configs/amcore.h +++ b/include/configs/amcore.h @@ -30,8 +30,6 @@ /* undef to save memory */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ - #define CONFIG_SYS_LOAD_ADDR 0x20000 /* default load address */ #define CONFIG_SYS_MEMTEST_START 0x0 diff --git a/include/configs/apalis-imx8.h b/include/configs/apalis-imx8.h index 32623c263a3..6eb8395162b 100644 --- a/include/configs/apalis-imx8.h +++ b/include/configs/apalis-imx8.h @@ -15,7 +15,6 @@ #undef CONFIG_BOOTM_NETBSD -#define CONFIG_FSL_USDHC #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define USDHC1_BASE_ADDR 0x5b010000 #define USDHC2_BASE_ADDR 0x5b020000 diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h index 974571df435..4eceb10e8fc 100644 --- a/include/configs/apalis_imx6.h +++ b/include/configs/apalis_imx6.h @@ -42,7 +42,6 @@ #define CONFIG_SYS_MXC_I2C3_SPEED 400000 /* MMC Configs */ -#define CONFIG_FSL_USDHC #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_FSL_USDHC_NUM 3 diff --git a/include/configs/armadillo-800eva.h b/include/configs/armadillo-800eva.h index 0d170ec9934..c3ccceedca9 100644 --- a/include/configs/armadillo-800eva.h +++ b/include/configs/armadillo-800eva.h @@ -14,7 +14,6 @@ #define BOARD_LATE_INIT -#define CONFIG_ARCH_CPU_INIT #define CONFIG_TMU_TIMER #define CONFIG_SYS_TIMER_COUNTS_DOWN #define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */ diff --git a/include/configs/at91-sama5_common.h b/include/configs/at91-sama5_common.h index 1b8373fbc64..7af6b8b8436 100644 --- a/include/configs/at91-sama5_common.h +++ b/include/configs/at91-sama5_common.h @@ -13,8 +13,6 @@ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ -#define CONFIG_ARCH_CPU_INIT - #ifndef CONFIG_SPL_BUILD #define CONFIG_SKIP_LOWLEVEL_INIT #endif diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index 95710fb4c8a..b283c9d8737 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -35,7 +35,6 @@ #endif /* Misc CPU related */ -#define CONFIG_ARCH_CPU_INIT #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index 6b1db9ff1e9..3e7adf63f30 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -20,8 +20,6 @@ #define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_ARCH_CPU_INIT - #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_INITRD_TAG 1 diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h index e9b97b6e97e..bc79e1739ba 100644 --- a/include/configs/at91sam9n12ek.h +++ b/include/configs/at91sam9n12ek.h @@ -151,11 +151,6 @@ #ifdef CONFIG_SD_BOOT #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" - -#elif CONFIG_SYS_USE_NANDFLASH -#elif CONFIG_SPI_BOOT -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8400 - #elif CONFIG_NAND_BOOT #define CONFIG_SPL_NAND_DRIVERS #define CONFIG_SPL_NAND_BASE diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h index 3e18716e20f..1c67be56b02 100644 --- a/include/configs/at91sam9rlek.h +++ b/include/configs/at91sam9rlek.h @@ -16,7 +16,6 @@ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* main clock xtal */ -#define CONFIG_ARCH_CPU_INIT #define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h index 9353de76f28..ad7d281dd63 100644 --- a/include/configs/at91sam9x5ek.h +++ b/include/configs/at91sam9x5ek.h @@ -124,10 +124,6 @@ #ifdef CONFIG_SD_BOOT #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" - -#elif CONFIG_SPI_BOOT -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8400 - #elif CONFIG_NAND_BOOT #define CONFIG_SPL_NAND_DRIVERS #define CONFIG_SPL_NAND_BASE diff --git a/include/configs/bav335x.h b/include/configs/bav335x.h index bfa9fc9a529..db21a473f14 100644 --- a/include/configs/bav335x.h +++ b/include/configs/bav335x.h @@ -443,7 +443,6 @@ DEFAULT_LINUX_BOOT_ENV \ */ #if defined(CONFIG_SPI_BOOT) /* SPL related */ -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT #define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */ diff --git a/include/configs/bcm23550_w1d.h b/include/configs/bcm23550_w1d.h index deafb7b702d..f59cd75d689 100644 --- a/include/configs/bcm23550_w1d.h +++ b/include/configs/bcm23550_w1d.h @@ -93,8 +93,6 @@ /* version string, parser, etc */ -#define CONFIG_MX_CYCLIC - /* Initial upstream - boot to cmd prompt only */ #define CONFIG_BOOTCOMMAND "" diff --git a/include/configs/bcm28155_ap.h b/include/configs/bcm28155_ap.h index 781689a9914..111858ffb04 100644 --- a/include/configs/bcm28155_ap.h +++ b/include/configs/bcm28155_ap.h @@ -92,8 +92,6 @@ /* version string, parser, etc */ -#define CONFIG_MX_CYCLIC - /* Initial upstream - boot to cmd prompt only */ #define CONFIG_BOOTCOMMAND "" diff --git a/include/configs/bcm_ep_board.h b/include/configs/bcm_ep_board.h index 09a5804e7a3..b67100aa3aa 100644 --- a/include/configs/bcm_ep_board.h +++ b/include/configs/bcm_ep_board.h @@ -51,8 +51,6 @@ /* version string, parser, etc */ -#define CONFIG_MX_CYCLIC - /* Enable Time Command */ #endif /* __BCM_EP_BOARD_H */ diff --git a/include/configs/brppt1.h b/include/configs/brppt1.h index 5a40f3abd12..bc0dabb51b5 100644 --- a/include/configs/brppt1.h +++ b/include/configs/brppt1.h @@ -181,7 +181,6 @@ NANDTGTS \ #if defined(CONFIG_SPI) /* SPI Flash */ -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 /* Environment */ #define CONFIG_SYS_REDUNDAND_ENVIRONMENT #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ diff --git a/include/configs/brsmarc1.h b/include/configs/brsmarc1.h index c18445816e5..c3eb5baacc4 100644 --- a/include/configs/brsmarc1.h +++ b/include/configs/brsmarc1.h @@ -72,7 +72,6 @@ BUR_COMMON_ENV \ #define CONFIG_INITRD_TAG /* SPI Flash */ -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 /* Environment */ #define CONFIG_SYS_REDUNDAND_ENVIRONMENT diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h index 07c6409e8fb..f109b22fdac 100644 --- a/include/configs/cgtqmx6eval.h +++ b/include/configs/cgtqmx6eval.h @@ -17,7 +17,6 @@ #define CONFIG_MACH_TYPE 4122 #ifdef CONFIG_SPL -#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024) #include "imx6_spl.h" #endif diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h index 4c93fc6cbea..7f3fdea039f 100644 --- a/include/configs/cl-som-imx7.h +++ b/include/configs/cl-som-imx7.h @@ -147,7 +147,6 @@ #define CONFIG_ENV_SECT_SIZE (64 * 1024) /* MMC Config*/ -#define CONFIG_FSL_USDHC #ifdef CONFIG_FSL_USDHC #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR @@ -166,8 +165,5 @@ /* SPL */ #include "imx7_spl.h" -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024) -#endif /* CONFIG_SPL_BUILD */ #endif /* __CONFIG_H */ diff --git a/include/configs/clearfog.h b/include/configs/clearfog.h index 15c402b542e..9d20a5e88c1 100644 --- a/include/configs/clearfog.h +++ b/include/configs/clearfog.h @@ -83,7 +83,6 @@ #if defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI) /* SPL related SPI defines */ -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS #elif defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC) || defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_SATA) /* SPL related MMC defines */ diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index 60bac9adc85..b957e9cba4b 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -207,7 +207,6 @@ /* SPL */ #include "imx6_spl.h" -#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024) /* Display */ #define CONFIG_IMX_HDMI diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h index b2c13004270..1314cf96a2d 100644 --- a/include/configs/cm_t43.h +++ b/include/configs/cm_t43.h @@ -9,7 +9,6 @@ #define __CONFIG_CM_T43_H #define CONFIG_CM_T43 -#define CONFIG_ARCH_CPU_INIT #define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2GB */ #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ @@ -115,7 +114,6 @@ /* SPL defines. */ #define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + (128 << 20)) -#define CONFIG_SYS_SPI_U_BOOT_OFFS (256 * 1024) #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* EEPROM */ diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h index 05af222a1fa..736717486bf 100644 --- a/include/configs/colibri-imx6ull.h +++ b/include/configs/colibri-imx6ull.h @@ -153,7 +153,6 @@ /* used to initialize CONFIG_SYS_NAND_BASE_LIST which is unused */ #define CONFIG_SYS_NAND_BASE -1 #define CONFIG_SYS_NAND_ONFI_DETECTION -#define CONFIG_SYS_NAND_USE_FLASH_BBT /* USB Configs */ #define CONFIG_EHCI_HCD_INIT_AFTER_RESET diff --git a/include/configs/colibri-imx8x.h b/include/configs/colibri-imx8x.h index 24690668490..6f3c34d1ad9 100644 --- a/include/configs/colibri-imx8x.h +++ b/include/configs/colibri-imx8x.h @@ -15,7 +15,6 @@ #undef CONFIG_BOOTM_NETBSD -#define CONFIG_FSL_USDHC #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define USDHC1_BASE_ADDR 0x5b010000 #define USDHC2_BASE_ADDR 0x5b020000 diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h index 147f8013534..aee9f2f1d07 100644 --- a/include/configs/colibri_imx6.h +++ b/include/configs/colibri_imx6.h @@ -40,7 +40,6 @@ #define CONFIG_SYS_MXC_I2C3_SPEED 400000 /* MMC Configs */ -#define CONFIG_FSL_USDHC #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_FSL_USDHC_NUM 2 diff --git a/include/configs/colibri_pxa270.h b/include/configs/colibri_pxa270.h index d4802f9914c..bc3d40e667c 100644 --- a/include/configs/colibri_pxa270.h +++ b/include/configs/colibri_pxa270.h @@ -21,7 +21,6 @@ */ #define CONFIG_ENV_OVERWRITE #define CONFIG_SYS_MALLOC_LEN (128 * 1024) -#define CONFIG_ARCH_CPU_INIT #define CONFIG_BOOTCOMMAND \ "if fatload mmc 0 0xa0000000 uImage; then " \ "bootm 0xa0000000; " \ diff --git a/include/configs/controlcenterdc.h b/include/configs/controlcenterdc.h index 54bbfe3f55b..f6d53284d7d 100644 --- a/include/configs/controlcenterdc.h +++ b/include/configs/controlcenterdc.h @@ -97,7 +97,6 @@ #if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH /* SPL related SPI defines */ -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x30000 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS #endif diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index e5c3a0c3f21..60e09c19399 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -54,7 +54,6 @@ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ #define CONFIG_ENV_OVERWRITE @@ -362,68 +361,25 @@ /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#else -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 -#endif -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull -#else -#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 -#endif -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ /* controller 2, Slot 2, tgtid 2, Base address 201000 */ #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull -#else -#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 -#endif -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull -#else -#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 -#endif -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull -#else -#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 -#endif -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull -#else -#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 -#endif -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ /* controller 4, Base address 203000 */ -#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull -#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull -#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ /* Qman/Bman */ #define CONFIG_SYS_BMAN_NUM_PORTALS 10 @@ -499,7 +455,26 @@ #endif #ifdef CONFIG_PCI +#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ +#endif #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif /* CONFIG_PCI */ diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index b87b6b208b3..41f0813a019 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -29,7 +29,6 @@ #define CONFIG_SKIP_LOWLEVEL_INIT_ONLY #ifdef CONFIG_DIRECT_NOR_BOOT -#define CONFIG_ARCH_CPU_INIT #define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11) #endif @@ -111,7 +110,6 @@ #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) #ifdef CONFIG_USE_SPIFLASH -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000 #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 #endif @@ -131,7 +129,6 @@ #define CONFIG_ENV_SIZE (128 << 10) #define CONFIG_ENV_SECT_SIZE (128 << 10) #endif -#define CONFIG_SYS_NAND_USE_FLASH_BBT #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST #define CONFIG_SYS_NAND_PAGE_2K #define CONFIG_SYS_NAND_CS 3 @@ -211,7 +208,6 @@ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) -#define CONFIG_MX_CYCLIC /* * Linux Information diff --git a/include/configs/dart_6ul.h b/include/configs/dart_6ul.h index fb1b899d712..4f99805ee26 100644 --- a/include/configs/dart_6ul.h +++ b/include/configs/dart_6ul.h @@ -55,7 +55,6 @@ #define CONFIG_MXC_UART_BASE UART1_BASE /* MMC Configs */ -#define CONFIG_FSL_USDHC #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR #define CONFIG_SUPPORT_EMMC_BOOT diff --git a/include/configs/db-88f6281-bp.h b/include/configs/db-88f6281-bp.h index 97af9a6258f..1b5541e49e3 100644 --- a/include/configs/db-88f6281-bp.h +++ b/include/configs/db-88f6281-bp.h @@ -72,7 +72,6 @@ /* * Other required minimal configurations */ -#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ #define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */ #define CONFIG_SYS_MEMTEST_END 0x007fffff /* (_8M - 1) */ #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ diff --git a/include/configs/db-88f6720.h b/include/configs/db-88f6720.h index a1780fa3da3..79b9ccfaa0b 100644 --- a/include/configs/db-88f6720.h +++ b/include/configs/db-88f6720.h @@ -73,7 +73,6 @@ #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) /* SPL related SPI defines */ -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS #endif /* _CONFIG_DB_88F6720_H */ diff --git a/include/configs/db-88f6820-amc.h b/include/configs/db-88f6820-amc.h index 5b59a92cb90..61b91dd91f0 100644 --- a/include/configs/db-88f6820-amc.h +++ b/include/configs/db-88f6820-amc.h @@ -32,7 +32,6 @@ #endif /* NAND */ -#define CONFIG_SYS_NAND_USE_FLASH_BBT #define CONFIG_SYS_NAND_ONFI_DETECTION /* Keep device tree and initrd in lower memory so the kernel can access them */ @@ -69,7 +68,6 @@ #if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH /* SPL related SPI defines */ -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS #endif diff --git a/include/configs/db-88f6820-gp.h b/include/configs/db-88f6820-gp.h index c98679e1095..900c9626790 100644 --- a/include/configs/db-88f6820-gp.h +++ b/include/configs/db-88f6820-gp.h @@ -85,7 +85,6 @@ #if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH /* SPL related SPI defines */ -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS #endif diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h index 6ed58ce91bb..907bd0d032f 100644 --- a/include/configs/db-mv784mp-gp.h +++ b/include/configs/db-mv784mp-gp.h @@ -46,7 +46,6 @@ #endif /* NAND */ -#define CONFIG_SYS_NAND_USE_FLASH_BBT #define CONFIG_SYS_NAND_ONFI_DETECTION /* @@ -83,7 +82,6 @@ #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) /* SPL related SPI defines */ -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ diff --git a/include/configs/db-xc3-24g4xg.h b/include/configs/db-xc3-24g4xg.h index 0f75ad71859..86d11e40b1d 100644 --- a/include/configs/db-xc3-24g4xg.h +++ b/include/configs/db-xc3-24g4xg.h @@ -22,7 +22,6 @@ #define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */ /* NAND */ -#define CONFIG_SYS_NAND_USE_FLASH_BBT #define CONFIG_SYS_NAND_ONFI_DETECTION /* Keep device tree and initrd in lower memory so the kernel can access them */ diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h index c93a5deb99b..16031c1da6b 100644 --- a/include/configs/devkit3250.h +++ b/include/configs/devkit3250.h @@ -98,7 +98,6 @@ #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 #define CONFIG_SYS_NAND_PAGE_SIZE NAND_LARGE_BLOCK_PAGE_SIZE -#define CONFIG_SYS_NAND_USE_FLASH_BBT /* * USB diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h index 7d2e5738467..c516e6ed4c2 100644 --- a/include/configs/dh_imx6.h +++ b/include/configs/dh_imx6.h @@ -23,7 +23,6 @@ /* SPL */ #include "imx6_spl.h" /* common IMX6 SPL configuration */ -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x11400 #define CONFIG_SPL_TARGET "u-boot-with-spl.imx" /* Miscellaneous configurable options */ @@ -49,7 +48,6 @@ #define CONFIG_ARP_TIMEOUT 200UL /* MMC Configs */ -#define CONFIG_FSL_USDHC #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_FSL_USDHC_NUM 3 #define CONFIG_SYS_MMC_ENV_DEV 2 /* 1 = SDHC3, 2 = SDHC4 (eMMC) */ diff --git a/include/configs/display5.h b/include/configs/display5.h index 1d3334ff12c..e503e4a0ce4 100644 --- a/include/configs/display5.h +++ b/include/configs/display5.h @@ -45,7 +45,6 @@ #define CONFIG_SYS_SPI_ARGS_SIZE 0x10000 #include "imx6_spl.h" -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS @@ -77,7 +76,6 @@ #endif /* MMC Configs */ -#define CONFIG_FSL_USDHC #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_FSL_USDHC_NUM 2 diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 7ec6e691c7d..3487b8ac1b3 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -92,7 +92,6 @@ #endif /* SPI SPL */ -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 /* USB xHCI HOST */ #define CONFIG_USB_XHCI_OMAP diff --git a/include/configs/ds414.h b/include/configs/ds414.h index b175e9d5745..552c7449d59 100644 --- a/include/configs/ds414.h +++ b/include/configs/ds414.h @@ -91,7 +91,6 @@ #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) /* SPL related SPI defines */ -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000 /* DS414 bus width is 32bits */ #define CONFIG_DDR_32BIT diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h index a608c0f0a56..f0717189446 100644 --- a/include/configs/edminiv2.h +++ b/include/configs/edminiv2.h @@ -183,7 +183,6 @@ /* * Other required minimal configurations */ -#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ #define CONFIG_SYS_LOAD_ADDR 0x00800000 #define CONFIG_SYS_MEMTEST_START 0x00400000 diff --git a/include/configs/el6x_common.h b/include/configs/el6x_common.h index bf70ea00295..fe28154dc19 100644 --- a/include/configs/el6x_common.h +++ b/include/configs/el6x_common.h @@ -20,7 +20,6 @@ #define CONFIG_MXC_UART #ifdef CONFIG_SPL -#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024) #include "imx6_spl.h" #endif diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h index 24aaae5640e..c9e7c8c0e2b 100644 --- a/include/configs/ethernut5.h +++ b/include/configs/ethernut5.h @@ -20,7 +20,6 @@ #define CONFIG_MACH_TYPE MACH_TYPE_ETHERNUT5 /* CPU information */ -#define CONFIG_ARCH_CPU_INIT /* ARM asynchronous clock */ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ diff --git a/include/configs/evb_rk3399.h b/include/configs/evb_rk3399.h index a99eeab4844..b9c4d683f47 100644 --- a/include/configs/evb_rk3399.h +++ b/include/configs/evb_rk3399.h @@ -8,7 +8,7 @@ #include <configs/rk3399_common.h> -#define CONFIG_SYS_MMC_ENV_DEV 1 +#define CONFIG_SYS_MMC_ENV_DEV 0 #define SDRAM_BANK_SIZE (2UL << 30) diff --git a/include/configs/exynos-common.h b/include/configs/exynos-common.h index 752acc58d07..5ae2b427cad 100644 --- a/include/configs/exynos-common.h +++ b/include/configs/exynos-common.h @@ -15,7 +15,6 @@ #include <asm/arch/cpu.h> /* get chip and board defs */ #include <linux/sizes.h> -#define CONFIG_ARCH_CPU_INIT #define CONFIG_SKIP_LOWLEVEL_INIT /* Keep L2 Cache Disabled */ diff --git a/include/configs/exynos7420-common.h b/include/configs/exynos7420-common.h index 2885cd70928..157260ca03b 100644 --- a/include/configs/exynos7420-common.h +++ b/include/configs/exynos7420-common.h @@ -16,8 +16,6 @@ #include <asm/arch/cpu.h> /* get chip and board defs */ #include <linux/sizes.h> -#define CONFIG_ARCH_CPU_INIT - /* Size of malloc() pool before and after relocation */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 << 20)) diff --git a/include/configs/fennec_rk3288.h b/include/configs/fennec_rk3288.h deleted file mode 100644 index ddd7012c8f3..00000000000 --- a/include/configs/fennec_rk3288.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define ROCKCHIP_DEVICE_SETTINGS -#include <configs/rk3288_common.h> - -#define CONFIG_SYS_MMC_ENV_DEV 0 - -#endif diff --git a/include/configs/gose.h b/include/configs/gose.h index 0de0a362e3e..fcb9f17750e 100644 --- a/include/configs/gose.h +++ b/include/configs/gose.h @@ -40,7 +40,6 @@ /* SPL support */ #define CONFIG_SPL_STACK 0xe6340000 #define CONFIG_SPL_MAX_SIZE 0x4000 -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000 #ifdef CONFIG_SPL_BUILD #define CONFIG_CONS_SCIF0 #define CONFIG_SH_SCIF_CLK_FREQ 65000000 diff --git a/include/configs/grpeach.h b/include/configs/grpeach.h index b7271ab1f6e..26ca6943b12 100644 --- a/include/configs/grpeach.h +++ b/include/configs/grpeach.h @@ -18,7 +18,6 @@ #define CONFIG_SYS_PBSIZE 256 #define CONFIG_SYS_ARM_CACHE_WRITETHROUGH #define CONFIG_CMDLINE_TAG -#define CONFIG_ARCH_CPU_INIT /* Internal RAM Size (RZ/A1=3M, RZ/A1M=5M, RZ/A1H=10M) */ #define CONFIG_SYS_SDRAM_BASE 0x20000000 diff --git a/include/configs/helios4.h b/include/configs/helios4.h index e03d8409ada..4df32002e09 100644 --- a/include/configs/helios4.h +++ b/include/configs/helios4.h @@ -104,7 +104,6 @@ #define CONFIG_SPL_SPI_FLASH_SUPPORT #define CONFIG_SPL_SPI_LOAD #define CONFIG_SPL_SPI_SUPPORT -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x30000 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS #endif diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h index dbf566522f3..d6b7477ee91 100644 --- a/include/configs/imx6_logic.h +++ b/include/configs/imx6_logic.h @@ -144,7 +144,6 @@ #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00500000 -#define CONFIG_SYS_NAND_USE_FLASH_BBT /* MTD device */ diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h index 16e4136fa9b..c2113439c30 100644 --- a/include/configs/imx8mq_evk.h +++ b/include/configs/imx8mq_evk.h @@ -216,7 +216,6 @@ #define CONFIG_IMX_BOOTAUX #define CONFIG_CMD_MMC -#define CONFIG_FSL_USDHC #define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 diff --git a/include/configs/imx8qm_mek.h b/include/configs/imx8qm_mek.h index 8fdf6775731..5a9fd57060b 100644 --- a/include/configs/imx8qm_mek.h +++ b/include/configs/imx8qm_mek.h @@ -47,7 +47,6 @@ #undef CONFIG_CMD_CRC32 #undef CONFIG_BOOTM_NETBSD -#define CONFIG_FSL_USDHC #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define USDHC1_BASE_ADDR 0x5B010000 #define USDHC2_BASE_ADDR 0x5B020000 diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h index c1f193487ea..02c4e9f8f67 100644 --- a/include/configs/imx8qxp_mek.h +++ b/include/configs/imx8qxp_mek.h @@ -46,7 +46,6 @@ #undef CONFIG_CMD_CRC32 #undef CONFIG_BOOTM_NETBSD -#define CONFIG_FSL_USDHC #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define USDHC1_BASE_ADDR 0x5B010000 #define USDHC2_BASE_ADDR 0x5B020000 diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h index f8d4d7bdf86..5fe77ef16dc 100644 --- a/include/configs/j721e_evm.h +++ b/include/configs/j721e_evm.h @@ -22,7 +22,6 @@ #ifdef CONFIG_TARGET_J721E_A72_EVM #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + \ CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE) -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x280000 #else /* * Maximum size in memory allocated to the SPL BSS. Keep it as tight as @@ -45,7 +44,6 @@ /* Configure R5 SPL post-relocation malloc pool in DDR */ #define CONFIG_SYS_SPL_MALLOC_START 0x84000000 #define CONFIG_SYS_SPL_MALLOC_SIZE SZ_16M -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x80000 #endif #ifdef CONFIG_SYS_K3_SPL_ATF diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h index d12d18770d7..829a5c78255 100644 --- a/include/configs/km/km_arm.h +++ b/include/configs/km/km_arm.h @@ -77,7 +77,6 @@ /* * Other required minimal configurations */ -#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ /* * Ethernet Driver configuration diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h index c42139dc3ad..140076a54e7 100644 --- a/include/configs/koelsch.h +++ b/include/configs/koelsch.h @@ -40,7 +40,6 @@ /* SPL support */ #define CONFIG_SPL_STACK 0xe6340000 #define CONFIG_SPL_MAX_SIZE 0x4000 -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000 #ifdef CONFIG_SPL_BUILD #define CONFIG_CONS_SCIF0 #define CONFIG_SH_SCIF_CLK_FREQ 65000000 diff --git a/include/configs/kp_imx6q_tpc.h b/include/configs/kp_imx6q_tpc.h index dbae2761213..2435ebbc7f0 100644 --- a/include/configs/kp_imx6q_tpc.h +++ b/include/configs/kp_imx6q_tpc.h @@ -39,7 +39,6 @@ #define CONFIG_SYS_I2C_SPEED 100000 /* MMC Configs */ -#define CONFIG_FSL_USDHC #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_SYS_MMC_ENV_DEV 1 /* 0 = SDHC2, 1 = SDHC4 (eMMC) */ diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h index a2c8224da7c..5a2b040225b 100644 --- a/include/configs/kzm9g.h +++ b/include/configs/kzm9g.h @@ -12,8 +12,6 @@ #include <asm/arch/rmobile.h> -#define CONFIG_ARCH_CPU_INIT - #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG diff --git a/include/configs/lager.h b/include/configs/lager.h index 5acd5a21184..db1dbc0ee88 100644 --- a/include/configs/lager.h +++ b/include/configs/lager.h @@ -41,7 +41,6 @@ /* SPL support */ #define CONFIG_SPL_STACK 0xe6340000 #define CONFIG_SPL_MAX_SIZE 0x4000 -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000 #ifdef CONFIG_SPL_BUILD #define CONFIG_CONS_SCIF0 #define CONFIG_SH_SCIF_CLK_FREQ 65000000 diff --git a/include/configs/legoev3.h b/include/configs/legoev3.h index c97e6a0ebb2..c1eeca0c60b 100644 --- a/include/configs/legoev3.h +++ b/include/configs/legoev3.h @@ -60,7 +60,6 @@ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) -#define CONFIG_MX_CYCLIC /* * Linux Information diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h index a6c7c3753d5..40fcd225829 100644 --- a/include/configs/ls1028a_common.h +++ b/include/configs/ls1028a_common.h @@ -42,7 +42,9 @@ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) /* I2C */ +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C +#endif /* Serial Port */ #define CONFIG_CONS_INDEX 1 diff --git a/include/configs/ls1028aqds.h b/include/configs/ls1028aqds.h index be018ef2be4..b0e9441a48b 100644 --- a/include/configs/ls1028aqds.h +++ b/include/configs/ls1028aqds.h @@ -16,7 +16,6 @@ #define CONFIG_DIMM_SLOTS_PER_CTLR 2 #define CONFIG_QIXIS_I2C_ACCESS -#define CONFIG_SYS_I2C_EARLY_INIT /* * QIXIS Definitions diff --git a/include/configs/ls1028ardb.h b/include/configs/ls1028ardb.h index 10791be8247..b77c36d2798 100644 --- a/include/configs/ls1028ardb.h +++ b/include/configs/ls1028ardb.h @@ -22,7 +22,6 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_QIXIS_I2C_ACCESS -#define CONFIG_SYS_I2C_EARLY_INIT /* * QIXIS Definitions diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index 0e4e370109f..0ea3ca03324 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -382,7 +382,6 @@ unsigned long get_board_ddr_clk(void); /* QSPI device */ #if defined(CONFIG_TFABOOT) || \ (defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)) -#define CONFIG_FSL_QSPI #ifdef CONFIG_FSL_QSPI #define CONFIG_SPI_FLASH_SPANSION #define FSL_QSPI_FLASH_SIZE (1 << 24) diff --git a/include/configs/ls1046afrwy.h b/include/configs/ls1046afrwy.h index 791bb8dc47f..8609ebfecc1 100644 --- a/include/configs/ls1046afrwy.h +++ b/include/configs/ls1046afrwy.h @@ -103,6 +103,9 @@ #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ #define CONFIG_ENV_OFFSET 0x500000 /* 5MB */ #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256KB */ +#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_FSL_QSPI_BASE + \ + CONFIG_ENV_OFFSET) /* FMan */ #ifdef CONFIG_SYS_DPAA_FMAN diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h index e8e1dc2d920..6f04dbaccde 100644 --- a/include/configs/ls1088a_common.h +++ b/include/configs/ls1088a_common.h @@ -67,7 +67,10 @@ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) /* I2C */ +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C +#endif + /* Serial Port */ #define CONFIG_SYS_NS16550_SERIAL diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h index 4387862582a..85e20617e6a 100644 --- a/include/configs/ls1088aqds.h +++ b/include/configs/ls1088aqds.h @@ -17,6 +17,8 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_TFABOOT #define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_MISC_INIT_R + #define CONFIG_ENV_SIZE 0x20000 #define CONFIG_ENV_OFFSET 0x500000 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \ @@ -46,7 +48,9 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_DDR_CLK_FREQ 100000000 #else #define CONFIG_QIXIS_I2C_ACCESS +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C_EARLY_INIT +#endif #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() #endif @@ -357,9 +361,7 @@ unsigned long get_board_ddr_clk(void); * RTC configuration */ #define RTC -#define CONFIG_RTC_PCF8563 1 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ -#define CONFIG_CMD_DATE /* EEPROM */ #define CONFIG_ID_EEPROM diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h index 322adb530a3..b71f70426cf 100644 --- a/include/configs/ls1088ardb.h +++ b/include/configs/ls1088ardb.h @@ -269,9 +269,7 @@ * RTC configuration */ #define RTC -#define CONFIG_RTC_PCF8563 1 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ -#define CONFIG_CMD_DATE #endif /* EEPROM */ diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index c7d8a3b6eb6..6be581a229c 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -75,7 +75,9 @@ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) /* I2C */ +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C +#endif /* Serial Port */ #define CONFIG_SYS_NS16550_SERIAL diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 18f30b585c4..e2a897557db 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -16,7 +16,9 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_FSL_QSPI #define CONFIG_QIXIS_I2C_ACCESS +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C_EARLY_INIT +#endif #define CONFIG_SYS_I2C_IFDR_DIV 0x7e #endif @@ -324,7 +326,9 @@ unsigned long get_board_ddr_clk(void); */ #define RTC #define CONFIG_RTC_DS3231 1 +#define CONFIG_RTC_ENABLE_32KHZ_OUTPUT #define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CONFIG_RTC_ENABLE_32KHZ_OUTPUT /* EEPROM */ #define CONFIG_ID_EEPROM diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index bfb54be79b9..2bf82176858 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -13,8 +13,10 @@ #ifdef CONFIG_TARGET_LS2081ARDB #define CONFIG_QIXIS_I2C_ACCESS #endif +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C_EARLY_INIT #endif +#endif #define I2C_MUX_CH_VOL_MONITOR 0xa #define I2C_VOL_MONITOR_ADDR 0x38 diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index a432259cfe3..49f11ea4b8d 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -70,7 +70,6 @@ #define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR #define CONFIG_SYS_NAND_LARGEPAGE #define CONFIG_MXC_NAND_HWECC -#define CONFIG_SYS_NAND_USE_FLASH_BBT /* Environment is in NAND */ #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE diff --git a/include/configs/maxbcm.h b/include/configs/maxbcm.h index a017d92cc9a..9d5fbcd516e 100644 --- a/include/configs/maxbcm.h +++ b/include/configs/maxbcm.h @@ -71,7 +71,6 @@ #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) /* SPL related SPI defines */ -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ #define CONFIG_DDR_FIXED_SIZE (1 << 20) /* 1GiB */ diff --git a/include/configs/meesc.h b/include/configs/meesc.h index aeab2e983be..3a173a2665a 100644 --- a/include/configs/meesc.h +++ b/include/configs/meesc.h @@ -33,7 +33,6 @@ /* Misc CPU related */ #define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_ARCH_CPU_INIT #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG #define CONFIG_SERIAL_TAG diff --git a/include/configs/mt7629.h b/include/configs/mt7629.h index 6e9b868aa49..741b6fbc1b1 100644 --- a/include/configs/mt7629.h +++ b/include/configs/mt7629.h @@ -38,7 +38,6 @@ #define CONFIG_SPL_PAD_TO 0x10000 #define CONFIG_SPI_ADDR 0x30000000 -#define CONFIG_SYS_SPI_U_BOOT_OFFS CONFIG_SPL_PAD_TO #define CONFIG_SYS_UBOOT_BASE (CONFIG_SPI_ADDR + CONFIG_SPL_PAD_TO) /* SPL -> Uboot */ diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h index e6d5c680d78..a041ddb79bb 100644 --- a/include/configs/mv-common.h +++ b/include/configs/mv-common.h @@ -58,7 +58,6 @@ /* * Other required minimal configurations */ -#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ #define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ #define CONFIG_SYS_MEMTEST_START 0x00800000 /* 8M */ #define CONFIG_SYS_MEMTEST_END 0x00ffffff /*(_16M -1) */ diff --git a/include/configs/mvebu_armada-37xx.h b/include/configs/mvebu_armada-37xx.h index ff8cc3c7707..bc249039c8e 100644 --- a/include/configs/mvebu_armada-37xx.h +++ b/include/configs/mvebu_armada-37xx.h @@ -37,7 +37,6 @@ /* * Other required minimal configurations */ -#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ #define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ #define CONFIG_SYS_MEMTEST_START 0x00800000 /* 8M */ #define CONFIG_SYS_MEMTEST_END 0x00ffffff /*(_16M -1) */ diff --git a/include/configs/mvebu_armada-8k.h b/include/configs/mvebu_armada-8k.h index f3f85385414..3be36833de0 100644 --- a/include/configs/mvebu_armada-8k.h +++ b/include/configs/mvebu_armada-8k.h @@ -38,7 +38,6 @@ /* * Other required minimal configurations */ -#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ #define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ #define CONFIG_SYS_MEMTEST_START 0x00800000 /* 8M */ #define CONFIG_SYS_MEMTEST_END 0x00ffffff /*(_16M -1) */ @@ -58,7 +57,6 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_MAX_CHIPS 1 #define CONFIG_SYS_NAND_ONFI_DETECTION -#define CONFIG_SYS_NAND_USE_FLASH_BBT /* * Ethernet Driver configuration diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h index 46ff99b4491..d25629f4155 100644 --- a/include/configs/mx53ard.h +++ b/include/configs/mx53ard.h @@ -28,7 +28,6 @@ #define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR #define CONFIG_SYS_NAND_LARGEPAGE #define CONFIG_MXC_NAND_HWECC -#define CONFIG_SYS_NAND_USE_FLASH_BBT #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART1_BASE diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index 2b8ce9d71d0..f6c0e21d072 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -55,7 +55,6 @@ #define CONFIG_SYS_MAXARGS 32 /* MMC */ -#define CONFIG_FSL_USDHC /* Secure boot (HAB) support */ #ifdef CONFIG_SECURE_BOOT diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h index 4f822ef9a07..70dda35eb06 100644 --- a/include/configs/mx7_common.h +++ b/include/configs/mx7_common.h @@ -40,7 +40,6 @@ #define CONFIG_MXC_UART /* MMC */ -#define CONFIG_FSL_USDHC #define CONFIG_ARMV7_SECURE_BASE 0x00900000 diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h index 2af5a4fe3e6..763a46b47fe 100644 --- a/include/configs/mx7ulp_evk.h +++ b/include/configs/mx7ulp_evk.h @@ -27,8 +27,6 @@ #define IRAM_BASE_ADDR OCRAM_0_BASE #define IOMUXC_BASE_ADDR IOMUXC1_RBASE -#define CONFIG_FSL_USDHC - #define CONFIG_SYS_FSL_USDHC_NUM 1 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 diff --git a/include/configs/mxs.h b/include/configs/mxs.h index cc5d4c85fe9..6cadd720d2b 100644 --- a/include/configs/mxs.h +++ b/include/configs/mxs.h @@ -94,12 +94,6 @@ /* * Drivers */ - -/* APBH DMA */ - -/* GPIO */ -#define CONFIG_MXS_GPIO - /* * DUART Serial Driver. * Conflicts with AUART driver which can be set by board. diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index b7c3ddf564d..90292ae3121 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -30,6 +30,9 @@ /* I2C */ #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C64 */ +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_USB_EHCI_OMAP +#endif #ifdef CONFIG_USB_EHCI_OMAP #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 4 #endif diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h index d4f404a78b5..cab402a484c 100644 --- a/include/configs/omapl138_lcdk.h +++ b/include/configs/omapl138_lcdk.h @@ -116,7 +116,6 @@ #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) #ifdef CONFIG_USE_SPIFLASH -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000 #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x30000 #endif @@ -133,7 +132,6 @@ #ifdef CONFIG_NAND #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ #define CONFIG_ENV_SIZE (128 << 9) -#define CONFIG_SYS_NAND_USE_FLASH_BBT #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST #define CONFIG_SYS_NAND_PAGE_2K #define CONFIG_SYS_NAND_CS 3 @@ -206,7 +204,6 @@ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) -#define CONFIG_MX_CYCLIC /* * USB Configs diff --git a/include/configs/ot1200.h b/include/configs/ot1200.h index 7dfcccb82bd..4efef892a84 100644 --- a/include/configs/ot1200.h +++ b/include/configs/ot1200.h @@ -59,7 +59,6 @@ /* SPL */ #ifdef CONFIG_SPL #include "imx6_spl.h" -#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024) #endif #define CONFIG_FEC_MXC diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index e07d2a178ff..1481d683e5c 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -207,8 +207,6 @@ #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ #define CONFIG_ENV_OVERWRITE @@ -572,44 +570,56 @@ */ /* controller 2, direct to uli, tgtid 2, Base address 9000 */ -#define CONFIG_SYS_PCIE2_NAME "PCIe SLOT" #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull #else -#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 #endif -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull #else #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 #endif -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ /* controller 1, Slot 2, tgtid 1, Base address a000 */ -#define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull #else -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 #endif -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull #else #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 #endif + +#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_PCI_INDIRECT_BRIDGE +#define CONFIG_SYS_PCIE2_NAME "PCIe SLOT" +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 +#else +#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 +#endif +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ + +#define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 +#else +#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 +#endif +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#endif #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif /* CONFIG_PCI */ diff --git a/include/configs/pcl063.h b/include/configs/pcl063.h index 8fef250ac47..943fca93776 100644 --- a/include/configs/pcl063.h +++ b/include/configs/pcl063.h @@ -31,7 +31,6 @@ #define CONFIG_MXC_UART_BASE UART1_BASE /* MMC Configs */ -#define CONFIG_FSL_USDHC #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR diff --git a/include/configs/pcl063_ull.h b/include/configs/pcl063_ull.h index 0f1a010b4e5..650caaa573e 100644 --- a/include/configs/pcl063_ull.h +++ b/include/configs/pcl063_ull.h @@ -37,7 +37,6 @@ #define CONFIG_MXC_UART_BASE UART1_BASE /* MMC Configs */ -#define CONFIG_FSL_USDHC #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR #define CONFIG_SUPPORT_EMMC_BOOT diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h index 153e567c2f9..fdbc07575cf 100644 --- a/include/configs/pcm051.h +++ b/include/configs/pcm051.h @@ -117,7 +117,6 @@ /* CPU */ #ifdef CONFIG_SPI_BOOT -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 #endif diff --git a/include/configs/pcm058.h b/include/configs/pcm058.h index b0415b28ade..855bc445fe1 100644 --- a/include/configs/pcm058.h +++ b/include/configs/pcm058.h @@ -8,7 +8,6 @@ #define __PCM058_CONFIG_H #ifdef CONFIG_SPL -#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024) #include "imx6_spl.h" #endif @@ -51,7 +50,6 @@ #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_ONFI_DETECTION -#define CONFIG_SYS_NAND_USE_FLASH_BBT #endif /* DMA stuff, needed for GPMI/MXS NAND support */ diff --git a/include/configs/pfla02.h b/include/configs/pfla02.h index 3a9b85acd8d..8731d89af2c 100644 --- a/include/configs/pfla02.h +++ b/include/configs/pfla02.h @@ -8,7 +8,6 @@ #define __PCM058_CONFIG_H #ifdef CONFIG_SPL -#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024) #include "imx6_spl.h" #endif diff --git a/include/configs/phycore_am335x_r2.h b/include/configs/phycore_am335x_r2.h index 78d265d1d2c..ca28b6ff1b3 100644 --- a/include/configs/phycore_am335x_r2.h +++ b/include/configs/phycore_am335x_r2.h @@ -119,7 +119,6 @@ /* CPU */ #ifdef CONFIG_SPI_BOOT -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 #elif defined(CONFIG_ENV_IS_IN_NAND) #define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h index c1ce12217aa..99ca1f730e6 100644 --- a/include/configs/pm9261.h +++ b/include/configs/pm9261.h @@ -26,7 +26,6 @@ #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 #define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9261" -#define CONFIG_ARCH_CPU_INIT #define CONFIG_MACH_TYPE MACH_TYPE_PM9261 diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h index b09d8515d3c..595acf1b943 100644 --- a/include/configs/pm9263.h +++ b/include/configs/pm9263.h @@ -26,7 +26,6 @@ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ #define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9263" -#define CONFIG_ARCH_CPU_INIT #define CONFIG_MACH_TYPE MACH_TYPE_PM9263 diff --git a/include/configs/porter.h b/include/configs/porter.h index 1db28869cd0..db42176d28e 100644 --- a/include/configs/porter.h +++ b/include/configs/porter.h @@ -45,7 +45,6 @@ /* SPL support */ #define CONFIG_SPL_STACK 0xe6340000 #define CONFIG_SPL_MAX_SIZE 0x4000 -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000 #ifdef CONFIG_SPL_BUILD #define CONFIG_CONS_SCIF0 #define CONFIG_SH_SCIF_CLK_FREQ 65000000 diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h index ecea1d47656..fa9b9af9346 100644 --- a/include/configs/qemu-riscv.h +++ b/include/configs/qemu-riscv.h @@ -8,6 +8,18 @@ #include <linux/sizes.h> +#ifdef CONFIG_SPL + +#define CONFIG_SPL_MAX_SIZE 0x00100000 +#define CONFIG_SPL_BSS_START_ADDR 0x84000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 +#define CONFIG_SYS_SPL_MALLOC_START 0x84100000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 + +#define CONFIG_SPL_LOAD_FIT_ADDRESS 0x80200000 + +#endif + #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) @@ -22,6 +34,7 @@ /* Environment options */ #define CONFIG_ENV_SIZE SZ_128K +#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(QEMU, qemu, na) \ func(VIRTIO, virtio, 0) \ @@ -47,5 +60,6 @@ "pxefile_addr_r=0x88200000\0" \ "ramdisk_addr_r=0x88300000\0" \ BOOTENV +#endif #endif /* __CONFIG_H */ diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h index 146a30b4c28..71a5909045b 100644 --- a/include/configs/rcar-gen2-common.h +++ b/include/configs/rcar-gen2-common.h @@ -18,8 +18,6 @@ #define CONFIG_SPL_TARGET "spl/u-boot-spl.srec" #endif -#define CONFIG_ARCH_CPU_INIT - #ifndef CONFIG_PINCTRL_PFC #define CONFIG_SH_GPIO_PFC #endif diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h index 11bf16b0549..95bd97c0ec3 100644 --- a/include/configs/rcar-gen3-common.h +++ b/include/configs/rcar-gen3-common.h @@ -23,8 +23,6 @@ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG -#define CONFIG_ARCH_CPU_INIT - /* Generic Interrupt Controller Definitions */ #define CONFIG_GICV2 #define GICD_BASE 0xF1010000 diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h index 66331a13766..7f148eff87e 100644 --- a/include/configs/rk3036_common.h +++ b/include/configs/rk3036_common.h @@ -8,7 +8,6 @@ #include <asm/arch-rockchip/hardware.h> #include "rockchip-common.h" -#define CONFIG_SYS_MALLOC_LEN (32 << 20) #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SKIP_LOWLEVEL_INIT diff --git a/include/configs/rk3128_common.h b/include/configs/rk3128_common.h index d12696d6b37..d0c9e5c809d 100644 --- a/include/configs/rk3128_common.h +++ b/include/configs/rk3128_common.h @@ -10,7 +10,6 @@ #define CONFIG_SYS_MAXARGS 16 #define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_MALLOC_LEN (32 << 20) #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SKIP_LOWLEVEL_INIT @@ -27,7 +26,6 @@ #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ /* RAW SD card / eMMC locations. */ -#define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10) #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SYS_SDRAM_BASE 0x60000000 diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h index 44e8d0ccd2b..3bcc04808a3 100644 --- a/include/configs/rk3188_common.h +++ b/include/configs/rk3188_common.h @@ -12,7 +12,6 @@ #include "rockchip-common.h" #define CONFIG_SKIP_LOWLEVEL_INIT_ONLY -#define CONFIG_SYS_MALLOC_LEN (32 << 20) #define CONFIG_SYS_CBSIZE 1024 #ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h index f2fb7e07b9b..7e0c831174a 100644 --- a/include/configs/rk322x_common.h +++ b/include/configs/rk322x_common.h @@ -9,7 +9,6 @@ #include "rockchip-common.h" #define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_MALLOC_LEN (32 << 20) #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index 84b474ac7bc..bcda769af55 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -12,7 +12,6 @@ #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* 16MB */ #define CONFIG_SKIP_LOWLEVEL_INIT_ONLY -#define CONFIG_SYS_MALLOC_LEN (32 << 20) #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_ROCKCHIP_STIMER_BASE 0xff810020 @@ -30,7 +29,6 @@ #define CONFIG_IRAM_BASE 0xff700000 /* RAW SD card / eMMC locations. */ -#define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10) /* FAT sd card locations. */ #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h index 6ed7525304c..3ff3331c808 100644 --- a/include/configs/rk3328_common.h +++ b/include/configs/rk3328_common.h @@ -12,7 +12,6 @@ #define CONFIG_ROCKCHIP_STIMER_BASE 0xff1d0020 -#define CONFIG_SYS_MALLOC_LEN (32 << 20) #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SKIP_LOWLEVEL_INIT @@ -25,8 +24,6 @@ #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ -#define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10) - /* FAT sd card locations. */ #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SYS_SDRAM_BASE 0 diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h index 340413dbbad..e4b2114a0dd 100644 --- a/include/configs/rk3368_common.h +++ b/include/configs/rk3368_common.h @@ -16,7 +16,6 @@ #define CONFIG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xff000000 #define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_MALLOC_LEN (32 << 20) #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SKIP_LOWLEVEL_INIT diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index 12ad60d4439..126c34763ea 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -8,7 +8,6 @@ #include "rockchip-common.h" -#define CONFIG_SYS_MALLOC_LEN (32 << 20) #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SKIP_LOWLEVEL_INIT @@ -39,7 +38,6 @@ #define CONFIG_ROCKCHIP_SDHCI_MAX_FREQ 200000000 /* RAW SD card / eMMC locations. */ -#define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10) /* FAT sd card locations. */ #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 diff --git a/include/configs/rpi.h b/include/configs/rpi.h index e706bea8cce..8473cecd943 100644 --- a/include/configs/rpi.h +++ b/include/configs/rpi.h @@ -14,7 +14,6 @@ #endif /* Architecture, CPU, etc.*/ -#define CONFIG_ARCH_CPU_INIT /* Use SoC timer for AArch32, but architected timer for AArch64 */ #ifndef CONFIG_ARM64 diff --git a/include/configs/rv1108_common.h b/include/configs/rv1108_common.h index 691aa51e987..758e85e89df 100644 --- a/include/configs/rv1108_common.h +++ b/include/configs/rv1108_common.h @@ -10,7 +10,6 @@ #define CONFIG_IRAM_BASE 0x10080000 -#define CONFIG_SYS_MALLOC_LEN (32 << 20) #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SKIP_LOWLEVEL_INIT diff --git a/include/configs/s32v234evb.h b/include/configs/s32v234evb.h index 216932046bc..cc6d9206373 100644 --- a/include/configs/s32v234evb.h +++ b/include/configs/s32v234evb.h @@ -65,7 +65,6 @@ #define CONFIG_ENV_OVERWRITE #define CONFIG_SYS_UART_PORT (1) -#define CONFIG_FSL_USDHC #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC_BASE_ADDR #define CONFIG_SYS_FSL_ESDHC_NUM 1 diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index ff634d91dd4..be6f011ab05 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -18,8 +18,6 @@ #include <linux/sizes.h> #include <asm/arch/cpu.h> /* get chip and board defs */ -#define CONFIG_ARCH_CPU_INIT - /* input clock of PLL: has 24MHz input clock at S5PC110 */ #define CONFIG_SYS_CLK_FREQ_C110 24000000 diff --git a/include/configs/sama5d27_som1_ek.h b/include/configs/sama5d27_som1_ek.h index 90846c4bfd4..9b33acd40d2 100644 --- a/include/configs/sama5d27_som1_ek.h +++ b/include/configs/sama5d27_som1_ek.h @@ -62,8 +62,4 @@ #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" #endif -#ifdef CONFIG_QSPI_BOOT -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000 -#endif - #endif diff --git a/include/configs/sama5d2_xplained.h b/include/configs/sama5d2_xplained.h index 3dea3591275..487339594ec 100644 --- a/include/configs/sama5d2_xplained.h +++ b/include/configs/sama5d2_xplained.h @@ -69,10 +69,6 @@ #ifdef CONFIG_SD_BOOT #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" - -#elif CONFIG_SPI_BOOT -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000 - #endif #endif diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h index db840e927e6..3a712b51bd1 100644 --- a/include/configs/sama5d3xek.h +++ b/include/configs/sama5d3xek.h @@ -83,10 +83,6 @@ #ifdef CONFIG_SD_BOOT #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" - -#elif CONFIG_SPI_BOOT -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000 - #elif CONFIG_NAND_BOOT #define CONFIG_SPL_NAND_DRIVERS #define CONFIG_SPL_NAND_BASE diff --git a/include/configs/sama5d4_xplained.h b/include/configs/sama5d4_xplained.h index 5e6f59f7560..17734128190 100644 --- a/include/configs/sama5d4_xplained.h +++ b/include/configs/sama5d4_xplained.h @@ -47,11 +47,6 @@ #ifdef CONFIG_SD_BOOT #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" - -#elif CONFIG_SYS_USE_NANDFLASH -#elif CONFIG_SPI_BOOT -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000 - #elif CONFIG_NAND_BOOT #define CONFIG_SPL_NAND_DRIVERS #define CONFIG_SPL_NAND_BASE diff --git a/include/configs/sama5d4ek.h b/include/configs/sama5d4ek.h index c1f22f70166..6cf07a11271 100644 --- a/include/configs/sama5d4ek.h +++ b/include/configs/sama5d4ek.h @@ -47,10 +47,6 @@ #ifdef CONFIG_SD_BOOT #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" - -#elif CONFIG_SPI_BOOT -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000 - #elif CONFIG_NAND_BOOT #define CONFIG_SPL_NAND_DRIVERS #define CONFIG_SPL_NAND_BASE diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index dd63adb6db7..ea6cc38fc13 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -94,8 +94,6 @@ #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 - #define CONFIG_SPL_NAND_BASE #define CONFIG_SPL_NAND_DRIVERS #define CONFIG_SPL_NAND_ECC diff --git a/include/configs/silk.h b/include/configs/silk.h index c42b57ab2a6..a78da46a17c 100644 --- a/include/configs/silk.h +++ b/include/configs/silk.h @@ -45,7 +45,6 @@ /* SPL support */ #define CONFIG_SPL_STACK 0xe6340000 #define CONFIG_SPL_MAX_SIZE 0x4000 -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000 #ifdef CONFIG_SPL_BUILD #define CONFIG_CONS_SCIF2 #define CONFIG_SH_SCIF_CLK_FREQ 65000000 diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h index b934ee70d5e..1d09792ce99 100644 --- a/include/configs/smdkc100.h +++ b/include/configs/smdkc100.h @@ -21,8 +21,6 @@ #include <asm/arch/cpu.h> /* get chip and board defs */ -#define CONFIG_ARCH_CPU_INIT - /* input clock of PLL: SMDKC100 has 12MHz input clock */ #define CONFIG_SYS_CLK_FREQ 12000000 diff --git a/include/configs/snapper9260.h b/include/configs/snapper9260.h index 7c2c5fb6ca6..b0408a55925 100644 --- a/include/configs/snapper9260.h +++ b/include/configs/snapper9260.h @@ -19,7 +19,6 @@ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* CPU */ -#define CONFIG_ARCH_CPU_INIT #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 36b0ed54596..b11fe021a72 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -213,13 +213,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #endif /* SPL QSPI boot support */ -#ifdef CONFIG_SPL_SPI_SUPPORT -#if defined(CONFIG_TARGET_SOCFPGA_GEN5) -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 -#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x100000 -#endif -#endif /* SPL NAND boot support */ #ifdef CONFIG_SPL_NAND_SUPPORT diff --git a/include/configs/socfpga_stratix10_socdk.h b/include/configs/socfpga_stratix10_socdk.h index 90ad8172e22..7b55dd14dab 100644 --- a/include/configs/socfpga_stratix10_socdk.h +++ b/include/configs/socfpga_stratix10_socdk.h @@ -201,7 +201,6 @@ unsigned int cm_get_l4_sys_free_clk_hz(void); #define CONFIG_SYS_SPL_MALLOC_SIZE (CONFIG_SYS_MALLOC_LEN) #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR \ - CONFIG_SYS_SPL_MALLOC_SIZE) -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x3C00000 /* SPL SDMMC boot support */ #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index ea5996fe1ee..d21ff977169 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -150,7 +150,6 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Miscellaneous configurable options */ -#define CONFIG_ARCH_CPU_INIT #define CONFIG_BOOT_PARAMS_ADDR 0x00000100 #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS diff --git a/include/configs/stm32mp1.h b/include/configs/stm32mp1.h index 24f7b9d463f..92660fe2a00 100644 --- a/include/configs/stm32mp1.h +++ b/include/configs/stm32mp1.h @@ -10,11 +10,6 @@ #include <linux/sizes.h> #include <asm/arch/stm32.h> -/* - * Number of clock ticks in 1 sec - */ -#define CONFIG_SYS_HZ 1000 - #ifndef CONFIG_STM32MP1_TRUSTED /* PSCI support */ #define CONFIG_ARMV7_PSCI_1_0 @@ -52,7 +47,6 @@ /* SPL support */ #ifdef CONFIG_SPL -/* BOOTROM load address */ /* SPL use DDR */ #define CONFIG_SPL_BSS_START_ADDR 0xC0200000 #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 @@ -85,7 +79,9 @@ #endif /* Dynamic MTD partition support */ +#if defined(CONFIG_STM32_QSPI) || defined(CONFIG_NAND_STM32_FMC2) #define CONFIG_SYS_MTDPARTS_RUNTIME +#endif /*****************************************************************************/ #ifdef CONFIG_DISTRO_DEFAULTS @@ -146,6 +142,7 @@ * and the ramdisk at the end. */ #define CONFIG_EXTRA_ENV_SETTINGS \ + "bootdelay=1\0" \ "kernel_addr_r=0xc2000000\0" \ "fdt_addr_r=0xc4000000\0" \ "scriptaddr=0xc4100000\0" \ @@ -154,7 +151,8 @@ "ramdisk_addr_r=0xc4400000\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ - "env_default=1\0" \ + "altbootcmd=run bootcmd\0" \ + "env_default=1\0" \ "env_check=if test $env_default -eq 1;"\ " then env set env_default 0;env save;fi\0" \ STM32MP_BOOTCMD \ diff --git a/include/configs/stout.h b/include/configs/stout.h index 4a465e01bd3..67345958be2 100644 --- a/include/configs/stout.h +++ b/include/configs/stout.h @@ -49,7 +49,6 @@ /* SPL support */ #define CONFIG_SPL_STACK 0xe6340000 #define CONFIG_SPL_MAX_SIZE 0x4000 -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000 #ifdef CONFIG_SPL_BUILD #define CONFIG_CONS_SCIFA0 #define CONFIG_SH_SCIF_CLK_FREQ 52000000 diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index d7133a73fc2..0ef289fd642 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -118,10 +118,6 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 8 #endif -#ifdef CONFIG_SPL_SPI_SUNXI -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000 -#endif - /* mmc config */ #ifdef CONFIG_MMC #define CONFIG_MMC_SUNXI_SLOT 0 diff --git a/include/configs/taurus.h b/include/configs/taurus.h index 36a41fff18a..fdd1c5224b7 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -33,7 +33,6 @@ #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* main clock xtal */ /* Misc CPU related */ -#define CONFIG_ARCH_CPU_INIT #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG @@ -103,7 +102,6 @@ #if defined(CONFIG_SPL_BUILD) /* SPL related */ -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 #endif /* load address */ diff --git a/include/configs/theadorable.h b/include/configs/theadorable.h index 3562a14261e..45cd7e2b83a 100644 --- a/include/configs/theadorable.h +++ b/include/configs/theadorable.h @@ -106,7 +106,6 @@ #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) /* SPL related SPI defines */ -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x1a000 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h index 90b424f4995..46b1b41ef9c 100644 --- a/include/configs/ti814x_evm.h +++ b/include/configs/ti814x_evm.h @@ -116,7 +116,6 @@ #define CONFIG_SYS_NS16550_COM1 0x48020000 /* Base EVM has UART0 */ /* CPU */ -#define CONFIG_ARCH_CPU_INIT #define CONFIG_ENV_OVERWRITE @@ -130,7 +129,6 @@ #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 /* diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h index 0b9930e884e..19e1e2249ed 100644 --- a/include/configs/ti_am335x_common.h +++ b/include/configs/ti_am335x_common.h @@ -11,7 +11,6 @@ #ifndef __CONFIG_TI_AM335X_COMMON_H__ #define __CONFIG_TI_AM335X_COMMON_H__ -#define CONFIG_ARCH_CPU_INIT #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index 03753c5b524..d7bb1efcbf5 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -15,7 +15,6 @@ #define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 2nd stage loader */ /* SoC Configuration */ -#define CONFIG_ARCH_CPU_INIT #define CONFIG_SPL_TARGET "u-boot-spi.gph" /* Memory Configuration */ @@ -44,7 +43,6 @@ CONFIG_SYS_SPL_MALLOC_SIZE + \ SPL_MALLOC_F_SIZE + \ KEYSTONE_SPL_STACK_SIZE - 4) -#define CONFIG_SYS_SPI_U_BOOT_OFFS CONFIG_SPL_PAD_TO /* SRAM scratch space entries */ #define SRAM_SCRATCH_SPACE_ADDR CONFIG_SPL_STACK + 0x8 @@ -154,7 +152,6 @@ #define CONFIG_SYS_NAND_MASK_CLE 0x4000 #define CONFIG_SYS_NAND_MASK_ALE 0x2000 #define CONFIG_SYS_NAND_CS 2 -#define CONFIG_SYS_NAND_USE_FLASH_BBT #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST #define CONFIG_SYS_NAND_LARGEPAGE @@ -175,7 +172,6 @@ DFU_ALT_INFO_MMC \ /* U-Boot general configuration */ -#define CONFIG_MX_CYCLIC #define CONFIG_TIMESTAMP /* EDMA3 */ diff --git a/include/configs/topic_miami.h b/include/configs/topic_miami.h index a915c326075..b98656dd4c1 100644 --- a/include/configs/topic_miami.h +++ b/include/configs/topic_miami.h @@ -22,8 +22,6 @@ /* SPL settings */ #undef CONFIG_SPL_ETH_SUPPORT -#undef CONFIG_SYS_SPI_U_BOOT_OFFS -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 #undef CONFIG_SPL_MAX_FOOTPRINT #define CONFIG_SPL_MAX_FOOTPRINT CONFIG_SYS_SPI_U_BOOT_OFFS #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" diff --git a/include/configs/turris_mox.h b/include/configs/turris_mox.h index 7d5f5fa409e..16a49c766f2 100644 --- a/include/configs/turris_mox.h +++ b/include/configs/turris_mox.h @@ -44,7 +44,6 @@ /* * Other required minimal configurations */ -#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ #define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ #define CONFIG_SYS_MEMTEST_START 0x00800000 /* 8M */ #define CONFIG_SYS_MEMTEST_END 0x00ffffff /*(_16M -1) */ diff --git a/include/configs/turris_omnia.h b/include/configs/turris_omnia.h index edd776ec706..abe1e99acda 100644 --- a/include/configs/turris_omnia.h +++ b/include/configs/turris_omnia.h @@ -50,7 +50,6 @@ #ifdef CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI /* SPL related SPI defines */ -# define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000 # define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS #endif diff --git a/include/configs/usb_a9263.h b/include/configs/usb_a9263.h index ee72354dd53..c0ba647d094 100644 --- a/include/configs/usb_a9263.h +++ b/include/configs/usb_a9263.h @@ -22,8 +22,6 @@ #define CONFIG_MACH_TYPE MACH_TYPE_USB_A9263 -#define CONFIG_ARCH_CPU_INIT - #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h index 89cd8b550ae..b2c14f9e10f 100644 --- a/include/configs/vexpress_aemv8a.h +++ b/include/configs/vexpress_aemv8a.h @@ -11,14 +11,12 @@ #ifndef CONFIG_SEMIHOSTING #error CONFIG_TARGET_VEXPRESS64_BASE_FVP requires CONFIG_SEMIHOSTING #endif -#define CONFIG_ARMV8_SWITCH_TO_EL1 #endif #define CONFIG_REMAKE_ELF /* Link Definitions */ -#if defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) || \ - defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM) +#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP /* ATF loads u-boot here for BASE_FVP model */ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000) #elif CONFIG_TARGET_VEXPRESS64_JUNO @@ -84,8 +82,7 @@ #define GICR_BASE (0x2f100000) #else -#if defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) || \ - defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM) +#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP #define GICD_BASE (0x2f000000) #define GICC_BASE (0x2c000000) #elif CONFIG_TARGET_VEXPRESS64_JUNO @@ -192,17 +189,6 @@ "booti $kernel_addr - $fdt_addr" -#elif CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM -#define CONFIG_EXTRA_ENV_SETTINGS \ - "kernel_addr=0x80080000\0" \ - "initrd_addr=0x84000000\0" \ - "fdt_addr=0x83000000\0" \ - "fdt_high=0xffffffffffffffff\0" \ - "initrd_high=0xffffffffffffffff\0" - -#define CONFIG_BOOTCOMMAND "booti $kernel_addr $initrd_addr $fdt_addr" - - #endif /* Monitor Command Prompt */ diff --git a/include/configs/wb50n.h b/include/configs/wb50n.h index 81d30a6114a..6e471f62e6b 100644 --- a/include/configs/wb50n.h +++ b/include/configs/wb50n.h @@ -12,8 +12,6 @@ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ -#define CONFIG_ARCH_CPU_INIT - #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG diff --git a/include/configs/x530.h b/include/configs/x530.h index 80ae15bd4e4..2269d1ed8cd 100644 --- a/include/configs/x530.h +++ b/include/configs/x530.h @@ -39,7 +39,6 @@ /* NAND */ #define CONFIG_SYS_NAND_ONFI_DETECTION -#define CONFIG_SYS_NAND_USE_FLASH_BBT #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define BBT_CUSTOM_SCAN @@ -74,7 +73,6 @@ #endif /* NAND */ -#define CONFIG_SYS_NAND_USE_FLASH_BBT #define CONFIG_SYS_NAND_ONFI_DETECTION #define CONFIG_CMD_UBI #define CONFIG_CMD_UBIFS @@ -89,7 +87,6 @@ /* * Other required minimal configurations */ -#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ #define CONFIG_SYS_ALT_MEMTEST @@ -120,8 +117,6 @@ #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) /* SPL related SPI defines */ -#define CONFIG_SPL_SPI_LOAD -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS #endif /* _CONFIG_X530_H */ diff --git a/include/configs/x600.h b/include/configs/x600.h index c893752dcdf..d4bbdcdb134 100644 --- a/include/configs/x600.h +++ b/include/configs/x600.h @@ -96,11 +96,9 @@ #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) /* Miscellaneous configurable options */ -#define CONFIG_ARCH_CPU_INIT #define CONFIG_BOOT_PARAMS_ADDR 0x00000100 #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */ #define CONFIG_SYS_MEMTEST_START 0x00800000 #define CONFIG_SYS_MEMTEST_END 0x04000000 diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index bbcb20737b0..a1c55a83069 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -217,8 +217,6 @@ # define CONFIG_SYS_SPI_KERNEL_OFFS 0x80000 # define CONFIG_SYS_SPI_ARGS_OFFS 0xa0000 # define CONFIG_SYS_SPI_ARGS_SIZE 0xa0000 - -# define CONFIG_SYS_SPI_U_BOOT_OFFS 0x170000 #endif /* u-boot is like dtb */ diff --git a/include/configs/xtfpga.h b/include/configs/xtfpga.h index b8de931d2c1..2f20273572d 100644 --- a/include/configs/xtfpga.h +++ b/include/configs/xtfpga.h @@ -119,8 +119,6 @@ /* U-Boot autoboot configuration */ /*==============================*/ -#define CONFIG_MX_CYCLIC - /*=========================================*/ /* FPGA Registers (board info and control) */ diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index bb6a835ece0..ae08ebf2afc 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -293,7 +293,6 @@ /* qspi mode is working fine */ #ifdef CONFIG_ZYNQ_QSPI -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x100000 #define CONFIG_SYS_SPI_ARGS_OFFS 0x200000 #define CONFIG_SYS_SPI_ARGS_SIZE 0x80000 #define CONFIG_SYS_SPI_KERNEL_OFFS (CONFIG_SYS_SPI_ARGS_OFFS + \ |