diff options
Diffstat (limited to 'include/dt-bindings/clock')
62 files changed, 399 insertions, 7905 deletions
diff --git a/include/dt-bindings/clock/actions,s700-cmu.h b/include/dt-bindings/clock/actions,s700-cmu.h deleted file mode 100644 index 3e194299672..00000000000 --- a/include/dt-bindings/clock/actions,s700-cmu.h +++ /dev/null @@ -1,118 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 - * - * Device Tree binding constants for Actions Semi S700 Clock Management Unit - * - * Copyright (c) 2014 Actions Semi Inc. - * Author: David Liu <liuwei@actions-semi.com> - * - * Author: Pathiban Nallathambi <pn@denx.de> - * Author: Saravanan Sekar <sravanhome@gmail.com> - */ - -#ifndef __DT_BINDINGS_CLOCK_S700_H -#define __DT_BINDINGS_CLOCK_S700_H - -#define CLK_NONE 0 - -/* pll clocks */ -#define CLK_CORE_PLL 1 -#define CLK_DEV_PLL 2 -#define CLK_DDR_PLL 3 -#define CLK_NAND_PLL 4 -#define CLK_DISPLAY_PLL 5 -#define CLK_TVOUT_PLL 6 -#define CLK_CVBS_PLL 7 -#define CLK_AUDIO_PLL 8 -#define CLK_ETHERNET_PLL 9 - -/* system clock */ -#define CLK_CPU 10 -#define CLK_DEV 11 -#define CLK_AHB 12 -#define CLK_APB 13 -#define CLK_DMAC 14 -#define CLK_NOC0_CLK_MUX 15 -#define CLK_NOC1_CLK_MUX 16 -#define CLK_HP_CLK_MUX 17 -#define CLK_HP_CLK_DIV 18 -#define CLK_NOC1_CLK_DIV 19 -#define CLK_NOC0 20 -#define CLK_NOC1 21 -#define CLK_SENOR_SRC 22 - -/* peripheral device clock */ -#define CLK_GPIO 23 -#define CLK_TIMER 24 -#define CLK_DSI 25 -#define CLK_CSI 26 -#define CLK_SI 27 -#define CLK_DE 28 -#define CLK_HDE 29 -#define CLK_VDE 30 -#define CLK_VCE 31 -#define CLK_NAND 32 -#define CLK_SD0 33 -#define CLK_SD1 34 -#define CLK_SD2 35 - -#define CLK_UART0 36 -#define CLK_UART1 37 -#define CLK_UART2 38 -#define CLK_UART3 39 -#define CLK_UART4 40 -#define CLK_UART5 41 -#define CLK_UART6 42 - -#define CLK_PWM0 43 -#define CLK_PWM1 44 -#define CLK_PWM2 45 -#define CLK_PWM3 46 -#define CLK_PWM4 47 -#define CLK_PWM5 48 -#define CLK_GPU3D 49 - -#define CLK_I2C0 50 -#define CLK_I2C1 51 -#define CLK_I2C2 52 -#define CLK_I2C3 53 - -#define CLK_SPI0 54 -#define CLK_SPI1 55 -#define CLK_SPI2 56 -#define CLK_SPI3 57 - -#define CLK_USB3_480MPLL0 58 -#define CLK_USB3_480MPHY0 59 -#define CLK_USB3_5GPHY 60 -#define CLK_USB3_CCE 61 -#define CLK_USB3_MAC 62 - -#define CLK_LCD 63 -#define CLK_HDMI_AUDIO 64 -#define CLK_I2SRX 65 -#define CLK_I2STX 66 - -#define CLK_SENSOR0 67 -#define CLK_SENSOR1 68 - -#define CLK_HDMI_DEV 69 - -#define CLK_ETHERNET 70 -#define CLK_RMII_REF 71 - -#define CLK_USB2H0_PLLEN 72 -#define CLK_USB2H0_PHY 73 -#define CLK_USB2H0_CCE 74 -#define CLK_USB2H1_PLLEN 75 -#define CLK_USB2H1_PHY 76 -#define CLK_USB2H1_CCE 77 - -#define CLK_TVOUT 78 - -#define CLK_THERMAL_SENSOR 79 - -#define CLK_IRC_SWITCH 80 -#define CLK_PCM1 81 -#define CLK_NR_CLKS (CLK_PCM1 + 1) - -#endif /* __DT_BINDINGS_CLOCK_S700_H */ diff --git a/include/dt-bindings/clock/actions,s900-cmu.h b/include/dt-bindings/clock/actions,s900-cmu.h deleted file mode 100644 index 7c1251565f4..00000000000 --- a/include/dt-bindings/clock/actions,s900-cmu.h +++ /dev/null @@ -1,129 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Device Tree binding constants for Actions Semi S900 Clock Management Unit -// -// Copyright (c) 2014 Actions Semi Inc. -// Copyright (c) 2018 Linaro Ltd. - -#ifndef __DT_BINDINGS_CLOCK_S900_CMU_H -#define __DT_BINDINGS_CLOCK_S900_CMU_H - -#define CLK_NONE 0 - -/* fixed rate clocks */ -#define CLK_LOSC 1 -#define CLK_HOSC 2 - -/* pll clocks */ -#define CLK_CORE_PLL 3 -#define CLK_DEV_PLL 4 -#define CLK_DDR_PLL 5 -#define CLK_NAND_PLL 6 -#define CLK_DISPLAY_PLL 7 -#define CLK_DSI_PLL 8 -#define CLK_ASSIST_PLL 9 -#define CLK_AUDIO_PLL 10 - -/* system clock */ -#define CLK_CPU 15 -#define CLK_DEV 16 -#define CLK_NOC 17 -#define CLK_NOC_MUX 18 -#define CLK_NOC_DIV 19 -#define CLK_AHB 20 -#define CLK_APB 21 -#define CLK_DMAC 22 - -/* peripheral device clock */ -#define CLK_GPIO 23 - -#define CLK_BISP 24 -#define CLK_CSI0 25 -#define CLK_CSI1 26 - -#define CLK_DE0 27 -#define CLK_DE1 28 -#define CLK_DE2 29 -#define CLK_DE3 30 -#define CLK_DSI 32 - -#define CLK_GPU 33 -#define CLK_GPU_CORE 34 -#define CLK_GPU_MEM 35 -#define CLK_GPU_SYS 36 - -#define CLK_HDE 37 -#define CLK_I2C0 38 -#define CLK_I2C1 39 -#define CLK_I2C2 40 -#define CLK_I2C3 41 -#define CLK_I2C4 42 -#define CLK_I2C5 43 -#define CLK_I2SRX 44 -#define CLK_I2STX 45 -#define CLK_IMX 46 -#define CLK_LCD 47 -#define CLK_NAND0 48 -#define CLK_NAND1 49 -#define CLK_PWM0 50 -#define CLK_PWM1 51 -#define CLK_PWM2 52 -#define CLK_PWM3 53 -#define CLK_PWM4 54 -#define CLK_PWM5 55 -#define CLK_SD0 56 -#define CLK_SD1 57 -#define CLK_SD2 58 -#define CLK_SD3 59 -#define CLK_SENSOR 60 -#define CLK_SPEED_SENSOR 61 -#define CLK_SPI0 62 -#define CLK_SPI1 63 -#define CLK_SPI2 64 -#define CLK_SPI3 65 -#define CLK_THERMAL_SENSOR 66 -#define CLK_UART0 67 -#define CLK_UART1 68 -#define CLK_UART2 69 -#define CLK_UART3 70 -#define CLK_UART4 71 -#define CLK_UART5 72 -#define CLK_UART6 73 -#define CLK_VCE 74 -#define CLK_VDE 75 - -#define CLK_USB3_480MPLL0 76 -#define CLK_USB3_480MPHY0 77 -#define CLK_USB3_5GPHY 78 -#define CLK_USB3_CCE 79 -#define CLK_USB3_MAC 80 - -#define CLK_TIMER 83 - -#define CLK_HDMI_AUDIO 84 - -#define CLK_24M 85 - -#define CLK_EDP 86 - -#define CLK_24M_EDP 87 -#define CLK_EDP_PLL 88 -#define CLK_EDP_LINK 89 - -#define CLK_USB2H0_PLLEN 90 -#define CLK_USB2H0_PHY 91 -#define CLK_USB2H0_CCE 92 -#define CLK_USB2H1_PLLEN 93 -#define CLK_USB2H1_PHY 94 -#define CLK_USB2H1_CCE 95 - -#define CLK_DDR0 96 -#define CLK_DDR1 97 -#define CLK_DMM 98 - -#define CLK_ETH_MAC 99 -#define CLK_RMII_REF 100 - -#define CLK_NR_CLKS (CLK_RMII_REF + 1) - -#endif /* __DT_BINDINGS_CLOCK_S900_CMU_H */ diff --git a/include/dt-bindings/clock/agilex-clock.h b/include/dt-bindings/clock/agilex-clock.h deleted file mode 100644 index f751aad4daf..00000000000 --- a/include/dt-bindings/clock/agilex-clock.h +++ /dev/null @@ -1,71 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2019, Intel Corporation - */ - -#ifndef __AGILEX_CLOCK_H -#define __AGILEX_CLOCK_H - -/* fixed rate clocks */ -#define AGILEX_OSC1 0 -#define AGILEX_CB_INTOSC_HS_DIV2_CLK 1 -#define AGILEX_CB_INTOSC_LS_CLK 2 -#define AGILEX_L4_SYS_FREE_CLK 3 -#define AGILEX_F2S_FREE_CLK 4 - -/* PLL clocks */ -#define AGILEX_MAIN_PLL_CLK 5 -#define AGILEX_MAIN_PLL_C0_CLK 6 -#define AGILEX_MAIN_PLL_C1_CLK 7 -#define AGILEX_MAIN_PLL_C2_CLK 8 -#define AGILEX_MAIN_PLL_C3_CLK 9 -#define AGILEX_PERIPH_PLL_CLK 10 -#define AGILEX_PERIPH_PLL_C0_CLK 11 -#define AGILEX_PERIPH_PLL_C1_CLK 12 -#define AGILEX_PERIPH_PLL_C2_CLK 13 -#define AGILEX_PERIPH_PLL_C3_CLK 14 -#define AGILEX_MPU_FREE_CLK 15 -#define AGILEX_MPU_CCU_CLK 16 -#define AGILEX_BOOT_CLK 17 - -/* fixed factor clocks */ -#define AGILEX_L3_MAIN_FREE_CLK 18 -#define AGILEX_NOC_FREE_CLK 19 -#define AGILEX_S2F_USR0_CLK 20 -#define AGILEX_NOC_CLK 21 -#define AGILEX_EMAC_A_FREE_CLK 22 -#define AGILEX_EMAC_B_FREE_CLK 23 -#define AGILEX_EMAC_PTP_FREE_CLK 24 -#define AGILEX_GPIO_DB_FREE_CLK 25 -#define AGILEX_SDMMC_FREE_CLK 26 -#define AGILEX_S2F_USER0_FREE_CLK 27 -#define AGILEX_S2F_USER1_FREE_CLK 28 -#define AGILEX_PSI_REF_FREE_CLK 29 - -/* Gate clocks */ -#define AGILEX_MPU_CLK 30 -#define AGILEX_MPU_PERIPH_CLK 31 -#define AGILEX_L4_MAIN_CLK 32 -#define AGILEX_L4_MP_CLK 33 -#define AGILEX_L4_SP_CLK 34 -#define AGILEX_CS_AT_CLK 35 -#define AGILEX_CS_TRACE_CLK 36 -#define AGILEX_CS_PDBG_CLK 37 -#define AGILEX_CS_TIMER_CLK 38 -#define AGILEX_S2F_USER0_CLK 39 -#define AGILEX_EMAC0_CLK 40 -#define AGILEX_EMAC1_CLK 41 -#define AGILEX_EMAC2_CLK 42 -#define AGILEX_EMAC_PTP_CLK 43 -#define AGILEX_GPIO_DB_CLK 44 -#define AGILEX_NAND_CLK 45 -#define AGILEX_PSI_REF_CLK 46 -#define AGILEX_S2F_USER1_CLK 47 -#define AGILEX_SDMMC_CLK 48 -#define AGILEX_SPI_M_CLK 49 -#define AGILEX_USB_CLK 50 -#define AGILEX_NAND_X_CLK 51 -#define AGILEX_NAND_ECC_CLK 52 -#define AGILEX_NUM_CLKS 53 - -#endif /* __AGILEX_CLOCK_H */ diff --git a/include/dt-bindings/clock/am3.h b/include/dt-bindings/clock/am3.h deleted file mode 100644 index 86a8806e214..00000000000 --- a/include/dt-bindings/clock/am3.h +++ /dev/null @@ -1,227 +0,0 @@ -/* - * Copyright 2017 Texas Instruments, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#ifndef __DT_BINDINGS_CLK_AM3_H -#define __DT_BINDINGS_CLK_AM3_H - -#define AM3_CLKCTRL_OFFSET 0x0 -#define AM3_CLKCTRL_INDEX(offset) ((offset) - AM3_CLKCTRL_OFFSET) - -/* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */ - -/* l4_per clocks */ -#define AM3_L4_PER_CLKCTRL_OFFSET 0x14 -#define AM3_L4_PER_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_PER_CLKCTRL_OFFSET) -#define AM3_CPGMAC0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x14) -#define AM3_LCDC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x18) -#define AM3_USB_OTG_HS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x1c) -#define AM3_TPTC0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x24) -#define AM3_EMIF_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x28) -#define AM3_OCMCRAM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x2c) -#define AM3_GPMC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x30) -#define AM3_MCASP0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x34) -#define AM3_UART6_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x38) -#define AM3_MMC1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x3c) -#define AM3_ELM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x40) -#define AM3_I2C3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x44) -#define AM3_I2C2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x48) -#define AM3_SPI0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x4c) -#define AM3_SPI1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x50) -#define AM3_L4_LS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x60) -#define AM3_MCASP1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x68) -#define AM3_UART2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x6c) -#define AM3_UART3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x70) -#define AM3_UART4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x74) -#define AM3_UART5_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x78) -#define AM3_TIMER7_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x7c) -#define AM3_TIMER2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x80) -#define AM3_TIMER3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x84) -#define AM3_TIMER4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x88) -#define AM3_RNG_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x90) -#define AM3_AES_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x94) -#define AM3_SHAM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xa0) -#define AM3_GPIO2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xac) -#define AM3_GPIO3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xb0) -#define AM3_GPIO4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xb4) -#define AM3_TPCC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xbc) -#define AM3_D_CAN0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xc0) -#define AM3_D_CAN1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xc4) -#define AM3_EPWMSS1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xcc) -#define AM3_EPWMSS0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xd4) -#define AM3_EPWMSS2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xd8) -#define AM3_L3_INSTR_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xdc) -#define AM3_L3_MAIN_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xe0) -#define AM3_PRUSS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xe8) -#define AM3_TIMER5_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xec) -#define AM3_TIMER6_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf0) -#define AM3_MMC2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf4) -#define AM3_MMC3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf8) -#define AM3_TPTC1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xfc) -#define AM3_TPTC2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x100) -#define AM3_SPINLOCK_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x10c) -#define AM3_MAILBOX_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x110) -#define AM3_L4_HS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x120) -#define AM3_OCPWP_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x130) -#define AM3_CLKDIV32K_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x14c) - -/* l4_wkup clocks */ -#define AM3_L4_WKUP_CLKCTRL_OFFSET 0x4 -#define AM3_L4_WKUP_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_WKUP_CLKCTRL_OFFSET) -#define AM3_CONTROL_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x4) -#define AM3_GPIO1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x8) -#define AM3_L4_WKUP_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc) -#define AM3_DEBUGSS_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x14) -#define AM3_WKUP_M3_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb0) -#define AM3_UART1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb4) -#define AM3_I2C1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb8) -#define AM3_ADC_TSC_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xbc) -#define AM3_SMARTREFLEX0_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc0) -#define AM3_TIMER1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc4) -#define AM3_SMARTREFLEX1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc8) -#define AM3_WD_TIMER2_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xd4) - -/* mpu clocks */ -#define AM3_MPU_CLKCTRL_OFFSET 0x4 -#define AM3_MPU_CLKCTRL_INDEX(offset) ((offset) - AM3_MPU_CLKCTRL_OFFSET) -#define AM3_MPU_CLKCTRL AM3_MPU_CLKCTRL_INDEX(0x4) - -/* l4_rtc clocks */ -#define AM3_RTC_CLKCTRL AM3_CLKCTRL_INDEX(0x0) - -/* gfx_l3 clocks */ -#define AM3_GFX_L3_CLKCTRL_OFFSET 0x4 -#define AM3_GFX_L3_CLKCTRL_INDEX(offset) ((offset) - AM3_GFX_L3_CLKCTRL_OFFSET) -#define AM3_GFX_CLKCTRL AM3_GFX_L3_CLKCTRL_INDEX(0x4) - -/* l4_cefuse clocks */ -#define AM3_L4_CEFUSE_CLKCTRL_OFFSET 0x20 -#define AM3_L4_CEFUSE_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_CEFUSE_CLKCTRL_OFFSET) -#define AM3_CEFUSE_CLKCTRL AM3_L4_CEFUSE_CLKCTRL_INDEX(0x20) - -/* XXX: Compatibility part end */ - -/* l4ls clocks */ -#define AM3_L4LS_CLKCTRL_OFFSET 0x38 -#define AM3_L4LS_CLKCTRL_INDEX(offset) ((offset) - AM3_L4LS_CLKCTRL_OFFSET) -#define AM3_L4LS_UART6_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x38) -#define AM3_L4LS_MMC1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x3c) -#define AM3_L4LS_ELM_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x40) -#define AM3_L4LS_I2C3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x44) -#define AM3_L4LS_I2C2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x48) -#define AM3_L4LS_SPI0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x4c) -#define AM3_L4LS_SPI1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x50) -#define AM3_L4LS_L4_LS_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x60) -#define AM3_L4LS_UART2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x6c) -#define AM3_L4LS_UART3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x70) -#define AM3_L4LS_UART4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x74) -#define AM3_L4LS_UART5_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x78) -#define AM3_L4LS_TIMER7_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x7c) -#define AM3_L4LS_TIMER2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x80) -#define AM3_L4LS_TIMER3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x84) -#define AM3_L4LS_TIMER4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x88) -#define AM3_L4LS_RNG_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x90) -#define AM3_L4LS_GPIO2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xac) -#define AM3_L4LS_GPIO3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xb0) -#define AM3_L4LS_GPIO4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xb4) -#define AM3_L4LS_D_CAN0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xc0) -#define AM3_L4LS_D_CAN1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xc4) -#define AM3_L4LS_EPWMSS1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xcc) -#define AM3_L4LS_EPWMSS0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xd4) -#define AM3_L4LS_EPWMSS2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xd8) -#define AM3_L4LS_TIMER5_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xec) -#define AM3_L4LS_TIMER6_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xf0) -#define AM3_L4LS_MMC2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xf4) -#define AM3_L4LS_SPINLOCK_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x10c) -#define AM3_L4LS_MAILBOX_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x110) -#define AM3_L4LS_OCPWP_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x130) - -/* l3s clocks */ -#define AM3_L3S_CLKCTRL_OFFSET 0x1c -#define AM3_L3S_CLKCTRL_INDEX(offset) ((offset) - AM3_L3S_CLKCTRL_OFFSET) -#define AM3_L3S_USB_OTG_HS_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x1c) -#define AM3_L3S_GPMC_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x30) -#define AM3_L3S_MCASP0_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x34) -#define AM3_L3S_MCASP1_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x68) -#define AM3_L3S_MMC3_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0xf8) - -/* l3 clocks */ -#define AM3_L3_CLKCTRL_OFFSET 0x24 -#define AM3_L3_CLKCTRL_INDEX(offset) ((offset) - AM3_L3_CLKCTRL_OFFSET) -#define AM3_L3_TPTC0_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x24) -#define AM3_L3_EMIF_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x28) -#define AM3_L3_OCMCRAM_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x2c) -#define AM3_L3_AES_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x94) -#define AM3_L3_SHAM_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xa0) -#define AM3_L3_TPCC_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xbc) -#define AM3_L3_L3_INSTR_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xdc) -#define AM3_L3_L3_MAIN_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xe0) -#define AM3_L3_TPTC1_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xfc) -#define AM3_L3_TPTC2_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x100) - -/* l4hs clocks */ -#define AM3_L4HS_CLKCTRL_OFFSET 0x120 -#define AM3_L4HS_CLKCTRL_INDEX(offset) ((offset) - AM3_L4HS_CLKCTRL_OFFSET) -#define AM3_L4HS_L4_HS_CLKCTRL AM3_L4HS_CLKCTRL_INDEX(0x120) - -/* pruss_ocp clocks */ -#define AM3_PRUSS_OCP_CLKCTRL_OFFSET 0xe8 -#define AM3_PRUSS_OCP_CLKCTRL_INDEX(offset) ((offset) - AM3_PRUSS_OCP_CLKCTRL_OFFSET) -#define AM3_PRUSS_OCP_PRUSS_CLKCTRL AM3_PRUSS_OCP_CLKCTRL_INDEX(0xe8) - -/* cpsw_125mhz clocks */ -#define AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL AM3_CLKCTRL_INDEX(0x14) - -/* lcdc clocks */ -#define AM3_LCDC_CLKCTRL_OFFSET 0x18 -#define AM3_LCDC_CLKCTRL_INDEX(offset) ((offset) - AM3_LCDC_CLKCTRL_OFFSET) -#define AM3_LCDC_LCDC_CLKCTRL AM3_LCDC_CLKCTRL_INDEX(0x18) - -/* clk_24mhz clocks */ -#define AM3_CLK_24MHZ_CLKCTRL_OFFSET 0x14c -#define AM3_CLK_24MHZ_CLKCTRL_INDEX(offset) ((offset) - AM3_CLK_24MHZ_CLKCTRL_OFFSET) -#define AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL AM3_CLK_24MHZ_CLKCTRL_INDEX(0x14c) - -/* l4_wkup clocks */ -#define AM3_L4_WKUP_CONTROL_CLKCTRL AM3_CLKCTRL_INDEX(0x4) -#define AM3_L4_WKUP_GPIO1_CLKCTRL AM3_CLKCTRL_INDEX(0x8) -#define AM3_L4_WKUP_L4_WKUP_CLKCTRL AM3_CLKCTRL_INDEX(0xc) -#define AM3_L4_WKUP_UART1_CLKCTRL AM3_CLKCTRL_INDEX(0xb4) -#define AM3_L4_WKUP_I2C1_CLKCTRL AM3_CLKCTRL_INDEX(0xb8) -#define AM3_L4_WKUP_ADC_TSC_CLKCTRL AM3_CLKCTRL_INDEX(0xbc) -#define AM3_L4_WKUP_SMARTREFLEX0_CLKCTRL AM3_CLKCTRL_INDEX(0xc0) -#define AM3_L4_WKUP_TIMER1_CLKCTRL AM3_CLKCTRL_INDEX(0xc4) -#define AM3_L4_WKUP_SMARTREFLEX1_CLKCTRL AM3_CLKCTRL_INDEX(0xc8) -#define AM3_L4_WKUP_WD_TIMER2_CLKCTRL AM3_CLKCTRL_INDEX(0xd4) - -/* l3_aon clocks */ -#define AM3_L3_AON_CLKCTRL_OFFSET 0x14 -#define AM3_L3_AON_CLKCTRL_INDEX(offset) ((offset) - AM3_L3_AON_CLKCTRL_OFFSET) -#define AM3_L3_AON_DEBUGSS_CLKCTRL AM3_L3_AON_CLKCTRL_INDEX(0x14) - -/* l4_wkup_aon clocks */ -#define AM3_L4_WKUP_AON_CLKCTRL_OFFSET 0xb0 -#define AM3_L4_WKUP_AON_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_WKUP_AON_CLKCTRL_OFFSET) -#define AM3_L4_WKUP_AON_WKUP_M3_CLKCTRL AM3_L4_WKUP_AON_CLKCTRL_INDEX(0xb0) - -/* mpu clocks */ -#define AM3_MPU_MPU_CLKCTRL AM3_CLKCTRL_INDEX(0x4) - -/* l4_rtc clocks */ -#define AM3_L4_RTC_RTC_CLKCTRL AM3_CLKCTRL_INDEX(0x0) - -/* gfx_l3 clocks */ -#define AM3_GFX_L3_GFX_CLKCTRL AM3_CLKCTRL_INDEX(0x4) - -/* l4_cefuse clocks */ -#define AM3_L4_CEFUSE_CEFUSE_CLKCTRL AM3_CLKCTRL_INDEX(0x20) - -#endif diff --git a/include/dt-bindings/clock/at91.h b/include/dt-bindings/clock/at91.h deleted file mode 100644 index ab3ee241d10..00000000000 --- a/include/dt-bindings/clock/at91.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This header provides constants for AT91 pmc status. - * - * The constants defined in this header are being used in dts. - * - * Licensed under GPLv2 or later. - */ - -#ifndef _DT_BINDINGS_CLK_AT91_H -#define _DT_BINDINGS_CLK_AT91_H - -#define AT91_PMC_MOSCS 0 /* MOSCS Flag */ -#define AT91_PMC_LOCKA 1 /* PLLA Lock */ -#define AT91_PMC_LOCKB 2 /* PLLB Lock */ -#define AT91_PMC_MCKRDY 3 /* Master Clock */ -#define AT91_PMC_LOCKU 6 /* UPLL Lock */ -#define AT91_PMC_PCKRDY(id) (8 + (id)) /* Programmable Clock */ -#define AT91_PMC_MOSCSELS 16 /* Main Oscillator Selection */ -#define AT91_PMC_MOSCRCS 17 /* Main On-Chip RC */ -#define AT91_PMC_CFDEV 18 /* Clock Failure Detector Event */ -#define AT91_PMC_GCKRDY 24 /* Generated Clocks */ - -#endif diff --git a/include/dt-bindings/clock/bcm-nsp.h b/include/dt-bindings/clock/bcm-nsp.h deleted file mode 100644 index ad5827cde78..00000000000 --- a/include/dt-bindings/clock/bcm-nsp.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2015 Broadcom Corporation. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _CLOCK_BCM_NSP_H -#define _CLOCK_BCM_NSP_H - -/* GENPLL clock channel ID */ -#define BCM_NSP_GENPLL 0 -#define BCM_NSP_GENPLL_PHY_CLK 1 -#define BCM_NSP_GENPLL_ENET_SW_CLK 2 -#define BCM_NSP_GENPLL_USB_PHY_REF_CLK 3 -#define BCM_NSP_GENPLL_IPROCFAST_CLK 4 -#define BCM_NSP_GENPLL_SATA1_CLK 5 -#define BCM_NSP_GENPLL_SATA2_CLK 6 - -/* LCPLL0 clock channel ID */ -#define BCM_NSP_LCPLL0 0 -#define BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK 1 -#define BCM_NSP_LCPLL0_SDIO_CLK 2 -#define BCM_NSP_LCPLL0_DDR_PHY_CLK 3 - -#endif /* _CLOCK_BCM_NSP_H */ diff --git a/include/dt-bindings/clock/bcm2835-aux.h b/include/dt-bindings/clock/bcm2835-aux.h deleted file mode 100644 index bb79de383a3..00000000000 --- a/include/dt-bindings/clock/bcm2835-aux.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2015 Broadcom Corporation - */ - -#define BCM2835_AUX_CLOCK_UART 0 -#define BCM2835_AUX_CLOCK_SPI1 1 -#define BCM2835_AUX_CLOCK_SPI2 2 -#define BCM2835_AUX_CLOCK_COUNT 3 diff --git a/include/dt-bindings/clock/bcm2835.h b/include/dt-bindings/clock/bcm2835.h deleted file mode 100644 index b60c03430cf..00000000000 --- a/include/dt-bindings/clock/bcm2835.h +++ /dev/null @@ -1,62 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2015 Broadcom Corporation - */ - -#define BCM2835_PLLA 0 -#define BCM2835_PLLB 1 -#define BCM2835_PLLC 2 -#define BCM2835_PLLD 3 -#define BCM2835_PLLH 4 - -#define BCM2835_PLLA_CORE 5 -#define BCM2835_PLLA_PER 6 -#define BCM2835_PLLB_ARM 7 -#define BCM2835_PLLC_CORE0 8 -#define BCM2835_PLLC_CORE1 9 -#define BCM2835_PLLC_CORE2 10 -#define BCM2835_PLLC_PER 11 -#define BCM2835_PLLD_CORE 12 -#define BCM2835_PLLD_PER 13 -#define BCM2835_PLLH_RCAL 14 -#define BCM2835_PLLH_AUX 15 -#define BCM2835_PLLH_PIX 16 - -#define BCM2835_CLOCK_TIMER 17 -#define BCM2835_CLOCK_OTP 18 -#define BCM2835_CLOCK_UART 19 -#define BCM2835_CLOCK_VPU 20 -#define BCM2835_CLOCK_V3D 21 -#define BCM2835_CLOCK_ISP 22 -#define BCM2835_CLOCK_H264 23 -#define BCM2835_CLOCK_VEC 24 -#define BCM2835_CLOCK_HSM 25 -#define BCM2835_CLOCK_SDRAM 26 -#define BCM2835_CLOCK_TSENS 27 -#define BCM2835_CLOCK_EMMC 28 -#define BCM2835_CLOCK_PERI_IMAGE 29 -#define BCM2835_CLOCK_PWM 30 -#define BCM2835_CLOCK_PCM 31 - -#define BCM2835_PLLA_DSI0 32 -#define BCM2835_PLLA_CCP2 33 -#define BCM2835_PLLD_DSI0 34 -#define BCM2835_PLLD_DSI1 35 - -#define BCM2835_CLOCK_AVEO 36 -#define BCM2835_CLOCK_DFT 37 -#define BCM2835_CLOCK_GP0 38 -#define BCM2835_CLOCK_GP1 39 -#define BCM2835_CLOCK_GP2 40 -#define BCM2835_CLOCK_SLIM 41 -#define BCM2835_CLOCK_SMI 42 -#define BCM2835_CLOCK_TEC 43 -#define BCM2835_CLOCK_DPI 44 -#define BCM2835_CLOCK_CAM0 45 -#define BCM2835_CLOCK_CAM1 46 -#define BCM2835_CLOCK_DSI0E 47 -#define BCM2835_CLOCK_DSI1E 48 -#define BCM2835_CLOCK_DSI0P 49 -#define BCM2835_CLOCK_DSI1P 50 - -#define BCM2711_CLOCK_EMMC2 51 diff --git a/include/dt-bindings/clock/bcm6328-clock.h b/include/dt-bindings/clock/bcm6328-clock.h deleted file mode 100644 index 6f1e018a74b..00000000000 --- a/include/dt-bindings/clock/bcm6328-clock.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com> - * - * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h - */ - -#ifndef __DT_BINDINGS_CLOCK_BCM6328_H -#define __DT_BINDINGS_CLOCK_BCM6328_H - -#define BCM6328_CLK_PHYMIPS 0 -#define BCM6328_CLK_ADSL_QPROC 1 -#define BCM6328_CLK_ADSL_AFE 2 -#define BCM6328_CLK_ADSL 3 -#define BCM6328_CLK_MIPS 4 -#define BCM6328_CLK_SAR 5 -#define BCM6328_CLK_PCM 6 -#define BCM6328_CLK_USBD 7 -#define BCM6328_CLK_USBH 8 -#define BCM6328_CLK_HSSPI 9 -#define BCM6328_CLK_PCIE 10 -#define BCM6328_CLK_ROBOSW 11 - -#endif /* __DT_BINDINGS_CLOCK_BCM6328_H */ diff --git a/include/dt-bindings/clock/bcm6358-clock.h b/include/dt-bindings/clock/bcm6358-clock.h deleted file mode 100644 index a7529bcc030..00000000000 --- a/include/dt-bindings/clock/bcm6358-clock.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com> - * - * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h - */ - -#ifndef __DT_BINDINGS_CLOCK_BCM6358_H -#define __DT_BINDINGS_CLOCK_BCM6358_H - -#define BCM6358_CLK_ENET 4 -#define BCM6358_CLK_ADSL 5 -#define BCM6358_CLK_PCM 8 -#define BCM6358_CLK_SPI 9 -#define BCM6358_CLK_USBS 10 -#define BCM6358_CLK_SAR 11 -#define BCM6358_CLK_EMUSB 17 -#define BCM6358_CLK_ENET0 18 -#define BCM6358_CLK_ENET1 19 -#define BCM6358_CLK_USBSU 20 -#define BCM6358_CLK_EPHY 21 - -#endif /* __DT_BINDINGS_CLOCK_BCM6358_H */ diff --git a/include/dt-bindings/clock/bcm6362-clock.h b/include/dt-bindings/clock/bcm6362-clock.h deleted file mode 100644 index d3770c50490..00000000000 --- a/include/dt-bindings/clock/bcm6362-clock.h +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com> - * - * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h - */ - -#ifndef __DT_BINDINGS_CLOCK_BCM6362_H -#define __DT_BINDINGS_CLOCK_BCM6362_H - -#define BCM6362_CLK_GLESS 0 -#define BCM6362_CLK_ADSL_QPROC 1 -#define BCM6362_CLK_ADSL_AFE 2 -#define BCM6362_CLK_ADSL 3 -#define BCM6362_CLK_MIPS 4 -#define BCM6362_CLK_WLAN_OCP 5 -#define BCM6362_CLK_SWPKT_USB 7 -#define BCM6362_CLK_SWPKT_SAR 8 -#define BCM6362_CLK_SAR 9 -#define BCM6362_CLK_ROBOSW 10 -#define BCM6362_CLK_PCM 11 -#define BCM6362_CLK_USBD 12 -#define BCM6362_CLK_USBH 13 -#define BCM6362_CLK_IPSEC 14 -#define BCM6362_CLK_SPI 15 -#define BCM6362_CLK_HSSPI 16 -#define BCM6362_CLK_PCIE 17 -#define BCM6362_CLK_FAP 18 -#define BCM6362_CLK_PHYMIPS 19 -#define BCM6362_CLK_NAND 20 - -#endif /* __DT_BINDINGS_CLOCK_BCM6362_H */ diff --git a/include/dt-bindings/clock/bcm6368-clock.h b/include/dt-bindings/clock/bcm6368-clock.h deleted file mode 100644 index 0c857826329..00000000000 --- a/include/dt-bindings/clock/bcm6368-clock.h +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com> - * - * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h - */ - -#ifndef __DT_BINDINGS_CLOCK_BCM6368_H -#define __DT_BINDINGS_CLOCK_BCM6368_H - -#define BCM6368_CLK_VDSL_QPROC 2 -#define BCM6368_CLK_VDSL_AFE 3 -#define BCM6368_CLK_VDSL_BONDING 4 -#define BCM6368_CLK_VDSL 5 -#define BCM6368_CLK_PHYMIPS 6 -#define BCM6368_CLK_SWPKT_USB 7 -#define BCM6368_CLK_SWPKT_SAR 8 -#define BCM6368_CLK_SPI 9 -#define BCM6368_CLK_USBD 10 -#define BCM6368_CLK_SAR 11 -#define BCM6368_CLK_ROBOSW 12 -#define BCM6368_CLK_UTOPIA 13 -#define BCM6368_CLK_PCM 14 -#define BCM6368_CLK_USBH 15 -#define BCM6368_CLK_GLESS 16 -#define BCM6368_CLK_NAND 17 -#define BCM6368_CLK_IPSEC 18 -#define BCM6368_CLK_USBH_IDDQ 19 - -#endif /* __DT_BINDINGS_CLOCK_BCM6368_H */ diff --git a/include/dt-bindings/clock/boston-clock.h b/include/dt-bindings/clock/boston-clock.h deleted file mode 100644 index 0b3906247c8..00000000000 --- a/include/dt-bindings/clock/boston-clock.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2016 Imagination Technologies - */ - -#ifndef __DT_BINDINGS_CLOCK_BOSTON_CLOCK_H__ -#define __DT_BINDINGS_CLOCK_BOSTON_CLOCK_H__ - -#define BOSTON_CLK_SYS 0 -#define BOSTON_CLK_CPU 1 - -#endif /* __DT_BINDINGS_CLOCK_BOSTON_CLOCK_H__ */ diff --git a/include/dt-bindings/clock/fsl,qoriq-clockgen.h b/include/dt-bindings/clock/fsl,qoriq-clockgen.h deleted file mode 100644 index ddec7d0bdc7..00000000000 --- a/include/dt-bindings/clock/fsl,qoriq-clockgen.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef DT_CLOCK_FSL_QORIQ_CLOCKGEN_H -#define DT_CLOCK_FSL_QORIQ_CLOCKGEN_H - -#define QORIQ_CLK_SYSCLK 0 -#define QORIQ_CLK_CMUX 1 -#define QORIQ_CLK_HWACCEL 2 -#define QORIQ_CLK_FMAN 3 -#define QORIQ_CLK_PLATFORM_PLL 4 -#define QORIQ_CLK_CORECLK 5 - -#define QORIQ_CLK_PLL_DIV(x) ((x) - 1) - -#endif /* DT_CLOCK_FSL_QORIQ_CLOCKGEN_H */ diff --git a/include/dt-bindings/clock/hi3660-clock.h b/include/dt-bindings/clock/hi3660-clock.h deleted file mode 100644 index e1374e18094..00000000000 --- a/include/dt-bindings/clock/hi3660-clock.h +++ /dev/null @@ -1,214 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (c) 2016-2017 Linaro Ltd. - * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd. - */ - -#ifndef __DTS_HI3660_CLOCK_H -#define __DTS_HI3660_CLOCK_H - -/* fixed rate clocks */ -#define HI3660_CLKIN_SYS 0 -#define HI3660_CLKIN_REF 1 -#define HI3660_CLK_FLL_SRC 2 -#define HI3660_CLK_PPLL0 3 -#define HI3660_CLK_PPLL1 4 -#define HI3660_CLK_PPLL2 5 -#define HI3660_CLK_PPLL3 6 -#define HI3660_CLK_SCPLL 7 -#define HI3660_PCLK 8 -#define HI3660_CLK_UART0_DBG 9 -#define HI3660_CLK_UART6 10 -#define HI3660_OSC32K 11 -#define HI3660_OSC19M 12 -#define HI3660_CLK_480M 13 -#define HI3660_CLK_INV 14 - -/* clk in crgctrl */ -#define HI3660_FACTOR_UART3 15 -#define HI3660_CLK_FACTOR_MMC 16 -#define HI3660_CLK_GATE_I2C0 17 -#define HI3660_CLK_GATE_I2C1 18 -#define HI3660_CLK_GATE_I2C2 19 -#define HI3660_CLK_GATE_I2C6 20 -#define HI3660_CLK_DIV_SYSBUS 21 -#define HI3660_CLK_DIV_320M 22 -#define HI3660_CLK_DIV_A53 23 -#define HI3660_CLK_GATE_SPI0 24 -#define HI3660_CLK_GATE_SPI2 25 -#define HI3660_PCIEPHY_REF 26 -#define HI3660_CLK_ABB_USB 27 -#define HI3660_HCLK_GATE_SDIO0 28 -#define HI3660_HCLK_GATE_SD 29 -#define HI3660_CLK_GATE_AOMM 30 -#define HI3660_PCLK_GPIO0 31 -#define HI3660_PCLK_GPIO1 32 -#define HI3660_PCLK_GPIO2 33 -#define HI3660_PCLK_GPIO3 34 -#define HI3660_PCLK_GPIO4 35 -#define HI3660_PCLK_GPIO5 36 -#define HI3660_PCLK_GPIO6 37 -#define HI3660_PCLK_GPIO7 38 -#define HI3660_PCLK_GPIO8 39 -#define HI3660_PCLK_GPIO9 40 -#define HI3660_PCLK_GPIO10 41 -#define HI3660_PCLK_GPIO11 42 -#define HI3660_PCLK_GPIO12 43 -#define HI3660_PCLK_GPIO13 44 -#define HI3660_PCLK_GPIO14 45 -#define HI3660_PCLK_GPIO15 46 -#define HI3660_PCLK_GPIO16 47 -#define HI3660_PCLK_GPIO17 48 -#define HI3660_PCLK_GPIO18 49 -#define HI3660_PCLK_GPIO19 50 -#define HI3660_PCLK_GPIO20 51 -#define HI3660_PCLK_GPIO21 52 -#define HI3660_CLK_GATE_SPI3 53 -#define HI3660_CLK_GATE_I2C7 54 -#define HI3660_CLK_GATE_I2C3 55 -#define HI3660_CLK_GATE_SPI1 56 -#define HI3660_CLK_GATE_UART1 57 -#define HI3660_CLK_GATE_UART2 58 -#define HI3660_CLK_GATE_UART4 59 -#define HI3660_CLK_GATE_UART5 60 -#define HI3660_CLK_GATE_I2C4 61 -#define HI3660_CLK_GATE_DMAC 62 -#define HI3660_PCLK_GATE_DSS 63 -#define HI3660_ACLK_GATE_DSS 64 -#define HI3660_CLK_GATE_LDI1 65 -#define HI3660_CLK_GATE_LDI0 66 -#define HI3660_CLK_GATE_VIVOBUS 67 -#define HI3660_CLK_GATE_EDC0 68 -#define HI3660_CLK_GATE_TXDPHY0_CFG 69 -#define HI3660_CLK_GATE_TXDPHY0_REF 70 -#define HI3660_CLK_GATE_TXDPHY1_CFG 71 -#define HI3660_CLK_GATE_TXDPHY1_REF 72 -#define HI3660_ACLK_GATE_USB3OTG 73 -#define HI3660_CLK_GATE_SPI4 74 -#define HI3660_CLK_GATE_SD 75 -#define HI3660_CLK_GATE_SDIO0 76 -#define HI3660_CLK_GATE_UFS_SUBSYS 77 -#define HI3660_PCLK_GATE_DSI0 78 -#define HI3660_PCLK_GATE_DSI1 79 -#define HI3660_ACLK_GATE_PCIE 80 -#define HI3660_PCLK_GATE_PCIE_SYS 81 -#define HI3660_CLK_GATE_PCIEAUX 82 -#define HI3660_PCLK_GATE_PCIE_PHY 83 -#define HI3660_CLK_ANDGT_LDI0 84 -#define HI3660_CLK_ANDGT_LDI1 85 -#define HI3660_CLK_ANDGT_EDC0 86 -#define HI3660_CLK_GATE_UFSPHY_GT 87 -#define HI3660_CLK_ANDGT_MMC 88 -#define HI3660_CLK_ANDGT_SD 89 -#define HI3660_CLK_A53HPM_ANDGT 90 -#define HI3660_CLK_ANDGT_SDIO 91 -#define HI3660_CLK_ANDGT_UART0 92 -#define HI3660_CLK_ANDGT_UART1 93 -#define HI3660_CLK_ANDGT_UARTH 94 -#define HI3660_CLK_ANDGT_SPI 95 -#define HI3660_CLK_VIVOBUS_ANDGT 96 -#define HI3660_CLK_AOMM_ANDGT 97 -#define HI3660_CLK_320M_PLL_GT 98 -#define HI3660_AUTODIV_EMMC0BUS 99 -#define HI3660_AUTODIV_SYSBUS 100 -#define HI3660_CLK_GATE_UFSPHY_CFG 101 -#define HI3660_CLK_GATE_UFSIO_REF 102 -#define HI3660_CLK_MUX_SYSBUS 103 -#define HI3660_CLK_MUX_UART0 104 -#define HI3660_CLK_MUX_UART1 105 -#define HI3660_CLK_MUX_UARTH 106 -#define HI3660_CLK_MUX_SPI 107 -#define HI3660_CLK_MUX_I2C 108 -#define HI3660_CLK_MUX_MMC_PLL 109 -#define HI3660_CLK_MUX_LDI1 110 -#define HI3660_CLK_MUX_LDI0 111 -#define HI3660_CLK_MUX_SD_PLL 112 -#define HI3660_CLK_MUX_SD_SYS 113 -#define HI3660_CLK_MUX_EDC0 114 -#define HI3660_CLK_MUX_SDIO_SYS 115 -#define HI3660_CLK_MUX_SDIO_PLL 116 -#define HI3660_CLK_MUX_VIVOBUS 117 -#define HI3660_CLK_MUX_A53HPM 118 -#define HI3660_CLK_MUX_320M 119 -#define HI3660_CLK_MUX_IOPERI 120 -#define HI3660_CLK_DIV_UART0 121 -#define HI3660_CLK_DIV_UART1 122 -#define HI3660_CLK_DIV_UARTH 123 -#define HI3660_CLK_DIV_MMC 124 -#define HI3660_CLK_DIV_SD 125 -#define HI3660_CLK_DIV_EDC0 126 -#define HI3660_CLK_DIV_LDI0 127 -#define HI3660_CLK_DIV_SDIO 128 -#define HI3660_CLK_DIV_LDI1 129 -#define HI3660_CLK_DIV_SPI 130 -#define HI3660_CLK_DIV_VIVOBUS 131 -#define HI3660_CLK_DIV_I2C 132 -#define HI3660_CLK_DIV_UFSPHY 133 -#define HI3660_CLK_DIV_CFGBUS 134 -#define HI3660_CLK_DIV_MMC0BUS 135 -#define HI3660_CLK_DIV_MMC1BUS 136 -#define HI3660_CLK_DIV_UFSPERI 137 -#define HI3660_CLK_DIV_AOMM 138 -#define HI3660_CLK_DIV_IOPERI 139 -#define HI3660_VENC_VOLT_HOLD 140 -#define HI3660_PERI_VOLT_HOLD 141 -#define HI3660_CLK_GATE_VENC 142 -#define HI3660_CLK_GATE_VDEC 143 -#define HI3660_CLK_ANDGT_VENC 144 -#define HI3660_CLK_ANDGT_VDEC 145 -#define HI3660_CLK_MUX_VENC 146 -#define HI3660_CLK_MUX_VDEC 147 -#define HI3660_CLK_DIV_VENC 148 -#define HI3660_CLK_DIV_VDEC 149 -#define HI3660_CLK_FAC_ISP_SNCLK 150 -#define HI3660_CLK_GATE_ISP_SNCLK0 151 -#define HI3660_CLK_GATE_ISP_SNCLK1 152 -#define HI3660_CLK_GATE_ISP_SNCLK2 153 -#define HI3660_CLK_ANGT_ISP_SNCLK 154 -#define HI3660_CLK_MUX_ISP_SNCLK 155 -#define HI3660_CLK_DIV_ISP_SNCLK 156 - -/* clk in pmuctrl */ -#define HI3660_GATE_ABB_192 0 - -/* clk in pctrl */ -#define HI3660_GATE_UFS_TCXO_EN 0 -#define HI3660_GATE_USB_TCXO_EN 1 - -/* clk in sctrl */ -#define HI3660_PCLK_AO_GPIO0 0 -#define HI3660_PCLK_AO_GPIO1 1 -#define HI3660_PCLK_AO_GPIO2 2 -#define HI3660_PCLK_AO_GPIO3 3 -#define HI3660_PCLK_AO_GPIO4 4 -#define HI3660_PCLK_AO_GPIO5 5 -#define HI3660_PCLK_AO_GPIO6 6 -#define HI3660_PCLK_GATE_MMBUF 7 -#define HI3660_CLK_GATE_DSS_AXI_MM 8 -#define HI3660_PCLK_MMBUF_ANDGT 9 -#define HI3660_CLK_MMBUF_PLL_ANDGT 10 -#define HI3660_CLK_FLL_MMBUF_ANDGT 11 -#define HI3660_CLK_SYS_MMBUF_ANDGT 12 -#define HI3660_CLK_GATE_PCIEPHY_GT 13 -#define HI3660_ACLK_MUX_MMBUF 14 -#define HI3660_CLK_SW_MMBUF 15 -#define HI3660_CLK_DIV_AOBUS 16 -#define HI3660_PCLK_DIV_MMBUF 17 -#define HI3660_ACLK_DIV_MMBUF 18 -#define HI3660_CLK_DIV_PCIEPHY 19 - -/* clk in iomcu */ -#define HI3660_CLK_I2C0_IOMCU 0 -#define HI3660_CLK_I2C1_IOMCU 1 -#define HI3660_CLK_I2C2_IOMCU 2 -#define HI3660_CLK_I2C6_IOMCU 3 -#define HI3660_CLK_IOMCU_PERI0 4 - -/* clk in stub clock */ -#define HI3660_CLK_STUB_CLUSTER0 0 -#define HI3660_CLK_STUB_CLUSTER1 1 -#define HI3660_CLK_STUB_GPU 2 -#define HI3660_CLK_STUB_DDR 3 -#define HI3660_CLK_STUB_NUM 4 - -#endif /* __DTS_HI3660_CLOCK_H */ diff --git a/include/dt-bindings/clock/hi6220-clock.h b/include/dt-bindings/clock/hi6220-clock.h deleted file mode 100644 index 70ee3833a7a..00000000000 --- a/include/dt-bindings/clock/hi6220-clock.h +++ /dev/null @@ -1,173 +0,0 @@ -/* - * Copyright (c) 2015 Hisilicon Limited. - * - * Author: Bintian Wang <bintian.wang@huawei.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __DT_BINDINGS_CLOCK_HI6220_H -#define __DT_BINDINGS_CLOCK_HI6220_H - -/* clk in Hi6220 AO (always on) controller */ -#define HI6220_NONE_CLOCK 0 - -/* fixed rate clocks */ -#define HI6220_REF32K 1 -#define HI6220_CLK_TCXO 2 -#define HI6220_MMC1_PAD 3 -#define HI6220_MMC2_PAD 4 -#define HI6220_MMC0_PAD 5 -#define HI6220_PLL_BBP 6 -#define HI6220_PLL_GPU 7 -#define HI6220_PLL1_DDR 8 -#define HI6220_PLL_SYS 9 -#define HI6220_PLL_SYS_MEDIA 10 -#define HI6220_DDR_SRC 11 -#define HI6220_PLL_MEDIA 12 -#define HI6220_PLL_DDR 13 - -/* fixed factor clocks */ -#define HI6220_300M 14 -#define HI6220_150M 15 -#define HI6220_PICOPHY_SRC 16 -#define HI6220_MMC0_SRC_SEL 17 -#define HI6220_MMC1_SRC_SEL 18 -#define HI6220_MMC2_SRC_SEL 19 -#define HI6220_VPU_CODEC 20 -#define HI6220_MMC0_SMP 21 -#define HI6220_MMC1_SMP 22 -#define HI6220_MMC2_SMP 23 - -/* gate clocks */ -#define HI6220_WDT0_PCLK 24 -#define HI6220_WDT1_PCLK 25 -#define HI6220_WDT2_PCLK 26 -#define HI6220_TIMER0_PCLK 27 -#define HI6220_TIMER1_PCLK 28 -#define HI6220_TIMER2_PCLK 29 -#define HI6220_TIMER3_PCLK 30 -#define HI6220_TIMER4_PCLK 31 -#define HI6220_TIMER5_PCLK 32 -#define HI6220_TIMER6_PCLK 33 -#define HI6220_TIMER7_PCLK 34 -#define HI6220_TIMER8_PCLK 35 -#define HI6220_UART0_PCLK 36 - -#define HI6220_AO_NR_CLKS 37 - -/* clk in Hi6220 systrl */ -/* gate clock */ -#define HI6220_MMC0_CLK 1 -#define HI6220_MMC0_CIUCLK 2 -#define HI6220_MMC1_CLK 3 -#define HI6220_MMC1_CIUCLK 4 -#define HI6220_MMC2_CLK 5 -#define HI6220_MMC2_CIUCLK 6 -#define HI6220_USBOTG_HCLK 7 -#define HI6220_CLK_PICOPHY 8 -#define HI6220_HIFI 9 -#define HI6220_DACODEC_PCLK 10 -#define HI6220_EDMAC_ACLK 11 -#define HI6220_CS_ATB 12 -#define HI6220_I2C0_CLK 13 -#define HI6220_I2C1_CLK 14 -#define HI6220_I2C2_CLK 15 -#define HI6220_I2C3_CLK 16 -#define HI6220_UART1_PCLK 17 -#define HI6220_UART2_PCLK 18 -#define HI6220_UART3_PCLK 19 -#define HI6220_UART4_PCLK 20 -#define HI6220_SPI_CLK 21 -#define HI6220_TSENSOR_CLK 22 -#define HI6220_MMU_CLK 23 -#define HI6220_HIFI_SEL 24 -#define HI6220_MMC0_SYSPLL 25 -#define HI6220_MMC1_SYSPLL 26 -#define HI6220_MMC2_SYSPLL 27 -#define HI6220_MMC0_SEL 28 -#define HI6220_MMC1_SEL 29 -#define HI6220_BBPPLL_SEL 30 -#define HI6220_MEDIA_PLL_SRC 31 -#define HI6220_MMC2_SEL 32 -#define HI6220_CS_ATB_SYSPLL 33 - -/* mux clocks */ -#define HI6220_MMC0_SRC 34 -#define HI6220_MMC0_SMP_IN 35 -#define HI6220_MMC1_SRC 36 -#define HI6220_MMC1_SMP_IN 37 -#define HI6220_MMC2_SRC 38 -#define HI6220_MMC2_SMP_IN 39 -#define HI6220_HIFI_SRC 40 -#define HI6220_UART1_SRC 41 -#define HI6220_UART2_SRC 42 -#define HI6220_UART3_SRC 43 -#define HI6220_UART4_SRC 44 -#define HI6220_MMC0_MUX0 45 -#define HI6220_MMC1_MUX0 46 -#define HI6220_MMC2_MUX0 47 -#define HI6220_MMC0_MUX1 48 -#define HI6220_MMC1_MUX1 49 -#define HI6220_MMC2_MUX1 50 - -/* divider clocks */ -#define HI6220_CLK_BUS 51 -#define HI6220_MMC0_DIV 52 -#define HI6220_MMC1_DIV 53 -#define HI6220_MMC2_DIV 54 -#define HI6220_HIFI_DIV 55 -#define HI6220_BBPPLL0_DIV 56 -#define HI6220_CS_DAPB 57 -#define HI6220_CS_ATB_DIV 58 - -#define HI6220_SYS_NR_CLKS 59 - -/* clk in Hi6220 media controller */ -/* gate clocks */ -#define HI6220_DSI_PCLK 1 -#define HI6220_G3D_PCLK 2 -#define HI6220_ACLK_CODEC_VPU 3 -#define HI6220_ISP_SCLK 4 -#define HI6220_ADE_CORE 5 -#define HI6220_MED_MMU 6 -#define HI6220_CFG_CSI4PHY 7 -#define HI6220_CFG_CSI2PHY 8 -#define HI6220_ISP_SCLK_GATE 9 -#define HI6220_ISP_SCLK_GATE1 10 -#define HI6220_ADE_CORE_GATE 11 -#define HI6220_CODEC_VPU_GATE 12 -#define HI6220_MED_SYSPLL 13 - -/* mux clocks */ -#define HI6220_1440_1200 14 -#define HI6220_1000_1200 15 -#define HI6220_1000_1440 16 - -/* divider clocks */ -#define HI6220_CODEC_JPEG 17 -#define HI6220_ISP_SCLK_SRC 18 -#define HI6220_ISP_SCLK1 19 -#define HI6220_ADE_CORE_SRC 20 -#define HI6220_ADE_PIX_SRC 21 -#define HI6220_G3D_CLK 22 -#define HI6220_CODEC_VPU_SRC 23 - -#define HI6220_MEDIA_NR_CLKS 24 - -/* clk in Hi6220 power controller */ -/* gate clocks */ -#define HI6220_PLL_GPU_GATE 1 -#define HI6220_PLL1_DDR_GATE 2 -#define HI6220_PLL_DDR_GATE 3 -#define HI6220_PLL_MEDIA_GATE 4 -#define HI6220_PLL0_BBP_GATE 5 - -/* divider clocks */ -#define HI6220_DDRC_SRC 6 -#define HI6220_DDRC_AXI1 7 - -#define HI6220_POWER_NR_CLKS 8 -#endif diff --git a/include/dt-bindings/clock/lpc32xx-clock.h b/include/dt-bindings/clock/lpc32xx-clock.h deleted file mode 100644 index e624d3a5279..00000000000 --- a/include/dt-bindings/clock/lpc32xx-clock.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright (c) 2015 Vladimir Zapolskiy <vz@mleia.com> - * - * This code is released using a dual license strategy: BSD/GPL - * You can choose the licence that better fits your requirements. - * - * Released under the terms of 3-clause BSD License - * Released under the terms of GNU General Public License Version 2.0 - * - */ - -#ifndef __DT_BINDINGS_LPC32XX_CLOCK_H -#define __DT_BINDINGS_LPC32XX_CLOCK_H - -/* LPC32XX System Control Block clocks */ -#define LPC32XX_CLK_RTC 1 -#define LPC32XX_CLK_DMA 2 -#define LPC32XX_CLK_MLC 3 -#define LPC32XX_CLK_SLC 4 -#define LPC32XX_CLK_LCD 5 -#define LPC32XX_CLK_MAC 6 -#define LPC32XX_CLK_SD 7 -#define LPC32XX_CLK_DDRAM 8 -#define LPC32XX_CLK_SSP0 9 -#define LPC32XX_CLK_SSP1 10 -#define LPC32XX_CLK_UART3 11 -#define LPC32XX_CLK_UART4 12 -#define LPC32XX_CLK_UART5 13 -#define LPC32XX_CLK_UART6 14 -#define LPC32XX_CLK_IRDA 15 -#define LPC32XX_CLK_I2C1 16 -#define LPC32XX_CLK_I2C2 17 -#define LPC32XX_CLK_TIMER0 18 -#define LPC32XX_CLK_TIMER1 19 -#define LPC32XX_CLK_TIMER2 20 -#define LPC32XX_CLK_TIMER3 21 -#define LPC32XX_CLK_TIMER4 22 -#define LPC32XX_CLK_TIMER5 23 -#define LPC32XX_CLK_WDOG 24 -#define LPC32XX_CLK_I2S0 25 -#define LPC32XX_CLK_I2S1 26 -#define LPC32XX_CLK_SPI1 27 -#define LPC32XX_CLK_SPI2 28 -#define LPC32XX_CLK_MCPWM 29 -#define LPC32XX_CLK_HSTIMER 30 -#define LPC32XX_CLK_KEY 31 -#define LPC32XX_CLK_PWM1 32 -#define LPC32XX_CLK_PWM2 33 -#define LPC32XX_CLK_ADC 34 -#define LPC32XX_CLK_HCLK_PLL 35 -#define LPC32XX_CLK_PERIPH 36 - -/* LPC32XX USB clocks */ -#define LPC32XX_USB_CLK_I2C 1 -#define LPC32XX_USB_CLK_DEVICE 2 -#define LPC32XX_USB_CLK_HOST 3 - -#endif /* __DT_BINDINGS_LPC32XX_CLOCK_H */ diff --git a/include/dt-bindings/clock/maxim,max77802.h b/include/dt-bindings/clock/maxim,max77802.h deleted file mode 100644 index 997312edcbb..00000000000 --- a/include/dt-bindings/clock/maxim,max77802.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (C) 2014 Google, Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Device Tree binding constants clocks for the Maxim 77802 PMIC. - */ - -#ifndef _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H -#define _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H - -/* Fixed rate clocks. */ - -#define MAX77802_CLK_32K_AP 0 -#define MAX77802_CLK_32K_CP 1 - -/* Total number of clocks. */ -#define MAX77802_CLKS_NUM (MAX77802_CLK_32K_CP + 1) - -#endif /* _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H */ diff --git a/include/dt-bindings/clock/mt7622-clk.h b/include/dt-bindings/clock/mt7622-clk.h deleted file mode 100644 index cdbcaef76eb..00000000000 --- a/include/dt-bindings/clock/mt7622-clk.h +++ /dev/null @@ -1,276 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2019 MediaTek Inc. - */ -#ifndef _DT_BINDINGS_CLK_MT7622_H -#define _DT_BINDINGS_CLK_MT7622_H - -/* TOPCKGEN */ - -/* FIXED_CLKS */ -#define CLK_TOP_TO_U2_PHY 0 -#define CLK_TOP_TO_U2_PHY_1P 1 -#define CLK_TOP_PCIE0_PIPE_EN 2 -#define CLK_TOP_PCIE1_PIPE_EN 3 -#define CLK_TOP_SSUSB_TX250M 4 -#define CLK_TOP_SSUSB_EQ_RX250M 5 -#define CLK_TOP_SSUSB_CDR_REF 6 -#define CLK_TOP_SSUSB_CDR_FB 7 -#define CLK_TOP_SATA_ASIC 8 -#define CLK_TOP_SATA_RBC 9 -/* FIXED_DIVS */ -#define CLK_TOP_TO_USB3_SYS 10 -#define CLK_TOP_P1_1MHZ 11 -#define CLK_TOP_4MHZ 12 -#define CLK_TOP_P0_1MHZ 13 -#define CLK_TOP_TXCLK_SRC_PRE 14 -#define CLK_TOP_RTC 15 -#define CLK_TOP_MEMPLL 16 -#define CLK_TOP_DMPLL 17 -#define CLK_TOP_SYSPLL_D2 18 -#define CLK_TOP_SYSPLL1_D2 19 -#define CLK_TOP_SYSPLL1_D4 20 -#define CLK_TOP_SYSPLL1_D8 21 -#define CLK_TOP_SYSPLL2_D4 22 -#define CLK_TOP_SYSPLL2_D8 23 -#define CLK_TOP_SYSPLL_D5 24 -#define CLK_TOP_SYSPLL3_D2 25 -#define CLK_TOP_SYSPLL3_D4 26 -#define CLK_TOP_SYSPLL4_D2 27 -#define CLK_TOP_SYSPLL4_D4 28 -#define CLK_TOP_SYSPLL4_D16 29 -#define CLK_TOP_UNIVPLL 30 -#define CLK_TOP_UNIVPLL_D2 31 -#define CLK_TOP_UNIVPLL1_D2 32 -#define CLK_TOP_UNIVPLL1_D4 33 -#define CLK_TOP_UNIVPLL1_D8 34 -#define CLK_TOP_UNIVPLL1_D16 35 -#define CLK_TOP_UNIVPLL2_D2 36 -#define CLK_TOP_UNIVPLL2_D4 37 -#define CLK_TOP_UNIVPLL2_D8 38 -#define CLK_TOP_UNIVPLL2_D16 39 -#define CLK_TOP_UNIVPLL_D5 40 -#define CLK_TOP_UNIVPLL3_D2 41 -#define CLK_TOP_UNIVPLL3_D4 42 -#define CLK_TOP_UNIVPLL3_D16 43 -#define CLK_TOP_UNIVPLL_D7 44 -#define CLK_TOP_UNIVPLL_D80_D4 45 -#define CLK_TOP_UNIV48M 46 -#define CLK_TOP_SGMIIPLL 47 -#define CLK_TOP_SGMIIPLL_D2 48 -#define CLK_TOP_AUD1PLL 49 -#define CLK_TOP_AUD2PLL 50 -#define CLK_TOP_AUD_I2S2_MCK 51 -#define CLK_TOP_TO_USB3_REF 52 -#define CLK_TOP_PCIE1_MAC_EN 53 -#define CLK_TOP_PCIE0_MAC_EN 54 -#define CLK_TOP_ETH_500M 55 -/* TOP_MUXES */ -#define CLK_TOP_AXI_SEL 56 -#define CLK_TOP_MEM_SEL 57 -#define CLK_TOP_DDRPHYCFG_SEL 58 -#define CLK_TOP_ETH_SEL 59 -#define CLK_TOP_PWM_SEL 60 -#define CLK_TOP_F10M_REF_SEL 61 -#define CLK_TOP_NFI_INFRA_SEL 62 -#define CLK_TOP_FLASH_SEL 63 -#define CLK_TOP_UART_SEL 64 -#define CLK_TOP_SPI0_SEL 65 -#define CLK_TOP_SPI1_SEL 66 -#define CLK_TOP_MSDC50_0_SEL 67 -#define CLK_TOP_MSDC30_0_SEL 68 -#define CLK_TOP_MSDC30_1_SEL 69 -#define CLK_TOP_A1SYS_HP_SEL 70 -#define CLK_TOP_A2SYS_HP_SEL 71 -#define CLK_TOP_INTDIR_SEL 72 -#define CLK_TOP_AUD_INTBUS_SEL 73 -#define CLK_TOP_PMICSPI_SEL 74 -#define CLK_TOP_SCP_SEL 75 -#define CLK_TOP_ATB_SEL 76 -#define CLK_TOP_HIF_SEL 77 -#define CLK_TOP_AUDIO_SEL 78 -#define CLK_TOP_U2_SEL 79 -#define CLK_TOP_AUD1_SEL 80 -#define CLK_TOP_AUD2_SEL 81 -#define CLK_TOP_IRRX_SEL 82 -#define CLK_TOP_IRTX_SEL 83 -#define CLK_TOP_ASM_L_SEL 84 -#define CLK_TOP_ASM_M_SEL 85 -#define CLK_TOP_ASM_H_SEL 86 -#define CLK_TOP_APLL1_SEL 87 -#define CLK_TOP_APLL2_SEL 88 -#define CLK_TOP_I2S0_MCK_SEL 89 -#define CLK_TOP_I2S1_MCK_SEL 90 -#define CLK_TOP_I2S2_MCK_SEL 91 -#define CLK_TOP_I2S3_MCK_SEL 92 -#define CLK_TOP_APLL1_DIV 93 -#define CLK_TOP_APLL2_DIV 94 -#define CLK_TOP_I2S0_MCK_DIV 95 -#define CLK_TOP_I2S1_MCK_DIV 96 -#define CLK_TOP_I2S2_MCK_DIV 97 -#define CLK_TOP_I2S3_MCK_DIV 98 -#define CLK_TOP_A1SYS_HP_DIV 99 -#define CLK_TOP_A2SYS_HP_DIV 100 -#define CLK_TOP_APLL1_DIV_PD 101 -#define CLK_TOP_APLL2_DIV_PD 102 -#define CLK_TOP_I2S0_MCK_DIV_PD 103 -#define CLK_TOP_I2S1_MCK_DIV_PD 104 -#define CLK_TOP_I2S2_MCK_DIV_PD 105 -#define CLK_TOP_I2S3_MCK_DIV_PD 106 -#define CLK_TOP_A1SYS_HP_DIV_PD 107 -#define CLK_TOP_A2SYS_HP_DIV_PD 108 - -/* INFRACFG */ - -#define CLK_INFRA_MUX1_SEL 0 -#define CLK_INFRA_DBGCLK_PD 1 -#define CLK_INFRA_AUDIO_PD 2 -#define CLK_INFRA_IRRX_PD 3 -#define CLK_INFRA_APXGPT_PD 4 -#define CLK_INFRA_PMIC_PD 5 -#define CLK_INFRA_TRNG 6 - -/* PERICFG */ - -#define CLK_PERIBUS_SEL 0 -#define CLK_PERI_THERM_PD 1 -#define CLK_PERI_PWM1_PD 2 -#define CLK_PERI_PWM2_PD 3 -#define CLK_PERI_PWM3_PD 4 -#define CLK_PERI_PWM4_PD 5 -#define CLK_PERI_PWM5_PD 6 -#define CLK_PERI_PWM6_PD 7 -#define CLK_PERI_PWM7_PD 8 -#define CLK_PERI_PWM_PD 9 -#define CLK_PERI_AP_DMA_PD 10 -#define CLK_PERI_MSDC30_0_PD 11 -#define CLK_PERI_MSDC30_1_PD 12 -#define CLK_PERI_UART0_PD 13 -#define CLK_PERI_UART1_PD 14 -#define CLK_PERI_UART2_PD 15 -#define CLK_PERI_UART3_PD 16 -#define CLK_PERI_UART4_PD 17 -#define CLK_PERI_BTIF_PD 18 -#define CLK_PERI_I2C0_PD 19 -#define CLK_PERI_I2C1_PD 20 -#define CLK_PERI_I2C2_PD 21 -#define CLK_PERI_SPI1_PD 22 -#define CLK_PERI_AUXADC_PD 23 -#define CLK_PERI_SPI0_PD 24 -#define CLK_PERI_SNFI_PD 25 -#define CLK_PERI_NFI_PD 26 -#define CLK_PERI_NFIECC_PD 27 -#define CLK_PERI_FLASH_PD 28 -#define CLK_PERI_IRTX_PD 29 - -/* APMIXEDSYS */ - -#define CLK_APMIXED_ARMPLL 0 -#define CLK_APMIXED_MAINPLL 1 -#define CLK_APMIXED_UNIV2PLL 2 -#define CLK_APMIXED_ETH1PLL 3 -#define CLK_APMIXED_ETH2PLL 4 -#define CLK_APMIXED_AUD1PLL 5 -#define CLK_APMIXED_AUD2PLL 6 -#define CLK_APMIXED_TRGPLL 7 -#define CLK_APMIXED_SGMIPLL 8 -#define CLK_APMIXED_MAIN_CORE_EN 9 - -/* AUDIOSYS */ - -#define CLK_AUDIO_AFE 0 -#define CLK_AUDIO_HDMI 1 -#define CLK_AUDIO_SPDF 2 -#define CLK_AUDIO_APLL 3 -#define CLK_AUDIO_I2SIN1 4 -#define CLK_AUDIO_I2SIN2 5 -#define CLK_AUDIO_I2SIN3 6 -#define CLK_AUDIO_I2SIN4 7 -#define CLK_AUDIO_I2SO1 8 -#define CLK_AUDIO_I2SO2 9 -#define CLK_AUDIO_I2SO3 10 -#define CLK_AUDIO_I2SO4 11 -#define CLK_AUDIO_ASRCI1 12 -#define CLK_AUDIO_ASRCI2 13 -#define CLK_AUDIO_ASRCO1 14 -#define CLK_AUDIO_ASRCO2 15 -#define CLK_AUDIO_INTDIR 16 -#define CLK_AUDIO_A1SYS 17 -#define CLK_AUDIO_A2SYS 18 -#define CLK_AUDIO_UL1 19 -#define CLK_AUDIO_UL2 20 -#define CLK_AUDIO_UL3 21 -#define CLK_AUDIO_UL4 22 -#define CLK_AUDIO_UL5 23 -#define CLK_AUDIO_UL6 24 -#define CLK_AUDIO_DL1 25 -#define CLK_AUDIO_DL2 26 -#define CLK_AUDIO_DL3 27 -#define CLK_AUDIO_DL4 28 -#define CLK_AUDIO_DL5 29 -#define CLK_AUDIO_DL6 30 -#define CLK_AUDIO_DLMCH 31 -#define CLK_AUDIO_ARB1 32 -#define CLK_AUDIO_AWB 33 -#define CLK_AUDIO_AWB2 34 -#define CLK_AUDIO_DAI 35 -#define CLK_AUDIO_MOD 36 -#define CLK_AUDIO_ASRCI3 37 -#define CLK_AUDIO_ASRCI4 38 -#define CLK_AUDIO_ASRCO3 39 -#define CLK_AUDIO_ASRCO4 40 -#define CLK_AUDIO_MEM_ASRC1 41 -#define CLK_AUDIO_MEM_ASRC2 42 -#define CLK_AUDIO_MEM_ASRC3 43 -#define CLK_AUDIO_MEM_ASRC4 44 -#define CLK_AUDIO_MEM_ASRC5 45 -#define CLK_AUDIO_AFE_CONN 46 -#define CLK_AUDIO_NR_CLK 47 - -/* SSUSBSYS */ - -#define CLK_SSUSB_U2_PHY_1P_EN 0 -#define CLK_SSUSB_U2_PHY_EN 1 -#define CLK_SSUSB_REF_EN 2 -#define CLK_SSUSB_SYS_EN 3 -#define CLK_SSUSB_MCU_EN 4 -#define CLK_SSUSB_DMA_EN 5 -#define CLK_SSUSB_NR_CLK 6 - -/* PCIESYS */ - -#define CLK_PCIE_P1_AUX_EN 0 -#define CLK_PCIE_P1_OBFF_EN 1 -#define CLK_PCIE_P1_AHB_EN 2 -#define CLK_PCIE_P1_AXI_EN 3 -#define CLK_PCIE_P1_MAC_EN 4 -#define CLK_PCIE_P1_PIPE_EN 5 -#define CLK_PCIE_P0_AUX_EN 6 -#define CLK_PCIE_P0_OBFF_EN 7 -#define CLK_PCIE_P0_AHB_EN 8 -#define CLK_PCIE_P0_AXI_EN 9 -#define CLK_PCIE_P0_MAC_EN 10 -#define CLK_PCIE_P0_PIPE_EN 11 -#define CLK_SATA_AHB_EN 12 -#define CLK_SATA_AXI_EN 13 -#define CLK_SATA_ASIC_EN 14 -#define CLK_SATA_RBC_EN 15 -#define CLK_SATA_PM_EN 16 -#define CLK_PCIE_NR_CLK 17 - -/* ETHSYS */ - -#define CLK_ETH_HSDMA_EN 0 -#define CLK_ETH_ESW_EN 1 -#define CLK_ETH_GP2_EN 2 -#define CLK_ETH_GP1_EN 3 -#define CLK_ETH_GP0_EN 4 - -/* SGMIISYS */ - -#define CLK_SGMII_TX250M_EN 0 -#define CLK_SGMII_RX250M_EN 1 -#define CLK_SGMII_CDR_REF 2 -#define CLK_SGMII_CDR_FB 3 - -#endif /* _DT_BINDINGS_CLK_MT7622_H */ diff --git a/include/dt-bindings/clock/omap4.h b/include/dt-bindings/clock/omap4.h deleted file mode 100644 index 88d73be84b9..00000000000 --- a/include/dt-bindings/clock/omap4.h +++ /dev/null @@ -1,149 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2017 Texas Instruments, Inc. - */ -#ifndef __DT_BINDINGS_CLK_OMAP4_H -#define __DT_BINDINGS_CLK_OMAP4_H - -#define OMAP4_CLKCTRL_OFFSET 0x20 -#define OMAP4_CLKCTRL_INDEX(offset) ((offset) - OMAP4_CLKCTRL_OFFSET) - -/* mpuss clocks */ -#define OMAP4_MPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) - -/* tesla clocks */ -#define OMAP4_DSP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) - -/* abe clocks */ -#define OMAP4_L4_ABE_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) -#define OMAP4_AESS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) -#define OMAP4_MCPDM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) -#define OMAP4_DMIC_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) -#define OMAP4_MCASP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40) -#define OMAP4_MCBSP1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x48) -#define OMAP4_MCBSP2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x50) -#define OMAP4_MCBSP3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x58) -#define OMAP4_SLIMBUS1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x60) -#define OMAP4_TIMER5_CLKCTRL OMAP4_CLKCTRL_INDEX(0x68) -#define OMAP4_TIMER6_CLKCTRL OMAP4_CLKCTRL_INDEX(0x70) -#define OMAP4_TIMER7_CLKCTRL OMAP4_CLKCTRL_INDEX(0x78) -#define OMAP4_TIMER8_CLKCTRL OMAP4_CLKCTRL_INDEX(0x80) -#define OMAP4_WD_TIMER3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x88) - -/* l4_ao clocks */ -#define OMAP4_SMARTREFLEX_MPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) -#define OMAP4_SMARTREFLEX_IVA_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) -#define OMAP4_SMARTREFLEX_CORE_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) - -/* l3_1 clocks */ -#define OMAP4_L3_MAIN_1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) - -/* l3_2 clocks */ -#define OMAP4_L3_MAIN_2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) -#define OMAP4_GPMC_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) -#define OMAP4_OCMC_RAM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) - -/* ducati clocks */ -#define OMAP4_IPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) - -/* l3_dma clocks */ -#define OMAP4_DMA_SYSTEM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) - -/* l3_emif clocks */ -#define OMAP4_DMM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) -#define OMAP4_EMIF1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) -#define OMAP4_EMIF2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) - -/* d2d clocks */ -#define OMAP4_C2C_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) - -/* l4_cfg clocks */ -#define OMAP4_L4_CFG_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) -#define OMAP4_SPINLOCK_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) -#define OMAP4_MAILBOX_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) - -/* l3_instr clocks */ -#define OMAP4_L3_MAIN_3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) -#define OMAP4_L3_INSTR_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) -#define OMAP4_OCP_WP_NOC_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40) - -/* ivahd clocks */ -#define OMAP4_IVA_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) -#define OMAP4_SL2IF_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) - -/* iss clocks */ -#define OMAP4_ISS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) -#define OMAP4_FDIF_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) - -/* l3_dss clocks */ -#define OMAP4_DSS_CORE_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) - -/* l3_gfx clocks */ -#define OMAP4_GPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) - -/* l3_init clocks */ -#define OMAP4_MMC1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) -#define OMAP4_MMC2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) -#define OMAP4_HSI_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) -#define OMAP4_USB_HOST_HS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x58) -#define OMAP4_USB_OTG_HS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x60) -#define OMAP4_USB_TLL_HS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x68) -#define OMAP4_USB_HOST_FS_CLKCTRL OMAP4_CLKCTRL_INDEX(0xd0) -#define OMAP4_OCP2SCP_USB_PHY_CLKCTRL OMAP4_CLKCTRL_INDEX(0xe0) - -/* l4_per clocks */ -#define OMAP4_TIMER10_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) -#define OMAP4_TIMER11_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) -#define OMAP4_TIMER2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) -#define OMAP4_TIMER3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40) -#define OMAP4_TIMER4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x48) -#define OMAP4_TIMER9_CLKCTRL OMAP4_CLKCTRL_INDEX(0x50) -#define OMAP4_ELM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x58) -#define OMAP4_GPIO2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x60) -#define OMAP4_GPIO3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x68) -#define OMAP4_GPIO4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x70) -#define OMAP4_GPIO5_CLKCTRL OMAP4_CLKCTRL_INDEX(0x78) -#define OMAP4_GPIO6_CLKCTRL OMAP4_CLKCTRL_INDEX(0x80) -#define OMAP4_HDQ1W_CLKCTRL OMAP4_CLKCTRL_INDEX(0x88) -#define OMAP4_I2C1_CLKCTRL OMAP4_CLKCTRL_INDEX(0xa0) -#define OMAP4_I2C2_CLKCTRL OMAP4_CLKCTRL_INDEX(0xa8) -#define OMAP4_I2C3_CLKCTRL OMAP4_CLKCTRL_INDEX(0xb0) -#define OMAP4_I2C4_CLKCTRL OMAP4_CLKCTRL_INDEX(0xb8) -#define OMAP4_L4_PER_CLKCTRL OMAP4_CLKCTRL_INDEX(0xc0) -#define OMAP4_MCBSP4_CLKCTRL OMAP4_CLKCTRL_INDEX(0xe0) -#define OMAP4_MCSPI1_CLKCTRL OMAP4_CLKCTRL_INDEX(0xf0) -#define OMAP4_MCSPI2_CLKCTRL OMAP4_CLKCTRL_INDEX(0xf8) -#define OMAP4_MCSPI3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x100) -#define OMAP4_MCSPI4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x108) -#define OMAP4_MMC3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x120) -#define OMAP4_MMC4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x128) -#define OMAP4_SLIMBUS2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x138) -#define OMAP4_UART1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x140) -#define OMAP4_UART2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x148) -#define OMAP4_UART3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x150) -#define OMAP4_UART4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x158) -#define OMAP4_MMC5_CLKCTRL OMAP4_CLKCTRL_INDEX(0x160) - -/* l4_secure clocks */ -#define OMAP4_L4_SECURE_CLKCTRL_OFFSET 0x1a0 -#define OMAP4_L4_SECURE_CLKCTRL_INDEX(offset) ((offset) - OMAP4_L4_SECURE_CLKCTRL_OFFSET) -#define OMAP4_AES1_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1a0) -#define OMAP4_AES2_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1a8) -#define OMAP4_DES3DES_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1b0) -#define OMAP4_PKA_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1b8) -#define OMAP4_RNG_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1c0) -#define OMAP4_SHA2MD5_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1c8) -#define OMAP4_CRYPTODMA_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1d8) - -/* l4_wkup clocks */ -#define OMAP4_L4_WKUP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) -#define OMAP4_WD_TIMER2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) -#define OMAP4_GPIO1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) -#define OMAP4_TIMER1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40) -#define OMAP4_COUNTER_32K_CLKCTRL OMAP4_CLKCTRL_INDEX(0x50) -#define OMAP4_KBD_CLKCTRL OMAP4_CLKCTRL_INDEX(0x78) - -/* emu_sys clocks */ -#define OMAP4_DEBUGSS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) - -#endif diff --git a/include/dt-bindings/clock/omap5.h b/include/dt-bindings/clock/omap5.h deleted file mode 100644 index 41775272fd2..00000000000 --- a/include/dt-bindings/clock/omap5.h +++ /dev/null @@ -1,129 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2017 Texas Instruments, Inc. - */ -#ifndef __DT_BINDINGS_CLK_OMAP5_H -#define __DT_BINDINGS_CLK_OMAP5_H - -#define OMAP5_CLKCTRL_OFFSET 0x20 -#define OMAP5_CLKCTRL_INDEX(offset) ((offset) - OMAP5_CLKCTRL_OFFSET) - -/* mpu clocks */ -#define OMAP5_MPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) - -/* dsp clocks */ -#define OMAP5_MMU_DSP_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) - -/* abe clocks */ -#define OMAP5_L4_ABE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) -#define OMAP5_AESS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) -#define OMAP5_MCPDM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) -#define OMAP5_DMIC_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38) -#define OMAP5_MCBSP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48) -#define OMAP5_MCBSP2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50) -#define OMAP5_MCBSP3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x58) -#define OMAP5_TIMER5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68) -#define OMAP5_TIMER6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x70) -#define OMAP5_TIMER7_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78) -#define OMAP5_TIMER8_CLKCTRL OMAP5_CLKCTRL_INDEX(0x80) - -/* l3main1 clocks */ -#define OMAP5_L3_MAIN_1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) - -/* l3main2 clocks */ -#define OMAP5_L3_MAIN_2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) - -/* ipu clocks */ -#define OMAP5_MMU_IPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) - -/* dma clocks */ -#define OMAP5_DMA_SYSTEM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) - -/* emif clocks */ -#define OMAP5_DMM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) -#define OMAP5_EMIF1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) -#define OMAP5_EMIF2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38) - -/* l4cfg clocks */ -#define OMAP5_L4_CFG_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) -#define OMAP5_SPINLOCK_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) -#define OMAP5_MAILBOX_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) - -/* l3instr clocks */ -#define OMAP5_L3_MAIN_3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) -#define OMAP5_L3_INSTR_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) - -/* l4per clocks */ -#define OMAP5_TIMER10_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) -#define OMAP5_TIMER11_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) -#define OMAP5_TIMER2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38) -#define OMAP5_TIMER3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x40) -#define OMAP5_TIMER4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48) -#define OMAP5_TIMER9_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50) -#define OMAP5_GPIO2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x60) -#define OMAP5_GPIO3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68) -#define OMAP5_GPIO4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x70) -#define OMAP5_GPIO5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78) -#define OMAP5_GPIO6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x80) -#define OMAP5_I2C1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xa0) -#define OMAP5_I2C2_CLKCTRL OMAP5_CLKCTRL_INDEX(0xa8) -#define OMAP5_I2C3_CLKCTRL OMAP5_CLKCTRL_INDEX(0xb0) -#define OMAP5_I2C4_CLKCTRL OMAP5_CLKCTRL_INDEX(0xb8) -#define OMAP5_L4_PER_CLKCTRL OMAP5_CLKCTRL_INDEX(0xc0) -#define OMAP5_MCSPI1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf0) -#define OMAP5_MCSPI2_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf8) -#define OMAP5_MCSPI3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x100) -#define OMAP5_MCSPI4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x108) -#define OMAP5_GPIO7_CLKCTRL OMAP5_CLKCTRL_INDEX(0x110) -#define OMAP5_GPIO8_CLKCTRL OMAP5_CLKCTRL_INDEX(0x118) -#define OMAP5_MMC3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x120) -#define OMAP5_MMC4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x128) -#define OMAP5_UART1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x140) -#define OMAP5_UART2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x148) -#define OMAP5_UART3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x150) -#define OMAP5_UART4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x158) -#define OMAP5_MMC5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x160) -#define OMAP5_I2C5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x168) -#define OMAP5_UART5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x170) -#define OMAP5_UART6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x178) - -/* l4_secure clocks */ -#define OMAP5_L4_SECURE_CLKCTRL_OFFSET 0x1a0 -#define OMAP5_L4_SECURE_CLKCTRL_INDEX(offset) ((offset) - OMAP5_L4_SECURE_CLKCTRL_OFFSET) -#define OMAP5_AES1_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1a0) -#define OMAP5_AES2_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1a8) -#define OMAP5_DES3DES_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1b0) -#define OMAP5_FPKA_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1b8) -#define OMAP5_RNG_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1c0) -#define OMAP5_SHA2MD5_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1c8) -#define OMAP5_DMA_CRYPTO_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1d8) - -/* iva clocks */ -#define OMAP5_IVA_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) -#define OMAP5_SL2IF_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) - -/* dss clocks */ -#define OMAP5_DSS_CORE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) - -/* gpu clocks */ -#define OMAP5_GPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) - -/* l3init clocks */ -#define OMAP5_MMC1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) -#define OMAP5_MMC2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) -#define OMAP5_USB_HOST_HS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x58) -#define OMAP5_USB_TLL_HS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68) -#define OMAP5_SATA_CLKCTRL OMAP5_CLKCTRL_INDEX(0x88) -#define OMAP5_OCP2SCP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xe0) -#define OMAP5_OCP2SCP3_CLKCTRL OMAP5_CLKCTRL_INDEX(0xe8) -#define OMAP5_USB_OTG_SS_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf0) - -/* wkupaon clocks */ -#define OMAP5_L4_WKUP_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) -#define OMAP5_WD_TIMER2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) -#define OMAP5_GPIO1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38) -#define OMAP5_TIMER1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x40) -#define OMAP5_COUNTER_32K_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50) -#define OMAP5_KBD_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78) - -#endif diff --git a/include/dt-bindings/clock/r7s72100-clock.h b/include/dt-bindings/clock/r7s72100-clock.h deleted file mode 100644 index a267ac25014..00000000000 --- a/include/dt-bindings/clock/r7s72100-clock.h +++ /dev/null @@ -1,112 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 - * - * Copyright (C) 2014 Renesas Solutions Corp. - * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com> - */ - -#ifndef __DT_BINDINGS_CLOCK_R7S72100_H__ -#define __DT_BINDINGS_CLOCK_R7S72100_H__ - -#define R7S72100_CLK_PLL 0 -#define R7S72100_CLK_I 1 -#define R7S72100_CLK_G 2 - -/* MSTP2 */ -#define R7S72100_CLK_CORESIGHT 0 - -/* MSTP3 */ -#define R7S72100_CLK_IEBUS 7 -#define R7S72100_CLK_IRDA 6 -#define R7S72100_CLK_LIN0 5 -#define R7S72100_CLK_LIN1 4 -#define R7S72100_CLK_MTU2 3 -#define R7S72100_CLK_CAN 2 -#define R7S72100_CLK_ADCPWR 1 -#define R7S72100_CLK_PWM 0 - -/* MSTP4 */ -#define R7S72100_CLK_SCIF0 7 -#define R7S72100_CLK_SCIF1 6 -#define R7S72100_CLK_SCIF2 5 -#define R7S72100_CLK_SCIF3 4 -#define R7S72100_CLK_SCIF4 3 -#define R7S72100_CLK_SCIF5 2 -#define R7S72100_CLK_SCIF6 1 -#define R7S72100_CLK_SCIF7 0 - -/* MSTP5 */ -#define R7S72100_CLK_SCI0 7 -#define R7S72100_CLK_SCI1 6 -#define R7S72100_CLK_SG0 5 -#define R7S72100_CLK_SG1 4 -#define R7S72100_CLK_SG2 3 -#define R7S72100_CLK_SG3 2 -#define R7S72100_CLK_OSTM0 1 -#define R7S72100_CLK_OSTM1 0 - -/* MSTP6 */ -#define R7S72100_CLK_ADC 7 -#define R7S72100_CLK_CEU 6 -#define R7S72100_CLK_DOC0 5 -#define R7S72100_CLK_DOC1 4 -#define R7S72100_CLK_DRC0 3 -#define R7S72100_CLK_DRC1 2 -#define R7S72100_CLK_JCU 1 -#define R7S72100_CLK_RTC 0 - -/* MSTP7 */ -#define R7S72100_CLK_VDEC0 7 -#define R7S72100_CLK_VDEC1 6 -#define R7S72100_CLK_ETHER 4 -#define R7S72100_CLK_NAND 3 -#define R7S72100_CLK_USB0 1 -#define R7S72100_CLK_USB1 0 - -/* MSTP8 */ -#define R7S72100_CLK_IMR0 7 -#define R7S72100_CLK_IMR1 6 -#define R7S72100_CLK_IMRDISP 5 -#define R7S72100_CLK_MMCIF 4 -#define R7S72100_CLK_MLB 3 -#define R7S72100_CLK_ETHAVB 2 -#define R7S72100_CLK_SCUX 1 - -/* MSTP9 */ -#define R7S72100_CLK_I2C0 7 -#define R7S72100_CLK_I2C1 6 -#define R7S72100_CLK_I2C2 5 -#define R7S72100_CLK_I2C3 4 -#define R7S72100_CLK_SPIBSC0 3 -#define R7S72100_CLK_SPIBSC1 2 -#define R7S72100_CLK_VDC50 1 /* and LVDS */ -#define R7S72100_CLK_VDC51 0 - -/* MSTP10 */ -#define R7S72100_CLK_SPI0 7 -#define R7S72100_CLK_SPI1 6 -#define R7S72100_CLK_SPI2 5 -#define R7S72100_CLK_SPI3 4 -#define R7S72100_CLK_SPI4 3 -#define R7S72100_CLK_CDROM 2 -#define R7S72100_CLK_SPDIF 1 -#define R7S72100_CLK_RGPVG2 0 - -/* MSTP11 */ -#define R7S72100_CLK_SSI0 5 -#define R7S72100_CLK_SSI1 4 -#define R7S72100_CLK_SSI2 3 -#define R7S72100_CLK_SSI3 2 -#define R7S72100_CLK_SSI4 1 -#define R7S72100_CLK_SSI5 0 - -/* MSTP12 */ -#define R7S72100_CLK_SDHI00 3 -#define R7S72100_CLK_SDHI01 2 -#define R7S72100_CLK_SDHI10 1 -#define R7S72100_CLK_SDHI11 0 - -/* MSTP13 */ -#define R7S72100_CLK_PIX1 2 -#define R7S72100_CLK_PIX0 1 - -#endif /* __DT_BINDINGS_CLOCK_R7S72100_H__ */ diff --git a/include/dt-bindings/clock/r9a06g032-sysctrl.h b/include/dt-bindings/clock/r9a06g032-sysctrl.h deleted file mode 100644 index d9d7b8b4f42..00000000000 --- a/include/dt-bindings/clock/r9a06g032-sysctrl.h +++ /dev/null @@ -1,149 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * R9A06G032 sysctrl IDs - * - * Copyright (C) 2018 Renesas Electronics Europe Limited - * - * Michel Pollet <michel.pollet@bp.renesas.com>, <buserror@gmail.com> - */ - -#ifndef __DT_BINDINGS_R9A06G032_SYSCTRL_H__ -#define __DT_BINDINGS_R9A06G032_SYSCTRL_H__ - -#define R9A06G032_CLK_PLL_USB 1 -#define R9A06G032_CLK_48 1 /* AKA CLK_PLL_USB */ -#define R9A06G032_MSEBIS_CLK 3 /* AKA CLKOUT_D16 */ -#define R9A06G032_MSEBIM_CLK 3 /* AKA CLKOUT_D16 */ -#define R9A06G032_CLK_DDRPHY_PLLCLK 5 /* AKA CLKOUT_D1OR2 */ -#define R9A06G032_CLK50 6 /* AKA CLKOUT_D20 */ -#define R9A06G032_CLK25 7 /* AKA CLKOUT_D40 */ -#define R9A06G032_CLK125 9 /* AKA CLKOUT_D8 */ -#define R9A06G032_CLK_P5_PG1 17 /* AKA DIV_P5_PG */ -#define R9A06G032_CLK_REF_SYNC 21 /* AKA DIV_REF_SYNC */ -#define R9A06G032_CLK_25_PG4 26 -#define R9A06G032_CLK_25_PG5 27 -#define R9A06G032_CLK_25_PG6 28 -#define R9A06G032_CLK_25_PG7 29 -#define R9A06G032_CLK_25_PG8 30 -#define R9A06G032_CLK_ADC 31 -#define R9A06G032_CLK_ECAT100 32 -#define R9A06G032_CLK_HSR100 33 -#define R9A06G032_CLK_I2C0 34 -#define R9A06G032_CLK_I2C1 35 -#define R9A06G032_CLK_MII_REF 36 -#define R9A06G032_CLK_NAND 37 -#define R9A06G032_CLK_NOUSBP2_PG6 38 -#define R9A06G032_CLK_P1_PG2 39 -#define R9A06G032_CLK_P1_PG3 40 -#define R9A06G032_CLK_P1_PG4 41 -#define R9A06G032_CLK_P4_PG3 42 -#define R9A06G032_CLK_P4_PG4 43 -#define R9A06G032_CLK_P6_PG1 44 -#define R9A06G032_CLK_P6_PG2 45 -#define R9A06G032_CLK_P6_PG3 46 -#define R9A06G032_CLK_P6_PG4 47 -#define R9A06G032_CLK_PCI_USB 48 -#define R9A06G032_CLK_QSPI0 49 -#define R9A06G032_CLK_QSPI1 50 -#define R9A06G032_CLK_RGMII_REF 51 -#define R9A06G032_CLK_RMII_REF 52 -#define R9A06G032_CLK_SDIO0 53 -#define R9A06G032_CLK_SDIO1 54 -#define R9A06G032_CLK_SERCOS100 55 -#define R9A06G032_CLK_SLCD 56 -#define R9A06G032_CLK_SPI0 57 -#define R9A06G032_CLK_SPI1 58 -#define R9A06G032_CLK_SPI2 59 -#define R9A06G032_CLK_SPI3 60 -#define R9A06G032_CLK_SPI4 61 -#define R9A06G032_CLK_SPI5 62 -#define R9A06G032_CLK_SWITCH 63 -#define R9A06G032_HCLK_ECAT125 65 -#define R9A06G032_HCLK_PINCONFIG 66 -#define R9A06G032_HCLK_SERCOS 67 -#define R9A06G032_HCLK_SGPIO2 68 -#define R9A06G032_HCLK_SGPIO3 69 -#define R9A06G032_HCLK_SGPIO4 70 -#define R9A06G032_HCLK_TIMER0 71 -#define R9A06G032_HCLK_TIMER1 72 -#define R9A06G032_HCLK_USBF 73 -#define R9A06G032_HCLK_USBH 74 -#define R9A06G032_HCLK_USBPM 75 -#define R9A06G032_CLK_48_PG_F 76 -#define R9A06G032_CLK_48_PG4 77 -#define R9A06G032_CLK_DDRPHY_PCLK 81 /* AKA CLK_REF_SYNC_D4 */ -#define R9A06G032_CLK_FW 81 /* AKA CLK_REF_SYNC_D4 */ -#define R9A06G032_CLK_CRYPTO 81 /* AKA CLK_REF_SYNC_D4 */ -#define R9A06G032_CLK_WATCHDOG 82 /* AKA CLK_REF_SYNC_D8 */ -#define R9A06G032_CLK_A7MP 84 /* AKA DIV_CA7 */ -#define R9A06G032_HCLK_CAN0 85 -#define R9A06G032_HCLK_CAN1 86 -#define R9A06G032_HCLK_DELTASIGMA 87 -#define R9A06G032_HCLK_PWMPTO 88 -#define R9A06G032_HCLK_RSV 89 -#define R9A06G032_HCLK_SGPIO0 90 -#define R9A06G032_HCLK_SGPIO1 91 -#define R9A06G032_RTOS_MDC 92 -#define R9A06G032_CLK_CM3 93 -#define R9A06G032_CLK_DDRC 94 -#define R9A06G032_CLK_ECAT25 95 -#define R9A06G032_CLK_HSR50 96 -#define R9A06G032_CLK_HW_RTOS 97 -#define R9A06G032_CLK_SERCOS50 98 -#define R9A06G032_HCLK_ADC 99 -#define R9A06G032_HCLK_CM3 100 -#define R9A06G032_HCLK_CRYPTO_EIP150 101 -#define R9A06G032_HCLK_CRYPTO_EIP93 102 -#define R9A06G032_HCLK_DDRC 103 -#define R9A06G032_HCLK_DMA0 104 -#define R9A06G032_HCLK_DMA1 105 -#define R9A06G032_HCLK_GMAC0 106 -#define R9A06G032_HCLK_GMAC1 107 -#define R9A06G032_HCLK_GPIO0 108 -#define R9A06G032_HCLK_GPIO1 109 -#define R9A06G032_HCLK_GPIO2 110 -#define R9A06G032_HCLK_HSR 111 -#define R9A06G032_HCLK_I2C0 112 -#define R9A06G032_HCLK_I2C1 113 -#define R9A06G032_HCLK_LCD 114 -#define R9A06G032_HCLK_MSEBI_M 115 -#define R9A06G032_HCLK_MSEBI_S 116 -#define R9A06G032_HCLK_NAND 117 -#define R9A06G032_HCLK_PG_I 118 -#define R9A06G032_HCLK_PG19 119 -#define R9A06G032_HCLK_PG20 120 -#define R9A06G032_HCLK_PG3 121 -#define R9A06G032_HCLK_PG4 122 -#define R9A06G032_HCLK_QSPI0 123 -#define R9A06G032_HCLK_QSPI1 124 -#define R9A06G032_HCLK_ROM 125 -#define R9A06G032_HCLK_RTC 126 -#define R9A06G032_HCLK_SDIO0 127 -#define R9A06G032_HCLK_SDIO1 128 -#define R9A06G032_HCLK_SEMAP 129 -#define R9A06G032_HCLK_SPI0 130 -#define R9A06G032_HCLK_SPI1 131 -#define R9A06G032_HCLK_SPI2 132 -#define R9A06G032_HCLK_SPI3 133 -#define R9A06G032_HCLK_SPI4 134 -#define R9A06G032_HCLK_SPI5 135 -#define R9A06G032_HCLK_SWITCH 136 -#define R9A06G032_HCLK_SWITCH_RG 137 -#define R9A06G032_HCLK_UART0 138 -#define R9A06G032_HCLK_UART1 139 -#define R9A06G032_HCLK_UART2 140 -#define R9A06G032_HCLK_UART3 141 -#define R9A06G032_HCLK_UART4 142 -#define R9A06G032_HCLK_UART5 143 -#define R9A06G032_HCLK_UART6 144 -#define R9A06G032_HCLK_UART7 145 -#define R9A06G032_CLK_UART0 146 -#define R9A06G032_CLK_UART1 147 -#define R9A06G032_CLK_UART2 148 -#define R9A06G032_CLK_UART3 149 -#define R9A06G032_CLK_UART4 150 -#define R9A06G032_CLK_UART5 151 -#define R9A06G032_CLK_UART6 152 -#define R9A06G032_CLK_UART7 153 - -#endif /* __DT_BINDINGS_R9A06G032_SYSCTRL_H__ */ diff --git a/include/dt-bindings/clock/rk3368-cru.h b/include/dt-bindings/clock/rk3368-cru.h deleted file mode 100644 index 0a06c5f514d..00000000000 --- a/include/dt-bindings/clock/rk3368-cru.h +++ /dev/null @@ -1,381 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de> - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3368_H -#define _DT_BINDINGS_CLK_ROCKCHIP_RK3368_H - -/* core clocks */ -#define PLL_APLLB 1 -#define PLL_APLLL 2 -#define PLL_DPLL 3 -#define PLL_CPLL 4 -#define PLL_GPLL 5 -#define PLL_NPLL 6 -#define ARMCLKB 7 -#define ARMCLKL 8 - -/* sclk gates (special clocks) */ -#define SCLK_GPU_CORE 64 -#define SCLK_SPI0 65 -#define SCLK_SPI1 66 -#define SCLK_SPI2 67 -#define SCLK_SDMMC 68 -#define SCLK_SDIO0 69 -#define SCLK_EMMC 71 -#define SCLK_TSADC 72 -#define SCLK_SARADC 73 -#define SCLK_NANDC0 75 -#define SCLK_UART0 77 -#define SCLK_UART1 78 -#define SCLK_UART2 79 -#define SCLK_UART3 80 -#define SCLK_UART4 81 -#define SCLK_I2S_8CH 82 -#define SCLK_SPDIF_8CH 83 -#define SCLK_I2S_2CH 84 -#define SCLK_TIMER00 85 -#define SCLK_TIMER01 86 -#define SCLK_TIMER02 87 -#define SCLK_TIMER03 88 -#define SCLK_TIMER04 89 -#define SCLK_TIMER05 90 -#define SCLK_OTGPHY0 93 -#define SCLK_OTG_ADP 96 -#define SCLK_HSICPHY480M 97 -#define SCLK_HSICPHY12M 98 -#define SCLK_MACREF 99 -#define SCLK_VOP0_PWM 100 -#define SCLK_MAC_RX 102 -#define SCLK_MAC_TX 103 -#define SCLK_EDP_24M 104 -#define SCLK_EDP 105 -#define SCLK_RGA 106 -#define SCLK_ISP 107 -#define SCLK_HDCP 108 -#define SCLK_HDMI_HDCP 109 -#define SCLK_HDMI_CEC 110 -#define SCLK_HEVC_CABAC 111 -#define SCLK_HEVC_CORE 112 -#define SCLK_I2S_8CH_OUT 113 -#define SCLK_SDMMC_DRV 114 -#define SCLK_SDIO0_DRV 115 -#define SCLK_EMMC_DRV 117 -#define SCLK_SDMMC_SAMPLE 118 -#define SCLK_SDIO0_SAMPLE 119 -#define SCLK_EMMC_SAMPLE 121 -#define SCLK_USBPHY480M 122 -#define SCLK_PVTM_CORE 123 -#define SCLK_PVTM_GPU 124 -#define SCLK_PVTM_PMU 125 -#define SCLK_SFC 126 -#define SCLK_MAC 127 -#define SCLK_MACREF_OUT 128 -#define SCLK_TIMER10 133 -#define SCLK_TIMER11 134 -#define SCLK_TIMER12 135 -#define SCLK_TIMER13 136 -#define SCLK_TIMER14 137 -#define SCLK_TIMER15 138 - -#define DCLK_VOP 190 -#define MCLK_CRYPTO 191 - -/* aclk gates */ -#define ACLK_GPU_MEM 192 -#define ACLK_GPU_CFG 193 -#define ACLK_DMAC_BUS 194 -#define ACLK_DMAC_PERI 195 -#define ACLK_PERI_MMU 196 -#define ACLK_GMAC 197 -#define ACLK_VOP 198 -#define ACLK_VOP_IEP 199 -#define ACLK_RGA 200 -#define ACLK_HDCP 201 -#define ACLK_IEP 202 -#define ACLK_VIO0_NOC 203 -#define ACLK_VIP 204 -#define ACLK_ISP 205 -#define ACLK_VIO1_NOC 206 -#define ACLK_VIDEO 208 -#define ACLK_BUS 209 -#define ACLK_PERI 210 - -/* pclk gates */ -#define PCLK_GPIO0 320 -#define PCLK_GPIO1 321 -#define PCLK_GPIO2 322 -#define PCLK_GPIO3 323 -#define PCLK_PMUGRF 324 -#define PCLK_MAILBOX 325 -#define PCLK_GRF 329 -#define PCLK_SGRF 330 -#define PCLK_PMU 331 -#define PCLK_I2C0 332 -#define PCLK_I2C1 333 -#define PCLK_I2C2 334 -#define PCLK_I2C3 335 -#define PCLK_I2C4 336 -#define PCLK_I2C5 337 -#define PCLK_SPI0 338 -#define PCLK_SPI1 339 -#define PCLK_SPI2 340 -#define PCLK_UART0 341 -#define PCLK_UART1 342 -#define PCLK_UART2 343 -#define PCLK_UART3 344 -#define PCLK_UART4 345 -#define PCLK_TSADC 346 -#define PCLK_SARADC 347 -#define PCLK_SIM 348 -#define PCLK_GMAC 349 -#define PCLK_PWM0 350 -#define PCLK_PWM1 351 -#define PCLK_TIMER0 353 -#define PCLK_TIMER1 354 -#define PCLK_EDP_CTRL 355 -#define PCLK_MIPI_DSI0 356 -#define PCLK_MIPI_CSI 358 -#define PCLK_HDCP 359 -#define PCLK_HDMI_CTRL 360 -#define PCLK_VIO_H2P 361 -#define PCLK_BUS 362 -#define PCLK_PERI 363 -#define PCLK_DDRUPCTL 364 -#define PCLK_DDRPHY 365 -#define PCLK_ISP 366 -#define PCLK_VIP 367 -#define PCLK_WDT 368 -#define PCLK_EFUSE256 369 - -/* hclk gates */ -#define HCLK_SFC 448 -#define HCLK_OTG0 449 -#define HCLK_HOST0 450 -#define HCLK_HOST1 451 -#define HCLK_HSIC 452 -#define HCLK_NANDC0 453 -#define HCLK_TSP 455 -#define HCLK_SDMMC 456 -#define HCLK_SDIO0 457 -#define HCLK_EMMC 459 -#define HCLK_HSADC 460 -#define HCLK_CRYPTO 461 -#define HCLK_I2S_2CH 462 -#define HCLK_I2S_8CH 463 -#define HCLK_SPDIF 464 -#define HCLK_VOP 465 -#define HCLK_ROM 467 -#define HCLK_IEP 468 -#define HCLK_ISP 469 -#define HCLK_RGA 470 -#define HCLK_VIO_AHB_ARBI 471 -#define HCLK_VIO_NOC 472 -#define HCLK_VIP 473 -#define HCLK_VIO_H2P 474 -#define HCLK_VIO_HDCPMMU 475 -#define HCLK_VIDEO 476 -#define HCLK_BUS 477 -#define HCLK_PERI 478 - -#define CLK_NR_CLKS (HCLK_PERI + 1) - -/* soft-reset indices */ -#define SRST_CORE_B0 0 -#define SRST_CORE_B1 1 -#define SRST_CORE_B2 2 -#define SRST_CORE_B3 3 -#define SRST_CORE_B0_PO 4 -#define SRST_CORE_B1_PO 5 -#define SRST_CORE_B2_PO 6 -#define SRST_CORE_B3_PO 7 -#define SRST_L2_B 8 -#define SRST_ADB_B 9 -#define SRST_PD_CORE_B_NIU 10 -#define SRST_PDBUS_STRSYS 11 -#define SRST_SOCDBG_B 14 -#define SRST_CORE_B_DBG 15 - -#define SRST_DMAC1 18 -#define SRST_INTMEM 19 -#define SRST_ROM 20 -#define SRST_SPDIF8CH 21 -#define SRST_I2S8CH 23 -#define SRST_MAILBOX 24 -#define SRST_I2S2CH 25 -#define SRST_EFUSE_256 26 -#define SRST_MCU_SYS 28 -#define SRST_MCU_PO 29 -#define SRST_MCU_NOC 30 -#define SRST_EFUSE 31 - -#define SRST_GPIO0 32 -#define SRST_GPIO1 33 -#define SRST_GPIO2 34 -#define SRST_GPIO3 35 -#define SRST_GPIO4 36 -#define SRST_PMUGRF 41 -#define SRST_I2C0 42 -#define SRST_I2C1 43 -#define SRST_I2C2 44 -#define SRST_I2C3 45 -#define SRST_I2C4 46 -#define SRST_I2C5 47 - -#define SRST_DWPWM 48 -#define SRST_MMC_PERI 49 -#define SRST_PERIPH_MMU 50 -#define SRST_GRF 55 -#define SRST_PMU 56 -#define SRST_PERIPH_AXI 57 -#define SRST_PERIPH_AHB 58 -#define SRST_PERIPH_APB 59 -#define SRST_PERIPH_NIU 60 -#define SRST_PDPERI_AHB_ARBI 61 -#define SRST_EMEM 62 -#define SRST_USB_PERI 63 - -#define SRST_DMAC2 64 -#define SRST_MAC 66 -#define SRST_GPS 67 -#define SRST_RKPWM 69 -#define SRST_USBHOST0 72 -#define SRST_HSIC 73 -#define SRST_HSIC_AUX 74 -#define SRST_HSIC_PHY 75 -#define SRST_HSADC 76 -#define SRST_NANDC0 77 -#define SRST_SFC 79 - -#define SRST_SPI0 83 -#define SRST_SPI1 84 -#define SRST_SPI2 85 -#define SRST_SARADC 87 -#define SRST_PDALIVE_NIU 88 -#define SRST_PDPMU_INTMEM 89 -#define SRST_PDPMU_NIU 90 -#define SRST_SGRF 91 - -#define SRST_VIO_ARBI 96 -#define SRST_RGA_NIU 97 -#define SRST_VIO0_NIU_AXI 98 -#define SRST_VIO_NIU_AHB 99 -#define SRST_LCDC0_AXI 100 -#define SRST_LCDC0_AHB 101 -#define SRST_LCDC0_DCLK 102 -#define SRST_VIP 104 -#define SRST_RGA_CORE 105 -#define SRST_IEP_AXI 106 -#define SRST_IEP_AHB 107 -#define SRST_RGA_AXI 108 -#define SRST_RGA_AHB 109 -#define SRST_ISP 110 -#define SRST_EDP_24M 111 - -#define SRST_VIDEO_AXI 112 -#define SRST_VIDEO_AHB 113 -#define SRST_MIPIDPHYTX 114 -#define SRST_MIPIDSI0 115 -#define SRST_MIPIDPHYRX 116 -#define SRST_MIPICSI 117 -#define SRST_GPU 120 -#define SRST_HDMI 121 -#define SRST_EDP 122 -#define SRST_PMU_PVTM 123 -#define SRST_CORE_PVTM 124 -#define SRST_GPU_PVTM 125 -#define SRST_GPU_SYS 126 -#define SRST_GPU_MEM_NIU 127 - -#define SRST_MMC0 128 -#define SRST_SDIO0 129 -#define SRST_EMMC 131 -#define SRST_USBOTG_AHB 132 -#define SRST_USBOTG_PHY 133 -#define SRST_USBOTG_CON 134 -#define SRST_USBHOST0_AHB 135 -#define SRST_USBHOST0_PHY 136 -#define SRST_USBHOST0_CON 137 -#define SRST_USBOTG_UTMI 138 -#define SRST_USBHOST1_UTMI 139 -#define SRST_USB_ADP 141 - -#define SRST_CORESIGHT 144 -#define SRST_PD_CORE_AHB_NOC 145 -#define SRST_PD_CORE_APB_NOC 146 -#define SRST_GIC 148 -#define SRST_LCDC_PWM0 149 -#define SRST_RGA_H2P_BRG 153 -#define SRST_VIDEO 154 -#define SRST_GPU_CFG_NIU 157 -#define SRST_TSADC 159 - -#define SRST_DDRPHY0 160 -#define SRST_DDRPHY0_APB 161 -#define SRST_DDRCTRL0 162 -#define SRST_DDRCTRL0_APB 163 -#define SRST_VIDEO_NIU 165 -#define SRST_VIDEO_NIU_AHB 167 -#define SRST_DDRMSCH0 170 -#define SRST_PDBUS_AHB 173 -#define SRST_CRYPTO 174 - -#define SRST_UART0 179 -#define SRST_UART1 180 -#define SRST_UART2 181 -#define SRST_UART3 182 -#define SRST_UART4 183 -#define SRST_SIMC 186 -#define SRST_TSP 188 -#define SRST_TSP_CLKIN0 189 - -#define SRST_CORE_L0 192 -#define SRST_CORE_L1 193 -#define SRST_CORE_L2 194 -#define SRST_CORE_L3 195 -#define SRST_CORE_L0_PO 195 -#define SRST_CORE_L1_PO 197 -#define SRST_CORE_L2_PO 198 -#define SRST_CORE_L3_PO 199 -#define SRST_L2_L 200 -#define SRST_ADB_L 201 -#define SRST_PD_CORE_L_NIU 202 -#define SRST_CCI_SYS 203 -#define SRST_CCI_DDR 204 -#define SRST_CCI 205 -#define SRST_SOCDBG_L 206 -#define SRST_CORE_L_DBG 207 - -#define SRST_CORE_B0_NC 208 -#define SRST_CORE_B0_PO_NC 209 -#define SRST_L2_B_NC 210 -#define SRST_ADB_B_NC 211 -#define SRST_PD_CORE_B_NIU_NC 212 -#define SRST_PDBUS_STRSYS_NC 213 -#define SRST_CORE_L0_NC 214 -#define SRST_CORE_L0_PO_NC 215 -#define SRST_L2_L_NC 216 -#define SRST_ADB_L_NC 217 -#define SRST_PD_CORE_L_NIU_NC 218 -#define SRST_CCI_SYS_NC 219 -#define SRST_CCI_DDR_NC 220 -#define SRST_CCI_NC 221 -#define SRST_TRACE_NC 222 - -#define SRST_TIMER00 224 -#define SRST_TIMER01 225 -#define SRST_TIMER02 226 -#define SRST_TIMER03 227 -#define SRST_TIMER04 228 -#define SRST_TIMER05 229 -#define SRST_TIMER10 230 -#define SRST_TIMER11 231 -#define SRST_TIMER12 232 -#define SRST_TIMER13 233 -#define SRST_TIMER14 234 -#define SRST_TIMER15 235 -#define SRST_TIMER0_APB 236 -#define SRST_TIMER1_APB 237 - -#endif diff --git a/include/dt-bindings/clock/sifive-fu740-prci.h b/include/dt-bindings/clock/sifive-fu740-prci.h deleted file mode 100644 index 672bdadbf6c..00000000000 --- a/include/dt-bindings/clock/sifive-fu740-prci.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ -/* - * Copyright (C) 2019 SiFive, Inc. - * Wesley Terpstra - * Paul Walmsley - * Zong Li - */ - -#ifndef __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H -#define __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H - -/* Clock indexes for use by Device Tree data and the PRCI driver */ - -#define FU740_PRCI_CLK_COREPLL 0 -#define FU740_PRCI_CLK_DDRPLL 1 -#define FU740_PRCI_CLK_GEMGXLPLL 2 -#define FU740_PRCI_CLK_DVFSCOREPLL 3 -#define FU740_PRCI_CLK_HFPCLKPLL 4 -#define FU740_PRCI_CLK_CLTXPLL 5 -#define FU740_PRCI_CLK_TLCLK 6 -#define FU740_PRCI_CLK_PCLK 7 -#define FU740_PRCI_CLK_PCIE_AUX 8 - -#endif /* __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H */ diff --git a/include/dt-bindings/clock/sophgo,cv1800.h b/include/dt-bindings/clock/sophgo,cv1800.h deleted file mode 100644 index cfbeca25a65..00000000000 --- a/include/dt-bindings/clock/sophgo,cv1800.h +++ /dev/null @@ -1,176 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ -/* - * Copyright (C) 2023 Sophgo Ltd. - */ - -#ifndef __DT_BINDINGS_SOPHGO_CV1800_CLK_H__ -#define __DT_BINDINGS_SOPHGO_CV1800_CLK_H__ - -#define CLK_MPLL 0 -#define CLK_TPLL 1 -#define CLK_FPLL 2 -#define CLK_MIPIMPLL 3 -#define CLK_A0PLL 4 -#define CLK_DISPPLL 5 -#define CLK_CAM0PLL 6 -#define CLK_CAM1PLL 7 - -#define CLK_MIPIMPLL_D3 8 -#define CLK_CAM0PLL_D2 9 -#define CLK_CAM0PLL_D3 10 - -#define CLK_TPU 11 -#define CLK_TPU_FAB 12 -#define CLK_AHB_ROM 13 -#define CLK_DDR_AXI_REG 14 -#define CLK_RTC_25M 15 -#define CLK_SRC_RTC_SYS_0 16 -#define CLK_TEMPSEN 17 -#define CLK_SARADC 18 -#define CLK_EFUSE 19 -#define CLK_APB_EFUSE 20 -#define CLK_DEBUG 21 -#define CLK_AP_DEBUG 22 -#define CLK_XTAL_MISC 23 -#define CLK_AXI4_EMMC 24 -#define CLK_EMMC 25 -#define CLK_EMMC_100K 26 -#define CLK_AXI4_SD0 27 -#define CLK_SD0 28 -#define CLK_SD0_100K 29 -#define CLK_AXI4_SD1 30 -#define CLK_SD1 31 -#define CLK_SD1_100K 32 -#define CLK_SPI_NAND 33 -#define CLK_ETH0_500M 34 -#define CLK_AXI4_ETH0 35 -#define CLK_ETH1_500M 36 -#define CLK_AXI4_ETH1 37 -#define CLK_APB_GPIO 38 -#define CLK_APB_GPIO_INTR 39 -#define CLK_GPIO_DB 40 -#define CLK_AHB_SF 41 -#define CLK_AHB_SF1 42 -#define CLK_A24M 43 -#define CLK_AUDSRC 44 -#define CLK_APB_AUDSRC 45 -#define CLK_SDMA_AXI 46 -#define CLK_SDMA_AUD0 47 -#define CLK_SDMA_AUD1 48 -#define CLK_SDMA_AUD2 49 -#define CLK_SDMA_AUD3 50 -#define CLK_I2C 51 -#define CLK_APB_I2C 52 -#define CLK_APB_I2C0 53 -#define CLK_APB_I2C1 54 -#define CLK_APB_I2C2 55 -#define CLK_APB_I2C3 56 -#define CLK_APB_I2C4 57 -#define CLK_APB_WDT 58 -#define CLK_PWM_SRC 59 -#define CLK_PWM 60 -#define CLK_SPI 61 -#define CLK_APB_SPI0 62 -#define CLK_APB_SPI1 63 -#define CLK_APB_SPI2 64 -#define CLK_APB_SPI3 65 -#define CLK_1M 66 -#define CLK_CAM0_200 67 -#define CLK_PM 68 -#define CLK_TIMER0 69 -#define CLK_TIMER1 70 -#define CLK_TIMER2 71 -#define CLK_TIMER3 72 -#define CLK_TIMER4 73 -#define CLK_TIMER5 74 -#define CLK_TIMER6 75 -#define CLK_TIMER7 76 -#define CLK_UART0 77 -#define CLK_APB_UART0 78 -#define CLK_UART1 79 -#define CLK_APB_UART1 80 -#define CLK_UART2 81 -#define CLK_APB_UART2 82 -#define CLK_UART3 83 -#define CLK_APB_UART3 84 -#define CLK_UART4 85 -#define CLK_APB_UART4 86 -#define CLK_APB_I2S0 87 -#define CLK_APB_I2S1 88 -#define CLK_APB_I2S2 89 -#define CLK_APB_I2S3 90 -#define CLK_AXI4_USB 91 -#define CLK_APB_USB 92 -#define CLK_USB_125M 93 -#define CLK_USB_33K 94 -#define CLK_USB_12M 95 -#define CLK_AXI4 96 -#define CLK_AXI6 97 -#define CLK_DSI_ESC 98 -#define CLK_AXI_VIP 99 -#define CLK_SRC_VIP_SYS_0 100 -#define CLK_SRC_VIP_SYS_1 101 -#define CLK_SRC_VIP_SYS_2 102 -#define CLK_SRC_VIP_SYS_3 103 -#define CLK_SRC_VIP_SYS_4 104 -#define CLK_CSI_BE_VIP 105 -#define CLK_CSI_MAC0_VIP 106 -#define CLK_CSI_MAC1_VIP 107 -#define CLK_CSI_MAC2_VIP 108 -#define CLK_CSI0_RX_VIP 109 -#define CLK_CSI1_RX_VIP 110 -#define CLK_ISP_TOP_VIP 111 -#define CLK_IMG_D_VIP 112 -#define CLK_IMG_V_VIP 113 -#define CLK_SC_TOP_VIP 114 -#define CLK_SC_D_VIP 115 -#define CLK_SC_V1_VIP 116 -#define CLK_SC_V2_VIP 117 -#define CLK_SC_V3_VIP 118 -#define CLK_DWA_VIP 119 -#define CLK_BT_VIP 120 -#define CLK_DISP_VIP 121 -#define CLK_DSI_MAC_VIP 122 -#define CLK_LVDS0_VIP 123 -#define CLK_LVDS1_VIP 124 -#define CLK_PAD_VI_VIP 125 -#define CLK_PAD_VI1_VIP 126 -#define CLK_PAD_VI2_VIP 127 -#define CLK_CFG_REG_VIP 128 -#define CLK_VIP_IP0 129 -#define CLK_VIP_IP1 130 -#define CLK_VIP_IP2 131 -#define CLK_VIP_IP3 132 -#define CLK_IVE_VIP 133 -#define CLK_RAW_VIP 134 -#define CLK_OSDC_VIP 135 -#define CLK_CAM0_VIP 136 -#define CLK_AXI_VIDEO_CODEC 137 -#define CLK_VC_SRC0 138 -#define CLK_VC_SRC1 139 -#define CLK_VC_SRC2 140 -#define CLK_H264C 141 -#define CLK_APB_H264C 142 -#define CLK_H265C 143 -#define CLK_APB_H265C 144 -#define CLK_JPEG 145 -#define CLK_APB_JPEG 146 -#define CLK_CAM0 147 -#define CLK_CAM1 148 -#define CLK_WGN 149 -#define CLK_WGN0 150 -#define CLK_WGN1 151 -#define CLK_WGN2 152 -#define CLK_KEYSCAN 153 -#define CLK_CFG_REG_VC 154 -#define CLK_C906_0 155 -#define CLK_C906_1 156 -#define CLK_A53 157 -#define CLK_CPU_AXI0 158 -#define CLK_CPU_GIC 159 -#define CLK_XTAL_AP 160 - -// Only for CV181x -#define CLK_DISP_SRC_VIP 161 - -#endif /* __DT_BINDINGS_SOPHGO_CV1800_CLK_H__ */ diff --git a/include/dt-bindings/clock/ste-ab8500.h b/include/dt-bindings/clock/ste-ab8500.h deleted file mode 100644 index fb42dd0cab5..00000000000 --- a/include/dt-bindings/clock/ste-ab8500.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __STE_CLK_AB8500_H__ -#define __STE_CLK_AB8500_H__ - -#define AB8500_SYSCLK_BUF2 0 -#define AB8500_SYSCLK_BUF3 1 -#define AB8500_SYSCLK_BUF4 2 -#define AB8500_SYSCLK_ULP 3 -#define AB8500_SYSCLK_INT 4 -#define AB8500_SYSCLK_AUDIO 5 - -#endif diff --git a/include/dt-bindings/clock/stm32mp13-clksrc.h b/include/dt-bindings/clock/stm32mp13-clksrc.h new file mode 100644 index 00000000000..312a6054699 --- /dev/null +++ b/include/dt-bindings/clock/stm32mp13-clksrc.h @@ -0,0 +1,399 @@ +/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + * + */ + +#ifndef _DT_BINDINGS_CLOCK_STM32MP13_CLKSRC_H_ +#define _DT_BINDINGS_CLOCK_STM32MP13_CLKSRC_H_ + +/* PLL output is enable when x=1, with x=p,q or r */ +#define PQR(p, q, r) (((p) & 1) | (((q) & 1) << 1) | (((r) & 1) << 2)) + +/* st,clksrc: mandatory clock source */ + +#define CMD_DIV 0 +#define CMD_MUX 1 +#define CMD_CLK 2 +#define CMD_RESERVED1 3 + +#define CMD_SHIFT 26 +#define CMD_MASK 0xFC000000 +#define CMD_DATA_MASK 0x03FFFFFF + +#define DIV_ID_SHIFT 8 +#define DIV_ID_MASK 0x0000FF00 + +#define DIV_DIVN_SHIFT 0 +#define DIV_DIVN_MASK 0x000000FF + +#define MUX_ID_SHIFT 4 +#define MUX_ID_MASK 0x00000FF0 + +#define MUX_SEL_SHIFT 0 +#define MUX_SEL_MASK 0x0000000F + +#define CLK_ID_MASK GENMASK_32(19, 11) +#define CLK_ID_SHIFT 11 +#define CLK_ON_MASK 0x00000400 +#define CLK_ON_SHIFT 10 +#define CLK_DIV_MASK GENMASK_32(9, 4) +#define CLK_DIV_SHIFT 4 +#define CLK_SEL_MASK GENMASK_32(3, 0) +#define CLK_SEL_SHIFT 0 + +#define DIV_PLL1DIVP 0 +#define DIV_PLL2DIVP 1 +#define DIV_PLL2DIVQ 2 +#define DIV_PLL2DIVR 3 +#define DIV_PLL3DIVP 4 +#define DIV_PLL3DIVQ 5 +#define DIV_PLL3DIVR 6 +#define DIV_PLL4DIVP 7 +#define DIV_PLL4DIVQ 8 +#define DIV_PLL4DIVR 9 +#define DIV_MPU 10 +#define DIV_AXI 11 +#define DIV_MLAHB 12 +#define DIV_APB1 13 +#define DIV_APB2 14 +#define DIV_APB3 15 +#define DIV_APB4 16 +#define DIV_APB5 17 +#define DIV_APB6 18 +#define DIV_RTC 19 +#define DIV_MCO1 20 +#define DIV_MCO2 21 +#define DIV_HSI 22 +#define DIV_TRACE 23 +#define DIV_ETH1PTP 24 +#define DIV_ETH2PTP 25 +#define DIV_MAX 26 + +#define DIV(div_id, div) ((CMD_DIV << CMD_SHIFT) |\ + ((div_id) << DIV_ID_SHIFT |\ + (div))) + +#define CLKSRC(mux_id, sel) ((CMD_MUX << CMD_SHIFT) |\ + ((mux_id) << MUX_ID_SHIFT |\ + (sel))) + +/* MCO output is enable */ +#define MCO_SRC(mco_id, sel) ((CMD_CLK << CMD_SHIFT) |\ + (((mco_id) << CLK_ID_SHIFT) |\ + (sel)) | CLK_ON_MASK) + +#define MCO_DISABLED(mco_id) ((CMD_CLK << CMD_SHIFT) |\ + ((mco_id) << CLK_ID_SHIFT)) + +/* CLK output is enable */ +#define CLK_SRC(clk_id, sel) ((CMD_CLK << CMD_SHIFT) |\ + (((clk_id) << CLK_ID_SHIFT) |\ + (sel)) | CLK_ON_MASK) + +#define CLK_DISABLED(clk_id) ((CMD_CLK << CMD_SHIFT) |\ + ((clk_id) << CLK_ID_SHIFT)) + +#define MUX_MPU 0 +#define MUX_AXI 1 +#define MUX_MLAHB 2 +#define MUX_PLL12 3 +#define MUX_PLL3 4 +#define MUX_PLL4 5 +#define MUX_RTC 6 +#define MUX_MCO1 7 +#define MUX_MCO2 8 +#define MUX_CKPER 9 +#define MUX_KERNEL_BEGIN 10 +#define MUX_ADC1 10 +#define MUX_ADC2 11 +#define MUX_DCMIPP 12 +#define MUX_ETH1 13 +#define MUX_ETH2 14 +#define MUX_FDCAN 15 +#define MUX_FMC 16 +#define MUX_I2C12 17 +#define MUX_I2C3 18 +#define MUX_I2C4 19 +#define MUX_I2C5 20 +#define MUX_LPTIM1 21 +#define MUX_LPTIM2 22 +#define MUX_LPTIM3 23 +#define MUX_LPTIM45 24 +#define MUX_QSPI 25 +#define MUX_RNG1 26 +#define MUX_SAES 27 +#define MUX_SAI1 28 +#define MUX_SAI2 29 +#define MUX_SDMMC1 30 +#define MUX_SDMMC2 31 +#define MUX_SPDIF 32 +#define MUX_SPI1 33 +#define MUX_SPI23 34 +#define MUX_SPI4 35 +#define MUX_SPI5 36 +#define MUX_STGEN 37 +#define MUX_UART1 38 +#define MUX_UART2 39 +#define MUX_UART35 40 +#define MUX_UART4 41 +#define MUX_UART6 42 +#define MUX_UART78 43 +#define MUX_USBO 44 +#define MUX_USBPHY 45 +#define MUX_MAX 46 + +#define CLK_MPU_HSI CLKSRC(MUX_MPU, 0) +#define CLK_MPU_HSE CLKSRC(MUX_MPU, 1) +#define CLK_MPU_PLL1P CLKSRC(MUX_MPU, 2) +#define CLK_MPU_PLL1P_DIV CLKSRC(MUX_MPU, 3) + +#define CLK_AXI_HSI CLKSRC(MUX_AXI, 0) +#define CLK_AXI_HSE CLKSRC(MUX_AXI, 1) +#define CLK_AXI_PLL2P CLKSRC(MUX_AXI, 2) + +#define CLK_MLAHBS_HSI CLKSRC(MUX_MLAHB, 0) +#define CLK_MLAHBS_HSE CLKSRC(MUX_MLAHB, 1) +#define CLK_MLAHBS_CSI CLKSRC(MUX_MLAHB, 2) +#define CLK_MLAHBS_PLL3 CLKSRC(MUX_MLAHB, 3) + +#define CLK_PLL12_HSI CLKSRC(MUX_PLL12, 0) +#define CLK_PLL12_HSE CLKSRC(MUX_PLL12, 1) + +#define CLK_PLL3_HSI CLKSRC(MUX_PLL3, 0) +#define CLK_PLL3_HSE CLKSRC(MUX_PLL3, 1) +#define CLK_PLL3_CSI CLKSRC(MUX_PLL3, 2) + +#define CLK_PLL4_HSI CLKSRC(MUX_PLL4, 0) +#define CLK_PLL4_HSE CLKSRC(MUX_PLL4, 1) +#define CLK_PLL4_CSI CLKSRC(MUX_PLL4, 2) + +#define CLK_RTC_DISABLED CLK_DISABLED(RTC) +#define CLK_RTC_LSE CLK_SRC(RTC, 1) +#define CLK_RTC_LSI CLK_SRC(RTC, 2) +#define CLK_RTC_HSE CLK_SRC(RTC, 3) + +#define CLK_MCO1_HSI CLK_SRC(CK_MCO1, 0) +#define CLK_MCO1_HSE CLK_SRC(CK_MCO1, 1) +#define CLK_MCO1_CSI CLK_SRC(CK_MCO1, 2) +#define CLK_MCO1_LSI CLK_SRC(CK_MCO1, 3) +#define CLK_MCO1_LSE CLK_SRC(CK_MCO1, 4) +#define CLK_MCO1_DISABLED CLK_DISABLED(CK_MCO1) + +#define CLK_MCO2_MPU CLK_SRC(CK_MCO2, 0) +#define CLK_MCO2_AXI CLK_SRC(CK_MCO2, 1) +#define CLK_MCO2_MLAHB CLK_SRC(CK_MCO2, 2) +#define CLK_MCO2_PLL4 CLK_SRC(CK_MCO2, 3) +#define CLK_MCO2_HSE CLK_SRC(CK_MCO2, 4) +#define CLK_MCO2_HSI CLK_SRC(CK_MCO2, 5) +#define CLK_MCO2_DISABLED CLK_DISABLED(CK_MCO2) + +#define CLK_CKPER_HSI CLKSRC(MUX_CKPER, 0) +#define CLK_CKPER_CSI CLKSRC(MUX_CKPER, 1) +#define CLK_CKPER_HSE CLKSRC(MUX_CKPER, 2) +#define CLK_CKPER_DISABLED CLKSRC(MUX_CKPER, 3) + +#define CLK_I2C12_PCLK1 CLKSRC(MUX_I2C12, 0) +#define CLK_I2C12_PLL4R CLKSRC(MUX_I2C12, 1) +#define CLK_I2C12_HSI CLKSRC(MUX_I2C12, 2) +#define CLK_I2C12_CSI CLKSRC(MUX_I2C12, 3) + +#define CLK_I2C3_PCLK6 CLKSRC(MUX_I2C3, 0) +#define CLK_I2C3_PLL4R CLKSRC(MUX_I2C3, 1) +#define CLK_I2C3_HSI CLKSRC(MUX_I2C3, 2) +#define CLK_I2C3_CSI CLKSRC(MUX_I2C3, 3) + +#define CLK_I2C4_PCLK6 CLKSRC(MUX_I2C4, 0) +#define CLK_I2C4_PLL4R CLKSRC(MUX_I2C4, 1) +#define CLK_I2C4_HSI CLKSRC(MUX_I2C4, 2) +#define CLK_I2C4_CSI CLKSRC(MUX_I2C4, 3) + +#define CLK_I2C5_PCLK6 CLKSRC(MUX_I2C5, 0) +#define CLK_I2C5_PLL4R CLKSRC(MUX_I2C5, 1) +#define CLK_I2C5_HSI CLKSRC(MUX_I2C5, 2) +#define CLK_I2C5_CSI CLKSRC(MUX_I2C5, 3) + +#define CLK_SPI1_PLL4P CLKSRC(MUX_SPI1, 0) +#define CLK_SPI1_PLL3Q CLKSRC(MUX_SPI1, 1) +#define CLK_SPI1_I2SCKIN CLKSRC(MUX_SPI1, 2) +#define CLK_SPI1_CKPER CLKSRC(MUX_SPI1, 3) +#define CLK_SPI1_PLL3R CLKSRC(MUX_SPI1, 4) + +#define CLK_SPI23_PLL4P CLKSRC(MUX_SPI23, 0) +#define CLK_SPI23_PLL3Q CLKSRC(MUX_SPI23, 1) +#define CLK_SPI23_I2SCKIN CLKSRC(MUX_SPI23, 2) +#define CLK_SPI23_CKPER CLKSRC(MUX_SPI23, 3) +#define CLK_SPI23_PLL3R CLKSRC(MUX_SPI23, 4) + +#define CLK_SPI4_PCLK6 CLKSRC(MUX_SPI4, 0) +#define CLK_SPI4_PLL4Q CLKSRC(MUX_SPI4, 1) +#define CLK_SPI4_HSI CLKSRC(MUX_SPI4, 2) +#define CLK_SPI4_CSI CLKSRC(MUX_SPI4, 3) +#define CLK_SPI4_HSE CLKSRC(MUX_SPI4, 4) +#define CLK_SPI4_I2SCKIN CLKSRC(MUX_SPI4, 5) + +#define CLK_SPI5_PCLK6 CLKSRC(MUX_SPI5, 0) +#define CLK_SPI5_PLL4Q CLKSRC(MUX_SPI5, 1) +#define CLK_SPI5_HSI CLKSRC(MUX_SPI5, 2) +#define CLK_SPI5_CSI CLKSRC(MUX_SPI5, 3) +#define CLK_SPI5_HSE CLKSRC(MUX_SPI5, 4) + +#define CLK_UART1_PCLK6 CLKSRC(MUX_UART1, 0) +#define CLK_UART1_PLL3Q CLKSRC(MUX_UART1, 1) +#define CLK_UART1_HSI CLKSRC(MUX_UART1, 2) +#define CLK_UART1_CSI CLKSRC(MUX_UART1, 3) +#define CLK_UART1_PLL4Q CLKSRC(MUX_UART1, 4) +#define CLK_UART1_HSE CLKSRC(MUX_UART1, 5) + +#define CLK_UART2_PCLK6 CLKSRC(MUX_UART2, 0) +#define CLK_UART2_PLL3Q CLKSRC(MUX_UART2, 1) +#define CLK_UART2_HSI CLKSRC(MUX_UART2, 2) +#define CLK_UART2_CSI CLKSRC(MUX_UART2, 3) +#define CLK_UART2_PLL4Q CLKSRC(MUX_UART2, 4) +#define CLK_UART2_HSE CLKSRC(MUX_UART2, 5) + +#define CLK_UART35_PCLK1 CLKSRC(MUX_UART35, 0) +#define CLK_UART35_PLL4Q CLKSRC(MUX_UART35, 1) +#define CLK_UART35_HSI CLKSRC(MUX_UART35, 2) +#define CLK_UART35_CSI CLKSRC(MUX_UART35, 3) +#define CLK_UART35_HSE CLKSRC(MUX_UART35, 4) + +#define CLK_UART4_PCLK1 CLKSRC(MUX_UART4, 0) +#define CLK_UART4_PLL4Q CLKSRC(MUX_UART4, 1) +#define CLK_UART4_HSI CLKSRC(MUX_UART4, 2) +#define CLK_UART4_CSI CLKSRC(MUX_UART4, 3) +#define CLK_UART4_HSE CLKSRC(MUX_UART4, 4) + +#define CLK_UART6_PCLK2 CLKSRC(MUX_UART6, 0) +#define CLK_UART6_PLL4Q CLKSRC(MUX_UART6, 1) +#define CLK_UART6_HSI CLKSRC(MUX_UART6, 2) +#define CLK_UART6_CSI CLKSRC(MUX_UART6, 3) +#define CLK_UART6_HSE CLKSRC(MUX_UART6, 4) + +#define CLK_UART78_PCLK1 CLKSRC(MUX_UART78, 0) +#define CLK_UART78_PLL4Q CLKSRC(MUX_UART78, 1) +#define CLK_UART78_HSI CLKSRC(MUX_UART78, 2) +#define CLK_UART78_CSI CLKSRC(MUX_UART78, 3) +#define CLK_UART78_HSE CLKSRC(MUX_UART78, 4) + +#define CLK_LPTIM1_PCLK1 CLKSRC(MUX_LPTIM1, 0) +#define CLK_LPTIM1_PLL4P CLKSRC(MUX_LPTIM1, 1) +#define CLK_LPTIM1_PLL3Q CLKSRC(MUX_LPTIM1, 2) +#define CLK_LPTIM1_LSE CLKSRC(MUX_LPTIM1, 3) +#define CLK_LPTIM1_LSI CLKSRC(MUX_LPTIM1, 4) +#define CLK_LPTIM1_CKPER CLKSRC(MUX_LPTIM1, 5) + +#define CLK_LPTIM2_PCLK3 CLKSRC(MUX_LPTIM2, 0) +#define CLK_LPTIM2_PLL4Q CLKSRC(MUX_LPTIM2, 1) +#define CLK_LPTIM2_CKPER CLKSRC(MUX_LPTIM2, 2) +#define CLK_LPTIM2_LSE CLKSRC(MUX_LPTIM2, 3) +#define CLK_LPTIM2_LSI CLKSRC(MUX_LPTIM2, 4) + +#define CLK_LPTIM3_PCLK3 CLKSRC(MUX_LPTIM3, 0) +#define CLK_LPTIM3_PLL4Q CLKSRC(MUX_LPTIM3, 1) +#define CLK_LPTIM3_CKPER CLKSRC(MUX_LPTIM3, 2) +#define CLK_LPTIM3_LSE CLKSRC(MUX_LPTIM3, 3) +#define CLK_LPTIM3_LSI CLKSRC(MUX_LPTIM3, 4) + +#define CLK_LPTIM45_PCLK3 CLKSRC(MUX_LPTIM45, 0) +#define CLK_LPTIM45_PLL4P CLKSRC(MUX_LPTIM45, 1) +#define CLK_LPTIM45_PLL3Q CLKSRC(MUX_LPTIM45, 2) +#define CLK_LPTIM45_LSE CLKSRC(MUX_LPTIM45, 3) +#define CLK_LPTIM45_LSI CLKSRC(MUX_LPTIM45, 4) +#define CLK_LPTIM45_CKPER CLKSRC(MUX_LPTIM45, 5) + +#define CLK_SAI1_PLL4Q CLKSRC(MUX_SAI1, 0) +#define CLK_SAI1_PLL3Q CLKSRC(MUX_SAI1, 1) +#define CLK_SAI1_I2SCKIN CLKSRC(MUX_SAI1, 2) +#define CLK_SAI1_CKPER CLKSRC(MUX_SAI1, 3) +#define CLK_SAI1_PLL3R CLKSRC(MUX_SAI1, 4) + +#define CLK_SAI2_PLL4Q CLKSRC(MUX_SAI2, 0) +#define CLK_SAI2_PLL3Q CLKSRC(MUX_SAI2, 1) +#define CLK_SAI2_I2SCKIN CLKSRC(MUX_SAI2, 2) +#define CLK_SAI2_CKPER CLKSRC(MUX_SAI2, 3) +#define CLK_SAI2_SPDIF CLKSRC(MUX_SAI2, 4) +#define CLK_SAI2_PLL3R CLKSRC(MUX_SAI2, 5) + +#define CLK_FDCAN_HSE CLKSRC(MUX_FDCAN, 0) +#define CLK_FDCAN_PLL3Q CLKSRC(MUX_FDCAN, 1) +#define CLK_FDCAN_PLL4Q CLKSRC(MUX_FDCAN, 2) +#define CLK_FDCAN_PLL4R CLKSRC(MUX_FDCAN, 3) + +#define CLK_SPDIF_PLL4P CLKSRC(MUX_SPDIF, 0) +#define CLK_SPDIF_PLL3Q CLKSRC(MUX_SPDIF, 1) +#define CLK_SPDIF_HSI CLKSRC(MUX_SPDIF, 2) + +#define CLK_ADC1_PLL4R CLKSRC(MUX_ADC1, 0) +#define CLK_ADC1_CKPER CLKSRC(MUX_ADC1, 1) +#define CLK_ADC1_PLL3Q CLKSRC(MUX_ADC1, 2) + +#define CLK_ADC2_PLL4R CLKSRC(MUX_ADC2, 0) +#define CLK_ADC2_CKPER CLKSRC(MUX_ADC2, 1) +#define CLK_ADC2_PLL3Q CLKSRC(MUX_ADC2, 2) + +#define CLK_SDMMC1_HCLK6 CLKSRC(MUX_SDMMC1, 0) +#define CLK_SDMMC1_PLL3R CLKSRC(MUX_SDMMC1, 1) +#define CLK_SDMMC1_PLL4P CLKSRC(MUX_SDMMC1, 2) +#define CLK_SDMMC1_HSI CLKSRC(MUX_SDMMC1, 3) + +#define CLK_SDMMC2_HCLK6 CLKSRC(MUX_SDMMC2, 0) +#define CLK_SDMMC2_PLL3R CLKSRC(MUX_SDMMC2, 1) +#define CLK_SDMMC2_PLL4P CLKSRC(MUX_SDMMC2, 2) +#define CLK_SDMMC2_HSI CLKSRC(MUX_SDMMC2, 3) + +#define CLK_ETH1_PLL4P CLKSRC(MUX_ETH1, 0) +#define CLK_ETH1_PLL3Q CLKSRC(MUX_ETH1, 1) + +#define CLK_ETH2_PLL4P CLKSRC(MUX_ETH2, 0) +#define CLK_ETH2_PLL3Q CLKSRC(MUX_ETH2, 1) + +#define CLK_USBPHY_HSE CLKSRC(MUX_USBPHY, 0) +#define CLK_USBPHY_PLL4R CLKSRC(MUX_USBPHY, 1) +#define CLK_USBPHY_HSE_DIV2 CLKSRC(MUX_USBPHY, 2) + +#define CLK_USBO_PLL4R CLKSRC(MUX_USBO, 0) +#define CLK_USBO_USBPHY CLKSRC(MUX_USBO, 1) + +#define CLK_QSPI_ACLK CLKSRC(MUX_QSPI, 0) +#define CLK_QSPI_PLL3R CLKSRC(MUX_QSPI, 1) +#define CLK_QSPI_PLL4P CLKSRC(MUX_QSPI, 2) +#define CLK_QSPI_CKPER CLKSRC(MUX_QSPI, 3) + +#define CLK_FMC_ACLK CLKSRC(MUX_FMC, 0) +#define CLK_FMC_PLL3R CLKSRC(MUX_FMC, 1) +#define CLK_FMC_PLL4P CLKSRC(MUX_FMC, 2) +#define CLK_FMC_CKPER CLKSRC(MUX_FMC, 3) + +#define CLK_RNG1_CSI CLKSRC(MUX_RNG1, 0) +#define CLK_RNG1_PLL4R CLKSRC(MUX_RNG1, 1) +/* WARNING: POSITION 2 OF RNG1 MUX IS RESERVED */ +#define CLK_RNG1_LSI CLKSRC(MUX_RNG1, 3) + +#define CLK_STGEN_HSI CLKSRC(MUX_STGEN, 0) +#define CLK_STGEN_HSE CLKSRC(MUX_STGEN, 1) + +#define CLK_DCMIPP_ACLK CLKSRC(MUX_DCMIPP, 0) +#define CLK_DCMIPP_PLL2Q CLKSRC(MUX_DCMIPP, 1) +#define CLK_DCMIPP_PLL4P CLKSRC(MUX_DCMIPP, 2) +#define CLK_DCMIPP_CKPER CLKSRC(MUX_DCMIPP, 3) + +#define CLK_SAES_AXI CLKSRC(MUX_SAES, 0) +#define CLK_SAES_CKPER CLKSRC(MUX_SAES, 1) +#define CLK_SAES_PLL4R CLKSRC(MUX_SAES, 2) +#define CLK_SAES_LSI CLKSRC(MUX_SAES, 3) + +/* PLL output is enable when x=1, with x=p,q or r */ +#define PQR(p, q, r) (((p) & 1) | (((q) & 1) << 1) | (((r) & 1) << 2)) + +/* define for st,pll /csg */ +#define SSCG_MODE_CENTER_SPREAD 0 +#define SSCG_MODE_DOWN_SPREAD 1 + +/* define for st,drive */ +#define LSEDRV_LOWEST 0 +#define LSEDRV_MEDIUM_LOW 1 +#define LSEDRV_MEDIUM_HIGH 2 +#define LSEDRV_HIGHEST 3 + +#endif diff --git a/include/dt-bindings/clock/sun20i-d1-ccu.h b/include/dt-bindings/clock/sun20i-d1-ccu.h deleted file mode 100644 index fdbfb404f92..00000000000 --- a/include/dt-bindings/clock/sun20i-d1-ccu.h +++ /dev/null @@ -1,158 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * Copyright (C) 2020 huangzhenwei@allwinnertech.com - * Copyright (C) 2021 Samuel Holland <samuel@sholland.org> - */ - -#ifndef _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_ -#define _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_ - -#define CLK_PLL_CPUX 0 -#define CLK_PLL_DDR0 1 -#define CLK_PLL_PERIPH0_4X 2 -#define CLK_PLL_PERIPH0_2X 3 -#define CLK_PLL_PERIPH0_800M 4 -#define CLK_PLL_PERIPH0 5 -#define CLK_PLL_PERIPH0_DIV3 6 -#define CLK_PLL_VIDEO0_4X 7 -#define CLK_PLL_VIDEO0_2X 8 -#define CLK_PLL_VIDEO0 9 -#define CLK_PLL_VIDEO1_4X 10 -#define CLK_PLL_VIDEO1_2X 11 -#define CLK_PLL_VIDEO1 12 -#define CLK_PLL_VE 13 -#define CLK_PLL_AUDIO0_4X 14 -#define CLK_PLL_AUDIO0_2X 15 -#define CLK_PLL_AUDIO0 16 -#define CLK_PLL_AUDIO1 17 -#define CLK_PLL_AUDIO1_DIV2 18 -#define CLK_PLL_AUDIO1_DIV5 19 -#define CLK_CPUX 20 -#define CLK_CPUX_AXI 21 -#define CLK_CPUX_APB 22 -#define CLK_PSI_AHB 23 -#define CLK_APB0 24 -#define CLK_APB1 25 -#define CLK_MBUS 26 -#define CLK_DE 27 -#define CLK_BUS_DE 28 -#define CLK_DI 29 -#define CLK_BUS_DI 30 -#define CLK_G2D 31 -#define CLK_BUS_G2D 32 -#define CLK_CE 33 -#define CLK_BUS_CE 34 -#define CLK_VE 35 -#define CLK_BUS_VE 36 -#define CLK_BUS_DMA 37 -#define CLK_BUS_MSGBOX0 38 -#define CLK_BUS_MSGBOX1 39 -#define CLK_BUS_MSGBOX2 40 -#define CLK_BUS_SPINLOCK 41 -#define CLK_BUS_HSTIMER 42 -#define CLK_AVS 43 -#define CLK_BUS_DBG 44 -#define CLK_BUS_PWM 45 -#define CLK_BUS_IOMMU 46 -#define CLK_DRAM 47 -#define CLK_MBUS_DMA 48 -#define CLK_MBUS_VE 49 -#define CLK_MBUS_CE 50 -#define CLK_MBUS_TVIN 51 -#define CLK_MBUS_CSI 52 -#define CLK_MBUS_G2D 53 -#define CLK_MBUS_RISCV 54 -#define CLK_BUS_DRAM 55 -#define CLK_MMC0 56 -#define CLK_MMC1 57 -#define CLK_MMC2 58 -#define CLK_BUS_MMC0 59 -#define CLK_BUS_MMC1 60 -#define CLK_BUS_MMC2 61 -#define CLK_BUS_UART0 62 -#define CLK_BUS_UART1 63 -#define CLK_BUS_UART2 64 -#define CLK_BUS_UART3 65 -#define CLK_BUS_UART4 66 -#define CLK_BUS_UART5 67 -#define CLK_BUS_I2C0 68 -#define CLK_BUS_I2C1 69 -#define CLK_BUS_I2C2 70 -#define CLK_BUS_I2C3 71 -#define CLK_SPI0 72 -#define CLK_SPI1 73 -#define CLK_BUS_SPI0 74 -#define CLK_BUS_SPI1 75 -#define CLK_EMAC_25M 76 -#define CLK_BUS_EMAC 77 -#define CLK_IR_TX 78 -#define CLK_BUS_IR_TX 79 -#define CLK_BUS_GPADC 80 -#define CLK_BUS_THS 81 -#define CLK_I2S0 82 -#define CLK_I2S1 83 -#define CLK_I2S2 84 -#define CLK_I2S2_ASRC 85 -#define CLK_BUS_I2S0 86 -#define CLK_BUS_I2S1 87 -#define CLK_BUS_I2S2 88 -#define CLK_SPDIF_TX 89 -#define CLK_SPDIF_RX 90 -#define CLK_BUS_SPDIF 91 -#define CLK_DMIC 92 -#define CLK_BUS_DMIC 93 -#define CLK_AUDIO_DAC 94 -#define CLK_AUDIO_ADC 95 -#define CLK_BUS_AUDIO 96 -#define CLK_USB_OHCI0 97 -#define CLK_USB_OHCI1 98 -#define CLK_BUS_OHCI0 99 -#define CLK_BUS_OHCI1 100 -#define CLK_BUS_EHCI0 101 -#define CLK_BUS_EHCI1 102 -#define CLK_BUS_OTG 103 -#define CLK_BUS_LRADC 104 -#define CLK_BUS_DPSS_TOP 105 -#define CLK_HDMI_24M 106 -#define CLK_HDMI_CEC_32K 107 -#define CLK_HDMI_CEC 108 -#define CLK_BUS_HDMI 109 -#define CLK_MIPI_DSI 110 -#define CLK_BUS_MIPI_DSI 111 -#define CLK_TCON_LCD0 112 -#define CLK_BUS_TCON_LCD0 113 -#define CLK_TCON_TV 114 -#define CLK_BUS_TCON_TV 115 -#define CLK_TVE 116 -#define CLK_BUS_TVE_TOP 117 -#define CLK_BUS_TVE 118 -#define CLK_TVD 119 -#define CLK_BUS_TVD_TOP 120 -#define CLK_BUS_TVD 121 -#define CLK_LEDC 122 -#define CLK_BUS_LEDC 123 -#define CLK_CSI_TOP 124 -#define CLK_CSI_MCLK 125 -#define CLK_BUS_CSI 126 -#define CLK_TPADC 127 -#define CLK_BUS_TPADC 128 -#define CLK_BUS_TZMA 129 -#define CLK_DSP 130 -#define CLK_BUS_DSP_CFG 131 -#define CLK_RISCV 132 -#define CLK_RISCV_AXI 133 -#define CLK_BUS_RISCV_CFG 134 -#define CLK_FANOUT_24M 135 -#define CLK_FANOUT_12M 136 -#define CLK_FANOUT_16M 137 -#define CLK_FANOUT_25M 138 -#define CLK_FANOUT_32K 139 -#define CLK_FANOUT_27M 140 -#define CLK_FANOUT_PCLK 141 -#define CLK_FANOUT0 142 -#define CLK_FANOUT1 143 -#define CLK_FANOUT2 144 -#define CLK_BUS_CAN0 145 -#define CLK_BUS_CAN1 146 - -#endif /* _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_ */ diff --git a/include/dt-bindings/clock/sun20i-d1-r-ccu.h b/include/dt-bindings/clock/sun20i-d1-r-ccu.h deleted file mode 100644 index f95c170711e..00000000000 --- a/include/dt-bindings/clock/sun20i-d1-r-ccu.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * Copyright (C) 2021 Samuel Holland <samuel@sholland.org> - */ - -#ifndef _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_ -#define _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_ - -#define CLK_R_AHB 0 - -#define CLK_BUS_R_TIMER 2 -#define CLK_BUS_R_TWD 3 -#define CLK_BUS_R_PPU 4 -#define CLK_R_IR_RX 5 -#define CLK_BUS_R_IR_RX 6 -#define CLK_BUS_R_RTC 7 -#define CLK_BUS_R_CPUCFG 8 - -#endif /* _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_ */ diff --git a/include/dt-bindings/clock/sun4i-a10-ccu.h b/include/dt-bindings/clock/sun4i-a10-ccu.h deleted file mode 100644 index e4fa61be5c7..00000000000 --- a/include/dt-bindings/clock/sun4i-a10-ccu.h +++ /dev/null @@ -1,202 +0,0 @@ -/* - * Copyright (C) 2017 Priit Laes <plaes@plaes.org> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLK_SUN4I_A10_H_ -#define _DT_BINDINGS_CLK_SUN4I_A10_H_ - -#define CLK_HOSC 1 -#define CLK_PLL_VIDEO0_2X 9 -#define CLK_PLL_VIDEO1_2X 18 -#define CLK_CPU 20 - -/* AHB Gates */ -#define CLK_AHB_OTG 26 -#define CLK_AHB_EHCI0 27 -#define CLK_AHB_OHCI0 28 -#define CLK_AHB_EHCI1 29 -#define CLK_AHB_OHCI1 30 -#define CLK_AHB_SS 31 -#define CLK_AHB_DMA 32 -#define CLK_AHB_BIST 33 -#define CLK_AHB_MMC0 34 -#define CLK_AHB_MMC1 35 -#define CLK_AHB_MMC2 36 -#define CLK_AHB_MMC3 37 -#define CLK_AHB_MS 38 -#define CLK_AHB_NAND 39 -#define CLK_AHB_SDRAM 40 -#define CLK_AHB_ACE 41 -#define CLK_AHB_EMAC 42 -#define CLK_AHB_TS 43 -#define CLK_AHB_SPI0 44 -#define CLK_AHB_SPI1 45 -#define CLK_AHB_SPI2 46 -#define CLK_AHB_SPI3 47 -#define CLK_AHB_PATA 48 -#define CLK_AHB_SATA 49 -#define CLK_AHB_GPS 50 -#define CLK_AHB_HSTIMER 51 -#define CLK_AHB_VE 52 -#define CLK_AHB_TVD 53 -#define CLK_AHB_TVE0 54 -#define CLK_AHB_TVE1 55 -#define CLK_AHB_LCD0 56 -#define CLK_AHB_LCD1 57 -#define CLK_AHB_CSI0 58 -#define CLK_AHB_CSI1 59 -#define CLK_AHB_HDMI0 60 -#define CLK_AHB_HDMI1 61 -#define CLK_AHB_DE_BE0 62 -#define CLK_AHB_DE_BE1 63 -#define CLK_AHB_DE_FE0 64 -#define CLK_AHB_DE_FE1 65 -#define CLK_AHB_GMAC 66 -#define CLK_AHB_MP 67 -#define CLK_AHB_GPU 68 - -/* APB0 Gates */ -#define CLK_APB0_CODEC 69 -#define CLK_APB0_SPDIF 70 -#define CLK_APB0_I2S0 71 -#define CLK_APB0_AC97 72 -#define CLK_APB0_I2S1 73 -#define CLK_APB0_PIO 74 -#define CLK_APB0_IR0 75 -#define CLK_APB0_IR1 76 -#define CLK_APB0_I2S2 77 -#define CLK_APB0_KEYPAD 78 - -/* APB1 Gates */ -#define CLK_APB1_I2C0 79 -#define CLK_APB1_I2C1 80 -#define CLK_APB1_I2C2 81 -#define CLK_APB1_I2C3 82 -#define CLK_APB1_CAN 83 -#define CLK_APB1_SCR 84 -#define CLK_APB1_PS20 85 -#define CLK_APB1_PS21 86 -#define CLK_APB1_I2C4 87 -#define CLK_APB1_UART0 88 -#define CLK_APB1_UART1 89 -#define CLK_APB1_UART2 90 -#define CLK_APB1_UART3 91 -#define CLK_APB1_UART4 92 -#define CLK_APB1_UART5 93 -#define CLK_APB1_UART6 94 -#define CLK_APB1_UART7 95 - -/* IP clocks */ -#define CLK_NAND 96 -#define CLK_MS 97 -#define CLK_MMC0 98 -#define CLK_MMC0_OUTPUT 99 -#define CLK_MMC0_SAMPLE 100 -#define CLK_MMC1 101 -#define CLK_MMC1_OUTPUT 102 -#define CLK_MMC1_SAMPLE 103 -#define CLK_MMC2 104 -#define CLK_MMC2_OUTPUT 105 -#define CLK_MMC2_SAMPLE 106 -#define CLK_MMC3 107 -#define CLK_MMC3_OUTPUT 108 -#define CLK_MMC3_SAMPLE 109 -#define CLK_TS 110 -#define CLK_SS 111 -#define CLK_SPI0 112 -#define CLK_SPI1 113 -#define CLK_SPI2 114 -#define CLK_PATA 115 -#define CLK_IR0 116 -#define CLK_IR1 117 -#define CLK_I2S0 118 -#define CLK_AC97 119 -#define CLK_SPDIF 120 -#define CLK_KEYPAD 121 -#define CLK_SATA 122 -#define CLK_USB_OHCI0 123 -#define CLK_USB_OHCI1 124 -#define CLK_USB_PHY 125 -#define CLK_GPS 126 -#define CLK_SPI3 127 -#define CLK_I2S1 128 -#define CLK_I2S2 129 - -/* DRAM Gates */ -#define CLK_DRAM_VE 130 -#define CLK_DRAM_CSI0 131 -#define CLK_DRAM_CSI1 132 -#define CLK_DRAM_TS 133 -#define CLK_DRAM_TVD 134 -#define CLK_DRAM_TVE0 135 -#define CLK_DRAM_TVE1 136 -#define CLK_DRAM_OUT 137 -#define CLK_DRAM_DE_FE1 138 -#define CLK_DRAM_DE_FE0 139 -#define CLK_DRAM_DE_BE0 140 -#define CLK_DRAM_DE_BE1 141 -#define CLK_DRAM_MP 142 -#define CLK_DRAM_ACE 143 - -/* Display Engine Clocks */ -#define CLK_DE_BE0 144 -#define CLK_DE_BE1 145 -#define CLK_DE_FE0 146 -#define CLK_DE_FE1 147 -#define CLK_DE_MP 148 -#define CLK_TCON0_CH0 149 -#define CLK_TCON1_CH0 150 -#define CLK_CSI_SCLK 151 -#define CLK_TVD_SCLK2 152 -#define CLK_TVD 153 -#define CLK_TCON0_CH1_SCLK2 154 -#define CLK_TCON0_CH1 155 -#define CLK_TCON1_CH1_SCLK2 156 -#define CLK_TCON1_CH1 157 -#define CLK_CSI0 158 -#define CLK_CSI1 159 -#define CLK_CODEC 160 -#define CLK_VE 161 -#define CLK_AVS 162 -#define CLK_ACE 163 -#define CLK_HDMI 164 -#define CLK_GPU 165 - -#endif /* _DT_BINDINGS_CLK_SUN4I_A10_H_ */ diff --git a/include/dt-bindings/clock/sun4i-a10-pll2.h b/include/dt-bindings/clock/sun4i-a10-pll2.h deleted file mode 100644 index 071c8112d53..00000000000 --- a/include/dt-bindings/clock/sun4i-a10-pll2.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright 2015 Maxime Ripard - * - * Maxime Ripard <maxime.ripard@free-electrons.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef __DT_BINDINGS_CLOCK_SUN4I_A10_PLL2_H_ -#define __DT_BINDINGS_CLOCK_SUN4I_A10_PLL2_H_ - -#define SUN4I_A10_PLL2_1X 0 -#define SUN4I_A10_PLL2_2X 1 -#define SUN4I_A10_PLL2_4X 2 -#define SUN4I_A10_PLL2_8X 3 - -#endif /* __DT_BINDINGS_CLOCK_SUN4I_A10_PLL2_H_ */ diff --git a/include/dt-bindings/clock/sun50i-a64-ccu.h b/include/dt-bindings/clock/sun50i-a64-ccu.h deleted file mode 100644 index 175892189e9..00000000000 --- a/include/dt-bindings/clock/sun50i-a64-ccu.h +++ /dev/null @@ -1,138 +0,0 @@ -/* - * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLK_SUN50I_A64_H_ -#define _DT_BINDINGS_CLK_SUN50I_A64_H_ - -#define CLK_PLL_VIDEO0 7 -#define CLK_PLL_PERIPH0 11 - -#define CLK_CPUX 21 -#define CLK_BUS_MIPI_DSI 28 -#define CLK_BUS_CE 29 -#define CLK_BUS_DMA 30 -#define CLK_BUS_MMC0 31 -#define CLK_BUS_MMC1 32 -#define CLK_BUS_MMC2 33 -#define CLK_BUS_NAND 34 -#define CLK_BUS_DRAM 35 -#define CLK_BUS_EMAC 36 -#define CLK_BUS_TS 37 -#define CLK_BUS_HSTIMER 38 -#define CLK_BUS_SPI0 39 -#define CLK_BUS_SPI1 40 -#define CLK_BUS_OTG 41 -#define CLK_BUS_EHCI0 42 -#define CLK_BUS_EHCI1 43 -#define CLK_BUS_OHCI0 44 -#define CLK_BUS_OHCI1 45 -#define CLK_BUS_VE 46 -#define CLK_BUS_TCON0 47 -#define CLK_BUS_TCON1 48 -#define CLK_BUS_DEINTERLACE 49 -#define CLK_BUS_CSI 50 -#define CLK_BUS_HDMI 51 -#define CLK_BUS_DE 52 -#define CLK_BUS_GPU 53 -#define CLK_BUS_MSGBOX 54 -#define CLK_BUS_SPINLOCK 55 -#define CLK_BUS_CODEC 56 -#define CLK_BUS_SPDIF 57 -#define CLK_BUS_PIO 58 -#define CLK_BUS_THS 59 -#define CLK_BUS_I2S0 60 -#define CLK_BUS_I2S1 61 -#define CLK_BUS_I2S2 62 -#define CLK_BUS_I2C0 63 -#define CLK_BUS_I2C1 64 -#define CLK_BUS_I2C2 65 -#define CLK_BUS_SCR 66 -#define CLK_BUS_UART0 67 -#define CLK_BUS_UART1 68 -#define CLK_BUS_UART2 69 -#define CLK_BUS_UART3 70 -#define CLK_BUS_UART4 71 -#define CLK_BUS_DBG 72 -#define CLK_THS 73 -#define CLK_NAND 74 -#define CLK_MMC0 75 -#define CLK_MMC1 76 -#define CLK_MMC2 77 -#define CLK_TS 78 -#define CLK_CE 79 -#define CLK_SPI0 80 -#define CLK_SPI1 81 -#define CLK_I2S0 82 -#define CLK_I2S1 83 -#define CLK_I2S2 84 -#define CLK_SPDIF 85 -#define CLK_USB_PHY0 86 -#define CLK_USB_PHY1 87 -#define CLK_USB_HSIC 88 -#define CLK_USB_HSIC_12M 89 - -#define CLK_USB_OHCI0 91 - -#define CLK_USB_OHCI1 93 -#define CLK_DRAM 94 -#define CLK_DRAM_VE 95 -#define CLK_DRAM_CSI 96 -#define CLK_DRAM_DEINTERLACE 97 -#define CLK_DRAM_TS 98 -#define CLK_DE 99 -#define CLK_TCON0 100 -#define CLK_TCON1 101 -#define CLK_DEINTERLACE 102 -#define CLK_CSI_MISC 103 -#define CLK_CSI_SCLK 104 -#define CLK_CSI_MCLK 105 -#define CLK_VE 106 -#define CLK_AC_DIG 107 -#define CLK_AC_DIG_4X 108 -#define CLK_AVS 109 -#define CLK_HDMI 110 -#define CLK_HDMI_DDC 111 -#define CLK_MBUS 112 -#define CLK_DSI_DPHY 113 -#define CLK_GPU 114 - -#endif /* _DT_BINDINGS_CLK_SUN50I_H_ */ diff --git a/include/dt-bindings/clock/sun50i-h6-ccu.h b/include/dt-bindings/clock/sun50i-h6-ccu.h deleted file mode 100644 index ef9123d8193..00000000000 --- a/include/dt-bindings/clock/sun50i-h6-ccu.h +++ /dev/null @@ -1,125 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> - */ - -#ifndef _DT_BINDINGS_CLK_SUN50I_H6_H_ -#define _DT_BINDINGS_CLK_SUN50I_H6_H_ - -#define CLK_PLL_PERIPH0 3 - -#define CLK_CPUX 21 - -#define CLK_APB1 26 - -#define CLK_DE 29 -#define CLK_BUS_DE 30 -#define CLK_DEINTERLACE 31 -#define CLK_BUS_DEINTERLACE 32 -#define CLK_GPU 33 -#define CLK_BUS_GPU 34 -#define CLK_CE 35 -#define CLK_BUS_CE 36 -#define CLK_VE 37 -#define CLK_BUS_VE 38 -#define CLK_EMCE 39 -#define CLK_BUS_EMCE 40 -#define CLK_VP9 41 -#define CLK_BUS_VP9 42 -#define CLK_BUS_DMA 43 -#define CLK_BUS_MSGBOX 44 -#define CLK_BUS_SPINLOCK 45 -#define CLK_BUS_HSTIMER 46 -#define CLK_AVS 47 -#define CLK_BUS_DBG 48 -#define CLK_BUS_PSI 49 -#define CLK_BUS_PWM 50 -#define CLK_BUS_IOMMU 51 - -#define CLK_MBUS_DMA 53 -#define CLK_MBUS_VE 54 -#define CLK_MBUS_CE 55 -#define CLK_MBUS_TS 56 -#define CLK_MBUS_NAND 57 -#define CLK_MBUS_CSI 58 -#define CLK_MBUS_DEINTERLACE 59 - -#define CLK_NAND0 61 -#define CLK_NAND1 62 -#define CLK_BUS_NAND 63 -#define CLK_MMC0 64 -#define CLK_MMC1 65 -#define CLK_MMC2 66 -#define CLK_BUS_MMC0 67 -#define CLK_BUS_MMC1 68 -#define CLK_BUS_MMC2 69 -#define CLK_BUS_UART0 70 -#define CLK_BUS_UART1 71 -#define CLK_BUS_UART2 72 -#define CLK_BUS_UART3 73 -#define CLK_BUS_I2C0 74 -#define CLK_BUS_I2C1 75 -#define CLK_BUS_I2C2 76 -#define CLK_BUS_I2C3 77 -#define CLK_BUS_SCR0 78 -#define CLK_BUS_SCR1 79 -#define CLK_SPI0 80 -#define CLK_SPI1 81 -#define CLK_BUS_SPI0 82 -#define CLK_BUS_SPI1 83 -#define CLK_BUS_EMAC 84 -#define CLK_TS 85 -#define CLK_BUS_TS 86 -#define CLK_IR_TX 87 -#define CLK_BUS_IR_TX 88 -#define CLK_BUS_THS 89 -#define CLK_I2S3 90 -#define CLK_I2S0 91 -#define CLK_I2S1 92 -#define CLK_I2S2 93 -#define CLK_BUS_I2S0 94 -#define CLK_BUS_I2S1 95 -#define CLK_BUS_I2S2 96 -#define CLK_BUS_I2S3 97 -#define CLK_SPDIF 98 -#define CLK_BUS_SPDIF 99 -#define CLK_DMIC 100 -#define CLK_BUS_DMIC 101 -#define CLK_AUDIO_HUB 102 -#define CLK_BUS_AUDIO_HUB 103 -#define CLK_USB_OHCI0 104 -#define CLK_USB_PHY0 105 -#define CLK_USB_PHY1 106 -#define CLK_USB_OHCI3 107 -#define CLK_USB_PHY3 108 -#define CLK_USB_HSIC_12M 109 -#define CLK_USB_HSIC 110 -#define CLK_BUS_OHCI0 111 -#define CLK_BUS_OHCI3 112 -#define CLK_BUS_EHCI0 113 -#define CLK_BUS_XHCI 114 -#define CLK_BUS_EHCI3 115 -#define CLK_BUS_OTG 116 -#define CLK_PCIE_REF_100M 117 -#define CLK_PCIE_REF 118 -#define CLK_PCIE_REF_OUT 119 -#define CLK_PCIE_MAXI 120 -#define CLK_PCIE_AUX 121 -#define CLK_BUS_PCIE 122 -#define CLK_HDMI 123 -#define CLK_HDMI_SLOW 124 -#define CLK_HDMI_CEC 125 -#define CLK_BUS_HDMI 126 -#define CLK_BUS_TCON_TOP 127 -#define CLK_TCON_LCD0 128 -#define CLK_BUS_TCON_LCD0 129 -#define CLK_TCON_TV0 130 -#define CLK_BUS_TCON_TV0 131 -#define CLK_CSI_CCI 132 -#define CLK_CSI_TOP 133 -#define CLK_CSI_MCLK 134 -#define CLK_BUS_CSI 135 -#define CLK_HDCP 136 -#define CLK_BUS_HDCP 137 - -#endif /* _DT_BINDINGS_CLK_SUN50I_H6_H_ */ diff --git a/include/dt-bindings/clock/sun50i-h6-r-ccu.h b/include/dt-bindings/clock/sun50i-h6-r-ccu.h deleted file mode 100644 index a96087abc86..00000000000 --- a/include/dt-bindings/clock/sun50i-h6-r-ccu.h +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.xyz> - */ - -#ifndef _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ -#define _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ - -#define CLK_AR100 0 - -#define CLK_R_APB1 2 - -#define CLK_R_APB1_TIMER 4 -#define CLK_R_APB1_TWD 5 -#define CLK_R_APB1_PWM 6 -#define CLK_R_APB2_UART 7 -#define CLK_R_APB2_I2C 8 -#define CLK_R_APB1_IR 9 -#define CLK_R_APB1_W1 10 - -#define CLK_IR 11 -#define CLK_W1 12 - -#define CLK_R_APB2_RSB 13 -#define CLK_R_APB1_RTC 14 - -#endif /* _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ */ diff --git a/include/dt-bindings/clock/sun5i-ccu.h b/include/dt-bindings/clock/sun5i-ccu.h deleted file mode 100644 index 75fe5619c3d..00000000000 --- a/include/dt-bindings/clock/sun5i-ccu.h +++ /dev/null @@ -1,97 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright 2016 Maxime Ripard - * - * Maxime Ripard <maxime.ripard@free-electrons.com> - */ - -#ifndef _DT_BINDINGS_CLK_SUN5I_H_ -#define _DT_BINDINGS_CLK_SUN5I_H_ - -#define CLK_HOSC 1 - -#define CLK_PLL_VIDEO0_2X 9 - -#define CLK_PLL_VIDEO1_2X 16 -#define CLK_CPU 17 - -#define CLK_AHB_OTG 23 -#define CLK_AHB_EHCI 24 -#define CLK_AHB_OHCI 25 -#define CLK_AHB_SS 26 -#define CLK_AHB_DMA 27 -#define CLK_AHB_BIST 28 -#define CLK_AHB_MMC0 29 -#define CLK_AHB_MMC1 30 -#define CLK_AHB_MMC2 31 -#define CLK_AHB_NAND 32 -#define CLK_AHB_SDRAM 33 -#define CLK_AHB_EMAC 34 -#define CLK_AHB_TS 35 -#define CLK_AHB_SPI0 36 -#define CLK_AHB_SPI1 37 -#define CLK_AHB_SPI2 38 -#define CLK_AHB_GPS 39 -#define CLK_AHB_HSTIMER 40 -#define CLK_AHB_VE 41 -#define CLK_AHB_TVE 42 -#define CLK_AHB_LCD 43 -#define CLK_AHB_CSI 44 -#define CLK_AHB_HDMI 45 -#define CLK_AHB_DE_BE 46 -#define CLK_AHB_DE_FE 47 -#define CLK_AHB_IEP 48 -#define CLK_AHB_GPU 49 -#define CLK_APB0_CODEC 50 -#define CLK_APB0_SPDIF 51 -#define CLK_APB0_I2S 52 -#define CLK_APB0_PIO 53 -#define CLK_APB0_IR 54 -#define CLK_APB0_KEYPAD 55 -#define CLK_APB1_I2C0 56 -#define CLK_APB1_I2C1 57 -#define CLK_APB1_I2C2 58 -#define CLK_APB1_UART0 59 -#define CLK_APB1_UART1 60 -#define CLK_APB1_UART2 61 -#define CLK_APB1_UART3 62 -#define CLK_NAND 63 -#define CLK_MMC0 64 -#define CLK_MMC1 65 -#define CLK_MMC2 66 -#define CLK_TS 67 -#define CLK_SS 68 -#define CLK_SPI0 69 -#define CLK_SPI1 70 -#define CLK_SPI2 71 -#define CLK_IR 72 -#define CLK_I2S 73 -#define CLK_SPDIF 74 -#define CLK_KEYPAD 75 -#define CLK_USB_OHCI 76 -#define CLK_USB_PHY0 77 -#define CLK_USB_PHY1 78 -#define CLK_GPS 79 -#define CLK_DRAM_VE 80 -#define CLK_DRAM_CSI 81 -#define CLK_DRAM_TS 82 -#define CLK_DRAM_TVE 83 -#define CLK_DRAM_DE_FE 84 -#define CLK_DRAM_DE_BE 85 -#define CLK_DRAM_ACE 86 -#define CLK_DRAM_IEP 87 -#define CLK_DE_BE 88 -#define CLK_DE_FE 89 -#define CLK_TCON_CH0 90 - -#define CLK_TCON_CH1 92 -#define CLK_CSI 93 -#define CLK_VE 94 -#define CLK_CODEC 95 -#define CLK_AVS 96 -#define CLK_HDMI 97 -#define CLK_GPU 98 -#define CLK_MBUS 99 -#define CLK_IEP 100 - -#endif /* _DT_BINDINGS_CLK_SUN5I_H_ */ diff --git a/include/dt-bindings/clock/sun6i-a31-ccu.h b/include/dt-bindings/clock/sun6i-a31-ccu.h deleted file mode 100644 index 39878d9dce9..00000000000 --- a/include/dt-bindings/clock/sun6i-a31-ccu.h +++ /dev/null @@ -1,193 +0,0 @@ -/* - * Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLK_SUN6I_A31_H_ -#define _DT_BINDINGS_CLK_SUN6I_A31_H_ - -#define CLK_PLL_VIDEO0_2X 7 - -#define CLK_PLL_PERIPH 10 - -#define CLK_PLL_VIDEO1_2X 13 - -#define CLK_PLL_MIPI 15 - -#define CLK_CPU 18 - -#define CLK_AHB1_MIPIDSI 23 -#define CLK_AHB1_SS 24 -#define CLK_AHB1_DMA 25 -#define CLK_AHB1_MMC0 26 -#define CLK_AHB1_MMC1 27 -#define CLK_AHB1_MMC2 28 -#define CLK_AHB1_MMC3 29 -#define CLK_AHB1_NAND1 30 -#define CLK_AHB1_NAND0 31 -#define CLK_AHB1_SDRAM 32 -#define CLK_AHB1_EMAC 33 -#define CLK_AHB1_TS 34 -#define CLK_AHB1_HSTIMER 35 -#define CLK_AHB1_SPI0 36 -#define CLK_AHB1_SPI1 37 -#define CLK_AHB1_SPI2 38 -#define CLK_AHB1_SPI3 39 -#define CLK_AHB1_OTG 40 -#define CLK_AHB1_EHCI0 41 -#define CLK_AHB1_EHCI1 42 -#define CLK_AHB1_OHCI0 43 -#define CLK_AHB1_OHCI1 44 -#define CLK_AHB1_OHCI2 45 -#define CLK_AHB1_VE 46 -#define CLK_AHB1_LCD0 47 -#define CLK_AHB1_LCD1 48 -#define CLK_AHB1_CSI 49 -#define CLK_AHB1_HDMI 50 -#define CLK_AHB1_BE0 51 -#define CLK_AHB1_BE1 52 -#define CLK_AHB1_FE0 53 -#define CLK_AHB1_FE1 54 -#define CLK_AHB1_MP 55 -#define CLK_AHB1_GPU 56 -#define CLK_AHB1_DEU0 57 -#define CLK_AHB1_DEU1 58 -#define CLK_AHB1_DRC0 59 -#define CLK_AHB1_DRC1 60 - -#define CLK_APB1_CODEC 61 -#define CLK_APB1_SPDIF 62 -#define CLK_APB1_DIGITAL_MIC 63 -#define CLK_APB1_PIO 64 -#define CLK_APB1_DAUDIO0 65 -#define CLK_APB1_DAUDIO1 66 - -#define CLK_APB2_I2C0 67 -#define CLK_APB2_I2C1 68 -#define CLK_APB2_I2C2 69 -#define CLK_APB2_I2C3 70 -#define CLK_APB2_UART0 71 -#define CLK_APB2_UART1 72 -#define CLK_APB2_UART2 73 -#define CLK_APB2_UART3 74 -#define CLK_APB2_UART4 75 -#define CLK_APB2_UART5 76 - -#define CLK_NAND0 77 -#define CLK_NAND1 78 -#define CLK_MMC0 79 -#define CLK_MMC0_SAMPLE 80 -#define CLK_MMC0_OUTPUT 81 -#define CLK_MMC1 82 -#define CLK_MMC1_SAMPLE 83 -#define CLK_MMC1_OUTPUT 84 -#define CLK_MMC2 85 -#define CLK_MMC2_SAMPLE 86 -#define CLK_MMC2_OUTPUT 87 -#define CLK_MMC3 88 -#define CLK_MMC3_SAMPLE 89 -#define CLK_MMC3_OUTPUT 90 -#define CLK_TS 91 -#define CLK_SS 92 -#define CLK_SPI0 93 -#define CLK_SPI1 94 -#define CLK_SPI2 95 -#define CLK_SPI3 96 -#define CLK_DAUDIO0 97 -#define CLK_DAUDIO1 98 -#define CLK_SPDIF 99 -#define CLK_USB_PHY0 100 -#define CLK_USB_PHY1 101 -#define CLK_USB_PHY2 102 -#define CLK_USB_OHCI0 103 -#define CLK_USB_OHCI1 104 -#define CLK_USB_OHCI2 105 - -#define CLK_DRAM_VE 110 -#define CLK_DRAM_CSI_ISP 111 -#define CLK_DRAM_TS 112 -#define CLK_DRAM_DRC0 113 -#define CLK_DRAM_DRC1 114 -#define CLK_DRAM_DEU0 115 -#define CLK_DRAM_DEU1 116 -#define CLK_DRAM_FE0 117 -#define CLK_DRAM_FE1 118 -#define CLK_DRAM_BE0 119 -#define CLK_DRAM_BE1 120 -#define CLK_DRAM_MP 121 - -#define CLK_BE0 122 -#define CLK_BE1 123 -#define CLK_FE0 124 -#define CLK_FE1 125 -#define CLK_MP 126 -#define CLK_LCD0_CH0 127 -#define CLK_LCD1_CH0 128 -#define CLK_LCD0_CH1 129 -#define CLK_LCD1_CH1 130 -#define CLK_CSI0_SCLK 131 -#define CLK_CSI0_MCLK 132 -#define CLK_CSI1_MCLK 133 -#define CLK_VE 134 -#define CLK_CODEC 135 -#define CLK_AVS 136 -#define CLK_DIGITAL_MIC 137 -#define CLK_HDMI 138 -#define CLK_HDMI_DDC 139 -#define CLK_PS 140 - -#define CLK_MIPI_DSI 143 -#define CLK_MIPI_DSI_DPHY 144 -#define CLK_MIPI_CSI_DPHY 145 -#define CLK_IEP_DRC0 146 -#define CLK_IEP_DRC1 147 -#define CLK_IEP_DEU0 148 -#define CLK_IEP_DEU1 149 -#define CLK_GPU_CORE 150 -#define CLK_GPU_MEMORY 151 -#define CLK_GPU_HYD 152 -#define CLK_ATS 153 -#define CLK_TRACE 154 - -#define CLK_OUT_A 155 -#define CLK_OUT_B 156 -#define CLK_OUT_C 157 - -#endif /* _DT_BINDINGS_CLK_SUN6I_A31_H_ */ diff --git a/include/dt-bindings/clock/sun6i-rtc.h b/include/dt-bindings/clock/sun6i-rtc.h deleted file mode 100644 index 3bd3aa3d57c..00000000000 --- a/include/dt-bindings/clock/sun6i-rtc.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ - -#ifndef _DT_BINDINGS_CLK_SUN6I_RTC_H_ -#define _DT_BINDINGS_CLK_SUN6I_RTC_H_ - -#define CLK_OSC32K 0 -#define CLK_OSC32K_FANOUT 1 -#define CLK_IOSC 2 - -#endif /* _DT_BINDINGS_CLK_SUN6I_RTC_H_ */ diff --git a/include/dt-bindings/clock/sun7i-a20-ccu.h b/include/dt-bindings/clock/sun7i-a20-ccu.h deleted file mode 100644 index 045a5178da0..00000000000 --- a/include/dt-bindings/clock/sun7i-a20-ccu.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (C) 2017 Priit Laes <plaes@plaes.org> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLK_SUN7I_A20_H_ -#define _DT_BINDINGS_CLK_SUN7I_A20_H_ - -#include <dt-bindings/clock/sun4i-a10-ccu.h> - -#define CLK_MBUS 166 -#define CLK_HDMI1_SLOW 167 -#define CLK_HDMI1 168 -#define CLK_OUT_A 169 -#define CLK_OUT_B 170 - -#endif /* _DT_BINDINGS_CLK_SUN7I_A20_H_ */ diff --git a/include/dt-bindings/clock/sun8i-a23-a33-ccu.h b/include/dt-bindings/clock/sun8i-a23-a33-ccu.h deleted file mode 100644 index eb524d0bbd0..00000000000 --- a/include/dt-bindings/clock/sun8i-a23-a33-ccu.h +++ /dev/null @@ -1,129 +0,0 @@ -/* - * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLK_SUN8I_A23_A33_H_ -#define _DT_BINDINGS_CLK_SUN8I_A23_A33_H_ - -#define CLK_PLL_MIPI 13 - -#define CLK_CPUX 18 - -#define CLK_BUS_MIPI_DSI 23 -#define CLK_BUS_SS 24 -#define CLK_BUS_DMA 25 -#define CLK_BUS_MMC0 26 -#define CLK_BUS_MMC1 27 -#define CLK_BUS_MMC2 28 -#define CLK_BUS_NAND 29 -#define CLK_BUS_DRAM 30 -#define CLK_BUS_HSTIMER 31 -#define CLK_BUS_SPI0 32 -#define CLK_BUS_SPI1 33 -#define CLK_BUS_OTG 34 -#define CLK_BUS_EHCI 35 -#define CLK_BUS_OHCI 36 -#define CLK_BUS_VE 37 -#define CLK_BUS_LCD 38 -#define CLK_BUS_CSI 39 -#define CLK_BUS_DE_BE 40 -#define CLK_BUS_DE_FE 41 -#define CLK_BUS_GPU 42 -#define CLK_BUS_MSGBOX 43 -#define CLK_BUS_SPINLOCK 44 -#define CLK_BUS_DRC 45 -#define CLK_BUS_SAT 46 -#define CLK_BUS_CODEC 47 -#define CLK_BUS_PIO 48 -#define CLK_BUS_I2S0 49 -#define CLK_BUS_I2S1 50 -#define CLK_BUS_I2C0 51 -#define CLK_BUS_I2C1 52 -#define CLK_BUS_I2C2 53 -#define CLK_BUS_UART0 54 -#define CLK_BUS_UART1 55 -#define CLK_BUS_UART2 56 -#define CLK_BUS_UART3 57 -#define CLK_BUS_UART4 58 -#define CLK_NAND 59 -#define CLK_MMC0 60 -#define CLK_MMC0_SAMPLE 61 -#define CLK_MMC0_OUTPUT 62 -#define CLK_MMC1 63 -#define CLK_MMC1_SAMPLE 64 -#define CLK_MMC1_OUTPUT 65 -#define CLK_MMC2 66 -#define CLK_MMC2_SAMPLE 67 -#define CLK_MMC2_OUTPUT 68 -#define CLK_SS 69 -#define CLK_SPI0 70 -#define CLK_SPI1 71 -#define CLK_I2S0 72 -#define CLK_I2S1 73 -#define CLK_USB_PHY0 74 -#define CLK_USB_PHY1 75 -#define CLK_USB_HSIC 76 -#define CLK_USB_HSIC_12M 77 -#define CLK_USB_OHCI 78 - -#define CLK_DRAM_VE 80 -#define CLK_DRAM_CSI 81 -#define CLK_DRAM_DRC 82 -#define CLK_DRAM_DE_FE 83 -#define CLK_DRAM_DE_BE 84 -#define CLK_DE_BE 85 -#define CLK_DE_FE 86 -#define CLK_LCD_CH0 87 -#define CLK_LCD_CH1 88 -#define CLK_CSI_SCLK 89 -#define CLK_CSI_MCLK 90 -#define CLK_VE 91 -#define CLK_AC_DIG 92 -#define CLK_AC_DIG_4X 93 -#define CLK_AVS 94 - -#define CLK_DSI_SCLK 96 -#define CLK_DSI_DPHY 97 -#define CLK_DRC 98 -#define CLK_GPU 99 -#define CLK_ATS 100 - -#endif /* _DT_BINDINGS_CLK_SUN8I_A23_A33_H_ */ diff --git a/include/dt-bindings/clock/sun8i-a83t-ccu.h b/include/dt-bindings/clock/sun8i-a83t-ccu.h deleted file mode 100644 index 78af5085f63..00000000000 --- a/include/dt-bindings/clock/sun8i-a83t-ccu.h +++ /dev/null @@ -1,140 +0,0 @@ -/* - * Copyright (C) 2017 Chen-Yu Tsai <wens@csie.org> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLOCK_SUN8I_A83T_CCU_H_ -#define _DT_BINDINGS_CLOCK_SUN8I_A83T_CCU_H_ - -#define CLK_PLL_PERIPH 6 - -#define CLK_PLL_DE 9 - -#define CLK_C0CPUX 11 -#define CLK_C1CPUX 12 - -#define CLK_BUS_MIPI_DSI 19 -#define CLK_BUS_SS 20 -#define CLK_BUS_DMA 21 -#define CLK_BUS_MMC0 22 -#define CLK_BUS_MMC1 23 -#define CLK_BUS_MMC2 24 -#define CLK_BUS_NAND 25 -#define CLK_BUS_DRAM 26 -#define CLK_BUS_EMAC 27 -#define CLK_BUS_HSTIMER 28 -#define CLK_BUS_SPI0 29 -#define CLK_BUS_SPI1 30 -#define CLK_BUS_OTG 31 -#define CLK_BUS_EHCI0 32 -#define CLK_BUS_EHCI1 33 -#define CLK_BUS_OHCI0 34 - -#define CLK_BUS_VE 35 -#define CLK_BUS_TCON0 36 -#define CLK_BUS_TCON1 37 -#define CLK_BUS_CSI 38 -#define CLK_BUS_HDMI 39 -#define CLK_BUS_DE 40 -#define CLK_BUS_GPU 41 -#define CLK_BUS_MSGBOX 42 -#define CLK_BUS_SPINLOCK 43 - -#define CLK_BUS_SPDIF 44 -#define CLK_BUS_PIO 45 -#define CLK_BUS_I2S0 46 -#define CLK_BUS_I2S1 47 -#define CLK_BUS_I2S2 48 -#define CLK_BUS_TDM 49 - -#define CLK_BUS_I2C0 50 -#define CLK_BUS_I2C1 51 -#define CLK_BUS_I2C2 52 -#define CLK_BUS_UART0 53 -#define CLK_BUS_UART1 54 -#define CLK_BUS_UART2 55 -#define CLK_BUS_UART3 56 -#define CLK_BUS_UART4 57 - -#define CLK_NAND 59 -#define CLK_MMC0 60 -#define CLK_MMC0_SAMPLE 61 -#define CLK_MMC0_OUTPUT 62 -#define CLK_MMC1 63 -#define CLK_MMC1_SAMPLE 64 -#define CLK_MMC1_OUTPUT 65 -#define CLK_MMC2 66 -#define CLK_MMC2_SAMPLE 67 -#define CLK_MMC2_OUTPUT 68 -#define CLK_SS 69 -#define CLK_SPI0 70 -#define CLK_SPI1 71 -#define CLK_I2S0 72 -#define CLK_I2S1 73 -#define CLK_I2S2 74 -#define CLK_TDM 75 -#define CLK_SPDIF 76 -#define CLK_USB_PHY0 77 -#define CLK_USB_PHY1 78 -#define CLK_USB_HSIC 79 -#define CLK_USB_HSIC_12M 80 -#define CLK_USB_OHCI0 81 - -#define CLK_DRAM_VE 83 -#define CLK_DRAM_CSI 84 - -#define CLK_TCON0 85 -#define CLK_TCON1 86 -#define CLK_CSI_MISC 87 -#define CLK_MIPI_CSI 88 -#define CLK_CSI_MCLK 89 -#define CLK_CSI_SCLK 90 -#define CLK_VE 91 -#define CLK_AVS 92 -#define CLK_HDMI 93 -#define CLK_HDMI_SLOW 94 - -#define CLK_MIPI_DSI0 96 -#define CLK_MIPI_DSI1 97 -#define CLK_GPU_CORE 98 -#define CLK_GPU_MEMORY 99 -#define CLK_GPU_HYD 100 - -#endif /* _DT_BINDINGS_CLOCK_SUN8I_A83T_CCU_H_ */ diff --git a/include/dt-bindings/clock/sun8i-de2.h b/include/dt-bindings/clock/sun8i-de2.h deleted file mode 100644 index 7768f73b051..00000000000 --- a/include/dt-bindings/clock/sun8i-de2.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.io> - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ - -#ifndef _DT_BINDINGS_CLOCK_SUN8I_DE2_H_ -#define _DT_BINDINGS_CLOCK_SUN8I_DE2_H_ - -#define CLK_BUS_MIXER0 0 -#define CLK_BUS_MIXER1 1 -#define CLK_BUS_WB 2 - -#define CLK_MIXER0 6 -#define CLK_MIXER1 7 -#define CLK_WB 8 - -#define CLK_BUS_ROT 9 -#define CLK_ROT 10 - -#endif /* _DT_BINDINGS_CLOCK_SUN8I_DE2_H_ */ diff --git a/include/dt-bindings/clock/sun8i-h3-ccu.h b/include/dt-bindings/clock/sun8i-h3-ccu.h deleted file mode 100644 index 5d4ada2c22e..00000000000 --- a/include/dt-bindings/clock/sun8i-h3-ccu.h +++ /dev/null @@ -1,152 +0,0 @@ -/* - * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLK_SUN8I_H3_H_ -#define _DT_BINDINGS_CLK_SUN8I_H3_H_ - -#define CLK_PLL_VIDEO 6 - -#define CLK_PLL_PERIPH0 9 - -#define CLK_CPUX 14 - -#define CLK_BUS_CE 20 -#define CLK_BUS_DMA 21 -#define CLK_BUS_MMC0 22 -#define CLK_BUS_MMC1 23 -#define CLK_BUS_MMC2 24 -#define CLK_BUS_NAND 25 -#define CLK_BUS_DRAM 26 -#define CLK_BUS_EMAC 27 -#define CLK_BUS_TS 28 -#define CLK_BUS_HSTIMER 29 -#define CLK_BUS_SPI0 30 -#define CLK_BUS_SPI1 31 -#define CLK_BUS_OTG 32 -#define CLK_BUS_EHCI0 33 -#define CLK_BUS_EHCI1 34 -#define CLK_BUS_EHCI2 35 -#define CLK_BUS_EHCI3 36 -#define CLK_BUS_OHCI0 37 -#define CLK_BUS_OHCI1 38 -#define CLK_BUS_OHCI2 39 -#define CLK_BUS_OHCI3 40 -#define CLK_BUS_VE 41 -#define CLK_BUS_TCON0 42 -#define CLK_BUS_TCON1 43 -#define CLK_BUS_DEINTERLACE 44 -#define CLK_BUS_CSI 45 -#define CLK_BUS_TVE 46 -#define CLK_BUS_HDMI 47 -#define CLK_BUS_DE 48 -#define CLK_BUS_GPU 49 -#define CLK_BUS_MSGBOX 50 -#define CLK_BUS_SPINLOCK 51 -#define CLK_BUS_CODEC 52 -#define CLK_BUS_SPDIF 53 -#define CLK_BUS_PIO 54 -#define CLK_BUS_THS 55 -#define CLK_BUS_I2S0 56 -#define CLK_BUS_I2S1 57 -#define CLK_BUS_I2S2 58 -#define CLK_BUS_I2C0 59 -#define CLK_BUS_I2C1 60 -#define CLK_BUS_I2C2 61 -#define CLK_BUS_UART0 62 -#define CLK_BUS_UART1 63 -#define CLK_BUS_UART2 64 -#define CLK_BUS_UART3 65 -#define CLK_BUS_SCR0 66 -#define CLK_BUS_EPHY 67 -#define CLK_BUS_DBG 68 - -#define CLK_THS 69 -#define CLK_NAND 70 -#define CLK_MMC0 71 -#define CLK_MMC0_SAMPLE 72 -#define CLK_MMC0_OUTPUT 73 -#define CLK_MMC1 74 -#define CLK_MMC1_SAMPLE 75 -#define CLK_MMC1_OUTPUT 76 -#define CLK_MMC2 77 -#define CLK_MMC2_SAMPLE 78 -#define CLK_MMC2_OUTPUT 79 -#define CLK_TS 80 -#define CLK_CE 81 -#define CLK_SPI0 82 -#define CLK_SPI1 83 -#define CLK_I2S0 84 -#define CLK_I2S1 85 -#define CLK_I2S2 86 -#define CLK_SPDIF 87 -#define CLK_USB_PHY0 88 -#define CLK_USB_PHY1 89 -#define CLK_USB_PHY2 90 -#define CLK_USB_PHY3 91 -#define CLK_USB_OHCI0 92 -#define CLK_USB_OHCI1 93 -#define CLK_USB_OHCI2 94 -#define CLK_USB_OHCI3 95 -#define CLK_DRAM 96 -#define CLK_DRAM_VE 97 -#define CLK_DRAM_CSI 98 -#define CLK_DRAM_DEINTERLACE 99 -#define CLK_DRAM_TS 100 -#define CLK_DE 101 -#define CLK_TCON0 102 -#define CLK_TVE 103 -#define CLK_DEINTERLACE 104 -#define CLK_CSI_MISC 105 -#define CLK_CSI_SCLK 106 -#define CLK_CSI_MCLK 107 -#define CLK_VE 108 -#define CLK_AC_DIG 109 -#define CLK_AVS 110 -#define CLK_HDMI 111 -#define CLK_HDMI_DDC 112 -#define CLK_MBUS 113 -#define CLK_GPU 114 - -/* New clocks imported in H5 */ -#define CLK_BUS_SCR1 115 - -#endif /* _DT_BINDINGS_CLK_SUN8I_H3_H_ */ diff --git a/include/dt-bindings/clock/sun8i-r-ccu.h b/include/dt-bindings/clock/sun8i-r-ccu.h deleted file mode 100644 index 779d20aa0d0..00000000000 --- a/include/dt-bindings/clock/sun8i-r-ccu.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLK_SUN8I_R_CCU_H_ -#define _DT_BINDINGS_CLK_SUN8I_R_CCU_H_ - -#define CLK_AR100 0 - -#define CLK_APB0_PIO 3 -#define CLK_APB0_IR 4 -#define CLK_APB0_TIMER 5 -#define CLK_APB0_RSB 6 -#define CLK_APB0_UART 7 -/* 8 is reserved for CLK_APB0_W1 on A31 */ -#define CLK_APB0_I2C 9 -#define CLK_APB0_TWD 10 - -#define CLK_IR 11 - -#endif /* _DT_BINDINGS_CLK_SUN8I_R_CCU_H_ */ diff --git a/include/dt-bindings/clock/sun8i-r40-ccu.h b/include/dt-bindings/clock/sun8i-r40-ccu.h deleted file mode 100644 index d7337b55a4e..00000000000 --- a/include/dt-bindings/clock/sun8i-r40-ccu.h +++ /dev/null @@ -1,191 +0,0 @@ -/* - * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLK_SUN8I_R40_H_ -#define _DT_BINDINGS_CLK_SUN8I_R40_H_ - -#define CLK_PLL_VIDEO0 7 - -#define CLK_PLL_VIDEO1 16 - -#define CLK_CPU 24 - -#define CLK_BUS_MIPI_DSI 29 -#define CLK_BUS_CE 30 -#define CLK_BUS_DMA 31 -#define CLK_BUS_MMC0 32 -#define CLK_BUS_MMC1 33 -#define CLK_BUS_MMC2 34 -#define CLK_BUS_MMC3 35 -#define CLK_BUS_NAND 36 -#define CLK_BUS_DRAM 37 -#define CLK_BUS_EMAC 38 -#define CLK_BUS_TS 39 -#define CLK_BUS_HSTIMER 40 -#define CLK_BUS_SPI0 41 -#define CLK_BUS_SPI1 42 -#define CLK_BUS_SPI2 43 -#define CLK_BUS_SPI3 44 -#define CLK_BUS_SATA 45 -#define CLK_BUS_OTG 46 -#define CLK_BUS_EHCI0 47 -#define CLK_BUS_EHCI1 48 -#define CLK_BUS_EHCI2 49 -#define CLK_BUS_OHCI0 50 -#define CLK_BUS_OHCI1 51 -#define CLK_BUS_OHCI2 52 -#define CLK_BUS_VE 53 -#define CLK_BUS_MP 54 -#define CLK_BUS_DEINTERLACE 55 -#define CLK_BUS_CSI0 56 -#define CLK_BUS_CSI1 57 -#define CLK_BUS_HDMI1 58 -#define CLK_BUS_HDMI0 59 -#define CLK_BUS_DE 60 -#define CLK_BUS_TVE0 61 -#define CLK_BUS_TVE1 62 -#define CLK_BUS_TVE_TOP 63 -#define CLK_BUS_GMAC 64 -#define CLK_BUS_GPU 65 -#define CLK_BUS_TVD0 66 -#define CLK_BUS_TVD1 67 -#define CLK_BUS_TVD2 68 -#define CLK_BUS_TVD3 69 -#define CLK_BUS_TVD_TOP 70 -#define CLK_BUS_TCON_LCD0 71 -#define CLK_BUS_TCON_LCD1 72 -#define CLK_BUS_TCON_TV0 73 -#define CLK_BUS_TCON_TV1 74 -#define CLK_BUS_TCON_TOP 75 -#define CLK_BUS_CODEC 76 -#define CLK_BUS_SPDIF 77 -#define CLK_BUS_AC97 78 -#define CLK_BUS_PIO 79 -#define CLK_BUS_IR0 80 -#define CLK_BUS_IR1 81 -#define CLK_BUS_THS 82 -#define CLK_BUS_KEYPAD 83 -#define CLK_BUS_I2S0 84 -#define CLK_BUS_I2S1 85 -#define CLK_BUS_I2S2 86 -#define CLK_BUS_I2C0 87 -#define CLK_BUS_I2C1 88 -#define CLK_BUS_I2C2 89 -#define CLK_BUS_I2C3 90 -#define CLK_BUS_CAN 91 -#define CLK_BUS_SCR 92 -#define CLK_BUS_PS20 93 -#define CLK_BUS_PS21 94 -#define CLK_BUS_I2C4 95 -#define CLK_BUS_UART0 96 -#define CLK_BUS_UART1 97 -#define CLK_BUS_UART2 98 -#define CLK_BUS_UART3 99 -#define CLK_BUS_UART4 100 -#define CLK_BUS_UART5 101 -#define CLK_BUS_UART6 102 -#define CLK_BUS_UART7 103 -#define CLK_BUS_DBG 104 - -#define CLK_THS 105 -#define CLK_NAND 106 -#define CLK_MMC0 107 -#define CLK_MMC1 108 -#define CLK_MMC2 109 -#define CLK_MMC3 110 -#define CLK_TS 111 -#define CLK_CE 112 -#define CLK_SPI0 113 -#define CLK_SPI1 114 -#define CLK_SPI2 115 -#define CLK_SPI3 116 -#define CLK_I2S0 117 -#define CLK_I2S1 118 -#define CLK_I2S2 119 -#define CLK_AC97 120 -#define CLK_SPDIF 121 -#define CLK_KEYPAD 122 -#define CLK_SATA 123 -#define CLK_USB_PHY0 124 -#define CLK_USB_PHY1 125 -#define CLK_USB_PHY2 126 -#define CLK_USB_OHCI0 127 -#define CLK_USB_OHCI1 128 -#define CLK_USB_OHCI2 129 -#define CLK_IR0 130 -#define CLK_IR1 131 - -#define CLK_DRAM_VE 133 -#define CLK_DRAM_CSI0 134 -#define CLK_DRAM_CSI1 135 -#define CLK_DRAM_TS 136 -#define CLK_DRAM_TVD 137 -#define CLK_DRAM_MP 138 -#define CLK_DRAM_DEINTERLACE 139 -#define CLK_DE 140 -#define CLK_MP 141 -#define CLK_TCON_LCD0 142 -#define CLK_TCON_LCD1 143 -#define CLK_TCON_TV0 144 -#define CLK_TCON_TV1 145 -#define CLK_DEINTERLACE 146 -#define CLK_CSI1_MCLK 147 -#define CLK_CSI_SCLK 148 -#define CLK_CSI0_MCLK 149 -#define CLK_VE 150 -#define CLK_CODEC 151 -#define CLK_AVS 152 -#define CLK_HDMI 153 -#define CLK_HDMI_SLOW 154 -#define CLK_MBUS 155 -#define CLK_DSI_DPHY 156 -#define CLK_TVE0 157 -#define CLK_TVE1 158 -#define CLK_TVD0 159 -#define CLK_TVD1 160 -#define CLK_TVD2 161 -#define CLK_TVD3 162 -#define CLK_GPU 163 -#define CLK_OUTA 164 -#define CLK_OUTB 165 - -#endif /* _DT_BINDINGS_CLK_SUN8I_R40_H_ */ diff --git a/include/dt-bindings/clock/sun8i-tcon-top.h b/include/dt-bindings/clock/sun8i-tcon-top.h deleted file mode 100644 index 25164d76783..00000000000 --- a/include/dt-bindings/clock/sun8i-tcon-top.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* Copyright (C) 2018 Jernej Skrabec <jernej.skrabec@siol.net> */ - -#ifndef _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_ -#define _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_ - -#define CLK_TCON_TOP_TV0 0 -#define CLK_TCON_TOP_TV1 1 -#define CLK_TCON_TOP_DSI 2 - -#endif /* _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_ */ diff --git a/include/dt-bindings/clock/sun8i-v3s-ccu.h b/include/dt-bindings/clock/sun8i-v3s-ccu.h deleted file mode 100644 index 014ac6123d1..00000000000 --- a/include/dt-bindings/clock/sun8i-v3s-ccu.h +++ /dev/null @@ -1,111 +0,0 @@ -/* - * Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz> - * - * Based on sun8i-h3-ccu.h, which is: - * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLK_SUN8I_V3S_H_ -#define _DT_BINDINGS_CLK_SUN8I_V3S_H_ - -#define CLK_CPU 14 - -#define CLK_BUS_CE 20 -#define CLK_BUS_DMA 21 -#define CLK_BUS_MMC0 22 -#define CLK_BUS_MMC1 23 -#define CLK_BUS_MMC2 24 -#define CLK_BUS_DRAM 25 -#define CLK_BUS_EMAC 26 -#define CLK_BUS_HSTIMER 27 -#define CLK_BUS_SPI0 28 -#define CLK_BUS_OTG 29 -#define CLK_BUS_EHCI0 30 -#define CLK_BUS_OHCI0 31 -#define CLK_BUS_VE 32 -#define CLK_BUS_TCON0 33 -#define CLK_BUS_CSI 34 -#define CLK_BUS_DE 35 -#define CLK_BUS_CODEC 36 -#define CLK_BUS_PIO 37 -#define CLK_BUS_I2C0 38 -#define CLK_BUS_I2C1 39 -#define CLK_BUS_UART0 40 -#define CLK_BUS_UART1 41 -#define CLK_BUS_UART2 42 -#define CLK_BUS_EPHY 43 -#define CLK_BUS_DBG 44 - -#define CLK_MMC0 45 -#define CLK_MMC0_SAMPLE 46 -#define CLK_MMC0_OUTPUT 47 -#define CLK_MMC1 48 -#define CLK_MMC1_SAMPLE 49 -#define CLK_MMC1_OUTPUT 50 -#define CLK_MMC2 51 -#define CLK_MMC2_SAMPLE 52 -#define CLK_MMC2_OUTPUT 53 -#define CLK_CE 54 -#define CLK_SPI0 55 -#define CLK_USB_PHY0 56 -#define CLK_USB_OHCI0 57 - -#define CLK_DRAM_VE 59 -#define CLK_DRAM_CSI 60 -#define CLK_DRAM_EHCI 61 -#define CLK_DRAM_OHCI 62 -#define CLK_DE 63 -#define CLK_TCON0 64 -#define CLK_CSI_MISC 65 -#define CLK_CSI0_MCLK 66 -#define CLK_CSI1_SCLK 67 -#define CLK_CSI1_MCLK 68 -#define CLK_VE 69 -#define CLK_AC_DIG 70 -#define CLK_AVS 71 - -#define CLK_MIPI_CSI 73 - -/* Clocks not available on V3s */ -#define CLK_BUS_I2S0 75 -#define CLK_I2S0 76 - -#endif /* _DT_BINDINGS_CLK_SUN8I_V3S_H_ */ diff --git a/include/dt-bindings/clock/sun9i-a80-ccu.h b/include/dt-bindings/clock/sun9i-a80-ccu.h deleted file mode 100644 index 6ea1492a73a..00000000000 --- a/include/dt-bindings/clock/sun9i-a80-ccu.h +++ /dev/null @@ -1,162 +0,0 @@ -/* - * Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLOCK_SUN9I_A80_CCU_H_ -#define _DT_BINDINGS_CLOCK_SUN9I_A80_CCU_H_ - -#define CLK_PLL_AUDIO 2 -#define CLK_PLL_PERIPH0 3 - -#define CLK_C0CPUX 12 -#define CLK_C1CPUX 13 - -#define CLK_OUT_A 27 -#define CLK_OUT_B 28 - -#define CLK_NAND0_0 29 -#define CLK_NAND0_1 30 -#define CLK_NAND1_0 31 -#define CLK_NAND1_1 32 -#define CLK_MMC0 33 -#define CLK_MMC0_SAMPLE 34 -#define CLK_MMC0_OUTPUT 35 -#define CLK_MMC1 36 -#define CLK_MMC1_SAMPLE 37 -#define CLK_MMC1_OUTPUT 38 -#define CLK_MMC2 39 -#define CLK_MMC2_SAMPLE 40 -#define CLK_MMC2_OUTPUT 41 -#define CLK_MMC3 42 -#define CLK_MMC3_SAMPLE 43 -#define CLK_MMC3_OUTPUT 44 -#define CLK_TS 45 -#define CLK_SS 46 -#define CLK_SPI0 47 -#define CLK_SPI1 48 -#define CLK_SPI2 49 -#define CLK_SPI3 50 -#define CLK_I2S0 51 -#define CLK_I2S1 52 -#define CLK_SPDIF 53 -#define CLK_SDRAM 54 -#define CLK_DE 55 -#define CLK_EDP 56 -#define CLK_MP 57 -#define CLK_LCD0 58 -#define CLK_LCD1 59 -#define CLK_MIPI_DSI0 60 -#define CLK_MIPI_DSI1 61 -#define CLK_HDMI 62 -#define CLK_HDMI_SLOW 63 -#define CLK_MIPI_CSI 64 -#define CLK_CSI_ISP 65 -#define CLK_CSI_MISC 66 -#define CLK_CSI0_MCLK 67 -#define CLK_CSI1_MCLK 68 -#define CLK_FD 69 -#define CLK_VE 70 -#define CLK_AVS 71 -#define CLK_GPU_CORE 72 -#define CLK_GPU_MEMORY 73 -#define CLK_GPU_AXI 74 -#define CLK_SATA 75 -#define CLK_AC97 76 -#define CLK_MIPI_HSI 77 -#define CLK_GPADC 78 -#define CLK_CIR_TX 79 - -#define CLK_BUS_FD 80 -#define CLK_BUS_VE 81 -#define CLK_BUS_GPU_CTRL 82 -#define CLK_BUS_SS 83 -#define CLK_BUS_MMC 84 -#define CLK_BUS_NAND0 85 -#define CLK_BUS_NAND1 86 -#define CLK_BUS_SDRAM 87 -#define CLK_BUS_MIPI_HSI 88 -#define CLK_BUS_SATA 89 -#define CLK_BUS_TS 90 -#define CLK_BUS_SPI0 91 -#define CLK_BUS_SPI1 92 -#define CLK_BUS_SPI2 93 -#define CLK_BUS_SPI3 94 - -#define CLK_BUS_OTG 95 -#define CLK_BUS_USB 96 -#define CLK_BUS_GMAC 97 -#define CLK_BUS_MSGBOX 98 -#define CLK_BUS_SPINLOCK 99 -#define CLK_BUS_HSTIMER 100 -#define CLK_BUS_DMA 101 - -#define CLK_BUS_LCD0 102 -#define CLK_BUS_LCD1 103 -#define CLK_BUS_EDP 104 -#define CLK_BUS_CSI 105 -#define CLK_BUS_HDMI 106 -#define CLK_BUS_DE 107 -#define CLK_BUS_MP 108 -#define CLK_BUS_MIPI_DSI 109 - -#define CLK_BUS_SPDIF 110 -#define CLK_BUS_PIO 111 -#define CLK_BUS_AC97 112 -#define CLK_BUS_I2S0 113 -#define CLK_BUS_I2S1 114 -#define CLK_BUS_LRADC 115 -#define CLK_BUS_GPADC 116 -#define CLK_BUS_TWD 117 -#define CLK_BUS_CIR_TX 118 - -#define CLK_BUS_I2C0 119 -#define CLK_BUS_I2C1 120 -#define CLK_BUS_I2C2 121 -#define CLK_BUS_I2C3 122 -#define CLK_BUS_I2C4 123 -#define CLK_BUS_UART0 124 -#define CLK_BUS_UART1 125 -#define CLK_BUS_UART2 126 -#define CLK_BUS_UART3 127 -#define CLK_BUS_UART4 128 -#define CLK_BUS_UART5 129 - -#endif /* _DT_BINDINGS_CLOCK_SUN9I_A80_CCU_H_ */ diff --git a/include/dt-bindings/clock/sun9i-a80-de.h b/include/dt-bindings/clock/sun9i-a80-de.h deleted file mode 100644 index 3dad6c3cd13..00000000000 --- a/include/dt-bindings/clock/sun9i-a80-de.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLOCK_SUN9I_A80_DE_H_ -#define _DT_BINDINGS_CLOCK_SUN9I_A80_DE_H_ - -#define CLK_FE0 0 -#define CLK_FE1 1 -#define CLK_FE2 2 -#define CLK_IEP_DEU0 3 -#define CLK_IEP_DEU1 4 -#define CLK_BE0 5 -#define CLK_BE1 6 -#define CLK_BE2 7 -#define CLK_IEP_DRC0 8 -#define CLK_IEP_DRC1 9 -#define CLK_MERGE 10 - -#define CLK_DRAM_FE0 11 -#define CLK_DRAM_FE1 12 -#define CLK_DRAM_FE2 13 -#define CLK_DRAM_DEU0 14 -#define CLK_DRAM_DEU1 15 -#define CLK_DRAM_BE0 16 -#define CLK_DRAM_BE1 17 -#define CLK_DRAM_BE2 18 -#define CLK_DRAM_DRC0 19 -#define CLK_DRAM_DRC1 20 - -#define CLK_BUS_FE0 21 -#define CLK_BUS_FE1 22 -#define CLK_BUS_FE2 23 -#define CLK_BUS_DEU0 24 -#define CLK_BUS_DEU1 25 -#define CLK_BUS_BE0 26 -#define CLK_BUS_BE1 27 -#define CLK_BUS_BE2 28 -#define CLK_BUS_DRC0 29 -#define CLK_BUS_DRC1 30 - -#endif /* _DT_BINDINGS_CLOCK_SUN9I_A80_DE_H_ */ diff --git a/include/dt-bindings/clock/sun9i-a80-usb.h b/include/dt-bindings/clock/sun9i-a80-usb.h deleted file mode 100644 index 783a60d2cce..00000000000 --- a/include/dt-bindings/clock/sun9i-a80-usb.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLOCK_SUN9I_A80_USB_H_ -#define _DT_BINDINGS_CLOCK_SUN9I_A80_USB_H_ - -#define CLK_BUS_HCI0 0 -#define CLK_USB_OHCI0 1 -#define CLK_BUS_HCI1 2 -#define CLK_BUS_HCI2 3 -#define CLK_USB_OHCI2 4 - -#define CLK_USB0_PHY 5 -#define CLK_USB1_HSIC 6 -#define CLK_USB1_PHY 7 -#define CLK_USB2_HSIC 8 -#define CLK_USB2_PHY 9 -#define CLK_USB_HSIC 10 - -#endif /* _DT_BINDINGS_CLOCK_SUN9I_A80_USB_H_ */ diff --git a/include/dt-bindings/clock/suniv-ccu-f1c100s.h b/include/dt-bindings/clock/suniv-ccu-f1c100s.h deleted file mode 100644 index d7570765f42..00000000000 --- a/include/dt-bindings/clock/suniv-ccu-f1c100s.h +++ /dev/null @@ -1,72 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) - * - * Copyright (c) 2018 Icenowy Zheng <icenowy@aosc.xyz> - * - */ - -#ifndef _DT_BINDINGS_CLK_SUNIV_F1C100S_H_ -#define _DT_BINDINGS_CLK_SUNIV_F1C100S_H_ - -#define CLK_CPU 11 - -#define CLK_BUS_DMA 14 -#define CLK_BUS_MMC0 15 -#define CLK_BUS_MMC1 16 -#define CLK_BUS_DRAM 17 -#define CLK_BUS_SPI0 18 -#define CLK_BUS_SPI1 19 -#define CLK_BUS_OTG 20 -#define CLK_BUS_VE 21 -#define CLK_BUS_LCD 22 -#define CLK_BUS_DEINTERLACE 23 -#define CLK_BUS_CSI 24 -#define CLK_BUS_TVD 25 -#define CLK_BUS_TVE 26 -#define CLK_BUS_DE_BE 27 -#define CLK_BUS_DE_FE 28 -#define CLK_BUS_CODEC 29 -#define CLK_BUS_SPDIF 30 -#define CLK_BUS_IR 31 -#define CLK_BUS_RSB 32 -#define CLK_BUS_I2S0 33 -#define CLK_BUS_I2C0 34 -#define CLK_BUS_I2C1 35 -#define CLK_BUS_I2C2 36 -#define CLK_BUS_PIO 37 -#define CLK_BUS_UART0 38 -#define CLK_BUS_UART1 39 -#define CLK_BUS_UART2 40 - -#define CLK_MMC0 41 -#define CLK_MMC0_SAMPLE 42 -#define CLK_MMC0_OUTPUT 43 -#define CLK_MMC1 44 -#define CLK_MMC1_SAMPLE 45 -#define CLK_MMC1_OUTPUT 46 -#define CLK_I2S 47 -#define CLK_SPDIF 48 - -#define CLK_USB_PHY0 49 - -#define CLK_DRAM_VE 50 -#define CLK_DRAM_CSI 51 -#define CLK_DRAM_DEINTERLACE 52 -#define CLK_DRAM_TVD 53 -#define CLK_DRAM_DE_FE 54 -#define CLK_DRAM_DE_BE 55 - -#define CLK_DE_BE 56 -#define CLK_DE_FE 57 -#define CLK_TCON 58 -#define CLK_DEINTERLACE 59 -#define CLK_TVE2_CLK 60 -#define CLK_TVE1_CLK 61 -#define CLK_TVD 62 -#define CLK_CSI 63 -#define CLK_VE 64 -#define CLK_CODEC 65 -#define CLK_AVS 66 - -#define CLK_IR 67 - -#endif diff --git a/include/dt-bindings/clock/tegra114-car.h b/include/dt-bindings/clock/tegra114-car.h deleted file mode 100644 index 534c03f8ad7..00000000000 --- a/include/dt-bindings/clock/tegra114-car.h +++ /dev/null @@ -1,343 +0,0 @@ -/* - * This header provides constants for binding nvidia,tegra114-car. - * - * The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB - * registers. These IDs often match those in the CAR's RST_DEVICES registers, - * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In - * this case, those clocks are assigned IDs above 160 in order to highlight - * this issue. Implementations that interpret these clock IDs as bit values - * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to - * explicitly handle these special cases. - * - * The balance of the clocks controlled by the CAR are assigned IDs of 160 and - * above. - */ - -#ifndef _DT_BINDINGS_CLOCK_TEGRA114_CAR_H -#define _DT_BINDINGS_CLOCK_TEGRA114_CAR_H - -/* 0 */ -/* 1 */ -/* 2 */ -/* 3 */ -#define TEGRA114_CLK_RTC 4 -#define TEGRA114_CLK_TIMER 5 -#define TEGRA114_CLK_UARTA 6 -/* 7 (register bit affects uartb and vfir) */ -/* 8 */ -#define TEGRA114_CLK_SDMMC2 9 -/* 10 (register bit affects spdif_in and spdif_out) */ -#define TEGRA114_CLK_I2S1 11 -#define TEGRA114_CLK_I2C1 12 -#define TEGRA114_CLK_NDFLASH 13 -#define TEGRA114_CLK_SDMMC1 14 -#define TEGRA114_CLK_SDMMC4 15 -/* 16 */ -#define TEGRA114_CLK_PWM 17 -#define TEGRA114_CLK_I2S2 18 -#define TEGRA114_CLK_EPP 19 -/* 20 (register bit affects vi and vi_sensor) */ -#define TEGRA114_CLK_GR2D 21 -#define TEGRA114_CLK_USBD 22 -#define TEGRA114_CLK_ISP 23 -#define TEGRA114_CLK_GR3D 24 -/* 25 */ -#define TEGRA114_CLK_DISP2 26 -#define TEGRA114_CLK_DISP1 27 -#define TEGRA114_CLK_HOST1X 28 -#define TEGRA114_CLK_VCP 29 -#define TEGRA114_CLK_I2S0 30 -/* 31 */ - -#define TEGRA114_CLK_MC 32 -/* 33 */ -#define TEGRA114_CLK_APBDMA 34 -/* 35 */ -#define TEGRA114_CLK_KBC 36 -/* 37 */ -/* 38 */ -/* 39 (register bit affects fuse and fuse_burn) */ -#define TEGRA114_CLK_KFUSE 40 -#define TEGRA114_CLK_SBC1 41 -#define TEGRA114_CLK_NOR 42 -/* 43 */ -#define TEGRA114_CLK_SBC2 44 -/* 45 */ -#define TEGRA114_CLK_SBC3 46 -#define TEGRA114_CLK_I2C5 47 -#define TEGRA114_CLK_DSIA 48 -/* 49 */ -#define TEGRA114_CLK_MIPI 50 -#define TEGRA114_CLK_HDMI 51 -#define TEGRA114_CLK_CSI 52 -/* 53 */ -#define TEGRA114_CLK_I2C2 54 -#define TEGRA114_CLK_UARTC 55 -#define TEGRA114_CLK_MIPI_CAL 56 -#define TEGRA114_CLK_EMC 57 -#define TEGRA114_CLK_USB2 58 -#define TEGRA114_CLK_USB3 59 -/* 60 */ -#define TEGRA114_CLK_VDE 61 -#define TEGRA114_CLK_BSEA 62 -#define TEGRA114_CLK_BSEV 63 - -/* 64 */ -#define TEGRA114_CLK_UARTD 65 -/* 66 */ -#define TEGRA114_CLK_I2C3 67 -#define TEGRA114_CLK_SBC4 68 -#define TEGRA114_CLK_SDMMC3 69 -/* 70 */ -#define TEGRA114_CLK_OWR 71 -/* 72 */ -#define TEGRA114_CLK_CSITE 73 -/* 74 */ -/* 75 */ -#define TEGRA114_CLK_LA 76 -#define TEGRA114_CLK_TRACE 77 -#define TEGRA114_CLK_SOC_THERM 78 -#define TEGRA114_CLK_DTV 79 -#define TEGRA114_CLK_NDSPEED 80 -#define TEGRA114_CLK_I2CSLOW 81 -#define TEGRA114_CLK_DSIB 82 -#define TEGRA114_CLK_TSEC 83 -/* 84 */ -/* 85 */ -/* 86 */ -/* 87 */ -/* 88 */ -#define TEGRA114_CLK_XUSB_HOST 89 -/* 90 */ -#define TEGRA114_CLK_MSENC 91 -#define TEGRA114_CLK_CSUS 92 -/* 93 */ -/* 94 */ -/* 95 (bit affects xusb_dev and xusb_dev_src) */ - -/* 96 */ -/* 97 */ -/* 98 */ -#define TEGRA114_CLK_MSELECT 99 -#define TEGRA114_CLK_TSENSOR 100 -#define TEGRA114_CLK_I2S3 101 -#define TEGRA114_CLK_I2S4 102 -#define TEGRA114_CLK_I2C4 103 -#define TEGRA114_CLK_SBC5 104 -#define TEGRA114_CLK_SBC6 105 -#define TEGRA114_CLK_D_AUDIO 106 -#define TEGRA114_CLK_APBIF 107 -#define TEGRA114_CLK_DAM0 108 -#define TEGRA114_CLK_DAM1 109 -#define TEGRA114_CLK_DAM2 110 -#define TEGRA114_CLK_HDA2CODEC_2X 111 -/* 112 */ -#define TEGRA114_CLK_AUDIO0_2X 113 -#define TEGRA114_CLK_AUDIO1_2X 114 -#define TEGRA114_CLK_AUDIO2_2X 115 -#define TEGRA114_CLK_AUDIO3_2X 116 -#define TEGRA114_CLK_AUDIO4_2X 117 -#define TEGRA114_CLK_SPDIF_2X 118 -#define TEGRA114_CLK_ACTMON 119 -#define TEGRA114_CLK_EXTERN1 120 -#define TEGRA114_CLK_EXTERN2 121 -#define TEGRA114_CLK_EXTERN3 122 -/* 123 */ -/* 124 */ -#define TEGRA114_CLK_HDA 125 -/* 126 */ -#define TEGRA114_CLK_SE 127 - -#define TEGRA114_CLK_HDA2HDMI 128 -/* 129 */ -/* 130 */ -/* 131 */ -/* 132 */ -/* 133 */ -/* 134 */ -/* 135 */ -/* 136 */ -/* 137 */ -/* 138 */ -/* 139 */ -/* 140 */ -/* 141 */ -/* 142 */ -/* 143 (bit affects xusb_falcon_src, xusb_fs_src, */ -/* xusb_host_src and xusb_ss_src) */ -#define TEGRA114_CLK_CILAB 144 -#define TEGRA114_CLK_CILCD 145 -#define TEGRA114_CLK_CILE 146 -#define TEGRA114_CLK_DSIALP 147 -#define TEGRA114_CLK_DSIBLP 148 -/* 149 */ -#define TEGRA114_CLK_DDS 150 -/* 151 */ -#define TEGRA114_CLK_DP2 152 -#define TEGRA114_CLK_AMX 153 -#define TEGRA114_CLK_ADX 154 -/* 155 (bit affects dfll_ref and dfll_soc) */ -#define TEGRA114_CLK_XUSB_SS 156 -/* 157 */ -/* 158 */ -/* 159 */ - -/* 160 */ -/* 161 */ -/* 162 */ -/* 163 */ -/* 164 */ -/* 165 */ -/* 166 */ -/* 167 */ -/* 168 */ -/* 169 */ -/* 170 */ -/* 171 */ -/* 172 */ -/* 173 */ -/* 174 */ -/* 175 */ -/* 176 */ -/* 177 */ -/* 178 */ -/* 179 */ -/* 180 */ -/* 181 */ -/* 182 */ -/* 183 */ -/* 184 */ -/* 185 */ -/* 186 */ -/* 187 */ -/* 188 */ -/* 189 */ -/* 190 */ -/* 191 */ - -#define TEGRA114_CLK_UARTB 192 -#define TEGRA114_CLK_VFIR 193 -#define TEGRA114_CLK_SPDIF_IN 194 -#define TEGRA114_CLK_SPDIF_OUT 195 -#define TEGRA114_CLK_VI 196 -#define TEGRA114_CLK_VI_SENSOR 197 -#define TEGRA114_CLK_FUSE 198 -#define TEGRA114_CLK_FUSE_BURN 199 -#define TEGRA114_CLK_CLK_32K 200 -#define TEGRA114_CLK_CLK_M 201 -#define TEGRA114_CLK_CLK_M_DIV2 202 -#define TEGRA114_CLK_CLK_M_DIV4 203 -#define TEGRA114_CLK_PLL_REF 204 -#define TEGRA114_CLK_PLL_C 205 -#define TEGRA114_CLK_PLL_C_OUT1 206 -#define TEGRA114_CLK_PLL_C2 207 -#define TEGRA114_CLK_PLL_C3 208 -#define TEGRA114_CLK_PLL_M 209 -#define TEGRA114_CLK_PLL_M_OUT1 210 -#define TEGRA114_CLK_PLL_P 211 -#define TEGRA114_CLK_PLL_P_OUT1 212 -#define TEGRA114_CLK_PLL_P_OUT2 213 -#define TEGRA114_CLK_PLL_P_OUT3 214 -#define TEGRA114_CLK_PLL_P_OUT4 215 -#define TEGRA114_CLK_PLL_A 216 -#define TEGRA114_CLK_PLL_A_OUT0 217 -#define TEGRA114_CLK_PLL_D 218 -#define TEGRA114_CLK_PLL_D_OUT0 219 -#define TEGRA114_CLK_PLL_D2 220 -#define TEGRA114_CLK_PLL_D2_OUT0 221 -#define TEGRA114_CLK_PLL_U 222 -#define TEGRA114_CLK_PLL_U_480M 223 - -#define TEGRA114_CLK_PLL_U_60M 224 -#define TEGRA114_CLK_PLL_U_48M 225 -#define TEGRA114_CLK_PLL_U_12M 226 -#define TEGRA114_CLK_PLL_X 227 -#define TEGRA114_CLK_PLL_X_OUT0 228 -#define TEGRA114_CLK_PLL_RE_VCO 229 -#define TEGRA114_CLK_PLL_RE_OUT 230 -#define TEGRA114_CLK_PLL_E_OUT0 231 -#define TEGRA114_CLK_SPDIF_IN_SYNC 232 -#define TEGRA114_CLK_I2S0_SYNC 233 -#define TEGRA114_CLK_I2S1_SYNC 234 -#define TEGRA114_CLK_I2S2_SYNC 235 -#define TEGRA114_CLK_I2S3_SYNC 236 -#define TEGRA114_CLK_I2S4_SYNC 237 -#define TEGRA114_CLK_VIMCLK_SYNC 238 -#define TEGRA114_CLK_AUDIO0 239 -#define TEGRA114_CLK_AUDIO1 240 -#define TEGRA114_CLK_AUDIO2 241 -#define TEGRA114_CLK_AUDIO3 242 -#define TEGRA114_CLK_AUDIO4 243 -#define TEGRA114_CLK_SPDIF 244 -#define TEGRA114_CLK_CLK_OUT_1 245 -#define TEGRA114_CLK_CLK_OUT_2 246 -#define TEGRA114_CLK_CLK_OUT_3 247 -#define TEGRA114_CLK_BLINK 248 -/* 249 */ -/* 250 */ -/* 251 */ -#define TEGRA114_CLK_XUSB_HOST_SRC 252 -#define TEGRA114_CLK_XUSB_FALCON_SRC 253 -#define TEGRA114_CLK_XUSB_FS_SRC 254 -#define TEGRA114_CLK_XUSB_SS_SRC 255 - -#define TEGRA114_CLK_XUSB_DEV_SRC 256 -#define TEGRA114_CLK_XUSB_DEV 257 -#define TEGRA114_CLK_XUSB_HS_SRC 258 -#define TEGRA114_CLK_SCLK 259 -#define TEGRA114_CLK_HCLK 260 -#define TEGRA114_CLK_PCLK 261 -#define TEGRA114_CLK_CCLK_G 262 -#define TEGRA114_CLK_CCLK_LP 263 -#define TEGRA114_CLK_DFLL_REF 264 -#define TEGRA114_CLK_DFLL_SOC 265 -/* 266 */ -/* 267 */ -/* 268 */ -/* 269 */ -/* 270 */ -/* 271 */ -/* 272 */ -/* 273 */ -/* 274 */ -/* 275 */ -/* 276 */ -/* 277 */ -/* 278 */ -/* 279 */ -/* 280 */ -/* 281 */ -/* 282 */ -/* 283 */ -/* 284 */ -/* 285 */ -/* 286 */ -/* 287 */ - -/* 288 */ -/* 289 */ -/* 290 */ -/* 291 */ -/* 292 */ -/* 293 */ -/* 294 */ -/* 295 */ -/* 296 */ -/* 297 */ -/* 298 */ -/* 299 */ -#define TEGRA114_CLK_AUDIO0_MUX 300 -#define TEGRA114_CLK_AUDIO1_MUX 301 -#define TEGRA114_CLK_AUDIO2_MUX 302 -#define TEGRA114_CLK_AUDIO3_MUX 303 -#define TEGRA114_CLK_AUDIO4_MUX 304 -#define TEGRA114_CLK_SPDIF_MUX 305 -#define TEGRA114_CLK_CLK_OUT_1_MUX 306 -#define TEGRA114_CLK_CLK_OUT_2_MUX 307 -#define TEGRA114_CLK_CLK_OUT_3_MUX 308 -#define TEGRA114_CLK_DSIA_MUX 309 -#define TEGRA114_CLK_DSIB_MUX 310 -#define TEGRA114_CLK_XUSB_SS_DIV2 311 -#define TEGRA114_CLK_CLK_MAX 312 - -#endif /* _DT_BINDINGS_CLOCK_TEGRA114_CAR_H */ diff --git a/include/dt-bindings/clock/tegra124-car-common.h b/include/dt-bindings/clock/tegra124-car-common.h deleted file mode 100644 index a2156090563..00000000000 --- a/include/dt-bindings/clock/tegra124-car-common.h +++ /dev/null @@ -1,345 +0,0 @@ -/* - * This header provides constants for binding nvidia,tegra124-car or - * nvidia,tegra132-car. - * - * The first 192 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB - * registers. These IDs often match those in the CAR's RST_DEVICES registers, - * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In - * this case, those clocks are assigned IDs above 185 in order to highlight - * this issue. Implementations that interpret these clock IDs as bit values - * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to - * explicitly handle these special cases. - * - * The balance of the clocks controlled by the CAR are assigned IDs of 185 and - * above. - */ - -#ifndef _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H -#define _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H - -/* 0 */ -/* 1 */ -/* 2 */ -#define TEGRA124_CLK_ISPB 3 -#define TEGRA124_CLK_RTC 4 -#define TEGRA124_CLK_TIMER 5 -#define TEGRA124_CLK_UARTA 6 -/* 7 (register bit affects uartb and vfir) */ -/* 8 */ -#define TEGRA124_CLK_SDMMC2 9 -/* 10 (register bit affects spdif_in and spdif_out) */ -#define TEGRA124_CLK_I2S1 11 -#define TEGRA124_CLK_I2C1 12 -/* 13 */ -#define TEGRA124_CLK_SDMMC1 14 -#define TEGRA124_CLK_SDMMC4 15 -/* 16 */ -#define TEGRA124_CLK_PWM 17 -#define TEGRA124_CLK_I2S2 18 -/* 20 (register bit affects vi and vi_sensor) */ -/* 21 */ -#define TEGRA124_CLK_USBD 22 -#define TEGRA124_CLK_ISP 23 -/* 26 */ -/* 25 */ -#define TEGRA124_CLK_DISP2 26 -#define TEGRA124_CLK_DISP1 27 -#define TEGRA124_CLK_HOST1X 28 -#define TEGRA124_CLK_VCP 29 -#define TEGRA124_CLK_I2S0 30 -/* 31 */ - -#define TEGRA124_CLK_MC 32 -/* 33 */ -#define TEGRA124_CLK_APBDMA 34 -/* 35 */ -#define TEGRA124_CLK_KBC 36 -/* 37 */ -/* 38 */ -/* 39 (register bit affects fuse and fuse_burn) */ -#define TEGRA124_CLK_KFUSE 40 -#define TEGRA124_CLK_SBC1 41 -#define TEGRA124_CLK_NOR 42 -/* 43 */ -#define TEGRA124_CLK_SBC2 44 -/* 45 */ -#define TEGRA124_CLK_SBC3 46 -#define TEGRA124_CLK_I2C5 47 -#define TEGRA124_CLK_DSIA 48 -/* 49 */ -#define TEGRA124_CLK_MIPI 50 -#define TEGRA124_CLK_HDMI 51 -#define TEGRA124_CLK_CSI 52 -/* 53 */ -#define TEGRA124_CLK_I2C2 54 -#define TEGRA124_CLK_UARTC 55 -#define TEGRA124_CLK_MIPI_CAL 56 -#define TEGRA124_CLK_EMC 57 -#define TEGRA124_CLK_USB2 58 -#define TEGRA124_CLK_USB3 59 -/* 60 */ -#define TEGRA124_CLK_VDE 61 -#define TEGRA124_CLK_BSEA 62 -#define TEGRA124_CLK_BSEV 63 - -/* 64 */ -#define TEGRA124_CLK_UARTD 65 -/* 66 */ -#define TEGRA124_CLK_I2C3 67 -#define TEGRA124_CLK_SBC4 68 -#define TEGRA124_CLK_SDMMC3 69 -#define TEGRA124_CLK_PCIE 70 -#define TEGRA124_CLK_OWR 71 -#define TEGRA124_CLK_AFI 72 -#define TEGRA124_CLK_CSITE 73 -/* 74 */ -/* 75 */ -#define TEGRA124_CLK_LA 76 -#define TEGRA124_CLK_TRACE 77 -#define TEGRA124_CLK_SOC_THERM 78 -#define TEGRA124_CLK_DTV 79 -/* 80 */ -#define TEGRA124_CLK_I2CSLOW 81 -#define TEGRA124_CLK_DSIB 82 -#define TEGRA124_CLK_TSEC 83 -/* 84 */ -/* 85 */ -/* 86 */ -/* 87 */ -/* 88 */ -#define TEGRA124_CLK_XUSB_HOST 89 -/* 90 */ -#define TEGRA124_CLK_MSENC 91 -#define TEGRA124_CLK_CSUS 92 -/* 93 */ -/* 94 */ -/* 95 (bit affects xusb_dev and xusb_dev_src) */ - -/* 96 */ -/* 97 */ -/* 98 */ -#define TEGRA124_CLK_MSELECT 99 -#define TEGRA124_CLK_TSENSOR 100 -#define TEGRA124_CLK_I2S3 101 -#define TEGRA124_CLK_I2S4 102 -#define TEGRA124_CLK_I2C4 103 -#define TEGRA124_CLK_SBC5 104 -#define TEGRA124_CLK_SBC6 105 -#define TEGRA124_CLK_D_AUDIO 106 -#define TEGRA124_CLK_APBIF 107 -#define TEGRA124_CLK_DAM0 108 -#define TEGRA124_CLK_DAM1 109 -#define TEGRA124_CLK_DAM2 110 -#define TEGRA124_CLK_HDA2CODEC_2X 111 -/* 112 */ -#define TEGRA124_CLK_AUDIO0_2X 113 -#define TEGRA124_CLK_AUDIO1_2X 114 -#define TEGRA124_CLK_AUDIO2_2X 115 -#define TEGRA124_CLK_AUDIO3_2X 116 -#define TEGRA124_CLK_AUDIO4_2X 117 -#define TEGRA124_CLK_SPDIF_2X 118 -#define TEGRA124_CLK_ACTMON 119 -#define TEGRA124_CLK_EXTERN1 120 -#define TEGRA124_CLK_EXTERN2 121 -#define TEGRA124_CLK_EXTERN3 122 -#define TEGRA124_CLK_SATA_OOB 123 -#define TEGRA124_CLK_SATA 124 -#define TEGRA124_CLK_HDA 125 -/* 126 */ -#define TEGRA124_CLK_SE 127 - -#define TEGRA124_CLK_HDA2HDMI 128 -#define TEGRA124_CLK_SATA_COLD 129 -/* 130 */ -/* 131 */ -/* 132 */ -/* 133 */ -/* 134 */ -/* 135 */ -/* 136 */ -/* 137 */ -/* 138 */ -/* 139 */ -/* 140 */ -/* 141 */ -/* 142 */ -/* 143 (bit affects xusb_falcon_src, xusb_fs_src, */ -/* xusb_host_src and xusb_ss_src) */ -#define TEGRA124_CLK_CILAB 144 -#define TEGRA124_CLK_CILCD 145 -#define TEGRA124_CLK_CILE 146 -#define TEGRA124_CLK_DSIALP 147 -#define TEGRA124_CLK_DSIBLP 148 -#define TEGRA124_CLK_ENTROPY 149 -#define TEGRA124_CLK_DDS 150 -/* 151 */ -#define TEGRA124_CLK_DP2 152 -#define TEGRA124_CLK_AMX 153 -#define TEGRA124_CLK_ADX 154 -/* 155 (bit affects dfll_ref and dfll_soc) */ -#define TEGRA124_CLK_XUSB_SS 156 -/* 157 */ -/* 158 */ -/* 159 */ - -/* 160 */ -/* 161 */ -/* 162 */ -/* 163 */ -/* 164 */ -/* 165 */ -#define TEGRA124_CLK_I2C6 166 -/* 167 */ -/* 168 */ -/* 169 */ -/* 170 */ -#define TEGRA124_CLK_VIM2_CLK 171 -/* 172 */ -/* 173 */ -/* 174 */ -/* 175 */ -#define TEGRA124_CLK_HDMI_AUDIO 176 -#define TEGRA124_CLK_CLK72MHZ 177 -#define TEGRA124_CLK_VIC03 178 -/* 179 */ -#define TEGRA124_CLK_ADX1 180 -#define TEGRA124_CLK_DPAUX 181 -#define TEGRA124_CLK_SOR0 182 -/* 183 */ -#define TEGRA124_CLK_GPU 184 -#define TEGRA124_CLK_AMX1 185 -/* 186 */ -/* 187 */ -/* 188 */ -/* 189 */ -/* 190 */ -/* 191 */ -#define TEGRA124_CLK_UARTB 192 -#define TEGRA124_CLK_VFIR 193 -#define TEGRA124_CLK_SPDIF_IN 194 -#define TEGRA124_CLK_SPDIF_OUT 195 -#define TEGRA124_CLK_VI 196 -#define TEGRA124_CLK_VI_SENSOR 197 -#define TEGRA124_CLK_FUSE 198 -#define TEGRA124_CLK_FUSE_BURN 199 -#define TEGRA124_CLK_CLK_32K 200 -#define TEGRA124_CLK_CLK_M 201 -#define TEGRA124_CLK_CLK_M_DIV2 202 -#define TEGRA124_CLK_CLK_M_DIV4 203 -#define TEGRA124_CLK_PLL_REF 204 -#define TEGRA124_CLK_PLL_C 205 -#define TEGRA124_CLK_PLL_C_OUT1 206 -#define TEGRA124_CLK_PLL_C2 207 -#define TEGRA124_CLK_PLL_C3 208 -#define TEGRA124_CLK_PLL_M 209 -#define TEGRA124_CLK_PLL_M_OUT1 210 -#define TEGRA124_CLK_PLL_P 211 -#define TEGRA124_CLK_PLL_P_OUT1 212 -#define TEGRA124_CLK_PLL_P_OUT2 213 -#define TEGRA124_CLK_PLL_P_OUT3 214 -#define TEGRA124_CLK_PLL_P_OUT4 215 -#define TEGRA124_CLK_PLL_A 216 -#define TEGRA124_CLK_PLL_A_OUT0 217 -#define TEGRA124_CLK_PLL_D 218 -#define TEGRA124_CLK_PLL_D_OUT0 219 -#define TEGRA124_CLK_PLL_D2 220 -#define TEGRA124_CLK_PLL_D2_OUT0 221 -#define TEGRA124_CLK_PLL_U 222 -#define TEGRA124_CLK_PLL_U_480M 223 - -#define TEGRA124_CLK_PLL_U_60M 224 -#define TEGRA124_CLK_PLL_U_48M 225 -#define TEGRA124_CLK_PLL_U_12M 226 -/* 227 */ -/* 228 */ -#define TEGRA124_CLK_PLL_RE_VCO 229 -#define TEGRA124_CLK_PLL_RE_OUT 230 -#define TEGRA124_CLK_PLL_E 231 -#define TEGRA124_CLK_SPDIF_IN_SYNC 232 -#define TEGRA124_CLK_I2S0_SYNC 233 -#define TEGRA124_CLK_I2S1_SYNC 234 -#define TEGRA124_CLK_I2S2_SYNC 235 -#define TEGRA124_CLK_I2S3_SYNC 236 -#define TEGRA124_CLK_I2S4_SYNC 237 -#define TEGRA124_CLK_VIMCLK_SYNC 238 -#define TEGRA124_CLK_AUDIO0 239 -#define TEGRA124_CLK_AUDIO1 240 -#define TEGRA124_CLK_AUDIO2 241 -#define TEGRA124_CLK_AUDIO3 242 -#define TEGRA124_CLK_AUDIO4 243 -#define TEGRA124_CLK_SPDIF 244 -#define TEGRA124_CLK_CLK_OUT_1 245 -#define TEGRA124_CLK_CLK_OUT_2 246 -#define TEGRA124_CLK_CLK_OUT_3 247 -#define TEGRA124_CLK_BLINK 248 -/* 249 */ -/* 250 */ -/* 251 */ -#define TEGRA124_CLK_XUSB_HOST_SRC 252 -#define TEGRA124_CLK_XUSB_FALCON_SRC 253 -#define TEGRA124_CLK_XUSB_FS_SRC 254 -#define TEGRA124_CLK_XUSB_SS_SRC 255 - -#define TEGRA124_CLK_XUSB_DEV_SRC 256 -#define TEGRA124_CLK_XUSB_DEV 257 -#define TEGRA124_CLK_XUSB_HS_SRC 258 -#define TEGRA124_CLK_SCLK 259 -#define TEGRA124_CLK_HCLK 260 -#define TEGRA124_CLK_PCLK 261 -/* 262 */ -/* 263 */ -#define TEGRA124_CLK_DFLL_REF 264 -#define TEGRA124_CLK_DFLL_SOC 265 -#define TEGRA124_CLK_VI_SENSOR2 266 -#define TEGRA124_CLK_PLL_P_OUT5 267 -#define TEGRA124_CLK_CML0 268 -#define TEGRA124_CLK_CML1 269 -#define TEGRA124_CLK_PLL_C4 270 -#define TEGRA124_CLK_PLL_DP 271 -#define TEGRA124_CLK_PLL_E_MUX 272 -#define TEGRA124_CLK_PLL_D_DSI_OUT 273 -/* 274 */ -/* 275 */ -/* 276 */ -/* 277 */ -/* 278 */ -/* 279 */ -/* 280 */ -/* 281 */ -/* 282 */ -/* 283 */ -/* 284 */ -/* 285 */ -/* 286 */ -/* 287 */ - -/* 288 */ -/* 289 */ -/* 290 */ -/* 291 */ -/* 292 */ -/* 293 */ -/* 294 */ -/* 295 */ -/* 296 */ -/* 297 */ -/* 298 */ -/* 299 */ -#define TEGRA124_CLK_AUDIO0_MUX 300 -#define TEGRA124_CLK_AUDIO1_MUX 301 -#define TEGRA124_CLK_AUDIO2_MUX 302 -#define TEGRA124_CLK_AUDIO3_MUX 303 -#define TEGRA124_CLK_AUDIO4_MUX 304 -#define TEGRA124_CLK_SPDIF_MUX 305 -#define TEGRA124_CLK_CLK_OUT_1_MUX 306 -#define TEGRA124_CLK_CLK_OUT_2_MUX 307 -#define TEGRA124_CLK_CLK_OUT_3_MUX 308 -/* 309 */ -/* 310 */ -#define TEGRA124_CLK_SOR0_LVDS 311 -#define TEGRA124_CLK_XUSB_SS_DIV2 312 - -#define TEGRA124_CLK_PLL_M_UD 313 -#define TEGRA124_CLK_PLL_C_UD 314 - -#endif /* _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H */ diff --git a/include/dt-bindings/clock/tegra124-car.h b/include/dt-bindings/clock/tegra124-car.h deleted file mode 100644 index 2860737f044..00000000000 --- a/include/dt-bindings/clock/tegra124-car.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * This header provides Tegra124-specific constants for binding - * nvidia,tegra124-car. - */ - -#include <dt-bindings/clock/tegra124-car-common.h> - -#ifndef _DT_BINDINGS_CLOCK_TEGRA124_CAR_H -#define _DT_BINDINGS_CLOCK_TEGRA124_CAR_H - -#define TEGRA124_CLK_PLL_X 227 -#define TEGRA124_CLK_PLL_X_OUT0 228 - -#define TEGRA124_CLK_CCLK_G 262 -#define TEGRA124_CLK_CCLK_LP 263 - -#define TEGRA124_CLK_CLK_MAX 315 - -#endif /* _DT_BINDINGS_CLOCK_TEGRA124_CAR_H */ diff --git a/include/dt-bindings/clock/tegra186-clock.h b/include/dt-bindings/clock/tegra186-clock.h deleted file mode 100644 index f73d32098f9..00000000000 --- a/include/dt-bindings/clock/tegra186-clock.h +++ /dev/null @@ -1,940 +0,0 @@ -/** @file */ - -#ifndef _MACH_T186_CLK_T186_H -#define _MACH_T186_CLK_T186_H - -/** - * @defgroup clock_ids Clock Identifiers - * @{ - * @defgroup extern_input external input clocks - * @{ - * @def TEGRA186_CLK_OSC - * @def TEGRA186_CLK_CLK_32K - * @def TEGRA186_CLK_DTV_INPUT - * @def TEGRA186_CLK_SOR0_PAD_CLKOUT - * @def TEGRA186_CLK_SOR1_PAD_CLKOUT - * @def TEGRA186_CLK_I2S1_SYNC_INPUT - * @def TEGRA186_CLK_I2S2_SYNC_INPUT - * @def TEGRA186_CLK_I2S3_SYNC_INPUT - * @def TEGRA186_CLK_I2S4_SYNC_INPUT - * @def TEGRA186_CLK_I2S5_SYNC_INPUT - * @def TEGRA186_CLK_I2S6_SYNC_INPUT - * @def TEGRA186_CLK_SPDIFIN_SYNC_INPUT - * @} - * - * @defgroup extern_output external output clocks - * @{ - * @def TEGRA186_CLK_EXTPERIPH1 - * @def TEGRA186_CLK_EXTPERIPH2 - * @def TEGRA186_CLK_EXTPERIPH3 - * @def TEGRA186_CLK_EXTPERIPH4 - * @} - * - * @defgroup display_clks display related clocks - * @{ - * @def TEGRA186_CLK_CEC - * @def TEGRA186_CLK_DSIC - * @def TEGRA186_CLK_DSIC_LP - * @def TEGRA186_CLK_DSID - * @def TEGRA186_CLK_DSID_LP - * @def TEGRA186_CLK_DPAUX1 - * @def TEGRA186_CLK_DPAUX - * @def TEGRA186_CLK_HDA2HDMICODEC - * @def TEGRA186_CLK_NVDISPLAY_DISP - * @def TEGRA186_CLK_NVDISPLAY_DSC - * @def TEGRA186_CLK_NVDISPLAY_P0 - * @def TEGRA186_CLK_NVDISPLAY_P1 - * @def TEGRA186_CLK_NVDISPLAY_P2 - * @def TEGRA186_CLK_NVDISPLAYHUB - * @def TEGRA186_CLK_SOR_SAFE - * @def TEGRA186_CLK_SOR0 - * @def TEGRA186_CLK_SOR0_OUT - * @def TEGRA186_CLK_SOR1 - * @def TEGRA186_CLK_SOR1_OUT - * @def TEGRA186_CLK_DSI - * @def TEGRA186_CLK_MIPI_CAL - * @def TEGRA186_CLK_DSIA_LP - * @def TEGRA186_CLK_DSIB - * @def TEGRA186_CLK_DSIB_LP - * @} - * - * @defgroup camera_clks camera related clocks - * @{ - * @def TEGRA186_CLK_NVCSI - * @def TEGRA186_CLK_NVCSILP - * @def TEGRA186_CLK_VI - * @} - * - * @defgroup audio_clks audio related clocks - * @{ - * @def TEGRA186_CLK_ACLK - * @def TEGRA186_CLK_ADSP - * @def TEGRA186_CLK_ADSPNEON - * @def TEGRA186_CLK_AHUB - * @def TEGRA186_CLK_APE - * @def TEGRA186_CLK_APB2APE - * @def TEGRA186_CLK_AUD_MCLK - * @def TEGRA186_CLK_DMIC1 - * @def TEGRA186_CLK_DMIC2 - * @def TEGRA186_CLK_DMIC3 - * @def TEGRA186_CLK_DMIC4 - * @def TEGRA186_CLK_DSPK1 - * @def TEGRA186_CLK_DSPK2 - * @def TEGRA186_CLK_HDA - * @def TEGRA186_CLK_HDA2CODEC_2X - * @def TEGRA186_CLK_I2S1 - * @def TEGRA186_CLK_I2S2 - * @def TEGRA186_CLK_I2S3 - * @def TEGRA186_CLK_I2S4 - * @def TEGRA186_CLK_I2S5 - * @def TEGRA186_CLK_I2S6 - * @def TEGRA186_CLK_MAUD - * @def TEGRA186_CLK_PLL_A_OUT0 - * @def TEGRA186_CLK_SPDIF_DOUBLER - * @def TEGRA186_CLK_SPDIF_IN - * @def TEGRA186_CLK_SPDIF_OUT - * @def TEGRA186_CLK_SYNC_DMIC1 - * @def TEGRA186_CLK_SYNC_DMIC2 - * @def TEGRA186_CLK_SYNC_DMIC3 - * @def TEGRA186_CLK_SYNC_DMIC4 - * @def TEGRA186_CLK_SYNC_DMIC5 - * @def TEGRA186_CLK_SYNC_DSPK1 - * @def TEGRA186_CLK_SYNC_DSPK2 - * @def TEGRA186_CLK_SYNC_I2S1 - * @def TEGRA186_CLK_SYNC_I2S2 - * @def TEGRA186_CLK_SYNC_I2S3 - * @def TEGRA186_CLK_SYNC_I2S4 - * @def TEGRA186_CLK_SYNC_I2S5 - * @def TEGRA186_CLK_SYNC_I2S6 - * @def TEGRA186_CLK_SYNC_SPDIF - * @} - * - * @defgroup uart_clks UART clocks - * @{ - * @def TEGRA186_CLK_AON_UART_FST_MIPI_CAL - * @def TEGRA186_CLK_UARTA - * @def TEGRA186_CLK_UARTB - * @def TEGRA186_CLK_UARTC - * @def TEGRA186_CLK_UARTD - * @def TEGRA186_CLK_UARTE - * @def TEGRA186_CLK_UARTF - * @def TEGRA186_CLK_UARTG - * @def TEGRA186_CLK_UART_FST_MIPI_CAL - * @} - * - * @defgroup i2c_clks I2C clocks - * @{ - * @def TEGRA186_CLK_AON_I2C_SLOW - * @def TEGRA186_CLK_I2C1 - * @def TEGRA186_CLK_I2C2 - * @def TEGRA186_CLK_I2C3 - * @def TEGRA186_CLK_I2C4 - * @def TEGRA186_CLK_I2C5 - * @def TEGRA186_CLK_I2C6 - * @def TEGRA186_CLK_I2C8 - * @def TEGRA186_CLK_I2C9 - * @def TEGRA186_CLK_I2C1 - * @def TEGRA186_CLK_I2C12 - * @def TEGRA186_CLK_I2C13 - * @def TEGRA186_CLK_I2C14 - * @def TEGRA186_CLK_I2C_SLOW - * @def TEGRA186_CLK_VI_I2C - * @} - * - * @defgroup spi_clks SPI clocks - * @{ - * @def TEGRA186_CLK_SPI1 - * @def TEGRA186_CLK_SPI2 - * @def TEGRA186_CLK_SPI3 - * @def TEGRA186_CLK_SPI4 - * @} - * - * @defgroup storage storage related clocks - * @{ - * @def TEGRA186_CLK_SATA - * @def TEGRA186_CLK_SATA_OOB - * @def TEGRA186_CLK_SATA_IOBIST - * @def TEGRA186_CLK_SDMMC_LEGACY_TM - * @def TEGRA186_CLK_SDMMC1 - * @def TEGRA186_CLK_SDMMC2 - * @def TEGRA186_CLK_SDMMC3 - * @def TEGRA186_CLK_SDMMC4 - * @def TEGRA186_CLK_QSPI - * @def TEGRA186_CLK_QSPI_OUT - * @def TEGRA186_CLK_UFSDEV_REF - * @def TEGRA186_CLK_UFSHC - * @} - * - * @defgroup pwm_clks PWM clocks - * @{ - * @def TEGRA186_CLK_PWM1 - * @def TEGRA186_CLK_PWM2 - * @def TEGRA186_CLK_PWM3 - * @def TEGRA186_CLK_PWM4 - * @def TEGRA186_CLK_PWM5 - * @def TEGRA186_CLK_PWM6 - * @def TEGRA186_CLK_PWM7 - * @def TEGRA186_CLK_PWM8 - * @} - * - * @defgroup plls PLLs and related clocks - * @{ - * @def TEGRA186_CLK_PLLREFE_OUT_GATED - * @def TEGRA186_CLK_PLLREFE_OUT1 - * @def TEGRA186_CLK_PLLD_OUT1 - * @def TEGRA186_CLK_PLLP_OUT0 - * @def TEGRA186_CLK_PLLP_OUT5 - * @def TEGRA186_CLK_PLLA - * @def TEGRA186_CLK_PLLE_PWRSEQ - * @def TEGRA186_CLK_PLLA_OUT1 - * @def TEGRA186_CLK_PLLREFE_REF - * @def TEGRA186_CLK_UPHY_PLL0_PWRSEQ - * @def TEGRA186_CLK_UPHY_PLL1_PWRSEQ - * @def TEGRA186_CLK_PLLREFE_PLLE_PASSTHROUGH - * @def TEGRA186_CLK_PLLREFE_PEX - * @def TEGRA186_CLK_PLLREFE_IDDQ - * @def TEGRA186_CLK_PLLC_OUT_AON - * @def TEGRA186_CLK_PLLC_OUT_ISP - * @def TEGRA186_CLK_PLLC_OUT_VE - * @def TEGRA186_CLK_PLLC4_OUT - * @def TEGRA186_CLK_PLLREFE_OUT - * @def TEGRA186_CLK_PLLREFE_PLL_REF - * @def TEGRA186_CLK_PLLE - * @def TEGRA186_CLK_PLLC - * @def TEGRA186_CLK_PLLP - * @def TEGRA186_CLK_PLLD - * @def TEGRA186_CLK_PLLD2 - * @def TEGRA186_CLK_PLLREFE_VCO - * @def TEGRA186_CLK_PLLC2 - * @def TEGRA186_CLK_PLLC3 - * @def TEGRA186_CLK_PLLDP - * @def TEGRA186_CLK_PLLC4_VCO - * @def TEGRA186_CLK_PLLA1 - * @def TEGRA186_CLK_PLLNVCSI - * @def TEGRA186_CLK_PLLDISPHUB - * @def TEGRA186_CLK_PLLD3 - * @def TEGRA186_CLK_PLLBPMPCAM - * @def TEGRA186_CLK_PLLAON - * @def TEGRA186_CLK_PLLU - * @def TEGRA186_CLK_PLLC4_VCO_DIV2 - * @def TEGRA186_CLK_PLL_REF - * @def TEGRA186_CLK_PLLREFE_OUT1_DIV5 - * @def TEGRA186_CLK_UTMIP_PLL_PWRSEQ - * @def TEGRA186_CLK_PLL_U_48M - * @def TEGRA186_CLK_PLL_U_480M - * @def TEGRA186_CLK_PLLC4_OUT0 - * @def TEGRA186_CLK_PLLC4_OUT1 - * @def TEGRA186_CLK_PLLC4_OUT2 - * @def TEGRA186_CLK_PLLC4_OUT_MUX - * @def TEGRA186_CLK_DFLLDISP_DIV - * @def TEGRA186_CLK_PLLDISPHUB_DIV - * @def TEGRA186_CLK_PLLP_DIV8 - * @} - * - * @defgroup nafll_clks NAFLL clock sources - * @{ - * @def TEGRA186_CLK_NAFLL_AXI_CBB - * @def TEGRA186_CLK_NAFLL_BCPU - * @def TEGRA186_CLK_NAFLL_BPMP - * @def TEGRA186_CLK_NAFLL_DISP - * @def TEGRA186_CLK_NAFLL_GPU - * @def TEGRA186_CLK_NAFLL_ISP - * @def TEGRA186_CLK_NAFLL_MCPU - * @def TEGRA186_CLK_NAFLL_NVDEC - * @def TEGRA186_CLK_NAFLL_NVENC - * @def TEGRA186_CLK_NAFLL_NVJPG - * @def TEGRA186_CLK_NAFLL_SCE - * @def TEGRA186_CLK_NAFLL_SE - * @def TEGRA186_CLK_NAFLL_TSEC - * @def TEGRA186_CLK_NAFLL_TSECB - * @def TEGRA186_CLK_NAFLL_VI - * @def TEGRA186_CLK_NAFLL_VIC - * @} - * - * @defgroup mphy MPHY related clocks - * @{ - * @def TEGRA186_CLK_MPHY_L0_RX_SYMB - * @def TEGRA186_CLK_MPHY_L0_RX_LS_BIT - * @def TEGRA186_CLK_MPHY_L0_TX_SYMB - * @def TEGRA186_CLK_MPHY_L0_TX_LS_3XBIT - * @def TEGRA186_CLK_MPHY_L0_RX_ANA - * @def TEGRA186_CLK_MPHY_L1_RX_ANA - * @def TEGRA186_CLK_MPHY_IOBIST - * @def TEGRA186_CLK_MPHY_TX_1MHZ_REF - * @def TEGRA186_CLK_MPHY_CORE_PLL_FIXED - * @} - * - * @defgroup eavb EAVB related clocks - * @{ - * @def TEGRA186_CLK_EQOS_AXI - * @def TEGRA186_CLK_EQOS_PTP_REF - * @def TEGRA186_CLK_EQOS_RX - * @def TEGRA186_CLK_EQOS_RX_INPUT - * @def TEGRA186_CLK_EQOS_TX - * @} - * - * @defgroup usb USB related clocks - * @{ - * @def TEGRA186_CLK_PEX_USB_PAD0_MGMT - * @def TEGRA186_CLK_PEX_USB_PAD1_MGMT - * @def TEGRA186_CLK_HSIC_TRK - * @def TEGRA186_CLK_USB2_TRK - * @def TEGRA186_CLK_USB2_HSIC_TRK - * @def TEGRA186_CLK_XUSB_CORE_SS - * @def TEGRA186_CLK_XUSB_CORE_DEV - * @def TEGRA186_CLK_XUSB_FALCON - * @def TEGRA186_CLK_XUSB_FS - * @def TEGRA186_CLK_XUSB - * @def TEGRA186_CLK_XUSB_DEV - * @def TEGRA186_CLK_XUSB_HOST - * @def TEGRA186_CLK_XUSB_SS - * @} - * - * @defgroup bigblock compute block related clocks - * @{ - * @def TEGRA186_CLK_GPCCLK - * @def TEGRA186_CLK_GPC2CLK - * @def TEGRA186_CLK_GPU - * @def TEGRA186_CLK_HOST1X - * @def TEGRA186_CLK_ISP - * @def TEGRA186_CLK_NVDEC - * @def TEGRA186_CLK_NVENC - * @def TEGRA186_CLK_NVJPG - * @def TEGRA186_CLK_SE - * @def TEGRA186_CLK_TSEC - * @def TEGRA186_CLK_TSECB - * @def TEGRA186_CLK_VIC - * @} - * - * @defgroup can CAN bus related clocks - * @{ - * @def TEGRA186_CLK_CAN1 - * @def TEGRA186_CLK_CAN1_HOST - * @def TEGRA186_CLK_CAN2 - * @def TEGRA186_CLK_CAN2_HOST - * @} - * - * @defgroup system basic system clocks - * @{ - * @def TEGRA186_CLK_ACTMON - * @def TEGRA186_CLK_AON_APB - * @def TEGRA186_CLK_AON_CPU_NIC - * @def TEGRA186_CLK_AON_NIC - * @def TEGRA186_CLK_AXI_CBB - * @def TEGRA186_CLK_BPMP_APB - * @def TEGRA186_CLK_BPMP_CPU_NIC - * @def TEGRA186_CLK_BPMP_NIC_RATE - * @def TEGRA186_CLK_CLK_M - * @def TEGRA186_CLK_EMC - * @def TEGRA186_CLK_MSS_ENCRYPT - * @def TEGRA186_CLK_SCE_APB - * @def TEGRA186_CLK_SCE_CPU_NIC - * @def TEGRA186_CLK_SCE_NIC - * @def TEGRA186_CLK_TSC - * @} - * - * @defgroup pcie_clks PCIe related clocks - * @{ - * @def TEGRA186_CLK_AFI - * @def TEGRA186_CLK_PCIE - * @def TEGRA186_CLK_PCIE2_IOBIST - * @def TEGRA186_CLK_PCIERX0 - * @def TEGRA186_CLK_PCIERX1 - * @def TEGRA186_CLK_PCIERX2 - * @def TEGRA186_CLK_PCIERX3 - * @def TEGRA186_CLK_PCIERX4 - * @} - */ - -/** @brief output of gate CLK_ENB_FUSE */ -#define TEGRA186_CLK_FUSE 0 -/** - * @brief It's not what you think - * @details output of gate CLK_ENB_GPU. This output connects to the GPU - * pwrclk. @warning: This is almost certainly not the clock you think - * it is. If you're looking for the clock of the graphics engine, see - * TEGRA186_GPCCLK - */ -#define TEGRA186_CLK_GPU 1 -/** @brief output of gate CLK_ENB_PCIE */ -#define TEGRA186_CLK_PCIE 3 -/** @brief output of the divider IPFS_CLK_DIVISOR */ -#define TEGRA186_CLK_AFI 4 -/** @brief output of gate CLK_ENB_PCIE2_IOBIST */ -#define TEGRA186_CLK_PCIE2_IOBIST 5 -/** @brief output of gate CLK_ENB_PCIERX0*/ -#define TEGRA186_CLK_PCIERX0 6 -/** @brief output of gate CLK_ENB_PCIERX1*/ -#define TEGRA186_CLK_PCIERX1 7 -/** @brief output of gate CLK_ENB_PCIERX2*/ -#define TEGRA186_CLK_PCIERX2 8 -/** @brief output of gate CLK_ENB_PCIERX3*/ -#define TEGRA186_CLK_PCIERX3 9 -/** @brief output of gate CLK_ENB_PCIERX4*/ -#define TEGRA186_CLK_PCIERX4 10 -/** @brief output branch of PLL_C for ISP, controlled by gate CLK_ENB_PLLC_OUT_ISP */ -#define TEGRA186_CLK_PLLC_OUT_ISP 11 -/** @brief output branch of PLL_C for VI, controlled by gate CLK_ENB_PLLC_OUT_VE */ -#define TEGRA186_CLK_PLLC_OUT_VE 12 -/** @brief output branch of PLL_C for AON domain, controlled by gate CLK_ENB_PLLC_OUT_AON */ -#define TEGRA186_CLK_PLLC_OUT_AON 13 -/** @brief output of gate CLK_ENB_SOR_SAFE */ -#define TEGRA186_CLK_SOR_SAFE 39 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S2 */ -#define TEGRA186_CLK_I2S2 42 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S3 */ -#define TEGRA186_CLK_I2S3 43 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPDF_IN */ -#define TEGRA186_CLK_SPDIF_IN 44 -/** @brief output of gate CLK_ENB_SPDIF_DOUBLER */ -#define TEGRA186_CLK_SPDIF_DOUBLER 45 -/** @clkdesc{spi_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_SPI3} */ -#define TEGRA186_CLK_SPI3 46 -/** @clkdesc{i2c_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1} */ -#define TEGRA186_CLK_I2C1 47 -/** @clkdesc{i2c_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_I2C5} */ -#define TEGRA186_CLK_I2C5 48 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI1 */ -#define TEGRA186_CLK_SPI1 49 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_ISP */ -#define TEGRA186_CLK_ISP 50 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI */ -#define TEGRA186_CLK_VI 51 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1 */ -#define TEGRA186_CLK_SDMMC1 52 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2 */ -#define TEGRA186_CLK_SDMMC2 53 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */ -#define TEGRA186_CLK_SDMMC4 54 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */ -#define TEGRA186_CLK_UARTA 55 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTB */ -#define TEGRA186_CLK_UARTB 56 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X */ -#define TEGRA186_CLK_HOST1X 57 -/** - * @brief controls the EMC clock frequency. - * @details Doing a clk_set_rate on this clock will select the - * appropriate clock source, program the source rate and execute a - * specific sequence to switch to the new clock source for both memory - * controllers. This can be used to control the balance between memory - * throughput and memory controller power. - */ -#define TEGRA186_CLK_EMC 58 -/* @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4 */ -#define TEGRA186_CLK_EXTPERIPH4 73 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI4 */ -#define TEGRA186_CLK_SPI4 74 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 */ -#define TEGRA186_CLK_I2C3 75 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3 */ -#define TEGRA186_CLK_SDMMC3 76 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTD */ -#define TEGRA186_CLK_UARTD 77 -/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S1 */ -#define TEGRA186_CLK_I2S1 79 -/** output of gate CLK_ENB_DTV */ -#define TEGRA186_CLK_DTV 80 -/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSEC */ -#define TEGRA186_CLK_TSEC 81 -/** @brief output of gate CLK_ENB_DP2 */ -#define TEGRA186_CLK_DP2 82 -/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S4 */ -#define TEGRA186_CLK_I2S4 84 -/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S5 */ -#define TEGRA186_CLK_I2S5 85 -/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 */ -#define TEGRA186_CLK_I2C4 86 -/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AHUB */ -#define TEGRA186_CLK_AHUB 87 -/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X */ -#define TEGRA186_CLK_HDA2CODEC_2X 88 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1 */ -#define TEGRA186_CLK_EXTPERIPH1 89 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2 */ -#define TEGRA186_CLK_EXTPERIPH2 90 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3 */ -#define TEGRA186_CLK_EXTPERIPH3 91 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW */ -#define TEGRA186_CLK_I2C_SLOW 92 -/** @brief output of the SOR1_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 */ -#define TEGRA186_CLK_SOR1 93 -/** @brief output of gate CLK_ENB_CEC */ -#define TEGRA186_CLK_CEC 94 -/** @brief output of gate CLK_ENB_DPAUX1 */ -#define TEGRA186_CLK_DPAUX1 95 -/** @brief output of gate CLK_ENB_DPAUX */ -#define TEGRA186_CLK_DPAUX 96 -/** @brief output of the SOR0_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0 */ -#define TEGRA186_CLK_SOR0 97 -/** @brief output of gate CLK_ENB_HDA2HDMICODEC */ -#define TEGRA186_CLK_HDA2HDMICODEC 98 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SATA */ -#define TEGRA186_CLK_SATA 99 -/** @brief output of gate CLK_ENB_SATA_OOB */ -#define TEGRA186_CLK_SATA_OOB 100 -/** @brief output of gate CLK_ENB_SATA_IOBIST */ -#define TEGRA186_CLK_SATA_IOBIST 101 -/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HDA */ -#define TEGRA186_CLK_HDA 102 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SE */ -#define TEGRA186_CLK_SE 103 -/** @brief output of gate CLK_ENB_APB2APE */ -#define TEGRA186_CLK_APB2APE 104 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_APE */ -#define TEGRA186_CLK_APE 105 -/** @brief output of gate CLK_ENB_IQC1 */ -#define TEGRA186_CLK_IQC1 106 -/** @brief output of gate CLK_ENB_IQC2 */ -#define TEGRA186_CLK_IQC2 107 -/** divide by 2 version of TEGRA186_CLK_PLLREFE_VCO */ -#define TEGRA186_CLK_PLLREFE_OUT 108 -/** @brief output of gate CLK_ENB_PLLREFE_PLL_REF */ -#define TEGRA186_CLK_PLLREFE_PLL_REF 109 -/** @brief output of gate CLK_ENB_PLLC4_OUT */ -#define TEGRA186_CLK_PLLC4_OUT 110 -/** @brief output of mux xusb_core_clk_switch on page 67 of T186_Clocks_IAS.doc */ -#define TEGRA186_CLK_XUSB 111 -/** controls xusb_dev_ce signal on page 66 and 67 of T186_Clocks_IAS.doc */ -#define TEGRA186_CLK_XUSB_DEV 112 -/** controls xusb_host_ce signal on page 67 of T186_Clocks_IAS.doc */ -#define TEGRA186_CLK_XUSB_HOST 113 -/** controls xusb_ss_ce signal on page 67 of T186_Clocks_IAS.doc */ -#define TEGRA186_CLK_XUSB_SS 114 -/** @brief output of gate CLK_ENB_DSI */ -#define TEGRA186_CLK_DSI 115 -/** @brief output of gate CLK_ENB_MIPI_CAL */ -#define TEGRA186_CLK_MIPI_CAL 116 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP */ -#define TEGRA186_CLK_DSIA_LP 117 -/** @brief output of gate CLK_ENB_DSIB */ -#define TEGRA186_CLK_DSIB 118 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP */ -#define TEGRA186_CLK_DSIB_LP 119 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1 */ -#define TEGRA186_CLK_DMIC1 122 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2 */ -#define TEGRA186_CLK_DMIC2 123 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK */ -#define TEGRA186_CLK_AUD_MCLK 124 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */ -#define TEGRA186_CLK_I2C6 125 -/**output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL */ -#define TEGRA186_CLK_UART_FST_MIPI_CAL 126 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VIC */ -#define TEGRA186_CLK_VIC 127 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM */ -#define TEGRA186_CLK_SDMMC_LEGACY_TM 128 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC */ -#define TEGRA186_CLK_NVDEC 129 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG */ -#define TEGRA186_CLK_NVJPG 130 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVENC */ -#define TEGRA186_CLK_NVENC 131 -/** @brief output of the QSPI_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI */ -#define TEGRA186_CLK_QSPI 132 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI_I2C */ -#define TEGRA186_CLK_VI_I2C 133 -/** @brief output of gate CLK_ENB_HSIC_TRK */ -#define TEGRA186_CLK_HSIC_TRK 134 -/** @brief output of gate CLK_ENB_USB2_TRK */ -#define TEGRA186_CLK_USB2_TRK 135 -/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_MAUD */ -#define TEGRA186_CLK_MAUD 136 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSECB */ -#define TEGRA186_CLK_TSECB 137 -/** @brief output of gate CLK_ENB_ADSP */ -#define TEGRA186_CLK_ADSP 138 -/** @brief output of gate CLK_ENB_ADSPNEON */ -#define TEGRA186_CLK_ADSPNEON 139 -/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB */ -#define TEGRA186_CLK_MPHY_L0_RX_SYMB 140 -/** @brief output of gate CLK_ENB_MPHY_L0_RX_LS_BIT */ -#define TEGRA186_CLK_MPHY_L0_RX_LS_BIT 141 -/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB */ -#define TEGRA186_CLK_MPHY_L0_TX_SYMB 142 -/** @brief output of gate CLK_ENB_MPHY_L0_TX_LS_3XBIT */ -#define TEGRA186_CLK_MPHY_L0_TX_LS_3XBIT 143 -/** @brief output of gate CLK_ENB_MPHY_L0_RX_ANA */ -#define TEGRA186_CLK_MPHY_L0_RX_ANA 144 -/** @brief output of gate CLK_ENB_MPHY_L1_RX_ANA */ -#define TEGRA186_CLK_MPHY_L1_RX_ANA 145 -/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST */ -#define TEGRA186_CLK_MPHY_IOBIST 146 -/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF */ -#define TEGRA186_CLK_MPHY_TX_1MHZ_REF 147 -/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED */ -#define TEGRA186_CLK_MPHY_CORE_PLL_FIXED 148 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB */ -#define TEGRA186_CLK_AXI_CBB 149 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3 */ -#define TEGRA186_CLK_DMIC3 150 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4 */ -#define TEGRA186_CLK_DMIC4 151 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1 */ -#define TEGRA186_CLK_DSPK1 152 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2 */ -#define TEGRA186_CLK_DSPK2 153 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */ -#define TEGRA186_CLK_I2S6 154 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0 */ -#define TEGRA186_CLK_NVDISPLAY_P0 155 -/** @brief output of the NVDISPLAY_DISP_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP */ -#define TEGRA186_CLK_NVDISPLAY_DISP 156 -/** @brief output of gate CLK_ENB_NVDISPLAY_DSC */ -#define TEGRA186_CLK_NVDISPLAY_DSC 157 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB */ -#define TEGRA186_CLK_NVDISPLAYHUB 158 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1 */ -#define TEGRA186_CLK_NVDISPLAY_P1 159 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2 */ -#define TEGRA186_CLK_NVDISPLAY_P2 160 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TACH */ -#define TEGRA186_CLK_TACH 166 -/** @brief output of gate CLK_ENB_EQOS */ -#define TEGRA186_CLK_EQOS_AXI 167 -/** @brief output of gate CLK_ENB_EQOS_RX */ -#define TEGRA186_CLK_EQOS_RX 168 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS */ -#define TEGRA186_CLK_UFSHC 178 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF */ -#define TEGRA186_CLK_UFSDEV_REF 179 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI */ -#define TEGRA186_CLK_NVCSI 180 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP */ -#define TEGRA186_CLK_NVCSILP 181 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C7 */ -#define TEGRA186_CLK_I2C7 182 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */ -#define TEGRA186_CLK_I2C9 183 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C12 */ -#define TEGRA186_CLK_I2C12 184 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C13 */ -#define TEGRA186_CLK_I2C13 185 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C14 */ -#define TEGRA186_CLK_I2C14 186 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM1 */ -#define TEGRA186_CLK_PWM1 187 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM2 */ -#define TEGRA186_CLK_PWM2 188 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM3 */ -#define TEGRA186_CLK_PWM3 189 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM5 */ -#define TEGRA186_CLK_PWM5 190 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM6 */ -#define TEGRA186_CLK_PWM6 191 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM7 */ -#define TEGRA186_CLK_PWM7 192 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM8 */ -#define TEGRA186_CLK_PWM8 193 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTE */ -#define TEGRA186_CLK_UARTE 194 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTF */ -#define TEGRA186_CLK_UARTF 195 -/** @deprecated */ -#define TEGRA186_CLK_DBGAPB 196 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC */ -#define TEGRA186_CLK_BPMP_CPU_NIC 197 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB */ -#define TEGRA186_CLK_BPMP_APB 199 -/** @brief output of mux controlled by TEGRA186_CLK_SOC_ACTMON */ -#define TEGRA186_CLK_ACTMON 201 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC */ -#define TEGRA186_CLK_AON_CPU_NIC 208 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN1 */ -#define TEGRA186_CLK_CAN1 210 -/** @brief output of gate CLK_ENB_CAN1_HOST */ -#define TEGRA186_CLK_CAN1_HOST 211 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN2 */ -#define TEGRA186_CLK_CAN2 212 -/** @brief output of gate CLK_ENB_CAN2_HOST */ -#define TEGRA186_CLK_CAN2_HOST 213 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB */ -#define TEGRA186_CLK_AON_APB 214 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTC */ -#define TEGRA186_CLK_UARTC 215 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTG */ -#define TEGRA186_CLK_UARTG 216 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL */ -#define TEGRA186_CLK_AON_UART_FST_MIPI_CAL 217 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */ -#define TEGRA186_CLK_I2C2 218 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C8 */ -#define TEGRA186_CLK_I2C8 219 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C10 */ -#define TEGRA186_CLK_I2C10 220 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW */ -#define TEGRA186_CLK_AON_I2C_SLOW 221 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI2 */ -#define TEGRA186_CLK_SPI2 222 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5 */ -#define TEGRA186_CLK_DMIC5 223 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH */ -#define TEGRA186_CLK_AON_TOUCH 224 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM4 */ -#define TEGRA186_CLK_PWM4 225 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSC. This clock object is read only and is used for all timers in the system. */ -#define TEGRA186_CLK_TSC 226 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT */ -#define TEGRA186_CLK_MSS_ENCRYPT 227 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC */ -#define TEGRA186_CLK_SCE_CPU_NIC 228 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB */ -#define TEGRA186_CLK_SCE_APB 230 -/** @brief output of gate CLK_ENB_DSIC */ -#define TEGRA186_CLK_DSIC 231 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIC_LP */ -#define TEGRA186_CLK_DSIC_LP 232 -/** @brief output of gate CLK_ENB_DSID */ -#define TEGRA186_CLK_DSID 233 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSID_LP */ -#define TEGRA186_CLK_DSID_LP 234 -/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP */ -#define TEGRA186_CLK_PEX_SATA_USB_RX_BYP 236 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT */ -#define TEGRA186_CLK_SPDIF_OUT 238 -/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0 */ -#define TEGRA186_CLK_EQOS_PTP_REF 239 -/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK */ -#define TEGRA186_CLK_EQOS_TX 240 -/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK */ -#define TEGRA186_CLK_USB2_HSIC_TRK 241 -/** @brief output of mux xusb_ss_clk_switch on page 66 of T186_Clocks_IAS.doc */ -#define TEGRA186_CLK_XUSB_CORE_SS 242 -/** @brief output of mux xusb_core_dev_clk_switch on page 67 of T186_Clocks_IAS.doc */ -#define TEGRA186_CLK_XUSB_CORE_DEV 243 -/** @brief output of mux xusb_core_falcon_clk_switch on page 67 of T186_Clocks_IAS.doc */ -#define TEGRA186_CLK_XUSB_FALCON 244 -/** @brief output of mux xusb_fs_clk_switch on page 66 of T186_Clocks_IAS.doc */ -#define TEGRA186_CLK_XUSB_FS 245 -/** @brief output of the divider CLK_RST_CONTROLLER_PLLA_OUT */ -#define TEGRA186_CLK_PLL_A_OUT0 246 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1 */ -#define TEGRA186_CLK_SYNC_I2S1 247 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2 */ -#define TEGRA186_CLK_SYNC_I2S2 248 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3 */ -#define TEGRA186_CLK_SYNC_I2S3 249 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4 */ -#define TEGRA186_CLK_SYNC_I2S4 250 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5 */ -#define TEGRA186_CLK_SYNC_I2S5 251 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6 */ -#define TEGRA186_CLK_SYNC_I2S6 252 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1 */ -#define TEGRA186_CLK_SYNC_DSPK1 253 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2 */ -#define TEGRA186_CLK_SYNC_DSPK2 254 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1 */ -#define TEGRA186_CLK_SYNC_DMIC1 255 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2 */ -#define TEGRA186_CLK_SYNC_DMIC2 256 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3 */ -#define TEGRA186_CLK_SYNC_DMIC3 257 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4 */ -#define TEGRA186_CLK_SYNC_DMIC4 259 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF */ -#define TEGRA186_CLK_SYNC_SPDIF 260 -/** @brief output of gate CLK_ENB_PLLREFE_OUT */ -#define TEGRA186_CLK_PLLREFE_OUT_GATED 261 -/** @brief output of the divider PLLREFE_DIVP in CLK_RST_CONTROLLER_PLLREFE_BASE. PLLREFE has 2 outputs: - * * VCO/pdiv defined by this clock object - * * VCO/2 defined by TEGRA186_CLK_PLLREFE_OUT - */ -#define TEGRA186_CLK_PLLREFE_OUT1 262 -#define TEGRA186_CLK_PLLD_OUT1 267 -/** @brief output of the divider PLLP_DIVP in CLK_RST_CONTROLLER_PLLP_BASE */ -#define TEGRA186_CLK_PLLP_OUT0 269 -/** @brief output of the divider CLK_RST_CONTROLLER_PLLP_OUTC */ -#define TEGRA186_CLK_PLLP_OUT5 270 -/** PLL controlled by CLK_RST_CONTROLLER_PLLA_BASE for use by audio clocks */ -#define TEGRA186_CLK_PLLA 271 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_ACLK_BURST_POLICY divided by the divider controlled by ACLK_CLK_DIVISOR in CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER */ -#define TEGRA186_CLK_ACLK 273 -/** fixed 48MHz clock divided down from TEGRA186_CLK_PLL_U */ -#define TEGRA186_CLK_PLL_U_48M 274 -/** fixed 480MHz clock divided down from TEGRA186_CLK_PLL_U */ -#define TEGRA186_CLK_PLL_U_480M 275 -/** @brief output of the divider PLLC4_DIVP in CLK_RST_CONTROLLER_PLLC4_BASE. Output frequency is TEGRA186_CLK_PLLC4_VCO/PLLC4_DIVP */ -#define TEGRA186_CLK_PLLC4_OUT0 276 -/** fixed /3 divider. Output frequency of this clock is TEGRA186_CLK_PLLC4_VCO/3 */ -#define TEGRA186_CLK_PLLC4_OUT1 277 -/** fixed /5 divider. Output frequency of this clock is TEGRA186_CLK_PLLC4_VCO/5 */ -#define TEGRA186_CLK_PLLC4_OUT2 278 -/** @brief output of mux controlled by PLLC4_CLK_SEL in CLK_RST_CONTROLLER_PLLC4_MISC1 */ -#define TEGRA186_CLK_PLLC4_OUT_MUX 279 -/** @brief output of divider NVDISPLAY_DISP_CLK_DIVISOR in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP when DFLLDISP_DIV is selected in NVDISPLAY_DISP_CLK_SRC */ -#define TEGRA186_CLK_DFLLDISP_DIV 284 -/** @brief output of divider NVDISPLAY_DISP_CLK_DIVISOR in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP when PLLDISPHUB_DIV is selected in NVDISPLAY_DISP_CLK_SRC */ -#define TEGRA186_CLK_PLLDISPHUB_DIV 285 -/** fixed /8 divider which is used as the input for TEGRA186_CLK_SOR_SAFE */ -#define TEGRA186_CLK_PLLP_DIV8 286 -/** @brief output of divider CLK_RST_CONTROLLER_BPMP_NIC_RATE */ -#define TEGRA186_CLK_BPMP_NIC 287 -/** @brief output of the divider CLK_RST_CONTROLLER_PLLA1_OUT1 */ -#define TEGRA186_CLK_PLL_A_OUT1 288 -/** @deprecated */ -#define TEGRA186_CLK_GPC2CLK 289 -/** A fake clock which must be enabled during KFUSE read operations to ensure adequate VDD_CORE voltage. */ -#define TEGRA186_CLK_KFUSE 293 -/** - * @brief controls the PLLE hardware sequencer. - * @details This clock only has enable and disable methods. When the - * PLLE hw sequencer is enabled, PLLE, will be enabled or disabled by - * hw based on the control signals from the PCIe, SATA and XUSB - * clocks. When the PLLE hw sequencer is disabled, the state of PLLE - * is controlled by sw using clk_enable/clk_disable on - * TEGRA186_CLK_PLLE. - */ -#define TEGRA186_CLK_PLLE_PWRSEQ 294 -/** fixed 60MHz clock divided down from, TEGRA186_CLK_PLL_U */ -#define TEGRA186_CLK_PLLREFE_REF 295 -/** @brief output of mux controlled by SOR0_CLK_SEL0 and SOR0_CLK_SEL1 in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0 */ -#define TEGRA186_CLK_SOR0_OUT 296 -/** @brief output of mux controlled by SOR1_CLK_SEL0 and SOR1_CLK_SEL1 in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 */ -#define TEGRA186_CLK_SOR1_OUT 297 -/** @brief fixed /5 divider. Output frequency of this clock is TEGRA186_CLK_PLLREFE_OUT1/5. Used as input for TEGRA186_CLK_EQOS_AXI */ -#define TEGRA186_CLK_PLLREFE_OUT1_DIV5 298 -/** @brief controls the UTMIP_PLL (aka PLLU) hardware sqeuencer */ -#define TEGRA186_CLK_UTMIP_PLL_PWRSEQ 301 -/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT */ -#define TEGRA186_CLK_PEX_USB_PAD0_MGMT 302 -/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT */ -#define TEGRA186_CLK_PEX_USB_PAD1_MGMT 303 -/** @brief controls the UPHY_PLL0 hardware sqeuencer */ -#define TEGRA186_CLK_UPHY_PLL0_PWRSEQ 304 -/** @brief controls the UPHY_PLL1 hardware sqeuencer */ -#define TEGRA186_CLK_UPHY_PLL1_PWRSEQ 305 -/** @brief control for PLLREFE_IDDQ in CLK_RST_CONTROLLER_PLLREFE_MISC so the bypass output even be used when the PLL is disabled */ -#define TEGRA186_CLK_PLLREFE_PLLE_PASSTHROUGH 306 -/** @brief output of the mux controlled by PLLREFE_SEL_CLKIN_PEX in CLK_RST_CONTROLLER_PLLREFE_MISC */ -#define TEGRA186_CLK_PLLREFE_PEX 307 -/** @brief control for PLLREFE_IDDQ in CLK_RST_CONTROLLER_PLLREFE_MISC to turn on the PLL when enabled */ -#define TEGRA186_CLK_PLLREFE_IDDQ 308 -/** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI */ -#define TEGRA186_CLK_QSPI_OUT 309 -/** - * @brief GPC2CLK-div-2 - * @details fixed /2 divider. Output frequency is - * TEGRA186_CLK_GPC2CLK/2. The frequency of this clock is the - * frequency at which the GPU graphics engine runs. */ -#define TEGRA186_CLK_GPCCLK 310 -/** @brief output of divider CLK_RST_CONTROLLER_AON_NIC_RATE */ -#define TEGRA186_CLK_AON_NIC 450 -/** @brief output of divider CLK_RST_CONTROLLER_SCE_NIC_RATE */ -#define TEGRA186_CLK_SCE_NIC 451 -/** Fixed 100MHz PLL for PCIe, SATA and superspeed USB */ -#define TEGRA186_CLK_PLLE 512 -/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC_BASE */ -#define TEGRA186_CLK_PLLC 513 -/** Fixed 408MHz PLL for use by peripheral clocks */ -#define TEGRA186_CLK_PLLP 516 -/** @deprecated */ -#define TEGRA186_CLK_PLL_P TEGRA186_CLK_PLLP -/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD_BASE for use by DSI */ -#define TEGRA186_CLK_PLLD 518 -/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD2_BASE for use by HDMI or DP */ -#define TEGRA186_CLK_PLLD2 519 -/** - * @brief PLL controlled by CLK_RST_CONTROLLER_PLLREFE_BASE. - * @details Note that this clock only controls the VCO output, before - * the post-divider. See TEGRA186_CLK_PLLREFE_OUT1 for more - * information. - */ -#define TEGRA186_CLK_PLLREFE_VCO 520 -/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC2_BASE */ -#define TEGRA186_CLK_PLLC2 521 -/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC3_BASE */ -#define TEGRA186_CLK_PLLC3 522 -/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLDP_BASE for use as the DP link clock */ -#define TEGRA186_CLK_PLLDP 523 -/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */ -#define TEGRA186_CLK_PLLC4_VCO 524 -/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLA1_BASE for use by audio clocks */ -#define TEGRA186_CLK_PLLA1 525 -/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLNVCSI_BASE */ -#define TEGRA186_CLK_PLLNVCSI 526 -/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLDISPHUB_BASE */ -#define TEGRA186_CLK_PLLDISPHUB 527 -/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD3_BASE for use by HDMI or DP */ -#define TEGRA186_CLK_PLLD3 528 -/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLBPMPCAM_BASE */ -#define TEGRA186_CLK_PLLBPMPCAM 531 -/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLAON_BASE for use by IP blocks in the AON domain */ -#define TEGRA186_CLK_PLLAON 532 -/** Fixed frequency 960MHz PLL for USB and EAVB */ -#define TEGRA186_CLK_PLLU 533 -/** fixed /2 divider. Output frequency is TEGRA186_CLK_PLLC4_VCO/2 */ -#define TEGRA186_CLK_PLLC4_VCO_DIV2 535 -/** @brief NAFLL clock source for AXI_CBB */ -#define TEGRA186_CLK_NAFLL_AXI_CBB 564 -/** @brief NAFLL clock source for BPMP */ -#define TEGRA186_CLK_NAFLL_BPMP 565 -/** @brief NAFLL clock source for ISP */ -#define TEGRA186_CLK_NAFLL_ISP 566 -/** @brief NAFLL clock source for NVDEC */ -#define TEGRA186_CLK_NAFLL_NVDEC 567 -/** @brief NAFLL clock source for NVENC */ -#define TEGRA186_CLK_NAFLL_NVENC 568 -/** @brief NAFLL clock source for NVJPG */ -#define TEGRA186_CLK_NAFLL_NVJPG 569 -/** @brief NAFLL clock source for SCE */ -#define TEGRA186_CLK_NAFLL_SCE 570 -/** @brief NAFLL clock source for SE */ -#define TEGRA186_CLK_NAFLL_SE 571 -/** @brief NAFLL clock source for TSEC */ -#define TEGRA186_CLK_NAFLL_TSEC 572 -/** @brief NAFLL clock source for TSECB */ -#define TEGRA186_CLK_NAFLL_TSECB 573 -/** @brief NAFLL clock source for VI */ -#define TEGRA186_CLK_NAFLL_VI 574 -/** @brief NAFLL clock source for VIC */ -#define TEGRA186_CLK_NAFLL_VIC 575 -/** @brief NAFLL clock source for DISP */ -#define TEGRA186_CLK_NAFLL_DISP 576 -/** @brief NAFLL clock source for GPU */ -#define TEGRA186_CLK_NAFLL_GPU 577 -/** @brief NAFLL clock source for M-CPU cluster */ -#define TEGRA186_CLK_NAFLL_MCPU 578 -/** @brief NAFLL clock source for B-CPU cluster */ -#define TEGRA186_CLK_NAFLL_BCPU 579 -/** @brief input from Tegra's CLK_32K_IN pad */ -#define TEGRA186_CLK_CLK_32K 608 -/** @brief output of divider CLK_RST_CONTROLLER_CLK_M_DIVIDE */ -#define TEGRA186_CLK_CLK_M 609 -/** @brief output of divider PLL_REF_DIV in CLK_RST_CONTROLLER_OSC_CTRL */ -#define TEGRA186_CLK_PLL_REF 610 -/** @brief input from Tegra's XTAL_IN */ -#define TEGRA186_CLK_OSC 612 -/** @brief clock recovered from EAVB input */ -#define TEGRA186_CLK_EQOS_RX_INPUT 613 -/** @brief clock recovered from DTV input */ -#define TEGRA186_CLK_DTV_INPUT 614 -/** @brief SOR0 brick output which feeds into SOR0_CLK_SEL mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0*/ -#define TEGRA186_CLK_SOR0_PAD_CLKOUT 615 -/** @brief SOR1 brick output which feeds into SOR1_CLK_SEL mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1*/ -#define TEGRA186_CLK_SOR1_PAD_CLKOUT 616 -/** @brief clock recovered from I2S1 input */ -#define TEGRA186_CLK_I2S1_SYNC_INPUT 617 -/** @brief clock recovered from I2S2 input */ -#define TEGRA186_CLK_I2S2_SYNC_INPUT 618 -/** @brief clock recovered from I2S3 input */ -#define TEGRA186_CLK_I2S3_SYNC_INPUT 619 -/** @brief clock recovered from I2S4 input */ -#define TEGRA186_CLK_I2S4_SYNC_INPUT 620 -/** @brief clock recovered from I2S5 input */ -#define TEGRA186_CLK_I2S5_SYNC_INPUT 621 -/** @brief clock recovered from I2S6 input */ -#define TEGRA186_CLK_I2S6_SYNC_INPUT 622 -/** @brief clock recovered from SPDIFIN input */ -#define TEGRA186_CLK_SPDIFIN_SYNC_INPUT 623 - -/** - * @brief subject to change - * @details maximum clock identifier value plus one. - */ -#define TEGRA186_CLK_CLK_MAX 624 - -/** @} */ - -#endif diff --git a/include/dt-bindings/clock/tegra20-car.h b/include/dt-bindings/clock/tegra20-car.h deleted file mode 100644 index 04500b243a4..00000000000 --- a/include/dt-bindings/clock/tegra20-car.h +++ /dev/null @@ -1,158 +0,0 @@ -/* - * This header provides constants for binding nvidia,tegra20-car. - * - * The first 96 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB - * registers. These IDs often match those in the CAR's RST_DEVICES registers, - * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In - * this case, those clocks are assigned IDs above 95 in order to highlight - * this issue. Implementations that interpret these clock IDs as bit values - * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to - * explicitly handle these special cases. - * - * The balance of the clocks controlled by the CAR are assigned IDs of 96 and - * above. - */ - -#ifndef _DT_BINDINGS_CLOCK_TEGRA20_CAR_H -#define _DT_BINDINGS_CLOCK_TEGRA20_CAR_H - -#define TEGRA20_CLK_CPU 0 -/* 1 */ -/* 2 */ -#define TEGRA20_CLK_AC97 3 -#define TEGRA20_CLK_RTC 4 -#define TEGRA20_CLK_TIMER 5 -#define TEGRA20_CLK_UARTA 6 -/* 7 (register bit affects uart2 and vfir) */ -#define TEGRA20_CLK_GPIO 8 -#define TEGRA20_CLK_SDMMC2 9 -/* 10 (register bit affects spdif_in and spdif_out) */ -#define TEGRA20_CLK_I2S1 11 -#define TEGRA20_CLK_I2C1 12 -#define TEGRA20_CLK_NDFLASH 13 -#define TEGRA20_CLK_SDMMC1 14 -#define TEGRA20_CLK_SDMMC4 15 -#define TEGRA20_CLK_TWC 16 -#define TEGRA20_CLK_PWM 17 -#define TEGRA20_CLK_I2S2 18 -#define TEGRA20_CLK_EPP 19 -/* 20 (register bit affects vi and vi_sensor) */ -#define TEGRA20_CLK_GR2D 21 -#define TEGRA20_CLK_USBD 22 -#define TEGRA20_CLK_ISP 23 -#define TEGRA20_CLK_GR3D 24 -#define TEGRA20_CLK_IDE 25 -#define TEGRA20_CLK_DISP2 26 -#define TEGRA20_CLK_DISP1 27 -#define TEGRA20_CLK_HOST1X 28 -#define TEGRA20_CLK_VCP 29 -/* 30 */ -#define TEGRA20_CLK_CACHE2 31 - -#define TEGRA20_CLK_MC 32 -#define TEGRA20_CLK_AHBDMA 33 -#define TEGRA20_CLK_APBDMA 34 -/* 35 */ -#define TEGRA20_CLK_KBC 36 -#define TEGRA20_CLK_STAT_MON 37 -#define TEGRA20_CLK_PMC 38 -#define TEGRA20_CLK_FUSE 39 -#define TEGRA20_CLK_KFUSE 40 -#define TEGRA20_CLK_SBC1 41 -#define TEGRA20_CLK_NOR 42 -#define TEGRA20_CLK_SPI 43 -#define TEGRA20_CLK_SBC2 44 -#define TEGRA20_CLK_XIO 45 -#define TEGRA20_CLK_SBC3 46 -#define TEGRA20_CLK_DVC 47 -#define TEGRA20_CLK_DSI 48 -/* 49 (register bit affects tvo and cve) */ -#define TEGRA20_CLK_MIPI 50 -#define TEGRA20_CLK_HDMI 51 -#define TEGRA20_CLK_CSI 52 -#define TEGRA20_CLK_TVDAC 53 -#define TEGRA20_CLK_I2C2 54 -#define TEGRA20_CLK_UARTC 55 -/* 56 */ -#define TEGRA20_CLK_EMC 57 -#define TEGRA20_CLK_USB2 58 -#define TEGRA20_CLK_USB3 59 -#define TEGRA20_CLK_MPE 60 -#define TEGRA20_CLK_VDE 61 -#define TEGRA20_CLK_BSEA 62 -#define TEGRA20_CLK_BSEV 63 - -#define TEGRA20_CLK_SPEEDO 64 -#define TEGRA20_CLK_UARTD 65 -#define TEGRA20_CLK_UARTE 66 -#define TEGRA20_CLK_I2C3 67 -#define TEGRA20_CLK_SBC4 68 -#define TEGRA20_CLK_SDMMC3 69 -#define TEGRA20_CLK_PEX 70 -#define TEGRA20_CLK_OWR 71 -#define TEGRA20_CLK_AFI 72 -#define TEGRA20_CLK_CSITE 73 -/* 74 */ -#define TEGRA20_CLK_AVPUCQ 75 -#define TEGRA20_CLK_LA 76 -/* 77 */ -/* 78 */ -/* 79 */ -/* 80 */ -/* 81 */ -/* 82 */ -/* 83 */ -#define TEGRA20_CLK_IRAMA 84 -#define TEGRA20_CLK_IRAMB 85 -#define TEGRA20_CLK_IRAMC 86 -#define TEGRA20_CLK_IRAMD 87 -#define TEGRA20_CLK_CRAM2 88 -#define TEGRA20_CLK_AUDIO_2X 89 /* a/k/a audio_2x_sync_clk */ -#define TEGRA20_CLK_CLK_D 90 -/* 91 */ -#define TEGRA20_CLK_CSUS 92 -#define TEGRA20_CLK_CDEV2 93 -#define TEGRA20_CLK_CDEV1 94 -/* 95 */ - -#define TEGRA20_CLK_UARTB 96 -#define TEGRA20_CLK_VFIR 97 -#define TEGRA20_CLK_SPDIF_IN 98 -#define TEGRA20_CLK_SPDIF_OUT 99 -#define TEGRA20_CLK_VI 100 -#define TEGRA20_CLK_VI_SENSOR 101 -#define TEGRA20_CLK_TVO 102 -#define TEGRA20_CLK_CVE 103 -#define TEGRA20_CLK_OSC 104 -#define TEGRA20_CLK_CLK_32K 105 /* a/k/a clk_s */ -#define TEGRA20_CLK_CLK_M 106 -#define TEGRA20_CLK_SCLK 107 -#define TEGRA20_CLK_CCLK 108 -#define TEGRA20_CLK_HCLK 109 -#define TEGRA20_CLK_PCLK 110 -#define TEGRA20_CLK_BLINK 111 -#define TEGRA20_CLK_PLL_A 112 -#define TEGRA20_CLK_PLL_A_OUT0 113 -#define TEGRA20_CLK_PLL_C 114 -#define TEGRA20_CLK_PLL_C_OUT1 115 -#define TEGRA20_CLK_PLL_D 116 -#define TEGRA20_CLK_PLL_D_OUT0 117 -#define TEGRA20_CLK_PLL_E 118 -#define TEGRA20_CLK_PLL_M 119 -#define TEGRA20_CLK_PLL_M_OUT1 120 -#define TEGRA20_CLK_PLL_P 121 -#define TEGRA20_CLK_PLL_P_OUT1 122 -#define TEGRA20_CLK_PLL_P_OUT2 123 -#define TEGRA20_CLK_PLL_P_OUT3 124 -#define TEGRA20_CLK_PLL_P_OUT4 125 -#define TEGRA20_CLK_PLL_S 126 -#define TEGRA20_CLK_PLL_U 127 - -#define TEGRA20_CLK_PLL_X 128 -#define TEGRA20_CLK_COP 129 /* a/k/a avp */ -#define TEGRA20_CLK_AUDIO 130 /* a/k/a audio_sync_clk */ -#define TEGRA20_CLK_PLL_REF 131 -#define TEGRA20_CLK_TWD 132 -#define TEGRA20_CLK_CLK_MAX 133 - -#endif /* _DT_BINDINGS_CLOCK_TEGRA20_CAR_H */ diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h deleted file mode 100644 index eddac16800d..00000000000 --- a/include/dt-bindings/clock/tegra210-car.h +++ /dev/null @@ -1,400 +0,0 @@ -/* - * This header provides constants for binding nvidia,tegra210-car. - * - * The first 224 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB - * registers. These IDs often match those in the CAR's RST_DEVICES registers, - * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In - * this case, those clocks are assigned IDs above 224 in order to highlight - * this issue. Implementations that interpret these clock IDs as bit values - * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to - * explicitly handle these special cases. - * - * The balance of the clocks controlled by the CAR are assigned IDs of 224 and - * above. - */ - -#ifndef _DT_BINDINGS_CLOCK_TEGRA210_CAR_H -#define _DT_BINDINGS_CLOCK_TEGRA210_CAR_H - -/* 0 */ -/* 1 */ -/* 2 */ -#define TEGRA210_CLK_ISPB 3 -#define TEGRA210_CLK_RTC 4 -#define TEGRA210_CLK_TIMER 5 -#define TEGRA210_CLK_UARTA 6 -/* 7 (register bit affects uartb and vfir) */ -#define TEGRA210_CLK_GPIO 8 -#define TEGRA210_CLK_SDMMC2 9 -/* 10 (register bit affects spdif_in and spdif_out) */ -#define TEGRA210_CLK_I2S1 11 -#define TEGRA210_CLK_I2C1 12 -/* 13 */ -#define TEGRA210_CLK_SDMMC1 14 -#define TEGRA210_CLK_SDMMC4 15 -/* 16 */ -#define TEGRA210_CLK_PWM 17 -#define TEGRA210_CLK_I2S2 18 -/* 19 */ -/* 20 (register bit affects vi and vi_sensor) */ -/* 21 */ -#define TEGRA210_CLK_USBD 22 -#define TEGRA210_CLK_ISP 23 -/* 24 */ -/* 25 */ -#define TEGRA210_CLK_DISP2 26 -#define TEGRA210_CLK_DISP1 27 -#define TEGRA210_CLK_HOST1X 28 -/* 29 */ -#define TEGRA210_CLK_I2S0 30 -/* 31 */ - -#define TEGRA210_CLK_MC 32 -#define TEGRA210_CLK_AHBDMA 33 -#define TEGRA210_CLK_APBDMA 34 -/* 35 */ -/* 36 */ -/* 37 */ -#define TEGRA210_CLK_PMC 38 -/* 39 (register bit affects fuse and fuse_burn) */ -#define TEGRA210_CLK_KFUSE 40 -#define TEGRA210_CLK_SBC1 41 -/* 42 */ -/* 43 */ -#define TEGRA210_CLK_SBC2 44 -/* 45 */ -#define TEGRA210_CLK_SBC3 46 -#define TEGRA210_CLK_I2C5 47 -#define TEGRA210_CLK_DSIA 48 -/* 49 */ -/* 50 */ -/* 51 */ -#define TEGRA210_CLK_CSI 52 -/* 53 */ -#define TEGRA210_CLK_I2C2 54 -#define TEGRA210_CLK_UARTC 55 -#define TEGRA210_CLK_MIPI_CAL 56 -#define TEGRA210_CLK_EMC 57 -#define TEGRA210_CLK_USB2 58 -/* 59 */ -/* 60 */ -/* 61 */ -/* 62 */ -#define TEGRA210_CLK_BSEV 63 - -/* 64 */ -#define TEGRA210_CLK_UARTD 65 -/* 66 */ -#define TEGRA210_CLK_I2C3 67 -#define TEGRA210_CLK_SBC4 68 -#define TEGRA210_CLK_SDMMC3 69 -#define TEGRA210_CLK_PCIE 70 -#define TEGRA210_CLK_OWR 71 -#define TEGRA210_CLK_AFI 72 -#define TEGRA210_CLK_CSITE 73 -/* 74 */ -/* 75 */ -/* 76 */ -/* 77 */ -#define TEGRA210_CLK_SOC_THERM 78 -#define TEGRA210_CLK_DTV 79 -/* 80 */ -#define TEGRA210_CLK_I2CSLOW 81 -#define TEGRA210_CLK_DSIB 82 -#define TEGRA210_CLK_TSEC 83 -/* 84 */ -/* 85 */ -/* 86 */ -/* 87 */ -/* 88 */ -#define TEGRA210_CLK_XUSB_HOST 89 -/* 90 */ -/* 91 */ -#define TEGRA210_CLK_CSUS 92 -/* 93 */ -/* 94 */ -/* 95 (bit affects xusb_dev and xusb_dev_src) */ - -/* 96 */ -/* 97 */ -/* 98 */ -#define TEGRA210_CLK_MSELECT 99 -#define TEGRA210_CLK_TSENSOR 100 -#define TEGRA210_CLK_I2S3 101 -#define TEGRA210_CLK_I2S4 102 -#define TEGRA210_CLK_I2C4 103 -/* 104 */ -/* 105 */ -#define TEGRA210_CLK_D_AUDIO 106 -#define TEGRA210_CLK_APB2APE 107 -/* 108 */ -/* 109 */ -/* 110 */ -#define TEGRA210_CLK_HDA2CODEC_2X 111 -/* 112 */ -/* 113 */ -/* 114 */ -/* 115 */ -/* 116 */ -/* 117 */ -#define TEGRA210_CLK_SPDIF_2X 118 -#define TEGRA210_CLK_ACTMON 119 -#define TEGRA210_CLK_EXTERN1 120 -#define TEGRA210_CLK_EXTERN2 121 -#define TEGRA210_CLK_EXTERN3 122 -#define TEGRA210_CLK_SATA_OOB 123 -#define TEGRA210_CLK_SATA 124 -#define TEGRA210_CLK_HDA 125 -/* 126 */ -/* 127 */ - -#define TEGRA210_CLK_HDA2HDMI 128 -/* 129 */ -/* 130 */ -/* 131 */ -/* 132 */ -/* 133 */ -/* 134 */ -/* 135 */ -/* 136 */ -/* 137 */ -/* 138 */ -/* 139 */ -/* 140 */ -/* 141 */ -/* 142 */ -/* (bit affects xusb_falcon_src, xusb_fs_src, xusb_host_src and xusb_ss_src) */ -#define TEGRA210_CLK_XUSB_GATE 143 -#define TEGRA210_CLK_CILAB 144 -#define TEGRA210_CLK_CILCD 145 -#define TEGRA210_CLK_CILE 146 -#define TEGRA210_CLK_DSIALP 147 -#define TEGRA210_CLK_DSIBLP 148 -#define TEGRA210_CLK_ENTROPY 149 -/* 150 */ -/* 151 */ -/* 152 */ -/* 153 */ -/* 154 */ -/* 155 (bit affects dfll_ref and dfll_soc) */ -#define TEGRA210_CLK_XUSB_SS 156 -/* 157 */ -/* 158 */ -/* 159 */ - -/* 160 */ -#define TEGRA210_CLK_DMIC1 161 -#define TEGRA210_CLK_DMIC2 162 -/* 163 */ -/* 164 */ -/* 165 */ -#define TEGRA210_CLK_I2C6 166 -/* 167 */ -/* 168 */ -/* 169 */ -/* 170 */ -#define TEGRA210_CLK_VIM2_CLK 171 -/* 172 */ -#define TEGRA210_CLK_MIPIBIF 173 -/* 174 */ -/* 175 */ -/* 176 */ -#define TEGRA210_CLK_CLK72MHZ 177 -#define TEGRA210_CLK_VIC03 178 -/* 179 */ -/* 180 */ -#define TEGRA210_CLK_DPAUX 181 -#define TEGRA210_CLK_SOR0 182 -#define TEGRA210_CLK_SOR1 183 -#define TEGRA210_CLK_GPU 184 -#define TEGRA210_CLK_DBGAPB 185 -/* 186 */ -#define TEGRA210_CLK_PLL_P_OUT_ADSP 187 -/* 188 */ -#define TEGRA210_CLK_PLL_G_REF 189 -/* 190 */ -/* 191 */ - -/* 192 */ -#define TEGRA210_CLK_SDMMC_LEGACY 193 -#define TEGRA210_CLK_NVDEC 194 -#define TEGRA210_CLK_NVJPG 195 -/* 196 */ -#define TEGRA210_CLK_DMIC3 197 -#define TEGRA210_CLK_APE 198 -/* 199 */ -/* 200 */ -/* 201 */ -#define TEGRA210_CLK_MAUD 202 -/* 203 */ -/* 204 */ -/* 205 */ -#define TEGRA210_CLK_TSECB 206 -#define TEGRA210_CLK_DPAUX1 207 -#define TEGRA210_CLK_VI_I2C 208 -#define TEGRA210_CLK_HSIC_TRK 209 -#define TEGRA210_CLK_USB2_TRK 210 -#define TEGRA210_CLK_QSPI 211 -#define TEGRA210_CLK_UARTAPE 212 -/* 213 */ -/* 214 */ -/* 215 */ -/* 216 */ -/* 217 */ -/* 218 */ -#define TEGRA210_CLK_NVENC 219 -/* 220 */ -/* 221 */ -#define TEGRA210_CLK_SOR_SAFE 222 -#define TEGRA210_CLK_PLL_P_OUT_CPU 223 - -#define TEGRA210_CLK_UARTB 224 -#define TEGRA210_CLK_VFIR 225 -#define TEGRA210_CLK_SPDIF_IN 226 -#define TEGRA210_CLK_SPDIF_OUT 227 -#define TEGRA210_CLK_VI 228 -#define TEGRA210_CLK_VI_SENSOR 229 -#define TEGRA210_CLK_FUSE 230 -#define TEGRA210_CLK_FUSE_BURN 231 -#define TEGRA210_CLK_CLK_32K 232 -#define TEGRA210_CLK_CLK_M 233 -#define TEGRA210_CLK_CLK_M_DIV2 234 -#define TEGRA210_CLK_CLK_M_DIV4 235 -#define TEGRA210_CLK_PLL_REF 236 -#define TEGRA210_CLK_PLL_C 237 -#define TEGRA210_CLK_PLL_C_OUT1 238 -#define TEGRA210_CLK_PLL_C2 239 -#define TEGRA210_CLK_PLL_C3 240 -#define TEGRA210_CLK_PLL_M 241 -#define TEGRA210_CLK_PLL_M_OUT1 242 -#define TEGRA210_CLK_PLL_P 243 -#define TEGRA210_CLK_PLL_P_OUT1 244 -#define TEGRA210_CLK_PLL_P_OUT2 245 -#define TEGRA210_CLK_PLL_P_OUT3 246 -#define TEGRA210_CLK_PLL_P_OUT4 247 -#define TEGRA210_CLK_PLL_A 248 -#define TEGRA210_CLK_PLL_A_OUT0 249 -#define TEGRA210_CLK_PLL_D 250 -#define TEGRA210_CLK_PLL_D_OUT0 251 -#define TEGRA210_CLK_PLL_D2 252 -#define TEGRA210_CLK_PLL_D2_OUT0 253 -#define TEGRA210_CLK_PLL_U 254 -#define TEGRA210_CLK_PLL_U_480M 255 - -#define TEGRA210_CLK_PLL_U_60M 256 -#define TEGRA210_CLK_PLL_U_48M 257 -/* 258 */ -#define TEGRA210_CLK_PLL_X 259 -#define TEGRA210_CLK_PLL_X_OUT0 260 -#define TEGRA210_CLK_PLL_RE_VCO 261 -#define TEGRA210_CLK_PLL_RE_OUT 262 -#define TEGRA210_CLK_PLL_E 263 -#define TEGRA210_CLK_SPDIF_IN_SYNC 264 -#define TEGRA210_CLK_I2S0_SYNC 265 -#define TEGRA210_CLK_I2S1_SYNC 266 -#define TEGRA210_CLK_I2S2_SYNC 267 -#define TEGRA210_CLK_I2S3_SYNC 268 -#define TEGRA210_CLK_I2S4_SYNC 269 -#define TEGRA210_CLK_VIMCLK_SYNC 270 -#define TEGRA210_CLK_AUDIO0 271 -#define TEGRA210_CLK_AUDIO1 272 -#define TEGRA210_CLK_AUDIO2 273 -#define TEGRA210_CLK_AUDIO3 274 -#define TEGRA210_CLK_AUDIO4 275 -#define TEGRA210_CLK_SPDIF 276 -#define TEGRA210_CLK_CLK_OUT_1 277 -#define TEGRA210_CLK_CLK_OUT_2 278 -#define TEGRA210_CLK_CLK_OUT_3 279 -#define TEGRA210_CLK_BLINK 280 -/* 281 */ -/* 282 */ -/* 283 */ -#define TEGRA210_CLK_XUSB_HOST_SRC 284 -#define TEGRA210_CLK_XUSB_FALCON_SRC 285 -#define TEGRA210_CLK_XUSB_FS_SRC 286 -#define TEGRA210_CLK_XUSB_SS_SRC 287 - -#define TEGRA210_CLK_XUSB_DEV_SRC 288 -#define TEGRA210_CLK_XUSB_DEV 289 -#define TEGRA210_CLK_XUSB_HS_SRC 290 -#define TEGRA210_CLK_SCLK 291 -#define TEGRA210_CLK_HCLK 292 -#define TEGRA210_CLK_PCLK 293 -#define TEGRA210_CLK_CCLK_G 294 -#define TEGRA210_CLK_CCLK_LP 295 -#define TEGRA210_CLK_DFLL_REF 296 -#define TEGRA210_CLK_DFLL_SOC 297 -#define TEGRA210_CLK_VI_SENSOR2 298 -#define TEGRA210_CLK_PLL_P_OUT5 299 -#define TEGRA210_CLK_CML0 300 -#define TEGRA210_CLK_CML1 301 -#define TEGRA210_CLK_PLL_C4 302 -#define TEGRA210_CLK_PLL_DP 303 -#define TEGRA210_CLK_PLL_E_MUX 304 -#define TEGRA210_CLK_PLL_MB 305 -#define TEGRA210_CLK_PLL_A1 306 -#define TEGRA210_CLK_PLL_D_DSI_OUT 307 -#define TEGRA210_CLK_PLL_C4_OUT0 308 -#define TEGRA210_CLK_PLL_C4_OUT1 309 -#define TEGRA210_CLK_PLL_C4_OUT2 310 -#define TEGRA210_CLK_PLL_C4_OUT3 311 -#define TEGRA210_CLK_PLL_U_OUT 312 -#define TEGRA210_CLK_PLL_U_OUT1 313 -#define TEGRA210_CLK_PLL_U_OUT2 314 -#define TEGRA210_CLK_USB2_HSIC_TRK 315 -#define TEGRA210_CLK_PLL_P_OUT_HSIO 316 -#define TEGRA210_CLK_PLL_P_OUT_XUSB 317 -#define TEGRA210_CLK_XUSB_SSP_SRC 318 -#define TEGRA210_CLK_PLL_RE_OUT1 319 -/* 320 */ -/* 321 */ -/* 322 */ -/* 323 */ -/* 324 */ -/* 325 */ -/* 326 */ -/* 327 */ -/* 328 */ -/* 329 */ -/* 330 */ -/* 331 */ -/* 332 */ -/* 333 */ -/* 334 */ -/* 335 */ -/* 336 */ -/* 337 */ -/* 338 */ -/* 339 */ -/* 340 */ -/* 341 */ -/* 342 */ -/* 343 */ -/* 344 */ -/* 345 */ -/* 346 */ -/* 347 */ -/* 348 */ -/* 349 */ - -#define TEGRA210_CLK_AUDIO0_MUX 350 -#define TEGRA210_CLK_AUDIO1_MUX 351 -#define TEGRA210_CLK_AUDIO2_MUX 352 -#define TEGRA210_CLK_AUDIO3_MUX 353 -#define TEGRA210_CLK_AUDIO4_MUX 354 -#define TEGRA210_CLK_SPDIF_MUX 355 -#define TEGRA210_CLK_CLK_OUT_1_MUX 356 -#define TEGRA210_CLK_CLK_OUT_2_MUX 357 -#define TEGRA210_CLK_CLK_OUT_3_MUX 358 -#define TEGRA210_CLK_DSIA_MUX 359 -#define TEGRA210_CLK_DSIB_MUX 360 -#define TEGRA210_CLK_SOR0_LVDS 361 -#define TEGRA210_CLK_XUSB_SS_DIV2 362 - -#define TEGRA210_CLK_PLL_M_UD 363 -#define TEGRA210_CLK_PLL_C_UD 364 -#define TEGRA210_CLK_SCLK_MUX 365 - -#define TEGRA210_CLK_CLK_MAX 366 - -#endif /* _DT_BINDINGS_CLOCK_TEGRA210_CAR_H */ diff --git a/include/dt-bindings/clock/tegra30-car.h b/include/dt-bindings/clock/tegra30-car.h deleted file mode 100644 index 889e49ba0aa..00000000000 --- a/include/dt-bindings/clock/tegra30-car.h +++ /dev/null @@ -1,273 +0,0 @@ -/* - * This header provides constants for binding nvidia,tegra30-car. - * - * The first 130 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB - * registers. These IDs often match those in the CAR's RST_DEVICES registers, - * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In - * this case, those clocks are assigned IDs above 160 in order to highlight - * this issue. Implementations that interpret these clock IDs as bit values - * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to - * explicitly handle these special cases. - * - * The balance of the clocks controlled by the CAR are assigned IDs of 160 and - * above. - */ - -#ifndef _DT_BINDINGS_CLOCK_TEGRA30_CAR_H -#define _DT_BINDINGS_CLOCK_TEGRA30_CAR_H - -#define TEGRA30_CLK_CPU 0 -/* 1 */ -/* 2 */ -/* 3 */ -#define TEGRA30_CLK_RTC 4 -#define TEGRA30_CLK_TIMER 5 -#define TEGRA30_CLK_UARTA 6 -/* 7 (register bit affects uartb and vfir) */ -#define TEGRA30_CLK_GPIO 8 -#define TEGRA30_CLK_SDMMC2 9 -/* 10 (register bit affects spdif_in and spdif_out) */ -#define TEGRA30_CLK_I2S1 11 -#define TEGRA30_CLK_I2C1 12 -#define TEGRA30_CLK_NDFLASH 13 -#define TEGRA30_CLK_SDMMC1 14 -#define TEGRA30_CLK_SDMMC4 15 -/* 16 */ -#define TEGRA30_CLK_PWM 17 -#define TEGRA30_CLK_I2S2 18 -#define TEGRA30_CLK_EPP 19 -/* 20 (register bit affects vi and vi_sensor) */ -#define TEGRA30_CLK_GR2D 21 -#define TEGRA30_CLK_USBD 22 -#define TEGRA30_CLK_ISP 23 -#define TEGRA30_CLK_GR3D 24 -/* 25 */ -#define TEGRA30_CLK_DISP2 26 -#define TEGRA30_CLK_DISP1 27 -#define TEGRA30_CLK_HOST1X 28 -#define TEGRA30_CLK_VCP 29 -#define TEGRA30_CLK_I2S0 30 -#define TEGRA30_CLK_COP_CACHE 31 - -#define TEGRA30_CLK_MC 32 -#define TEGRA30_CLK_AHBDMA 33 -#define TEGRA30_CLK_APBDMA 34 -/* 35 */ -#define TEGRA30_CLK_KBC 36 -#define TEGRA30_CLK_STATMON 37 -#define TEGRA30_CLK_PMC 38 -/* 39 (register bit affects fuse and fuse_burn) */ -#define TEGRA30_CLK_KFUSE 40 -#define TEGRA30_CLK_SBC1 41 -#define TEGRA30_CLK_NOR 42 -/* 43 */ -#define TEGRA30_CLK_SBC2 44 -/* 45 */ -#define TEGRA30_CLK_SBC3 46 -#define TEGRA30_CLK_I2C5 47 -#define TEGRA30_CLK_DSIA 48 -/* 49 (register bit affects cve and tvo) */ -#define TEGRA30_CLK_MIPI 50 -#define TEGRA30_CLK_HDMI 51 -#define TEGRA30_CLK_CSI 52 -#define TEGRA30_CLK_TVDAC 53 -#define TEGRA30_CLK_I2C2 54 -#define TEGRA30_CLK_UARTC 55 -/* 56 */ -#define TEGRA30_CLK_EMC 57 -#define TEGRA30_CLK_USB2 58 -#define TEGRA30_CLK_USB3 59 -#define TEGRA30_CLK_MPE 60 -#define TEGRA30_CLK_VDE 61 -#define TEGRA30_CLK_BSEA 62 -#define TEGRA30_CLK_BSEV 63 - -#define TEGRA30_CLK_SPEEDO 64 -#define TEGRA30_CLK_UARTD 65 -#define TEGRA30_CLK_UARTE 66 -#define TEGRA30_CLK_I2C3 67 -#define TEGRA30_CLK_SBC4 68 -#define TEGRA30_CLK_SDMMC3 69 -#define TEGRA30_CLK_PCIE 70 -#define TEGRA30_CLK_OWR 71 -#define TEGRA30_CLK_AFI 72 -#define TEGRA30_CLK_CSITE 73 -/* 74 */ -#define TEGRA30_CLK_AVPUCQ 75 -#define TEGRA30_CLK_LA 76 -/* 77 */ -/* 78 */ -#define TEGRA30_CLK_DTV 79 -#define TEGRA30_CLK_NDSPEED 80 -#define TEGRA30_CLK_I2CSLOW 81 -#define TEGRA30_CLK_DSIB 82 -/* 83 */ -#define TEGRA30_CLK_IRAMA 84 -#define TEGRA30_CLK_IRAMB 85 -#define TEGRA30_CLK_IRAMC 86 -#define TEGRA30_CLK_IRAMD 87 -#define TEGRA30_CLK_CRAM2 88 -/* 89 */ -#define TEGRA30_CLK_AUDIO_2X 90 /* a/k/a audio_2x_sync_clk */ -/* 91 */ -#define TEGRA30_CLK_CSUS 92 -#define TEGRA30_CLK_CDEV2 93 -#define TEGRA30_CLK_CDEV1 94 -/* 95 */ - -#define TEGRA30_CLK_CPU_G 96 -#define TEGRA30_CLK_CPU_LP 97 -#define TEGRA30_CLK_GR3D2 98 -#define TEGRA30_CLK_MSELECT 99 -#define TEGRA30_CLK_TSENSOR 100 -#define TEGRA30_CLK_I2S3 101 -#define TEGRA30_CLK_I2S4 102 -#define TEGRA30_CLK_I2C4 103 -#define TEGRA30_CLK_SBC5 104 -#define TEGRA30_CLK_SBC6 105 -#define TEGRA30_CLK_D_AUDIO 106 -#define TEGRA30_CLK_APBIF 107 -#define TEGRA30_CLK_DAM0 108 -#define TEGRA30_CLK_DAM1 109 -#define TEGRA30_CLK_DAM2 110 -#define TEGRA30_CLK_HDA2CODEC_2X 111 -#define TEGRA30_CLK_ATOMICS 112 -#define TEGRA30_CLK_AUDIO0_2X 113 -#define TEGRA30_CLK_AUDIO1_2X 114 -#define TEGRA30_CLK_AUDIO2_2X 115 -#define TEGRA30_CLK_AUDIO3_2X 116 -#define TEGRA30_CLK_AUDIO4_2X 117 -#define TEGRA30_CLK_SPDIF_2X 118 -#define TEGRA30_CLK_ACTMON 119 -#define TEGRA30_CLK_EXTERN1 120 -#define TEGRA30_CLK_EXTERN2 121 -#define TEGRA30_CLK_EXTERN3 122 -#define TEGRA30_CLK_SATA_OOB 123 -#define TEGRA30_CLK_SATA 124 -#define TEGRA30_CLK_HDA 125 -/* 126 */ -#define TEGRA30_CLK_SE 127 - -#define TEGRA30_CLK_HDA2HDMI 128 -#define TEGRA30_CLK_SATA_COLD 129 -/* 130 */ -/* 131 */ -/* 132 */ -/* 133 */ -/* 134 */ -/* 135 */ -/* 136 */ -/* 137 */ -/* 138 */ -/* 139 */ -/* 140 */ -/* 141 */ -/* 142 */ -/* 143 */ -/* 144 */ -/* 145 */ -/* 146 */ -/* 147 */ -/* 148 */ -/* 149 */ -/* 150 */ -/* 151 */ -/* 152 */ -/* 153 */ -/* 154 */ -/* 155 */ -/* 156 */ -/* 157 */ -/* 158 */ -/* 159 */ - -#define TEGRA30_CLK_UARTB 160 -#define TEGRA30_CLK_VFIR 161 -#define TEGRA30_CLK_SPDIF_IN 162 -#define TEGRA30_CLK_SPDIF_OUT 163 -#define TEGRA30_CLK_VI 164 -#define TEGRA30_CLK_VI_SENSOR 165 -#define TEGRA30_CLK_FUSE 166 -#define TEGRA30_CLK_FUSE_BURN 167 -#define TEGRA30_CLK_CVE 168 -#define TEGRA30_CLK_TVO 169 -#define TEGRA30_CLK_CLK_32K 170 -#define TEGRA30_CLK_CLK_M 171 -#define TEGRA30_CLK_CLK_M_DIV2 172 -#define TEGRA30_CLK_CLK_M_DIV4 173 -#define TEGRA30_CLK_PLL_REF 174 -#define TEGRA30_CLK_PLL_C 175 -#define TEGRA30_CLK_PLL_C_OUT1 176 -#define TEGRA30_CLK_PLL_M 177 -#define TEGRA30_CLK_PLL_M_OUT1 178 -#define TEGRA30_CLK_PLL_P 179 -#define TEGRA30_CLK_PLL_P_OUT1 180 -#define TEGRA30_CLK_PLL_P_OUT2 181 -#define TEGRA30_CLK_PLL_P_OUT3 182 -#define TEGRA30_CLK_PLL_P_OUT4 183 -#define TEGRA30_CLK_PLL_A 184 -#define TEGRA30_CLK_PLL_A_OUT0 185 -#define TEGRA30_CLK_PLL_D 186 -#define TEGRA30_CLK_PLL_D_OUT0 187 -#define TEGRA30_CLK_PLL_D2 188 -#define TEGRA30_CLK_PLL_D2_OUT0 189 -#define TEGRA30_CLK_PLL_U 190 -#define TEGRA30_CLK_PLL_X 191 - -#define TEGRA30_CLK_PLL_X_OUT0 192 -#define TEGRA30_CLK_PLL_E 193 -#define TEGRA30_CLK_SPDIF_IN_SYNC 194 -#define TEGRA30_CLK_I2S0_SYNC 195 -#define TEGRA30_CLK_I2S1_SYNC 196 -#define TEGRA30_CLK_I2S2_SYNC 197 -#define TEGRA30_CLK_I2S3_SYNC 198 -#define TEGRA30_CLK_I2S4_SYNC 199 -#define TEGRA30_CLK_VIMCLK_SYNC 200 -#define TEGRA30_CLK_AUDIO0 201 -#define TEGRA30_CLK_AUDIO1 202 -#define TEGRA30_CLK_AUDIO2 203 -#define TEGRA30_CLK_AUDIO3 204 -#define TEGRA30_CLK_AUDIO4 205 -#define TEGRA30_CLK_SPDIF 206 -#define TEGRA30_CLK_CLK_OUT_1 207 /* (extern1) */ -#define TEGRA30_CLK_CLK_OUT_2 208 /* (extern2) */ -#define TEGRA30_CLK_CLK_OUT_3 209 /* (extern3) */ -#define TEGRA30_CLK_SCLK 210 -#define TEGRA30_CLK_BLINK 211 -#define TEGRA30_CLK_CCLK_G 212 -#define TEGRA30_CLK_CCLK_LP 213 -#define TEGRA30_CLK_TWD 214 -#define TEGRA30_CLK_CML0 215 -#define TEGRA30_CLK_CML1 216 -#define TEGRA30_CLK_HCLK 217 -#define TEGRA30_CLK_PCLK 218 -/* 219 */ -/* 220 */ -/* 221 */ -/* 222 */ -/* 223 */ - -/* 288 */ -/* 289 */ -/* 290 */ -/* 291 */ -/* 292 */ -/* 293 */ -/* 294 */ -/* 295 */ -/* 296 */ -/* 297 */ -/* 298 */ -/* 299 */ -#define TEGRA30_CLK_CLK_OUT_1_MUX 300 -#define TEGRA30_CLK_CLK_OUT_2_MUX 301 -#define TEGRA30_CLK_CLK_OUT_3_MUX 302 -#define TEGRA30_CLK_AUDIO0_MUX 303 -#define TEGRA30_CLK_AUDIO1_MUX 304 -#define TEGRA30_CLK_AUDIO2_MUX 305 -#define TEGRA30_CLK_AUDIO3_MUX 306 -#define TEGRA30_CLK_AUDIO4_MUX 307 -#define TEGRA30_CLK_SPDIF_MUX 308 -#define TEGRA30_CLK_CLK_MAX 309 - -#endif /* _DT_BINDINGS_CLOCK_TEGRA30_CAR_H */ diff --git a/include/dt-bindings/clock/versaclock.h b/include/dt-bindings/clock/versaclock.h deleted file mode 100644 index c6a6a094656..00000000000 --- a/include/dt-bindings/clock/versaclock.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ - -/* This file defines field values used by the versaclock 6 family - * for defining output type - */ - -#define VC5_LVPECL 0 -#define VC5_CMOS 1 -#define VC5_HCSL33 2 -#define VC5_LVDS 3 -#define VC5_CMOS2 4 -#define VC5_CMOSD 5 -#define VC5_HCSL25 6 diff --git a/include/dt-bindings/clock/vf610-clock.h b/include/dt-bindings/clock/vf610-clock.h deleted file mode 100644 index 373644e4674..00000000000 --- a/include/dt-bindings/clock/vf610-clock.h +++ /dev/null @@ -1,202 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#ifndef __DT_BINDINGS_CLOCK_VF610_H -#define __DT_BINDINGS_CLOCK_VF610_H - -#define VF610_CLK_DUMMY 0 -#define VF610_CLK_SIRC_128K 1 -#define VF610_CLK_SIRC_32K 2 -#define VF610_CLK_FIRC 3 -#define VF610_CLK_SXOSC 4 -#define VF610_CLK_FXOSC 5 -#define VF610_CLK_FXOSC_HALF 6 -#define VF610_CLK_SLOW_CLK_SEL 7 -#define VF610_CLK_FASK_CLK_SEL 8 -#define VF610_CLK_AUDIO_EXT 9 -#define VF610_CLK_ENET_EXT 10 -#define VF610_CLK_PLL1_SYS 11 -#define VF610_CLK_PLL1_PFD1 12 -#define VF610_CLK_PLL1_PFD2 13 -#define VF610_CLK_PLL1_PFD3 14 -#define VF610_CLK_PLL1_PFD4 15 -#define VF610_CLK_PLL2_BUS 16 -#define VF610_CLK_PLL2_PFD1 17 -#define VF610_CLK_PLL2_PFD2 18 -#define VF610_CLK_PLL2_PFD3 19 -#define VF610_CLK_PLL2_PFD4 20 -#define VF610_CLK_PLL3_USB_OTG 21 -#define VF610_CLK_PLL3_PFD1 22 -#define VF610_CLK_PLL3_PFD2 23 -#define VF610_CLK_PLL3_PFD3 24 -#define VF610_CLK_PLL3_PFD4 25 -#define VF610_CLK_PLL4_AUDIO 26 -#define VF610_CLK_PLL5_ENET 27 -#define VF610_CLK_PLL6_VIDEO 28 -#define VF610_CLK_PLL3_MAIN_DIV 29 -#define VF610_CLK_PLL4_MAIN_DIV 30 -#define VF610_CLK_PLL6_MAIN_DIV 31 -#define VF610_CLK_PLL1_PFD_SEL 32 -#define VF610_CLK_PLL2_PFD_SEL 33 -#define VF610_CLK_SYS_SEL 34 -#define VF610_CLK_DDR_SEL 35 -#define VF610_CLK_SYS_BUS 36 -#define VF610_CLK_PLATFORM_BUS 37 -#define VF610_CLK_IPG_BUS 38 -#define VF610_CLK_UART0 39 -#define VF610_CLK_UART1 40 -#define VF610_CLK_UART2 41 -#define VF610_CLK_UART3 42 -#define VF610_CLK_UART4 43 -#define VF610_CLK_UART5 44 -#define VF610_CLK_PIT 45 -#define VF610_CLK_I2C0 46 -#define VF610_CLK_I2C1 47 -#define VF610_CLK_I2C2 48 -#define VF610_CLK_I2C3 49 -#define VF610_CLK_FTM0_EXT_SEL 50 -#define VF610_CLK_FTM0_FIX_SEL 51 -#define VF610_CLK_FTM0_EXT_FIX_EN 52 -#define VF610_CLK_FTM1_EXT_SEL 53 -#define VF610_CLK_FTM1_FIX_SEL 54 -#define VF610_CLK_FTM1_EXT_FIX_EN 55 -#define VF610_CLK_FTM2_EXT_SEL 56 -#define VF610_CLK_FTM2_FIX_SEL 57 -#define VF610_CLK_FTM2_EXT_FIX_EN 58 -#define VF610_CLK_FTM3_EXT_SEL 59 -#define VF610_CLK_FTM3_FIX_SEL 60 -#define VF610_CLK_FTM3_EXT_FIX_EN 61 -#define VF610_CLK_FTM0 62 -#define VF610_CLK_FTM1 63 -#define VF610_CLK_FTM2 64 -#define VF610_CLK_FTM3 65 -#define VF610_CLK_ENET_50M 66 -#define VF610_CLK_ENET_25M 67 -#define VF610_CLK_ENET_SEL 68 -#define VF610_CLK_ENET 69 -#define VF610_CLK_ENET_TS_SEL 70 -#define VF610_CLK_ENET_TS 71 -#define VF610_CLK_DSPI0 72 -#define VF610_CLK_DSPI1 73 -#define VF610_CLK_DSPI2 74 -#define VF610_CLK_DSPI3 75 -#define VF610_CLK_WDT 76 -#define VF610_CLK_ESDHC0_SEL 77 -#define VF610_CLK_ESDHC0_EN 78 -#define VF610_CLK_ESDHC0_DIV 79 -#define VF610_CLK_ESDHC0 80 -#define VF610_CLK_ESDHC1_SEL 81 -#define VF610_CLK_ESDHC1_EN 82 -#define VF610_CLK_ESDHC1_DIV 83 -#define VF610_CLK_ESDHC1 84 -#define VF610_CLK_DCU0_SEL 85 -#define VF610_CLK_DCU0_EN 86 -#define VF610_CLK_DCU0_DIV 87 -#define VF610_CLK_DCU0 88 -#define VF610_CLK_DCU1_SEL 89 -#define VF610_CLK_DCU1_EN 90 -#define VF610_CLK_DCU1_DIV 91 -#define VF610_CLK_DCU1 92 -#define VF610_CLK_ESAI_SEL 93 -#define VF610_CLK_ESAI_EN 94 -#define VF610_CLK_ESAI_DIV 95 -#define VF610_CLK_ESAI 96 -#define VF610_CLK_SAI0_SEL 97 -#define VF610_CLK_SAI0_EN 98 -#define VF610_CLK_SAI0_DIV 99 -#define VF610_CLK_SAI0 100 -#define VF610_CLK_SAI1_SEL 101 -#define VF610_CLK_SAI1_EN 102 -#define VF610_CLK_SAI1_DIV 103 -#define VF610_CLK_SAI1 104 -#define VF610_CLK_SAI2_SEL 105 -#define VF610_CLK_SAI2_EN 106 -#define VF610_CLK_SAI2_DIV 107 -#define VF610_CLK_SAI2 108 -#define VF610_CLK_SAI3_SEL 109 -#define VF610_CLK_SAI3_EN 110 -#define VF610_CLK_SAI3_DIV 111 -#define VF610_CLK_SAI3 112 -#define VF610_CLK_USBC0 113 -#define VF610_CLK_USBC1 114 -#define VF610_CLK_QSPI0_SEL 115 -#define VF610_CLK_QSPI0_EN 116 -#define VF610_CLK_QSPI0_X4_DIV 117 -#define VF610_CLK_QSPI0_X2_DIV 118 -#define VF610_CLK_QSPI0_X1_DIV 119 -#define VF610_CLK_QSPI1_SEL 120 -#define VF610_CLK_QSPI1_EN 121 -#define VF610_CLK_QSPI1_X4_DIV 122 -#define VF610_CLK_QSPI1_X2_DIV 123 -#define VF610_CLK_QSPI1_X1_DIV 124 -#define VF610_CLK_QSPI0 125 -#define VF610_CLK_QSPI1 126 -#define VF610_CLK_NFC_SEL 127 -#define VF610_CLK_NFC_EN 128 -#define VF610_CLK_NFC_PRE_DIV 129 -#define VF610_CLK_NFC_FRAC_DIV 130 -#define VF610_CLK_NFC_INV 131 -#define VF610_CLK_NFC 132 -#define VF610_CLK_VADC_SEL 133 -#define VF610_CLK_VADC_EN 134 -#define VF610_CLK_VADC_DIV 135 -#define VF610_CLK_VADC_DIV_HALF 136 -#define VF610_CLK_VADC 137 -#define VF610_CLK_ADC0 138 -#define VF610_CLK_ADC1 139 -#define VF610_CLK_DAC0 140 -#define VF610_CLK_DAC1 141 -#define VF610_CLK_FLEXCAN0 142 -#define VF610_CLK_FLEXCAN1 143 -#define VF610_CLK_ASRC 144 -#define VF610_CLK_GPU_SEL 145 -#define VF610_CLK_GPU_EN 146 -#define VF610_CLK_GPU2D 147 -#define VF610_CLK_ENET0 148 -#define VF610_CLK_ENET1 149 -#define VF610_CLK_DMAMUX0 150 -#define VF610_CLK_DMAMUX1 151 -#define VF610_CLK_DMAMUX2 152 -#define VF610_CLK_DMAMUX3 153 -#define VF610_CLK_FLEXCAN0_EN 154 -#define VF610_CLK_FLEXCAN1_EN 155 -#define VF610_CLK_PLL7_USB_HOST 156 -#define VF610_CLK_USBPHY0 157 -#define VF610_CLK_USBPHY1 158 -#define VF610_CLK_LVDS1_IN 159 -#define VF610_CLK_ANACLK1 160 -#define VF610_CLK_PLL1_BYPASS_SRC 161 -#define VF610_CLK_PLL2_BYPASS_SRC 162 -#define VF610_CLK_PLL3_BYPASS_SRC 163 -#define VF610_CLK_PLL4_BYPASS_SRC 164 -#define VF610_CLK_PLL5_BYPASS_SRC 165 -#define VF610_CLK_PLL6_BYPASS_SRC 166 -#define VF610_CLK_PLL7_BYPASS_SRC 167 -#define VF610_CLK_PLL1 168 -#define VF610_CLK_PLL2 169 -#define VF610_CLK_PLL3 170 -#define VF610_CLK_PLL4 171 -#define VF610_CLK_PLL5 172 -#define VF610_CLK_PLL6 173 -#define VF610_CLK_PLL7 174 -#define VF610_PLL1_BYPASS 175 -#define VF610_PLL2_BYPASS 176 -#define VF610_PLL3_BYPASS 177 -#define VF610_PLL4_BYPASS 178 -#define VF610_PLL5_BYPASS 179 -#define VF610_PLL6_BYPASS 180 -#define VF610_PLL7_BYPASS 181 -#define VF610_CLK_SNVS 182 -#define VF610_CLK_DAP 183 -#define VF610_CLK_OCOTP 184 -#define VF610_CLK_DDRMC 185 -#define VF610_CLK_WKPU 186 -#define VF610_CLK_TCON0 187 -#define VF610_CLK_TCON1 188 -#define VF610_CLK_CAAM 189 -#define VF610_CLK_CRC 190 -#define VF610_CLK_END 191 - -#endif /* __DT_BINDINGS_CLOCK_VF610_H */ diff --git a/include/dt-bindings/clock/xlnx-versal-clk.h b/include/dt-bindings/clock/xlnx-versal-clk.h deleted file mode 100644 index 264d634d226..00000000000 --- a/include/dt-bindings/clock/xlnx-versal-clk.h +++ /dev/null @@ -1,123 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2019 Xilinx Inc. - * - */ - -#ifndef _DT_BINDINGS_CLK_VERSAL_H -#define _DT_BINDINGS_CLK_VERSAL_H - -#define PMC_PLL 1 -#define APU_PLL 2 -#define RPU_PLL 3 -#define CPM_PLL 4 -#define NOC_PLL 5 -#define PLL_MAX 6 -#define PMC_PRESRC 7 -#define PMC_POSTCLK 8 -#define PMC_PLL_OUT 9 -#define PPLL 10 -#define NOC_PRESRC 11 -#define NOC_POSTCLK 12 -#define NOC_PLL_OUT 13 -#define NPLL 14 -#define APU_PRESRC 15 -#define APU_POSTCLK 16 -#define APU_PLL_OUT 17 -#define APLL 18 -#define RPU_PRESRC 19 -#define RPU_POSTCLK 20 -#define RPU_PLL_OUT 21 -#define RPLL 22 -#define CPM_PRESRC 23 -#define CPM_POSTCLK 24 -#define CPM_PLL_OUT 25 -#define CPLL 26 -#define PPLL_TO_XPD 27 -#define NPLL_TO_XPD 28 -#define APLL_TO_XPD 29 -#define RPLL_TO_XPD 30 -#define EFUSE_REF 31 -#define SYSMON_REF 32 -#define IRO_SUSPEND_REF 33 -#define USB_SUSPEND 34 -#define SWITCH_TIMEOUT 35 -#define RCLK_PMC 36 -#define RCLK_LPD 37 -#define WDT 38 -#define TTC0 39 -#define TTC1 40 -#define TTC2 41 -#define TTC3 42 -#define GEM_TSU 43 -#define GEM_TSU_LB 44 -#define MUXED_IRO_DIV2 45 -#define MUXED_IRO_DIV4 46 -#define PSM_REF 47 -#define GEM0_RX 48 -#define GEM0_TX 49 -#define GEM1_RX 50 -#define GEM1_TX 51 -#define CPM_CORE_REF 52 -#define CPM_LSBUS_REF 53 -#define CPM_DBG_REF 54 -#define CPM_AUX0_REF 55 -#define CPM_AUX1_REF 56 -#define QSPI_REF 57 -#define OSPI_REF 58 -#define SDIO0_REF 59 -#define SDIO1_REF 60 -#define PMC_LSBUS_REF 61 -#define I2C_REF 62 -#define TEST_PATTERN_REF 63 -#define DFT_OSC_REF 64 -#define PMC_PL0_REF 65 -#define PMC_PL1_REF 66 -#define PMC_PL2_REF 67 -#define PMC_PL3_REF 68 -#define CFU_REF 69 -#define SPARE_REF 70 -#define NPI_REF 71 -#define HSM0_REF 72 -#define HSM1_REF 73 -#define SD_DLL_REF 74 -#define FPD_TOP_SWITCH 75 -#define FPD_LSBUS 76 -#define ACPU 77 -#define DBG_TRACE 78 -#define DBG_FPD 79 -#define LPD_TOP_SWITCH 80 -#define ADMA 81 -#define LPD_LSBUS 82 -#define CPU_R5 83 -#define CPU_R5_CORE 84 -#define CPU_R5_OCM 85 -#define CPU_R5_OCM2 86 -#define IOU_SWITCH 87 -#define GEM0_REF 88 -#define GEM1_REF 89 -#define GEM_TSU_REF 90 -#define USB0_BUS_REF 91 -#define UART0_REF 92 -#define UART1_REF 93 -#define SPI0_REF 94 -#define SPI1_REF 95 -#define CAN0_REF 96 -#define CAN1_REF 97 -#define I2C0_REF 98 -#define I2C1_REF 99 -#define DBG_LPD 100 -#define TIMESTAMP_REF 101 -#define DBG_TSTMP 102 -#define CPM_TOPSW_REF 103 -#define USB3_DUAL_REF 104 -#define OUTCLK_MAX 105 -#define REF_CLK 106 -#define PL_ALT_REF_CLK 107 -#define MUXED_IRO 108 -#define PL_EXT 109 -#define PL_LB 110 -#define MIO_50_OR_51 111 -#define MIO_24_OR_25 112 - -#endif diff --git a/include/dt-bindings/clock/xlnx-zynqmp-clk.h b/include/dt-bindings/clock/xlnx-zynqmp-clk.h deleted file mode 100644 index cdc4c0b9a37..00000000000 --- a/include/dt-bindings/clock/xlnx-zynqmp-clk.h +++ /dev/null @@ -1,126 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Xilinx Zynq MPSoC Firmware layer - * - * Copyright (C) 2014-2018 Xilinx, Inc. - * - */ - -#ifndef _DT_BINDINGS_CLK_ZYNQMP_H -#define _DT_BINDINGS_CLK_ZYNQMP_H - -#define IOPLL 0 -#define RPLL 1 -#define APLL 2 -#define DPLL 3 -#define VPLL 4 -#define IOPLL_TO_FPD 5 -#define RPLL_TO_FPD 6 -#define APLL_TO_LPD 7 -#define DPLL_TO_LPD 8 -#define VPLL_TO_LPD 9 -#define ACPU 10 -#define ACPU_HALF 11 -#define DBF_FPD 12 -#define DBF_LPD 13 -#define DBG_TRACE 14 -#define DBG_TSTMP 15 -#define DP_VIDEO_REF 16 -#define DP_AUDIO_REF 17 -#define DP_STC_REF 18 -#define GDMA_REF 19 -#define DPDMA_REF 20 -#define DDR_REF 21 -#define SATA_REF 22 -#define PCIE_REF 23 -#define GPU_REF 24 -#define GPU_PP0_REF 25 -#define GPU_PP1_REF 26 -#define TOPSW_MAIN 27 -#define TOPSW_LSBUS 28 -#define GTGREF0_REF 29 -#define LPD_SWITCH 30 -#define LPD_LSBUS 31 -#define USB0_BUS_REF 32 -#define USB1_BUS_REF 33 -#define USB3_DUAL_REF 34 -#define USB0 35 -#define USB1 36 -#define CPU_R5 37 -#define CPU_R5_CORE 38 -#define CSU_SPB 39 -#define CSU_PLL 40 -#define PCAP 41 -#define IOU_SWITCH 42 -#define GEM_TSU_REF 43 -#define GEM_TSU 44 -#define GEM0_TX 45 -#define GEM1_TX 46 -#define GEM2_TX 47 -#define GEM3_TX 48 -#define GEM0_RX 49 -#define GEM1_RX 50 -#define GEM2_RX 51 -#define GEM3_RX 52 -#define QSPI_REF 53 -#define SDIO0_REF 54 -#define SDIO1_REF 55 -#define UART0_REF 56 -#define UART1_REF 57 -#define SPI0_REF 58 -#define SPI1_REF 59 -#define NAND_REF 60 -#define I2C0_REF 61 -#define I2C1_REF 62 -#define CAN0_REF 63 -#define CAN1_REF 64 -#define CAN0 65 -#define CAN1 66 -#define DLL_REF 67 -#define ADMA_REF 68 -#define TIMESTAMP_REF 69 -#define AMS_REF 70 -#define PL0_REF 71 -#define PL1_REF 72 -#define PL2_REF 73 -#define PL3_REF 74 -#define WDT 75 -#define IOPLL_INT 76 -#define IOPLL_PRE_SRC 77 -#define IOPLL_HALF 78 -#define IOPLL_INT_MUX 79 -#define IOPLL_POST_SRC 80 -#define RPLL_INT 81 -#define RPLL_PRE_SRC 82 -#define RPLL_HALF 83 -#define RPLL_INT_MUX 84 -#define RPLL_POST_SRC 85 -#define APLL_INT 86 -#define APLL_PRE_SRC 87 -#define APLL_HALF 88 -#define APLL_INT_MUX 89 -#define APLL_POST_SRC 90 -#define DPLL_INT 91 -#define DPLL_PRE_SRC 92 -#define DPLL_HALF 93 -#define DPLL_INT_MUX 94 -#define DPLL_POST_SRC 95 -#define VPLL_INT 96 -#define VPLL_PRE_SRC 97 -#define VPLL_HALF 98 -#define VPLL_INT_MUX 99 -#define VPLL_POST_SRC 100 -#define CAN0_MIO 101 -#define CAN1_MIO 102 -#define ACPU_FULL 103 -#define GEM0_REF 104 -#define GEM1_REF 105 -#define GEM2_REF 106 -#define GEM3_REF 107 -#define GEM0_REF_UNG 108 -#define GEM1_REF_UNG 109 -#define GEM2_REF_UNG 110 -#define GEM3_REF_UNG 111 -#define LPD_WDT 112 - -#endif |