diff options
Diffstat (limited to 'include/dt-bindings/mfd')
| -rw-r--r-- | include/dt-bindings/mfd/arizona.h | 115 | ||||
| -rw-r--r-- | include/dt-bindings/mfd/as3722.h | 53 | ||||
| -rw-r--r-- | include/dt-bindings/mfd/at91-usart.h | 17 | ||||
| -rw-r--r-- | include/dt-bindings/mfd/atmel-flexcom.h | 15 | ||||
| -rw-r--r-- | include/dt-bindings/mfd/cros_ec.h | 18 | ||||
| -rw-r--r-- | include/dt-bindings/mfd/dbx500-prcmu.h | 104 | ||||
| -rw-r--r-- | include/dt-bindings/mfd/k210-sysctl.h | 38 | ||||
| -rw-r--r-- | include/dt-bindings/mfd/max77620.h | 40 | ||||
| -rw-r--r-- | include/dt-bindings/mfd/palmas.h | 19 | ||||
| -rw-r--r-- | include/dt-bindings/mfd/qcom-rpm.h | 183 | ||||
| -rw-r--r-- | include/dt-bindings/mfd/st,stpmic1.h | 50 | ||||
| -rw-r--r-- | include/dt-bindings/mfd/st-lpc.h | 17 | ||||
| -rw-r--r-- | include/dt-bindings/mfd/stm32f4-rcc.h | 108 | ||||
| -rw-r--r-- | include/dt-bindings/mfd/stm32f7-rcc.h | 116 | ||||
| -rw-r--r-- | include/dt-bindings/mfd/stm32h7-rcc.h | 136 |
15 files changed, 90 insertions, 939 deletions
diff --git a/include/dt-bindings/mfd/arizona.h b/include/dt-bindings/mfd/arizona.h deleted file mode 100644 index 1056108c959..00000000000 --- a/include/dt-bindings/mfd/arizona.h +++ /dev/null @@ -1,115 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Device Tree defines for Arizona devices - * - * Copyright 2015 Cirrus Logic Inc. - * - * Author: Charles Keepax <ckeepax@opensource.wolfsonmicro.com> - */ - -#ifndef _DT_BINDINGS_MFD_ARIZONA_H -#define _DT_BINDINGS_MFD_ARIZONA_H - -/* GPIO Function Definitions */ -#define ARIZONA_GP_FN_TXLRCLK 0x00 -#define ARIZONA_GP_FN_GPIO 0x01 -#define ARIZONA_GP_FN_IRQ1 0x02 -#define ARIZONA_GP_FN_IRQ2 0x03 -#define ARIZONA_GP_FN_OPCLK 0x04 -#define ARIZONA_GP_FN_FLL1_OUT 0x05 -#define ARIZONA_GP_FN_FLL2_OUT 0x06 -#define ARIZONA_GP_FN_PWM1 0x08 -#define ARIZONA_GP_FN_PWM2 0x09 -#define ARIZONA_GP_FN_SYSCLK_UNDERCLOCKED 0x0A -#define ARIZONA_GP_FN_ASYNCCLK_UNDERCLOCKED 0x0B -#define ARIZONA_GP_FN_FLL1_LOCK 0x0C -#define ARIZONA_GP_FN_FLL2_LOCK 0x0D -#define ARIZONA_GP_FN_FLL1_CLOCK_OK 0x0F -#define ARIZONA_GP_FN_FLL2_CLOCK_OK 0x10 -#define ARIZONA_GP_FN_HEADPHONE_DET 0x12 -#define ARIZONA_GP_FN_MIC_DET 0x13 -#define ARIZONA_GP_FN_WSEQ_STATUS 0x15 -#define ARIZONA_GP_FN_CIF_ADDRESS_ERROR 0x16 -#define ARIZONA_GP_FN_ASRC1_LOCK 0x1A -#define ARIZONA_GP_FN_ASRC2_LOCK 0x1B -#define ARIZONA_GP_FN_ASRC_CONFIG_ERROR 0x1C -#define ARIZONA_GP_FN_DRC1_SIGNAL_DETECT 0x1D -#define ARIZONA_GP_FN_DRC1_ANTICLIP 0x1E -#define ARIZONA_GP_FN_DRC1_DECAY 0x1F -#define ARIZONA_GP_FN_DRC1_NOISE 0x20 -#define ARIZONA_GP_FN_DRC1_QUICK_RELEASE 0x21 -#define ARIZONA_GP_FN_DRC2_SIGNAL_DETECT 0x22 -#define ARIZONA_GP_FN_DRC2_ANTICLIP 0x23 -#define ARIZONA_GP_FN_DRC2_DECAY 0x24 -#define ARIZONA_GP_FN_DRC2_NOISE 0x25 -#define ARIZONA_GP_FN_DRC2_QUICK_RELEASE 0x26 -#define ARIZONA_GP_FN_MIXER_DROPPED_SAMPLE 0x27 -#define ARIZONA_GP_FN_AIF1_CONFIG_ERROR 0x28 -#define ARIZONA_GP_FN_AIF2_CONFIG_ERROR 0x29 -#define ARIZONA_GP_FN_AIF3_CONFIG_ERROR 0x2A -#define ARIZONA_GP_FN_SPK_TEMP_SHUTDOWN 0x2B -#define ARIZONA_GP_FN_SPK_TEMP_WARNING 0x2C -#define ARIZONA_GP_FN_UNDERCLOCKED 0x2D -#define ARIZONA_GP_FN_OVERCLOCKED 0x2E -#define ARIZONA_GP_FN_DSP_IRQ1 0x35 -#define ARIZONA_GP_FN_DSP_IRQ2 0x36 -#define ARIZONA_GP_FN_ASYNC_OPCLK 0x3D -#define ARIZONA_GP_FN_BOOT_DONE 0x44 -#define ARIZONA_GP_FN_DSP1_RAM_READY 0x45 -#define ARIZONA_GP_FN_SYSCLK_ENA_STATUS 0x4B -#define ARIZONA_GP_FN_ASYNCCLK_ENA_STATUS 0x4C - -/* GPIO Configuration Bits */ -#define ARIZONA_GPN_DIR 0x8000 -#define ARIZONA_GPN_PU 0x4000 -#define ARIZONA_GPN_PD 0x2000 -#define ARIZONA_GPN_LVL 0x0800 -#define ARIZONA_GPN_POL 0x0400 -#define ARIZONA_GPN_OP_CFG 0x0200 -#define ARIZONA_GPN_DB 0x0100 - -/* Provide some defines for the most common configs */ -#define ARIZONA_GP_DEFAULT 0xffffffff -#define ARIZONA_GP_OUTPUT (ARIZONA_GP_FN_GPIO) -#define ARIZONA_GP_INPUT (ARIZONA_GP_FN_GPIO | \ - ARIZONA_GPN_DIR) - -#define ARIZONA_32KZ_MCLK1 1 -#define ARIZONA_32KZ_MCLK2 2 -#define ARIZONA_32KZ_NONE 3 - -#define ARIZONA_DMIC_MICVDD 0 -#define ARIZONA_DMIC_MICBIAS1 1 -#define ARIZONA_DMIC_MICBIAS2 2 -#define ARIZONA_DMIC_MICBIAS3 3 - -#define ARIZONA_INMODE_DIFF 0 -#define ARIZONA_INMODE_SE 1 -#define ARIZONA_INMODE_DMIC 2 - -#define ARIZONA_MICD_TIME_CONTINUOUS 0 -#define ARIZONA_MICD_TIME_250US 1 -#define ARIZONA_MICD_TIME_500US 2 -#define ARIZONA_MICD_TIME_1MS 3 -#define ARIZONA_MICD_TIME_2MS 4 -#define ARIZONA_MICD_TIME_4MS 5 -#define ARIZONA_MICD_TIME_8MS 6 -#define ARIZONA_MICD_TIME_16MS 7 -#define ARIZONA_MICD_TIME_32MS 8 -#define ARIZONA_MICD_TIME_64MS 9 -#define ARIZONA_MICD_TIME_128MS 10 -#define ARIZONA_MICD_TIME_256MS 11 -#define ARIZONA_MICD_TIME_512MS 12 - -#define ARIZONA_ACCDET_MODE_MIC 0 -#define ARIZONA_ACCDET_MODE_HPL 1 -#define ARIZONA_ACCDET_MODE_HPR 2 -#define ARIZONA_ACCDET_MODE_HPM 4 -#define ARIZONA_ACCDET_MODE_ADC 7 - -#define ARIZONA_GPSW_OPEN 0 -#define ARIZONA_GPSW_CLOSED 1 -#define ARIZONA_GPSW_CLAMP_ENABLED 2 -#define ARIZONA_GPSW_CLAMP_DISABLED 3 - -#endif diff --git a/include/dt-bindings/mfd/as3722.h b/include/dt-bindings/mfd/as3722.h deleted file mode 100644 index 9ef0cba9040..00000000000 --- a/include/dt-bindings/mfd/as3722.h +++ /dev/null @@ -1,53 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides macros for ams AS3722 device bindings. - * - * Copyright (c) 2013, NVIDIA Corporation. - * - * Author: Laxman Dewangan <ldewangan@nvidia.com> - * - */ - -#ifndef __DT_BINDINGS_AS3722_H__ -#define __DT_BINDINGS_AS3722_H__ - -/* External control pins */ -#define AS3722_EXT_CONTROL_PIN_ENABLE1 1 -#define AS3722_EXT_CONTROL_PIN_ENABLE2 2 -#define AS3722_EXT_CONTROL_PIN_ENABLE3 3 - -/* Interrupt numbers for AS3722 */ -#define AS3722_IRQ_LID 0 -#define AS3722_IRQ_ACOK 1 -#define AS3722_IRQ_ENABLE1 2 -#define AS3722_IRQ_OCCUR_ALARM_SD0 3 -#define AS3722_IRQ_ONKEY_LONG_PRESS 4 -#define AS3722_IRQ_ONKEY 5 -#define AS3722_IRQ_OVTMP 6 -#define AS3722_IRQ_LOWBAT 7 -#define AS3722_IRQ_SD0_LV 8 -#define AS3722_IRQ_SD1_LV 9 -#define AS3722_IRQ_SD2_LV 10 -#define AS3722_IRQ_PWM1_OV_PROT 11 -#define AS3722_IRQ_PWM2_OV_PROT 12 -#define AS3722_IRQ_ENABLE2 13 -#define AS3722_IRQ_SD6_LV 14 -#define AS3722_IRQ_RTC_REP 15 -#define AS3722_IRQ_RTC_ALARM 16 -#define AS3722_IRQ_GPIO1 17 -#define AS3722_IRQ_GPIO2 18 -#define AS3722_IRQ_GPIO3 19 -#define AS3722_IRQ_GPIO4 20 -#define AS3722_IRQ_GPIO5 21 -#define AS3722_IRQ_WATCHDOG 22 -#define AS3722_IRQ_ENABLE3 23 -#define AS3722_IRQ_TEMP_SD0_SHUTDOWN 24 -#define AS3722_IRQ_TEMP_SD1_SHUTDOWN 25 -#define AS3722_IRQ_TEMP_SD2_SHUTDOWN 26 -#define AS3722_IRQ_TEMP_SD0_ALARM 27 -#define AS3722_IRQ_TEMP_SD1_ALARM 28 -#define AS3722_IRQ_TEMP_SD6_ALARM 29 -#define AS3722_IRQ_OCCUR_ALARM_SD6 30 -#define AS3722_IRQ_ADC 31 - -#endif /* __DT_BINDINGS_AS3722_H__ */ diff --git a/include/dt-bindings/mfd/at91-usart.h b/include/dt-bindings/mfd/at91-usart.h deleted file mode 100644 index 2de5bc312e1..00000000000 --- a/include/dt-bindings/mfd/at91-usart.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides macros for AT91 USART DT bindings. - * - * Copyright (C) 2018 Microchip Technology - * - * Author: Radu Pirea <radu.pirea@microchip.com> - * - */ - -#ifndef __DT_BINDINGS_AT91_USART_H__ -#define __DT_BINDINGS_AT91_USART_H__ - -#define AT91_USART_MODE_SERIAL 0 -#define AT91_USART_MODE_SPI 1 - -#endif /* __DT_BINDINGS_AT91_USART_H__ */ diff --git a/include/dt-bindings/mfd/atmel-flexcom.h b/include/dt-bindings/mfd/atmel-flexcom.h deleted file mode 100644 index 4e2fc323639..00000000000 --- a/include/dt-bindings/mfd/atmel-flexcom.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * This header provides macros for Atmel Flexcom DT bindings. - * - * Copyright (C) 2015 Cyrille Pitchen <cyrille.pitchen@atmel.com> - */ - -#ifndef __DT_BINDINGS_ATMEL_FLEXCOM_H__ -#define __DT_BINDINGS_ATMEL_FLEXCOM_H__ - -#define ATMEL_FLEXCOM_MODE_USART 1 -#define ATMEL_FLEXCOM_MODE_SPI 2 -#define ATMEL_FLEXCOM_MODE_TWI 3 - -#endif /* __DT_BINDINGS_ATMEL_FLEXCOM_H__ */ diff --git a/include/dt-bindings/mfd/cros_ec.h b/include/dt-bindings/mfd/cros_ec.h deleted file mode 100644 index 3b29cd04957..00000000000 --- a/include/dt-bindings/mfd/cros_ec.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -/* - * DTS binding definitions used for the Chromium OS Embedded Controller. - * - * Copyright (c) 2022 The Chromium OS Authors. All rights reserved. - */ - -#ifndef _DT_BINDINGS_MFD_CROS_EC_H -#define _DT_BINDINGS_MFD_CROS_EC_H - -/* Typed channel for keyboard backlight. */ -#define CROS_EC_PWM_DT_KB_LIGHT 0 -/* Typed channel for display backlight. */ -#define CROS_EC_PWM_DT_DISPLAY_LIGHT 1 -/* Number of typed channels. */ -#define CROS_EC_PWM_DT_COUNT 2 - -#endif diff --git a/include/dt-bindings/mfd/dbx500-prcmu.h b/include/dt-bindings/mfd/dbx500-prcmu.h index 0404bcc47dd..7266ae67b03 100644 --- a/include/dt-bindings/mfd/dbx500-prcmu.h +++ b/include/dt-bindings/mfd/dbx500-prcmu.h @@ -12,64 +12,64 @@ */ #define ARMCLK 0 #define PRCMU_ACLK 1 -#define PRCMU_SVAMMCSPCLK 2 -#define PRCMU_SDMMCHCLK 2 /* DBx540 only. */ -#define PRCMU_SIACLK 3 -#define PRCMU_SIAMMDSPCLK 3 /* DBx540 only. */ -#define PRCMU_SGACLK 4 -#define PRCMU_UARTCLK 5 -#define PRCMU_MSP02CLK 6 -#define PRCMU_MSP1CLK 7 -#define PRCMU_I2CCLK 8 -#define PRCMU_SDMMCCLK 9 -#define PRCMU_SLIMCLK 10 -#define PRCMU_CAMCLK 10 /* DBx540 only. */ -#define PRCMU_PER1CLK 11 -#define PRCMU_PER2CLK 12 -#define PRCMU_PER3CLK 13 -#define PRCMU_PER5CLK 14 -#define PRCMU_PER6CLK 15 -#define PRCMU_PER7CLK 16 -#define PRCMU_LCDCLK 17 -#define PRCMU_BMLCLK 18 -#define PRCMU_HSITXCLK 19 -#define PRCMU_HSIRXCLK 20 +#define PRCMU_SVAMMCSPCLK 2 +#define PRCMU_SDMMCHCLK 2 /* DBx540 only. */ +#define PRCMU_SIACLK 3 +#define PRCMU_SIAMMDSPCLK 3 /* DBx540 only. */ +#define PRCMU_SGACLK 4 +#define PRCMU_UARTCLK 5 +#define PRCMU_MSP02CLK 6 +#define PRCMU_MSP1CLK 7 +#define PRCMU_I2CCLK 8 +#define PRCMU_SDMMCCLK 9 +#define PRCMU_SLIMCLK 10 +#define PRCMU_CAMCLK 10 /* DBx540 only. */ +#define PRCMU_PER1CLK 11 +#define PRCMU_PER2CLK 12 +#define PRCMU_PER3CLK 13 +#define PRCMU_PER5CLK 14 +#define PRCMU_PER6CLK 15 +#define PRCMU_PER7CLK 16 +#define PRCMU_LCDCLK 17 +#define PRCMU_BMLCLK 18 +#define PRCMU_HSITXCLK 19 +#define PRCMU_HSIRXCLK 20 #define PRCMU_HDMICLK 21 -#define PRCMU_APEATCLK 22 -#define PRCMU_APETRACECLK 23 -#define PRCMU_MCDECLK 24 -#define PRCMU_IPI2CCLK 25 -#define PRCMU_DSIALTCLK 26 -#define PRCMU_DMACLK 27 -#define PRCMU_B2R2CLK 28 -#define PRCMU_TVCLK 29 -#define SPARE_UNIPROCLK 30 -#define PRCMU_SSPCLK 31 -#define PRCMU_RNGCLK 32 -#define PRCMU_UICCCLK 33 +#define PRCMU_APEATCLK 22 +#define PRCMU_APETRACECLK 23 +#define PRCMU_MCDECLK 24 +#define PRCMU_IPI2CCLK 25 +#define PRCMU_DSIALTCLK 26 +#define PRCMU_DMACLK 27 +#define PRCMU_B2R2CLK 28 +#define PRCMU_TVCLK 29 +#define SPARE_UNIPROCLK 30 +#define PRCMU_SSPCLK 31 +#define PRCMU_RNGCLK 32 +#define PRCMU_UICCCLK 33 #define PRCMU_G1CLK 34 /* DBx540 only. */ #define PRCMU_HVACLK 35 /* DBx540 only. */ -#define PRCMU_SPARE1CLK 36 -#define PRCMU_SPARE2CLK 37 +#define PRCMU_SPARE1CLK 36 +#define PRCMU_SPARE2CLK 37 -#define PRCMU_NUM_REG_CLOCKS 38 +#define PRCMU_NUM_REG_CLOCKS 38 -#define PRCMU_RTCCLK PRCMU_NUM_REG_CLOCKS -#define PRCMU_SYSCLK 39 -#define PRCMU_CDCLK 40 -#define PRCMU_TIMCLK 41 -#define PRCMU_PLLSOC0 42 -#define PRCMU_PLLSOC1 43 -#define PRCMU_ARMSS 44 -#define PRCMU_PLLDDR 45 +#define PRCMU_RTCCLK PRCMU_NUM_REG_CLOCKS +#define PRCMU_SYSCLK 39 +#define PRCMU_CDCLK 40 +#define PRCMU_TIMCLK 41 +#define PRCMU_PLLSOC0 42 +#define PRCMU_PLLSOC1 43 +#define PRCMU_ARMSS 44 +#define PRCMU_PLLDDR 45 /* DSI Clocks */ -#define PRCMU_PLLDSI 46 -#define PRCMU_DSI0CLK 47 -#define PRCMU_DSI1CLK 48 -#define PRCMU_DSI0ESCCLK 49 -#define PRCMU_DSI1ESCCLK 50 -#define PRCMU_DSI2ESCCLK 51 +#define PRCMU_PLLDSI 46 +#define PRCMU_DSI0CLK 47 +#define PRCMU_DSI1CLK 48 +#define PRCMU_DSI0ESCCLK 49 +#define PRCMU_DSI1ESCCLK 50 +#define PRCMU_DSI2ESCCLK 51 /* LCD DSI PLL - Ux540 only */ #define PRCMU_PLLDSI_LCD 52 @@ -79,6 +79,6 @@ #define PRCMU_DSI1ESCCLK_LCD 56 #define PRCMU_DSI2ESCCLK_LCD 57 -#define PRCMU_NUM_CLKS 58 +#define PRCMU_NUM_CLKS 58 #endif diff --git a/include/dt-bindings/mfd/k210-sysctl.h b/include/dt-bindings/mfd/k210-sysctl.h new file mode 100644 index 00000000000..bfc918d3ba9 --- /dev/null +++ b/include/dt-bindings/mfd/k210-sysctl.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020 Sean Anderson <seanga2@gmail.com> + */ + +#ifndef K210_SYSCTL_H +#define K210_SYSCTL_H + +/* Taken from kendryte-standalone-sdk/lib/drivers/include/sysctl.h */ +#define K210_SYSCTL_GIT_ID 0x00 /* Git short commit id */ +#define K210_SYSCTL_UART_BAUD 0x04 /* Default UARTHS baud rate */ +#define K210_SYSCTL_PLL0 0x08 /* PLL0 controller */ +#define K210_SYSCTL_PLL1 0x0C /* PLL1 controller */ +#define K210_SYSCTL_PLL2 0x10 /* PLL2 controller */ +#define K210_SYSCTL_PLL_LOCK 0x18 /* PLL lock tester */ +#define K210_SYSCTL_ROM_ERROR 0x1C /* AXI ROM detector */ +#define K210_SYSCTL_SEL0 0x20 /* Clock select controller 0 */ +#define K210_SYSCTL_SEL1 0x24 /* Clock select controller 1 */ +#define K210_SYSCTL_EN_CENT 0x28 /* Central clock enable */ +#define K210_SYSCTL_EN_PERI 0x2C /* Peripheral clock enable */ +#define K210_SYSCTL_SOFT_RESET 0x30 /* Soft reset ctrl */ +#define K210_SYSCTL_PERI_RESET 0x34 /* Peripheral reset controller */ +#define K210_SYSCTL_THR0 0x38 /* Clock threshold controller 0 */ +#define K210_SYSCTL_THR1 0x3C /* Clock threshold controller 1 */ +#define K210_SYSCTL_THR2 0x40 /* Clock threshold controller 2 */ +#define K210_SYSCTL_THR3 0x44 /* Clock threshold controller 3 */ +#define K210_SYSCTL_THR4 0x48 /* Clock threshold controller 4 */ +#define K210_SYSCTL_THR5 0x4C /* Clock threshold controller 5 */ +#define K210_SYSCTL_THR6 0x50 /* Clock threshold controller 6 */ +#define K210_SYSCTL_MISC 0x54 /* Miscellaneous controller */ +#define K210_SYSCTL_PERI 0x58 /* Peripheral controller */ +#define K210_SYSCTL_SPI_SLEEP 0x5C /* SPI sleep controller */ +#define K210_SYSCTL_RESET_STAT 0x60 /* Reset source status */ +#define K210_SYSCTL_DMA_SEL0 0x64 /* DMA handshake selector 0 */ +#define K210_SYSCTL_DMA_SEL1 0x68 /* DMA handshake selector 1 */ +#define K210_SYSCTL_POWER_SEL 0x6C /* IO Power Mode Select controller */ + +#endif /* K210_SYSCTL_H */ diff --git a/include/dt-bindings/mfd/max77620.h b/include/dt-bindings/mfd/max77620.h deleted file mode 100644 index 1e19c5f908d..00000000000 --- a/include/dt-bindings/mfd/max77620.h +++ /dev/null @@ -1,40 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides macros for MAXIM MAX77620 device bindings. - * - * Copyright (c) 2016, NVIDIA Corporation. - * Author: Laxman Dewangan <ldewangan@nvidia.com> - */ - -#ifndef _DT_BINDINGS_MFD_MAX77620_H -#define _DT_BINDINGS_MFD_MAX77620_H - -/* MAX77620 interrupts */ -#define MAX77620_IRQ_TOP_GLBL 0 /* Low-Battery */ -#define MAX77620_IRQ_TOP_SD 1 /* SD power fail */ -#define MAX77620_IRQ_TOP_LDO 2 /* LDO power fail */ -#define MAX77620_IRQ_TOP_GPIO 3 /* GPIO internal int to MAX77620 */ -#define MAX77620_IRQ_TOP_RTC 4 /* RTC */ -#define MAX77620_IRQ_TOP_32K 5 /* 32kHz oscillator */ -#define MAX77620_IRQ_TOP_ONOFF 6 /* ON/OFF oscillator */ -#define MAX77620_IRQ_LBT_MBATLOW 7 /* Thermal alarm status, > 120C */ -#define MAX77620_IRQ_LBT_TJALRM1 8 /* Thermal alarm status, > 120C */ -#define MAX77620_IRQ_LBT_TJALRM2 9 /* Thermal alarm status, > 140C */ - -/* FPS event source */ -#define MAX77620_FPS_EVENT_SRC_EN0 0 -#define MAX77620_FPS_EVENT_SRC_EN1 1 -#define MAX77620_FPS_EVENT_SRC_SW 2 - -/* Device state when FPS event LOW */ -#define MAX77620_FPS_INACTIVE_STATE_SLEEP 0 -#define MAX77620_FPS_INACTIVE_STATE_LOW_POWER 1 - -/* FPS source */ -#define MAX77620_FPS_SRC_0 0 -#define MAX77620_FPS_SRC_1 1 -#define MAX77620_FPS_SRC_2 2 -#define MAX77620_FPS_SRC_NONE 3 -#define MAX77620_FPS_SRC_DEF 4 - -#endif diff --git a/include/dt-bindings/mfd/palmas.h b/include/dt-bindings/mfd/palmas.h deleted file mode 100644 index c4f1d57ff4f..00000000000 --- a/include/dt-bindings/mfd/palmas.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides macros for Palmas device bindings. - * - * Copyright (c) 2013, NVIDIA Corporation. - * - * Author: Laxman Dewangan <ldewangan@nvidia.com> - * - */ - -#ifndef __DT_BINDINGS_PALMAS_H -#define __DT_BINDINGS_PALMAS_H - -/* External control pins */ -#define PALMAS_EXT_CONTROL_PIN_ENABLE1 1 -#define PALMAS_EXT_CONTROL_PIN_ENABLE2 2 -#define PALMAS_EXT_CONTROL_PIN_NSLEEP 3 - -#endif /* __DT_BINDINGS_PALMAS_H */ diff --git a/include/dt-bindings/mfd/qcom-rpm.h b/include/dt-bindings/mfd/qcom-rpm.h deleted file mode 100644 index c9204c4df52..00000000000 --- a/include/dt-bindings/mfd/qcom-rpm.h +++ /dev/null @@ -1,183 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for the Qualcomm RPM bindings. - */ - -#ifndef _DT_BINDINGS_MFD_QCOM_RPM_H -#define _DT_BINDINGS_MFD_QCOM_RPM_H - -/* - * Constants use to identify individual resources in the RPM. - */ -#define QCOM_RPM_APPS_FABRIC_ARB 1 -#define QCOM_RPM_APPS_FABRIC_CLK 2 -#define QCOM_RPM_APPS_FABRIC_HALT 3 -#define QCOM_RPM_APPS_FABRIC_IOCTL 4 -#define QCOM_RPM_APPS_FABRIC_MODE 5 -#define QCOM_RPM_APPS_L2_CACHE_CTL 6 -#define QCOM_RPM_CFPB_CLK 7 -#define QCOM_RPM_CXO_BUFFERS 8 -#define QCOM_RPM_CXO_CLK 9 -#define QCOM_RPM_DAYTONA_FABRIC_CLK 10 -#define QCOM_RPM_DDR_DMM 11 -#define QCOM_RPM_EBI1_CLK 12 -#define QCOM_RPM_HDMI_SWITCH 13 -#define QCOM_RPM_MMFPB_CLK 14 -#define QCOM_RPM_MM_FABRIC_ARB 15 -#define QCOM_RPM_MM_FABRIC_CLK 16 -#define QCOM_RPM_MM_FABRIC_HALT 17 -#define QCOM_RPM_MM_FABRIC_IOCTL 18 -#define QCOM_RPM_MM_FABRIC_MODE 19 -#define QCOM_RPM_PLL_4 20 -#define QCOM_RPM_PM8058_LDO0 21 -#define QCOM_RPM_PM8058_LDO1 22 -#define QCOM_RPM_PM8058_LDO2 23 -#define QCOM_RPM_PM8058_LDO3 24 -#define QCOM_RPM_PM8058_LDO4 25 -#define QCOM_RPM_PM8058_LDO5 26 -#define QCOM_RPM_PM8058_LDO6 27 -#define QCOM_RPM_PM8058_LDO7 28 -#define QCOM_RPM_PM8058_LDO8 29 -#define QCOM_RPM_PM8058_LDO9 30 -#define QCOM_RPM_PM8058_LDO10 31 -#define QCOM_RPM_PM8058_LDO11 32 -#define QCOM_RPM_PM8058_LDO12 33 -#define QCOM_RPM_PM8058_LDO13 34 -#define QCOM_RPM_PM8058_LDO14 35 -#define QCOM_RPM_PM8058_LDO15 36 -#define QCOM_RPM_PM8058_LDO16 37 -#define QCOM_RPM_PM8058_LDO17 38 -#define QCOM_RPM_PM8058_LDO18 39 -#define QCOM_RPM_PM8058_LDO19 40 -#define QCOM_RPM_PM8058_LDO20 41 -#define QCOM_RPM_PM8058_LDO21 42 -#define QCOM_RPM_PM8058_LDO22 43 -#define QCOM_RPM_PM8058_LDO23 44 -#define QCOM_RPM_PM8058_LDO24 45 -#define QCOM_RPM_PM8058_LDO25 46 -#define QCOM_RPM_PM8058_LVS0 47 -#define QCOM_RPM_PM8058_LVS1 48 -#define QCOM_RPM_PM8058_NCP 49 -#define QCOM_RPM_PM8058_SMPS0 50 -#define QCOM_RPM_PM8058_SMPS1 51 -#define QCOM_RPM_PM8058_SMPS2 52 -#define QCOM_RPM_PM8058_SMPS3 53 -#define QCOM_RPM_PM8058_SMPS4 54 -#define QCOM_RPM_PM8821_LDO1 55 -#define QCOM_RPM_PM8821_SMPS1 56 -#define QCOM_RPM_PM8821_SMPS2 57 -#define QCOM_RPM_PM8901_LDO0 58 -#define QCOM_RPM_PM8901_LDO1 59 -#define QCOM_RPM_PM8901_LDO2 60 -#define QCOM_RPM_PM8901_LDO3 61 -#define QCOM_RPM_PM8901_LDO4 62 -#define QCOM_RPM_PM8901_LDO5 63 -#define QCOM_RPM_PM8901_LDO6 64 -#define QCOM_RPM_PM8901_LVS0 65 -#define QCOM_RPM_PM8901_LVS1 66 -#define QCOM_RPM_PM8901_LVS2 67 -#define QCOM_RPM_PM8901_LVS3 68 -#define QCOM_RPM_PM8901_MVS 69 -#define QCOM_RPM_PM8901_SMPS0 70 -#define QCOM_RPM_PM8901_SMPS1 71 -#define QCOM_RPM_PM8901_SMPS2 72 -#define QCOM_RPM_PM8901_SMPS3 73 -#define QCOM_RPM_PM8901_SMPS4 74 -#define QCOM_RPM_PM8921_CLK1 75 -#define QCOM_RPM_PM8921_CLK2 76 -#define QCOM_RPM_PM8921_LDO1 77 -#define QCOM_RPM_PM8921_LDO2 78 -#define QCOM_RPM_PM8921_LDO3 79 -#define QCOM_RPM_PM8921_LDO4 80 -#define QCOM_RPM_PM8921_LDO5 81 -#define QCOM_RPM_PM8921_LDO6 82 -#define QCOM_RPM_PM8921_LDO7 83 -#define QCOM_RPM_PM8921_LDO8 84 -#define QCOM_RPM_PM8921_LDO9 85 -#define QCOM_RPM_PM8921_LDO10 86 -#define QCOM_RPM_PM8921_LDO11 87 -#define QCOM_RPM_PM8921_LDO12 88 -#define QCOM_RPM_PM8921_LDO13 89 -#define QCOM_RPM_PM8921_LDO14 90 -#define QCOM_RPM_PM8921_LDO15 91 -#define QCOM_RPM_PM8921_LDO16 92 -#define QCOM_RPM_PM8921_LDO17 93 -#define QCOM_RPM_PM8921_LDO18 94 -#define QCOM_RPM_PM8921_LDO19 95 -#define QCOM_RPM_PM8921_LDO20 96 -#define QCOM_RPM_PM8921_LDO21 97 -#define QCOM_RPM_PM8921_LDO22 98 -#define QCOM_RPM_PM8921_LDO23 99 -#define QCOM_RPM_PM8921_LDO24 100 -#define QCOM_RPM_PM8921_LDO25 101 -#define QCOM_RPM_PM8921_LDO26 102 -#define QCOM_RPM_PM8921_LDO27 103 -#define QCOM_RPM_PM8921_LDO28 104 -#define QCOM_RPM_PM8921_LDO29 105 -#define QCOM_RPM_PM8921_LVS1 106 -#define QCOM_RPM_PM8921_LVS2 107 -#define QCOM_RPM_PM8921_LVS3 108 -#define QCOM_RPM_PM8921_LVS4 109 -#define QCOM_RPM_PM8921_LVS5 110 -#define QCOM_RPM_PM8921_LVS6 111 -#define QCOM_RPM_PM8921_LVS7 112 -#define QCOM_RPM_PM8921_MVS 113 -#define QCOM_RPM_PM8921_NCP 114 -#define QCOM_RPM_PM8921_SMPS1 115 -#define QCOM_RPM_PM8921_SMPS2 116 -#define QCOM_RPM_PM8921_SMPS3 117 -#define QCOM_RPM_PM8921_SMPS4 118 -#define QCOM_RPM_PM8921_SMPS5 119 -#define QCOM_RPM_PM8921_SMPS6 120 -#define QCOM_RPM_PM8921_SMPS7 121 -#define QCOM_RPM_PM8921_SMPS8 122 -#define QCOM_RPM_PXO_CLK 123 -#define QCOM_RPM_QDSS_CLK 124 -#define QCOM_RPM_SFPB_CLK 125 -#define QCOM_RPM_SMI_CLK 126 -#define QCOM_RPM_SYS_FABRIC_ARB 127 -#define QCOM_RPM_SYS_FABRIC_CLK 128 -#define QCOM_RPM_SYS_FABRIC_HALT 129 -#define QCOM_RPM_SYS_FABRIC_IOCTL 130 -#define QCOM_RPM_SYS_FABRIC_MODE 131 -#define QCOM_RPM_USB_OTG_SWITCH 132 -#define QCOM_RPM_VDDMIN_GPIO 133 -#define QCOM_RPM_NSS_FABRIC_0_CLK 134 -#define QCOM_RPM_NSS_FABRIC_1_CLK 135 -#define QCOM_RPM_SMB208_S1a 136 -#define QCOM_RPM_SMB208_S1b 137 -#define QCOM_RPM_SMB208_S2a 138 -#define QCOM_RPM_SMB208_S2b 139 -#define QCOM_RPM_PM8018_SMPS1 140 -#define QCOM_RPM_PM8018_SMPS2 141 -#define QCOM_RPM_PM8018_SMPS3 142 -#define QCOM_RPM_PM8018_SMPS4 143 -#define QCOM_RPM_PM8018_SMPS5 144 -#define QCOM_RPM_PM8018_LDO1 145 -#define QCOM_RPM_PM8018_LDO2 146 -#define QCOM_RPM_PM8018_LDO3 147 -#define QCOM_RPM_PM8018_LDO4 148 -#define QCOM_RPM_PM8018_LDO5 149 -#define QCOM_RPM_PM8018_LDO6 150 -#define QCOM_RPM_PM8018_LDO7 151 -#define QCOM_RPM_PM8018_LDO8 152 -#define QCOM_RPM_PM8018_LDO9 153 -#define QCOM_RPM_PM8018_LDO10 154 -#define QCOM_RPM_PM8018_LDO11 155 -#define QCOM_RPM_PM8018_LDO12 156 -#define QCOM_RPM_PM8018_LDO13 157 -#define QCOM_RPM_PM8018_LDO14 158 -#define QCOM_RPM_PM8018_LVS1 159 -#define QCOM_RPM_PM8018_NCP 160 -#define QCOM_RPM_VOLTAGE_CORNER 161 - -/* - * Constants used to select force mode for regulators. - */ -#define QCOM_RPM_FORCE_MODE_NONE 0 -#define QCOM_RPM_FORCE_MODE_LPM 1 -#define QCOM_RPM_FORCE_MODE_HPM 2 -#define QCOM_RPM_FORCE_MODE_AUTO 3 -#define QCOM_RPM_FORCE_MODE_BYPASS 4 - -#endif diff --git a/include/dt-bindings/mfd/st,stpmic1.h b/include/dt-bindings/mfd/st,stpmic1.h deleted file mode 100644 index 9dd15b9c743..00000000000 --- a/include/dt-bindings/mfd/st,stpmic1.h +++ /dev/null @@ -1,50 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ -/* - * Copyright (C) STMicroelectronics 2018 - All Rights Reserved - * Author: Philippe Peurichard <philippe.peurichard@st.com>, - * Pascal Paillet <p.paillet@st.com> for STMicroelectronics. - */ - -#ifndef __DT_BINDINGS_STPMIC1_H__ -#define __DT_BINDINGS_STPMIC1_H__ - -/* IRQ definitions */ -#define IT_PONKEY_F 0 -#define IT_PONKEY_R 1 -#define IT_WAKEUP_F 2 -#define IT_WAKEUP_R 3 -#define IT_VBUS_OTG_F 4 -#define IT_VBUS_OTG_R 5 -#define IT_SWOUT_F 6 -#define IT_SWOUT_R 7 - -#define IT_CURLIM_BUCK1 8 -#define IT_CURLIM_BUCK2 9 -#define IT_CURLIM_BUCK3 10 -#define IT_CURLIM_BUCK4 11 -#define IT_OCP_OTG 12 -#define IT_OCP_SWOUT 13 -#define IT_OCP_BOOST 14 -#define IT_OVP_BOOST 15 - -#define IT_CURLIM_LDO1 16 -#define IT_CURLIM_LDO2 17 -#define IT_CURLIM_LDO3 18 -#define IT_CURLIM_LDO4 19 -#define IT_CURLIM_LDO5 20 -#define IT_CURLIM_LDO6 21 -#define IT_SHORT_SWOTG 22 -#define IT_SHORT_SWOUT 23 - -#define IT_TWARN_F 24 -#define IT_TWARN_R 25 -#define IT_VINLOW_F 26 -#define IT_VINLOW_R 27 -#define IT_SWIN_F 30 -#define IT_SWIN_R 31 - -/* BUCK MODES definitions */ -#define STPMIC1_BUCK_MODE_NORMAL 0 -#define STPMIC1_BUCK_MODE_LP 2 - -#endif /* __DT_BINDINGS_STPMIC1_H__ */ diff --git a/include/dt-bindings/mfd/st-lpc.h b/include/dt-bindings/mfd/st-lpc.h deleted file mode 100644 index 88a7f56843b..00000000000 --- a/include/dt-bindings/mfd/st-lpc.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides shared DT/Driver defines for ST's LPC device - * - * Copyright (C) 2014 STMicroelectronics -- All Rights Reserved - * - * Author: Lee Jones <lee.jones@linaro.org> for STMicroelectronics - */ - -#ifndef __DT_BINDINGS_ST_LPC_H__ -#define __DT_BINDINGS_ST_LPC_H__ - -#define ST_LPC_MODE_RTC 0 -#define ST_LPC_MODE_WDT 1 -#define ST_LPC_MODE_CLKSRC 2 - -#endif /* __DT_BINDINGS_ST_LPC_H__ */ diff --git a/include/dt-bindings/mfd/stm32f4-rcc.h b/include/dt-bindings/mfd/stm32f4-rcc.h deleted file mode 100644 index 36448a5619a..00000000000 --- a/include/dt-bindings/mfd/stm32f4-rcc.h +++ /dev/null @@ -1,108 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for the STM32F4 RCC IP - */ - -#ifndef _DT_BINDINGS_MFD_STM32F4_RCC_H -#define _DT_BINDINGS_MFD_STM32F4_RCC_H - -/* AHB1 */ -#define STM32F4_RCC_AHB1_GPIOA 0 -#define STM32F4_RCC_AHB1_GPIOB 1 -#define STM32F4_RCC_AHB1_GPIOC 2 -#define STM32F4_RCC_AHB1_GPIOD 3 -#define STM32F4_RCC_AHB1_GPIOE 4 -#define STM32F4_RCC_AHB1_GPIOF 5 -#define STM32F4_RCC_AHB1_GPIOG 6 -#define STM32F4_RCC_AHB1_GPIOH 7 -#define STM32F4_RCC_AHB1_GPIOI 8 -#define STM32F4_RCC_AHB1_GPIOJ 9 -#define STM32F4_RCC_AHB1_GPIOK 10 -#define STM32F4_RCC_AHB1_CRC 12 -#define STM32F4_RCC_AHB1_BKPSRAM 18 -#define STM32F4_RCC_AHB1_CCMDATARAM 20 -#define STM32F4_RCC_AHB1_DMA1 21 -#define STM32F4_RCC_AHB1_DMA2 22 -#define STM32F4_RCC_AHB1_DMA2D 23 -#define STM32F4_RCC_AHB1_ETHMAC 25 -#define STM32F4_RCC_AHB1_ETHMACTX 26 -#define STM32F4_RCC_AHB1_ETHMACRX 27 -#define STM32F4_RCC_AHB1_ETHMACPTP 28 -#define STM32F4_RCC_AHB1_OTGHS 29 -#define STM32F4_RCC_AHB1_OTGHSULPI 30 - -#define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) -#define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) - -/* AHB2 */ -#define STM32F4_RCC_AHB2_DCMI 0 -#define STM32F4_RCC_AHB2_CRYP 4 -#define STM32F4_RCC_AHB2_HASH 5 -#define STM32F4_RCC_AHB2_RNG 6 -#define STM32F4_RCC_AHB2_OTGFS 7 - -#define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) -#define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) - -/* AHB3 */ -#define STM32F4_RCC_AHB3_FMC 0 -#define STM32F4_RCC_AHB3_QSPI 1 - -#define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) -#define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) - -/* APB1 */ -#define STM32F4_RCC_APB1_TIM2 0 -#define STM32F4_RCC_APB1_TIM3 1 -#define STM32F4_RCC_APB1_TIM4 2 -#define STM32F4_RCC_APB1_TIM5 3 -#define STM32F4_RCC_APB1_TIM6 4 -#define STM32F4_RCC_APB1_TIM7 5 -#define STM32F4_RCC_APB1_TIM12 6 -#define STM32F4_RCC_APB1_TIM13 7 -#define STM32F4_RCC_APB1_TIM14 8 -#define STM32F4_RCC_APB1_WWDG 11 -#define STM32F4_RCC_APB1_SPI2 14 -#define STM32F4_RCC_APB1_SPI3 15 -#define STM32F4_RCC_APB1_UART2 17 -#define STM32F4_RCC_APB1_UART3 18 -#define STM32F4_RCC_APB1_UART4 19 -#define STM32F4_RCC_APB1_UART5 20 -#define STM32F4_RCC_APB1_I2C1 21 -#define STM32F4_RCC_APB1_I2C2 22 -#define STM32F4_RCC_APB1_I2C3 23 -#define STM32F4_RCC_APB1_CAN1 25 -#define STM32F4_RCC_APB1_CAN2 26 -#define STM32F4_RCC_APB1_PWR 28 -#define STM32F4_RCC_APB1_DAC 29 -#define STM32F4_RCC_APB1_UART7 30 -#define STM32F4_RCC_APB1_UART8 31 - -#define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) -#define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80) - -/* APB2 */ -#define STM32F4_RCC_APB2_TIM1 0 -#define STM32F4_RCC_APB2_TIM8 1 -#define STM32F4_RCC_APB2_USART1 4 -#define STM32F4_RCC_APB2_USART6 5 -#define STM32F4_RCC_APB2_ADC1 8 -#define STM32F4_RCC_APB2_ADC2 9 -#define STM32F4_RCC_APB2_ADC3 10 -#define STM32F4_RCC_APB2_SDIO 11 -#define STM32F4_RCC_APB2_SPI1 12 -#define STM32F4_RCC_APB2_SPI4 13 -#define STM32F4_RCC_APB2_SYSCFG 14 -#define STM32F4_RCC_APB2_TIM9 16 -#define STM32F4_RCC_APB2_TIM10 17 -#define STM32F4_RCC_APB2_TIM11 18 -#define STM32F4_RCC_APB2_SPI5 20 -#define STM32F4_RCC_APB2_SPI6 21 -#define STM32F4_RCC_APB2_SAI1 22 -#define STM32F4_RCC_APB2_LTDC 26 -#define STM32F4_RCC_APB2_DSI 27 - -#define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) -#define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0) - -#endif /* _DT_BINDINGS_MFD_STM32F4_RCC_H */ diff --git a/include/dt-bindings/mfd/stm32f7-rcc.h b/include/dt-bindings/mfd/stm32f7-rcc.h deleted file mode 100644 index a4e4f927139..00000000000 --- a/include/dt-bindings/mfd/stm32f7-rcc.h +++ /dev/null @@ -1,116 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for the STM32F7 RCC IP - */ - -#ifndef _DT_BINDINGS_MFD_STM32F7_RCC_H -#define _DT_BINDINGS_MFD_STM32F7_RCC_H - -/* AHB1 */ -#define STM32F7_RCC_AHB1_GPIOA 0 -#define STM32F7_RCC_AHB1_GPIOB 1 -#define STM32F7_RCC_AHB1_GPIOC 2 -#define STM32F7_RCC_AHB1_GPIOD 3 -#define STM32F7_RCC_AHB1_GPIOE 4 -#define STM32F7_RCC_AHB1_GPIOF 5 -#define STM32F7_RCC_AHB1_GPIOG 6 -#define STM32F7_RCC_AHB1_GPIOH 7 -#define STM32F7_RCC_AHB1_GPIOI 8 -#define STM32F7_RCC_AHB1_GPIOJ 9 -#define STM32F7_RCC_AHB1_GPIOK 10 -#define STM32F7_RCC_AHB1_CRC 12 -#define STM32F7_RCC_AHB1_BKPSRAM 18 -#define STM32F7_RCC_AHB1_DTCMRAM 20 -#define STM32F7_RCC_AHB1_DMA1 21 -#define STM32F7_RCC_AHB1_DMA2 22 -#define STM32F7_RCC_AHB1_DMA2D 23 -#define STM32F7_RCC_AHB1_ETHMAC 25 -#define STM32F7_RCC_AHB1_ETHMACTX 26 -#define STM32F7_RCC_AHB1_ETHMACRX 27 -#define STM32FF_RCC_AHB1_ETHMACPTP 28 -#define STM32F7_RCC_AHB1_OTGHS 29 -#define STM32F7_RCC_AHB1_OTGHSULPI 30 - -#define STM32F7_AHB1_RESET(bit) (STM32F7_RCC_AHB1_##bit + (0x10 * 8)) -#define STM32F7_AHB1_CLOCK(bit) (STM32F7_RCC_AHB1_##bit) - - -/* AHB2 */ -#define STM32F7_RCC_AHB2_DCMI 0 -#define STM32F7_RCC_AHB2_CRYP 4 -#define STM32F7_RCC_AHB2_HASH 5 -#define STM32F7_RCC_AHB2_RNG 6 -#define STM32F7_RCC_AHB2_OTGFS 7 - -#define STM32F7_AHB2_RESET(bit) (STM32F7_RCC_AHB2_##bit + (0x14 * 8)) -#define STM32F7_AHB2_CLOCK(bit) (STM32F7_RCC_AHB2_##bit + 0x20) - -/* AHB3 */ -#define STM32F7_RCC_AHB3_FMC 0 -#define STM32F7_RCC_AHB3_QSPI 1 - -#define STM32F7_AHB3_RESET(bit) (STM32F7_RCC_AHB3_##bit + (0x18 * 8)) -#define STM32F7_AHB3_CLOCK(bit) (STM32F7_RCC_AHB3_##bit + 0x40) - -/* APB1 */ -#define STM32F7_RCC_APB1_TIM2 0 -#define STM32F7_RCC_APB1_TIM3 1 -#define STM32F7_RCC_APB1_TIM4 2 -#define STM32F7_RCC_APB1_TIM5 3 -#define STM32F7_RCC_APB1_TIM6 4 -#define STM32F7_RCC_APB1_TIM7 5 -#define STM32F7_RCC_APB1_TIM12 6 -#define STM32F7_RCC_APB1_TIM13 7 -#define STM32F7_RCC_APB1_TIM14 8 -#define STM32F7_RCC_APB1_LPTIM1 9 -#define STM32F7_RCC_APB1_WWDG 11 -#define STM32F7_RCC_APB1_CAN3 13 -#define STM32F7_RCC_APB1_SPI2 14 -#define STM32F7_RCC_APB1_SPI3 15 -#define STM32F7_RCC_APB1_SPDIFRX 16 -#define STM32F7_RCC_APB1_UART2 17 -#define STM32F7_RCC_APB1_UART3 18 -#define STM32F7_RCC_APB1_UART4 19 -#define STM32F7_RCC_APB1_UART5 20 -#define STM32F7_RCC_APB1_I2C1 21 -#define STM32F7_RCC_APB1_I2C2 22 -#define STM32F7_RCC_APB1_I2C3 23 -#define STM32F7_RCC_APB1_I2C4 24 -#define STM32F7_RCC_APB1_CAN1 25 -#define STM32F7_RCC_APB1_CAN2 26 -#define STM32F7_RCC_APB1_CEC 27 -#define STM32F7_RCC_APB1_PWR 28 -#define STM32F7_RCC_APB1_DAC 29 -#define STM32F7_RCC_APB1_UART7 30 -#define STM32F7_RCC_APB1_UART8 31 - -#define STM32F7_APB1_RESET(bit) (STM32F7_RCC_APB1_##bit + (0x20 * 8)) -#define STM32F7_APB1_CLOCK(bit) (STM32F7_RCC_APB1_##bit + 0x80) - -/* APB2 */ -#define STM32F7_RCC_APB2_TIM1 0 -#define STM32F7_RCC_APB2_TIM8 1 -#define STM32F7_RCC_APB2_USART1 4 -#define STM32F7_RCC_APB2_USART6 5 -#define STM32F7_RCC_APB2_SDMMC2 7 -#define STM32F7_RCC_APB2_ADC1 8 -#define STM32F7_RCC_APB2_ADC2 9 -#define STM32F7_RCC_APB2_ADC3 10 -#define STM32F7_RCC_APB2_SDMMC1 11 -#define STM32F7_RCC_APB2_SPI1 12 -#define STM32F7_RCC_APB2_SPI4 13 -#define STM32F7_RCC_APB2_SYSCFG 14 -#define STM32F7_RCC_APB2_TIM9 16 -#define STM32F7_RCC_APB2_TIM10 17 -#define STM32F7_RCC_APB2_TIM11 18 -#define STM32F7_RCC_APB2_SPI5 20 -#define STM32F7_RCC_APB2_SPI6 21 -#define STM32F7_RCC_APB2_SAI1 22 -#define STM32F7_RCC_APB2_SAI2 23 -#define STM32F7_RCC_APB2_LTDC 26 -#define STM32F7_RCC_APB2_DSI 27 - -#define STM32F7_APB2_RESET(bit) (STM32F7_RCC_APB2_##bit + (0x24 * 8)) -#define STM32F7_APB2_CLOCK(bit) (STM32F7_RCC_APB2_##bit + 0xA0) - -#endif /* _DT_BINDINGS_MFD_STM32F7_RCC_H */ diff --git a/include/dt-bindings/mfd/stm32h7-rcc.h b/include/dt-bindings/mfd/stm32h7-rcc.h deleted file mode 100644 index 461a8e04453..00000000000 --- a/include/dt-bindings/mfd/stm32h7-rcc.h +++ /dev/null @@ -1,136 +0,0 @@ -/* - * This header provides constants for the STM32H7 RCC IP - */ - -#ifndef _DT_BINDINGS_MFD_STM32H7_RCC_H -#define _DT_BINDINGS_MFD_STM32H7_RCC_H - -/* AHB3 */ -#define STM32H7_RCC_AHB3_MDMA 0 -#define STM32H7_RCC_AHB3_DMA2D 4 -#define STM32H7_RCC_AHB3_JPGDEC 5 -#define STM32H7_RCC_AHB3_FMC 12 -#define STM32H7_RCC_AHB3_QUADSPI 14 -#define STM32H7_RCC_AHB3_SDMMC1 16 -#define STM32H7_RCC_AHB3_CPU 31 - -#define STM32H7_AHB3_RESET(bit) (STM32H7_RCC_AHB3_##bit + (0x7C * 8)) - -/* AHB1 */ -#define STM32H7_RCC_AHB1_DMA1 0 -#define STM32H7_RCC_AHB1_DMA2 1 -#define STM32H7_RCC_AHB1_ADC12 5 -#define STM32H7_RCC_AHB1_ART 14 -#define STM32H7_RCC_AHB1_ETH1MAC 15 -#define STM32H7_RCC_AHB1_USB1OTG 25 -#define STM32H7_RCC_AHB1_USB2OTG 27 - -#define STM32H7_AHB1_RESET(bit) (STM32H7_RCC_AHB1_##bit + (0x80 * 8)) - -/* AHB2 */ -#define STM32H7_RCC_AHB2_CAMITF 0 -#define STM32H7_RCC_AHB2_CRYPT 4 -#define STM32H7_RCC_AHB2_HASH 5 -#define STM32H7_RCC_AHB2_RNG 6 -#define STM32H7_RCC_AHB2_SDMMC2 9 - -#define STM32H7_AHB2_RESET(bit) (STM32H7_RCC_AHB2_##bit + (0x84 * 8)) - -/* AHB4 */ -#define STM32H7_RCC_AHB4_GPIOA 0 -#define STM32H7_RCC_AHB4_GPIOB 1 -#define STM32H7_RCC_AHB4_GPIOC 2 -#define STM32H7_RCC_AHB4_GPIOD 3 -#define STM32H7_RCC_AHB4_GPIOE 4 -#define STM32H7_RCC_AHB4_GPIOF 5 -#define STM32H7_RCC_AHB4_GPIOG 6 -#define STM32H7_RCC_AHB4_GPIOH 7 -#define STM32H7_RCC_AHB4_GPIOI 8 -#define STM32H7_RCC_AHB4_GPIOJ 9 -#define STM32H7_RCC_AHB4_GPIOK 10 -#define STM32H7_RCC_AHB4_CRC 19 -#define STM32H7_RCC_AHB4_BDMA 21 -#define STM32H7_RCC_AHB4_ADC3 24 -#define STM32H7_RCC_AHB4_HSEM 25 - -#define STM32H7_AHB4_RESET(bit) (STM32H7_RCC_AHB4_##bit + (0x88 * 8)) - -/* APB3 */ -#define STM32H7_RCC_APB3_LTDC 3 -#define STM32H7_RCC_APB3_DSI 4 - -#define STM32H7_APB3_RESET(bit) (STM32H7_RCC_APB3_##bit + (0x8C * 8)) - -/* APB1L */ -#define STM32H7_RCC_APB1L_TIM2 0 -#define STM32H7_RCC_APB1L_TIM3 1 -#define STM32H7_RCC_APB1L_TIM4 2 -#define STM32H7_RCC_APB1L_TIM5 3 -#define STM32H7_RCC_APB1L_TIM6 4 -#define STM32H7_RCC_APB1L_TIM7 5 -#define STM32H7_RCC_APB1L_TIM12 6 -#define STM32H7_RCC_APB1L_TIM13 7 -#define STM32H7_RCC_APB1L_TIM14 8 -#define STM32H7_RCC_APB1L_LPTIM1 9 -#define STM32H7_RCC_APB1L_SPI2 14 -#define STM32H7_RCC_APB1L_SPI3 15 -#define STM32H7_RCC_APB1L_SPDIF_RX 16 -#define STM32H7_RCC_APB1L_USART2 17 -#define STM32H7_RCC_APB1L_USART3 18 -#define STM32H7_RCC_APB1L_UART4 19 -#define STM32H7_RCC_APB1L_UART5 20 -#define STM32H7_RCC_APB1L_I2C1 21 -#define STM32H7_RCC_APB1L_I2C2 22 -#define STM32H7_RCC_APB1L_I2C3 23 -#define STM32H7_RCC_APB1L_HDMICEC 27 -#define STM32H7_RCC_APB1L_DAC12 29 -#define STM32H7_RCC_APB1L_USART7 30 -#define STM32H7_RCC_APB1L_USART8 31 - -#define STM32H7_APB1L_RESET(bit) (STM32H7_RCC_APB1L_##bit + (0x90 * 8)) - -/* APB1H */ -#define STM32H7_RCC_APB1H_CRS 1 -#define STM32H7_RCC_APB1H_SWP 2 -#define STM32H7_RCC_APB1H_OPAMP 4 -#define STM32H7_RCC_APB1H_MDIOS 5 -#define STM32H7_RCC_APB1H_FDCAN 8 - -#define STM32H7_APB1H_RESET(bit) (STM32H7_RCC_APB1H_##bit + (0x94 * 8)) - -/* APB2 */ -#define STM32H7_RCC_APB2_TIM1 0 -#define STM32H7_RCC_APB2_TIM8 1 -#define STM32H7_RCC_APB2_USART1 4 -#define STM32H7_RCC_APB2_USART6 5 -#define STM32H7_RCC_APB2_SPI1 12 -#define STM32H7_RCC_APB2_SPI4 13 -#define STM32H7_RCC_APB2_TIM15 16 -#define STM32H7_RCC_APB2_TIM16 17 -#define STM32H7_RCC_APB2_TIM17 18 -#define STM32H7_RCC_APB2_SPI5 20 -#define STM32H7_RCC_APB2_SAI1 22 -#define STM32H7_RCC_APB2_SAI2 23 -#define STM32H7_RCC_APB2_SAI3 24 -#define STM32H7_RCC_APB2_DFSDM1 28 -#define STM32H7_RCC_APB2_HRTIM 29 - -#define STM32H7_APB2_RESET(bit) (STM32H7_RCC_APB2_##bit + (0x98 * 8)) - -/* APB4 */ -#define STM32H7_RCC_APB4_SYSCFG 1 -#define STM32H7_RCC_APB4_LPUART1 3 -#define STM32H7_RCC_APB4_SPI6 5 -#define STM32H7_RCC_APB4_I2C4 7 -#define STM32H7_RCC_APB4_LPTIM2 9 -#define STM32H7_RCC_APB4_LPTIM3 10 -#define STM32H7_RCC_APB4_LPTIM4 11 -#define STM32H7_RCC_APB4_LPTIM5 12 -#define STM32H7_RCC_APB4_COMP12 14 -#define STM32H7_RCC_APB4_VREF 15 -#define STM32H7_RCC_APB4_SAI4 21 -#define STM32H7_RCC_APB4_TMPSENS 26 - -#define STM32H7_APB4_RESET(bit) (STM32H7_RCC_APB4_##bit + (0x9C * 8)) - -#endif /* _DT_BINDINGS_MFD_STM32H7_RCC_H */ |