summaryrefslogtreecommitdiff
path: root/include/dt-bindings/reset
diff options
context:
space:
mode:
Diffstat (limited to 'include/dt-bindings/reset')
-rw-r--r--include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h19
-rw-r--r--include/dt-bindings/reset/amlogic,meson-axg-reset.h123
-rw-r--r--include/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h53
-rw-r--r--include/dt-bindings/reset/amlogic,meson-g12a-reset.h137
-rw-r--r--include/dt-bindings/reset/amlogic,meson-gxbb-reset.h161
5 files changed, 0 insertions, 493 deletions
diff --git a/include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h b/include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h
deleted file mode 100644
index 1ef807856cb..00000000000
--- a/include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0 OR MIT)
- *
- * Copyright (c) 2018 Baylibre SAS.
- * Author: Jerome Brunet <jbrunet@baylibre.com>
- */
-
-#ifndef _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H
-#define _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H
-
-#define AXG_ARB_TODDR_A 0
-#define AXG_ARB_TODDR_B 1
-#define AXG_ARB_TODDR_C 2
-#define AXG_ARB_FRDDR_A 3
-#define AXG_ARB_FRDDR_B 4
-#define AXG_ARB_FRDDR_C 5
-#define AXG_ARB_TODDR_D 6
-#define AXG_ARB_FRDDR_D 7
-
-#endif /* _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H */
diff --git a/include/dt-bindings/reset/amlogic,meson-axg-reset.h b/include/dt-bindings/reset/amlogic,meson-axg-reset.h
deleted file mode 100644
index 0f2e0fe45ca..00000000000
--- a/include/dt-bindings/reset/amlogic,meson-axg-reset.h
+++ /dev/null
@@ -1,123 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
-/*
- * Copyright (c) 2016 BayLibre, SAS.
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- *
- * Copyright (c) 2017 Amlogic, inc.
- * Author: Yixun Lan <yixun.lan@amlogic.com>
- *
- */
-
-#ifndef _DT_BINDINGS_AMLOGIC_MESON_AXG_RESET_H
-#define _DT_BINDINGS_AMLOGIC_MESON_AXG_RESET_H
-
-/* RESET0 */
-#define RESET_HIU 0
-#define RESET_PCIE_A 1
-#define RESET_PCIE_B 2
-#define RESET_DDR_TOP 3
-/* 4 */
-#define RESET_VIU 5
-#define RESET_PCIE_PHY 6
-#define RESET_PCIE_APB 7
-/* 8 */
-/* 9 */
-#define RESET_VENC 10
-#define RESET_ASSIST 11
-/* 12 */
-#define RESET_VCBUS 13
-/* 14 */
-/* 15 */
-#define RESET_GIC 16
-#define RESET_CAPB3_DECODE 17
-/* 18-21 */
-#define RESET_SYS_CPU_CAPB3 22
-#define RESET_CBUS_CAPB3 23
-#define RESET_AHB_CNTL 24
-#define RESET_AHB_DATA 25
-#define RESET_VCBUS_CLK81 26
-#define RESET_MMC 27
-/* 28-31 */
-/* RESET1 */
-/* 32 */
-/* 33 */
-#define RESET_USB_OTG 34
-#define RESET_DDR 35
-#define RESET_AO_RESET 36
-/* 37 */
-#define RESET_AHB_SRAM 38
-/* 39 */
-/* 40 */
-#define RESET_DMA 41
-#define RESET_ISA 42
-#define RESET_ETHERNET 43
-/* 44 */
-#define RESET_SD_EMMC_B 45
-#define RESET_SD_EMMC_C 46
-#define RESET_ROM_BOOT 47
-#define RESET_SYS_CPU_0 48
-#define RESET_SYS_CPU_1 49
-#define RESET_SYS_CPU_2 50
-#define RESET_SYS_CPU_3 51
-#define RESET_SYS_CPU_CORE_0 52
-#define RESET_SYS_CPU_CORE_1 53
-#define RESET_SYS_CPU_CORE_2 54
-#define RESET_SYS_CPU_CORE_3 55
-#define RESET_SYS_PLL_DIV 56
-#define RESET_SYS_CPU_AXI 57
-#define RESET_SYS_CPU_L2 58
-#define RESET_SYS_CPU_P 59
-#define RESET_SYS_CPU_MBIST 60
-/* 61-63 */
-/* RESET2 */
-/* 64 */
-/* 65 */
-#define RESET_AUDIO 66
-/* 67 */
-#define RESET_MIPI_HOST 68
-#define RESET_AUDIO_LOCKER 69
-#define RESET_GE2D 70
-/* 71-76 */
-#define RESET_AO_CPU_RESET 77
-/* 78-95 */
-/* RESET3 */
-#define RESET_RING_OSCILLATOR 96
-/* 97-127 */
-/* RESET4 */
-/* 128 */
-/* 129 */
-#define RESET_MIPI_PHY 130
-/* 131-140 */
-#define RESET_VENCL 141
-#define RESET_I2C_MASTER_2 142
-#define RESET_I2C_MASTER_1 143
-/* 144-159 */
-/* RESET5 */
-/* 160-191 */
-/* RESET6 */
-#define RESET_PERIPHS_GENERAL 192
-#define RESET_PERIPHS_SPICC 193
-/* 194 */
-/* 195 */
-#define RESET_PERIPHS_I2C_MASTER_0 196
-/* 197-200 */
-#define RESET_PERIPHS_UART_0 201
-#define RESET_PERIPHS_UART_1 202
-/* 203-204 */
-#define RESET_PERIPHS_SPI_0 205
-#define RESET_PERIPHS_I2C_MASTER_3 206
-/* 207-223 */
-/* RESET7 */
-#define RESET_USB_DDR_0 224
-#define RESET_USB_DDR_1 225
-#define RESET_USB_DDR_2 226
-#define RESET_USB_DDR_3 227
-/* 228 */
-#define RESET_DEVICE_MMC_ARB 229
-/* 230 */
-#define RESET_VID_LOCK 231
-#define RESET_A9_DMC_PIPEL 232
-#define RESET_DMC_VPU_PIPEL 233
-/* 234-255 */
-
-#endif
diff --git a/include/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h b/include/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h
deleted file mode 100644
index f805129ca7a..00000000000
--- a/include/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2019 BayLibre, SAS.
- * Author: Jerome Brunet <jbrunet@baylibre.com>
- *
- */
-
-#ifndef _DT_BINDINGS_AMLOGIC_MESON_G12A_AUDIO_RESET_H
-#define _DT_BINDINGS_AMLOGIC_MESON_G12A_AUDIO_RESET_H
-
-#define AUD_RESET_PDM 0
-#define AUD_RESET_TDMIN_A 1
-#define AUD_RESET_TDMIN_B 2
-#define AUD_RESET_TDMIN_C 3
-#define AUD_RESET_TDMIN_LB 4
-#define AUD_RESET_LOOPBACK 5
-#define AUD_RESET_TODDR_A 6
-#define AUD_RESET_TODDR_B 7
-#define AUD_RESET_TODDR_C 8
-#define AUD_RESET_FRDDR_A 9
-#define AUD_RESET_FRDDR_B 10
-#define AUD_RESET_FRDDR_C 11
-#define AUD_RESET_TDMOUT_A 12
-#define AUD_RESET_TDMOUT_B 13
-#define AUD_RESET_TDMOUT_C 14
-#define AUD_RESET_SPDIFOUT 15
-#define AUD_RESET_SPDIFOUT_B 16
-#define AUD_RESET_SPDIFIN 17
-#define AUD_RESET_EQDRC 18
-#define AUD_RESET_RESAMPLE 19
-#define AUD_RESET_DDRARB 20
-#define AUD_RESET_POWDET 21
-#define AUD_RESET_TORAM 22
-#define AUD_RESET_TOACODEC 23
-#define AUD_RESET_TOHDMITX 24
-#define AUD_RESET_CLKTREE 25
-
-/* SM1 added resets */
-#define AUD_RESET_RESAMPLE_B 26
-#define AUD_RESET_TOVAD 27
-#define AUD_RESET_LOCKER 28
-#define AUD_RESET_SPDIFIN_LB 29
-#define AUD_RESET_FRATV 30
-#define AUD_RESET_FRHDMIRX 31
-#define AUD_RESET_FRDDR_D 32
-#define AUD_RESET_TODDR_D 33
-#define AUD_RESET_LOOPBACK_B 34
-#define AUD_RESET_EARCTX 35
-#define AUD_RESET_EARCRX 36
-#define AUD_RESET_FRDDR_E 37
-#define AUD_RESET_TODDR_E 38
-
-#endif
diff --git a/include/dt-bindings/reset/amlogic,meson-g12a-reset.h b/include/dt-bindings/reset/amlogic,meson-g12a-reset.h
deleted file mode 100644
index 6d487c5eba2..00000000000
--- a/include/dt-bindings/reset/amlogic,meson-g12a-reset.h
+++ /dev/null
@@ -1,137 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
-/*
- * Copyright (c) 2019 BayLibre, SAS.
- * Author: Jerome Brunet <jbrunet@baylibre.com>
- *
- */
-
-#ifndef _DT_BINDINGS_AMLOGIC_MESON_G12A_RESET_H
-#define _DT_BINDINGS_AMLOGIC_MESON_G12A_RESET_H
-
-/* RESET0 */
-#define RESET_HIU 0
-/* 1 */
-#define RESET_DOS 2
-/* 3-4 */
-#define RESET_VIU 5
-#define RESET_AFIFO 6
-#define RESET_VID_PLL_DIV 7
-/* 8-9 */
-#define RESET_VENC 10
-#define RESET_ASSIST 11
-#define RESET_PCIE_CTRL_A 12
-#define RESET_VCBUS 13
-#define RESET_PCIE_PHY 14
-#define RESET_PCIE_APB 15
-#define RESET_GIC 16
-#define RESET_CAPB3_DECODE 17
-/* 18 */
-#define RESET_HDMITX_CAPB3 19
-#define RESET_DVALIN_CAPB3 20
-#define RESET_DOS_CAPB3 21
-/* 22 */
-#define RESET_CBUS_CAPB3 23
-#define RESET_AHB_CNTL 24
-#define RESET_AHB_DATA 25
-#define RESET_VCBUS_CLK81 26
-/* 27-31 */
-/* RESET1 */
-/* 32 */
-#define RESET_DEMUX 33
-#define RESET_USB 34
-#define RESET_DDR 35
-/* 36 */
-#define RESET_BT656 37
-#define RESET_AHB_SRAM 38
-/* 39 */
-#define RESET_PARSER 40
-/* 41 */
-#define RESET_ISA 42
-#define RESET_ETHERNET 43
-#define RESET_SD_EMMC_A 44
-#define RESET_SD_EMMC_B 45
-#define RESET_SD_EMMC_C 46
-/* 47 */
-#define RESET_USB_PHY20 48
-#define RESET_USB_PHY21 49
-/* 50-60 */
-#define RESET_AUDIO_CODEC 61
-/* 62-63 */
-/* RESET2 */
-/* 64 */
-#define RESET_AUDIO 65
-#define RESET_HDMITX_PHY 66
-/* 67 */
-#define RESET_MIPI_DSI_HOST 68
-#define RESET_ALOCKER 69
-#define RESET_GE2D 70
-#define RESET_PARSER_REG 71
-#define RESET_PARSER_FETCH 72
-#define RESET_CTL 73
-#define RESET_PARSER_TOP 74
-/* 75-77 */
-#define RESET_DVALIN 78
-#define RESET_HDMITX 79
-/* 80-95 */
-/* RESET3 */
-/* 96-95 */
-#define RESET_DEMUX_TOP 105
-#define RESET_DEMUX_DES_PL 106
-#define RESET_DEMUX_S2P_0 107
-#define RESET_DEMUX_S2P_1 108
-#define RESET_DEMUX_0 109
-#define RESET_DEMUX_1 110
-#define RESET_DEMUX_2 111
-/* 112-127 */
-/* RESET4 */
-/* 128-129 */
-#define RESET_MIPI_DSI_PHY 130
-/* 131-132 */
-#define RESET_RDMA 133
-#define RESET_VENCI 134
-#define RESET_VENCP 135
-/* 136 */
-#define RESET_VDAC 137
-/* 138-139 */
-#define RESET_VDI6 140
-#define RESET_VENCL 141
-#define RESET_I2C_M1 142
-#define RESET_I2C_M2 143
-/* 144-159 */
-/* RESET5 */
-/* 160-191 */
-/* RESET6 */
-#define RESET_GEN 192
-#define RESET_SPICC0 193
-#define RESET_SC 194
-#define RESET_SANA_3 195
-#define RESET_I2C_M0 196
-#define RESET_TS_PLL 197
-#define RESET_SPICC1 198
-#define RESET_STREAM 199
-#define RESET_TS_CPU 200
-#define RESET_UART0 201
-#define RESET_UART1_2 202
-#define RESET_ASYNC0 203
-#define RESET_ASYNC1 204
-#define RESET_SPIFC0 205
-#define RESET_I2C_M3 206
-/* 207-223 */
-/* RESET7 */
-#define RESET_USB_DDR_0 224
-#define RESET_USB_DDR_1 225
-#define RESET_USB_DDR_2 226
-#define RESET_USB_DDR_3 227
-#define RESET_TS_GPU 228
-#define RESET_DEVICE_MMC_ARB 229
-#define RESET_DVALIN_DMC_PIPL 230
-#define RESET_VID_LOCK 231
-#define RESET_NIC_DMC_PIPL 232
-#define RESET_DMC_VPU_PIPL 233
-#define RESET_GE2D_DMC_PIPL 234
-#define RESET_HCODEC_DMC_PIPL 235
-#define RESET_WAVE420_DMC_PIPL 236
-#define RESET_HEVCF_DMC_PIPL 237
-/* 238-255 */
-
-#endif
diff --git a/include/dt-bindings/reset/amlogic,meson-gxbb-reset.h b/include/dt-bindings/reset/amlogic,meson-gxbb-reset.h
deleted file mode 100644
index 883bfd3bcba..00000000000
--- a/include/dt-bindings/reset/amlogic,meson-gxbb-reset.h
+++ /dev/null
@@ -1,161 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
-/*
- * Copyright (c) 2016 BayLibre, SAS.
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- */
-#ifndef _DT_BINDINGS_AMLOGIC_MESON_GXBB_RESET_H
-#define _DT_BINDINGS_AMLOGIC_MESON_GXBB_RESET_H
-
-/* RESET0 */
-#define RESET_HIU 0
-/* 1 */
-#define RESET_DOS_RESET 2
-#define RESET_DDR_TOP 3
-#define RESET_DCU_RESET 4
-#define RESET_VIU 5
-#define RESET_AIU 6
-#define RESET_VID_PLL_DIV 7
-/* 8 */
-#define RESET_PMUX 9
-#define RESET_VENC 10
-#define RESET_ASSIST 11
-#define RESET_AFIFO2 12
-#define RESET_VCBUS 13
-/* 14 */
-/* 15 */
-#define RESET_GIC 16
-#define RESET_CAPB3_DECODE 17
-#define RESET_NAND_CAPB3 18
-#define RESET_HDMITX_CAPB3 19
-#define RESET_MALI_CAPB3 20
-#define RESET_DOS_CAPB3 21
-#define RESET_SYS_CPU_CAPB3 22
-#define RESET_CBUS_CAPB3 23
-#define RESET_AHB_CNTL 24
-#define RESET_AHB_DATA 25
-#define RESET_VCBUS_CLK81 26
-#define RESET_MMC 27
-#define RESET_MIPI_0 28
-#define RESET_MIPI_1 29
-#define RESET_MIPI_2 30
-#define RESET_MIPI_3 31
-/* RESET1 */
-#define RESET_CPPM 32
-#define RESET_DEMUX 33
-#define RESET_USB_OTG 34
-#define RESET_DDR 35
-#define RESET_AO_RESET 36
-#define RESET_BT656 37
-#define RESET_AHB_SRAM 38
-/* 39 */
-#define RESET_PARSER 40
-#define RESET_BLKMV 41
-#define RESET_ISA 42
-#define RESET_ETHERNET 43
-#define RESET_SD_EMMC_A 44
-#define RESET_SD_EMMC_B 45
-#define RESET_SD_EMMC_C 46
-#define RESET_ROM_BOOT 47
-#define RESET_SYS_CPU_0 48
-#define RESET_SYS_CPU_1 49
-#define RESET_SYS_CPU_2 50
-#define RESET_SYS_CPU_3 51
-#define RESET_SYS_CPU_CORE_0 52
-#define RESET_SYS_CPU_CORE_1 53
-#define RESET_SYS_CPU_CORE_2 54
-#define RESET_SYS_CPU_CORE_3 55
-#define RESET_SYS_PLL_DIV 56
-#define RESET_SYS_CPU_AXI 57
-#define RESET_SYS_CPU_L2 58
-#define RESET_SYS_CPU_P 59
-#define RESET_SYS_CPU_MBIST 60
-#define RESET_ACODEC 61
-/* 62 */
-/* 63 */
-/* RESET2 */
-#define RESET_VD_RMEM 64
-#define RESET_AUDIN 65
-#define RESET_HDMI_TX 66
-/* 67 */
-/* 68 */
-/* 69 */
-#define RESET_GE2D 70
-#define RESET_PARSER_REG 71
-#define RESET_PARSER_FETCH 72
-#define RESET_PARSER_CTL 73
-#define RESET_PARSER_TOP 74
-/* 75 */
-/* 76 */
-#define RESET_AO_CPU_RESET 77
-#define RESET_MALI 78
-#define RESET_HDMI_SYSTEM_RESET 79
-/* 80-95 */
-/* RESET3 */
-#define RESET_RING_OSCILLATOR 96
-#define RESET_SYS_CPU 97
-#define RESET_EFUSE 98
-#define RESET_SYS_CPU_BVCI 99
-#define RESET_AIFIFO 100
-#define RESET_TVFE 101
-#define RESET_AHB_BRIDGE_CNTL 102
-/* 103 */
-#define RESET_AUDIO_DAC 104
-#define RESET_DEMUX_TOP 105
-#define RESET_DEMUX_DES 106
-#define RESET_DEMUX_S2P_0 107
-#define RESET_DEMUX_S2P_1 108
-#define RESET_DEMUX_RESET_0 109
-#define RESET_DEMUX_RESET_1 110
-#define RESET_DEMUX_RESET_2 111
-/* 112-127 */
-/* RESET4 */
-/* 128 */
-/* 129 */
-/* 130 */
-/* 131 */
-#define RESET_DVIN_RESET 132
-#define RESET_RDMA 133
-#define RESET_VENCI 134
-#define RESET_VENCP 135
-/* 136 */
-#define RESET_VDAC 137
-#define RESET_RTC 138
-/* 139 */
-#define RESET_VDI6 140
-#define RESET_VENCL 141
-#define RESET_I2C_MASTER_2 142
-#define RESET_I2C_MASTER_1 143
-/* 144-159 */
-/* RESET5 */
-/* 160-191 */
-/* RESET6 */
-#define RESET_PERIPHS_GENERAL 192
-#define RESET_PERIPHS_SPICC 193
-#define RESET_PERIPHS_SMART_CARD 194
-#define RESET_PERIPHS_SAR_ADC 195
-#define RESET_PERIPHS_I2C_MASTER_0 196
-#define RESET_SANA 197
-/* 198 */
-#define RESET_PERIPHS_STREAM_INTERFACE 199
-#define RESET_PERIPHS_SDIO 200
-#define RESET_PERIPHS_UART_0 201
-#define RESET_PERIPHS_UART_1_2 202
-#define RESET_PERIPHS_ASYNC_0 203
-#define RESET_PERIPHS_ASYNC_1 204
-#define RESET_PERIPHS_SPI_0 205
-#define RESET_PERIPHS_SDHC 206
-#define RESET_UART_SLIP 207
-/* 208-223 */
-/* RESET7 */
-#define RESET_USB_DDR_0 224
-#define RESET_USB_DDR_1 225
-#define RESET_USB_DDR_2 226
-#define RESET_USB_DDR_3 227
-/* 228 */
-#define RESET_DEVICE_MMC_ARB 229
-/* 230 */
-#define RESET_VID_LOCK 231
-#define RESET_A9_DMC_PIPEL 232
-/* 233-255 */
-
-#endif
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-02 20:07:47 +0000