diff options
Diffstat (limited to 'include/dt-bindings')
-rw-r--r-- | include/dt-bindings/clock/mt7622-clk.h | 68 | ||||
-rw-r--r-- | include/dt-bindings/clock/mt7623-clk.h | 832 | ||||
-rw-r--r-- | include/dt-bindings/clock/mt7981-clk.h | 429 | ||||
-rw-r--r-- | include/dt-bindings/clock/mt7986-clk.h | 359 | ||||
-rw-r--r-- | include/dt-bindings/clock/mt7988-clk.h | 545 | ||||
-rw-r--r-- | include/dt-bindings/clock/px30-cru.h | 389 | ||||
-rw-r--r-- | include/dt-bindings/clock/rockchip,rk808.h | 11 | ||||
-rw-r--r-- | include/dt-bindings/pinctrl/sandbox-pinmux.h | 1 | ||||
-rw-r--r-- | include/dt-bindings/power/px30-power.h | 27 | ||||
-rw-r--r-- | include/dt-bindings/soc/rockchip,boot-mode.h | 16 | ||||
-rw-r--r-- | include/dt-bindings/soc/rockchip,vop2.h | 18 |
11 files changed, 1057 insertions, 1638 deletions
diff --git a/include/dt-bindings/clock/mt7622-clk.h b/include/dt-bindings/clock/mt7622-clk.h index 76fcaff0e42..cdbcaef76eb 100644 --- a/include/dt-bindings/clock/mt7622-clk.h +++ b/include/dt-bindings/clock/mt7622-clk.h @@ -117,46 +117,51 @@ #define CLK_TOP_I2S1_MCK_DIV_PD 104 #define CLK_TOP_I2S2_MCK_DIV_PD 105 #define CLK_TOP_I2S3_MCK_DIV_PD 106 +#define CLK_TOP_A1SYS_HP_DIV_PD 107 +#define CLK_TOP_A2SYS_HP_DIV_PD 108 /* INFRACFG */ -#define CLK_INFRA_DBGCLK_PD 0 -#define CLK_INFRA_TRNG 1 +#define CLK_INFRA_MUX1_SEL 0 +#define CLK_INFRA_DBGCLK_PD 1 #define CLK_INFRA_AUDIO_PD 2 #define CLK_INFRA_IRRX_PD 3 #define CLK_INFRA_APXGPT_PD 4 #define CLK_INFRA_PMIC_PD 5 +#define CLK_INFRA_TRNG 6 /* PERICFG */ -#define CLK_PERI_THERM_PD 0 -#define CLK_PERI_PWM1_PD 1 -#define CLK_PERI_PWM2_PD 2 -#define CLK_PERI_PWM3_PD 3 -#define CLK_PERI_PWM4_PD 4 -#define CLK_PERI_PWM5_PD 5 -#define CLK_PERI_PWM6_PD 6 -#define CLK_PERI_PWM7_PD 7 -#define CLK_PERI_PWM_PD 8 -#define CLK_PERI_AP_DMA_PD 9 -#define CLK_PERI_MSDC30_0_PD 10 -#define CLK_PERI_MSDC30_1_PD 11 -#define CLK_PERI_UART0_PD 12 -#define CLK_PERI_UART1_PD 13 -#define CLK_PERI_UART2_PD 14 -#define CLK_PERI_UART3_PD 15 -#define CLK_PERI_BTIF_PD 16 -#define CLK_PERI_I2C0_PD 17 -#define CLK_PERI_I2C1_PD 18 -#define CLK_PERI_I2C2_PD 19 -#define CLK_PERI_SPI1_PD 20 -#define CLK_PERI_AUXADC_PD 21 -#define CLK_PERI_SPI0_PD 22 -#define CLK_PERI_SNFI_PD 23 -#define CLK_PERI_NFI_PD 24 -#define CLK_PERI_NFIECC_PD 25 -#define CLK_PERI_FLASH_PD 26 -#define CLK_PERI_IRTX_PD 27 +#define CLK_PERIBUS_SEL 0 +#define CLK_PERI_THERM_PD 1 +#define CLK_PERI_PWM1_PD 2 +#define CLK_PERI_PWM2_PD 3 +#define CLK_PERI_PWM3_PD 4 +#define CLK_PERI_PWM4_PD 5 +#define CLK_PERI_PWM5_PD 6 +#define CLK_PERI_PWM6_PD 7 +#define CLK_PERI_PWM7_PD 8 +#define CLK_PERI_PWM_PD 9 +#define CLK_PERI_AP_DMA_PD 10 +#define CLK_PERI_MSDC30_0_PD 11 +#define CLK_PERI_MSDC30_1_PD 12 +#define CLK_PERI_UART0_PD 13 +#define CLK_PERI_UART1_PD 14 +#define CLK_PERI_UART2_PD 15 +#define CLK_PERI_UART3_PD 16 +#define CLK_PERI_UART4_PD 17 +#define CLK_PERI_BTIF_PD 18 +#define CLK_PERI_I2C0_PD 19 +#define CLK_PERI_I2C1_PD 20 +#define CLK_PERI_I2C2_PD 21 +#define CLK_PERI_SPI1_PD 22 +#define CLK_PERI_AUXADC_PD 23 +#define CLK_PERI_SPI0_PD 24 +#define CLK_PERI_SNFI_PD 25 +#define CLK_PERI_NFI_PD 26 +#define CLK_PERI_NFIECC_PD 27 +#define CLK_PERI_FLASH_PD 28 +#define CLK_PERI_IRTX_PD 29 /* APMIXEDSYS */ @@ -169,6 +174,7 @@ #define CLK_APMIXED_AUD2PLL 6 #define CLK_APMIXED_TRGPLL 7 #define CLK_APMIXED_SGMIPLL 8 +#define CLK_APMIXED_MAIN_CORE_EN 9 /* AUDIOSYS */ @@ -206,7 +212,7 @@ #define CLK_AUDIO_DLMCH 31 #define CLK_AUDIO_ARB1 32 #define CLK_AUDIO_AWB 33 -#define CLK_AUDIO_AWB3 34 +#define CLK_AUDIO_AWB2 34 #define CLK_AUDIO_DAI 35 #define CLK_AUDIO_MOD 36 #define CLK_AUDIO_ASRCI3 37 diff --git a/include/dt-bindings/clock/mt7623-clk.h b/include/dt-bindings/clock/mt7623-clk.h index 71ced1593af..0caeb65c3d2 100644 --- a/include/dt-bindings/clock/mt7623-clk.h +++ b/include/dt-bindings/clock/mt7623-clk.h @@ -7,407 +7,477 @@ #define _DT_BINDINGS_CLK_MT2701_H /* TOPCKGEN */ -#define CLK_TOP_FCLKS_OFF 0 - -#define CLK_TOP_DPI 0 -#define CLK_TOP_DMPLL 1 -#define CLK_TOP_VENCPLL 2 -#define CLK_TOP_HDMI_0_PIX340M 3 -#define CLK_TOP_HDMI_0_DEEP340M 4 -#define CLK_TOP_HDMI_0_PLL340M 5 -#define CLK_TOP_HADDS2_FB 6 -#define CLK_TOP_WBG_DIG_416M 7 -#define CLK_TOP_DSI0_LNTC_DSI 8 -#define CLK_TOP_HDMI_SCL_RX 9 -#define CLK_TOP_32K_EXTERNAL 10 -#define CLK_TOP_HDMITX_CLKDIG_CTS 11 -#define CLK_TOP_AUD_EXT1 12 -#define CLK_TOP_AUD_EXT2 13 -#define CLK_TOP_NFI1X_PAD 14 - -#define CLK_TOP_SYSPLL 15 -#define CLK_TOP_SYSPLL_D2 16 -#define CLK_TOP_SYSPLL_D3 17 -#define CLK_TOP_SYSPLL_D5 18 -#define CLK_TOP_SYSPLL_D7 19 -#define CLK_TOP_SYSPLL1_D2 20 -#define CLK_TOP_SYSPLL1_D4 21 -#define CLK_TOP_SYSPLL1_D8 22 -#define CLK_TOP_SYSPLL1_D16 23 -#define CLK_TOP_SYSPLL2_D2 24 -#define CLK_TOP_SYSPLL2_D4 25 -#define CLK_TOP_SYSPLL2_D8 26 -#define CLK_TOP_SYSPLL3_D2 27 -#define CLK_TOP_SYSPLL3_D4 28 -#define CLK_TOP_SYSPLL4_D2 29 -#define CLK_TOP_SYSPLL4_D4 30 -#define CLK_TOP_UNIVPLL 31 -#define CLK_TOP_UNIVPLL_D2 32 -#define CLK_TOP_UNIVPLL_D3 33 -#define CLK_TOP_UNIVPLL_D5 34 -#define CLK_TOP_UNIVPLL_D7 35 -#define CLK_TOP_UNIVPLL_D26 36 -#define CLK_TOP_UNIVPLL_D52 37 -#define CLK_TOP_UNIVPLL_D108 38 -#define CLK_TOP_USB_PHY48M 39 -#define CLK_TOP_UNIVPLL1_D2 40 -#define CLK_TOP_UNIVPLL1_D4 41 -#define CLK_TOP_UNIVPLL1_D8 42 -#define CLK_TOP_UNIVPLL2_D2 43 -#define CLK_TOP_UNIVPLL2_D4 44 -#define CLK_TOP_UNIVPLL2_D8 45 -#define CLK_TOP_UNIVPLL2_D16 46 -#define CLK_TOP_UNIVPLL2_D32 47 -#define CLK_TOP_UNIVPLL3_D2 48 -#define CLK_TOP_UNIVPLL3_D4 49 -#define CLK_TOP_UNIVPLL3_D8 50 -#define CLK_TOP_MSDCPLL 51 -#define CLK_TOP_MSDCPLL_D2 52 -#define CLK_TOP_MSDCPLL_D4 53 -#define CLK_TOP_MSDCPLL_D8 54 -#define CLK_TOP_MMPLL 55 -#define CLK_TOP_MMPLL_D2 56 -#define CLK_TOP_DMPLL_D2 57 -#define CLK_TOP_DMPLL_D4 58 -#define CLK_TOP_DMPLL_X2 59 -#define CLK_TOP_TVDPLL 60 -#define CLK_TOP_TVDPLL_D2 61 -#define CLK_TOP_TVDPLL_D4 62 -#define CLK_TOP_VDECPLL 63 -#define CLK_TOP_TVD2PLL 64 -#define CLK_TOP_TVD2PLL_D2 65 -#define CLK_TOP_MIPIPLL 66 -#define CLK_TOP_MIPIPLL_D2 67 -#define CLK_TOP_MIPIPLL_D4 68 -#define CLK_TOP_HDMIPLL 69 -#define CLK_TOP_HDMIPLL_D2 70 -#define CLK_TOP_HDMIPLL_D3 71 -#define CLK_TOP_ARMPLL_1P3G 72 -#define CLK_TOP_AUDPLL 73 -#define CLK_TOP_AUDPLL_D4 74 -#define CLK_TOP_AUDPLL_D8 75 -#define CLK_TOP_AUDPLL_D16 76 -#define CLK_TOP_AUDPLL_D24 77 -#define CLK_TOP_AUD1PLL_98M 78 -#define CLK_TOP_AUD2PLL_90M 79 -#define CLK_TOP_HADDS2PLL_98M 80 -#define CLK_TOP_HADDS2PLL_294M 81 -#define CLK_TOP_ETHPLL_500M 82 -#define CLK_TOP_CLK26M_D8 83 -#define CLK_TOP_32K_INTERNAL 84 -#define CLK_TOP_AXISEL_D4 85 -#define CLK_TOP_8BDAC 86 - -#define CLK_TOP_AXI_SEL 87 -#define CLK_TOP_MEM_SEL 88 -#define CLK_TOP_DDRPHYCFG_SEL 89 -#define CLK_TOP_MM_SEL 90 -#define CLK_TOP_PWM_SEL 91 -#define CLK_TOP_VDEC_SEL 92 -#define CLK_TOP_MFG_SEL 93 -#define CLK_TOP_CAMTG_SEL 94 -#define CLK_TOP_UART_SEL 95 -#define CLK_TOP_SPI0_SEL 96 -#define CLK_TOP_USB20_SEL 97 -#define CLK_TOP_MSDC30_0_SEL 98 -#define CLK_TOP_MSDC30_1_SEL 99 -#define CLK_TOP_MSDC30_2_SEL 100 -#define CLK_TOP_AUDIO_SEL 101 -#define CLK_TOP_AUDINTBUS_SEL 102 -#define CLK_TOP_PMICSPI_SEL 103 -#define CLK_TOP_SCP_SEL 104 -#define CLK_TOP_DPI0_SEL 105 -#define CLK_TOP_DPI1_SEL 106 -#define CLK_TOP_TVE_SEL 107 -#define CLK_TOP_HDMI_SEL 108 -#define CLK_TOP_APLL_SEL 109 -#define CLK_TOP_RTC_SEL 110 -#define CLK_TOP_NFI2X_SEL 111 -#define CLK_TOP_EMMC_HCLK_SEL 112 -#define CLK_TOP_FLASH_SEL 113 -#define CLK_TOP_DI_SEL 114 -#define CLK_TOP_NR_SEL 115 -#define CLK_TOP_OSD_SEL 116 -#define CLK_TOP_HDMIRX_BIST_SEL 117 -#define CLK_TOP_INTDIR_SEL 118 -#define CLK_TOP_ASM_I_SEL 119 -#define CLK_TOP_ASM_M_SEL 120 -#define CLK_TOP_ASM_H_SEL 121 -#define CLK_TOP_MS_CARD_SEL 122 -#define CLK_TOP_ETHIF_SEL 123 -#define CLK_TOP_HDMIRX26_24_SEL 124 -#define CLK_TOP_MSDC30_3_SEL 125 -#define CLK_TOP_CMSYS_SEL 126 -#define CLK_TOP_SPI1_SEL 127 -#define CLK_TOP_SPI2_SEL 128 -#define CLK_TOP_8BDAC_SEL 129 -#define CLK_TOP_AUD2DVD_SEL 130 -#define CLK_TOP_PADMCLK_SEL 131 -#define CLK_TOP_AUD_MUX1_SEL 132 -#define CLK_TOP_AUD_MUX2_SEL 133 -#define CLK_TOP_AUDPLL_MUX_SEL 134 -#define CLK_TOP_AUD_K1_SRC_SEL 135 -#define CLK_TOP_AUD_K2_SRC_SEL 136 -#define CLK_TOP_AUD_K3_SRC_SEL 137 -#define CLK_TOP_AUD_K4_SRC_SEL 138 -#define CLK_TOP_AUD_K5_SRC_SEL 139 -#define CLK_TOP_AUD_K6_SRC_SEL 140 - -#define CLK_TOP_AUD_EXTCK1_DIV 141 -#define CLK_TOP_AUD_EXTCK2_DIV 142 -#define CLK_TOP_AUD_MUX1_DIV 143 -#define CLK_TOP_AUD_MUX2_DIV 144 -#define CLK_TOP_AUD_K1_SRC_DIV 145 -#define CLK_TOP_AUD_K2_SRC_DIV 146 -#define CLK_TOP_AUD_K3_SRC_DIV 147 -#define CLK_TOP_AUD_K4_SRC_DIV 148 -#define CLK_TOP_AUD_K5_SRC_DIV 149 -#define CLK_TOP_AUD_K6_SRC_DIV 150 -#define CLK_TOP_AUD_48K_TIMING 151 -#define CLK_TOP_AUD_44K_TIMING 152 -#define CLK_TOP_AUD_I2S1_MCLK 153 -#define CLK_TOP_AUD_I2S2_MCLK 154 -#define CLK_TOP_AUD_I2S3_MCLK 155 -#define CLK_TOP_AUD_I2S4_MCLK 156 -#define CLK_TOP_AUD_I2S5_MCLK 157 -#define CLK_TOP_AUD_I2S6_MCLK 158 +#define CLK_TOP_SYSPLL 1 +#define CLK_TOP_SYSPLL_D2 2 +#define CLK_TOP_SYSPLL_D3 3 +#define CLK_TOP_SYSPLL_D5 4 +#define CLK_TOP_SYSPLL_D7 5 +#define CLK_TOP_SYSPLL1_D2 6 +#define CLK_TOP_SYSPLL1_D4 7 +#define CLK_TOP_SYSPLL1_D8 8 +#define CLK_TOP_SYSPLL1_D16 9 +#define CLK_TOP_SYSPLL2_D2 10 +#define CLK_TOP_SYSPLL2_D4 11 +#define CLK_TOP_SYSPLL2_D8 12 +#define CLK_TOP_SYSPLL3_D2 13 +#define CLK_TOP_SYSPLL3_D4 14 +#define CLK_TOP_SYSPLL4_D2 15 +#define CLK_TOP_SYSPLL4_D4 16 +#define CLK_TOP_UNIVPLL 17 +#define CLK_TOP_UNIVPLL_D2 18 +#define CLK_TOP_UNIVPLL_D3 19 +#define CLK_TOP_UNIVPLL_D5 20 +#define CLK_TOP_UNIVPLL_D7 21 +#define CLK_TOP_UNIVPLL_D26 22 +#define CLK_TOP_UNIVPLL_D52 23 +#define CLK_TOP_UNIVPLL_D108 24 +#define CLK_TOP_USB_PHY48M 25 +#define CLK_TOP_UNIVPLL1_D2 26 +#define CLK_TOP_UNIVPLL1_D4 27 +#define CLK_TOP_UNIVPLL1_D8 28 +#define CLK_TOP_UNIVPLL2_D2 29 +#define CLK_TOP_UNIVPLL2_D4 30 +#define CLK_TOP_UNIVPLL2_D8 31 +#define CLK_TOP_UNIVPLL2_D16 32 +#define CLK_TOP_UNIVPLL2_D32 33 +#define CLK_TOP_UNIVPLL3_D2 34 +#define CLK_TOP_UNIVPLL3_D4 35 +#define CLK_TOP_UNIVPLL3_D8 36 +#define CLK_TOP_MSDCPLL 37 +#define CLK_TOP_MSDCPLL_D2 38 +#define CLK_TOP_MSDCPLL_D4 39 +#define CLK_TOP_MSDCPLL_D8 40 +#define CLK_TOP_MMPLL 41 +#define CLK_TOP_MMPLL_D2 42 +#define CLK_TOP_DMPLL 43 +#define CLK_TOP_DMPLL_D2 44 +#define CLK_TOP_DMPLL_D4 45 +#define CLK_TOP_DMPLL_X2 46 +#define CLK_TOP_TVDPLL 47 +#define CLK_TOP_TVDPLL_D2 48 +#define CLK_TOP_TVDPLL_D4 49 +#define CLK_TOP_TVD2PLL 50 +#define CLK_TOP_TVD2PLL_D2 51 +#define CLK_TOP_HADDS2PLL_98M 52 +#define CLK_TOP_HADDS2PLL_294M 53 +#define CLK_TOP_HADDS2_FB 54 +#define CLK_TOP_MIPIPLL_D2 55 +#define CLK_TOP_MIPIPLL_D4 56 +#define CLK_TOP_HDMIPLL 57 +#define CLK_TOP_HDMIPLL_D2 58 +#define CLK_TOP_HDMIPLL_D3 59 +#define CLK_TOP_HDMI_SCL_RX 60 +#define CLK_TOP_HDMI_0_PIX340M 61 +#define CLK_TOP_HDMI_0_DEEP340M 62 +#define CLK_TOP_HDMI_0_PLL340M 63 +#define CLK_TOP_AUD1PLL_98M 64 +#define CLK_TOP_AUD2PLL_90M 65 +#define CLK_TOP_AUDPLL 66 +#define CLK_TOP_AUDPLL_D4 67 +#define CLK_TOP_AUDPLL_D8 68 +#define CLK_TOP_AUDPLL_D16 69 +#define CLK_TOP_AUDPLL_D24 70 +#define CLK_TOP_ETHPLL_500M 71 +#define CLK_TOP_VDECPLL 72 +#define CLK_TOP_VENCPLL 73 +#define CLK_TOP_MIPIPLL 74 +#define CLK_TOP_ARMPLL_1P3G 75 + +#define CLK_TOP_MM_SEL 76 +#define CLK_TOP_DDRPHYCFG_SEL 77 +#define CLK_TOP_MEM_SEL 78 +#define CLK_TOP_AXI_SEL 79 +#define CLK_TOP_CAMTG_SEL 80 +#define CLK_TOP_MFG_SEL 81 +#define CLK_TOP_VDEC_SEL 82 +#define CLK_TOP_PWM_SEL 83 +#define CLK_TOP_MSDC30_0_SEL 84 +#define CLK_TOP_USB20_SEL 85 +#define CLK_TOP_SPI0_SEL 86 +#define CLK_TOP_UART_SEL 87 +#define CLK_TOP_AUDINTBUS_SEL 88 +#define CLK_TOP_AUDIO_SEL 89 +#define CLK_TOP_MSDC30_2_SEL 90 +#define CLK_TOP_MSDC30_1_SEL 91 +#define CLK_TOP_DPI1_SEL 92 +#define CLK_TOP_DPI0_SEL 93 +#define CLK_TOP_SCP_SEL 94 +#define CLK_TOP_PMICSPI_SEL 95 +#define CLK_TOP_APLL_SEL 96 +#define CLK_TOP_HDMI_SEL 97 +#define CLK_TOP_TVE_SEL 98 +#define CLK_TOP_EMMC_HCLK_SEL 99 +#define CLK_TOP_NFI2X_SEL 100 +#define CLK_TOP_RTC_SEL 101 +#define CLK_TOP_OSD_SEL 102 +#define CLK_TOP_NR_SEL 103 +#define CLK_TOP_DI_SEL 104 +#define CLK_TOP_FLASH_SEL 105 +#define CLK_TOP_ASM_M_SEL 106 +#define CLK_TOP_ASM_I_SEL 107 +#define CLK_TOP_INTDIR_SEL 108 +#define CLK_TOP_HDMIRX_BIST_SEL 109 +#define CLK_TOP_ETHIF_SEL 110 +#define CLK_TOP_MS_CARD_SEL 111 +#define CLK_TOP_ASM_H_SEL 112 +#define CLK_TOP_SPI1_SEL 113 +#define CLK_TOP_CMSYS_SEL 114 +#define CLK_TOP_MSDC30_3_SEL 115 +#define CLK_TOP_HDMIRX26_24_SEL 116 +#define CLK_TOP_AUD2DVD_SEL 117 +#define CLK_TOP_8BDAC_SEL 118 +#define CLK_TOP_SPI2_SEL 119 +#define CLK_TOP_AUD_MUX1_SEL 120 +#define CLK_TOP_AUD_MUX2_SEL 121 +#define CLK_TOP_AUDPLL_MUX_SEL 122 +#define CLK_TOP_AUD_K1_SRC_SEL 123 +#define CLK_TOP_AUD_K2_SRC_SEL 124 +#define CLK_TOP_AUD_K3_SRC_SEL 125 +#define CLK_TOP_AUD_K4_SRC_SEL 126 +#define CLK_TOP_AUD_K5_SRC_SEL 127 +#define CLK_TOP_AUD_K6_SRC_SEL 128 +#define CLK_TOP_PADMCLK_SEL 129 +#define CLK_TOP_AUD_EXTCK1_DIV 130 +#define CLK_TOP_AUD_EXTCK2_DIV 131 +#define CLK_TOP_AUD_MUX1_DIV 132 +#define CLK_TOP_AUD_MUX2_DIV 133 +#define CLK_TOP_AUD_K1_SRC_DIV 134 +#define CLK_TOP_AUD_K2_SRC_DIV 135 +#define CLK_TOP_AUD_K3_SRC_DIV 136 +#define CLK_TOP_AUD_K4_SRC_DIV 137 +#define CLK_TOP_AUD_K5_SRC_DIV 138 +#define CLK_TOP_AUD_K6_SRC_DIV 139 +#define CLK_TOP_AUD_I2S1_MCLK 140 +#define CLK_TOP_AUD_I2S2_MCLK 141 +#define CLK_TOP_AUD_I2S3_MCLK 142 +#define CLK_TOP_AUD_I2S4_MCLK 143 +#define CLK_TOP_AUD_I2S5_MCLK 144 +#define CLK_TOP_AUD_I2S6_MCLK 145 +#define CLK_TOP_AUD_48K_TIMING 146 +#define CLK_TOP_AUD_44K_TIMING 147 + +#define CLK_TOP_32K_INTERNAL 148 +#define CLK_TOP_32K_EXTERNAL 149 +#define CLK_TOP_CLK26M_D8 150 +#define CLK_TOP_8BDAC 151 +#define CLK_TOP_WBG_DIG_416M 152 +#define CLK_TOP_DPI 153 +#define CLK_TOP_DSI0_LNTC_DSI 154 +#define CLK_TOP_AUD_EXT1 155 +#define CLK_TOP_AUD_EXT2 156 +#define CLK_TOP_NFI1X_PAD 157 +#define CLK_TOP_AXISEL_D4 158 #define CLK_TOP_NR 159 /* APMIXEDSYS */ -#define CLK_APMIXED_ARMPLL 0 -#define CLK_APMIXED_MAINPLL 1 -#define CLK_APMIXED_UNIVPLL 2 -#define CLK_APMIXED_MMPLL 3 -#define CLK_APMIXED_MSDCPLL 4 -#define CLK_APMIXED_TVDPLL 5 -#define CLK_APMIXED_AUD1PLL 6 -#define CLK_APMIXED_TRGPLL 7 -#define CLK_APMIXED_ETHPLL 8 -#define CLK_APMIXED_VDECPLL 9 -#define CLK_APMIXED_HADDS2PLL 10 -#define CLK_APMIXED_AUD2PLL 11 -#define CLK_APMIXED_TVD2PLL 12 -#define CLK_APMIXED_NR 13 + +#define CLK_APMIXED_ARMPLL 1 +#define CLK_APMIXED_MAINPLL 2 +#define CLK_APMIXED_UNIVPLL 3 +#define CLK_APMIXED_MMPLL 4 +#define CLK_APMIXED_MSDCPLL 5 +#define CLK_APMIXED_TVDPLL 6 +#define CLK_APMIXED_AUD1PLL 7 +#define CLK_APMIXED_TRGPLL 8 +#define CLK_APMIXED_ETHPLL 9 +#define CLK_APMIXED_VDECPLL 10 +#define CLK_APMIXED_HADDS2PLL 11 +#define CLK_APMIXED_AUD2PLL 12 +#define CLK_APMIXED_TVD2PLL 13 +#define CLK_APMIXED_HDMI_REF 14 +#define CLK_APMIXED_NR 15 + +/* DDRPHY */ + +#define CLK_DDRPHY_VENCPLL 1 +#define CLK_DDRPHY_NR 2 /* INFRACFG */ -#define CLK_INFRA_DBG 0 -#define CLK_INFRA_SMI 1 -#define CLK_INFRA_QAXI_CM4 2 -#define CLK_INFRA_AUD_SPLIN_B 3 -#define CLK_INFRA_AUDIO 4 -#define CLK_INFRA_EFUSE 5 -#define CLK_INFRA_L2C_SRAM 6 -#define CLK_INFRA_M4U 7 -#define CLK_INFRA_CONNMCU 8 -#define CLK_INFRA_TRNG 9 -#define CLK_INFRA_RAMBUFIF 10 -#define CLK_INFRA_CPUM 11 -#define CLK_INFRA_KP 12 -#define CLK_INFRA_CEC 13 -#define CLK_INFRA_IRRX 14 -#define CLK_INFRA_PMICSPI 15 -#define CLK_INFRA_PMICWRAP 16 -#define CLK_INFRA_DDCCI 17 -#define CLK_INFRA_CPUSEL 18 -#define CLK_INFRA_NR 19 + +#define CLK_INFRA_DBG 1 +#define CLK_INFRA_SMI 2 +#define CLK_INFRA_QAXI_CM4 3 +#define CLK_INFRA_AUD_SPLIN_B 4 +#define CLK_INFRA_AUDIO 5 +#define CLK_INFRA_EFUSE 6 +#define CLK_INFRA_L2C_SRAM 7 +#define CLK_INFRA_M4U 8 +#define CLK_INFRA_CONNMCU 9 +#define CLK_INFRA_TRNG 10 +#define CLK_INFRA_RAMBUFIF 11 +#define CLK_INFRA_CPUM 12 +#define CLK_INFRA_KP 13 +#define CLK_INFRA_CEC 14 +#define CLK_INFRA_IRRX 15 +#define CLK_INFRA_PMICSPI 16 +#define CLK_INFRA_PMICWRAP 17 +#define CLK_INFRA_DDCCI 18 +#define CLK_INFRA_CLK_13M 19 +#define CLK_INFRA_CPUSEL 20 +#define CLK_INFRA_NR 21 /* PERICFG */ -#define CLK_PERI_NFI 0 -#define CLK_PERI_THERM 1 -#define CLK_PERI_PWM1 2 -#define CLK_PERI_PWM2 3 -#define CLK_PERI_PWM3 4 -#define CLK_PERI_PWM4 5 -#define CLK_PERI_PWM5 6 -#define CLK_PERI_PWM6 7 -#define CLK_PERI_PWM7 8 -#define CLK_PERI_PWM 9 -#define CLK_PERI_USB0 10 -#define CLK_PERI_USB1 11 -#define CLK_PERI_AP_DMA 12 -#define CLK_PERI_MSDC30_0 13 -#define CLK_PERI_MSDC30_1 14 -#define CLK_PERI_MSDC30_2 15 -#define CLK_PERI_MSDC30_3 16 -#define CLK_PERI_MSDC50_3 17 -#define CLK_PERI_NLI 18 -#define CLK_PERI_UART0 19 -#define CLK_PERI_UART1 20 -#define CLK_PERI_UART2 21 -#define CLK_PERI_UART3 22 -#define CLK_PERI_BTIF 23 -#define CLK_PERI_I2C0 24 -#define CLK_PERI_I2C1 25 -#define CLK_PERI_I2C2 26 -#define CLK_PERI_I2C3 27 -#define CLK_PERI_AUXADC 28 -#define CLK_PERI_SPI0 39 -#define CLK_PERI_ETH 30 -#define CLK_PERI_USB0_MCU 31 - -#define CLK_PERI_USB1_MCU 32 -#define CLK_PERI_USB_SLV 33 -#define CLK_PERI_GCPU 34 -#define CLK_PERI_NFI_ECC 35 -#define CLK_PERI_NFI_PAD 36 -#define CLK_PERI_FLASH 37 -#define CLK_PERI_HOST89_INT 38 -#define CLK_PERI_HOST89_SPI 39 -#define CLK_PERI_HOST89_DVD 40 -#define CLK_PERI_SPI1 41 -#define CLK_PERI_SPI2 42 -#define CLK_PERI_FCI 43 -#define CLK_PERI_NR 44 + +#define CLK_PERI_NFI 1 +#define CLK_PERI_THERM 2 +#define CLK_PERI_PWM1 3 +#define CLK_PERI_PWM2 4 +#define CLK_PERI_PWM3 5 +#define CLK_PERI_PWM4 6 +#define CLK_PERI_PWM5 7 +#define CLK_PERI_PWM6 8 +#define CLK_PERI_PWM7 9 +#define CLK_PERI_PWM 10 +#define CLK_PERI_USB0 11 +#define CLK_PERI_USB1 12 +#define CLK_PERI_AP_DMA 13 +#define CLK_PERI_MSDC30_0 14 +#define CLK_PERI_MSDC30_1 15 +#define CLK_PERI_MSDC30_2 16 +#define CLK_PERI_MSDC30_3 17 +#define CLK_PERI_MSDC50_3 18 +#define CLK_PERI_NLI 19 +#define CLK_PERI_UART0 20 +#define CLK_PERI_UART1 21 +#define CLK_PERI_UART2 22 +#define CLK_PERI_UART3 23 +#define CLK_PERI_BTIF 24 +#define CLK_PERI_I2C0 25 +#define CLK_PERI_I2C1 26 +#define CLK_PERI_I2C2 27 +#define CLK_PERI_I2C3 28 +#define CLK_PERI_AUXADC 29 +#define CLK_PERI_SPI0 30 +#define CLK_PERI_ETH 31 +#define CLK_PERI_USB0_MCU 32 + +#define CLK_PERI_USB1_MCU 33 +#define CLK_PERI_USB_SLV 34 +#define CLK_PERI_GCPU 35 +#define CLK_PERI_NFI_ECC 36 +#define CLK_PERI_NFI_PAD 37 +#define CLK_PERI_FLASH 38 +#define CLK_PERI_HOST89_INT 39 +#define CLK_PERI_HOST89_SPI 40 +#define CLK_PERI_HOST89_DVD 41 +#define CLK_PERI_SPI1 42 +#define CLK_PERI_SPI2 43 +#define CLK_PERI_FCI 44 + +#define CLK_PERI_UART0_SEL 45 +#define CLK_PERI_UART1_SEL 46 +#define CLK_PERI_UART2_SEL 47 +#define CLK_PERI_UART3_SEL 48 +#define CLK_PERI_NR 49 /* AUDIO */ -#define CLK_AUD_AFE 0 -#define CLK_AUD_LRCK_DETECT 1 -#define CLK_AUD_I2S 2 -#define CLK_AUD_APLL_TUNER 3 -#define CLK_AUD_HDMI 4 -#define CLK_AUD_SPDF 5 -#define CLK_AUD_SPDF2 6 -#define CLK_AUD_APLL 7 -#define CLK_AUD_TML 8 -#define CLK_AUD_AHB_IDLE_EXT 9 -#define CLK_AUD_AHB_IDLE_INT 10 - -#define CLK_AUD_I2SIN1 11 -#define CLK_AUD_I2SIN2 12 -#define CLK_AUD_I2SIN3 13 -#define CLK_AUD_I2SIN4 14 -#define CLK_AUD_I2SIN5 15 -#define CLK_AUD_I2SIN6 16 -#define CLK_AUD_I2SO1 17 -#define CLK_AUD_I2SO2 18 -#define CLK_AUD_I2SO3 19 -#define CLK_AUD_I2SO4 20 -#define CLK_AUD_I2SO5 21 -#define CLK_AUD_I2SO6 22 -#define CLK_AUD_ASRCI1 23 -#define CLK_AUD_ASRCI2 24 -#define CLK_AUD_ASRCO1 25 -#define CLK_AUD_ASRCO2 26 -#define CLK_AUD_ASRC11 27 -#define CLK_AUD_ASRC12 28 -#define CLK_AUD_HDMIRX 29 -#define CLK_AUD_INTDIR 30 -#define CLK_AUD_A1SYS 31 -#define CLK_AUD_A2SYS 32 -#define CLK_AUD_AFE_CONN 33 -#define CLK_AUD_AFE_PCMIF 34 -#define CLK_AUD_AFE_MRGIF 35 - -#define CLK_AUD_MMIF_UL1 36 -#define CLK_AUD_MMIF_UL2 37 -#define CLK_AUD_MMIF_UL3 38 -#define CLK_AUD_MMIF_UL4 39 -#define CLK_AUD_MMIF_UL5 40 -#define CLK_AUD_MMIF_UL6 41 -#define CLK_AUD_MMIF_DL1 42 -#define CLK_AUD_MMIF_DL2 43 -#define CLK_AUD_MMIF_DL3 44 -#define CLK_AUD_MMIF_DL4 45 -#define CLK_AUD_MMIF_DL5 46 -#define CLK_AUD_MMIF_DL6 47 -#define CLK_AUD_MMIF_DLMCH 48 -#define CLK_AUD_MMIF_ARB1 49 -#define CLK_AUD_MMIF_AWB1 50 -#define CLK_AUD_MMIF_AWB2 51 -#define CLK_AUD_MMIF_DAI 52 - -#define CLK_AUD_DMIC1 53 -#define CLK_AUD_DMIC2 54 -#define CLK_AUD_ASRCI3 55 -#define CLK_AUD_ASRCI4 56 -#define CLK_AUD_ASRCI5 57 -#define CLK_AUD_ASRCI6 58 -#define CLK_AUD_ASRCO3 59 -#define CLK_AUD_ASRCO4 60 -#define CLK_AUD_ASRCO5 61 -#define CLK_AUD_ASRCO6 62 -#define CLK_AUD_MEM_ASRC1 63 -#define CLK_AUD_MEM_ASRC2 64 -#define CLK_AUD_MEM_ASRC3 65 -#define CLK_AUD_MEM_ASRC4 66 -#define CLK_AUD_MEM_ASRC5 67 -#define CLK_AUD_DSD_ENC 68 -#define CLK_AUD_ASRC_BRG 60 -#define CLK_AUD_NR 70 + +#define CLK_AUD_AFE 1 +#define CLK_AUD_LRCK_DETECT 2 +#define CLK_AUD_I2S 3 +#define CLK_AUD_APLL_TUNER 4 +#define CLK_AUD_HDMI 5 +#define CLK_AUD_SPDF 6 +#define CLK_AUD_SPDF2 7 +#define CLK_AUD_APLL 8 +#define CLK_AUD_TML 9 +#define CLK_AUD_AHB_IDLE_EXT 10 +#define CLK_AUD_AHB_IDLE_INT 11 + +#define CLK_AUD_I2SIN1 12 +#define CLK_AUD_I2SIN2 13 +#define CLK_AUD_I2SIN3 14 +#define CLK_AUD_I2SIN4 15 +#define CLK_AUD_I2SIN5 16 +#define CLK_AUD_I2SIN6 17 +#define CLK_AUD_I2SO1 18 +#define CLK_AUD_I2SO2 19 +#define CLK_AUD_I2SO3 20 +#define CLK_AUD_I2SO4 21 +#define CLK_AUD_I2SO5 22 +#define CLK_AUD_I2SO6 23 +#define CLK_AUD_ASRCI1 24 +#define CLK_AUD_ASRCI2 25 +#define CLK_AUD_ASRCO1 26 +#define CLK_AUD_ASRCO2 27 +#define CLK_AUD_ASRC11 28 +#define CLK_AUD_ASRC12 29 +#define CLK_AUD_HDMIRX 30 +#define CLK_AUD_INTDIR 31 +#define CLK_AUD_A1SYS 32 +#define CLK_AUD_A2SYS 33 +#define CLK_AUD_AFE_CONN 34 +#define CLK_AUD_AFE_PCMIF 35 +#define CLK_AUD_AFE_MRGIF 36 + +#define CLK_AUD_MMIF_UL1 37 +#define CLK_AUD_MMIF_UL2 38 +#define CLK_AUD_MMIF_UL3 39 +#define CLK_AUD_MMIF_UL4 40 +#define CLK_AUD_MMIF_UL5 41 +#define CLK_AUD_MMIF_UL6 42 +#define CLK_AUD_MMIF_DL1 43 +#define CLK_AUD_MMIF_DL2 44 +#define CLK_AUD_MMIF_DL3 45 +#define CLK_AUD_MMIF_DL4 46 +#define CLK_AUD_MMIF_DL5 47 +#define CLK_AUD_MMIF_DL6 48 +#define CLK_AUD_MMIF_DLMCH 49 +#define CLK_AUD_MMIF_ARB1 50 +#define CLK_AUD_MMIF_AWB1 51 +#define CLK_AUD_MMIF_AWB2 52 +#define CLK_AUD_MMIF_DAI 53 + +#define CLK_AUD_DMIC1 54 +#define CLK_AUD_DMIC2 55 +#define CLK_AUD_ASRCI3 56 +#define CLK_AUD_ASRCI4 57 +#define CLK_AUD_ASRCI5 58 +#define CLK_AUD_ASRCI6 59 +#define CLK_AUD_ASRCO3 60 +#define CLK_AUD_ASRCO4 61 +#define CLK_AUD_ASRCO5 62 +#define CLK_AUD_ASRCO6 63 +#define CLK_AUD_MEM_ASRC1 64 +#define CLK_AUD_MEM_ASRC2 65 +#define CLK_AUD_MEM_ASRC3 66 +#define CLK_AUD_MEM_ASRC4 67 +#define CLK_AUD_MEM_ASRC5 68 +#define CLK_AUD_DSD_ENC 69 +#define CLK_AUD_ASRC_BRG 70 +#define CLK_AUD_NR 71 /* MMSYS */ -#define CLK_MM_SMI_COMMON 0 -#define CLK_MM_SMI_LARB0 1 -#define CLK_MM_CMDQ 2 -#define CLK_MM_MUTEX 3 -#define CLK_MM_DISP_COLOR 4 -#define CLK_MM_DISP_BLS 5 -#define CLK_MM_DISP_WDMA 6 -#define CLK_MM_DISP_RDMA 7 -#define CLK_MM_DISP_OVL 8 -#define CLK_MM_MDP_TDSHP 9 -#define CLK_MM_MDP_WROT 10 -#define CLK_MM_MDP_WDMA 11 -#define CLK_MM_MDP_RSZ1 12 -#define CLK_MM_MDP_RSZ0 13 -#define CLK_MM_MDP_RDMA 14 -#define CLK_MM_MDP_BLS_26M 15 -#define CLK_MM_CAM_MDP 16 -#define CLK_MM_FAKE_ENG 17 -#define CLK_MM_MUTEX_32K 18 -#define CLK_MM_DISP_RDMA1 19 -#define CLK_MM_DISP_UFOE 20 - -#define CLK_MM_DSI_ENGINE 21 -#define CLK_MM_DSI_DIG 22 -#define CLK_MM_DPI_DIGL 23 -#define CLK_MM_DPI_ENGINE 24 -#define CLK_MM_DPI1_DIGL 25 -#define CLK_MM_DPI1_ENGINE 26 -#define CLK_MM_TVE_OUTPUT 27 -#define CLK_MM_TVE_INPUT 28 -#define CLK_MM_HDMI_PIXEL 29 -#define CLK_MM_HDMI_PLL 30 -#define CLK_MM_HDMI_AUDIO 31 -#define CLK_MM_HDMI_SPDIF 32 -#define CLK_MM_TVE_FMM 33 -#define CLK_MM_NR 34 + +#define CLK_MM_SMI_COMMON 1 +#define CLK_MM_SMI_LARB0 2 +#define CLK_MM_CMDQ 3 +#define CLK_MM_MUTEX 4 +#define CLK_MM_DISP_COLOR 5 +#define CLK_MM_DISP_BLS 6 +#define CLK_MM_DISP_WDMA 7 +#define CLK_MM_DISP_RDMA 8 +#define CLK_MM_DISP_OVL 9 +#define CLK_MM_MDP_TDSHP 10 +#define CLK_MM_MDP_WROT 11 +#define CLK_MM_MDP_WDMA 12 +#define CLK_MM_MDP_RSZ1 13 +#define CLK_MM_MDP_RSZ0 14 +#define CLK_MM_MDP_RDMA 15 +#define CLK_MM_MDP_BLS_26M 16 +#define CLK_MM_CAM_MDP 17 +#define CLK_MM_FAKE_ENG 18 +#define CLK_MM_MUTEX_32K 19 +#define CLK_MM_DISP_RDMA1 20 +#define CLK_MM_DISP_UFOE 21 + +#define CLK_MM_DSI_ENGINE 22 +#define CLK_MM_DSI_DIG 23 +#define CLK_MM_DPI_DIGL 24 +#define CLK_MM_DPI_ENGINE 25 +#define CLK_MM_DPI1_DIGL 26 +#define CLK_MM_DPI1_ENGINE 27 +#define CLK_MM_TVE_OUTPUT 28 +#define CLK_MM_TVE_INPUT 29 +#define CLK_MM_HDMI_PIXEL 30 +#define CLK_MM_HDMI_PLL 31 +#define CLK_MM_HDMI_AUDIO 32 +#define CLK_MM_HDMI_SPDIF 33 +#define CLK_MM_TVE_FMM 34 +#define CLK_MM_NR 35 /* IMGSYS */ -#define CLK_IMG_SMI_COMM 0 -#define CLK_IMG_RESZ 1 -#define CLK_IMG_JPGDEC_SMI 2 -#define CLK_IMG_JPGDEC 3 -#define CLK_IMG_VENC_LT 4 -#define CLK_IMG_VENC 5 -#define CLK_IMG_NR 6 + +#define CLK_IMG_SMI_COMM 1 +#define CLK_IMG_RESZ 2 +#define CLK_IMG_JPGDEC_SMI 3 +#define CLK_IMG_JPGDEC 4 +#define CLK_IMG_VENC_LT 5 +#define CLK_IMG_VENC 6 +#define CLK_IMG_NR 7 /* VDEC */ -#define CLK_VDEC_CKGEN 0 -#define CLK_VDEC_LARB 1 -#define CLK_VDEC_NR 2 + +#define CLK_VDEC_CKGEN 1 +#define CLK_VDEC_LARB 2 +#define CLK_VDEC_NR 3 /* HIFSYS */ -#define CLK_HIFSYS_USB0PHY 0 -#define CLK_HIFSYS_USB1PHY 1 -#define CLK_HIFSYS_PCIE0 2 -#define CLK_HIFSYS_PCIE1 3 -#define CLK_HIFSYS_PCIE2 4 -#define CLK_HIFSYS_NR 5 + +#define CLK_HIFSYS_USB0PHY 1 +#define CLK_HIFSYS_USB1PHY 2 +#define CLK_HIFSYS_PCIE0 3 +#define CLK_HIFSYS_PCIE1 4 +#define CLK_HIFSYS_PCIE2 5 +#define CLK_HIFSYS_NR 6 /* ETHSYS */ -#define CLK_ETHSYS_HSDMA 0 -#define CLK_ETHSYS_ESW 1 -#define CLK_ETHSYS_GP2 2 -#define CLK_ETHSYS_GP1 3 -#define CLK_ETHSYS_PCM 4 -#define CLK_ETHSYS_GDMA 5 -#define CLK_ETHSYS_I2S 6 -#define CLK_ETHSYS_CRYPTO 7 -#define CLK_ETHSYS_NR 8 +#define CLK_ETHSYS_HSDMA 1 +#define CLK_ETHSYS_ESW 2 +#define CLK_ETHSYS_GP2 3 +#define CLK_ETHSYS_GP1 4 +#define CLK_ETHSYS_PCM 5 +#define CLK_ETHSYS_GDMA 6 +#define CLK_ETHSYS_I2S 7 +#define CLK_ETHSYS_CRYPTO 8 +#define CLK_ETHSYS_NR 9 /* G3DSYS */ -#define CLK_G3DSYS_CORE 0 -#define CLK_G3DSYS_NR 1 +#define CLK_G3DSYS_CORE 1 +#define CLK_G3DSYS_NR 2 + +/* BDP */ + +#define CLK_BDP_BRG_BA 1 +#define CLK_BDP_BRG_DRAM 2 +#define CLK_BDP_LARB_DRAM 3 +#define CLK_BDP_WR_VDI_PXL 4 +#define CLK_BDP_WR_VDI_DRAM 5 +#define CLK_BDP_WR_B 6 +#define CLK_BDP_DGI_IN 7 +#define CLK_BDP_DGI_OUT 8 +#define CLK_BDP_FMT_MAST_27 9 +#define CLK_BDP_FMT_B 10 +#define CLK_BDP_OSD_B 11 +#define CLK_BDP_OSD_DRAM 12 +#define CLK_BDP_OSD_AGENT 13 +#define CLK_BDP_OSD_PXL 14 +#define CLK_BDP_RLE_B 15 +#define CLK_BDP_RLE_AGENT 16 +#define CLK_BDP_RLE_DRAM 17 +#define CLK_BDP_F27M 18 +#define CLK_BDP_F27M_VDOUT 19 +#define CLK_BDP_F27_74_74 20 +#define CLK_BDP_F2FS 21 +#define CLK_BDP_F2FS74_148 22 +#define CLK_BDP_FB 23 +#define CLK_BDP_VDO_DRAM 24 +#define CLK_BDP_VDO_2FS 25 +#define CLK_BDP_VDO_B 26 +#define CLK_BDP_WR_DI_PXL 27 +#define CLK_BDP_WR_DI_DRAM 28 +#define CLK_BDP_WR_DI_B 29 +#define CLK_BDP_NR_PXL 30 +#define CLK_BDP_NR_DRAM 31 +#define CLK_BDP_NR_B 32 + +#define CLK_BDP_RX_F 33 +#define CLK_BDP_RX_X 34 +#define CLK_BDP_RXPDT 35 +#define CLK_BDP_RX_CSCL_N 36 +#define CLK_BDP_RX_CSCL 37 +#define CLK_BDP_RX_DDCSCL_N 38 +#define CLK_BDP_RX_DDCSCL 39 +#define CLK_BDP_RX_VCO 40 +#define CLK_BDP_RX_DP 41 +#define CLK_BDP_RX_P 42 +#define CLK_BDP_RX_M 43 +#define CLK_BDP_RX_PLL 44 +#define CLK_BDP_BRG_RT_B 45 +#define CLK_BDP_BRG_RT_DRAM 46 +#define CLK_BDP_LARBRT_DRAM 47 +#define CLK_BDP_TMDS_SYN 48 +#define CLK_BDP_HDMI_MON 49 +#define CLK_BDP_NR 50 #endif /* _DT_BINDINGS_CLK_MT2701_H */ diff --git a/include/dt-bindings/clock/mt7981-clk.h b/include/dt-bindings/clock/mt7981-clk.h index e24c759e499..52325916015 100644 --- a/include/dt-bindings/clock/mt7981-clk.h +++ b/include/dt-bindings/clock/mt7981-clk.h @@ -8,260 +8,219 @@ #ifndef _DT_BINDINGS_CLK_MT7981_H #define _DT_BINDINGS_CLK_MT7981_H -/* INFRACFG */ - -#define CK_INFRA_CK_F26M 0 -#define CK_INFRA_UART 1 -#define CK_INFRA_ISPI0 2 -#define CK_INFRA_I2C 3 -#define CK_INFRA_ISPI1 4 -#define CK_INFRA_PWM 5 -#define CK_INFRA_66M_MCK 6 -#define CK_INFRA_CK_F32K 7 -#define CK_INFRA_PCIE_CK 8 -#define CK_INFRA_PWM_BCK 9 -#define CK_INFRA_PWM_CK1 10 -#define CK_INFRA_PWM_CK2 11 -#define CK_INFRA_133M_HCK 12 -#define CK_INFRA_66M_PHCK 13 -#define CK_INFRA_FAUD_L_CK 14 -#define CK_INFRA_FAUD_AUD_CK 15 -#define CK_INFRA_FAUD_EG2_CK 16 -#define CK_INFRA_I2CS_CK 17 -#define CK_INFRA_MUX_UART0 18 -#define CK_INFRA_MUX_UART1 19 -#define CK_INFRA_MUX_UART2 20 -#define CK_INFRA_NFI_CK 21 -#define CK_INFRA_SPINFI_CK 22 -#define CK_INFRA_MUX_SPI0 23 -#define CK_INFRA_MUX_SPI1 24 -#define CK_INFRA_MUX_SPI2 25 -#define CK_INFRA_RTC_32K 26 -#define CK_INFRA_FMSDC_CK 27 -#define CK_INFRA_FMSDC_HCK_CK 28 -#define CK_INFRA_PERI_133M 29 -#define CK_INFRA_133M_PHCK 30 -#define CK_INFRA_USB_SYS_CK 31 -#define CK_INFRA_USB_CK 32 -#define CK_INFRA_USB_XHCI_CK 33 -#define CK_INFRA_PCIE_GFMUX_TL_O_PRE 34 -#define CK_INFRA_F26M_CK0 35 -#define CK_INFRA_133M_MCK 36 -#define CLK_INFRA_NR_CLK 37 - /* TOPCKGEN */ -#define CK_TOP_CB_CKSQ_40M 0 -#define CK_TOP_CB_M_416M 1 -#define CK_TOP_CB_M_D2 2 -#define CK_TOP_CB_M_D3 3 -#define CK_TOP_M_D3_D2 4 -#define CK_TOP_CB_M_D4 5 -#define CK_TOP_CB_M_D8 6 -#define CK_TOP_M_D8_D2 7 -#define CK_TOP_CB_MM_720M 8 -#define CK_TOP_CB_MM_D2 9 -#define CK_TOP_CB_MM_D3 10 -#define CK_TOP_CB_MM_D3_D5 11 -#define CK_TOP_CB_MM_D4 12 -#define CK_TOP_CB_MM_D6 13 -#define CK_TOP_MM_D6_D2 14 -#define CK_TOP_CB_MM_D8 15 -#define CK_TOP_CB_APLL2_196M 16 -#define CK_TOP_APLL2_D2 17 -#define CK_TOP_APLL2_D4 18 -#define CK_TOP_NET1_2500M 19 -#define CK_TOP_CB_NET1_D4 20 -#define CK_TOP_CB_NET1_D5 21 -#define CK_TOP_NET1_D5_D2 22 -#define CK_TOP_NET1_D5_D4 23 -#define CK_TOP_CB_NET1_D8 24 -#define CK_TOP_NET1_D8_D2 25 -#define CK_TOP_NET1_D8_D4 26 -#define CK_TOP_CB_NET2_800M 27 -#define CK_TOP_CB_NET2_D2 28 -#define CK_TOP_CB_NET2_D4 29 -#define CK_TOP_NET2_D4_D2 30 -#define CK_TOP_NET2_D4_D4 31 -#define CK_TOP_CB_NET2_D6 32 -#define CK_TOP_CB_WEDMCU_208M 33 -#define CK_TOP_CB_SGM_325M 34 -#define CK_TOP_CKSQ_40M_D2 35 -#define CK_TOP_CB_RTC_32K 36 -#define CK_TOP_CB_RTC_32P7K 37 -#define CK_TOP_USB_TX250M 38 -#define CK_TOP_FAUD 39 -#define CK_TOP_NFI1X 40 -#define CK_TOP_USB_EQ_RX250M 41 -#define CK_TOP_USB_CDR_CK 42 -#define CK_TOP_USB_LN0_CK 43 -#define CK_TOP_SPINFI_BCK 44 -#define CK_TOP_SPI 45 -#define CK_TOP_SPIM_MST 46 -#define CK_TOP_UART_BCK 47 -#define CK_TOP_PWM_BCK 48 -#define CK_TOP_I2C_BCK 49 -#define CK_TOP_PEXTP_TL 50 -#define CK_TOP_EMMC_208M 51 -#define CK_TOP_EMMC_400M 52 -#define CK_TOP_DRAMC_REF 53 -#define CK_TOP_DRAMC_MD32 54 -#define CK_TOP_SYSAXI 55 -#define CK_TOP_SYSAPB 56 -#define CK_TOP_ARM_DB_MAIN 57 -#define CK_TOP_AP2CNN_HOST 58 -#define CK_TOP_NETSYS 59 -#define CK_TOP_NETSYS_500M 60 -#define CK_TOP_NETSYS_WED_MCU 61 -#define CK_TOP_NETSYS_2X 62 -#define CK_TOP_SGM_325M 63 -#define CK_TOP_SGM_REG 64 -#define CK_TOP_F26M 65 -#define CK_TOP_EIP97B 66 -#define CK_TOP_USB3_PHY 67 -#define CK_TOP_AUD 68 -#define CK_TOP_A1SYS 69 -#define CK_TOP_AUD_L 70 -#define CK_TOP_A_TUNER 71 -#define CK_TOP_U2U3_REF 72 -#define CK_TOP_U2U3_SYS 73 -#define CK_TOP_U2U3_XHCI 74 -#define CK_TOP_USB_FRMCNT 75 -#define CK_TOP_NFI1X_SEL 76 -#define CK_TOP_SPINFI_SEL 77 -#define CK_TOP_SPI_SEL 78 -#define CK_TOP_SPIM_MST_SEL 79 -#define CK_TOP_UART_SEL 80 -#define CK_TOP_PWM_SEL 81 -#define CK_TOP_I2C_SEL 82 -#define CK_TOP_PEXTP_TL_SEL 83 -#define CK_TOP_EMMC_208M_SEL 84 -#define CK_TOP_EMMC_400M_SEL 85 -#define CK_TOP_F26M_SEL 86 -#define CK_TOP_DRAMC_SEL 87 -#define CK_TOP_DRAMC_MD32_SEL 88 -#define CK_TOP_SYSAXI_SEL 89 -#define CK_TOP_SYSAPB_SEL 90 -#define CK_TOP_ARM_DB_MAIN_SEL 91 -#define CK_TOP_AP2CNN_HOST_SEL 92 -#define CK_TOP_NETSYS_SEL 93 -#define CK_TOP_NETSYS_500M_SEL 94 -#define CK_TOP_NETSYS_MCU_SEL 95 -#define CK_TOP_NETSYS_2X_SEL 96 -#define CK_TOP_SGM_325M_SEL 97 -#define CK_TOP_SGM_REG_SEL 98 -#define CK_TOP_EIP97B_SEL 99 -#define CK_TOP_USB3_PHY_SEL 100 -#define CK_TOP_AUD_SEL 101 -#define CK_TOP_A1SYS_SEL 102 -#define CK_TOP_AUD_L_SEL 103 -#define CK_TOP_A_TUNER_SEL 104 -#define CK_TOP_U2U3_SEL 105 -#define CK_TOP_U2U3_SYS_SEL 106 -#define CK_TOP_U2U3_XHCI_SEL 107 -#define CK_TOP_USB_FRMCNT_SEL 108 -#define CLK_TOP_NR_CLK 109 +#define CLK_TOP_CB_CKSQ_40M 0 +#define CLK_TOP_CB_M_416M 1 +#define CLK_TOP_CB_M_D2 2 +#define CLK_TOP_CB_M_D3 3 +#define CLK_TOP_M_D3_D2 4 +#define CLK_TOP_CB_M_D4 5 +#define CLK_TOP_CB_M_D8 6 +#define CLK_TOP_M_D8_D2 7 +#define CLK_TOP_CB_MM_720M 8 +#define CLK_TOP_CB_MM_D2 9 +#define CLK_TOP_CB_MM_D3 10 +#define CLK_TOP_CB_MM_D3_D5 11 +#define CLK_TOP_CB_MM_D4 12 +#define CLK_TOP_CB_MM_D6 13 +#define CLK_TOP_MM_D6_D2 14 +#define CLK_TOP_CB_MM_D8 15 +#define CLK_TOP_CB_APLL2_196M 16 +#define CLK_TOP_APLL2_D2 17 +#define CLK_TOP_APLL2_D4 18 +#define CLK_TOP_NET1_2500M 19 +#define CLK_TOP_CB_NET1_D4 20 +#define CLK_TOP_CB_NET1_D5 21 +#define CLK_TOP_NET1_D5_D2 22 +#define CLK_TOP_NET1_D5_D4 23 +#define CLK_TOP_CB_NET1_D8 24 +#define CLK_TOP_NET1_D8_D2 25 +#define CLK_TOP_NET1_D8_D4 26 +#define CLK_TOP_CB_NET2_800M 27 +#define CLK_TOP_CB_NET2_D2 28 +#define CLK_TOP_CB_NET2_D4 29 +#define CLK_TOP_NET2_D4_D2 30 +#define CLK_TOP_NET2_D4_D4 31 +#define CLK_TOP_CB_NET2_D6 32 +#define CLK_TOP_CB_WEDMCU_208M 33 +#define CLK_TOP_CB_SGM_325M 34 +#define CLK_TOP_CKSQ_40M_D2 35 +#define CLK_TOP_CB_RTC_32K 36 +#define CLK_TOP_CB_RTC_32P7K 37 +#define CLK_TOP_USB_TX250M 38 +#define CLK_TOP_FAUD 39 +#define CLK_TOP_NFI1X 40 +#define CLK_TOP_USB_EQ_RX250M 41 +#define CLK_TOP_USB_CDR_CK 42 +#define CLK_TOP_USB_LN0_CK 43 +#define CLK_TOP_SPINFI_BCK 44 +#define CLK_TOP_SPI 45 +#define CLK_TOP_SPIM_MST 46 +#define CLK_TOP_UART_BCK 47 +#define CLK_TOP_PWM_BCK 48 +#define CLK_TOP_I2C_BCK 49 +#define CLK_TOP_PEXTP_TL 50 +#define CLK_TOP_EMMC_208M 51 +#define CLK_TOP_EMMC_400M 52 +#define CLK_TOP_DRAMC_REF 53 +#define CLK_TOP_DRAMC_MD32 54 +#define CLK_TOP_SYSAXI 55 +#define CLK_TOP_SYSAPB 56 +#define CLK_TOP_ARM_DB_MAIN 57 +#define CLK_TOP_AP2CNN_HOST 58 +#define CLK_TOP_NETSYS 59 +#define CLK_TOP_NETSYS_500M 60 +#define CLK_TOP_NETSYS_WED_MCU 61 +#define CLK_TOP_NETSYS_2X 62 +#define CLK_TOP_SGM_325M 63 +#define CLK_TOP_SGM_REG 64 +#define CLK_TOP_F26M 65 +#define CLK_TOP_EIP97B 66 +#define CLK_TOP_USB3_PHY 67 +#define CLK_TOP_AUD 68 +#define CLK_TOP_A1SYS 69 +#define CLK_TOP_AUD_L 70 +#define CLK_TOP_A_TUNER 71 +#define CLK_TOP_U2U3_REF 72 +#define CLK_TOP_U2U3_SYS 73 +#define CLK_TOP_U2U3_XHCI 74 +#define CLK_TOP_USB_FRMCNT 75 +#define CLK_TOP_NFI1X_SEL 76 +#define CLK_TOP_SPINFI_SEL 77 +#define CLK_TOP_SPI_SEL 78 +#define CLK_TOP_SPIM_MST_SEL 79 +#define CLK_TOP_UART_SEL 80 +#define CLK_TOP_PWM_SEL 81 +#define CLK_TOP_I2C_SEL 82 +#define CLK_TOP_PEXTP_TL_SEL 83 +#define CLK_TOP_EMMC_208M_SEL 84 +#define CLK_TOP_EMMC_400M_SEL 85 +#define CLK_TOP_F26M_SEL 86 +#define CLK_TOP_DRAMC_SEL 87 +#define CLK_TOP_DRAMC_MD32_SEL 88 +#define CLK_TOP_SYSAXI_SEL 89 +#define CLK_TOP_SYSAPB_SEL 90 +#define CLK_TOP_ARM_DB_MAIN_SEL 91 +#define CLK_TOP_AP2CNN_HOST_SEL 92 +#define CLK_TOP_NETSYS_SEL 93 +#define CLK_TOP_NETSYS_500M_SEL 94 +#define CLK_TOP_NETSYS_MCU_SEL 95 +#define CLK_TOP_NETSYS_2X_SEL 96 +#define CLK_TOP_SGM_325M_SEL 97 +#define CLK_TOP_SGM_REG_SEL 98 +#define CLK_TOP_EIP97B_SEL 99 +#define CLK_TOP_USB3_PHY_SEL 100 +#define CLK_TOP_AUD_SEL 101 +#define CLK_TOP_A1SYS_SEL 102 +#define CLK_TOP_AUD_L_SEL 103 +#define CLK_TOP_A_TUNER_SEL 104 +#define CLK_TOP_U2U3_SEL 105 +#define CLK_TOP_U2U3_SYS_SEL 106 +#define CLK_TOP_U2U3_XHCI_SEL 107 +#define CLK_TOP_USB_FRMCNT_SEL 108 +#define CLK_TOP_AUD_I2S_M 109 +#define CLK_TOP_NR_CLK 110 -/* - * INFRACFG_AO - * clock muxes need to be append to infracfg domain, and clock gates - * need to be keep in infracgh_ao domain - */ -#define INFRACFG_AO_OFFSET 10 +/* INFRACFG */ -#define CK_INFRA_UART0_SEL (0 + CLK_INFRA_NR_CLK) -#define CK_INFRA_UART1_SEL (1 + CLK_INFRA_NR_CLK) -#define CK_INFRA_UART2_SEL (2 + CLK_INFRA_NR_CLK) -#define CK_INFRA_SPI0_SEL (3 + CLK_INFRA_NR_CLK) -#define CK_INFRA_SPI1_SEL (4 + CLK_INFRA_NR_CLK) -#define CK_INFRA_SPI2_SEL (5 + CLK_INFRA_NR_CLK) -#define CK_INFRA_PWM1_SEL (6 + CLK_INFRA_NR_CLK) -#define CK_INFRA_PWM2_SEL (7 + CLK_INFRA_NR_CLK) -#define CK_INFRA_PWM_BSEL (8 + CLK_INFRA_NR_CLK) -#define CK_INFRA_PCIE_SEL (9 + CLK_INFRA_NR_CLK) -#define CK_INFRA_GPT_STA (10 - INFRACFG_AO_OFFSET) -#define CK_INFRA_PWM_HCK (11 - INFRACFG_AO_OFFSET) -#define CK_INFRA_PWM_STA (12 - INFRACFG_AO_OFFSET) -#define CK_INFRA_PWM1_CK (13 - INFRACFG_AO_OFFSET) -#define CK_INFRA_PWM2_CK (14 - INFRACFG_AO_OFFSET) -#define CK_INFRA_CQ_DMA_CK (15 - INFRACFG_AO_OFFSET) -#define CK_INFRA_AUD_BUS_CK (16 - INFRACFG_AO_OFFSET) -#define CK_INFRA_AUD_26M_CK (17 - INFRACFG_AO_OFFSET) -#define CK_INFRA_AUD_L_CK (18 - INFRACFG_AO_OFFSET) -#define CK_INFRA_AUD_AUD_CK (19 - INFRACFG_AO_OFFSET) -#define CK_INFRA_AUD_EG2_CK (20 - INFRACFG_AO_OFFSET) -#define CK_INFRA_DRAMC_26M_CK (21 - INFRACFG_AO_OFFSET) -#define CK_INFRA_DBG_CK (22 - INFRACFG_AO_OFFSET) -#define CK_INFRA_AP_DMA_CK (23 - INFRACFG_AO_OFFSET) -#define CK_INFRA_SEJ_CK (24 - INFRACFG_AO_OFFSET) -#define CK_INFRA_SEJ_13M_CK (25 - INFRACFG_AO_OFFSET) -#define CK_INFRA_THERM_CK (26 - INFRACFG_AO_OFFSET) -#define CK_INFRA_I2CO_CK (27 - INFRACFG_AO_OFFSET) -#define CK_INFRA_UART0_CK (28 - INFRACFG_AO_OFFSET) -#define CK_INFRA_UART1_CK (29 - INFRACFG_AO_OFFSET) -#define CK_INFRA_UART2_CK (30 - INFRACFG_AO_OFFSET) -#define CK_INFRA_SPI2_CK (31 - INFRACFG_AO_OFFSET) -#define CK_INFRA_SPI2_HCK_CK (32 - INFRACFG_AO_OFFSET) -#define CK_INFRA_NFI1_CK (33 - INFRACFG_AO_OFFSET) -#define CK_INFRA_SPINFI1_CK (34 - INFRACFG_AO_OFFSET) -#define CK_INFRA_NFI_HCK_CK (35 - INFRACFG_AO_OFFSET) -#define CK_INFRA_SPI0_CK (36 - INFRACFG_AO_OFFSET) -#define CK_INFRA_SPI1_CK (37 - INFRACFG_AO_OFFSET) -#define CK_INFRA_SPI0_HCK_CK (38 - INFRACFG_AO_OFFSET) -#define CK_INFRA_SPI1_HCK_CK (39 - INFRACFG_AO_OFFSET) -#define CK_INFRA_FRTC_CK (40 - INFRACFG_AO_OFFSET) -#define CK_INFRA_MSDC_CK (41 - INFRACFG_AO_OFFSET) -#define CK_INFRA_MSDC_HCK_CK (42 - INFRACFG_AO_OFFSET) -#define CK_INFRA_MSDC_133M_CK (43 - INFRACFG_AO_OFFSET) -#define CK_INFRA_MSDC_66M_CK (44 - INFRACFG_AO_OFFSET) -#define CK_INFRA_ADC_26M_CK (45 - INFRACFG_AO_OFFSET) -#define CK_INFRA_ADC_FRC_CK (46 - INFRACFG_AO_OFFSET) -#define CK_INFRA_FBIST2FPC_CK (47 - INFRACFG_AO_OFFSET) -#define CK_INFRA_I2C_MCK_CK (48 - INFRACFG_AO_OFFSET) -#define CK_INFRA_I2C_PCK_CK (49 - INFRACFG_AO_OFFSET) -#define CK_INFRA_IUSB_133_CK (50 - INFRACFG_AO_OFFSET) -#define CK_INFRA_IUSB_66M_CK (51 - INFRACFG_AO_OFFSET) -#define CK_INFRA_IUSB_SYS_CK (52 - INFRACFG_AO_OFFSET) -#define CK_INFRA_IUSB_CK (53 - INFRACFG_AO_OFFSET) -#define CK_INFRA_IPCIE_CK (54 - INFRACFG_AO_OFFSET) -#define CK_INFRA_IPCIER_CK (55 - INFRACFG_AO_OFFSET) -#define CK_INFRA_IPCIEB_CK (56 - INFRACFG_AO_OFFSET) -#define CLK_INFRA_AO_NR_CLK (57 - INFRACFG_AO_OFFSET) +#define CLK_INFRA_66M_MCK 0 +#define CLK_INFRA_UART0_SEL 1 +#define CLK_INFRA_UART1_SEL 2 +#define CLK_INFRA_UART2_SEL 3 +#define CLK_INFRA_SPI0_SEL 4 +#define CLK_INFRA_SPI1_SEL 5 +#define CLK_INFRA_SPI2_SEL 6 +#define CLK_INFRA_PWM1_SEL 7 +#define CLK_INFRA_PWM2_SEL 8 +#define CLK_INFRA_PWM3_SEL 9 +#define CLK_INFRA_PWM_BSEL 10 +#define CLK_INFRA_PCIE_SEL 11 +#define CLK_INFRA_GPT_STA 12 +#define CLK_INFRA_PWM_HCK 13 +#define CLK_INFRA_PWM_STA 14 +#define CLK_INFRA_PWM1_CK 15 +#define CLK_INFRA_PWM2_CK 16 +#define CLK_INFRA_PWM3_CK 17 +#define CLK_INFRA_CQ_DMA_CK 18 +#define CLK_INFRA_AUD_BUS_CK 19 +#define CLK_INFRA_AUD_26M_CK 20 +#define CLK_INFRA_AUD_L_CK 21 +#define CLK_INFRA_AUD_AUD_CK 22 +#define CLK_INFRA_AUD_EG2_CK 23 +#define CLK_INFRA_DRAMC_26M_CK 24 +#define CLK_INFRA_DBG_CK 25 +#define CLK_INFRA_AP_DMA_CK 26 +#define CLK_INFRA_SEJ_CK 27 +#define CLK_INFRA_SEJ_13M_CK 28 +#define CLK_INFRA_THERM_CK 29 +#define CLK_INFRA_I2C0_CK 30 +#define CLK_INFRA_UART0_CK 31 +#define CLK_INFRA_UART1_CK 32 +#define CLK_INFRA_UART2_CK 33 +#define CLK_INFRA_SPI2_CK 34 +#define CLK_INFRA_SPI2_HCK_CK 35 +#define CLK_INFRA_NFI1_CK 36 +#define CLK_INFRA_SPINFI1_CK 37 +#define CLK_INFRA_NFI_HCK_CK 38 +#define CLK_INFRA_SPI0_CK 39 +#define CLK_INFRA_SPI1_CK 40 +#define CLK_INFRA_SPI0_HCK_CK 41 +#define CLK_INFRA_SPI1_HCK_CK 42 +#define CLK_INFRA_FRTC_CK 43 +#define CLK_INFRA_MSDC_CK 44 +#define CLK_INFRA_MSDC_HCK_CK 45 +#define CLK_INFRA_MSDC_133M_CK 46 +#define CLK_INFRA_MSDC_66M_CK 47 +#define CLK_INFRA_ADC_26M_CK 48 +#define CLK_INFRA_ADC_FRC_CK 49 +#define CLK_INFRA_FBIST2FPC_CK 50 +#define CLK_INFRA_I2C_MCK_CK 51 +#define CLK_INFRA_I2C_PCK_CK 52 +#define CLK_INFRA_IUSB_133_CK 53 +#define CLK_INFRA_IUSB_66M_CK 54 +#define CLK_INFRA_IUSB_SYS_CK 55 +#define CLK_INFRA_IUSB_CK 56 +#define CLK_INFRA_IPCIE_CK 57 +#define CLK_INFRA_IPCIE_PIPE_CK 58 +#define CLK_INFRA_IPCIER_CK 59 +#define CLK_INFRA_IPCIEB_CK 60 +#define CLK_INFRA_NR_CLK 61 /* APMIXEDSYS */ -#define CK_APMIXED_ARMPLL 0 -#define CK_APMIXED_NET2PLL 1 -#define CK_APMIXED_MMPLL 2 -#define CK_APMIXED_SGMPLL 3 -#define CK_APMIXED_WEDMCUPLL 4 -#define CK_APMIXED_NET1PLL 5 -#define CK_APMIXED_MPLL 6 -#define CK_APMIXED_APLL2 7 +#define CLK_APMIXED_ARMPLL 0 +#define CLK_APMIXED_NET2PLL 1 +#define CLK_APMIXED_MMPLL 2 +#define CLK_APMIXED_SGMPLL 3 +#define CLK_APMIXED_WEDMCUPLL 4 +#define CLK_APMIXED_NET1PLL 5 +#define CLK_APMIXED_MPLL 6 +#define CLK_APMIXED_APLL2 7 #define CLK_APMIXED_NR_CLK 8 /* SGMIISYS_0 */ -#define CK_SGM0_TX_EN 0 -#define CK_SGM0_RX_EN 1 -#define CK_SGM0_CK0_EN 2 -#define CK_SGM0_CDR_CK0_EN 3 +#define CLK_SGM0_TX_EN 0 +#define CLK_SGM0_RX_EN 1 +#define CLK_SGM0_CK0_EN 2 +#define CLK_SGM0_CDR_CK0_EN 3 #define CLK_SGMII0_NR_CLK 4 /* SGMIISYS_1 */ -#define CK_SGM1_TX_EN 0 -#define CK_SGM1_RX_EN 1 -#define CK_SGM1_CK1_EN 2 -#define CK_SGM1_CDR_CK1_EN 3 +#define CLK_SGM1_TX_EN 0 +#define CLK_SGM1_RX_EN 1 +#define CLK_SGM1_CK1_EN 2 +#define CLK_SGM1_CDR_CK1_EN 3 #define CLK_SGMII1_NR_CLK 4 /* ETHSYS */ -#define CK_ETH_FE_EN 0 -#define CK_ETH_GP2_EN 1 -#define CK_ETH_GP1_EN 2 -#define CK_ETH_WOCPU0_EN 3 +#define CLK_ETH_FE_EN 0 +#define CLK_ETH_GP2_EN 1 +#define CLK_ETH_GP1_EN 2 +#define CLK_ETH_WOCPU0_EN 3 #define CLK_ETH_NR_CLK 4 #endif /* _DT_BINDINGS_CLK_MT7981_H */ diff --git a/include/dt-bindings/clock/mt7986-clk.h b/include/dt-bindings/clock/mt7986-clk.h index 820f8631831..5da260386fd 100644 --- a/include/dt-bindings/clock/mt7986-clk.h +++ b/include/dt-bindings/clock/mt7986-clk.h @@ -8,240 +8,169 @@ #ifndef _DT_BINDINGS_CLK_MT7986_H #define _DT_BINDINGS_CLK_MT7986_H -/* INFRACFG */ - -#define CK_INFRA_CK_F26M 0 -#define CK_INFRA_UART 1 -#define CK_INFRA_ISPI0 2 -#define CK_INFRA_I2C 3 -#define CK_INFRA_ISPI1 4 -#define CK_INFRA_PWM 5 -#define CK_INFRA_66M_MCK 6 -#define CK_INFRA_CK_F32K 7 -#define CK_INFRA_PCIE_CK 8 -#define CK_INFRA_PWM_BCK 9 -#define CK_INFRA_PWM_CK1 10 -#define CK_INFRA_PWM_CK2 11 -#define CK_INFRA_133M_HCK 12 -#define CK_INFRA_EIP_CK 13 -#define CK_INFRA_66M_PHCK 14 -#define CK_INFRA_FAUD_L_CK 15 -#define CK_INFRA_FAUD_AUD_CK 17 -#define CK_INFRA_FAUD_EG2_CK 17 -#define CK_INFRA_I2CS_CK 18 -#define CK_INFRA_MUX_UART0 19 -#define CK_INFRA_MUX_UART1 20 -#define CK_INFRA_MUX_UART2 21 -#define CK_INFRA_NFI_CK 22 -#define CK_INFRA_SPINFI_CK 23 -#define CK_INFRA_MUX_SPI0 24 -#define CK_INFRA_MUX_SPI1 25 -#define CK_INFRA_RTC_32K 26 -#define CK_INFRA_FMSDC_CK 27 -#define CK_INFRA_FMSDC_HCK_CK 28 -#define CK_INFRA_PERI_133M 29 -#define CK_INFRA_133M_PHCK 30 -#define CK_INFRA_USB_SYS_CK 31 -#define CK_INFRA_USB_CK 32 -#define CK_INFRA_USB_XHCI_CK 33 -#define CK_INFRA_PCIE_GFMUX_TL_O_PRE 34 -#define CK_INFRA_F26M_CK0 35 -#define CK_INFRA_HD_133M 36 -#define CLK_INFRA_NR_CLK 37 - /* TOPCKGEN */ -#define CK_TOP_CB_CKSQ_40M 0 -#define CK_TOP_CB_M_416M 1 -#define CK_TOP_CB_M_D2 2 -#define CK_TOP_CB_M_D4 3 -#define CK_TOP_CB_M_D8 4 -#define CK_TOP_M_D8_D2 5 -#define CK_TOP_M_D3_D2 6 -#define CK_TOP_CB_MM_D2 7 -#define CK_TOP_CB_MM_D4 8 -#define CK_TOP_CB_MM_D8 9 -#define CK_TOP_MM_D8_D2 10 -#define CK_TOP_MM_D3_D8 11 -#define CK_TOP_CB_U2_PHYD_CK 12 -#define CK_TOP_CB_APLL2_196M 13 -#define CK_TOP_APLL2_D4 14 -#define CK_TOP_CB_NET1_D4 15 -#define CK_TOP_CB_NET1_D5 16 -#define CK_TOP_NET1_D5_D2 17 -#define CK_TOP_NET1_D5_D4 18 -#define CK_TOP_NET1_D8_D2 19 -#define CK_TOP_NET1_D8_D4 20 -#define CK_TOP_CB_NET2_800M 21 -#define CK_TOP_CB_NET2_D4 22 -#define CK_TOP_NET2_D4_D2 23 -#define CK_TOP_NET2_D3_D2 24 -#define CK_TOP_CB_WEDMCU_760M 25 -#define CK_TOP_WEDMCU_D5_D2 26 -#define CK_TOP_CB_SGM_325M 27 -#define CK_TOP_CB_CKSQ_40M_D2 28 -#define CK_TOP_CB_RTC_32K 29 -#define CK_TOP_CB_RTC_32P7K 30 -#define CK_TOP_NFI1X 31 -#define CK_TOP_USB_EQ_RX250M 32 -#define CK_TOP_USB_TX250M 33 -#define CK_TOP_USB_LN0_CK 34 -#define CK_TOP_USB_CDR_CK 35 -#define CK_TOP_SPINFI_BCK 36 -#define CK_TOP_I2C_BCK 37 -#define CK_TOP_PEXTP_TL 38 -#define CK_TOP_EMMC_250M 39 -#define CK_TOP_EMMC_416M 40 -#define CK_TOP_F_26M_ADC_CK 41 -#define CK_TOP_SYSAXI 42 -#define CK_TOP_NETSYS_WED_MCU 43 -#define CK_TOP_NETSYS_2X 44 -#define CK_TOP_SGM_325M 45 -#define CK_TOP_A1SYS 46 -#define CK_TOP_EIP_B 47 -#define CK_TOP_F26M 48 -#define CK_TOP_AUD_L 49 -#define CK_TOP_A_TUNER 50 -#define CK_TOP_U2U3_REF 51 -#define CK_TOP_U2U3_SYS 52 -#define CK_TOP_U2U3_XHCI 53 -#define CK_TOP_AP2CNN_HOST 54 -#define CK_TOP_NFI1X_SEL 55 -#define CK_TOP_SPINFI_SEL 56 -#define CK_TOP_SPI_SEL 57 -#define CK_TOP_SPIM_MST_SEL 58 -#define CK_TOP_UART_SEL 59 -#define CK_TOP_PWM_SEL 60 -#define CK_TOP_I2C_SEL 61 -#define CK_TOP_PEXTP_TL_SEL 62 -#define CK_TOP_EMMC_250M_SEL 63 -#define CK_TOP_EMMC_416M_SEL 64 -#define CK_TOP_F_26M_ADC_SEL 65 -#define CK_TOP_DRAMC_SEL 66 -#define CK_TOP_DRAMC_MD32_SEL 67 -#define CK_TOP_SYSAXI_SEL 68 -#define CK_TOP_SYSAPB_SEL 69 -#define CK_TOP_ARM_DB_MAIN_SEL 70 -#define CK_TOP_ARM_DB_JTSEL 71 -#define CK_TOP_NETSYS_SEL 72 -#define CK_TOP_NETSYS_500M_SEL 73 -#define CK_TOP_NETSYS_MCU_SEL 74 -#define CK_TOP_NETSYS_2X_SEL 75 -#define CK_TOP_SGM_325M_SEL 76 -#define CK_TOP_SGM_REG_SEL 77 -#define CK_TOP_A1SYS_SEL 78 -#define CK_TOP_CONN_MCUSYS_SEL 79 -#define CK_TOP_EIP_B_SEL 80 -#define CK_TOP_PCIE_PHY_SEL 81 -#define CK_TOP_USB3_PHY_SEL 82 -#define CK_TOP_F26M_SEL 83 -#define CK_TOP_AUD_L_SEL 84 -#define CK_TOP_A_TUNER_SEL 85 -#define CK_TOP_U2U3_SEL 86 -#define CK_TOP_U2U3_SYS_SEL 87 -#define CK_TOP_U2U3_XHCI_SEL 88 -#define CK_TOP_DA_U2_REFSEL 89 -#define CK_TOP_DA_U2_CK_1P_SEL 90 -#define CK_TOP_AP2CNN_HOST_SEL 91 -#define CLK_TOP_NR_CLK 92 +#define CLK_TOP_XTAL 0 +#define CLK_TOP_XTAL_D2 1 +#define CLK_TOP_RTC_32K 2 +#define CLK_TOP_RTC_32P7K 3 +/* #define CLK_TOP_A_TUNER 4 */ +#define CLK_TOP_MPLL_D2 4 +#define CLK_TOP_MPLL_D4 5 +#define CLK_TOP_MPLL_D8 6 +#define CLK_TOP_MPLL_D8_D2 7 +#define CLK_TOP_MPLL_D3_D2 8 +#define CLK_TOP_MMPLL_D2 9 +#define CLK_TOP_MMPLL_D4 10 +#define CLK_TOP_MMPLL_D8 11 +#define CLK_TOP_MMPLL_D8_D2 12 +#define CLK_TOP_MMPLL_D3_D8 13 +#define CLK_TOP_MMPLL_U2PHYD 14 +#define CLK_TOP_APLL2_D4 15 +#define CLK_TOP_NET1PLL_D4 16 +#define CLK_TOP_NET1PLL_D5 17 +#define CLK_TOP_NET1PLL_D5_D2 18 +#define CLK_TOP_NET1PLL_D5_D4 19 +#define CLK_TOP_NET1PLL_D8_D2 20 +#define CLK_TOP_NET1PLL_D8_D4 21 +#define CLK_TOP_NET2PLL_D4 22 +#define CLK_TOP_NET2PLL_D4_D2 23 +#define CLK_TOP_NET2PLL_D3_D2 24 +#define CLK_TOP_WEDMCUPLL_D5_D2 25 +#define CLK_TOP_NFI1X_SEL 26 +#define CLK_TOP_SPINFI_SEL 27 +#define CLK_TOP_SPI_SEL 28 +#define CLK_TOP_SPIM_MST_SEL 29 +#define CLK_TOP_UART_SEL 30 +#define CLK_TOP_PWM_SEL 31 +#define CLK_TOP_I2C_SEL 32 +#define CLK_TOP_PEXTP_TL_SEL 33 +#define CLK_TOP_EMMC_250M_SEL 34 +#define CLK_TOP_EMMC_416M_SEL 35 +#define CLK_TOP_F_26M_ADC_SEL 36 +#define CLK_TOP_DRAMC_SEL 37 +#define CLK_TOP_DRAMC_MD32_SEL 38 +#define CLK_TOP_SYSAXI_SEL 39 +#define CLK_TOP_SYSAPB_SEL 40 +#define CLK_TOP_ARM_DB_MAIN_SEL 41 +#define CLK_TOP_ARM_DB_JTSEL 42 +#define CLK_TOP_NETSYS_SEL 43 +#define CLK_TOP_NETSYS_500M_SEL 44 +#define CLK_TOP_NETSYS_MCU_SEL 45 +#define CLK_TOP_NETSYS_2X_SEL 46 +#define CLK_TOP_SGM_325M_SEL 47 +#define CLK_TOP_SGM_REG_SEL 48 +#define CLK_TOP_A1SYS_SEL 49 +#define CLK_TOP_CONN_MCUSYS_SEL 50 +#define CLK_TOP_EIP_B_SEL 51 +#define CLK_TOP_PCIE_PHY_SEL 52 +#define CLK_TOP_USB3_PHY_SEL 53 +#define CLK_TOP_F26M_SEL 54 +#define CLK_TOP_AUD_L_SEL 55 +#define CLK_TOP_A_TUNER_SEL 56 +#define CLK_TOP_U2U3_SEL 57 +#define CLK_TOP_U2U3_SYS_SEL 58 +#define CLK_TOP_U2U3_XHCI_SEL 59 +#define CLK_TOP_DA_U2_REFSEL 60 +#define CLK_TOP_DA_U2_CK_1P_SEL 61 +#define CLK_TOP_AP2CNN_HOST_SEL 62 +#define CLK_TOP_NR_CLK 63 -/* - * INFRACFG_AO - * clock muxes need to be append to infracfg domain, and clock gates - * need to be keep in infracgh_ao domain - */ +/* INFRACFG */ -#define CK_INFRA_UART0_SEL (0 + CLK_INFRA_NR_CLK) -#define CK_INFRA_UART1_SEL (1 + CLK_INFRA_NR_CLK) -#define CK_INFRA_UART2_SEL (2 + CLK_INFRA_NR_CLK) -#define CK_INFRA_SPI0_SEL (3 + CLK_INFRA_NR_CLK) -#define CK_INFRA_SPI1_SEL (4 + CLK_INFRA_NR_CLK) -#define CK_INFRA_PWM1_SEL (5 + CLK_INFRA_NR_CLK) -#define CK_INFRA_PWM2_SEL (6 + CLK_INFRA_NR_CLK) -#define CK_INFRA_PWM_BSEL (7 + CLK_INFRA_NR_CLK) -#define CK_INFRA_PCIE_SEL (8 + CLK_INFRA_NR_CLK) -#define CK_INFRA_GPT_STA 0 -#define CK_INFRA_PWM_HCK 1 -#define CK_INFRA_PWM_STA 2 -#define CK_INFRA_PWM1_CK 3 -#define CK_INFRA_PWM2_CK 4 -#define CK_INFRA_CQ_DMA_CK 5 -#define CK_INFRA_EIP97_CK 6 -#define CK_INFRA_AUD_BUS_CK 7 -#define CK_INFRA_AUD_26M_CK 8 -#define CK_INFRA_AUD_L_CK 9 -#define CK_INFRA_AUD_AUD_CK 10 -#define CK_INFRA_AUD_EG2_CK 11 -#define CK_INFRA_DRAMC_26M_CK 12 -#define CK_INFRA_DBG_CK 13 -#define CK_INFRA_AP_DMA_CK 14 -#define CK_INFRA_SEJ_CK 15 -#define CK_INFRA_SEJ_13M_CK 16 -#define CK_INFRA_THERM_CK 17 -#define CK_INFRA_I2CO_CK 18 -#define CK_INFRA_TRNG_CK 19 -#define CK_INFRA_UART0_CK 20 -#define CK_INFRA_UART1_CK 21 -#define CK_INFRA_UART2_CK 22 -#define CK_INFRA_NFI1_CK 23 -#define CK_INFRA_SPINFI1_CK 24 -#define CK_INFRA_NFI_HCK_CK 25 -#define CK_INFRA_SPI0_CK 26 -#define CK_INFRA_SPI1_CK 27 -#define CK_INFRA_SPI0_HCK_CK 28 -#define CK_INFRA_SPI1_HCK_CK 29 -#define CK_INFRA_FRTC_CK 30 -#define CK_INFRA_MSDC_CK 31 -#define CK_INFRA_MSDC_HCK_CK 32 -#define CK_INFRA_MSDC_133M_CK 33 -#define CK_INFRA_MSDC_66M_CK 34 -#define CK_INFRA_ADC_26M_CK 35 -#define CK_INFRA_ADC_FRC_CK 36 -#define CK_INFRA_FBIST2FPC_CK 37 -#define CK_INFRA_IUSB_133_CK 38 -#define CK_INFRA_IUSB_66M_CK 39 -#define CK_INFRA_IUSB_SYS_CK 40 -#define CK_INFRA_IUSB_CK 41 -#define CK_INFRA_IPCIE_CK 42 -#define CK_INFRA_IPCIER_CK 43 -#define CK_INFRA_IPCIEB_CK 44 -#define CLK_INFRA_AO_NR_CLK 45 +#define CLK_INFRA_SYSAXI_D2 0 +#define CLK_INFRA_UART0_SEL 1 +#define CLK_INFRA_UART1_SEL 2 +#define CLK_INFRA_UART2_SEL 3 +#define CLK_INFRA_SPI0_SEL 4 +#define CLK_INFRA_SPI1_SEL 5 +#define CLK_INFRA_PWM1_SEL 6 +#define CLK_INFRA_PWM2_SEL 7 +#define CLK_INFRA_PWM_BSEL 8 +#define CLK_INFRA_PCIE_SEL 9 +#define CLK_INFRA_GPT_STA 10 +#define CLK_INFRA_PWM_HCK 11 +#define CLK_INFRA_PWM_STA 12 +#define CLK_INFRA_PWM1_CK 13 +#define CLK_INFRA_PWM2_CK 14 +#define CLK_INFRA_CQ_DMA_CK 15 +#define CLK_INFRA_EIP97_CK 16 +#define CLK_INFRA_AUD_BUS_CK 17 +#define CLK_INFRA_AUD_26M_CK 18 +#define CLK_INFRA_AUD_L_CK 19 +#define CLK_INFRA_AUD_AUD_CK 20 +#define CLK_INFRA_AUD_EG2_CK 21 +#define CLK_INFRA_DRAMC_26M_CK 22 +#define CLK_INFRA_DBG_CK 23 +#define CLK_INFRA_AP_DMA_CK 24 +#define CLK_INFRA_SEJ_CK 25 +#define CLK_INFRA_SEJ_13M_CK 26 +#define CLK_INFRA_THERM_CK 27 +#define CLK_INFRA_I2C0_CK 28 +#define CLK_INFRA_UART0_CK 29 +#define CLK_INFRA_UART1_CK 30 +#define CLK_INFRA_UART2_CK 31 +#define CLK_INFRA_NFI1_CK 32 +#define CLK_INFRA_SPINFI1_CK 33 +#define CLK_INFRA_NFI_HCK_CK 34 +#define CLK_INFRA_SPI0_CK 35 +#define CLK_INFRA_SPI1_CK 36 +#define CLK_INFRA_SPI0_HCK_CK 37 +#define CLK_INFRA_SPI1_HCK_CK 38 +#define CLK_INFRA_FRTC_CK 39 +#define CLK_INFRA_MSDC_CK 40 +#define CLK_INFRA_MSDC_HCK_CK 41 +#define CLK_INFRA_MSDC_133M_CK 42 +#define CLK_INFRA_MSDC_66M_CK 43 +#define CLK_INFRA_ADC_26M_CK 44 +#define CLK_INFRA_ADC_FRC_CK 45 +#define CLK_INFRA_FBIST2FPC_CK 46 +#define CLK_INFRA_IUSB_133_CK 47 +#define CLK_INFRA_IUSB_66M_CK 48 +#define CLK_INFRA_IUSB_SYS_CK 49 +#define CLK_INFRA_IUSB_CK 50 +#define CLK_INFRA_IPCIE_CK 51 +#define CLK_INFRA_IPCIE_PIPE_CK 52 +#define CLK_INFRA_IPCIER_CK 53 +#define CLK_INFRA_IPCIEB_CK 54 +#define CLK_INFRA_TRNG_CK 55 +#define CLK_INFRA_AO_NR_CLK 46 /* APMIXEDSYS */ -#define CK_APMIXED_ARMPLL 0 -#define CK_APMIXED_NET2PLL 1 -#define CK_APMIXED_MMPLL 2 -#define CK_APMIXED_SGMPLL 3 -#define CK_APMIXED_WEDMCUPLL 4 -#define CK_APMIXED_NET1PLL 5 -#define CK_APMIXED_MPLL 6 -#define CK_APMIXED_APLL2 7 +#define CLK_APMIXED_ARMPLL 0 +#define CLK_APMIXED_NET2PLL 1 +#define CLK_APMIXED_MMPLL 2 +#define CLK_APMIXED_SGMPLL 3 +#define CLK_APMIXED_WEDMCUPLL 4 +#define CLK_APMIXED_NET1PLL 5 +#define CLK_APMIXED_MPLL 6 +#define CLK_APMIXED_APLL2 7 #define CLK_APMIXED_NR_CLK 8 /* SGMIISYS_0 */ -#define CK_SGM0_TX_EN 0 -#define CK_SGM0_RX_EN 1 -#define CK_SGM0_CK0_EN 2 -#define CK_SGM0_CDR_CK0_EN 3 +#define CLK_SGM0_TX_EN 0 +#define CLK_SGM0_RX_EN 1 +#define CLK_SGM0_CK0_EN 2 +#define CLK_SGM0_CDR_CK0_EN 3 #define CLK_SGMII0_NR_CLK 4 /* SGMIISYS_1 */ -#define CK_SGM1_TX_EN 0 -#define CK_SGM1_RX_EN 1 -#define CK_SGM1_CK1_EN 2 -#define CK_SGM1_CDR_CK1_EN 3 +#define CLK_SGM1_TX_EN 0 +#define CLK_SGM1_RX_EN 1 +#define CLK_SGM1_CK1_EN 2 +#define CLK_SGM1_CDR_CK1_EN 3 #define CLK_SGMII1_NR_CLK 4 /* ETHSYS */ -#define CK_ETH_FE_EN 0 -#define CK_ETH_GP2_EN 1 -#define CK_ETH_GP1_EN 2 -#define CK_ETH_WOCPU1_EN 3 -#define CK_ETH_WOCPU0_EN 4 +#define CLK_ETH_FE_EN 0 +#define CLK_ETH_GP2_EN 1 +#define CLK_ETH_GP1_EN 2 +#define CLK_ETH_WOCPU1_EN 3 +#define CLK_ETH_WOCPU0_EN 4 #define CLK_ETH_NR_CLK 5 #endif diff --git a/include/dt-bindings/clock/mt7988-clk.h b/include/dt-bindings/clock/mt7988-clk.h index 5c21bf63119..e6e6978809d 100644 --- a/include/dt-bindings/clock/mt7988-clk.h +++ b/include/dt-bindings/clock/mt7988-clk.h @@ -8,342 +8,257 @@ #ifndef _DT_BINDINGS_CLK_MT7988_H #define _DT_BINDINGS_CLK_MT7988_H -/* INFRACFG */ -/* mtk_fixed_factor */ -#define CK_INFRA_CK_F26M 0 -#define CK_INFRA_PWM_O 1 -#define CK_INFRA_PCIE_OCC_P0 2 -#define CK_INFRA_PCIE_OCC_P1 3 -#define CK_INFRA_PCIE_OCC_P2 4 -#define CK_INFRA_PCIE_OCC_P3 5 -#define CK_INFRA_133M_HCK 6 -#define CK_INFRA_133M_PHCK 7 -#define CK_INFRA_66M_PHCK 8 -#define CK_INFRA_FAUD_L_O 9 -#define CK_INFRA_FAUD_AUD_O 10 -#define CK_INFRA_FAUD_EG2_O 11 -#define CK_INFRA_I2C_O 12 -#define CK_INFRA_UART_O0 13 -#define CK_INFRA_UART_O1 14 -#define CK_INFRA_UART_O2 15 -#define CK_INFRA_NFI_O 16 -#define CK_INFRA_SPINFI_O 17 -#define CK_INFRA_SPI0_O 18 -#define CK_INFRA_SPI1_O 19 -#define CK_INFRA_LB_MUX_FRTC 20 -#define CK_INFRA_FRTC 21 -#define CK_INFRA_FMSDC400_O 22 -#define CK_INFRA_FMSDC2_HCK_OCC 23 -#define CK_INFRA_PERI_133M 24 -#define CK_INFRA_USB_O 25 -#define CK_INFRA_USB_O_P1 26 -#define CK_INFRA_USB_FRMCNT_O 27 -#define CK_INFRA_USB_FRMCNT_O_P1 28 -#define CK_INFRA_USB_XHCI_O 29 -#define CK_INFRA_USB_XHCI_O_P1 30 -#define CK_INFRA_USB_PIPE_O 31 -#define CK_INFRA_USB_PIPE_O_P1 32 -#define CK_INFRA_USB_UTMI_O 33 -#define CK_INFRA_USB_UTMI_O_P1 34 -#define CK_INFRA_PCIE_PIPE_OCC_P0 35 -#define CK_INFRA_PCIE_PIPE_OCC_P1 36 -#define CK_INFRA_PCIE_PIPE_OCC_P2 37 -#define CK_INFRA_PCIE_PIPE_OCC_P3 38 -#define CK_INFRA_F26M_O0 39 -#define CK_INFRA_F26M_O1 40 -#define CK_INFRA_133M_MCK 41 -#define CK_INFRA_66M_MCK 42 -#define CK_INFRA_PERI_66M_O 43 -#define CK_INFRA_USB_SYS_O 44 -#define CK_INFRA_USB_SYS_O_P1 45 - /* INFRACFG_AO */ -#define GATE_OFFSET 65 /* mtk_mux */ -#define CK_INFRA_MUX_UART0_SEL 46 /* Linux CLK ID (0) */ -#define CK_INFRA_MUX_UART1_SEL 47 /* Linux CLK ID (1) */ -#define CK_INFRA_MUX_UART2_SEL 48 /* Linux CLK ID (2) */ -#define CK_INFRA_MUX_SPI0_SEL 49 /* Linux CLK ID (3) */ -#define CK_INFRA_MUX_SPI1_SEL 50 /* Linux CLK ID (4) */ -#define CK_INFRA_MUX_SPI2_SEL 51 /* Linux CLK ID (5) */ -#define CK_INFRA_PWM_SEL 52 /* Linux CLK ID (6) */ -#define CK_INFRA_PWM_CK1_SEL 53 /* Linux CLK ID (7) */ -#define CK_INFRA_PWM_CK2_SEL 54 /* Linux CLK ID (8) */ -#define CK_INFRA_PWM_CK3_SEL 55 /* Linux CLK ID (9) */ -#define CK_INFRA_PWM_CK4_SEL 56 /* Linux CLK ID (10) */ -#define CK_INFRA_PWM_CK5_SEL 57 /* Linux CLK ID (11) */ -#define CK_INFRA_PWM_CK6_SEL 58 /* Linux CLK ID (12) */ -#define CK_INFRA_PWM_CK7_SEL 59 /* Linux CLK ID (13) */ -#define CK_INFRA_PWM_CK8_SEL 60 /* Linux CLK ID (14) */ -#define CK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 61 /* Linux CLK ID (15) */ -#define CK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 62 /* Linux CLK ID (16) */ -#define CK_INFRA_PCIE_GFMUX_TL_O_P2_SEL 63 /* Linux CLK ID (17) */ -#define CK_INFRA_PCIE_GFMUX_TL_O_P3_SEL 64 /* Linux CLK ID (18) */ +#define CLK_INFRA_MUX_UART0_SEL 0 +#define CLK_INFRA_MUX_UART1_SEL 1 +#define CLK_INFRA_MUX_UART2_SEL 2 +#define CLK_INFRA_MUX_SPI0_SEL 3 +#define CLK_INFRA_MUX_SPI1_SEL 4 +#define CLK_INFRA_MUX_SPI2_SEL 5 +#define CLK_INFRA_PWM_SEL 6 +#define CLK_INFRA_PWM_CK1_SEL 7 +#define CLK_INFRA_PWM_CK2_SEL 8 +#define CLK_INFRA_PWM_CK3_SEL 9 +#define CLK_INFRA_PWM_CK4_SEL 10 +#define CLK_INFRA_PWM_CK5_SEL 11 +#define CLK_INFRA_PWM_CK6_SEL 12 +#define CLK_INFRA_PWM_CK7_SEL 13 +#define CLK_INFRA_PWM_CK8_SEL 14 +#define CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 15 +#define CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 16 +#define CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL 17 +#define CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL 18 + +/* INFRACFG */ /* mtk_gate */ -#define CK_INFRA_66M_GPT_BCK (65 - GATE_OFFSET) /* Linux CLK ID (19) */ -#define CK_INFRA_66M_PWM_HCK (66 - GATE_OFFSET) /* Linux CLK ID (20) */ -#define CK_INFRA_66M_PWM_BCK (67 - GATE_OFFSET) /* Linux CLK ID (21) */ -#define CK_INFRA_66M_PWM_CK1 (68 - GATE_OFFSET) /* Linux CLK ID (22) */ -#define CK_INFRA_66M_PWM_CK2 (69 - GATE_OFFSET) /* Linux CLK ID (23) */ -#define CK_INFRA_66M_PWM_CK3 (70 - GATE_OFFSET) /* Linux CLK ID (24) */ -#define CK_INFRA_66M_PWM_CK4 (71 - GATE_OFFSET) /* Linux CLK ID (25) */ -#define CK_INFRA_66M_PWM_CK5 (72 - GATE_OFFSET) /* Linux CLK ID (26) */ -#define CK_INFRA_66M_PWM_CK6 (73 - GATE_OFFSET) /* Linux CLK ID (27) */ -#define CK_INFRA_66M_PWM_CK7 (74 - GATE_OFFSET) /* Linux CLK ID (28) */ -#define CK_INFRA_66M_PWM_CK8 (75 - GATE_OFFSET) /* Linux CLK ID (29) */ -#define CK_INFRA_133M_CQDMA_BCK (76 - GATE_OFFSET) /* Linux CLK ID (30) */ -#define CK_INFRA_66M_AUD_SLV_BCK (77 - GATE_OFFSET) /* Linux CLK ID (31) */ -#define CK_INFRA_AUD_26M (78 - GATE_OFFSET) /* Linux CLK ID (32) */ -#define CK_INFRA_AUD_L (79 - GATE_OFFSET) /* Linux CLK ID (33) */ -#define CK_INFRA_AUD_AUD (80 - GATE_OFFSET) /* Linux CLK ID (34) */ -#define CK_INFRA_AUD_EG2 (81 - GATE_OFFSET) /* Linux CLK ID (35) */ -#define CK_INFRA_DRAMC_F26M (82 - GATE_OFFSET) /* Linux CLK ID (36) */ -#define CK_INFRA_133M_DBG_ACKM (83 - GATE_OFFSET) /* Linux CLK ID (37) */ -#define CK_INFRA_66M_AP_DMA_BCK (84 - GATE_OFFSET) /* Linux CLK ID (38) */ -#define CK_INFRA_66M_SEJ_BCK (85 - GATE_OFFSET) /* Linux CLK ID (39) */ -#define CK_INFRA_PRE_CK_SEJ_F13M (86 - GATE_OFFSET) /* Linux CLK ID (40) */ -#define CK_INFRA_66M_TRNG (87 - GATE_OFFSET) /* Linux CLK ID (41) */ -#define CK_INFRA_26M_THERM_SYSTEM (88 - GATE_OFFSET) /* Linux CLK ID (42) */ -#define CK_INFRA_I2C_BCK (89 - GATE_OFFSET) /* Linux CLK ID (43) */ -#define CK_INFRA_66M_UART0_PCK (90 - GATE_OFFSET) /* Linux CLK ID (44) */ -#define CK_INFRA_66M_UART1_PCK (91 - GATE_OFFSET) /* Linux CLK ID (45) */ -#define CK_INFRA_66M_UART2_PCK (92 - GATE_OFFSET) /* Linux CLK ID (46) */ -#define CK_INFRA_52M_UART0_CK (93 - GATE_OFFSET) /* Linux CLK ID (47) */ -#define CK_INFRA_52M_UART1_CK (94 - GATE_OFFSET) /* Linux CLK ID (48) */ -#define CK_INFRA_52M_UART2_CK (95 - GATE_OFFSET) /* Linux CLK ID (49) */ -#define CK_INFRA_NFI (96 - GATE_OFFSET) /* Linux CLK ID (50) */ -#define CK_INFRA_SPINFI (97 - GATE_OFFSET) /* Linux CLK ID (51) */ -#define CK_INFRA_66M_NFI_HCK (98 - GATE_OFFSET) /* Linux CLK ID (52) */ -#define CK_INFRA_104M_SPI0 (99 - GATE_OFFSET) /* Linux CLK ID (53) */ -#define CK_INFRA_104M_SPI1 (100 - GATE_OFFSET) /* Linux CLK ID (54) */ -#define CK_INFRA_104M_SPI2_BCK (101 - GATE_OFFSET) /* Linux CLK ID (55) */ -#define CK_INFRA_66M_SPI0_HCK (102 - GATE_OFFSET) /* Linux CLK ID (56) */ -#define CK_INFRA_66M_SPI1_HCK (103 - GATE_OFFSET) /* Linux CLK ID (57) */ -#define CK_INFRA_66M_SPI2_HCK (104 - GATE_OFFSET) /* Linux CLK ID (58) */ -#define CK_INFRA_66M_FLASHIF_AXI (105 - GATE_OFFSET) /* Linux CLK ID (59) */ -#define CK_INFRA_RTC (106 - GATE_OFFSET) /* Linux CLK ID (60) */ -#define CK_INFRA_26M_ADC_BCK (107 - GATE_OFFSET) /* Linux CLK ID (61) */ -#define CK_INFRA_RC_ADC (108 - GATE_OFFSET) /* Linux CLK ID (62) */ -#define CK_INFRA_MSDC400 (109 - GATE_OFFSET) /* Linux CLK ID (63) */ -#define CK_INFRA_MSDC2_HCK (110 - GATE_OFFSET) /* Linux CLK ID (64) */ -#define CK_INFRA_133M_MSDC_0_HCK (111 - GATE_OFFSET) /* Linux CLK ID (65) */ -#define CK_INFRA_66M_MSDC_0_HCK (112 - GATE_OFFSET) /* Linux CLK ID (66) */ -#define CK_INFRA_133M_CPUM_BCK (113 - GATE_OFFSET) /* Linux CLK ID (67) */ -#define CK_INFRA_BIST2FPC (114 - GATE_OFFSET) /* Linux CLK ID (68) */ -#define CK_INFRA_I2C_X16W_MCK_CK_P1 (115 - GATE_OFFSET) /* Linux CLK ID (69) */ -#define CK_INFRA_I2C_X16W_PCK_CK_P1 (116 - GATE_OFFSET) /* Linux CLK ID (70) */ -#define CK_INFRA_133M_USB_HCK (117 - GATE_OFFSET) /* Linux CLK ID (71) */ -#define CK_INFRA_133M_USB_HCK_CK_P1 (118 - GATE_OFFSET) /* Linux CLK ID (72) */ -#define CK_INFRA_66M_USB_HCK (119 - GATE_OFFSET) /* Linux CLK ID (73) */ -#define CK_INFRA_66M_USB_HCK_CK_P1 (120 - GATE_OFFSET) /* Linux CLK ID (74) */ -#define CK_INFRA_USB_SYS (121 - GATE_OFFSET) /* Linux CLK ID (75) */ -#define CK_INFRA_USB_SYS_CK_P1 (122 - GATE_OFFSET) /* Linux CLK ID (76) */ -#define CK_INFRA_USB_REF (123 - GATE_OFFSET) /* Linux CLK ID (77) */ -#define CK_INFRA_USB_CK_P1 (124 - GATE_OFFSET) /* Linux CLK ID (78) */ -#define CK_INFRA_USB_FRMCNT (125 - GATE_OFFSET) /* Linux CLK ID (79) */ -#define CK_INFRA_USB_FRMCNT_CK_P1 (126 - GATE_OFFSET) /* Linux CLK ID (80) */ -#define CK_INFRA_USB_PIPE (127 - GATE_OFFSET) /* Linux CLK ID (81) */ -#define CK_INFRA_USB_PIPE_CK_P1 (128 - GATE_OFFSET) /* Linux CLK ID (82) */ -#define CK_INFRA_USB_UTMI (129 - GATE_OFFSET) /* Linux CLK ID (83) */ -#define CK_INFRA_USB_UTMI_CK_P1 (130 - GATE_OFFSET) /* Linux CLK ID (84) */ -#define CK_INFRA_USB_XHCI (131 - GATE_OFFSET) /* Linux CLK ID (85) */ -#define CK_INFRA_USB_XHCI_CK_P1 (132 - GATE_OFFSET) /* Linux CLK ID (86) */ -#define CK_INFRA_PCIE_GFMUX_TL_P0 (133 - GATE_OFFSET) /* Linux CLK ID (87) */ -#define CK_INFRA_PCIE_GFMUX_TL_P1 (134 - GATE_OFFSET) /* Linux CLK ID (88) */ -#define CK_INFRA_PCIE_GFMUX_TL_P2 (135 - GATE_OFFSET) /* Linux CLK ID (89) */ -#define CK_INFRA_PCIE_GFMUX_TL_P3 (136 - GATE_OFFSET) /* Linux CLK ID (90) */ -#define CK_INFRA_PCIE_PIPE_P0 (137 - GATE_OFFSET) /* Linux CLK ID (91) */ -#define CK_INFRA_PCIE_PIPE_P1 (138 - GATE_OFFSET) /* Linux CLK ID (92) */ -#define CK_INFRA_PCIE_PIPE_P2 (139 - GATE_OFFSET) /* Linux CLK ID (93) */ -#define CK_INFRA_PCIE_PIPE_P3 (140 - GATE_OFFSET) /* Linux CLK ID (94) */ -#define CK_INFRA_133M_PCIE_CK_P0 (141 - GATE_OFFSET) /* Linux CLK ID (95) */ -#define CK_INFRA_133M_PCIE_CK_P1 (142 - GATE_OFFSET) /* Linux CLK ID (96) */ -#define CK_INFRA_133M_PCIE_CK_P2 (143 - GATE_OFFSET) /* Linux CLK ID (97) */ -#define CK_INFRA_133M_PCIE_CK_P3 (144 - GATE_OFFSET) /* Linux CLK ID (98) */ -#define CK_INFRA_PCIE_PERI_26M_CK_P0 (145 - GATE_OFFSET) /* Linux CLK ID (99) */ -#define CK_INFRA_PCIE_PERI_26M_CK_P1 \ - (146 - GATE_OFFSET) /* Linux CLK ID (100) */ -#define CK_INFRA_PCIE_PERI_26M_CK_P2 \ - (147 - GATE_OFFSET) /* Linux CLK ID (101) */ -#define CK_INFRA_PCIE_PERI_26M_CK_P3 \ - (148 - GATE_OFFSET) /* Linux CLK ID (102) */ +#define CLK_INFRA_PCIE_PERI_26M_CK_P0 19 +#define CLK_INFRA_PCIE_PERI_26M_CK_P1 20 +#define CLK_INFRA_PCIE_PERI_26M_CK_P2 21 +#define CLK_INFRA_PCIE_PERI_26M_CK_P3 22 +#define CLK_INFRA_66M_GPT_BCK 23 +#define CLK_INFRA_66M_PWM_HCK 24 +#define CLK_INFRA_66M_PWM_BCK 25 +#define CLK_INFRA_66M_PWM_CK1 26 +#define CLK_INFRA_66M_PWM_CK2 27 +#define CLK_INFRA_66M_PWM_CK3 28 +#define CLK_INFRA_66M_PWM_CK4 29 +#define CLK_INFRA_66M_PWM_CK5 30 +#define CLK_INFRA_66M_PWM_CK6 31 +#define CLK_INFRA_66M_PWM_CK7 32 +#define CLK_INFRA_66M_PWM_CK8 33 +#define CLK_INFRA_133M_CQDMA_BCK 34 +#define CLK_INFRA_66M_AUD_SLV_BCK 35 +#define CLK_INFRA_AUD_26M 36 +#define CLK_INFRA_AUD_L 37 +#define CLK_INFRA_AUD_AUD 38 +#define CLK_INFRA_AUD_EG2 39 +#define CLK_INFRA_DRAMC_F26M 40 +#define CLK_INFRA_133M_DBG_ACKM 41 +#define CLK_INFRA_66M_AP_DMA_BCK 42 +#define CLK_INFRA_66M_SEJ_BCK 43 +#define CLK_INFRA_PRE_CK_SEJ_F13M 44 +/* #define CLK_INFRA_66M_TRNG 44 */ +#define CLK_INFRA_26M_THERM_SYSTEM 45 +#define CLK_INFRA_I2C_BCK 46 +/* #define CLK_INFRA_66M_UART0_PCK 46 */ +/* #define CLK_INFRA_66M_UART1_PCK 47 */ +/* #define CLK_INFRA_66M_UART2_PCK 48 */ +#define CLK_INFRA_52M_UART0_CK 47 +#define CLK_INFRA_52M_UART1_CK 48 +#define CLK_INFRA_52M_UART2_CK 49 +#define CLK_INFRA_NFI 50 +#define CLK_INFRA_SPINFI 51 +#define CLK_INFRA_66M_NFI_HCK 52 +#define CLK_INFRA_104M_SPI0 53 +#define CLK_INFRA_104M_SPI1 54 +#define CLK_INFRA_104M_SPI2_BCK 55 +#define CLK_INFRA_66M_SPI0_HCK 56 +#define CLK_INFRA_66M_SPI1_HCK 57 +#define CLK_INFRA_66M_SPI2_HCK 58 +#define CLK_INFRA_66M_FLASHIF_AXI 59 +#define CLK_INFRA_RTC 60 +#define CLK_INFRA_26M_ADC_BCK 61 +#define CLK_INFRA_RC_ADC 62 +#define CLK_INFRA_MSDC400 63 +#define CLK_INFRA_MSDC2_HCK 64 +#define CLK_INFRA_133M_MSDC_0_HCK 65 +#define CLK_INFRA_66M_MSDC_0_HCK 66 +#define CLK_INFRA_133M_CPUM_BCK 67 +#define CLK_INFRA_BIST2FPC 68 +#define CLK_INFRA_I2C_X16W_MCK_CK_P1 69 +#define CLK_INFRA_I2C_X16W_PCK_CK_P1 70 +#define CLK_INFRA_133M_USB_HCK 71 +#define CLK_INFRA_133M_USB_HCK_CK_P1 72 +#define CLK_INFRA_66M_USB_HCK 73 +#define CLK_INFRA_66M_USB_HCK_CK_P1 74 +#define CLK_INFRA_USB_SYS 75 +#define CLK_INFRA_USB_SYS_CK_P1 76 +#define CLK_INFRA_USB_REF 77 +#define CLK_INFRA_USB_CK_P1 78 +#define CLK_INFRA_USB_FRMCNT 79 +#define CLK_INFRA_USB_FRMCNT_CK_P1 80 +#define CLK_INFRA_USB_PIPE 81 +#define CLK_INFRA_USB_PIPE_CK_P1 82 +#define CLK_INFRA_USB_UTMI 83 +#define CLK_INFRA_USB_UTMI_CK_P1 84 +#define CLK_INFRA_USB_XHCI 85 +#define CLK_INFRA_USB_XHCI_CK_P1 86 +#define CLK_INFRA_PCIE_GFMUX_TL_P0 87 +#define CLK_INFRA_PCIE_GFMUX_TL_P1 88 +#define CLK_INFRA_PCIE_GFMUX_TL_P2 89 +#define CLK_INFRA_PCIE_GFMUX_TL_P3 90 +#define CLK_INFRA_PCIE_PIPE_P0 91 +#define CLK_INFRA_PCIE_PIPE_P1 92 +#define CLK_INFRA_PCIE_PIPE_P2 93 +#define CLK_INFRA_PCIE_PIPE_P3 94 +#define CLK_INFRA_133M_PCIE_CK_P0 95 +#define CLK_INFRA_133M_PCIE_CK_P1 96 +#define CLK_INFRA_133M_PCIE_CK_P2 97 +#define CLK_INFRA_133M_PCIE_CK_P3 98 /* TOPCKGEN */ +/* mtk_fixed_clk */ +#define CLK_TOP_XTAL 0 /* mtk_fixed_factor */ -#define CK_TOP_CB_CKSQ_40M 0 /* Linux CLK ID (74) */ -#define CK_TOP_CB_M_416M 1 /* Linux CLK ID (75) */ -#define CK_TOP_CB_M_D2 2 /* Linux CLK ID (76) */ -#define CK_TOP_M_D3_D2 3 /* Linux CLK ID (77) */ -#define CK_TOP_CB_M_D4 4 /* Linux CLK ID (78) */ -#define CK_TOP_CB_M_D8 5 /* Linux CLK ID (79) */ -#define CK_TOP_M_D8_D2 6 /* Linux CLK ID (80) */ -#define CK_TOP_CB_MM_720M 7 /* Linux CLK ID (81) */ -#define CK_TOP_CB_MM_D2 8 /* Linux CLK ID (82) */ -#define CK_TOP_CB_MM_D3_D5 9 /* Linux CLK ID (83) */ -#define CK_TOP_CB_MM_D4 10 /* Linux CLK ID (84) */ -#define CK_TOP_MM_D6_D2 11 /* Linux CLK ID (85) */ -#define CK_TOP_CB_MM_D8 12 /* Linux CLK ID (86) */ -#define CK_TOP_CB_APLL2_196M 13 /* Linux CLK ID (87) */ -#define CK_TOP_CB_APLL2_D4 14 /* Linux CLK ID (88) */ -#define CK_TOP_CB_NET1_D4 15 /* Linux CLK ID (89) */ -#define CK_TOP_CB_NET1_D5 16 /* Linux CLK ID (90) */ -#define CK_TOP_NET1_D5_D2 17 /* Linux CLK ID (91) */ -#define CK_TOP_NET1_D5_D4 18 /* Linux CLK ID (92) */ -#define CK_TOP_CB_NET1_D8 19 /* Linux CLK ID (93) */ -#define CK_TOP_NET1_D8_D2 20 /* Linux CLK ID (94) */ -#define CK_TOP_NET1_D8_D4 21 /* Linux CLK ID (95) */ -#define CK_TOP_NET1_D8_D8 22 /* Linux CLK ID (96) */ -#define CK_TOP_NET1_D8_D16 23 /* Linux CLK ID (97) */ -#define CK_TOP_CB_NET2_800M 24 /* Linux CLK ID (98) */ -#define CK_TOP_CB_NET2_D2 25 /* Linux CLK ID (99) */ -#define CK_TOP_CB_NET2_D4 26 /* Linux CLK ID (100) */ -#define CK_TOP_NET2_D4_D4 27 /* Linux CLK ID (101) */ -#define CK_TOP_NET2_D4_D8 28 /* Linux CLK ID (102) */ -#define CK_TOP_CB_NET2_D6 29 /* Linux CLK ID (103) */ -#define CK_TOP_CB_NET2_D8 30 /* Linux CLK ID (104) */ -#define CK_TOP_CB_WEDMCU_208M 31 /* Linux CLK ID (105) */ -#define CK_TOP_CB_SGM_325M 32 /* Linux CLK ID (106) */ -#define CK_TOP_CB_NETSYS_850M 33 /* Linux CLK ID (107) */ -#define CK_TOP_CB_MSDC_400M 34 /* Linux CLK ID (108) */ -#define CK_TOP_CKSQ_40M_D2 35 /* Linux CLK ID (109) */ -#define CK_TOP_CB_RTC_32K 36 /* Linux CLK ID (110) */ -#define CK_TOP_CB_RTC_32P7K 37 /* Linux CLK ID (111) */ -#define CK_TOP_INFRA_F32K 38 /* Linux CLK ID (112) */ -#define CK_TOP_CKSQ_SRC 39 /* Linux CLK ID (113) */ -#define CK_TOP_NETSYS_2X 40 /* Linux CLK ID (114) */ -#define CK_TOP_NETSYS_GSW 41 /* Linux CLK ID (115) */ -#define CK_TOP_NETSYS_WED_MCU 42 /* Linux CLK ID (116) */ -#define CK_TOP_EIP197 43 /* Linux CLK ID (117) */ -#define CK_TOP_EMMC_250M 44 /* Linux CLK ID (118) */ -#define CK_TOP_EMMC_400M 45 /* Linux CLK ID (119) */ -#define CK_TOP_SPI 46 /* Linux CLK ID (120) */ -#define CK_TOP_SPIM_MST 47 /* Linux CLK ID (121) */ -#define CK_TOP_NFI1X 48 /* Linux CLK ID (122) */ -#define CK_TOP_SPINFI_BCK 49 /* Linux CLK ID (123) */ -#define CK_TOP_I2C_BCK 50 /* Linux CLK ID (124) */ -#define CK_TOP_USB_SYS 51 /* Linux CLK ID (125) */ -#define CK_TOP_USB_SYS_P1 52 /* Linux CLK ID (126) */ -#define CK_TOP_USB_XHCI 53 /* Linux CLK ID (127) */ -#define CK_TOP_USB_XHCI_P1 54 /* Linux CLK ID (128) */ -#define CK_TOP_USB_FRMCNT 55 /* Linux CLK ID (129) */ -#define CK_TOP_USB_FRMCNT_P1 56 /* Linux CLK ID (130) */ -#define CK_TOP_AUD 57 /* Linux CLK ID (131) */ -#define CK_TOP_A1SYS 58 /* Linux CLK ID (132) */ -#define CK_TOP_AUD_L 59 /* Linux CLK ID (133) */ -#define CK_TOP_A_TUNER 60 /* Linux CLK ID (134) */ -#define CK_TOP_SYSAXI 61 /* Linux CLK ID (135) */ -#define CK_TOP_INFRA_F26M 62 /* Linux CLK ID (136) */ -#define CK_TOP_USB_REF 63 /* Linux CLK ID (137) */ -#define CK_TOP_USB_CK_P1 64 /* Linux CLK ID (138) */ +#define CLK_TOP_XTAL_D2 1 +#define CLK_TOP_RTC_32K 2 +#define CLK_TOP_RTC_32P7K 3 +#define CLK_TOP_MPLL_D2 4 +#define CLK_TOP_MPLL_D3_D2 5 +#define CLK_TOP_MPLL_D4 6 +#define CLK_TOP_MPLL_D8 7 +#define CLK_TOP_MPLL_D8_D2 8 +#define CLK_TOP_MMPLL_D2 9 +#define CLK_TOP_MMPLL_D3_D5 10 +#define CLK_TOP_MMPLL_D4 11 +#define CLK_TOP_MMPLL_D6_D2 12 +#define CLK_TOP_MMPLL_D8 13 +#define CLK_TOP_APLL2_D4 14 +#define CLK_TOP_NET1PLL_D4 15 +#define CLK_TOP_NET1PLL_D5 16 +#define CLK_TOP_NET1PLL_D5_D2 17 +#define CLK_TOP_NET1PLL_D5_D4 18 +#define CLK_TOP_NET1PLL_D8 19 +#define CLK_TOP_NET1PLL_D8_D2 20 +#define CLK_TOP_NET1PLL_D8_D4 21 +#define CLK_TOP_NET1PLL_D8_D8 22 +#define CLK_TOP_NET1PLL_D8_D16 23 +#define CLK_TOP_NET2PLL_D2 24 +#define CLK_TOP_NET2PLL_D4 25 +#define CLK_TOP_NET2PLL_D4_D4 26 +#define CLK_TOP_NET2PLL_D4_D8 27 +#define CLK_TOP_NET2PLL_D6 28 +#define CLK_TOP_NET2PLL_D8 29 /* mtk_mux */ -#define CK_TOP_NETSYS_SEL 65 /* Linux CLK ID (0) */ -#define CK_TOP_NETSYS_500M_SEL 66 /* Linux CLK ID (1) */ -#define CK_TOP_NETSYS_2X_SEL 67 /* Linux CLK ID (2) */ -#define CK_TOP_NETSYS_GSW_SEL 68 /* Linux CLK ID (3) */ -#define CK_TOP_ETH_GMII_SEL 69 /* Linux CLK ID (4) */ -#define CK_TOP_NETSYS_MCU_SEL 70 /* Linux CLK ID (5) */ -#define CK_TOP_NETSYS_PAO_2X_SEL 71 /* Linux CLK ID (6) */ -#define CK_TOP_EIP197_SEL 72 /* Linux CLK ID (7) */ -#define CK_TOP_AXI_INFRA_SEL 73 /* Linux CLK ID (8) */ -#define CK_TOP_UART_SEL 74 /* Linux CLK ID (9) */ -#define CK_TOP_EMMC_250M_SEL 75 /* Linux CLK ID (10) */ -#define CK_TOP_EMMC_400M_SEL 76 /* Linux CLK ID (11) */ -#define CK_TOP_SPI_SEL 77 /* Linux CLK ID (12) */ -#define CK_TOP_SPIM_MST_SEL 78 /* Linux CLK ID (13) */ -#define CK_TOP_NFI1X_SEL 79 /* Linux CLK ID (14) */ -#define CK_TOP_SPINFI_SEL 80 /* Linux CLK ID (15) */ -#define CK_TOP_PWM_SEL 81 /* Linux CLK ID (16) */ -#define CK_TOP_I2C_SEL 82 /* Linux CLK ID (17) */ -#define CK_TOP_PCIE_MBIST_250M_SEL 83 /* Linux CLK ID (18) */ -#define CK_TOP_PEXTP_TL_SEL 84 /* Linux CLK ID (19) */ -#define CK_TOP_PEXTP_TL_P1_SEL 85 /* Linux CLK ID (20) */ -#define CK_TOP_PEXTP_TL_P2_SEL 86 /* Linux CLK ID (21) */ -#define CK_TOP_PEXTP_TL_P3_SEL 87 /* Linux CLK ID (22) */ -#define CK_TOP_USB_SYS_SEL 88 /* Linux CLK ID (23) */ -#define CK_TOP_USB_SYS_P1_SEL 89 /* Linux CLK ID (24) */ -#define CK_TOP_USB_XHCI_SEL 90 /* Linux CLK ID (25) */ -#define CK_TOP_USB_XHCI_P1_SEL 91 /* Linux CLK ID (26) */ -#define CK_TOP_USB_FRMCNT_SEL 92 /* Linux CLK ID (27) */ -#define CK_TOP_USB_FRMCNT_P1_SEL 93 /* Linux CLK ID (28) */ -#define CK_TOP_AUD_SEL 94 /* Linux CLK ID (29) */ -#define CK_TOP_A1SYS_SEL 95 /* Linux CLK ID (30) */ -#define CK_TOP_AUD_L_SEL 96 /* Linux CLK ID (31) */ -#define CK_TOP_A_TUNER_SEL 97 /* Linux CLK ID (32) */ -#define CK_TOP_SSPXTP_SEL 98 /* Linux CLK ID (33) */ -#define CK_TOP_USB_PHY_SEL 99 /* Linux CLK ID (34) */ -#define CK_TOP_USXGMII_SBUS_0_SEL 100 /* Linux CLK ID (35) */ -#define CK_TOP_USXGMII_SBUS_1_SEL 101 /* Linux CLK ID (36) */ -#define CK_TOP_SGM_0_SEL 102 /* Linux CLK ID (37) */ -#define CK_TOP_SGM_SBUS_0_SEL 103 /* Linux CLK ID (38) */ -#define CK_TOP_SGM_1_SEL 104 /* Linux CLK ID (39) */ -#define CK_TOP_SGM_SBUS_1_SEL 105 /* Linux CLK ID (40) */ -#define CK_TOP_XFI_PHY_0_XTAL_SEL 106 /* Linux CLK ID (41) */ -#define CK_TOP_XFI_PHY_1_XTAL_SEL 107 /* Linux CLK ID (42) */ -#define CK_TOP_SYSAXI_SEL 108 /* Linux CLK ID (43) */ -#define CK_TOP_SYSAPB_SEL 109 /* Linux CLK ID (44) */ -#define CK_TOP_ETH_REFCK_50M_SEL 110 /* Linux CLK ID (45) */ -#define CK_TOP_ETH_SYS_200M_SEL 111 /* Linux CLK ID (46) */ -#define CK_TOP_ETH_SYS_SEL 112 /* Linux CLK ID (47) */ -#define CK_TOP_ETH_XGMII_SEL 113 /* Linux CLK ID (48) */ -#define CK_TOP_BUS_TOPS_SEL 114 /* Linux CLK ID (49) */ -#define CK_TOP_NPU_TOPS_SEL 115 /* Linux CLK ID (50) */ -#define CK_TOP_DRAMC_SEL 116 /* Linux CLK ID (51) */ -#define CK_TOP_DRAMC_MD32_SEL 117 /* Linux CLK ID (52) */ -#define CK_TOP_INFRA_F26M_SEL 118 /* Linux CLK ID (53) */ -#define CK_TOP_PEXTP_P0_SEL 119 /* Linux CLK ID (54) */ -#define CK_TOP_PEXTP_P1_SEL 120 /* Linux CLK ID (55) */ -#define CK_TOP_PEXTP_P2_SEL 121 /* Linux CLK ID (56) */ -#define CK_TOP_PEXTP_P3_SEL 122 /* Linux CLK ID (57) */ -#define CK_TOP_DA_XTP_GLB_P0_SEL 123 /* Linux CLK ID (58) */ -#define CK_TOP_DA_XTP_GLB_P1_SEL 124 /* Linux CLK ID (59) */ -#define CK_TOP_DA_XTP_GLB_P2_SEL 125 /* Linux CLK ID (60) */ -#define CK_TOP_DA_XTP_GLB_P3_SEL 126 /* Linux CLK ID (61) */ -#define CK_TOP_CKM_SEL 127 /* Linux CLK ID (62) */ -#define CK_TOP_DA_SELM_XTAL_SEL 128 /* Linux CLK ID (63) */ -#define CK_TOP_PEXTP_SEL 129 /* Linux CLK ID (64) */ -#define CK_TOP_TOPS_P2_26M_SEL 130 /* Linux CLK ID (65) */ -#define CK_TOP_MCUSYS_BACKUP_625M_SEL 131 /* Linux CLK ID (66) */ -#define CK_TOP_NETSYS_SYNC_250M_SEL 132 /* Linux CLK ID (67) */ -#define CK_TOP_MACSEC_SEL 133 /* Linux CLK ID (68) */ -#define CK_TOP_NETSYS_TOPS_400M_SEL 134 /* Linux CLK ID (69) */ -#define CK_TOP_NETSYS_PPEFB_250M_SEL 135 /* Linux CLK ID (70) */ -#define CK_TOP_NETSYS_WARP_SEL 136 /* Linux CLK ID (71) */ -#define CK_TOP_ETH_MII_SEL 137 /* Linux CLK ID (72) */ -#define CK_TOP_CK_NPU_SEL_CM_TOPS_SEL 138 /* Linux CLK ID (73) */ +#define CLK_TOP_NETSYS_SEL 30 +#define CLK_TOP_NETSYS_500M_SEL 31 +#define CLK_TOP_NETSYS_2X_SEL 32 +#define CLK_TOP_NETSYS_GSW_SEL 33 +#define CLK_TOP_ETH_GMII_SEL 34 +#define CLK_TOP_NETSYS_MCU_SEL 35 +#define CLK_TOP_NETSYS_PAO_2X_SEL 36 +#define CLK_TOP_EIP197_SEL 37 +#define CLK_TOP_AXI_INFRA_SEL 38 +#define CLK_TOP_UART_SEL 39 +#define CLK_TOP_EMMC_250M_SEL 40 +#define CLK_TOP_EMMC_400M_SEL 41 +#define CLK_TOP_SPI_SEL 42 +#define CLK_TOP_SPIM_MST_SEL 43 +#define CLK_TOP_NFI1X_SEL 44 +#define CLK_TOP_SPINFI_SEL 45 +#define CLK_TOP_PWM_SEL 46 +#define CLK_TOP_I2C_SEL 47 +#define CLK_TOP_PCIE_MBIST_250M_SEL 48 +#define CLK_TOP_PEXTP_TL_SEL 49 +#define CLK_TOP_PEXTP_TL_P1_SEL 50 +#define CLK_TOP_PEXTP_TL_P2_SEL 51 +#define CLK_TOP_PEXTP_TL_P3_SEL 52 +#define CLK_TOP_USB_SYS_SEL 53 +#define CLK_TOP_USB_SYS_P1_SEL 54 +#define CLK_TOP_USB_XHCI_SEL 55 +#define CLK_TOP_USB_XHCI_P1_SEL 56 +#define CLK_TOP_USB_FRMCNT_SEL 57 +#define CLK_TOP_USB_FRMCNT_P1_SEL 58 +#define CLK_TOP_AUD_SEL 59 +#define CLK_TOP_A1SYS_SEL 60 +#define CLK_TOP_AUD_L_SEL 61 +#define CLK_TOP_A_TUNER_SEL 62 +#define CLK_TOP_SSPXTP_SEL 63 +#define CLK_TOP_USB_PHY_SEL 64 +#define CLK_TOP_USXGMII_SBUS_0_SEL 65 +#define CLK_TOP_USXGMII_SBUS_1_SEL 66 +#define CLK_TOP_SGM_0_SEL 67 +#define CLK_TOP_SGM_SBUS_0_SEL 68 +#define CLK_TOP_SGM_1_SEL 69 +#define CLK_TOP_SGM_SBUS_1_SEL 70 +#define CLK_TOP_XFI_PHY_0_XTAL_SEL 71 +#define CLK_TOP_XFI_PHY_1_XTAL_SEL 72 +#define CLK_TOP_SYSAXI_SEL 73 +#define CLK_TOP_SYSAPB_SEL 74 +#define CLK_TOP_ETH_REFCK_50M_SEL 75 +#define CLK_TOP_ETH_SYS_200M_SEL 76 +#define CLK_TOP_ETH_SYS_SEL 77 +#define CLK_TOP_ETH_XGMII_SEL 78 +#define CLK_TOP_BUS_TOPS_SEL 79 +#define CLK_TOP_NPU_TOPS_SEL 80 +#define CLK_TOP_DRAMC_SEL 81 +#define CLK_TOP_DRAMC_MD32_SEL 82 +#define CLK_TOP_INFRA_F26M_SEL 83 +#define CLK_TOP_PEXTP_P0_SEL 84 +#define CLK_TOP_PEXTP_P1_SEL 85 +#define CLK_TOP_PEXTP_P2_SEL 86 +#define CLK_TOP_PEXTP_P3_SEL 87 +#define CLK_TOP_DA_XTP_GLB_P0_SEL 88 +#define CLK_TOP_DA_XTP_GLB_P1_SEL 89 +#define CLK_TOP_DA_XTP_GLB_P2_SEL 90 +#define CLK_TOP_DA_XTP_GLB_P3_SEL 91 +#define CLK_TOP_CKM_SEL 92 +#define CLK_TOP_DA_SEL 93 +#define CLK_TOP_PEXTP_SEL 94 +#define CLK_TOP_TOPS_P2_26M_SEL 95 +#define CLK_TOP_MCUSYS_BACKUP_625M_SEL 96 +#define CLK_TOP_NETSYS_SYNC_250M_SEL 97 +#define CLK_TOP_MACSEC_SEL 98 +#define CLK_TOP_NETSYS_TOPS_400M_SEL 99 +#define CLK_TOP_NETSYS_PPEFB_250M_SEL 100 +#define CLK_TOP_NETSYS_WARP_SEL 101 +#define CLK_TOP_ETH_MII_SEL 102 +#define CLK_TOP_NPU_SEL 103 /* APMIXEDSYS */ /* mtk_pll_data */ -#define CK_APMIXED_NETSYSPLL 0 -#define CK_APMIXED_MPLL 1 -#define CK_APMIXED_MMPLL 2 -#define CK_APMIXED_APLL2 3 -#define CK_APMIXED_NET1PLL 4 -#define CK_APMIXED_NET2PLL 5 -#define CK_APMIXED_WEDMCUPLL 6 -#define CK_APMIXED_SGMPLL 7 -#define CK_APMIXED_ARM_B 8 -#define CK_APMIXED_CCIPLL2_B 9 -#define CK_APMIXED_USXGMIIPLL 10 -#define CK_APMIXED_MSDCPLL 11 +#define CLK_APMIXED_NETSYSPLL 0 +#define CLK_APMIXED_MPLL 1 +#define CLK_APMIXED_MMPLL 2 +#define CLK_APMIXED_APLL2 3 +#define CLK_APMIXED_NET1PLL 4 +#define CLK_APMIXED_NET2PLL 5 +#define CLK_APMIXED_WEDMCUPLL 6 +#define CLK_APMIXED_SGMPLL 7 +#define CLK_APMIXED_ARM_B 8 +#define CLK_APMIXED_CCIPLL2_B 9 +#define CLK_APMIXED_USXGMIIPLL 10 +#define CLK_APMIXED_MSDCPLL 11 /* ETHSYS ETH DMA */ /* mtk_gate */ -#define CK_ETHDMA_FE_EN 0 +#define CLK_ETHDMA_FE_EN 0 /* SGMIISYS_0 */ /* mtk_gate */ -#define CK_SGM0_TX_EN 0 -#define CK_SGM0_RX_EN 1 +#define CLK_SGM0_TX_EN 0 +#define CLK_SGM0_RX_EN 1 /* SGMIISYS_1 */ /* mtk_gate */ -#define CK_SGM1_TX_EN 0 -#define CK_SGM1_RX_EN 1 +#define CLK_SGM1_TX_EN 0 +#define CLK_SGM1_RX_EN 1 /* ETHWARP */ /* mtk_gate */ -#define CK_ETHWARP_WOCPU2_EN 0 -#define CK_ETHWARP_WOCPU1_EN 1 -#define CK_ETHWARP_WOCPU0_EN 2 +#define CLK_ETHWARP_WOCPU2_EN 0 +#define CLK_ETHWARP_WOCPU1_EN 1 +#define CLK_ETHWARP_WOCPU0_EN 2 #endif /* _DT_BINDINGS_CLK_MT7988_H */ diff --git a/include/dt-bindings/clock/px30-cru.h b/include/dt-bindings/clock/px30-cru.h deleted file mode 100644 index e5e59690b5f..00000000000 --- a/include/dt-bindings/clock/px30-cru.h +++ /dev/null @@ -1,389 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2017 Rockchip Electronics Co. Ltd. - * Author: Elaine <zhangqing@rock-chips.com> - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_PX30_H -#define _DT_BINDINGS_CLK_ROCKCHIP_PX30_H - -/* core clocks */ -#define PLL_APLL 1 -#define PLL_DPLL 2 -#define PLL_CPLL 3 -#define PLL_NPLL 4 -#define APLL_BOOST_H 5 -#define APLL_BOOST_L 6 -#define ARMCLK 7 - -/* sclk gates (special clocks) */ -#define USB480M 14 -#define SCLK_PDM 15 -#define SCLK_I2S0_TX 16 -#define SCLK_I2S0_TX_OUT 17 -#define SCLK_I2S0_RX 18 -#define SCLK_I2S0_RX_OUT 19 -#define SCLK_I2S1 20 -#define SCLK_I2S1_OUT 21 -#define SCLK_I2S2 22 -#define SCLK_I2S2_OUT 23 -#define SCLK_UART1 24 -#define SCLK_UART2 25 -#define SCLK_UART3 26 -#define SCLK_UART4 27 -#define SCLK_UART5 28 -#define SCLK_I2C0 29 -#define SCLK_I2C1 30 -#define SCLK_I2C2 31 -#define SCLK_I2C3 32 -#define SCLK_I2C4 33 -#define SCLK_PWM0 34 -#define SCLK_PWM1 35 -#define SCLK_SPI0 36 -#define SCLK_SPI1 37 -#define SCLK_TIMER0 38 -#define SCLK_TIMER1 39 -#define SCLK_TIMER2 40 -#define SCLK_TIMER3 41 -#define SCLK_TIMER4 42 -#define SCLK_TIMER5 43 -#define SCLK_TSADC 44 -#define SCLK_SARADC 45 -#define SCLK_OTP 46 -#define SCLK_OTP_USR 47 -#define SCLK_CRYPTO 48 -#define SCLK_CRYPTO_APK 49 -#define SCLK_DDRC 50 -#define SCLK_ISP 51 -#define SCLK_CIF_OUT 52 -#define SCLK_RGA_CORE 53 -#define SCLK_VOPB_PWM 54 -#define SCLK_NANDC 55 -#define SCLK_SDIO 56 -#define SCLK_EMMC 57 -#define SCLK_SFC 58 -#define SCLK_SDMMC 59 -#define SCLK_OTG_ADP 60 -#define SCLK_GMAC_SRC 61 -#define SCLK_GMAC 62 -#define SCLK_GMAC_RX_TX 63 -#define SCLK_MAC_REF 64 -#define SCLK_MAC_REFOUT 65 -#define SCLK_MAC_OUT 66 -#define SCLK_SDMMC_DRV 67 -#define SCLK_SDMMC_SAMPLE 68 -#define SCLK_SDIO_DRV 69 -#define SCLK_SDIO_SAMPLE 70 -#define SCLK_EMMC_DRV 71 -#define SCLK_EMMC_SAMPLE 72 -#define SCLK_GPU 73 -#define SCLK_PVTM 74 -#define SCLK_CORE_VPU 75 -#define SCLK_GMAC_RMII 76 -#define SCLK_UART2_SRC 77 -#define SCLK_NANDC_DIV 78 -#define SCLK_NANDC_DIV50 79 -#define SCLK_SDIO_DIV 80 -#define SCLK_SDIO_DIV50 81 -#define SCLK_EMMC_DIV 82 -#define SCLK_EMMC_DIV50 83 - -/* dclk gates */ -#define DCLK_VOPB 150 -#define DCLK_VOPL 151 - -/* aclk gates */ -#define ACLK_GPU 170 -#define ACLK_BUS_PRE 171 -#define ACLK_CRYPTO 172 -#define ACLK_VI_PRE 173 -#define ACLK_VO_PRE 174 -#define ACLK_VPU 175 -#define ACLK_PERI_PRE 176 -#define ACLK_GMAC 178 -#define ACLK_CIF 179 -#define ACLK_ISP 180 -#define ACLK_VOPB 181 -#define ACLK_VOPL 182 -#define ACLK_RGA 183 -#define ACLK_GIC 184 -#define ACLK_DCF 186 -#define ACLK_DMAC 187 - -/* hclk gates */ -#define HCLK_BUS_PRE 240 -#define HCLK_CRYPTO 241 -#define HCLK_VI_PRE 242 -#define HCLK_VO_PRE 243 -#define HCLK_VPU 244 -#define HCLK_PERI_PRE 245 -#define HCLK_MMC_NAND 246 -#define HCLK_SDMMC 247 -#define HCLK_USB 248 -#define HCLK_CIF 249 -#define HCLK_ISP 250 -#define HCLK_VOPB 251 -#define HCLK_VOPL 252 -#define HCLK_RGA 253 -#define HCLK_NANDC 254 -#define HCLK_SDIO 255 -#define HCLK_EMMC 256 -#define HCLK_SFC 257 -#define HCLK_OTG 258 -#define HCLK_HOST 259 -#define HCLK_HOST_ARB 260 -#define HCLK_PDM 261 -#define HCLK_I2S0 262 -#define HCLK_I2S1 263 -#define HCLK_I2S2 264 - -/* pclk gates */ -#define PCLK_BUS_PRE 320 -#define PCLK_DDR 321 -#define PCLK_VO_PRE 322 -#define PCLK_GMAC 323 -#define PCLK_MIPI_DSI 324 -#define PCLK_MIPIDSIPHY 325 -#define PCLK_MIPICSIPHY 326 -#define PCLK_USB_GRF 327 -#define PCLK_DCF 328 -#define PCLK_UART1 329 -#define PCLK_UART2 330 -#define PCLK_UART3 331 -#define PCLK_UART4 332 -#define PCLK_UART5 333 -#define PCLK_I2C0 334 -#define PCLK_I2C1 335 -#define PCLK_I2C2 336 -#define PCLK_I2C3 337 -#define PCLK_I2C4 338 -#define PCLK_PWM0 339 -#define PCLK_PWM1 340 -#define PCLK_SPI0 341 -#define PCLK_SPI1 342 -#define PCLK_SARADC 343 -#define PCLK_TSADC 344 -#define PCLK_TIMER 345 -#define PCLK_OTP_NS 346 -#define PCLK_WDT_NS 347 -#define PCLK_GPIO1 348 -#define PCLK_GPIO2 349 -#define PCLK_GPIO3 350 -#define PCLK_ISP 351 -#define PCLK_CIF 352 -#define PCLK_OTP_PHY 353 - -#define CLK_NR_CLKS (PCLK_OTP_PHY + 1) - -/* pmu-clocks indices */ - -#define PLL_GPLL 1 - -#define SCLK_RTC32K_PMU 4 -#define SCLK_WIFI_PMU 5 -#define SCLK_UART0_PMU 6 -#define SCLK_PVTM_PMU 7 -#define PCLK_PMU_PRE 8 -#define SCLK_REF24M_PMU 9 -#define SCLK_USBPHY_REF 10 -#define SCLK_MIPIDSIPHY_REF 11 - -#define XIN24M_DIV 12 - -#define PCLK_GPIO0_PMU 20 -#define PCLK_UART0_PMU 21 - -#define CLKPMU_NR_CLKS (PCLK_UART0_PMU + 1) - -/* soft-reset indices */ -#define SRST_CORE0_PO 0 -#define SRST_CORE1_PO 1 -#define SRST_CORE2_PO 2 -#define SRST_CORE3_PO 3 -#define SRST_CORE0 4 -#define SRST_CORE1 5 -#define SRST_CORE2 6 -#define SRST_CORE3 7 -#define SRST_CORE0_DBG 8 -#define SRST_CORE1_DBG 9 -#define SRST_CORE2_DBG 10 -#define SRST_CORE3_DBG 11 -#define SRST_TOPDBG 12 -#define SRST_CORE_NOC 13 -#define SRST_STRC_A 14 -#define SRST_L2C 15 - -#define SRST_DAP 16 -#define SRST_CORE_PVTM 17 -#define SRST_GPU 18 -#define SRST_GPU_NIU 19 -#define SRST_UPCTL2 20 -#define SRST_UPCTL2_A 21 -#define SRST_UPCTL2_P 22 -#define SRST_MSCH 23 -#define SRST_MSCH_P 24 -#define SRST_DDRMON_P 25 -#define SRST_DDRSTDBY_P 26 -#define SRST_DDRSTDBY 27 -#define SRST_DDRGRF_p 28 -#define SRST_AXI_SPLIT_A 29 -#define SRST_AXI_CMD_A 30 -#define SRST_AXI_CMD_P 31 - -#define SRST_DDRPHY 32 -#define SRST_DDRPHYDIV 33 -#define SRST_DDRPHY_P 34 -#define SRST_VPU_A 36 -#define SRST_VPU_NIU_A 37 -#define SRST_VPU_H 38 -#define SRST_VPU_NIU_H 39 -#define SRST_VI_NIU_A 40 -#define SRST_VI_NIU_H 41 -#define SRST_ISP_H 42 -#define SRST_ISP 43 -#define SRST_CIF_A 44 -#define SRST_CIF_H 45 -#define SRST_CIF_PCLKIN 46 -#define SRST_MIPICSIPHY_P 47 - -#define SRST_VO_NIU_A 48 -#define SRST_VO_NIU_H 49 -#define SRST_VO_NIU_P 50 -#define SRST_VOPB_A 51 -#define SRST_VOPB_H 52 -#define SRST_VOPB 53 -#define SRST_PWM_VOPB 54 -#define SRST_VOPL_A 55 -#define SRST_VOPL_H 56 -#define SRST_VOPL 57 -#define SRST_RGA_A 58 -#define SRST_RGA_H 59 -#define SRST_RGA 60 -#define SRST_MIPIDSI_HOST_P 61 -#define SRST_MIPIDSIPHY_P 62 -#define SRST_VPU_CORE 63 - -#define SRST_PERI_NIU_A 64 -#define SRST_USB_NIU_H 65 -#define SRST_USB2OTG_H 66 -#define SRST_USB2OTG 67 -#define SRST_USB2OTG_ADP 68 -#define SRST_USB2HOST_H 69 -#define SRST_USB2HOST_ARB_H 70 -#define SRST_USB2HOST_AUX_H 71 -#define SRST_USB2HOST_EHCI 72 -#define SRST_USB2HOST 73 -#define SRST_USBPHYPOR 74 -#define SRST_USBPHY_OTG_PORT 75 -#define SRST_USBPHY_HOST_PORT 76 -#define SRST_USBPHY_GRF 77 -#define SRST_CPU_BOOST_P 78 -#define SRST_CPU_BOOST 79 - -#define SRST_MMC_NAND_NIU_H 80 -#define SRST_SDIO_H 81 -#define SRST_EMMC_H 82 -#define SRST_SFC_H 83 -#define SRST_SFC 84 -#define SRST_SDCARD_NIU_H 85 -#define SRST_SDMMC_H 86 -#define SRST_NANDC_H 89 -#define SRST_NANDC 90 -#define SRST_GMAC_NIU_A 92 -#define SRST_GMAC_NIU_P 93 -#define SRST_GMAC_A 94 - -#define SRST_PMU_NIU_P 96 -#define SRST_PMU_SGRF_P 97 -#define SRST_PMU_GRF_P 98 -#define SRST_PMU 99 -#define SRST_PMU_MEM_P 100 -#define SRST_PMU_GPIO0_P 101 -#define SRST_PMU_UART0_P 102 -#define SRST_PMU_CRU_P 103 -#define SRST_PMU_PVTM 104 -#define SRST_PMU_UART 105 -#define SRST_PMU_NIU_H 106 -#define SRST_PMU_DDR_FAIL_SAVE 107 -#define SRST_PMU_CORE_PERF_A 108 -#define SRST_PMU_CORE_GRF_P 109 -#define SRST_PMU_GPU_PERF_A 110 -#define SRST_PMU_GPU_GRF_P 111 - -#define SRST_CRYPTO_NIU_A 112 -#define SRST_CRYPTO_NIU_H 113 -#define SRST_CRYPTO_A 114 -#define SRST_CRYPTO_H 115 -#define SRST_CRYPTO 116 -#define SRST_CRYPTO_APK 117 -#define SRST_BUS_NIU_H 120 -#define SRST_USB_NIU_P 121 -#define SRST_BUS_TOP_NIU_P 122 -#define SRST_INTMEM_A 123 -#define SRST_GIC_A 124 -#define SRST_ROM_H 126 -#define SRST_DCF_A 127 - -#define SRST_DCF_P 128 -#define SRST_PDM_H 129 -#define SRST_PDM 130 -#define SRST_I2S0_H 131 -#define SRST_I2S0_TX 132 -#define SRST_I2S1_H 133 -#define SRST_I2S1 134 -#define SRST_I2S2_H 135 -#define SRST_I2S2 136 -#define SRST_UART1_P 137 -#define SRST_UART1 138 -#define SRST_UART2_P 139 -#define SRST_UART2 140 -#define SRST_UART3_P 141 -#define SRST_UART3 142 -#define SRST_UART4_P 143 - -#define SRST_UART4 144 -#define SRST_UART5_P 145 -#define SRST_UART5 146 -#define SRST_I2C0_P 147 -#define SRST_I2C0 148 -#define SRST_I2C1_P 149 -#define SRST_I2C1 150 -#define SRST_I2C2_P 151 -#define SRST_I2C2 152 -#define SRST_I2C3_P 153 -#define SRST_I2C3 154 -#define SRST_PWM0_P 157 -#define SRST_PWM0 158 -#define SRST_PWM1_P 159 - -#define SRST_PWM1 160 -#define SRST_SPI0_P 161 -#define SRST_SPI0 162 -#define SRST_SPI1_P 163 -#define SRST_SPI1 164 -#define SRST_SARADC_P 165 -#define SRST_SARADC 166 -#define SRST_TSADC_P 167 -#define SRST_TSADC 168 -#define SRST_TIMER_P 169 -#define SRST_TIMER0 170 -#define SRST_TIMER1 171 -#define SRST_TIMER2 172 -#define SRST_TIMER3 173 -#define SRST_TIMER4 174 -#define SRST_TIMER5 175 - -#define SRST_OTP_NS_P 176 -#define SRST_OTP_NS_SBPI 177 -#define SRST_OTP_NS_USR 178 -#define SRST_OTP_PHY_P 179 -#define SRST_OTP_PHY 180 -#define SRST_WDT_NS_P 181 -#define SRST_GPIO1_P 182 -#define SRST_GPIO2_P 183 -#define SRST_GPIO3_P 184 -#define SRST_SGRF_P 185 -#define SRST_GRF_P 186 -#define SRST_I2S0_RX 191 - -#endif diff --git a/include/dt-bindings/clock/rockchip,rk808.h b/include/dt-bindings/clock/rockchip,rk808.h deleted file mode 100644 index 1a873432f96..00000000000 --- a/include/dt-bindings/clock/rockchip,rk808.h +++ /dev/null @@ -1,11 +0,0 @@ -/* - * This header provides constants clk index RK808 pmic clkout - */ -#ifndef _CLK_ROCKCHIP_RK808 -#define _CLK_ROCKCHIP_RK808 - -/* CLOCKOUT index */ -#define RK808_CLKOUT0 0 -#define RK808_CLKOUT1 1 - -#endif diff --git a/include/dt-bindings/pinctrl/sandbox-pinmux.h b/include/dt-bindings/pinctrl/sandbox-pinmux.h index 891af072e52..21c5a1762ab 100644 --- a/include/dt-bindings/pinctrl/sandbox-pinmux.h +++ b/include/dt-bindings/pinctrl/sandbox-pinmux.h @@ -13,6 +13,7 @@ #define SANDBOX_PINMUX_GPIO 4 #define SANDBOX_PINMUX_CS 5 #define SANDBOX_PINMUX_PWM 6 +#define SANDBOX_PINMUX_ONEWIRE 7 #define SANDBOX_PINMUX(pin, func) ((func) << 16 | (pin)) diff --git a/include/dt-bindings/power/px30-power.h b/include/dt-bindings/power/px30-power.h deleted file mode 100644 index 30917a99ad2..00000000000 --- a/include/dt-bindings/power/px30-power.h +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_BINDINGS_POWER_PX30_POWER_H__ -#define __DT_BINDINGS_POWER_PX30_POWER_H__ - -/* VD_CORE */ -#define PX30_PD_A35_0 0 -#define PX30_PD_A35_1 1 -#define PX30_PD_A35_2 2 -#define PX30_PD_A35_3 3 -#define PX30_PD_SCU 4 - -/* VD_LOGIC */ -#define PX30_PD_USB 5 -#define PX30_PD_DDR 6 -#define PX30_PD_SDCARD 7 -#define PX30_PD_CRYPTO 8 -#define PX30_PD_GMAC 9 -#define PX30_PD_MMC_NAND 10 -#define PX30_PD_VPU 11 -#define PX30_PD_VO 12 -#define PX30_PD_VI 13 -#define PX30_PD_GPU 14 - -/* VD_PMU */ -#define PX30_PD_PMU 15 - -#endif diff --git a/include/dt-bindings/soc/rockchip,boot-mode.h b/include/dt-bindings/soc/rockchip,boot-mode.h deleted file mode 100644 index 4b0914c0989..00000000000 --- a/include/dt-bindings/soc/rockchip,boot-mode.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ROCKCHIP_BOOT_MODE_H -#define __ROCKCHIP_BOOT_MODE_H - -/*high 24 bits is tag, low 8 bits is type*/ -#define REBOOT_FLAG 0x5242C300 -/* normal boot */ -#define BOOT_NORMAL (REBOOT_FLAG + 0) -/* enter bootloader rockusb mode */ -#define BOOT_BL_DOWNLOAD (REBOOT_FLAG + 1) -/* enter recovery */ -#define BOOT_RECOVERY (REBOOT_FLAG + 3) - /* enter fastboot mode */ -#define BOOT_FASTBOOT (REBOOT_FLAG + 9) - -#endif diff --git a/include/dt-bindings/soc/rockchip,vop2.h b/include/dt-bindings/soc/rockchip,vop2.h deleted file mode 100644 index 668f199df9f..00000000000 --- a/include/dt-bindings/soc/rockchip,vop2.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ - -#ifndef __DT_BINDINGS_ROCKCHIP_VOP2_H -#define __DT_BINDINGS_ROCKCHIP_VOP2_H - -#define ROCKCHIP_VOP2_EP_RGB0 1 -#define ROCKCHIP_VOP2_EP_HDMI0 2 -#define ROCKCHIP_VOP2_EP_EDP0 3 -#define ROCKCHIP_VOP2_EP_MIPI0 4 -#define ROCKCHIP_VOP2_EP_LVDS0 5 -#define ROCKCHIP_VOP2_EP_MIPI1 6 -#define ROCKCHIP_VOP2_EP_LVDS1 7 -#define ROCKCHIP_VOP2_EP_HDMI1 8 -#define ROCKCHIP_VOP2_EP_EDP1 9 -#define ROCKCHIP_VOP2_EP_DP0 10 -#define ROCKCHIP_VOP2_EP_DP1 11 - -#endif /* __DT_BINDINGS_ROCKCHIP_VOP2_H */ |