diff options
Diffstat (limited to 'include/dt-bindings')
| -rw-r--r-- | include/dt-bindings/clock/stm32fx-clock.h | 9 | ||||
| -rw-r--r-- | include/dt-bindings/mfd/st,stpmic1.h | 4 | ||||
| -rw-r--r-- | include/dt-bindings/mfd/stm32f7-rcc.h | 1 | ||||
| -rw-r--r-- | include/dt-bindings/mfd/stm32h7-rcc.h | 2 |
4 files changed, 12 insertions, 4 deletions
diff --git a/include/dt-bindings/clock/stm32fx-clock.h b/include/dt-bindings/clock/stm32fx-clock.h index 58d8b515be5..1cc89c54857 100644 --- a/include/dt-bindings/clock/stm32fx-clock.h +++ b/include/dt-bindings/clock/stm32fx-clock.h @@ -1,9 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * stm32fx-clock.h * * Copyright (C) 2016 STMicroelectronics * Author: Gabriel Fernandez for STMicroelectronics. - * License terms: GNU General Public License (GPL), version 2 */ /* @@ -54,7 +54,10 @@ #define CLK_I2C3 28 #define CLK_I2C4 29 #define CLK_LPTIMER 30 - -#define END_PRIMARY_CLK_F7 31 +#define CLK_PLL_SRC 31 +#define CLK_DFSDM1 32 +#define CLK_ADFSDM1 33 +#define CLK_F769_DSI 34 +#define END_PRIMARY_CLK_F7 35 #endif diff --git a/include/dt-bindings/mfd/st,stpmic1.h b/include/dt-bindings/mfd/st,stpmic1.h index b2d6c83462a..321cd08797d 100644 --- a/include/dt-bindings/mfd/st,stpmic1.h +++ b/include/dt-bindings/mfd/st,stpmic1.h @@ -43,4 +43,8 @@ #define IT_SWIN_F 30 #define IT_SWIN_R 31 +/* BUCK MODES definitions */ +#define STPMIC1_BUCK_MODE_NORMAL 0 +#define STPMIC1_BUCK_MODE_LP 2 + #endif /* __DT_BINDINGS_STPMIC1_H__ */ diff --git a/include/dt-bindings/mfd/stm32f7-rcc.h b/include/dt-bindings/mfd/stm32f7-rcc.h index c9087f5f3da..ba5cb7456ee 100644 --- a/include/dt-bindings/mfd/stm32f7-rcc.h +++ b/include/dt-bindings/mfd/stm32f7-rcc.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* * This header provides constants for the STM32F7 RCC IP */ diff --git a/include/dt-bindings/mfd/stm32h7-rcc.h b/include/dt-bindings/mfd/stm32h7-rcc.h index b96b3c3ac1a..06e8476bf08 100644 --- a/include/dt-bindings/mfd/stm32h7-rcc.h +++ b/include/dt-bindings/mfd/stm32h7-rcc.h @@ -12,6 +12,7 @@ #define STM32H7_RCC_AHB3_FMC 12 #define STM32H7_RCC_AHB3_QUADSPI 14 #define STM32H7_RCC_AHB3_SDMMC1 16 +#define STM32H7_RCC_AHB3_CPU 31 #define STM32H7_RCC_AHB3_CPU1 31 #define STM32H7_AHB3_RESET(bit) (STM32H7_RCC_AHB3_##bit + (0x7C * 8)) @@ -56,7 +57,6 @@ #define STM32H7_AHB4_RESET(bit) (STM32H7_RCC_AHB4_##bit + (0x88 * 8)) - /* APB3 */ #define STM32H7_RCC_APB3_LTDC 3 #define STM32H7_RCC_APB3_DSI 4 |