diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-ppc/8xx_immap.h | 14 | ||||
| -rw-r--r-- | include/bmp_logo.h | 2 | ||||
| -rw-r--r-- | include/common.h | 26 | ||||
| -rw-r--r-- | include/commproc.h | 20 | ||||
| -rw-r--r-- | include/configs/ADS860.h | 360 | ||||
| -rw-r--r-- | include/configs/DK1C20.h | 11 | ||||
| -rw-r--r-- | include/configs/DUET_ADS.h | 53 | ||||
| -rw-r--r-- | include/configs/FADS823.h | 12 | ||||
| -rw-r--r-- | include/configs/FADS850SAR.h | 12 | ||||
| -rw-r--r-- | include/configs/FADS860T.h | 419 | ||||
| -rw-r--r-- | include/configs/MPC86xADS.h | 388 | ||||
| -rw-r--r-- | include/configs/PPChameleonEVB.h | 51 | ||||
| -rw-r--r-- | include/cramfs/cramfs_fs.h | 70 | ||||
| -rw-r--r-- | include/jffs2/jffs2.h | 1 | ||||
| -rw-r--r-- | include/mpc8xx.h | 42 | ||||
| -rw-r--r-- | include/nios-io.h | 31 | ||||
| -rw-r--r-- | include/pcmcia.h | 4 |
17 files changed, 286 insertions, 1230 deletions
diff --git a/include/asm-ppc/8xx_immap.h b/include/asm-ppc/8xx_immap.h index 53559c01e83..469edb34f1c 100644 --- a/include/asm-ppc/8xx_immap.h +++ b/include/asm-ppc/8xx_immap.h @@ -435,7 +435,19 @@ typedef struct comm_proc { u_char res13[2]; ushort cp_pbodr; uint cp_pbdat; - u_char res14[0x18]; + + /* Port E - MPC87x/88x only. + */ + uint cp_pedir; + uint cp_pepar; + uint cp_peso; + uint cp_peodr; + uint cp_pedat; + + /* Communications Processor Timing Register - + Contains RMII Timing for the FECs on MPC87x/88x only. + */ + uint cp_cptr; /* Serial Interface and Time Slot Assignment. */ diff --git a/include/bmp_logo.h b/include/bmp_logo.h index 9c924b8592d..265f744d0e3 100644 --- a/include/bmp_logo.h +++ b/include/bmp_logo.h @@ -18,7 +18,7 @@ unsigned short bmp_logo_palette[] = { 0x0343, 0x0454, 0x0565, 0x0565, 0x0676, 0x0787, 0x0898, 0x0999, 0x0AAA, 0x0ABA, 0x0BCB, 0x0CCC, 0x0DDD, 0x0EEE, 0x0FFF, 0x0FB3, 0x0FB4, 0x0FC4, 0x0FC5, 0x0FC6, 0x0FD7, 0x0FD8, 0x0FD9, 0x0FDA, - 0x0FEA, 0x0FEB, 0x0FEC, 0x0FFD, 0x0FFE, 0x0FFF, 0x0FFF, + 0x0FEA, 0x0FEB, 0x0FEC, 0x0FFD, 0x0FFE, 0x0FFF, 0x0FFF, }; unsigned char bmp_logo_bitmap[] = { diff --git a/include/common.h b/include/common.h index 6b92548243e..32107a0942e 100644 --- a/include/common.h +++ b/include/common.h @@ -12,7 +12,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -29,7 +29,7 @@ typedef unsigned char uchar; typedef volatile unsigned long vu_long; -typedef volatile unsigned short vu_short; +typedef volatile unsigned short vu_short; typedef volatile unsigned char vu_char; #include <config.h> @@ -41,21 +41,25 @@ typedef volatile unsigned char vu_char; #if defined(CONFIG_PCI) && defined(CONFIG_440) #include <pci.h> #endif -#ifdef CONFIG_8xx +#if defined(CONFIG_8xx) #include <asm/8xx_immap.h> -#ifdef CONFIG_MPC860 -#define CONFIG_MPC86x 1 -#endif -#ifdef CONFIG_MPC860T -#define CONFIG_MPC86x 1 -#endif #if defined(CONFIG_MPC852) || defined(CONFIG_MPC852T) || \ defined(CONFIG_MPC859) || defined(CONFIG_MPC859T) || \ defined(CONFIG_MPC859DSL) || \ defined(CONFIG_MPC866) || defined(CONFIG_MPC866T) || \ defined(CONFIG_MPC866P) -#define CONFIG_MPC866_et_al 1 -#define CONFIG_MPC86x 1 +# define CONFIG_MPC866_et_al 1 +#elif defined(CONFIG_MPC870) \ + || defined(CONFIG_MPC875) \ + || defined(CONFIG_MPC880) \ + || defined(CONFIG_MPC885) +# define CONFIG_DUET 1 +#endif +#if defined(CONFIG_MPC860) \ + || defined(CONFIG_MPC860T) \ + || defined(CONFIG_MPC866_et_al) \ + || defined(CONFIG_DUET) +# define CONFIG_MPC86x 1 #endif #elif defined(CONFIG_5xx) #include <asm/5xx_immap.h> diff --git a/include/commproc.h b/include/commproc.h index 8bab5225c24..11f31e9da4d 100644 --- a/include/commproc.h +++ b/include/commproc.h @@ -716,13 +716,14 @@ typedef struct scc_enet { /*** FADS860T********************************************************/ -#if (defined(CONFIG_MPC860T) || defined(CONFIG_MPC866_et_al)) \ - && defined(CONFIG_FADS) -/* This ENET stuff is for the MPC860TFADS/MPC8xxADS with ethernet on SCC1. +#if defined(CONFIG_FADS) && defined(CONFIG_MPC86x) +/* + * This ENET stuff is for the MPC86xFADS/MPC8xxADS with ethernet on SCC1. */ #ifdef CONFIG_SCC1_ENET + #define SCC_ENET 0 -#endif /* CONFIG_SCC1_ETHERNET */ + #define PROFF_ENET PROFF_SCC1 #define CPM_CR_ENET CPM_CR_CH_SCC1 @@ -739,14 +740,17 @@ typedef struct scc_enet { #define SICR_ENET_MASK ((uint)0x000000ff) #define SICR_ENET_CLKRT ((uint)0x0000002c) -/* This ENET stuff is for the MPC860TFADS with ethernet on FEC. +#endif /* CONFIG_SCC1_ETHERNET */ + +/* + * This ENET stuff is for the MPC860TFADS/MPC86xADS/DUET with ethernet on FEC. */ #ifdef CONFIG_FEC_ENET -#define FEC_ENET /* use FEC for EThernet */ -#endif /* CONFIG_FEC_ETHERNET */ +#define FEC_ENET /* Use FEC for Ethernet */ +#endif /* CONFIG_FEC_ENET */ -#endif /* CONFIG_FADS860T */ +#endif /* CONFIG_FADS && CONFIG_MPC86x */ /*** FPS850L, FPS860L ************************************************/ diff --git a/include/configs/ADS860.h b/include/configs/ADS860.h index 1b037c9b11b..916272dce10 100644 --- a/include/configs/ADS860.h +++ b/include/configs/ADS860.h @@ -5,17 +5,14 @@ * Helmut Buchsbaum added bitvalues for BCSRx * * Copyright (c) 1998 Dan Malek (dmalek@jlc.net) + * + * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com + * + * Values common to all FADS family boards are in board/fads/fads.h */ -/* ------------------------------------------------------------------------- */ - -#ifndef _CONFIG_ADS860_H -#define _CONFIG_ADS860_H - -/* - * High Level Configuration Options - * (easy to change) - */ +#ifndef __CONFIG_H +#define __CONFIG_H /* Board type */ #define CONFIG_ADS 1 /* Old Motorola MPC821/860ADS */ @@ -38,351 +35,20 @@ #define CFG_8XX_FACT 12 /* Multiply by 12 */ #endif -#define CONFIG_8xx_GCLK_FREQ ((CFG_8XX_XIN) * (CFG_8XX_FACT)) - -#define CONFIG_DRAM_50MHZ 1 - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "dhcp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \ - "bootm" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_DHCP \ - | CFG_CMD_IMMAP \ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_DHCP \ + | CFG_CMD_IMMAP \ | CFG_CMD_PCMCIA \ - | CFG_CMD_PING \ + | CFG_CMD_PING \ ) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -/* - * Miscellaneous configurable options - */ -#undef CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=>" /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15 MB in DRAM */ +#define CONFIG_DRAM_50MHZ 1 -#define CFG_LOAD_ADDR 0x00100000 +#include "fads.h" -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFF000000 -#define CFG_IMMR_SIZE ((uint)(64 * 1024)) - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_FLASH_BASE TEXT_BASE -#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */ - -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 16 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#undef CFG_ENV_IS_IN_NVRAM -#undef CFG_ENV_IS_IN_EEPROM -#define CFG_ENV_IS_IN_FLASH 1 - -#define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sector total size */ -#define CFG_ENV_OFFSET CFG_ENV_SECT_SIZE -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment */ - -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MONITOR_LEN (256 << 10) /* Reserve one flash sector - (256 KB) for monitor */ -#define CFG_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */ - -/* the other CS:s are determined by looking at parameters in BCSRx */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * I2C configuration - */ -#if (CONFIG_COMMANDS & CFG_CMD_I2C) -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address defaults */ -#define CFG_I2C_SLAVE 0x7F -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * set the PLL, the low-power modes and the reset control (15-29) - */ #define CFG_PLPRCR (((CFG_8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR (SCCR_TBS | SCCR_COM00 | SCCR_DFSYNC00 | \ - SCCR_DFBRG00 | SCCR_DFNL000 | SCCR_DFNH000 | \ - SCCR_DFLCD000 | SCCR_DFALCD00) - - - /*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* Because of the way the 860 starts up and assigns CS0 the -* entire address space, we have to set the memory controller -* differently. Normally, you write the option register -* first, and then enable the chip select by writing the -* base register. For CS0, you must write the base register -* first, followed by the option register. -*/ - -/* - * Init Memory Controller: - * - * BR0 and OR0 (FLASH) - * BR1 and OR1 (BCSR) - */ -/* the other CS:s are determined by looking at parameters in BCSRx */ - -#define BCSR_ADDR ((uint) 0xff010000) - -#define CFG_PRELIM_OR_AM 0xff800000 /* OR addr mask */ - -/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */ -#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX) - -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) /* 8 Mbyte until detected */ -#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_V) - -/* BCSRx - Board Control and Status Registers */ -#define CFG_OR1_PRELIM 0xffff8110 /* 64Kbyte address space */ -#define CFG_BR1_PRELIM ((BCSR_ADDR) | BR_V ) - -/* - * Memory Periodic Timer Prescaler - */ - -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - - -/* values according to the manual */ -#define BCSR0 (BCSR_ADDR + 0x00) -#define BCSR1 (BCSR_ADDR + 0x04) -#define BCSR2 (BCSR_ADDR + 0x08) -#define BCSR3 (BCSR_ADDR + 0x0c) - - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#ifdef CONFIG_MPC860 -#define PCMCIA_SLOT_A 1 -#endif - -#define CFG_PCMCIA_MEM_ADDR (0xE0000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_IDE_8xx_DIRECT 1 /* PCMCIA interface required */ -#undef CONFIG_IDE_LED /* LED for ide supported */ -#define CONFIG_IDE_RESET 1 /* reset for ide supported */ - -#define CFG_IDE_MAXBUS 1 /* max. 2 IDE busses */ -#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ - -#define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */ #define CFG_PC_IDE_RESET ((ushort)0x0008) /* PC 12 */ -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ -#define CFG_ATA_REG_OFFSET 0x0080 /* Offset for normal register accesses */ -#define CFG_ATA_ALT_OFFSET 0x0100 /* Offset for alternate registers */ - -#define CONFIG_DISK_SPINUP_TIME 1000000 -#undef CONFIG_DISK_SPINUP_TIME /* usinī Compact Flash */ - -/* (F)ADS bitvalues by Helmut Buchsbaum - * see MPC8xxADS User's Manual for a proper description - * of the following structures - */ - -#define BCSR0_ERB ((uint)0x80000000) -#define BCSR0_IP ((uint)0x40000000) -#define BCSR0_BDIS ((uint)0x10000000) -#define BCSR0_BPS_MASK ((uint)0x0C000000) -#define BCSR0_ISB_MASK ((uint)0x01800000) -#define BCSR0_DBGC_MASK ((uint)0x00600000) -#define BCSR0_DBPC_MASK ((uint)0x00180000) -#define BCSR0_EBDF_MASK ((uint)0x00060000) - -#define BCSR1_FLASH_EN ((uint)0x80000000) -#define BCSR1_DRAM_EN ((uint)0x40000000) -#define BCSR1_ETHEN ((uint)0x20000000) -#define BCSR1_IRDEN ((uint)0x10000000) -#define BCSR1_FLASH_CFG_EN ((uint)0x08000000) -#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000) -#define BCSR1_BCSR_EN ((uint)0x02000000) -#define BCSR1_RS232EN_1 ((uint)0x01000000) -#define BCSR1_PCCEN ((uint)0x00800000) -#define BCSR1_PCCVCC0 ((uint)0x00400000) -#define BCSR1_PCCVCCON BCSR1_PCCVCC0 -#define BCSR1_PCCVPP_MASK ((uint)0x00300000) -#define BCSR1_DRAM_HALF_WORD ((uint)0x00080000) -#define BCSR1_RS232EN_2 ((uint)0x00040000) -#define BCSR1_SDRAM_EN ((uint)0x00020000) -#define BCSR1_PCCVCC1 ((uint)0x00010000) - -#define BCSR2_FLASH_PD_MASK ((uint)0xF0000000) -#define BCSR2_DRAM_PD_MASK ((uint)0x07800000) -#define BCSR2_DRAM_PD_SHIFT (23) -#define BCSR2_EXTTOLI_MASK ((uint)0x00780000) -#define BCSR2_DBREVNR_MASK ((uint)0x00030000) - -#define BCSR3_DBID_MASK ((ushort)0x3800) -#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400) -#define BCSR3_BREVNR0 ((ushort)0x0080) -#define BCSR3_FLASH_PD_MASK ((ushort)0x0070) -#define BCSR3_BREVN1 ((ushort)0x0008) -#define BCSR3_BREVN2_MASK ((ushort)0x0003) - -/* We don't use the 8259. - */ -#define NR_8259_INTS 0 - -/* Machine type - */ -#define _MACH_8xx (_MACH_ads) - -#endif /* _CONFIG_ADS860_H */ +#endif /* __CONFIG_H */ diff --git a/include/configs/DK1C20.h b/include/configs/DK1C20.h index 2b0b176e241..0d8e4631b37 100644 --- a/include/configs/DK1C20.h +++ b/include/configs/DK1C20.h @@ -413,7 +413,7 @@ #endif /*------------------------------------------------------------------------ - * Ethernet -- needs work! + * Ethernet *----------------------------------------------------------------------*/ #if (CFG_NIOS_CPU_LAN_NUMS == 1) @@ -642,6 +642,15 @@ #endif /* CFG_NIOS_CPU_PIO_NUMS */ /*------------------------------------------------------------------------ + * ASMI - Active Serial Memory Interface. + * + * ASMI is for Cyclone devices only and only works when the configuration + * is loaded via JTAG or ASMI. Please see doc/README.dk1c20 for details. + *----------------------------------------------------------------------*/ +#define CONFIG_NIOS_ASMI /* Enable ASMI */ +#define CFG_NIOS_ASMIBASE 0x00920b00 /* ASMI base address */ + +/*------------------------------------------------------------------------ * COMMANDS *----------------------------------------------------------------------*/ #define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \ diff --git a/include/configs/DUET_ADS.h b/include/configs/DUET_ADS.h new file mode 100644 index 00000000000..8a4025797db --- /dev/null +++ b/include/configs/DUET_ADS.h @@ -0,0 +1,53 @@ +/* + * A collection of structures, addresses, and values associated with + * the Motorola DUET ADS board. Values common to all FADS family boards + * are in board/fads/fads.h + * + * Copyright (C) 2003 Arabella Software Ltd. + * Yuli Barcohen <yuli@arabellasw.com> + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* Board type */ +#define CONFIG_DUET_ADS 1 /* Duet (MPC87x/88x) ADS */ +#define CONFIG_FADS 1 /* We are FADS compatible (more or less) */ + +#define CONFIG_MPC885 1 /* MPC885 CPU (Duet family) */ + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#undef CONFIG_8xx_CONS_SMC2 +#undef CONFIG_8xx_CONS_NONE +#define CONFIG_BAUDRATE 38400 + +#define CFG_8XX_FACT 5 /* Multiply by 5 */ +#define CFG_8XX_XIN 10000000 /* 10 MHz in */ + +#define CONFIG_SDRAM_50MHZ 1 + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 14-22 + *----------------------------------------------------------------------- + * set the PLL, the low-power modes and the reset control + */ +#define CFG_PLPRCR ((CFG_8XX_FACT << PLPRCR_MFI_SHIFT) | PLPRCR_TEXPS) + +#include "fads.h" + +#define CFG_PHYDEV_ADDR (BCSR_ADDR + 0x20000) + +#define CFG_OR5_PRELIM 0xFFFF8110 /* 64Kbyte address space */ +#define CFG_BR5_PRELIM (CFG_PHYDEV_ADDR | BR_PS_8 | BR_V) + +#define BCSR5 (CFG_PHYDEV_ADDR + 0x300) + +#define BCSR5_MII2_EN 0x40 +#define BCSR5_MII2_RST 0x20 +#define BCSR5_T1_RST 0x10 +#define BCSR5_ATM155_RST 0x08 +#define BCSR5_ATM25_RST 0x04 +#define BCSR5_MII1_EN 0x02 +#define BCSR5_MII1_RST 0x01 + +#endif /* __CONFIG_H */ diff --git a/include/configs/FADS823.h b/include/configs/FADS823.h index 3b201a79108..4f3d3977a87 100644 --- a/include/configs/FADS823.h +++ b/include/configs/FADS823.h @@ -66,8 +66,6 @@ * High Level Configuration Options * (easy to change) */ -#include <mpc8xx_irq.h> - #define CONFIG_MPC823 1 #define CONFIG_MPC823FADS 1 #define CONFIG_FADS 1 @@ -433,14 +431,6 @@ #define CONFIG_DRAM_50MHZ 1 #define CONFIG_SDRAM_50MHZ -#ifdef CONFIG_MPC860T - -/* Interrupt level assignments. -*/ -#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */ - -#endif /* CONFIG_MPC860T */ - /* We don't use the 8259. */ #define NR_8259_INTS 0 @@ -468,4 +458,6 @@ #define PCMCIA_SLOT_A 1 #endif +#define CFG_DAUGHTERBOARD + #endif /* __CONFIG_H */ diff --git a/include/configs/FADS850SAR.h b/include/configs/FADS850SAR.h index 3d04ef0dd97..9e292ae0eb3 100644 --- a/include/configs/FADS850SAR.h +++ b/include/configs/FADS850SAR.h @@ -30,8 +30,6 @@ * High Level Configuration Options * (easy to change) */ -#include <mpc8xx_irq.h> - #define CONFIG_MPC850 1 #define CONFIG_MPC850SAR 1 #define CONFIG_FADS 1 @@ -393,14 +391,6 @@ #define CONFIG_DRAM_50MHZ 1 #define CONFIG_SDRAM_50MHZ -#ifdef CONFIG_MPC860T - -/* Interrupt level assignments. -*/ -#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */ - -#endif /* CONFIG_MPC860T */ - /* We don't use the 8259. */ #define NR_8259_INTS 0 @@ -420,4 +410,6 @@ #define PCMCIA_SLOT_A 1 #endif +#define CFG_DAUGHTERBOARD + #endif /* __CONFIG_H */ diff --git a/include/configs/FADS860T.h b/include/configs/FADS860T.h index 114603c6270..e57571bf3ad 100644 --- a/include/configs/FADS860T.h +++ b/include/configs/FADS860T.h @@ -5,32 +5,15 @@ * Helmut Buchsbaum added bitvalues for BCSRx * * Copyright (c) 1998 Dan Malek (dmalek@jlc.net) + * + * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com + * + * Values common to all FADS family boards are in board/fads/fads.h */ -/* - * 1999-nov-26: The FADS is using the following physical memorymap: - * - * ff020000 -> ff02ffff : pcmcia - * ff010000 -> ff01ffff : BCSR connected to CS1, setup by 8xxrom - * ff000000 -> ff00ffff : IMAP internal in the cpu - * fe000000 -> ffnnnnnn : flash connected to CS0, setup by 8xxrom - * 00000000 -> nnnnnnnn : sdram/dram setup by 8xxrom - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - #ifndef __CONFIG_H #define __CONFIG_H -/* - * High Level Configuration Options - * (easy to change) - */ - /* board type */ #define CONFIG_FADS 1 /* old/new FADS + new ADS */ @@ -51,403 +34,25 @@ # define CFG_8XX_XIN 5000000 /* 5 MHz in */ #endif -#define MPC8XX_HZ ((CFG_8XX_XIN) * (CFG_8XX_FACT)) - -/* should ALWAYS define this, measure_gclk in speed.c is unreliable */ -/* in general, we always know this for FADS+new ADS anyway */ -#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ - -#if 1 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \ - "bootm" - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* ATA / IDE and partition support */ -#define CONFIG_MAC_PARTITION 1 -#define CONFIG_DOS_PARTITION 1 -#define CONFIG_ISO_PARTITION 1 -#undef CONFIG_ATAPI -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -/* choose SCC1 ethernet (10BASET on motherboard) - * or FEC ethernet (10/100 on daughterboard) - */ -#if 0 -#define CONFIG_SCC1_ENET 1 /* use SCC1 ethernet */ -#undef CONFIG_FEC_ENET /* disable FEC ethernet */ -#else /* all 86x cores have FECs, if in doubt, use it */ -#undef CONFIG_SCC1_ENET /* disable SCC1 ethernet */ -#define CONFIG_FEC_ENET 1 /* use FEC ethernet */ -#define CFG_DISCOVER_PHY -#endif -#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET) -#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured -#endif - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -/* - * Miscellaneous configurable options - */ -#undef CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=>" /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0100000 /* memtest works on */ -#if (CFG_SDRAM_SIZE) -#define CFG_MEMTEST_END CFG_SDRAM_SIZE /* 1 ... SDRAM_SIZE */ -#else -#define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */ -#endif - -#define CFG_LOAD_ADDR 0x00100000 - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*---------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFF000000 -#define CFG_IMMR_SIZE ((uint)(64 * 1024)) - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#ifdef CONFIG_FADS -# define CFG_SDRAM_SIZE 0x00400000 /* 4 meg */ -#else /* !CONFIG_FADS */ /* old ADS */ -# define CFG_SDRAM_SIZE 0x00000000 /* NO SDRAM */ -#endif - -#define CFG_FLASH_BASE TEXT_BASE - -#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */ - -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 16 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x00040000 -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -#define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sector total size */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * set the PLL, the low-power modes and the reset control (15-29) - */ -#define CFG_PLPRCR (((CFG_8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ - PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR (SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00) - - /*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* Because of the way the 860 starts up and assigns CS0 the -* entire address space, we have to set the memory controller -* differently. Normally, you write the option register -* first, and then enable the chip select by writing the -* base register. For CS0, you must write the base register -* first, followed by the option register. -*/ - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ -/* the other CS:s are determined by looking at parameters in BCSRx */ - -#define BCSR_ADDR ((uint) 0xFF010000) -#define BCSR_SIZE ((uint)(64 * 1024)) +#define CONFIG_DRAM_50MHZ 1 +#define CONFIG_SDRAM_50MHZ 1 -#define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask */ +#include "fads.h" -/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */ -#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX) +#define CFG_PLPRCR (((CFG_8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ + PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) #ifdef USE_REAL_FLASH_VALUES /* * These values fit our FADS860T ... * The "default" behaviour with 1Mbyte initial doesn't work for us! */ +#undef CFG_OR0_PRELIM +#undef CFG_BR0_PRELIM #define CFG_OR0_PRELIM 0x0FFC00D34 /* Real values for the board */ #define CFG_BR0_PRELIM 0x02800001 /* Real values for the board */ -#else -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) /* 8 Mbyte until detected */ -#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BR_BA_MSK) | BR_V ) -#endif - -/* BCSRx - Board Control and Status Registers */ -#define CFG_OR1_PRELIM 0xffff8110 /* 64Kbyte address space */ -#define CFG_BR1_PRELIM ((BCSR_ADDR) | BR_V ) - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - - -/* values according to the manual */ - - -#define PCMCIA_MEM_ADDR ((uint)0xff020000) -#define PCMCIA_MEM_SIZE ((uint)(64 * 1024)) - -#define BCSR0 ((uint) (BCSR_ADDR + 0x00)) -#define BCSR1 ((uint) (BCSR_ADDR + 0x04)) -#define BCSR2 ((uint) (BCSR_ADDR + 0x08)) -#define BCSR3 ((uint) (BCSR_ADDR + 0x0c)) -#define BCSR4 ((uint) (BCSR_ADDR + 0x10)) - -/* FADS bitvalues by Helmut Buchsbaum - * see MPC8xxADS User's Manual for a proper description - * of the following structures - */ - -#define BCSR0_ERB ((uint)0x80000000) -#define BCSR0_IP ((uint)0x40000000) -#define BCSR0_BDIS ((uint)0x10000000) -#define BCSR0_BPS_MASK ((uint)0x0C000000) -#define BCSR0_ISB_MASK ((uint)0x01800000) -#define BCSR0_DBGC_MASK ((uint)0x00600000) -#define BCSR0_DBPC_MASK ((uint)0x00180000) -#define BCSR0_EBDF_MASK ((uint)0x00060000) - -#define BCSR1_FLASH_EN ((uint)0x80000000) -#define BCSR1_DRAM_EN ((uint)0x40000000) -#define BCSR1_ETHEN ((uint)0x20000000) -#define BCSR1_IRDEN ((uint)0x10000000) -#define BCSR1_FLASH_CFG_EN ((uint)0x08000000) -#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000) -#define BCSR1_BCSR_EN ((uint)0x02000000) -#define BCSR1_RS232EN_1 ((uint)0x01000000) -#define BCSR1_PCCEN ((uint)0x00800000) -#define BCSR1_PCCVCC0 ((uint)0x00400000) -#define BCSR1_PCCVPP_MASK ((uint)0x00300000) -#define BCSR1_DRAM_HALF_WORD ((uint)0x00080000) -#define BCSR1_RS232EN_2 ((uint)0x00040000) -#define BCSR1_SDRAM_EN ((uint)0x00020000) -#define BCSR1_PCCVCC1 ((uint)0x00010000) - -#define BCSR2_FLASH_PD_MASK ((uint)0xF0000000) -#define BCSR2_DRAM_PD_MASK ((uint)0x07800000) -#define BCSR2_DRAM_PD_SHIFT (23) -#define BCSR2_EXTTOLI_MASK ((uint)0x00780000) -#define BCSR2_DBREVNR_MASK ((uint)0x00030000) - -#define BCSR3_DBID_MASK ((ushort)0x3800) -#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400) -#define BCSR3_BREVNR0 ((ushort)0x0080) -#define BCSR3_FLASH_PD_MASK ((ushort)0x0070) -#define BCSR3_BREVN1 ((ushort)0x0008) -#define BCSR3_BREVN2_MASK ((ushort)0x0003) - -#define BCSR4_ETHLOOP ((uint)0x80000000) -#define BCSR4_TFPLDL ((uint)0x40000000) -#define BCSR4_TPSQEL ((uint)0x20000000) -#define BCSR4_SIGNAL_LAMP ((uint)0x10000000) -#ifdef CONFIG_MPC823 -#define BCSR4_USB_EN ((uint)0x08000000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860SAR -#define BCSR4_UTOPIA_EN ((uint)0x08000000) -#endif /* CONFIG_MPC860SAR */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETH_EN ((uint)0x08000000) -#endif /* CONFIG_MPC860T */ -#ifdef CONFIG_MPC823 -#define BCSR4_USB_SPEED ((uint)0x04000000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETHCFG0 ((uint)0x04000000) -#endif /* CONFIG_MPC860T */ -#ifdef CONFIG_MPC823 -#define BCSR4_VCCO ((uint)0x02000000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETHFDE ((uint)0x02000000) -#endif /* CONFIG_MPC860T */ -#ifdef CONFIG_MPC823 -#define BCSR4_VIDEO_ON ((uint)0x00800000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC823 -#define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETHCFG1 ((uint)0x00400000) -#endif /* CONFIG_MPC860T */ -#ifdef CONFIG_MPC823 -#define BCSR4_VIDEO_RST ((uint)0x00200000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETHRST ((uint)0x00200000) -#endif /* CONFIG_MPC860T */ -#ifdef CONFIG_MPC823 -#define BCSR4_MODEM_EN ((uint)0x00100000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC823 -#define BCSR4_DATA_VOICE ((uint)0x00080000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC850 -#define BCSR4_DATA_VOICE ((uint)0x00080000) -#endif /* CONFIG_MPC850 */ - -#define CONFIG_DRAM_50MHZ 1 -#define CONFIG_SDRAM_50MHZ 1 - -/* We don't use the 8259. -*/ -#define NR_8259_INTS 0 - -/* Machine type -*/ -#define _MACH_8xx (_MACH_fads) - -#define CONFIG_DISK_SPINUP_TIME 1000000 - - -/* PCMCIA configuration */ - -#ifdef CONFIG_MPC860 -#define PCMCIA_SLOT_A 1 #endif -/*#define CFG_PCMCIA_MEM_SIZE ( 64 << 20) */ -#define CFG_PCMCIA_MEM_ADDR (0x50000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0x54000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0x58000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0x5C000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) -/* we have 8 windows, we take everything up to 60000000 */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0x0000 -/*#define CFG_ATA_ALT_OFFSET 0x0100 */ +#define CFG_DAUGHTERBOARD /* FADS has processor-specfic daughterboard */ #endif /* __CONFIG_H */ diff --git a/include/configs/MPC86xADS.h b/include/configs/MPC86xADS.h index 1eac6ef68fb..a6e26067142 100644 --- a/include/configs/MPC86xADS.h +++ b/include/configs/MPC86xADS.h @@ -3,24 +3,12 @@ * the Motorola MPC8xxADS board. Copied from the FADS config. * * Copyright (c) 1998 Dan Malek (dmalek@jlc.net) + * + * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com + * + * Values common to all FADS family boards are in board/fads/fads.h */ -/* - * 1999-nov-26: The FADS is using the following physical memorymap: - * - * ff020000 -> ff02ffff : pcmcia - * ff010000 -> ff01ffff : BCSR connected to CS1 - * ff000000 -> ff00ffff : IMAP internal in the cpu - * fe000000 -> fennnnnn : flash connected to CS0 - * 00000000 -> nnnnnnnn : sdram connected to CS4 - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - #ifndef __CONFIG_H #define __CONFIG_H @@ -33,7 +21,7 @@ #define CONFIG_MPC86xADS 1 /* new ADS */ #define CONFIG_FADS 1 /* We are FADS compatible (more or less) */ -/* new 86xADS only - pick one of these */ +/* New MPC86xADS - pick one of these */ #define CONFIG_MPC866T 1 #undef CONFIG_MPC866P #undef CONFIG_MPC859T @@ -44,374 +32,20 @@ #undef CONFIG_8xx_CONS_SMC2 #undef CONFIG_8xx_CONS_NONE #define CONFIG_BAUDRATE 38400 -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#ifdef CONFIG_MPC86xADS # define CFG_8XX_FACT 5 /* Multiply by 5 */ # define CFG_8XX_XIN 10000000 /* 10 MHz in */ -#else /* ! CONFIG_MPC86xADS */ -# if 0 /* old FADS */ -# define CFG_8XX_FACT 12 /* Multiply by 12 */ -# define CFG_8XX_XIN 4000000 /* 4 MHz in */ -# else /* new FADS */ -# define CFG_8XX_FACT 10 /* Multiply by 10 */ -# define CFG_8XX_XIN 5000000 /* 5 MHz in */ -# endif -#endif /* ! CONFIG_MPC86xADS */ - -#define MPC8XX_HZ ((CFG_8XX_XIN) * (CFG_8XX_FACT)) - -/* should ALWAYS define this, measure_gclk in speed.c is unreliable */ -/* in general, we always know this for FADS+new ADS anyway */ -#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ - -#if 1 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "dhcp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \ - "bootm" - -#undef CONFIG_WATCHDOG /* watchdog disabled */ -/* ATA / IDE and partition support */ -#define CONFIG_MAC_PARTITION 1 -#define CONFIG_DOS_PARTITION 1 -#define CONFIG_ISO_PARTITION 1 -#undef CONFIG_ATAPI -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -/* - * New MPC86xADS provides two Ethernet connectivity options: - * 10Mbit/s on SCC1 and 100Mbit/s on FEC. All new PQ1 chips - * has got FEC so FEC is the default. - */ -#undef CONFIG_SCC1_ENET /* disable SCC1 ethernet */ -#define CONFIG_FEC_ENET 1 /* use FEC ethernet */ -#ifdef CONFIG_FEC_ENET -#define CFG_DISCOVER_PHY -#endif -#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET) -#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured -#endif - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_DHCP \ - | CFG_CMD_IMMAP \ - | CFG_CMD_MII \ - | CFG_CMD_PING \ - ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -/* - * Miscellaneous configurable options - */ -#undef CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=>" /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_LOAD_ADDR 0x00100000 - -#define CFG_HZ 1000 /* decr freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFF000000 -#define CFG_IMMR_SIZE ((uint)(64 * 1024)) - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#if defined(CONFIG_MPC86xADS) /* new ADS */ -#define CFG_SDRAM_SIZE 0x00800000 /* 8 meg */ -#elif defined(CONFIG_FADS) /* old/new FADS */ -#define CFG_SDRAM_SIZE 0x00400000 /* 4 meg */ -#else /* old ADS */ -#define CFG_SDRAM_SIZE 0x00000000 /* No SDRAM */ -#endif - -#define CFG_MEMTEST_START 0x0100000 /* memtest works on */ -#if (CFG_SDRAM_SIZE) -#define CFG_MEMTEST_END CFG_SDRAM_SIZE /* 1 ... SDRAM_SIZE */ -#else -#define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */ -#endif /* CFG_SDRAM_SIZE */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_FLASH_BASE TEXT_BASE -#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */ - -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 16 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sector total size */ -#define CFG_ENV_OFFSET CFG_ENV_SECT_SIZE -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment */ - -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 KB for monitor */ -#define CFG_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif +#define CONFIG_DRAM_50MHZ 1 +#define CONFIG_SDRAM_50MHZ 1 /*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 + * PLPRCR - PLL, Low-Power, and Reset Control Register 14-22 *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state + * set the PLL, the low-power modes and the reset control */ -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * set the PLL, the low-power modes and the reset control (15-29) - */ -#define CFG_PLPRCR ((CFG_8XX_FACT << PLPRCR_MFI_SHIFT) | \ - PLPRCR_SPLSS | PLPRCR_TEXPS) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR (SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00) - - /*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* Because of the way the 860 starts up and assigns CS0 the -* entire address space, we have to set the memory controller -* differently. Normally, you write the option register -* first, and then enable the chip select by writing the -* base register. For CS0, you must write the base register -* first, followed by the option register. -*/ - -/* - * Init Memory Controller: - * - * BR0/OR0 (Flash) - * BR1/OR1 (BCSR) - */ -/* the other CS:s are determined by looking at parameters in BCSRx */ - -#define BCSR_ADDR ((uint) 0xFF010000) -#define BCSR_SIZE ((uint)(64 * 1024)) - -#define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask */ - -/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */ -#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX) - -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) /* 8 Mbyte until detected */ -#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BR_BA_MSK) | BR_V ) - -/* BCSRx - Board Control and Status Registers */ -#define CFG_OR1_PRELIM 0xffff8110 /* 64Kbyte address space */ -#define CFG_BR1_PRELIM ((BCSR_ADDR) | BR_V ) - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -/* values according to the manual */ - -#define PCMCIA_MEM_ADDR ((uint)0xff020000) -#define PCMCIA_MEM_SIZE ((uint)(64 * 1024)) - -#define BCSR0 ((uint) (BCSR_ADDR + 0x00)) -#define BCSR1 ((uint) (BCSR_ADDR + 0x04)) -#define BCSR2 ((uint) (BCSR_ADDR + 0x08)) -#define BCSR3 ((uint) (BCSR_ADDR + 0x0c)) -#define BCSR4 ((uint) (BCSR_ADDR + 0x10)) - -/* FADS bitvalues by Helmut Buchsbaum - * see MPC8xxADS User's Manual for a proper description - * of the following structures - */ - -#define BCSR0_ERB ((uint)0x80000000) -#define BCSR0_IP ((uint)0x40000000) -#define BCSR0_BDIS ((uint)0x10000000) -#define BCSR0_BPS_MASK ((uint)0x0C000000) -#define BCSR0_ISB_MASK ((uint)0x01800000) -#define BCSR0_DBGC_MASK ((uint)0x00600000) -#define BCSR0_DBPC_MASK ((uint)0x00180000) -#define BCSR0_EBDF_MASK ((uint)0x00060000) - -#define BCSR1_FLASH_EN ((uint)0x80000000) -#define BCSR1_DRAM_EN ((uint)0x40000000) -#define BCSR1_ETHEN ((uint)0x20000000) -#define BCSR1_IRDEN ((uint)0x10000000) -#define BCSR1_FLASH_CFG_EN ((uint)0x08000000) -#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000) -#define BCSR1_BCSR_EN ((uint)0x02000000) -#define BCSR1_RS232EN_1 ((uint)0x01000000) -#define BCSR1_PCCEN ((uint)0x00800000) -#define BCSR1_PCCVCC0 ((uint)0x00400000) -#define BCSR1_PCCVPP_MASK ((uint)0x00300000) -#define BCSR1_DRAM_HALF_WORD ((uint)0x00080000) -#define BCSR1_RS232EN_2 ((uint)0x00040000) -#define BCSR1_SDRAM_EN ((uint)0x00020000) -#define BCSR1_PCCVCC1 ((uint)0x00010000) - -#define BCSR2_FLASH_PD_MASK ((uint)0xF0000000) -#define BCSR2_DRAM_PD_MASK ((uint)0x07800000) -#define BCSR2_DRAM_PD_SHIFT (23) -#define BCSR2_EXTTOLI_MASK ((uint)0x00780000) -#define BCSR2_DBREVNR_MASK ((uint)0x00030000) - -#define BCSR3_DBID_MASK ((ushort)0x3800) -#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400) -#define BCSR3_BREVNR0 ((ushort)0x0080) -#define BCSR3_FLASH_PD_MASK ((ushort)0x0070) -#define BCSR3_BREVN1 ((ushort)0x0008) -#define BCSR3_BREVN2_MASK ((ushort)0x0003) - -#define BCSR4_ETHLOOP ((uint)0x80000000) -#define BCSR4_TFPLDL ((uint)0x40000000) -#define BCSR4_TPSQEL ((uint)0x20000000) -#define BCSR4_SIGNAL_LAMP ((uint)0x10000000) -#define BCSR4_FETH_EN ((uint)0x08000000) -#define BCSR4_FETHCFG0 ((uint)0x04000000) -#define BCSR4_FETHFDE ((uint)0x02000000) -#define BCSR4_FETHCFG1 ((uint)0x00400000) -#define BCSR4_FETHRST ((uint)0x00200000) - -#define CONFIG_DRAM_50MHZ 1 -#define CONFIG_SDRAM_50MHZ 1 - -/* We don't use the 8259. -*/ -#define NR_8259_INTS 0 - -/* Machine type -*/ -#define _MACH_8xx (_MACH_fads) - -#define CONFIG_DISK_SPINUP_TIME 1000000 - - -/* PCMCIA configuration */ - -#ifdef CONFIG_MPC860 -#define PCMCIA_SLOT_A 1 -#endif - -#define CFG_PCMCIA_MEM_ADDR (0x50000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0x54000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0x58000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0x5C000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) -/* we have 8 windows, we take everything up to 60000000 */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0x0000 -/*#define CFG_ATA_ALT_OFFSET 0x0100 */ +#define CFG_PLPRCR ((CFG_8XX_FACT << PLPRCR_MFI_SHIFT) | PLPRCR_TEXPS) +#include "fads.h" #endif /* __CONFIG_H */ diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h index 78ae6ba9c05..50e8a15b8d0 100644 --- a/include/configs/PPChameleonEVB.h +++ b/include/configs/PPChameleonEVB.h @@ -521,7 +521,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if 1 /* test-only */ + #define CONFIG_NO_SERIAL_EEPROM /*#undef CONFIG_NO_SERIAL_EEPROM*/ /*--------------------------------------------------------------------*/ @@ -651,16 +651,11 @@ #define PLL_PCIDIV_3 0x00000002 #define PLL_PCIDIV_4 0x00000003 -/* -!----------------------------------------------------------------------- -! PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI, -! assuming a 33.3MHz input clock to the 405EP. -!----------------------------------------------------------------------- -*/ -#define PLLMR0_133_66_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \ +/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 33.3MHz input clock to the 405EP) */ +#define PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \ PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PLLMR1_133_66_66_33 (PLL_FBKDIV_4 | \ +#define PLLMR1_133_133_33_66_33 (PLL_FBKDIV_4 | \ PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \ PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) #define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ @@ -669,27 +664,35 @@ #define PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \ PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \ PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) -#define PLLMR0_266_133_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ +#define PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PLLMR1_266_133_66_33 (PLL_FBKDIV_8 | \ +#define PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \ PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) -#if 0 /* test-only */ -#define PLLMR0_DEFAULT PLLMR0_266_133_66_33 -#define PLLMR1_DEFAULT PLLMR1_266_133_66_33 -#endif -#if 0 /* test-only */ -#define PLLMR0_DEFAULT PLLMR0_200_100_50_33 -#define PLLMR1_DEFAULT PLLMR1_200_100_50_33 -#endif -#if 1 /* test-only */ -#define PLLMR0_DEFAULT PLLMR0_133_66_66_33 -#define PLLMR1_DEFAULT PLLMR1_133_66_66_33 -#endif +#define PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ + PLL_MALDIV_1 | PLL_PCIDIV_2) +#define PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) + +#if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI) +/* Model HI */ +#define PLLMR0_DEFAULT PLLMR0_333_111_37_55_55 +#define PLLMR1_DEFAULT PLLMR1_333_111_37_55_55 +/* Model ME */ +#elif (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME) +#define PLLMR0_DEFAULT PLLMR0_266_133_33_66_33 +#define PLLMR1_DEFAULT PLLMR1_266_133_33_66_33 +#else +/* Model BA (default) */ +#define PLLMR0_DEFAULT PLLMR0_133_133_33_66_33 +#define PLLMR1_DEFAULT PLLMR1_133_133_33_66_33 #endif -#endif + +#endif /* CONFIG_NO_SERIAL_EEPROM */ #define CFG_OPB_FREQ 50000000 diff --git a/include/cramfs/cramfs_fs.h b/include/cramfs/cramfs_fs.h index 7b292c0c1ec..233370988b5 100644 --- a/include/cramfs/cramfs_fs.h +++ b/include/cramfs/cramfs_fs.h @@ -1,14 +1,6 @@ #ifndef __CRAMFS_H #define __CRAMFS_H -#ifndef __KERNEL__ - -typedef unsigned char u8; -typedef unsigned short u16; -typedef unsigned int u32; - -#endif - #define CRAMFS_MAGIC 0x28cd3d45 /* some random number */ #define CRAMFS_SIGNATURE "Compressed ROMFS" @@ -16,12 +8,12 @@ typedef unsigned int u32; * Width of various bitfields in struct cramfs_inode. * Primarily used to generate warnings in mkcramfs. */ -#define CRAMFS_MODE_WIDTH 16 -#define CRAMFS_UID_WIDTH 16 -#define CRAMFS_SIZE_WIDTH 24 -#define CRAMFS_GID_WIDTH 8 -#define CRAMFS_NAMELEN_WIDTH 6 -#define CRAMFS_OFFSET_WIDTH 26 +#define CRAMFS_MODE_WIDTH 16 +#define CRAMFS_UID_WIDTH 16 +#define CRAMFS_SIZE_WIDTH 24 +#define CRAMFS_GID_WIDTH 8 +#define CRAMFS_NAMELEN_WIDTH 6 +#define CRAMFS_OFFSET_WIDTH 26 /* * Since inode.namelen is a unsigned 6-bit number, the maximum cramfs @@ -34,8 +26,10 @@ typedef unsigned int u32; */ struct cramfs_inode { u32 mode:CRAMFS_MODE_WIDTH, uid:CRAMFS_UID_WIDTH; + /* SIZE for device files is i_rdev */ u32 size:CRAMFS_SIZE_WIDTH, gid:CRAMFS_GID_WIDTH; + /* NAMELEN is the length of the file name, divided by 4 and rounded up. (cramfs doesn't support hard links.) */ /* OFFSET: For symlinks and non-empty regular files, this @@ -90,9 +84,53 @@ struct cramfs_super { | CRAMFS_FLAG_WRONG_SIGNATURE \ | CRAMFS_FLAG_SHIFTED_ROOT_OFFSET ) +/* + * Since cramfs is little-endian, provide macros to swab the bitfields. + */ + +#ifndef __BYTE_ORDER +#if defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN) +#define __BYTE_ORDER __LITTLE_ENDIAN +#elif defined(__BIG_ENDIAN) && !defined(__LITTLE_ENDIAN) +#define __BYTE_ORDER __BIG_ENDIAN +#else +#error "unable to define __BYTE_ORDER" +#endif +#endif /* not __BYTE_ORDER */ + +#if __BYTE_ORDER == __LITTLE_ENDIAN +#define CRAMFS_16(x) (x) +#define CRAMFS_24(x) (x) +#define CRAMFS_32(x) (x) +#define CRAMFS_GET_NAMELEN(x) ((x)->namelen) +#define CRAMFS_GET_OFFSET(x) ((x)->offset) +#define CRAMFS_SET_OFFSET(x,y) ((x)->offset = (y)) +#define CRAMFS_SET_NAMELEN(x,y) ((x)->namelen = (y)) +#elif __BYTE_ORDER == __BIG_ENDIAN +#ifdef __KERNEL__ +#define CRAMFS_16(x) swab16(x) +#define CRAMFS_24(x) ((swab32(x)) >> 8) +#define CRAMFS_32(x) swab32(x) +#else /* not __KERNEL__ */ +#define CRAMFS_16(x) bswap_16(x) +#define CRAMFS_24(x) ((bswap_32(x)) >> 8) +#define CRAMFS_32(x) bswap_32(x) +#endif /* not __KERNEL__ */ +#define CRAMFS_GET_NAMELEN(x) (((u8*)(x))[8] & 0x3f) +#define CRAMFS_GET_OFFSET(x) ((CRAMFS_24(((u32*)(x))[2] & 0xffffff) << 2) |\ + ((((u32*)(x))[2] & 0xc0000000) >> 30)) +#define CRAMFS_SET_NAMELEN(x,y) (((u8*)(x))[8] = (((0x3f & (y))) | \ + (0xc0 & ((u8*)(x))[8]))) +#define CRAMFS_SET_OFFSET(x,y) (((u32*)(x))[2] = (((y) & 3) << 30) | \ + CRAMFS_24((((y) & 0x03ffffff) >> 2)) | \ + (((u32)(((u8*)(x))[8] & 0x3f)) << 24)) +#else +#error "__BYTE_ORDER must be __LITTLE_ENDIAN or __BIG_ENDIAN" +#endif + /* Uncompression interfaces to the underlying zlib */ -int cramfs_uncompress_block(void *dst, int dstlen, void *src, int srclen); +int cramfs_uncompress_block(void *dst, void *src, int srclen); int cramfs_uncompress_init(void); int cramfs_uncompress_exit(void); -#endif +#endif /* __CRAMFS_H */ diff --git a/include/jffs2/jffs2.h b/include/jffs2/jffs2.h index 4bdc525ce29..dee43a6d319 100644 --- a/include/jffs2/jffs2.h +++ b/include/jffs2/jffs2.h @@ -202,4 +202,5 @@ void dynrubin_decompress(unsigned char *data_in, unsigned char *cpage_out, long zlib_decompress(unsigned char *data_in, unsigned char *cpage_out, __u32 srclen, __u32 destlen); +char *mkmodestr(unsigned long mode, char *str); #endif /* __LINUX_JFFS2_H__ */ diff --git a/include/mpc8xx.h b/include/mpc8xx.h index 847c2b4b6b9..3976125bfea 100644 --- a/include/mpc8xx.h +++ b/include/mpc8xx.h @@ -132,10 +132,15 @@ #define RSR_ALLBITS (RSR_JTRS|RSR_DBSRS|RSR_DBHRS|RSR_CSRS|RSR_SWRS|RSR_LLRS|RSR_ESRS|RSR_EHRS) /*----------------------------------------------------------------------- + * Newer chips (MPC866 family and MPC87x/88x family) have different + * clock distribution system. Their IMMR lower half is >= 0x0800 + */ +#define MPC8xx_NEW_CLK 0x0800 + +/*----------------------------------------------------------------------- * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 */ -#ifdef CONFIG_MPC866_et_al -#define PLPRCR_MF_MSK 0xFFFF001E /* Multiplication factor + PDF bits */ +/* Newer chips (MPC866/87x/88x et al) defines */ #define PLPRCR_MFN_MSK 0xF8000000 /* Multiplication factor numerator bits */ #define PLPRCR_MFN_SHIFT 27 /* Multiplication factor numerator shift*/ #define PLPRCR_MFD_MSK 0x07C00000 /* Multiplication factor denominator bits */ @@ -144,32 +149,39 @@ #define PLPRCR_S_SHIFT 20 /* Multiplication factor integer shift */ #define PLPRCR_MFI_MSK 0x000F0000 /* Multiplication factor integer bits */ #define PLPRCR_MFI_SHIFT 16 /* Multiplication factor integer shift */ -#else + +#define PLPRCR_PDF_MSK 0x0000001E /* Predivision Factor bits */ +#define PLPRCR_PDF_SHIFT 1 /* Predivision Factor shift value */ +#define PLPRCR_DBRMO 0x00000001 /* DPLL BRM Order bit */ + +/* Multiplication factor + PDF bits */ +#define PLPRCR_MFACT_MSK (PLPRCR_MFN_MSK | \ + PLPRCR_MFD_MSK | \ + PLPRCR_S_MSK | \ + PLPRCR_MFI_MSK | \ + PLPRCR_PDF_MSK) + +/* Older chips (MPC860/862 et al) defines */ #define PLPRCR_MF_MSK 0xFFF00000 /* Multiplication factor bits */ #define PLPRCR_MF_SHIFT 20 /* Multiplication factor shift value */ -#endif + #define PLPRCR_SPLSS 0x00008000 /* SPLL Lock Status Sticky bit */ -#define PLPRCR_TEXPS 0x00004000 /* TEXP Status */ -#ifndef CONFIG_MPC866_et_al #define PLPRCR_TMIST 0x00001000 /* Timers Interrupt Status */ -#endif -#define PLPRCR_CSRC 0x00000400 /* Clock Source */ -#ifndef CONFIG_MPC866_et_al + #define PLPRCR_LPM_MSK 0x00000300 /* Low Power Mode mask */ #define PLPRCR_LPM_NORMAL 0x00000000 /* normal power management mode */ #define PLPRCR_LPM_DOZE 0x00000100 /* doze power management mode */ #define PLPRCR_LPM_SLEEP 0x00000200 /* sleep power management mode */ #define PLPRCR_LPM_DEEP_SLEEP 0x00000300 /* deep sleep power mgt mode */ #define PLPRCR_LPM_DOWN 0x00000300 /* down power management mode */ -#endif + +/* Common defines */ +#define PLPRCR_TEXPS 0x00004000 /* TEXP Status */ +#define PLPRCR_CSRC 0x00000400 /* Clock Source */ + #define PLPRCR_CSR 0x00000080 /* CheskStop Reset value */ #define PLPRCR_LOLRE 0x00000040 /* Loss Of Lock Reset Enable */ #define PLPRCR_FIOPD 0x00000020 /* Force I/O Pull Down */ -#ifdef CONFIG_MPC866_et_al -#define PLPRCR_PDF_MSK 0x0000001E /* Predivision Factor bits */ -#define PLPRCR_PDF_SHIFT 1 /* Predivision Factor shift value */ -#define PLPRCR_DBRMO 0x00000001 /* DPLL BRM Order bit */ -#endif /*----------------------------------------------------------------------- * SCCR - System Clock and reset Control Register 15-27 diff --git a/include/nios-io.h b/include/nios-io.h index 11ff78d0764..64da92abfe4 100644 --- a/include/nios-io.h +++ b/include/nios-io.h @@ -136,4 +136,35 @@ typedef volatile struct nios_spi_t { #define NIOS_SPI_IE (1 << 8) /* exception int ena */ #define NIOS_SPI_SSO (1 << 10) /* override SS_n output */ +/*------------------------------------------------------------------------ + * ASMI + *----------------------------------------------------------------------*/ +typedef volatile struct nios_asmi_t { + unsigned rxdata; /* Rx data reg */ + unsigned txdata; /* Tx data reg */ + unsigned status; /* Status reg */ + unsigned control; /* Control reg */ + unsigned reserved; + unsigned slavesel; /* Slave select */ + unsigned endofpacket; /* End-of-packet reg */ +}nios_asmi_t; + +/* status register */ +#define NIOS_ASMI_ROE (1 << 3) /* rx overrun */ +#define NIOS_ASMI_TOE (1 << 4) /* tx overrun */ +#define NIOS_ASMI_TMT (1 << 5) /* tx empty */ +#define NIOS_ASMI_TRDY (1 << 6) /* tx ready */ +#define NIOS_ASMI_RRDY (1 << 7) /* rx ready */ +#define NIOS_ASMI_E (1 << 8) /* exception */ +#define NIOS_ASMI_EOP (1 << 9) /* eop detected */ + +/* control register */ +#define NIOS_ASMI_IROE (1 << 3) /* rx overrun int ena */ +#define NIOS_ASMI_ITOE (1 << 4) /* tx overrun int ena */ +#define NIOS_ASMI_ITRDY (1 << 6) /* tx ready int ena */ +#define NIOS_ASMI_IRRDY (1 << 7) /* rx ready int ena */ +#define NIOS_ASMI_IE (1 << 8) /* exception int ena */ +#define NIOS_ASMI_IEOP (1 << 9) /* rx eop int ena */ +#define NIOS_ASMI_SSO (1 << 10) /* slave select enable */ + #endif /* __NIOSIO_H__ */ diff --git a/include/pcmcia.h b/include/pcmcia.h index 388b149e0b8..3080be3b006 100644 --- a/include/pcmcia.h +++ b/include/pcmcia.h @@ -40,10 +40,10 @@ /* The RPX series use SLOT_B */ #if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE) # define CONFIG_PCMCIA_SLOT_B -#elif defined(CONFIG_ADS) /* The ADS board use SLOT_A */ +#elif defined(CONFIG_ADS) /* The ADS board uses SLOT_A */ # define CONFIG_PCMCIA_SLOT_A #elif defined(CONFIG_FADS) /* The FADS series are a mess */ -# if defined(CONFIG_MPC86x || defined(CONFIG_MPC821) +# if defined(CONFIG_MPC86x) || defined(CONFIG_MPC821) # define CONFIG_PCMCIA_SLOT_A # else # define CONFIG_PCMCIA_SLOT_B |