diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/davinci_dvevm.h | 2 | ||||
| -rw-r--r-- | include/configs/davinci_schmoogie.h | 2 | ||||
| -rw-r--r-- | include/configs/davinci_sffsdr.h | 2 | ||||
| -rw-r--r-- | include/configs/davinci_sonata.h | 2 | ||||
| -rw-r--r-- | include/configs/kilauea.h | 13 | ||||
| -rw-r--r-- | include/configs/sequoia.h | 15 |
6 files changed, 29 insertions, 7 deletions
diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h index b43beaa03e8..fae430ba6f8 100644 --- a/include/configs/davinci_dvevm.h +++ b/include/configs/davinci_dvevm.h @@ -85,7 +85,7 @@ /*====================*/ #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 4 /* NS16550 register size */ +#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size, byteorder */ #define CONFIG_SYS_NS16550_COM1 0x01c20000 /* Base address of UART0 */ #define CONFIG_SYS_NS16550_CLK 27000000 /* Input clock to NS16550 */ #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ diff --git a/include/configs/davinci_schmoogie.h b/include/configs/davinci_schmoogie.h index 2c97a00167a..923e4777be3 100644 --- a/include/configs/davinci_schmoogie.h +++ b/include/configs/davinci_schmoogie.h @@ -52,7 +52,7 @@ /*====================*/ #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 4 /* NS16550 register size */ +#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size, byteorder */ #define CONFIG_SYS_NS16550_COM1 0x01c20000 /* Base address of UART0 */ #define CONFIG_SYS_NS16550_CLK 27000000 /* Input clock to NS16550 */ #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ diff --git a/include/configs/davinci_sffsdr.h b/include/configs/davinci_sffsdr.h index 9354c2ffb0d..73a59db8713 100644 --- a/include/configs/davinci_sffsdr.h +++ b/include/configs/davinci_sffsdr.h @@ -54,7 +54,7 @@ /* Serial Driver info */ #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 4 /* NS16550 register size */ +#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size, byteorder */ #define CONFIG_SYS_NS16550_COM1 0x01c20000 /* Base address of UART0 */ #define CONFIG_SYS_NS16550_CLK 27000000 /* Input clock to NS16550 */ #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ diff --git a/include/configs/davinci_sonata.h b/include/configs/davinci_sonata.h index 0865d0d33b8..70d2c7d0c5e 100644 --- a/include/configs/davinci_sonata.h +++ b/include/configs/davinci_sonata.h @@ -85,7 +85,7 @@ /*====================*/ #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 4 /* NS16550 register size */ +#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size, byteorder */ #define CONFIG_SYS_NS16550_COM1 0x01c20000 /* Base address of UART0 */ #define CONFIG_SYS_NS16550_CLK 27000000 /* Input clock to NS16550 */ #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h index 26cb854394a..97bac99597b 100644 --- a/include/configs/kilauea.h +++ b/include/configs/kilauea.h @@ -430,12 +430,23 @@ #define CONFIG_CMD_PCI #define CONFIG_CMD_SNTP +/* + * Don't run the memory POST on the NAND-booting version. It will + * overwrite part of the U-Boot image which is already loaded from NAND + * to SDRAM. + */ +#if defined(CONFIG_NAND_U_BOOT) +#define CONFIG_SYS_POST_MEMORY_ON 0 +#else +#define CONFIG_SYS_POST_MEMORY_ON CONFIG_SYS_POST_MEMORY +#endif + /* POST support */ #define CONFIG_POST (CONFIG_SYS_POST_CACHE | \ CONFIG_SYS_POST_CPU | \ CONFIG_SYS_POST_ETHER | \ CONFIG_SYS_POST_I2C | \ - CONFIG_SYS_POST_MEMORY | \ + CONFIG_SYS_POST_MEMORY_ON | \ CONFIG_SYS_POST_UART) /* Define here the base-addresses of the UARTs to test in POST */ diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index a3e2fcef444..fa226b28cb5 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -301,13 +301,24 @@ #define CONFIG_SYS_POST_FPU_ON 0 #endif +/* + * Don't run the memory POST on the NAND-booting version. It will + * overwrite part of the U-Boot image which is already loaded from NAND + * to SDRAM. + */ +#if defined(CONFIG_NAND_U_BOOT) +#define CONFIG_SYS_POST_MEMORY_ON 0 +#else +#define CONFIG_SYS_POST_MEMORY_ON CONFIG_SYS_POST_MEMORY +#endif + /* POST support */ #define CONFIG_POST (CONFIG_SYS_POST_CACHE | \ CONFIG_SYS_POST_CPU | \ CONFIG_SYS_POST_ETHER | \ - CONFIG_SYS_POST_FPU_ON | \ + CONFIG_SYS_POST_FPU_ON | \ CONFIG_SYS_POST_I2C | \ - CONFIG_SYS_POST_MEMORY | \ + CONFIG_SYS_POST_MEMORY_ON | \ CONFIG_SYS_POST_SPR | \ CONFIG_SYS_POST_UART) |