diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-arm/arch-ixp/ixp425.h | 56 | ||||
| -rw-r--r-- | include/asm-arm/mach-types.h | 1 | ||||
| -rw-r--r-- | include/asm-arm/u-boot.h | 4 | ||||
| -rw-r--r-- | include/configs/ixdp425.h | 32 | ||||
| -rw-r--r-- | include/configs/ixdpg425.h | 240 | ||||
| -rw-r--r-- | include/configs/pdnb3.h | 307 | ||||
| -rw-r--r-- | include/flash.h | 2 |
7 files changed, 598 insertions, 44 deletions
diff --git a/include/asm-arm/arch-ixp/ixp425.h b/include/asm-arm/arch-ixp/ixp425.h index fbe68586b3c..11dc356a928 100644 --- a/include/asm-arm/arch-ixp/ixp425.h +++ b/include/asm-arm/arch-ixp/ixp425.h @@ -73,21 +73,18 @@ * PCI Configuration space */ #define IXP425_PCI_CFG_BASE_PHYS (0xC0000000) -#define IXP425_PCI_CFG_BASE_VIRT (0xFFFD0000) #define IXP425_PCI_CFG_REGION_SIZE (0x00001000) /* * Expansion BUS Configuration registers */ #define IXP425_EXP_CFG_BASE_PHYS (0xC4000000) -#define IXP425_EXP_CFG_BASE_VIRT (0xFFFD1000) #define IXP425_EXP_CFG_REGION_SIZE (0x00001000) /* * Peripheral space */ #define IXP425_PERIPHERAL_BASE_PHYS (0xC8000000) -#define IXP425_PERIPHERAL_BASE_VIRT (0xFFFD2000) #define IXP425_PERIPHERAL_REGION_SIZE (0x0000C000) /* @@ -99,7 +96,6 @@ * Q Manager space .. not static mapped */ #define IXP425_QMGR_BASE_PHYS (0x60000000) -#define IXP425_QMGR_BASE_VIRT (0xFFFDE000) #define IXP425_QMGR_REGION_SIZE (0x00004000) /* @@ -113,10 +109,8 @@ */ #define IXP425_EXP_BUS_BASE1_PHYS (0x00000000) #define IXP425_EXP_BUS_BASE2_PHYS (0x50000000) -#define IXP425_EXP_BUS_BASE2_VIRT (0xF0000000) #define IXP425_EXP_BUS_BASE_PHYS IXP425_EXP_BUS_BASE2_PHYS -#define IXP425_EXP_BUS_BASE_VIRT IXP425_EXP_BUS_BASE2_VIRT #define IXP425_EXP_BUS_REGION_SIZE (0x08000000) #define IXP425_EXP_BUS_CSX_REGION_SIZE (0x01000000) @@ -130,20 +124,10 @@ #define IXP425_EXP_BUS_CS6_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x06000000) #define IXP425_EXP_BUS_CS7_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x07000000) -#define IXP425_EXP_BUS_CS0_BASE_VIRT (IXP425_EXP_BUS_BASE2_VIRT + 0x00000000) -#define IXP425_EXP_BUS_CS1_BASE_VIRT (IXP425_EXP_BUS_BASE2_VIRT + 0x01000000) -#define IXP425_EXP_BUS_CS2_BASE_VIRT (IXP425_EXP_BUS_BASE2_VIRT + 0x02000000) -#define IXP425_EXP_BUS_CS3_BASE_VIRT (IXP425_EXP_BUS_BASE2_VIRT + 0x03000000) -#define IXP425_EXP_BUS_CS4_BASE_VIRT (IXP425_EXP_BUS_BASE2_VIRT + 0x04000000) -#define IXP425_EXP_BUS_CS5_BASE_VIRT (IXP425_EXP_BUS_BASE2_VIRT + 0x05000000) -#define IXP425_EXP_BUS_CS6_BASE_VIRT (IXP425_EXP_BUS_BASE2_VIRT + 0x06000000) -#define IXP425_EXP_BUS_CS7_BASE_VIRT (IXP425_EXP_BUS_BASE2_VIRT + 0x07000000) - #define IXP425_FLASH_WRITABLE (0x2) #define IXP425_FLASH_DEFAULT (0xbcd23c40) #define IXP425_FLASH_WRITE (0xbcd23c42) - #define IXP425_EXP_CS0_OFFSET 0x00 #define IXP425_EXP_CS1_OFFSET 0x04 #define IXP425_EXP_CS2_OFFSET 0x08 @@ -161,7 +145,7 @@ * Expansion Bus Controller registers. */ #ifndef __ASSEMBLY__ -#define IXP425_EXP_REG(x) ((volatile u32 *)(IXP425_EXP_CFG_BASE_VIRT+(x))) +#define IXP425_EXP_REG(x) ((volatile u32 *)(IXP425_EXP_CFG_BASE_PHYS+(x))) #else #define IXP425_EXP_REG(x) (IXP425_EXP_CFG_BASE_PHYS+(x)) #endif @@ -288,7 +272,6 @@ #define MSR_DDSR (1 << 1) /* Delta Data Set Ready */ #define MSR_DCTS (1 << 0) /* Delta Clear To Send */ -#define IXP425_CONSOLE_UART_BASE_VIRT IXP425_UART1_BASE_VIRT #define IXP425_CONSOLE_UART_BASE_PHYS IXP425_UART1_BASE_PHYS /* * Peripheral Space Registers @@ -306,20 +289,6 @@ #define IXP425_EthB_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0xA000) #define IXP425_USB_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0xB000) -#define IXP425_UART1_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0x0000) -#define IXP425_UART2_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0x1000) -#define IXP425_PMU_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0x2000) -#define IXP425_INTC_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0x3000) -#define IXP425_GPIO_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0x4000) -#define IXP425_TIMER_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0x5000) -#define IXP425_NPEA_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0x6000) -#define IXP425_NPEB_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0x7000) -#define IXP425_NPEC_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0x8000) -#define IXP425_EthA_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0x9000) -#define IXP425_EthB_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0xA000) -#define IXP425_USB_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0xB000) - - /* * UART Register Definitions , Offsets only as there are 2 UARTS. * IXP425_UART1_BASE , IXP425_UART2_BASE. @@ -341,11 +310,14 @@ #define IXP425_ICIH_OFFSET 0x18 /* IRQ Highest Pri Int */ #define IXP425_ICFH_OFFSET 0x1C /* FIQ Highest Pri Int */ +#define N_IRQS 32 +#define IXP425_TIMER_2_IRQ 11 + /* * Interrupt Controller Register Definitions. */ #ifndef __ASSEMBLY__ -#define IXP425_INTC_REG(x) ((volatile u32 *)(IXP425_INTC_BASE_VIRT+(x))) +#define IXP425_INTC_REG(x) ((volatile u32 *)(IXP425_INTC_BASE_PHYS+(x))) #else #define IXP425_INTC_REG(x) (IXP425_INTC_BASE_PHYS+(x)) #endif @@ -375,7 +347,7 @@ * GPIO Register Definitions. * [Only perform 32bit reads/writes] */ -#define IXP425_GPIO_REG(x) ((volatile u32 *)(IXP425_GPIO_BASE_VIRT+(x))) +#define IXP425_GPIO_REG(x) ((volatile u32 *)(IXP425_GPIO_BASE_PHYS+(x))) #define IXP425_GPIO_GPOUTR IXP425_GPIO_REG(IXP425_GPIO_GPOUTR_OFFSET) #define IXP425_GPIO_GPOER IXP425_GPIO_REG(IXP425_GPIO_GPOER_OFFSET) @@ -387,6 +359,16 @@ #define IXP425_GPIO_GPDBSELR IXP425_GPIO_REG(IXP425_GPIO_GPDBSELR_OFFSET) /* + * Macros to make it easy to access the GPIO registers + */ +#define GPIO_OUTPUT_ENABLE(line) *IXP425_GPIO_GPOER &= ~(1 << (line)) +#define GPIO_OUTPUT_DISABLE(line) *IXP425_GPIO_GPOER |= (1 << (line)) +#define GPIO_OUTPUT_SET(line) *IXP425_GPIO_GPOUTR |= (1 << (line)) +#define GPIO_OUTPUT_CLEAR(line) *IXP425_GPIO_GPOUTR &= ~(1 << (line)) +#define GPIO_INT_ACT_LOW_SET(line) *IXP425_GPIO_GPIT1R = \ + (*IXP425_GPIO_GPIT1R & ~(0x7 << (line * 3))) | (0x1 << (line * 3)) + +/* * Constants to make it easy to access Timer Control/Status registers */ #define IXP425_OSTS_OFFSET 0x00 /* Continious TimeStamp */ @@ -409,7 +391,9 @@ #define IXP425_TIMER_REG(x) (IXP425_TIMER_BASE_PHYS+(x)) #endif +#if 0 /* test-only: also defined in npe/include/... */ #define IXP425_OSTS IXP425_TIMER_REG(IXP425_OSTS_OFFSET) +#endif #define IXP425_OST1 IXP425_TIMER_REG(IXP425_OST1_OFFSET) #define IXP425_OSRT1 IXP425_TIMER_REG(IXP425_OSRT1_OFFSET) #define IXP425_OST2 IXP425_TIMER_REG(IXP425_OST2_OFFSET) @@ -457,12 +441,12 @@ #define PCI_ATPDMA0_LENADDR_OFFSET 0x48 #define PCI_ATPDMA1_AHBADDR_OFFSET 0x4C #define PCI_ATPDMA1_PCIADDR_OFFSET 0x50 -#define PCI_ATPDMA1_LENADDR_OFFSET 0x54 +#define PCI_ATPDMA1_LENADDR_OFFSET 0x54 /* * PCI Control/Status Registers */ -#define IXP425_PCI_CSR(x) ((volatile u32 *)(IXP425_PCI_CFG_BASE_VIRT+(x))) +#define IXP425_PCI_CSR(x) ((volatile u32 *)(IXP425_PCI_CFG_BASE_PHYS+(x))) #define PCI_NP_AD IXP425_PCI_CSR(PCI_NP_AD_OFFSET) #define PCI_NP_CBE IXP425_PCI_CSR(PCI_NP_CBE_OFFSET) diff --git a/include/asm-arm/mach-types.h b/include/asm-arm/mach-types.h index fd037485235..7d7888ed8c7 100644 --- a/include/asm-arm/mach-types.h +++ b/include/asm-arm/mach-types.h @@ -736,6 +736,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_LN2410SBC 725 #define MACH_TYPE_CB3RUFC 726 #define MACH_TYPE_MP2USB 727 +#define MACH_TYPE_PDNB3 1002 #ifdef CONFIG_ARCH_EBSA110 # ifdef machine_arch_type diff --git a/include/asm-arm/u-boot.h b/include/asm-arm/u-boot.h index 146934cf0cb..c120312e0aa 100644 --- a/include/asm-arm/u-boot.h +++ b/include/asm-arm/u-boot.h @@ -48,6 +48,10 @@ typedef struct bd_info { ulong start; ulong size; } bi_dram[CONFIG_NR_DRAM_BANKS]; +#ifdef CONFIG_HAS_ETH1 + /* second onboard ethernet port */ + unsigned char bi_enet1addr[6]; +#endif } bd_t; #define bi_env_data bi_env->data diff --git a/include/configs/ixdp425.h b/include/configs/ixdp425.h index b0a80a3ea23..9f9fdb25e2c 100644 --- a/include/configs/ixdp425.h +++ b/include/configs/ixdp425.h @@ -33,6 +33,9 @@ #define CONFIG_IXP425 1 /* This is an IXP425 CPU */ #define CONFIG_IXDP425 1 /* on an IXDP425 Board */ +#define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info (and speed) */ +#define CONFIG_DISPLAY_BOARDINFO 1 /* display board info */ + /*************************************************************** * U-boot generic defines start here. ***************************************************************/ @@ -135,6 +138,8 @@ #define CFG_DRAM_SIZE 0x01000000 #define CFG_FLASH_BASE PHYS_FLASH_1 +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ /* * Expansion bus settings @@ -155,16 +160,27 @@ /* * FLASH and environment organization */ +/* + * FLASH and environment organization + */ #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ + +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CFG_ENV_IS_IN_FLASH 1 + +#define CFG_FLASH_BANKS_LIST { PHYS_FLASH_1 } + +#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT /* no byte writes on IXP4xx */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ -/* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */ +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -/* FIXME */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x20000) /* Addr of Environment Sector */ -#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */ +#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ +#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x20000) +#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ #endif /* __CONFIG_H */ diff --git a/include/configs/ixdpg425.h b/include/configs/ixdpg425.h new file mode 100644 index 00000000000..af4ecf621a3 --- /dev/null +++ b/include/configs/ixdpg425.h @@ -0,0 +1,240 @@ +/* + * (C) Copyright 2005-2006 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * (C) Copyright 2003 + * Martijn de Gouw, Prodrive B.V., martijn.de.gouw@prodrive.nl + * + * Configuation settings for the IXDPG425 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_IXP425 1 /* This is an IXP425 CPU */ +#define CONFIG_IXDPG425 1 /* on an IXDPG425 Board */ + +#define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info (and speed) */ +#define CONFIG_DISPLAY_BOARDINFO 1 /* display board info */ + +/* + * Ethernet + */ +#define CONFIG_IXP4XX_NPE 1 /* include IXP4xx NPE support */ +#define CONFIG_NET_MULTI 1 +#define CONFIG_PHY_ADDR 5 /* NPE0 PHY address */ +#define CONFIG_HAS_ETH1 +#define CONFIG_PHY1_ADDR 4 /* NPE1 PHY address */ +#define CONFIG_MII 1 /* MII PHY management */ +#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */ + +/* + * Misc configuration options + */ +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ +#define CONFIG_USE_IRQ 1 /* we need IRQ stuff for timer */ + +#define CONFIG_BOOTCOUNT_LIMIT /* support for bootcount limit */ +#define CFG_BOOTCOUNT_ADDR 0x60003000 /* inside qmrg sram */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (256 << 10) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 115200 +#define CFG_IXP425_CONSOLE IXP425_UART1 /* we use UART1 for console */ + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_ELF | \ + CFG_CMD_NET | \ + CFG_CMD_MII | \ + CFG_CMD_PING) + +/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +/* These are u-boot generic parameters */ +#include <cmd_confdefs.h> + +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00800000 /* 4 ... 8 MB in DRAM */ +#define CFG_LOAD_ADDR 0x00010000 /* default load address */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + + /* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/*************************************************************** + * Platform/Board specific defines start here. + ***************************************************************/ + +/*----------------------------------------------------------------------- + * Default configuration (environment varibles...) + *----------------------------------------------------------------------*/ +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "hostname=ixdpg425\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "rootpath=/opt/eldk/arm\0" \ + "bootfile=/tftpboot/ixdpg425/uImage\0" \ + "kernel_addr=50080000\0" \ + "ramdisk_addr=50200000\0" \ + "load=tftp 100000 /tftpboot/ixdpg425/u-boot.bin\0" \ + "update=protect off 50000000 5003ffff;era 50000000 5003ffff;" \ + "cp.b 100000 50000000 40000;" \ + "setenv filesize;saveenv\0" \ + "upd=run load;run update\0" \ + "" +#define CONFIG_BOOTCOMMAND "run net_nfs" + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 2 banks of DRAM */ +#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ + +#define PHYS_FLASH_1 0x50000000 /* Flash Bank #1 */ +#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */ +#define PHYS_FLASH_BANK_SIZE 0x01000000 /* 16 MB Banks */ +#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 128 KB sectors (x1) */ + +#define CFG_DRAM_BASE 0x00000000 +#define CFG_DRAM_SIZE 0x01000000 + +#define CFG_FLASH_BASE PHYS_FLASH_1 +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ + +/* + * Expansion bus settings + */ +#define CFG_EXP_CS0 0xbcd23c42 + +/* + * SDRAM settings + */ +#define CFG_SDR_CONFIG 0x18 +#define CFG_SDR_MODE_CONFIG 0x1 +#define CFG_SDRAM_REFRESH_CNT 0x81a + +/* + * FLASH and environment organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ + +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CFG_ENV_IS_IN_FLASH 1 + +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#define CFG_FLASH_PROTECTION 1 /* hardware flash protection */ + +#define CFG_FLASH_BANKS_LIST { PHYS_FLASH_1 } + +#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT /* no byte writes on IXP4xx */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ +#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x40000) +#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +/* + * GPIO settings + */ +#define CFG_GPIO_PCI_INTA_N 6 +#define CFG_GPIO_PCI_INTB_N 7 +#define CFG_GPIO_SWITCH_RESET_N 8 +#define CFG_GPIO_SLIC_RESET_N 13 +#define CFG_GPIO_PCI_CLK 14 +#define CFG_GPIO_EXTBUS_CLK 15 + +/* + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 + +#endif /* __CONFIG_H */ diff --git a/include/configs/pdnb3.h b/include/configs/pdnb3.h new file mode 100644 index 00000000000..ba6b113d8c2 --- /dev/null +++ b/include/configs/pdnb3.h @@ -0,0 +1,307 @@ +/* + * (C) Copyright 2006 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * Configuation settings for the PDNB3 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_IXP425 1 /* This is an IXP425 CPU */ +#define CONFIG_PDNB3 1 /* on an PDNB3 board */ + +#define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info (and speed) */ +#define CONFIG_DISPLAY_BOARDINFO 1 /* display board info */ + +/* + * Ethernet + */ +#define CONFIG_IXP4XX_NPE 1 /* include IXP4xx NPE support */ +#define CONFIG_NET_MULTI 1 +#define CONFIG_PHY_ADDR 16 /* NPE0 PHY address */ +#define CONFIG_HAS_ETH1 +#define CONFIG_PHY1_ADDR 18 /* NPE1 PHY address */ +#define CONFIG_MII 1 /* MII PHY management */ +#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */ + +/* + * Misc configuration options + */ +#define CONFIG_USE_IRQ 1 /* we need IRQ stuff for timer */ + +#define CONFIG_BOOTCOUNT_LIMIT /* support for bootcount limit */ +#define CFG_BOOTCOUNT_ADDR 0x60003000 /* inside qmrg sram */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (1 << 20) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 115200 +#define CFG_IXP425_CONSOLE IXP425_UART1 /* we use UART1 for console */ + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_DATE | \ + CFG_CMD_NET | \ + CFG_CMD_MII | \ + CFG_CMD_NAND | \ + CFG_CMD_I2C | \ + CFG_CMD_ELF | \ + CFG_CMD_PING) + +/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +/* These are u-boot generic parameters */ +#include <cmd_confdefs.h> + +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00800000 /* 4 ... 8 MB in DRAM */ +#define CFG_LOAD_ADDR 0x00010000 /* default load address */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + /* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/*************************************************************** + * Platform/Board specific defines start here. + ***************************************************************/ + +/*----------------------------------------------------------------------- + * Default configuration (environment varibles...) + *----------------------------------------------------------------------*/ +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "hostname=pdnb3\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} ethaddr=${ethaddr} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate} " \ + "mtdparts=${mtdparts}\0" \ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "rootpath=/opt/buildroot\0" \ + "bootfile=/tftpboot/netbox/uImage\0" \ + "kernel_addr=50080000\0" \ + "ramdisk_addr=50200000\0" \ + "load=tftp 100000 /tftpboot/netbox/u-boot.bin\0" \ + "update=protect off 50000000 5007dfff;era 50000000 5007dfff;" \ + "cp.b 100000 50000000 ${filesize};" \ + "setenv filesize;saveenv\0" \ + "upd=run load;run update\0" \ + "ipaddr=10.0.0.233\0" \ + "serverip=10.0.0.152\0" \ + "netmask=255.255.0.0\0" \ + "ethaddr=c6:6f:13:36:f3:81\0" \ + "eth1addr=c6:6f:13:36:f3:82\0" \ + "mtdparts=IXP4XX-Flash.0:504k@0(uboot),4k@504k(env)," \ + "4k@508k(renv)\0" \ + "" +#define CONFIG_BOOTCOMMAND "run net_nfs" + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ + +#define CFG_FLASH_BASE 0x50000000 +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MONITOR_LEN (504 << 10) /* Reserve 512 kB for Monitor */ + +/* + * Expansion bus settings + */ +#define CFG_EXP_CS0 0x94913C43 /* 8bit, max size */ +#define CFG_EXP_CS1 0x85000043 /* 8bit, 512bytes */ + +/* + * SDRAM settings + */ +#define CFG_SDR_CONFIG 0x18 +#define CFG_SDR_MODE_CONFIG 0x1 +#define CFG_SDRAM_REFRESH_CNT 0x81a + +/* + * FLASH and environment organization + */ +#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ + +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_WORD_SIZE unsigned char /* flash word size (width) */ +#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ +#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ +/* + * The following defines are added for buggy IOP480 byte interface. + * All other boards should use the standard values (CPCI405 etc.) + */ +#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ +#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ +#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +#define CFG_ENV_IS_IN_FLASH 1 + +#define CFG_ENV_SECT_SIZE 0x1000 /* size of one complete sector */ +#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN) +#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +/* + * NAND-FLASH stuff + */ +#define CFG_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CFG_NAND_BASE 0x51000000 /* NAND FLASH Base Address */ + +/* + * GPIO settings + */ + +/* FPGA program pin configuration */ +#define CFG_GPIO_PRG 12 /* FPGA program pin (cpu output)*/ +#define CFG_GPIO_CLK 10 /* FPGA clk pin (cpu output) */ +#define CFG_GPIO_DATA 14 /* FPGA data pin (cpu output) */ +#define CFG_GPIO_INIT 13 /* FPGA init pin (cpu input) */ +#define CFG_GPIO_DONE 11 /* FPGA done pin (cpu input) */ + +/* other GPIO's */ +#define CFG_GPIO_RESTORE_INT 0 +#define CFG_GPIO_RESTART_INT 1 +#define CFG_GPIO_SYS_RUNNING 2 +#define CFG_GPIO_PCI_INTA 3 +#define CFG_GPIO_PCI_INTB 4 +#define CFG_GPIO_I2C_SCL 6 +#define CFG_GPIO_I2C_SDA 7 +#define CFG_GPIO_FPGA_RESET 9 +#define CFG_GPIO_CLK_33M 15 + +/* + * I2C stuff + */ + +/* enable I2C and select the hardware/software driver */ +#undef CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ + +#define CFG_I2C_SPEED 83000 /* 83 kHz is supposed to work */ +#define CFG_I2C_SLAVE 0xFE + +/* + * Software (bit-bang) I2C driver configuration + */ +#define PB_SCL (1 << CFG_GPIO_I2C_SCL) +#define PB_SDA (1 << CFG_GPIO_I2C_SDA) + +#define I2C_INIT GPIO_OUTPUT_ENABLE(CFG_GPIO_I2C_SCL) +#define I2C_ACTIVE GPIO_OUTPUT_ENABLE(CFG_GPIO_I2C_SDA) +#define I2C_TRISTATE GPIO_OUTPUT_DISABLE(CFG_GPIO_I2C_SDA) +#define I2C_READ ((*IXP425_GPIO_GPINR & PB_SDA) != 0) +#define I2C_SDA(bit) if (bit) GPIO_OUTPUT_SET(CFG_GPIO_I2C_SDA); \ + else GPIO_OUTPUT_CLEAR(CFG_GPIO_I2C_SDA) +#define I2C_SCL(bit) if (bit) GPIO_OUTPUT_SET(CFG_GPIO_I2C_SCL); \ + else GPIO_OUTPUT_CLEAR(CFG_GPIO_I2C_SCL) +#define I2C_DELAY udelay(3) /* 1/4 I2C clock duration */ + +/* + * I2C RTC + */ +#define CONFIG_RTC_M41T11 1 +#define CFG_I2C_RTC_ADDR 0x68 +#define CFG_M41T11_BASE_YEAR 1900 /* play along with the linux driver */ + +/* + * Spartan3 FPGA configuration support + */ +#define CFG_FPGA_MAX_SIZE 700*1024 /* 700kByte for XC3S500E */ + +#define CFG_FPGA_PRG (1 << CFG_GPIO_PRG) /* FPGA program pin (cpu output)*/ +#define CFG_FPGA_CLK (1 << CFG_GPIO_CLK) /* FPGA clk pin (cpu output) */ +#define CFG_FPGA_DATA (1 << CFG_GPIO_DATA) /* FPGA data pin (cpu output) */ +#define CFG_FPGA_INIT (1 << CFG_GPIO_INIT) /* FPGA init pin (cpu input) */ +#define CFG_FPGA_DONE (1 << CFG_GPIO_DONE) /* FPGA done pin (cpu input) */ + +/* + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 + +#endif /* __CONFIG_H */ diff --git a/include/flash.h b/include/flash.h index a84dc6872e1..84b48a9f2e7 100644 --- a/include/flash.h +++ b/include/flash.h @@ -234,6 +234,7 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of #define SST_ID_xF3202 0x235A235A /* 39xF3202 ID (32M = 2M x 16 ) */ #define SST_ID_xF6401 0x236B236B /* 39xF6401 ID (64M = 4M x 16 ) */ #define SST_ID_xF6402 0x236A236A /* 39xF6402 ID (64M = 4M x 16 ) */ +#define SST_ID_xF020 0xBFD6BFD6 /* 39xF020 ID (256KB = 2Mbit x 8) */ #define SST_ID_xF040 0xBFD7BFD7 /* 39xF040 ID (512KB = 4Mbit x 8) */ #define STM_ID_F040B 0xE2 /* M29F040B ID ( 4M = 512K x 8 ) */ @@ -343,6 +344,7 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of #define FLASH_SST160A 0x0046 /* SST 39xF160A ID ( 16M = 1M x 16 ) */ #define FLASH_SST320 0x0048 /* SST 39xF160A ID ( 16M = 1M x 16 ) */ #define FLASH_SST640 0x004A /* SST 39xF160A ID ( 16M = 1M x 16 ) */ +#define FLASH_SST020 0x0024 /* SST 39xF020 ID (256KB = 2Mbit x 8 ) */ #define FLASH_SST040 0x000E /* SST 39xF040 ID (512KB = 4Mbit x 8 ) */ #define FLASH_STM800AB 0x0051 /* STM M29WF800AB ( 8M = 512K x 16 ) */ |