diff options
Diffstat (limited to 'include')
39 files changed, 660 insertions, 329 deletions
diff --git a/include/axp152.h b/include/axp152.h new file mode 100644 index 00000000000..3e5ccbd0d8d --- /dev/null +++ b/include/axp152.h @@ -0,0 +1,10 @@ +/* + * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +int axp152_set_dcdc2(int mvolt); +int axp152_set_dcdc3(int mvolt); +int axp152_set_dcdc4(int mvolt); +int axp152_set_ldo2(int mvolt); +int axp152_init(void); diff --git a/include/axp209.h b/include/axp209.h new file mode 100644 index 00000000000..21efce64bb8 --- /dev/null +++ b/include/axp209.h @@ -0,0 +1,14 @@ +/* + * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +extern int axp209_set_dcdc2(int mvolt); +extern int axp209_set_dcdc3(int mvolt); +extern int axp209_set_ldo2(int mvolt); +extern int axp209_set_ldo3(int mvolt); +extern int axp209_set_ldo4(int mvolt); +extern int axp209_init(void); +extern int axp209_poweron_by_dc(void); +extern int axp209_power_button(void); diff --git a/include/common.h b/include/common.h index a75fc25c5f6..1d6cb48ff07 100644 --- a/include/common.h +++ b/include/common.h @@ -318,14 +318,14 @@ int arch_early_init_r(void); void board_show_dram(ulong size); /** - * arch_fixup_memory_node() - Write arch-specific memory information to fdt + * arch_fixup_fdt() - Write arch-specific information to fdt * - * Defined in arch/$(ARCH)/lib/bootm.c + * Defined in arch/$(ARCH)/lib/bootm-fdt.c * * @blob: FDT blob to write to * @return 0 if ok, or -ve FDT_ERR_... on failure */ -int arch_fixup_memory_node(void *blob); +int arch_fixup_fdt(void *blob); /* common/flash.c */ void flash_perror (int); diff --git a/include/configs/alt.h b/include/configs/alt.h new file mode 100644 index 00000000000..9eec4bc2313 --- /dev/null +++ b/include/configs/alt.h @@ -0,0 +1,166 @@ +/* + * include/configs/alt.h + * This file is alt board configuration. + * + * Copyright (C) 2014 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __ALT_H +#define __ALT_H + +#undef DEBUG +#define CONFIG_ARMV7 +#define CONFIG_R8A7794 +#define CONFIG_RMOBILE +#define CONFIG_RMOBILE_BOARD_STRING "Alt" +#define CONFIG_SH_GPIO_PFC + +#include <asm/arch/rmobile.h> + +#define CONFIG_CMD_EDITENV +#define CONFIG_CMD_SAVEENV +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_DFL +#define CONFIG_CMD_SDRAM +#define CONFIG_CMD_RUN +#define CONFIG_CMD_LOADS +#define CONFIG_CMD_NET +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_NFS +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_SF +#define CONFIG_CMD_SPI + +#define CONFIG_SYS_TEXT_BASE 0xE6304000 +#define CONFIG_SYS_THUMB_BUILD +#define CONFIG_SYS_GENERIC_BOARD + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_CMDLINE_EDITING + +#define CONFIG_OF_LIBFDT +#define BOARD_LATE_INIT + +#define CONFIG_BAUDRATE 38400 +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTARGS "" + +#define CONFIG_VERSION_VARIABLE +#undef CONFIG_SHOW_BOOT_PROGRESS + +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_TMU_TIMER + +#define CONFIG_SYS_INIT_SP_ADDR 0xE633FFFC +#define STACK_AREA_SIZE 0xC000 +#define LOW_LEVEL_MERAM_STACK \ + (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) + +/* MEMORY */ +#define ALT_SDRAM_BASE 0x40000000 +#define ALT_SDRAM_SIZE (1024u * 1024 * 1024) +#define ALT_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) + +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_PBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE 512 +#define CONFIG_SYS_BAUDRATE_TABLE { 38400, 115200 } + +/* SCIF */ +#define CONFIG_SCIF_CONSOLE +#define CONFIG_CONS_SCIF2 +#undef CONFIG_SYS_CONSOLE_INFO_QUIET +#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE +#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE + +#define CONFIG_SYS_MEMTEST_START (ALT_SDRAM_BASE) +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ + 504 * 1024 * 1024) +#undef CONFIG_SYS_ALT_MEMTEST +#undef CONFIG_SYS_MEMTEST_SCRATCH +#undef CONFIG_SYS_LOADS_BAUD_CHANGE + +#define CONFIG_SYS_SDRAM_BASE (ALT_SDRAM_BASE) +#define CONFIG_SYS_SDRAM_SIZE (ALT_UBOOT_SDRAM_SIZE) +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fc0) +#define CONFIG_NR_DRAM_BANKS 1 + +#define CONFIG_SYS_MONITOR_BASE 0x00000000 +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) +#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) +#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) + +/* FLASH */ +#define CONFIG_SPI +#define CONFIG_SPI_FLASH_BAR +#define CONFIG_SH_QSPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SPANSION +#define CONFIG_SPI_FLASH_QUAD +#define CONFIG_SYS_NO_FLASH + +/* ENV setting */ +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SECT_SIZE (256 * 1024) +#define CONFIG_ENV_ADDR 0xC0000 +#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR) +#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootm_low=0x40e00000\0" \ + "bootm_size=0x100000\0" \ + +/* SH Ether */ +#define CONFIG_NET_MULTI +#define CONFIG_SH_ETHER +#define CONFIG_SH_ETHER_USE_PORT 0 +#define CONFIG_SH_ETHER_PHY_ADDR 0x1 +#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII +#define CONFIG_SH_ETHER_CACHE_WRITEBACK +#define CONFIG_SH_ETHER_CACHE_INVALIDATE +#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL +#define CONFIG_BITBANGMII +#define CONFIG_BITBANGMII_MULTI + +/* Board Clock */ +#define RMOBILE_XTAL_CLK 20000000u +#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK +#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */ +#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2) +#define CONFIG_P_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 24) +#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_P_CLK_FREQ + +#define CONFIG_SYS_TMU_CLK_DIV 4 + +/* i2c */ +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_SH +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3 +#define CONFIG_SYS_I2C_SH_BASE0 0xE6500000 +#define CONFIG_SYS_I2C_SH_SPEED0 400000 +#define CONFIG_SYS_I2C_SH_BASE1 0xE6510000 +#define CONFIG_SYS_I2C_SH_SPEED1 400000 +#define CONFIG_SYS_I2C_SH_BASE2 0xE60B0000 +#define CONFIG_SYS_I2C_SH_SPEED2 400000 +#define CONFIG_SH_I2C_DATA_HIGH 4 +#define CONFIG_SH_I2C_DATA_LOW 5 +#define CONFIG_SH_I2C_CLOCK 10000000 + +#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ + +#endif /* __ALT_H */ diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 34d27c632a9..35ae0e6fb76 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -254,6 +254,11 @@ #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 +#ifdef CONFIG_SPL_OS_BOOT +#define CONFIG_CMD_SPL_NAND_OFS 0x00080000 /* os parameters */ +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */ +#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000 +#endif #endif #endif @@ -453,6 +458,7 @@ #define CONFIG_SYS_MAX_FLASH_BANKS 1 #define CONFIG_SYS_FLASH_BASE (0x08000000) #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_SYS_FLASH_SIZE 0x01000000 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Reduce SPL size by removing unlikey targets */ #ifdef CONFIG_NOR_BOOT diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h index ad4cbd88b89..d826214efe0 100644 --- a/include/configs/am3517_crane.h +++ b/include/configs/am3517_crane.h @@ -252,17 +252,12 @@ */ /* **** PISMO SUPPORT *** */ - -/* Configure the PISMO */ -#define PISMO1_NAND_SIZE GPMC_SIZE_128M -#define PISMO1_ONEN_SIZE GPMC_SIZE_128M - #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */ /* on one chip */ #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ -#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE +#define CONFIG_SYS_FLASH_BASE NAND_BASE /* Monitor at start of flash */ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index 0102ff5b7f9..a9c5a8f3af3 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -259,18 +259,13 @@ */ /* **** PISMO SUPPORT *** */ - -/* Configure the PISMO */ -#define PISMO1_NAND_SIZE GPMC_SIZE_128M -#define PISMO1_ONEN_SIZE GPMC_SIZE_128M - #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */ /* on one chip */ #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ #if defined(CONFIG_CMD_NAND) -#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE +#define CONFIG_SYS_FLASH_BASE NAND_BASE #endif /* Monitor at start of flash */ diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index 974ce986e9c..e26204025f8 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -33,6 +33,8 @@ #define CONFIG_SYS_I2C_MULTI_EEPROMS /* Power */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C #define CONFIG_POWER_TPS65218 /* SPL defines. */ diff --git a/include/configs/cm_t335.h b/include/configs/cm_t335.h index 4d1dd28a915..a3e6452ec1d 100644 --- a/include/configs/cm_t335.h +++ b/include/configs/cm_t335.h @@ -150,6 +150,11 @@ #define CONFIG_ENV_OFFSET 0x300000 /* environment starts here */ #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ #define CONFIG_SYS_NAND_ONFI_DETECTION +#ifdef CONFIG_SPL_OS_BOOT +#define CONFIG_CMD_SPL_NAND_OFS 0x400000 /* un-assigned: (using dtb) */ +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x500000 +#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000 +#endif /* GPIO pin + bank to pin ID mapping */ #define GPIO_PIN(_bank, _pin) ((_bank << 5) + _pin) diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index 5c484ef0788..d8d71a94ee9 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -258,9 +258,6 @@ */ /* **** PISMO SUPPORT *** */ -/* Configure the PISMO */ -#define PISMO1_NAND_SIZE GPMC_SIZE_128M - /* Monitor at start of flash */ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index 5308790fe6b..cc53fc9cd78 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -262,8 +262,6 @@ #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 /* NAND and environment organization */ -#define PISMO1_NAND_SIZE GPMC_SIZE_128M - #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ #define CONFIG_ENV_IS_IN_NAND 1 diff --git a/include/configs/dig297.h b/include/configs/dig297.h index ce205e9b3eb..7e47c564530 100644 --- a/include/configs/dig297.h +++ b/include/configs/dig297.h @@ -251,10 +251,6 @@ */ /* **** PISMO SUPPORT *** */ - -/* Configure the PISMO */ -#define PISMO1_NAND_SIZE GPMC_SIZE_128M - #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ #define CONFIG_SYS_FLASH_BASE boot_flash_base diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h index 8b9f66a29c1..77717a84aee 100644 --- a/include/configs/edminiv2.h +++ b/include/configs/edminiv2.h @@ -187,7 +187,8 @@ * I2C related stuff */ #ifdef CONFIG_CMD_I2C -#define CONFIG_I2C_MVTWSI +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MVTWSI #define CONFIG_I2C_MVTWSI_BASE ORION5X_TWSI_BASE #define CONFIG_SYS_I2C_SLAVE 0x0 #define CONFIG_SYS_I2C_SPEED 100000 diff --git a/include/configs/k2e_evm.h b/include/configs/k2e_evm.h new file mode 100644 index 00000000000..3502d104720 --- /dev/null +++ b/include/configs/k2e_evm.h @@ -0,0 +1,37 @@ +/* + * Configuration header file for TI's k2e-evm + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_K2E_EVM_H +#define __CONFIG_K2E_EVM_H + +/* Platform type */ +#define CONFIG_SOC_K2E +#define CONFIG_K2E_EVM + +/* U-Boot general configuration */ +#define CONFIG_SYS_PROMPT "K2E EVM # " + +#define KS2_ARGS_UBI "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs "\ + "root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,2048\0" + +#define KS2_FDT_NAME "name_fdt=k2e-evm.dtb\0" +#define KS2_ADDR_MON "addr_mon=0x0c140000\0" +#define KS2_NAME_MON "name_mon=skern-k2e-evm.bin\0" +#define NAME_UBOOT "name_uboot=u-boot-spi-k2e-evm.gph\0" +#define NAME_UBI "name_ubi=k2e-evm-ubifs.ubi\0" + +#include <configs/ks2_evm.h> + +/* SPL SPI Loader Configuration */ +#define CONFIG_SPL_TEXT_BASE 0x0c100000 + +/* NAND Configuration */ +#define CONFIG_SYS_NAND_PAGE_2K + +#endif /* __CONFIG_K2E_EVM_H */ diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h index 858329f9586..8aa616da0e0 100644 --- a/include/configs/k2hk_evm.h +++ b/include/configs/k2hk_evm.h @@ -14,252 +14,27 @@ #define CONFIG_SOC_K2HK #define CONFIG_K2HK_EVM -/* U-Boot Build Configuration */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 2nd stage loader */ -#define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */ -#define CONFIG_SYS_CONSOLE_INFO_QUIET -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_SYS_THUMB_BUILD - -/* SoC Configuration */ -#define CONFIG_ARMV7 -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_SYS_ARCH_TIMER -#define CONFIG_SYS_HZ 1000 -#define CONFIG_SYS_TEXT_BASE 0x0c001000 -#define CONFIG_SPL_TARGET "u-boot-spi.gph" -#define CONFIG_SYS_DCACHE_OFF - -/* Memory Configuration */ -#define CONFIG_NR_DRAM_BANKS 2 -#define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_LPAE_SDRAM_BASE 0x800000000 -#define CONFIG_MAX_RAM_BANK_SIZE (2 << 30) /* 2GB */ -#define CONFIG_STACKSIZE (512 << 10) /* 512 KiB */ -#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4 MiB */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - \ - GENERATED_GBL_DATA_SIZE) - -/* SPL SPI Loader Configuration */ -#define CONFIG_SPL_TEXT_BASE 0x0c200000 -#define CONFIG_SPL_PAD_TO 65536 -#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_PAD_TO - 8) -#define CONFIG_SPL_BSS_START_ADDR (CONFIG_SPL_TEXT_BASE + \ - CONFIG_SPL_MAX_SIZE) -#define CONFIG_SPL_BSS_MAX_SIZE (32 * 1024) -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ - CONFIG_SPL_BSS_MAX_SIZE) -#define CONFIG_SYS_SPL_MALLOC_SIZE (32 * 1024) -#define CONFIG_SPL_STACK_SIZE (8 * 1024) -#define CONFIG_SPL_STACK (CONFIG_SYS_SPL_MALLOC_START + \ - CONFIG_SYS_SPL_MALLOC_SIZE + \ - CONFIG_SPL_STACK_SIZE - 4) -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_LIBGENERIC_SUPPORT -#define CONFIG_SPL_SERIAL_SUPPORT -#define CONFIG_SPL_SPI_FLASH_SUPPORT -#define CONFIG_SPL_SPI_SUPPORT -#define CONFIG_SPL_BOARD_INIT -#define CONFIG_SPL_SPI_LOAD -#define CONFIG_SPL_SPI_BUS 0 -#define CONFIG_SPL_SPI_CS 0 -#define CONFIG_SYS_SPI_U_BOOT_OFFS CONFIG_SPL_PAD_TO -#define CONFIG_SPL_FRAMEWORK - -/* UART Configuration */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_MEM32 -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#define CONFIG_SYS_NS16550_COM1 KS2_UART0_BASE -#define CONFIG_SYS_NS16550_COM2 KS2_UART1_BASE -#define CONFIG_SYS_NS16550_CLK clk_get_rate(K2HK_CLK1_6) -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 - -/* SPI Configuration */ -#define CONFIG_SPI -#define CONFIG_SPI_FLASH -#define CONFIG_SPI_FLASH_STMICRO -#define CONFIG_DAVINCI_SPI -#define CONFIG_SYS_SPI0 -#define CONFIG_SYS_SPI_BASE K2HK_SPI_BASE -#define CONFIG_SYS_SPI0_NUM_CS 4 -#define CONFIG_SYS_SPI1 -#define CONFIG_SYS_SPI1_BASE K2HK_SPI1_BASE -#define CONFIG_SYS_SPI1_NUM_CS 4 -#define CONFIG_SYS_SPI2 -#define CONFIG_SYS_SPI2_NUM_CS 4 -#define CONFIG_SYS_SPI2_BASE K2HK_SPI2_BASE -#define CONFIG_CMD_SPI -#define CONFIG_SYS_SPI_CLK clk_get_rate(K2HK_LPSC_EMIF25_SPI) -#define CONFIG_SF_DEFAULT_SPEED 30000000 -#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +/* U-Boot general configuration */ +#define CONFIG_SYS_PROMPT "K2HK EVM # " -/* I2C Configuration */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_DAVINCI -#define CONFIG_SYS_DAVINCI_I2C_SPEED 100000 -#define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 /* SMBus host address */ -#define CONFIG_SYS_DAVINCI_I2C_SPEED1 100000 -#define CONFIG_SYS_DAVINCI_I2C_SLAVE1 0x10 /* SMBus host address */ -#define CONFIG_SYS_DAVINCI_I2C_SPEED2 100000 -#define CONFIG_SYS_DAVINCI_I2C_SLAVE2 0x10 /* SMBus host address */ -#define I2C_BUS_MAX 3 +#define KS2_ARGS_UBI "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs "\ + "root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,2048\0" -/* EEPROM definitions */ -#define CONFIG_SYS_I2C_MULTI_EEPROMS -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 -#define CONFIG_ENV_EEPROM_IS_ON_I2C +#define KS2_FDT_NAME "name_fdt=k2hk-evm.dtb\0" +#define KS2_ADDR_MON "addr_mon=0x0c5f0000\0" +#define KS2_NAME_MON "name_mon=skern-k2hk-evm.bin\0" +#define NAME_UBOOT "name_uboot=u-boot-spi-k2hk-evm.gph\0" +#define NAME_UBI "name_ubi=k2hk-evm-ubifs.ubi\0" -/* Network Configuration */ -#define CONFIG_DRIVER_TI_KEYSTONE_NET -#define CONFIG_MII -#define CONFIG_BOOTP_DEFAULT -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_NET_RETRY_COUNT 32 -#define CONFIG_NET_MULTI -#define CONFIG_GET_LINK_STATUS_ATTEMPTS 5 -#define CONFIG_SYS_SGMII_REFCLK_MHZ 312 -#define CONFIG_SYS_SGMII_LINERATE_MHZ 1250 -#define CONFIG_SYS_SGMII_RATESCALE 2 +#include <configs/ks2_evm.h> -/* AEMIF */ -#define CONFIG_TI_AEMIF -#define CONFIG_AEMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE +/* SPL SPI Loader Configuration */ +#define CONFIG_SPL_TEXT_BASE 0x0c200000 /* NAND Configuration */ -#define CONFIG_NAND_DAVINCI -#define CONFIG_CMD_NAND_ECCLAYOUT -#define CONFIG_SYS_NAND_CS 2 -#define CONFIG_SYS_NAND_USE_FLASH_BBT -#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST #define CONFIG_SYS_NAND_PAGE_2K -#define CONFIG_SYS_NAND_MASK_CLE 0x4000 -#define CONFIG_SYS_NAND_MASK_ALE 0x2000 - -#define CONFIG_SYS_NAND_LARGEPAGE -#define CONFIG_SYS_NAND_BASE_LIST { 0x30000000, } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_MAX_CHIPS 1 -#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE -#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */ -#define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_OFFSET 0x100000 -#define CONFIG_MTD_PARTITIONS -#define CONFIG_MTD_DEVICE -#define CONFIG_RBTREE -#define CONFIG_LZO -#define MTDPARTS_DEFAULT "mtdparts=davinci_nand.0:" \ - "1024k(bootloader)ro,512k(params)ro," \ - "-(ubifs)" -/* U-Boot command configuration */ -#include <config_cmd_default.h> -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_I2C -#define CONFIG_CMD_PING -#define CONFIG_CMD_SAVES -#define CONFIG_CMD_MTDPARTS -#define CONFIG_CMD_NAND -#define CONFIG_CMD_UBI -#define CONFIG_CMD_UBIFS -#define CONFIG_CMD_SF -#define CONFIG_CMD_EEPROM - -/* U-Boot general configuration */ -#define CONFIG_SYS_GENERIC_BOARD -#define CONFIG_SYS_PROMPT "K2HK EVM # " -#define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_PBSIZE 2048 -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_LONGHELP -#define CONFIG_CRC32_VERIFY -#define CONFIG_MX_CYCLIC -#define CONFIG_CMDLINE_EDITING -#define CONFIG_VERSION_VARIABLE -#define CONFIG_TIMESTAMP -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_EXTRA_ENV_SETTINGS \ - "boot=ramfs\0" \ - "tftp_root=/\0" \ - "nfs_root=/export\0" \ - "mem_lpae=1\0" \ - "mem_reserve=512M\0" \ - "addr_fdt=0x87000000\0" \ - "addr_kern=0x88000000\0" \ - "addr_mon=0x0c5f0000\0" \ - "addr_uboot=0x87000000\0" \ - "addr_fs=0x82000000\0" \ - "addr_ubi=0x82000000\0" \ - "fdt_high=0xffffffff\0" \ - "name_fdt=uImage-k2hk-evm.dtb\0" \ - "name_fs=arago-console-image.cpio.gz\0" \ - "name_kern=uImage-keystone-evm.bin\0" \ - "name_mon=skern-keystone-evm.bin\0" \ - "name_uboot=u-boot-spi-keystone-evm.gph\0" \ - "name_ubi=keystone-evm-ubifs.ubi\0" \ - "run_mon=mon_install ${addr_mon}\0" \ - "run_kern=bootm ${addr_kern} - ${addr_fdt}\0" \ - "init_net=run args_all args_net\0" \ - "init_ubi=run args_all args_ubi; " \ - "ubi part ubifs; ubifsmount boot\0" \ - "get_fdt_net=dhcp ${addr_fdt} ${tftp_root}/${name_fdt}\0" \ - "get_fdt_ubi=ubifsload ${addr_fdt} ${name_fdt}\0" \ - "get_kern_net=dhcp ${addr_kern} ${tftp_root}/${name_kern}\0" \ - "get_kern_ubi=ubifsload ${addr_kern} ${name_kern}\0" \ - "get_mon_net=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \ - "get_mon_ubi=ubifsload ${addr_mon} ${name_mon}\0" \ - "get_uboot_net=dhcp ${addr_uboot} ${tftp_root}/${name_uboot}\0" \ - "burn_uboot=sf probe; sf erase 0 0x100000; " \ - "sf write ${addr_uboot} 0 ${filesize}\0" \ - "args_all=setenv bootargs console=ttyS0,115200n8 rootwait=1\0" \ - "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs " \ - "root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,2048\0" \ - "args_net=setenv bootargs ${bootargs} rootfstype=nfs " \ - "root=/dev/nfs rw nfsroot=${serverip}:${nfs_root}," \ - "${nfs_options} ip=dhcp\0" \ - "nfs_options=v3,tcp,rsize=4096,wsize=4096\0" \ - "get_fdt_ramfs=dhcp ${addr_fdt} ${tftp_root}/${name_fdt}\0" \ - "get_kern_ramfs=dhcp ${addr_kern} ${tftp_root}/${name_kern}\0" \ - "get_mon_ramfs=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \ - "get_fs_ramfs=dhcp ${addr_fs} ${tftp_root}/${name_fs}\0" \ - "get_ubi_net=dhcp ${addr_ubi} ${tftp_root}/${name_ubi}\0" \ - "burn_ubi=nand erase.part ubifs; " \ - "nand write ${addr_ubi} ubifs ${filesize}\0" \ - "init_ramfs=run args_all args_ramfs get_fs_ramfs\0" \ - "args_ramfs=setenv bootargs ${bootargs} earlyprintk " \ - "rdinit=/sbin/init rw root=/dev/ram0 " \ - "initrd=0x802000000,9M\0" \ - "no_post=1\0" \ - "mtdparts=mtdparts=davinci_nand.0:" \ - "1024k(bootloader)ro,512k(params)ro,522752k(ubifs)\0" -#define CONFIG_BOOTCOMMAND \ - "run init_${boot} get_fdt_${boot} get_mon_${boot} " \ - "get_kern_${boot} run_mon run_kern" -#define CONFIG_BOOTARGS \ - -/* Linux interfacing */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP -#define CONFIG_SYS_BARGSIZE 1024 -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x08000000) - -#define CONFIG_SUPPORT_RAW_INITRD - -/* we may include files below only after all above definitions */ -#include <asm/arch/hardware.h> -#include <asm/arch/clock.h> -#define CONFIG_SYS_HZ_CLOCK clk_get_rate(K2HK_CLK1_6) +/* Network */ +#define CONFIG_DRIVER_TI_KEYSTONE_NET #endif /* __CONFIG_K2HK_EVM_H */ diff --git a/include/configs/ks2_evm.h b/include/configs/ks2_evm.h new file mode 100644 index 00000000000..43db581c75d --- /dev/null +++ b/include/configs/ks2_evm.h @@ -0,0 +1,275 @@ +/* + * Common configuration header file for all Keystone II EVM platforms + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_KS2_EVM_H +#define __CONFIG_KS2_EVM_H + +#define CONFIG_SOC_KEYSTONE + +/* U-Boot Build Configuration */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 2nd stage loader */ +#define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */ +#define CONFIG_SYS_CONSOLE_INFO_QUIET +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_SYS_THUMB_BUILD + +/* SoC Configuration */ +#define CONFIG_ARMV7 +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_SYS_ARCH_TIMER +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_TEXT_BASE 0x0c001000 +#define CONFIG_SPL_TARGET "u-boot-spi.gph" +#define CONFIG_SYS_DCACHE_OFF + +/* Memory Configuration */ +#define CONFIG_NR_DRAM_BANKS 2 +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_LPAE_SDRAM_BASE 0x800000000 +#define CONFIG_MAX_RAM_BANK_SIZE (2 << 30) /* 2GB */ +#define CONFIG_STACKSIZE (512 << 10) /* 512 KiB */ +#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4 MiB */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - \ + GENERATED_GBL_DATA_SIZE) + +/* SPL SPI Loader Configuration */ +#define CONFIG_SPL_PAD_TO 65536 +#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_PAD_TO - 8) +#define CONFIG_SPL_BSS_START_ADDR (CONFIG_SPL_TEXT_BASE + \ + CONFIG_SPL_MAX_SIZE) +#define CONFIG_SPL_BSS_MAX_SIZE (32 * 1024) +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ + CONFIG_SPL_BSS_MAX_SIZE) +#define CONFIG_SYS_SPL_MALLOC_SIZE (32 * 1024) +#define CONFIG_SPL_STACK_SIZE (8 * 1024) +#define CONFIG_SPL_STACK (CONFIG_SYS_SPL_MALLOC_START + \ + CONFIG_SYS_SPL_MALLOC_SIZE + \ + CONFIG_SPL_STACK_SIZE - 4) +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SPL_SPI_BUS 0 +#define CONFIG_SPL_SPI_CS 0 +#define CONFIG_SYS_SPI_U_BOOT_OFFS CONFIG_SPL_PAD_TO +#define CONFIG_SPL_FRAMEWORK + +/* UART Configuration */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_MEM32 +#define CONFIG_SYS_NS16550_REG_SIZE -4 +#define CONFIG_SYS_NS16550_COM1 KS2_UART0_BASE +#define CONFIG_SYS_NS16550_COM2 KS2_UART1_BASE +#define CONFIG_SYS_NS16550_CLK clk_get_rate(KS2_CLK1_6) +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +/* SPI Configuration */ +#define CONFIG_SPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_DAVINCI_SPI +#define CONFIG_CMD_SPI +#define CONFIG_SYS_SPI_CLK clk_get_rate(KS2_CLK1_6) +#define CONFIG_SF_DEFAULT_SPEED 30000000 +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#define CONFIG_SYS_SPI0 +#define CONFIG_SYS_SPI_BASE KS2_SPI0_BASE +#define CONFIG_SYS_SPI0_NUM_CS 4 +#define CONFIG_SYS_SPI1 +#define CONFIG_SYS_SPI1_BASE KS2_SPI1_BASE +#define CONFIG_SYS_SPI1_NUM_CS 4 +#define CONFIG_SYS_SPI2 +#define CONFIG_SYS_SPI2_BASE KS2_SPI2_BASE +#define CONFIG_SYS_SPI2_NUM_CS 4 + +/* Network Configuration */ +#define CONFIG_MII +#define CONFIG_BOOTP_DEFAULT +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_NET_RETRY_COUNT 32 +#define CONFIG_NET_MULTI +#define CONFIG_GET_LINK_STATUS_ATTEMPTS 5 +#define CONFIG_SYS_SGMII_REFCLK_MHZ 312 +#define CONFIG_SYS_SGMII_LINERATE_MHZ 1250 +#define CONFIG_SYS_SGMII_RATESCALE 2 + +/* AEMIF */ +#define CONFIG_TI_AEMIF +#define CONFIG_AEMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE + +/* I2C Configuration */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_DAVINCI +#define CONFIG_SYS_DAVINCI_I2C_SPEED 100000 +#define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 /* SMBus host address */ +#define CONFIG_SYS_DAVINCI_I2C_SPEED1 100000 +#define CONFIG_SYS_DAVINCI_I2C_SLAVE1 0x10 /* SMBus host address */ +#define CONFIG_SYS_DAVINCI_I2C_SPEED2 100000 +#define CONFIG_SYS_DAVINCI_I2C_SLAVE2 0x10 /* SMBus host address */ +#define I2C_BUS_MAX 3 + +/* EEPROM definitions */ +#define CONFIG_SYS_I2C_MULTI_EEPROMS +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 +#define CONFIG_ENV_EEPROM_IS_ON_I2C + +/* NAND Configuration */ +#define CONFIG_NAND_DAVINCI +#define CONFIG_KEYSTONE_RBL_NAND +#define CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE CONFIG_ENV_OFFSET +#define CONFIG_SYS_NAND_MASK_CLE 0x4000 +#define CONFIG_SYS_NAND_MASK_ALE 0x2000 +#define CONFIG_SYS_NAND_CS 2 +#define CONFIG_SYS_NAND_USE_FLASH_BBT +#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST + +#define CONFIG_SYS_NAND_LARGEPAGE +#define CONFIG_SYS_NAND_BASE_LIST { 0x30000000, } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_MAX_CHIPS 1 +#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE +#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */ +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET 0x100000 +#define CONFIG_MTD_PARTITIONS +#define CONFIG_MTD_DEVICE +#define CONFIG_RBTREE +#define CONFIG_LZO +#define MTDIDS_DEFAULT "nand0=davinci_nand.0" +#define MTDPARTS_DEFAULT "mtdparts=davinci_nand.0:" \ + "1024k(bootloader)ro,512k(params)ro," \ + "-(ubifs)" + +/* U-Boot command configuration */ +#include <config_cmd_default.h> +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_I2C +#define CONFIG_CMD_PING +#define CONFIG_CMD_SAVES +#define CONFIG_CMD_MTDPARTS +#define CONFIG_CMD_NAND +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_CMD_SF +#define CONFIG_CMD_EEPROM + +/* U-Boot general configuration */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SYS_PBSIZE 2048 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_LONGHELP +#define CONFIG_CRC32_VERIFY +#define CONFIG_MX_CYCLIC +#define CONFIG_CMDLINE_EDITING +#define CONFIG_VERSION_VARIABLE +#define CONFIG_TIMESTAMP + +/* EDMA3 */ +#define CONFIG_TI_EDMA3 + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_EXTRA_ENV_SETTINGS \ + "boot=ramfs\0" \ + "tftp_root=/\0" \ + "nfs_root=/export\0" \ + "mem_lpae=1\0" \ + "mem_reserve=512M\0" \ + "addr_fdt=0x87000000\0" \ + "addr_kern=0x88000000\0" \ + KS2_ADDR_MON \ + "addr_uboot=0x87000000\0" \ + "addr_fs=0x82000000\0" \ + "addr_ubi=0x82000000\0" \ + "addr_secdb_key=0xc000000\0" \ + "fdt_high=0xffffffff\0" \ + KS2_FDT_NAME \ + "name_fs=arago-console-image.cpio.gz\0" \ + "name_kern=uImage\0" \ + KS2_NAME_MON \ + NAME_UBOOT \ + NAME_UBI \ + "run_mon=mon_install ${addr_mon}\0" \ + "run_kern=bootm ${addr_kern} - ${addr_fdt}\0" \ + "init_net=run args_all args_net\0" \ + "init_ubi=run args_all args_ubi; " \ + "ubi part ubifs; ubifsmount boot;" \ + "ubifsload ${addr_secdb_key} securedb.key.bin;\0" \ + "get_fdt_net=dhcp ${addr_fdt} ${tftp_root}/${name_fdt}\0" \ + "get_fdt_ubi=ubifsload ${addr_fdt} ${name_fdt}\0" \ + "get_kern_net=dhcp ${addr_kern} ${tftp_root}/${name_kern}\0" \ + "get_kern_ubi=ubifsload ${addr_kern} ${name_kern}\0" \ + "get_mon_net=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \ + "get_mon_ubi=ubifsload ${addr_mon} ${name_mon}\0" \ + "get_uboot_net=dhcp ${addr_uboot} ${tftp_root}/${name_uboot}\0" \ + "burn_uboot_spi=sf probe; sf erase 0 0x100000; " \ + "sf write ${addr_uboot} 0 ${filesize}\0" \ + "burn_uboot_nand=nand erase 0 0x100000; " \ + "nand write ${addr_uboot} 0 ${filesize}\0" \ + "args_all=setenv bootargs console=ttyS0,115200n8 rootwait=1\0" \ + KS2_ARGS_UBI \ + "args_net=setenv bootargs ${bootargs} rootfstype=nfs " \ + "root=/dev/nfs rw nfsroot=${serverip}:${nfs_root}," \ + "${nfs_options} ip=dhcp\0" \ + "nfs_options=v3,tcp,rsize=4096,wsize=4096\0" \ + "get_fdt_ramfs=dhcp ${addr_fdt} ${tftp_root}/${name_fdt}\0" \ + "get_kern_ramfs=dhcp ${addr_kern} ${tftp_root}/${name_kern}\0" \ + "get_mon_ramfs=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \ + "get_fs_ramfs=dhcp ${addr_fs} ${tftp_root}/${name_fs}\0" \ + "get_ubi_net=dhcp ${addr_ubi} ${tftp_root}/${name_ubi}\0" \ + "burn_ubi=nand erase.part ubifs; " \ + "nand write ${addr_ubi} ubifs ${filesize}\0" \ + "init_ramfs=run args_all args_ramfs get_fs_ramfs\0" \ + "args_ramfs=setenv bootargs ${bootargs} " \ + "rdinit=/sbin/init rw root=/dev/ram0 " \ + "initrd=0x802000000,9M\0" \ + "no_post=1\0" \ + "mtdparts=mtdparts=davinci_nand.0:" \ + "1024k(bootloader)ro,512k(params)ro,-(ubifs)\0" + +#define CONFIG_BOOTCOMMAND \ + "run init_${boot} get_fdt_${boot} get_mon_${boot} " \ + "get_kern_${boot} run_mon run_kern" + +#define CONFIG_BOOTARGS \ + +/* Linux interfacing */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_SYS_BARGSIZE 1024 +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x08000000) +#define CONFIG_LINUX_BOOT_PARAM_ADDR (CONFIG_SYS_SDRAM_BASE + 0x100) + +#define CONFIG_SUPPORT_RAW_INITRD + +/* we may include files below only after all above definitions */ +#include <asm/arch/hardware.h> +#include <asm/arch/clock.h> +#define CONFIG_SYS_HZ_CLOCK clk_get_rate(KS2_CLK1_6) + +/* Maximum memory size for relocated U-boot at the end of the DDR3 memory + which is NOT applicable for DDR ECC test */ +#define CONFIG_MAX_UBOOT_MEM_SIZE (4 << 20) /* 4 MiB */ + +#endif /* __CONFIG_KS2_EVM_H */ diff --git a/include/configs/mcx.h b/include/configs/mcx.h index 47244c00343..75abb602cf9 100644 --- a/include/configs/mcx.h +++ b/include/configs/mcx.h @@ -316,10 +316,6 @@ */ /* **** PISMO SUPPORT *** */ - -/* Configure the PISMO */ -#define PISMO1_NAND_SIZE GPMC_SIZE_128M - #define CONFIG_NAND_OMAP_GPMC #define CONFIG_ENV_IS_IN_NAND #define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */ diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index 53cb3902f3f..43c1617a5ef 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -220,8 +220,6 @@ #ifdef ONENAND_SUPPORT -#define PISMO1_NAND_SIZE GPMC_SIZE_128M -#define PISMO1_ONEN_SIZE GPMC_SIZE_128M #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP #define CONFIG_MTD_DEVICE #define CONFIG_MTD_PARTITIONS diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 9ba031d4ba5..644e97f4c4f 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -266,13 +266,8 @@ */ /* **** PISMO SUPPORT *** */ - -/* Configure the PISMO */ -#define PISMO1_NAND_SIZE GPMC_SIZE_128M -#define PISMO1_ONEN_SIZE GPMC_SIZE_128M - #if defined(CONFIG_CMD_NAND) -#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE +#define CONFIG_SYS_FLASH_BASE NAND_BASE #endif /* Monitor at start of flash */ @@ -309,5 +304,11 @@ #define CONFIG_SYS_NAND_ECCBYTES 3 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 +/* NAND: SPL falcon mode configs */ +#ifdef CONFIG_SPL_OS_BOOT +#define CONFIG_CMD_SPL_NAND_OFS 0x240000 +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 +#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000 +#endif #endif /* __CONFIG_H */ diff --git a/include/configs/omap3_evm_common.h b/include/configs/omap3_evm_common.h index ae4ce63f67f..739d392edc2 100644 --- a/include/configs/omap3_evm_common.h +++ b/include/configs/omap3_evm_common.h @@ -95,9 +95,6 @@ /* * PISMO support */ -#define PISMO1_NAND_SIZE GPMC_SIZE_128M -#define PISMO1_ONEN_SIZE GPMC_SIZE_128M - /* Monitor at start of flash - Reserve 2 sectors */ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE @@ -205,12 +202,12 @@ * NAND / OneNAND */ #if defined(CONFIG_CMD_NAND) -#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE +#define CONFIG_SYS_FLASH_BASE NAND_BASE #define CONFIG_NAND_OMAP_GPMC #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET #elif defined(CONFIG_CMD_ONENAND) -#define CONFIG_SYS_FLASH_BASE PISMO1_ONEN_BASE +#define CONFIG_SYS_FLASH_BASE ONENAND_MAP #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP #endif diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h index 79daabd6bbf..006c9a9c0da 100644 --- a/include/configs/omap3_igep00x0.h +++ b/include/configs/omap3_igep00x0.h @@ -146,8 +146,6 @@ */ #ifdef CONFIG_BOOT_ONENAND -#define PISMO1_ONEN_SIZE GPMC_SIZE_128M /* Configure the PISMO */ - #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ @@ -158,7 +156,6 @@ #endif #ifdef CONFIG_NAND -#define PISMO1_NAND_SIZE GPMC_SIZE_128M /* Configure the PISMO */ #define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */ #define CONFIG_ENV_IS_IN_NAND 1 #define CONFIG_ENV_SIZE (512 << 10) /* Total Size Environment */ @@ -199,6 +196,13 @@ #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 3 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 +/* NAND: SPL falcon mode configs */ +#ifdef CONFIG_SPL_OS_BOOT +#define CONFIG_CMD_SPL_NAND_OFS 0x240000 +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 +#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000 +#endif #endif #endif /* __IGEP00X0_H */ diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index 8dcbba3c40d..717c935d2c4 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -277,16 +277,12 @@ */ /* **** PISMO SUPPORT *** */ - -/* Configure the PISMO */ -#define PISMO1_NAND_SIZE GPMC_SIZE_128M - #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ #if defined(CONFIG_CMD_NAND) -#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE +#define CONFIG_SYS_FLASH_BASE NAND_BASE #elif defined(CONFIG_CMD_ONENAND) -#define CONFIG_SYS_FLASH_BASE PISMO1_ONEN_BASE +#define CONFIG_SYS_FLASH_BASE ONENAND_MAP #endif /* Monitor at start of flash */ diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index f7483a08278..e66f30655d6 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -173,12 +173,8 @@ 0x01F00000) /* 31MB */ /* FLASH and environment organization */ -/* Configure the PISMO */ -#define PISMO1_NAND_SIZE GPMC_SIZE_128M -#define PISMO1_ONEN_SIZE GPMC_SIZE_128M - #if defined(CONFIG_NAND) -#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE +#define CONFIG_SYS_FLASH_BASE NAND_BASE #endif /* Monitor at start of flash */ @@ -220,5 +216,11 @@ #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 +/* NAND: SPL falcon mode configs */ +#ifdef CONFIG_SPL_OS_BOOT +#define CONFIG_CMD_SPL_NAND_OFS 0x240000 +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 +#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000 +#endif #endif /* __CONFIG_H */ diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h index da67787e69e..c22c1fc6aaa 100644 --- a/include/configs/omap3_pandora.h +++ b/include/configs/omap3_pandora.h @@ -220,15 +220,10 @@ */ /* **** PISMO SUPPORT *** */ - -/* Configure the PISMO */ -#define PISMO1_NAND_SIZE GPMC_SIZE_128M -#define PISMO1_ONEN_SIZE GPMC_SIZE_128M - #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ #if defined(CONFIG_CMD_NAND) -#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE +#define CONFIG_SYS_FLASH_BASE NAND_BASE #endif /* Monitor at start of flash */ diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h index 3efe4cf8157..93f4d627a14 100644 --- a/include/configs/omap3_zoom1.h +++ b/include/configs/omap3_zoom1.h @@ -70,6 +70,12 @@ "4m(kernel),-(fs)" #if defined(CONFIG_CMD_NAND) +/* NAND: SPL falcon mode configs */ +#ifdef CONFIG_SPL_OS_BOOT +#define CONFIG_CMD_SPL_NAND_OFS 0x240000 +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 +#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000 +#endif #define CONFIG_CMD_NAND_LOCK_UNLOCK /* Enable lock/unlock support */ #endif @@ -165,13 +171,8 @@ */ /* **** PISMO SUPPORT *** */ - -/* Configure the PISMO */ -#define PISMO1_NAND_SIZE GPMC_SIZE_128M -#define PISMO1_ONEN_SIZE GPMC_SIZE_128M - #if defined(CONFIG_CMD_NAND) -#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE +#define CONFIG_SYS_FLASH_BASE NAND_BASE #endif /* Monitor at start of flash */ diff --git a/include/configs/pengwyn.h b/include/configs/pengwyn.h index 85104057a96..4684ad68522 100644 --- a/include/configs/pengwyn.h +++ b/include/configs/pengwyn.h @@ -159,6 +159,12 @@ #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */ #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ +/* NAND: SPL falcon mode configs */ +#ifdef CONFIG_SPL_OS_BOOT +#define CONFIG_CMD_SPL_NAND_OFS 0x240000 /* un-assigned */ +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 +#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000 +#endif /* * USB configuration. We enable MUSB support, both for host and for diff --git a/include/configs/sun4i.h b/include/configs/sun4i.h new file mode 100644 index 00000000000..037f9952f8f --- /dev/null +++ b/include/configs/sun4i.h @@ -0,0 +1,24 @@ +/* + * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net> + * + * Configuration settings for the Allwinner A10 (sun4i) CPU + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * A10 specific configuration + */ +#define CONFIG_SUN4I /* sun4i SoC generation */ +#define CONFIG_CLK_FULL_SPEED 1008000000 + +#define CONFIG_SYS_PROMPT "sun4i# " + +/* + * Include common sunxi configuration where most the settings are + */ +#include <configs/sunxi-common.h> + +#endif /* __CONFIG_H */ diff --git a/include/configs/sun5i.h b/include/configs/sun5i.h new file mode 100644 index 00000000000..c6138b7cd4f --- /dev/null +++ b/include/configs/sun5i.h @@ -0,0 +1,24 @@ +/* + * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net> + * + * Configuration settings for the Allwinner A13 (sun5i) CPU + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_SUN5I /* sun5i SoC generation */ +#define CONFIG_CLK_FULL_SPEED 1008000000 + +#define CONFIG_SYS_PROMPT "sun5i# " + +/* + * Include common sunxi configuration where most the settings are + */ +#include <configs/sunxi-common.h> + +#endif /* __CONFIG_H */ diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h index 9b693f70397..d9be1046b0c 100644 --- a/include/configs/sun7i.h +++ b/include/configs/sun7i.h @@ -13,6 +13,7 @@ * A20 specific configuration */ #define CONFIG_SUN7I /* sun7i SoC generation */ +#define CONFIG_CLK_FULL_SPEED 912000000 #define CONFIG_SYS_PROMPT "sun7i# " diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 5d72d62f14d..845b004a270 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -70,7 +70,6 @@ #define CONFIG_CMD_MMC #define CONFIG_MMC_SUNXI #define CONFIG_MMC_SUNXI_SLOT 0 -#define CONFIG_MMC_SUNXI_USE_DMA #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 /* first detected MMC controller */ @@ -162,7 +161,31 @@ #undef CONFIG_CMD_NET #undef CONFIG_CMD_NFS +/* I2C */ +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MVTWSI +#define CONFIG_SYS_I2C_SPEED 400000 +#define CONFIG_SYS_I2C_SLAVE 0x7f +#define CONFIG_CMD_I2C + +/* PMU */ +#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || defined CONFIG_AXP221_POWER +#define CONFIG_SPL_POWER_SUPPORT +#endif + +#ifndef CONFIG_CONS_INDEX #define CONFIG_CONS_INDEX 1 /* UART0 */ +#endif + +/* GPIO */ +#define CONFIG_SUNXI_GPIO +#define CONFIG_CMD_GPIO + +/* Ethernet support */ +#ifdef CONFIG_SUNXI_EMAC +#define CONFIG_MII /* MII PHY management */ +#endif #ifdef CONFIG_SUNXI_GMAC #define CONFIG_DESIGNWARE_ETH /* GMAC can use designware driver */ @@ -188,6 +211,8 @@ #define CONFIG_ENV_IS_NOWHERE #endif +#define CONFIG_MISC_INIT_R + #ifndef CONFIG_SPL_BUILD #include <config_distro_defaults.h> #endif diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h index 0c2f0f19c82..aa0ea162d25 100644 --- a/include/configs/tam3517-common.h +++ b/include/configs/tam3517-common.h @@ -181,10 +181,6 @@ */ /* **** PISMO SUPPORT *** */ - -/* Configure the PISMO */ -#define PISMO1_NAND_SIZE GPMC_SIZE_128M - #define CONFIG_NAND #define CONFIG_NAND_OMAP_GPMC #define CONFIG_ENV_IS_IN_NAND diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h index 1b0fee9a808..9fc31bed6ad 100644 --- a/include/configs/tao3530.h +++ b/include/configs/tao3530.h @@ -22,6 +22,7 @@ #define CONFIG_OMAP_GPIO #define CONFIG_OMAP_COMMON +#define CONFIG_SYS_GENERIC_BOARD #define MACH_TYPE_OMAP3_TAO3530 2836 @@ -253,13 +254,8 @@ */ /* **** PISMO SUPPORT *** */ - -/* Configure the PISMO */ -#define PISMO1_NAND_SIZE GPMC_SIZE_128M -#define PISMO1_ONEN_SIZE GPMC_SIZE_128M - #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ -#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE +#define CONFIG_SYS_FLASH_BASE NAND_BASE /* Monitor at start of flash */ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index 6e0bf090588..85c027c1d27 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -243,13 +243,6 @@ #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */ #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */ -/* NAND */ -#ifdef CONFIG_NAND -#define CONFIG_CMD_SPL_NAND_OFS 0x240000 /* end of u-boot */ -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 -#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000 -#endif - /* spl export command */ #define CONFIG_CMD_SPL #endif @@ -275,7 +268,6 @@ #define CONFIG_SPL_NAND_ECC #define CONFIG_SPL_MTD_SUPPORT #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 #endif #endif /* !CONFIG_NOR_BOOT */ diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h index 80985a2655a..6c2f65305f0 100644 --- a/include/configs/tricorder.h +++ b/include/configs/tricorder.h @@ -35,6 +35,8 @@ #include <asm/arch/cpu.h> /* get chip and board defs */ #include <asm/arch/omap3.h> +#define CONFIG_SYS_GENERIC_BOARD + /* Display CPU and Board information */ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO @@ -315,8 +317,6 @@ #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 /* NAND and environment organization */ -#define PISMO1_NAND_SIZE GPMC_SIZE_128M - #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index fa252c0b13e..690cacbc94b 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -339,4 +339,6 @@ #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_GENERIC_BOARD + #endif /* __CONFIG_ZYNQ_COMMON_H */ diff --git a/include/cpsw.h b/include/cpsw.h index a73843d2f75..547b40c57bb 100644 --- a/include/cpsw.h +++ b/include/cpsw.h @@ -44,6 +44,7 @@ struct cpsw_platform_data { struct cpsw_slave_data *slave_data; void (*control)(int enabled); u32 host_port_num; + u32 active_slave; u8 version; }; diff --git a/include/netdev.h b/include/netdev.h index 63481eca226..e45dd7abec3 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -78,8 +78,8 @@ int sh_eth_initialize(bd_t *bis); int skge_initialize(bd_t *bis); int smc91111_initialize(u8 dev_num, int base_addr); int smc911x_initialize(u8 dev_num, int base_addr); +int sunxi_emac_initialize(bd_t *bis); int sunxi_gmac_initialize(bd_t *bis); -int sunxi_wemac_initialize(bd_t *bis); int tsi108_eth_initialize(bd_t *bis); int uec_standard_init(bd_t *bis); int uli526x_initialize(bd_t *bis); diff --git a/include/power/pmic.h b/include/power/pmic.h index a62e6c90a5e..afbc5aab7e2 100644 --- a/include/power/pmic.h +++ b/include/power/pmic.h @@ -79,6 +79,7 @@ struct pmic { }; int pmic_init(unsigned char bus); +int power_init_board(void); int pmic_dialog_init(unsigned char bus); int check_reg(struct pmic *p, u32 reg); struct pmic *pmic_alloc(void); diff --git a/include/power/tps65218.h b/include/power/tps65218.h index 67aa2f8c8d4..f8f33b8b16b 100644 --- a/include/power/tps65218.h +++ b/include/power/tps65218.h @@ -60,4 +60,5 @@ enum { int tps65218_reg_write(uchar prot_level, uchar dest_reg, uchar dest_val, uchar mask); int tps65218_voltage_update(uchar dc_cntrl_reg, uchar volt_sel); +int power_tps65218_init(unsigned char bus); #endif /* __POWER_TPS65218_H__ */ |