diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/bcm28155_ap.h | 20 | ||||
| -rw-r--r-- | include/configs/bur_am335x_common.h | 67 | ||||
| -rw-r--r-- | include/configs/bur_cfg_common.h | 64 | ||||
| -rw-r--r-- | include/configs/cm_t43.h | 15 | ||||
| -rw-r--r-- | include/configs/kwb.h | 19 | ||||
| -rw-r--r-- | include/configs/ls1021aqds.h | 23 | ||||
| -rw-r--r-- | include/configs/ls1043aqds.h | 13 | ||||
| -rw-r--r-- | include/configs/ls1043ardb.h | 7 | ||||
| -rw-r--r-- | include/configs/ls2080a_common.h | 11 | ||||
| -rw-r--r-- | include/configs/ls2080aqds.h | 4 | ||||
| -rw-r--r-- | include/configs/ls2080ardb.h | 6 | ||||
| -rw-r--r-- | include/configs/odroid_xu3.h | 1 | ||||
| -rw-r--r-- | include/configs/omap3_logic.h | 2 | ||||
| -rw-r--r-- | include/configs/rpi-common.h | 1 | ||||
| -rw-r--r-- | include/configs/stm32f746-disco.h | 89 | ||||
| -rw-r--r-- | include/configs/tseries.h | 14 | ||||
| -rw-r--r-- | include/dfu.h | 25 | ||||
| -rw-r--r-- | include/dm/platform_data/serial_stm32x7.h | 17 | ||||
| -rw-r--r-- | include/fsl_fman.h | 1 | ||||
| -rw-r--r-- | include/fsl_qe.h | 299 | ||||
| -rw-r--r-- | include/power/tps65218.h | 12 |
21 files changed, 587 insertions, 123 deletions
diff --git a/include/configs/bcm28155_ap.h b/include/configs/bcm28155_ap.h index a257084a03c..c9515a8cb8f 100644 --- a/include/configs/bcm28155_ap.h +++ b/include/configs/bcm28155_ap.h @@ -130,7 +130,6 @@ #define CONFIG_CMD_BOOTZ #define CONFIG_FAT_WRITE - /* Fastboot and USB OTG */ #define CONFIG_USB_FUNCTION_FASTBOOT #define CONFIG_CMD_FASTBOOT @@ -150,23 +149,4 @@ #define CONFIG_G_DNL_PRODUCT_NUM 0x0d02 /* nexus one */ #define CONFIG_G_DNL_MANUFACTURER "Broadcom Corporation" -/* Fastboot and USB OTG */ -#define CONFIG_USB_FUNCTION_FASTBOOT -#define CONFIG_CMD_FASTBOOT -#define CONFIG_FASTBOOT_FLASH -#define CONFIG_FASTBOOT_FLASH_MMC_DEV 0 -#define CONFIG_SYS_CACHELINE_SIZE 64 -#define CONFIG_USB_FASTBOOT_BUF_SIZE (CONFIG_SYS_SDRAM_SIZE - SZ_1M) -#define CONFIG_USB_FASTBOOT_BUF_ADDR CONFIG_SYS_SDRAM_BASE -#define CONFIG_USB_GADGET -#define CONFIG_USB_GADGET_DUALSPEED -#define CONFIG_USB_GADGET_VBUS_DRAW 0 -#define CONFIG_USB_GADGET_S3C_UDC_OTG -#define CONFIG_USB_GADGET_BCM_UDC_OTG_PHY -#define CONFIG_USB_GADGET_DOWNLOAD -#define CONFIG_USBID_ADDR 0x34052c46 -#define CONFIG_G_DNL_VENDOR_NUM 0x18d1 /* google */ -#define CONFIG_G_DNL_PRODUCT_NUM 0x0d02 /* nexus one */ -#define CONFIG_G_DNL_MANUFACTURER "Broadcom Corporation" - #endif /* __BCM28155_AP_H */ diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h index ffc6811bb91..a94b1e27115 100644 --- a/include/configs/bur_am335x_common.h +++ b/include/configs/bur_am335x_common.h @@ -3,7 +3,7 @@ * * common parts used by B&R AM335x based boards * - * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at> - + * Copyright (C) 2016 Hannes Schmelzer <oe5hpm@oevsv.at> - * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com * * SPDX-License-Identifier: GPL-2.0+ @@ -12,25 +12,9 @@ #ifndef __BUR_AM335X_COMMON_H__ #define __BUR_AM335X_COMMON_H__ /* ------------------------------------------------------------------------- */ -#define BUR_COMMON_ENV \ -"usbscript=usb start && fatload usb 0 0x80000000 usbscript.img && source\0" \ -"brdefaultip=if test -r ${ipaddr}; then; else" \ -" setenv ipaddr 192.168.60.1; setenv serverip 192.168.60.254;" \ -" setenv gatewayip 192.168.60.254; setenv netmask 255.255.255.0; fi;\0" \ -"netconsole=echo switching to network console ...; " \ -"if dhcp; then; else run brdefaultip; fi; setenv ncip ${serverip}; " \ -"setcurs 1 9; lcdputs myip; setcurs 10 9; lcdputs ${ipaddr};" \ -"setcurs 1 10;lcdputs serverip; setcurs 10 10; lcdputs ${serverip};" \ -"setenv stdout nc;setenv stdin nc;setenv stderr nc\0" - -#define CONFIG_PREBOOT "run brdefaultip" -#define CONFIG_CMD_TIME - - #define CONFIG_AM33XX #define CONFIG_OMAP #define CONFIG_OMAP_COMMON -#define CONFIG_BOARD_LATE_INIT #define CONFIG_SYS_CACHELINE_SIZE 64 #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ @@ -53,24 +37,11 @@ #define CONFIG_BAUDRATE 115200 /* Network defines */ -#define CONFIG_CMD_DHCP -#define CONFIG_BOOTP_DNS /* Configurable parts of CMD_DHCP */ -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_NET_RETRY_COUNT 2 -#define CONFIG_CMD_PING #define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */ #define CONFIG_MII /* Required in net/eth.c */ -#define CONFIG_SPL_ETH_SUPPORT #define CONFIG_PHYLIB #define CONFIG_PHY_NATSEMI -#define CONFIG_SPL_NET_SUPPORT -#define CONFIG_SPL_ENV_SUPPORT /* used for a fetching MAC-Address */ -#define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL" -/* Network console */ -#define CONFIG_NETCONSOLE 1 -#define CONFIG_BOOTP_MAY_FAIL /* if we don't have DHCP environment */ + /* * SPL related defines. The Public RAM memory map the ROM defines the * area between 0x402F0400 and 0x4030B800 as a download area and @@ -109,42 +80,8 @@ #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 #define CONFIG_SYS_I2C_OMAP24XX -#define CONFIG_CMD_I2C /* GPIO */ #define CONFIG_OMAP_GPIO -/* - * ---------------------------------------------------------------------------- - * The following are general good-enough settings for U-Boot. We set a - * large malloc pool as we generally have a lot of DDR, and we opt for - * function over binary size in the main portion of U-Boot as this is - * generally easily constrained later if needed. We enable the config - * options that give us information in the environment about what board - * we are on so we do not need to rely on the command prompt. We set a - * console baudrate of 115200 and use the default baud rate table. - */ -#define CONFIG_SYS_MALLOC_LEN (5120 << 10) -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_CONSOLE_INFO_QUIET -#define CONFIG_ENV_OVERWRITE /* Overwrite ethaddr / serial# */ -#define CONFIG_SYS_CONSOLE_IS_IN_ENV -#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE - -/* As stated above, the following choices are optional. */ -#define CONFIG_SYS_LONGHELP -#define CONFIG_AUTO_COMPLETE -#define CONFIG_CMDLINE_EDITING -#define CONFIG_VERSION_VARIABLE - -/* We set the max number of command args high to avoid HUSH bugs. */ -#define CONFIG_SYS_MAXARGS 64 - -/* Console I/O Buffer Size */ -#define CONFIG_SYS_CBSIZE 512 -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE +\ - sizeof(CONFIG_SYS_PROMPT) + 16) -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* * Our platforms make use of SPL to initalize the hardware (primarily diff --git a/include/configs/bur_cfg_common.h b/include/configs/bur_cfg_common.h new file mode 100644 index 00000000000..f1837752ca5 --- /dev/null +++ b/include/configs/bur_cfg_common.h @@ -0,0 +1,64 @@ +/* + * bur_cfg_common.h + * + * common parts used over all B&R boards + * + * Copyright (C) 2016 Hannes Schmelzer <oe5hpm@oevsv.at> - + * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __BUR_CFG_COMMON_H__ +#define __BUR_CFG_COMMON_H__ +/* ------------------------------------------------------------------------- */ +#define BUR_COMMON_ENV \ +"usbscript=usb start && fatload usb 0 ${scradr} usbscript.img &&" \ +" source ${scradr}\0" \ +"brdefaultip=if test -r ${ipaddr}; then; else" \ +" setenv ipaddr 192.168.60.1; setenv serverip 192.168.60.254;" \ +" setenv gatewayip 192.168.60.254; setenv netmask 255.255.255.0; fi;\0" \ +"netconsole=echo switching to network console ...; " \ +"if dhcp; then; else run brdefaultip; fi; setenv ncip ${serverip}; " \ +"setcurs 1 9; lcdputs myip; setcurs 10 9; lcdputs ${ipaddr};" \ +"setcurs 1 10;lcdputs serverip; setcurs 10 10; lcdputs ${serverip};" \ +"setenv stdout nc;setenv stdin nc;setenv stderr nc\0" + +#define CONFIG_PREBOOT "run cfgscr; run brdefaultip" + +#define CONFIG_BOARD_LATE_INIT + +/* Network defines */ +#define CONFIG_BOOTP_DNS /* Configurable parts of CMD_DHCP */ +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_NET_RETRY_COUNT 2 + +/* Network console */ +#define CONFIG_NETCONSOLE 1 +#define CONFIG_BOOTP_MAY_FAIL /* if we don't have DHCP environment */ + +#define CONFIG_SYS_CONSOLE_INFO_QUIET +#define CONFIG_ENV_OVERWRITE /* Overwrite ethaddr / serial# */ +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE + +/* As stated above, the following choices are optional. */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_VERSION_VARIABLE + +/* We set the max number of command args high to avoid HUSH bugs. */ +#define CONFIG_SYS_MAXARGS 64 + +/* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 512 +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE +\ + sizeof(CONFIG_SYS_PROMPT) + 16) +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#endif /* __BUR_CFG_COMMON_H__ */ diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h index d3cd38d70f3..1c1951c4c5f 100644 --- a/include/configs/cm_t43.h +++ b/include/configs/cm_t43.h @@ -18,10 +18,12 @@ #include <asm/arch/omap.h> /* Serial support */ -#define CONFIG_DM_SERIAL #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_CLK 48000000 #define CONFIG_SYS_NS16550_COM1 0x44e09000 +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#endif /* NAND support */ #define CONFIG_NAND @@ -68,9 +70,7 @@ #define CONFIG_AM437X_USB2PHY2_HOST /* SPI Flash support */ -#define CONFIG_SPI_FLASH #define CONFIG_TI_SPI_MMAP -#define CONFIG_SPI_FLASH_BAR #define CONFIG_SF_DEFAULT_SPEED 48000000 #define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3 @@ -98,9 +98,8 @@ #undef CONFIG_SPL_OS_BOOT #undef CONFIG_SPL_GPIO_SUPPORT #undef CONFIG_SPL_NAND_SUPPORT -#undef CONFIG_SPL_BOARD_INIT -#undef CONFIG_BOOTDELAY -#include <config_distro_defaults.h> +#undef CONFIG_SYS_MONITOR_LEN +#undef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR #define CONFIG_ZERO_BOOTDELAY_CHECK #undef CONFIG_CMD_IMLS @@ -165,8 +164,12 @@ #define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + (128 << 20)) #define CONFIG_SPL_POWER_SUPPORT #define CONFIG_SYS_SPI_U_BOOT_OFFS (256 * 1024) +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x480 #define CONFIG_SPL_SPI_SUPPORT #define CONFIG_SPL_SPI_FLASH_SUPPORT #define CONFIG_SPL_SPI_LOAD +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_POWER_SUPPORT #endif /* __CONFIG_CM_T43_H */ diff --git a/include/configs/kwb.h b/include/configs/kwb.h index 45253b8118a..60e6496fad3 100644 --- a/include/configs/kwb.h +++ b/include/configs/kwb.h @@ -12,6 +12,7 @@ #ifndef __CONFIG_KWB_H__ #define __CONFIG_KWB_H__ +#include <configs/bur_cfg_common.h> #include <configs/bur_am335x_common.h> /* ------------------------------------------------------------------------- */ #define CONFIG_AM335X_LCD @@ -27,6 +28,9 @@ #define CONFIG_BMP_24BMP #define CONFIG_BMP_32BPP +/* memory */ +#define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024) + /* Clock Defines */ #define V_OSCK 26000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) @@ -103,10 +107,9 @@ BUR_COMMON_ENV \ #define CONFIG_BOOTDELAY 0 /* undefine command which we not need here */ -#undef CONFIG_BOOTM_NETBSD -#undef CONFIG_BOOTM_PLAN9 -#undef CONFIG_BOOTM_RTEMS -#undef CONFIG_CMD_CRC32 +#undef CONFIG_BOOTM_NETBSD +#undef CONFIG_BOOTM_PLAN9 +#undef CONFIG_BOOTM_RTEMS /* Support both device trees and ATAGs. */ #define CONFIG_OF_LIBFDT @@ -122,17 +125,11 @@ BUR_COMMON_ENV \ #define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT /* attention! not only for gadget, enables also highspeed in hostmode */ #define CONFIG_USB_GADGET_DUALSPEED -#define CONFIG_USB_MUSB_HOST #define CONFIG_AM335X_USB0 #define CONFIG_AM335X_USB0_MODE MUSB_HOST #define CONFIG_AM335X_USB1 #define CONFIG_AM335X_USB1_MODE MUSB_HOST -#ifdef CONFIG_USB_MUSB_HOST -#define CONFIG_CMD_USB -#define CONFIG_USB_STORAGE -#endif /* CONFIG_USB_MUSB_HOST */ - #undef CONFIG_ENV_IS_NOWHERE #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 @@ -151,4 +148,4 @@ BUR_COMMON_ENV \ #define CONFIG_CMD_FS_GENERIC #endif /* CONFIG_MMC, ... */ -#endif /* ! __CONFIG_TSERIES_H__ */ +#endif /* __CONFIG_KWB_H__ */ diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index f6efc55059a..39d747f55ea 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -42,7 +42,7 @@ unsigned long get_board_sys_clk(void); unsigned long get_board_ddr_clk(void); #endif -#ifdef CONFIG_QSPI_BOOT +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_SYS_CLK_FREQ 100000000 #define CONFIG_DDR_CLK_FREQ 100000000 #define CONFIG_QIXIS_I2C_ACCESS @@ -56,7 +56,13 @@ unsigned long get_board_ddr_clk(void); #endif #ifdef CONFIG_SD_BOOT -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg +#ifdef CONFIG_SD_BOOT_QSPI +#define CONFIG_SYS_FSL_PBL_RCW \ + board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg +#else +#define CONFIG_SYS_FSL_PBL_RCW \ + board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg +#endif #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" #define CONFIG_SPL_LIBCOMMON_SUPPORT @@ -87,6 +93,9 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_QSPI_BOOT #define CONFIG_SYS_TEXT_BASE 0x40010000 +#endif + +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_SYS_NO_FLASH #endif @@ -162,7 +171,7 @@ unsigned long get_board_ddr_clk(void); /* * IFC Definitions */ -#ifndef CONFIG_QSPI_BOOT +#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_FSL_IFC #define CONFIG_SYS_FLASH_BASE 0x60000000 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE @@ -375,7 +384,9 @@ unsigned long get_board_ddr_clk(void); #else #define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550_SERIAL +#ifndef CONFIG_DM_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 +#endif #define CONFIG_SYS_NS16550_CLK get_serial_clock() #endif @@ -410,7 +421,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_DOS_PARTITION /* SPI */ -#ifdef CONFIG_QSPI_BOOT +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) /* QSPI */ #define QSPI0_AMBA_BASE 0x40000000 #define FSL_QSPI_FLASH_SIZE (1 << 24) @@ -555,6 +566,10 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMDLINE_TAG #define CONFIG_CMDLINE_EDITING +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) +#undef CONFIG_CMD_IMLS +#endif + #define CONFIG_ARMV7_NONSEC #define CONFIG_ARMV7_VIRT #define CONFIG_PEN_ADDR_BIG_ENDIAN diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index 4ab8e13ba1a..158cf027634 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -379,6 +379,19 @@ unsigned long get_board_ddr_clk(void); #endif #endif +/* USB */ +#define CONFIG_HAS_FSL_XHCI_USB +#ifdef CONFIG_HAS_FSL_XHCI_USB +#define CONFIG_USB_XHCI +#define CONFIG_USB_XHCI_FSL +#define CONFIG_USB_XHCI_DWC3 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_EXT2 +#endif + /* * Miscellaneous configurable options */ diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index 506f50d8955..bc40b06a89f 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -268,6 +268,13 @@ #define CONFIG_ETHPRIME "FM1@DTSEC3" #endif +/* QE */ +#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ + !defined(CONFIG_QSPI_BOOT) +#define CONFIG_U_QE +#endif +#define CONFIG_SYS_QE_FW_ADDR 0x60600000 + /* USB */ #define CONFIG_HAS_FSL_XHCI_USB #ifdef CONFIG_HAS_FSL_XHCI_USB diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index def0a6f3f09..64b82e83881 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -264,14 +264,17 @@ unsigned long long get_qixis_addr(void); "kernel_start=0x581200000\0" \ "kernel_load=0xa0000000\0" \ "kernel_size=0x2800000\0" \ - "console=ttyAMA0,38400n8\0" + "console=ttyAMA0,38400n8\0" \ + "mcinitcmd=fsl_mc start mc 0x580300000" \ + " 0x580800000 \0" #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ "earlycon=uart8250,mmio,0x21c0500" \ "ramdisk_size=0x2000000 default_hugepagesz=2m" \ - " hugepagesz=2m hugepages=16" -#define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ - "$kernel_size && bootm $kernel_load" + " hugepagesz=2m hugepages=256" +#define CONFIG_BOOTCOMMAND "fsl_mc apply dpl 0x580700000 &&" \ + " cp.b $kernel_start $kernel_load" \ + " $kernel_size && bootm $kernel_load" #define CONFIG_BOOTDELAY 10 /* Monitor Command Prompt */ diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index a402c06a3bd..dab38208f5a 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -346,7 +346,9 @@ unsigned long get_board_ddr_clk(void); "initrd_high=0xffffffffffffffff\0" \ "kernel_start=0x581100000\0" \ "kernel_load=0xa0000000\0" \ - "kernel_size=0x2800000\0" + "kernel_size=0x2800000\0" \ + "mcinitcmd=fsl_mc start mc 0x580300000" \ + " 0x580800000 \0" #ifdef CONFIG_FSL_MC_ENET #define CONFIG_FSL_MEMAC diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 116dbcde5b7..b2c0181132a 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -327,13 +327,15 @@ unsigned long get_board_sys_clk(void); "initrd_high=0xffffffffffffffff\0" \ "kernel_start=0x581100000\0" \ "kernel_load=0xa0000000\0" \ - "kernel_size=0x2800000\0" + "kernel_size=0x2800000\0" \ + "mcinitcmd=fsl_mc start mc 0x580300000" \ + " 0x580800000 \0" #undef CONFIG_BOOTARGS #define CONFIG_BOOTARGS "console=ttyS1,115200 root=/dev/ram0 " \ "earlycon=uart8250,mmio,0x21c0600" \ "ramdisk_size=0x2000000 default_hugepagesz=2m" \ - " hugepagesz=2m hugepages=16" + " hugepagesz=2m hugepages=256" /* MAC/PHY configuration */ #ifdef CONFIG_FSL_MC_ENET diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h index 648e48bcf4b..500f0f9d4f9 100644 --- a/include/configs/odroid_xu3.h +++ b/include/configs/odroid_xu3.h @@ -69,6 +69,7 @@ #define CONFIG_CMD_DFU #define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M #define DFU_DEFAULT_POLL_TIMEOUT 300 +#define DFU_MANIFEST_POLL_TIMEOUT 25000 /* THOR */ #define CONFIG_G_DNL_THOR_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index fba2a1256b8..0fc9d1c4e13 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -40,7 +40,7 @@ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO - +#define CONFIG_BOARD_LATE_INIT #define CONFIG_MISC_INIT_R /* misc_init_r dumps the die id */ #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS diff --git a/include/configs/rpi-common.h b/include/configs/rpi-common.h index 97e5d2c7952..e07fa6566e6 100644 --- a/include/configs/rpi-common.h +++ b/include/configs/rpi-common.h @@ -68,6 +68,7 @@ #define CONFIG_FB_ADDR 0 #define CONFIG_VIDEO_BCM2835 #define CONFIG_SYS_WHITE_ON_BLACK +#define CONFIG_CONSOLE_SCROLL_LINES 10 /* SD/MMC configuration */ #define CONFIG_GENERIC_MMC diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h new file mode 100644 index 00000000000..e1b8bcb084d --- /dev/null +++ b/include/configs/stm32f746-disco.h @@ -0,0 +1,89 @@ +/* + * (C) Copyright 2016 + * Vikas Manocha, <vikas.manocha@st.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_SYS_THUMB_BUILD +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_OF_LIBFDT +#define CONFIG_BOARD_EARLY_INIT_F + +#define CONFIG_SYS_FLASH_BASE 0x08000000 +#define CONFIG_SYS_INIT_SP_ADDR 0x20050000 +#define CONFIG_SYS_TEXT_BASE 0x08000000 + +#define CONFIG_SYS_ICACHE_OFF +#define CONFIG_SYS_DCACHE_OFF + +/* + * Configuration of the external SDRAM memory + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_RAM_SIZE ((64 + 192) << 10) +#define CONFIG_SYS_RAM_CS 1 +#define CONFIG_SYS_RAM_FREQ_DIV 2 +#define CONFIG_SYS_RAM_BASE 0x20000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_RAM_BASE +#define CONFIG_SYS_LOAD_ADDR 0x20000000 +#define CONFIG_LOADADDR 0x20000000 + +#define CONFIG_SYS_MAX_FLASH_SECT 12 +#define CONFIG_SYS_MAX_FLASH_BANKS 2 + +#ifndef CONFIG_SYS_NO_FLASH +#define CONFIG_ENV_IS_IN_FLASH +#else +#define CONFIG_ENV_IS_NOWHERE +#endif +#define CONFIG_ENV_SIZE (8 << 10) + +#define CONFIG_STM32_GPIO +#define CONFIG_STM32X7_SERIAL + +#define CONFIG_SYS_CLK_FREQ 16*1000*1000 /* 180 MHz */ +#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ + + sizeof(CONFIG_SYS_PROMPT) + 16) + +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_MALLOC_LEN (16 * 1024) +#define CONFIG_STACKSIZE (64 << 10) + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTARGS \ + "console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel" +#define CONFIG_BOOTCOMMAND \ + "run bootcmd_romfs" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootargs_romfs=uclinux.physaddr=0x08180000 root=/dev/mtdblock0\0" \ + "bootcmd_romfs=setenv bootargs ${bootargs} ${bootargs_romfs};" \ + "bootm 0x08044000 - 0x08042000\0" + +#define CONFIG_BOOTDELAY 3 + +/* + * Command line configuration. + */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING + +#define CONFIG_CMD_MEM +#define CONFIG_CMD_TIMER +#undef CONFIG_CMD_IMLS +#endif /* __CONFIG_H */ diff --git a/include/configs/tseries.h b/include/configs/tseries.h index 93e34544cb5..43cf9658f33 100644 --- a/include/configs/tseries.h +++ b/include/configs/tseries.h @@ -12,6 +12,7 @@ #ifndef __CONFIG_TSERIES_H__ #define __CONFIG_TSERIES_H__ +#include <configs/bur_cfg_common.h> #include <configs/bur_am335x_common.h> /* ------------------------------------------------------------------------- */ #define CONFIG_AM335X_LCD @@ -30,6 +31,10 @@ #define CONFIG_SYS_BOOTCOUNT_ADDR 0x44E3E000 #define CONFIG_BOOTCOUNT_LIMIT #define CONFIG_BOOTCOUNT_AM33XX + +/* memory */ +#define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024) + /* Clock Defines */ #define V_OSCK 26000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) @@ -204,7 +209,6 @@ MMCARGS #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x8000000 #define CONFIG_NAND_OMAP_GPMC -#define CONFIG_CMD_NAND /* don't change OMAP_ELM, ECCSCHEME. ROM code only supports this */ #define CONFIG_NAND_OMAP_ELM #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW @@ -249,23 +253,15 @@ MMCARGS #define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT /* attention! not only for gadget, enables also highspeed in hostmode */ #define CONFIG_USB_GADGET_DUALSPEED -#define CONFIG_USB_MUSB_HOST #define CONFIG_AM335X_USB0 #define CONFIG_AM335X_USB0_MODE MUSB_HOST #define CONFIG_AM335X_USB1 #define CONFIG_AM335X_USB1_MODE MUSB_HOST -#ifdef CONFIG_USB_MUSB_HOST -#define CONFIG_CMD_USB -#define CONFIG_USB_STORAGE -#endif /* CONFIG_USB_MUSB_HOST */ - #if defined(CONFIG_SPI_BOOT) /* McSPI IP block */ #define CONFIG_SPI #define CONFIG_OMAP3_SPI -#define CONFIG_CMD_SPI -#define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 24000000 #define CONFIG_SPL_SPI_SUPPORT diff --git a/include/dfu.h b/include/dfu.h index 6118dc27b95..f39d3f1171a 100644 --- a/include/dfu.h +++ b/include/dfu.h @@ -163,6 +163,31 @@ int dfu_read(struct dfu_entity *de, void *buf, int size, int blk_seq_num); int dfu_write(struct dfu_entity *de, void *buf, int size, int blk_seq_num); int dfu_flush(struct dfu_entity *de, void *buf, int size, int blk_seq_num); +/* + * dfu_defer_flush - pointer to store dfu_entity for deferred flashing. + * It should be NULL when not used. + */ +extern struct dfu_entity *dfu_defer_flush; +/** + * dfu_get_defer_flush - get current value of dfu_defer_flush pointer + * + * @return - value of the dfu_defer_flush pointer + */ +static inline struct dfu_entity *dfu_get_defer_flush(void) +{ + return dfu_defer_flush; +} + +/** + * dfu_set_defer_flush - set the dfu_defer_flush pointer + * + * @param dfu - pointer to the dfu_entity, which should be written + */ +static inline void dfu_set_defer_flush(struct dfu_entity *dfu) +{ + dfu_defer_flush = dfu; +} + /** * dfu_write_from_mem_addr - write data from memory to DFU managed medium * diff --git a/include/dm/platform_data/serial_stm32x7.h b/include/dm/platform_data/serial_stm32x7.h new file mode 100644 index 00000000000..328a8a3ff22 --- /dev/null +++ b/include/dm/platform_data/serial_stm32x7.h @@ -0,0 +1,17 @@ +/* + * (C) Copyright 2016 + * Vikas Manocha, <vikas.manocha@st.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __SERIAL_STM32x7_H +#define __SERIAL_STM32x7_H + +/* Information about a serial port */ +struct stm32x7_serial_platdata { + struct stm32_usart *base; /* address of registers in physical memory */ + unsigned int clock; +}; + +#endif /* __SERIAL_STM32x7_H */ diff --git a/include/fsl_fman.h b/include/fsl_fman.h index 4d04415ba8c..f3e35f8c6b8 100644 --- a/include/fsl_fman.h +++ b/include/fsl_fman.h @@ -460,4 +460,5 @@ typedef struct ccsr_fman { u8 res5[4*1024]; } ccsr_fman_t; +void fdt_fixup_fman_firmware(void *blob); #endif /*__FSL_FMAN_H__*/ diff --git a/include/fsl_qe.h b/include/fsl_qe.h new file mode 100644 index 00000000000..77b18e928ff --- /dev/null +++ b/include/fsl_qe.h @@ -0,0 +1,299 @@ +/* + * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. + * + * Dave Liu <daveliu@freescale.com> + * based on source code of Shlomi Gridish + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __QE_H__ +#define __QE_H__ + +#include "common.h" +#ifdef CONFIG_U_QE +#include <linux/immap_qe.h> +#endif + +#define QE_NUM_OF_BRGS 16 +#define UCC_MAX_NUM 8 + +#define QE_DATAONLY_BASE 0 +#define QE_DATAONLY_SIZE (QE_MURAM_SIZE - QE_DATAONLY_BASE) + +/* QE threads SNUM +*/ +typedef enum qe_snum_state { + QE_SNUM_STATE_USED, /* used */ + QE_SNUM_STATE_FREE /* free */ +} qe_snum_state_e; + +typedef struct qe_snum { + u8 num; /* snum */ + qe_snum_state_e state; /* state */ +} qe_snum_t; + +/* QE RISC allocation +*/ +#define QE_RISC_ALLOCATION_RISC1 0x1 /* RISC 1 */ +#define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */ +#define QE_RISC_ALLOCATION_RISC3 0x4 /* RISC 3 */ +#define QE_RISC_ALLOCATION_RISC4 0x8 /* RISC 4 */ +#define QE_RISC_ALLOCATION_RISC1_AND_RISC2 (QE_RISC_ALLOCATION_RISC1 | \ + QE_RISC_ALLOCATION_RISC2) +#define QE_RISC_ALLOCATION_FOUR_RISCS (QE_RISC_ALLOCATION_RISC1 | \ + QE_RISC_ALLOCATION_RISC2 | \ + QE_RISC_ALLOCATION_RISC3 | \ + QE_RISC_ALLOCATION_RISC4) + +/* QE CECR commands for UCC fast. +*/ +#define QE_CR_FLG 0x00010000 +#define QE_RESET 0x80000000 +#define QE_INIT_TX_RX 0x00000000 +#define QE_INIT_RX 0x00000001 +#define QE_INIT_TX 0x00000002 +#define QE_ENTER_HUNT_MODE 0x00000003 +#define QE_STOP_TX 0x00000004 +#define QE_GRACEFUL_STOP_TX 0x00000005 +#define QE_RESTART_TX 0x00000006 +#define QE_SWITCH_COMMAND 0x00000007 +#define QE_SET_GROUP_ADDRESS 0x00000008 +#define QE_INSERT_CELL 0x00000009 +#define QE_ATM_TRANSMIT 0x0000000a +#define QE_CELL_POOL_GET 0x0000000b +#define QE_CELL_POOL_PUT 0x0000000c +#define QE_IMA_HOST_CMD 0x0000000d +#define QE_ATM_MULTI_THREAD_INIT 0x00000011 +#define QE_ASSIGN_PAGE 0x00000012 +#define QE_START_FLOW_CONTROL 0x00000014 +#define QE_STOP_FLOW_CONTROL 0x00000015 +#define QE_ASSIGN_PAGE_TO_DEVICE 0x00000016 +#define QE_GRACEFUL_STOP_RX 0x0000001a +#define QE_RESTART_RX 0x0000001b + +/* QE CECR Sub Block Code - sub block code of QE command. +*/ +#define QE_CR_SUBBLOCK_INVALID 0x00000000 +#define QE_CR_SUBBLOCK_USB 0x03200000 +#define QE_CR_SUBBLOCK_UCCFAST1 0x02000000 +#define QE_CR_SUBBLOCK_UCCFAST2 0x02200000 +#define QE_CR_SUBBLOCK_UCCFAST3 0x02400000 +#define QE_CR_SUBBLOCK_UCCFAST4 0x02600000 +#define QE_CR_SUBBLOCK_UCCFAST5 0x02800000 +#define QE_CR_SUBBLOCK_UCCFAST6 0x02a00000 +#define QE_CR_SUBBLOCK_UCCFAST7 0x02c00000 +#define QE_CR_SUBBLOCK_UCCFAST8 0x02e00000 +#define QE_CR_SUBBLOCK_UCCSLOW1 0x00000000 +#define QE_CR_SUBBLOCK_UCCSLOW2 0x00200000 +#define QE_CR_SUBBLOCK_UCCSLOW3 0x00400000 +#define QE_CR_SUBBLOCK_UCCSLOW4 0x00600000 +#define QE_CR_SUBBLOCK_UCCSLOW5 0x00800000 +#define QE_CR_SUBBLOCK_UCCSLOW6 0x00a00000 +#define QE_CR_SUBBLOCK_UCCSLOW7 0x00c00000 +#define QE_CR_SUBBLOCK_UCCSLOW8 0x00e00000 +#define QE_CR_SUBBLOCK_MCC1 0x03800000 +#define QE_CR_SUBBLOCK_MCC2 0x03a00000 +#define QE_CR_SUBBLOCK_MCC3 0x03000000 +#define QE_CR_SUBBLOCK_IDMA1 0x02800000 +#define QE_CR_SUBBLOCK_IDMA2 0x02a00000 +#define QE_CR_SUBBLOCK_IDMA3 0x02c00000 +#define QE_CR_SUBBLOCK_IDMA4 0x02e00000 +#define QE_CR_SUBBLOCK_HPAC 0x01e00000 +#define QE_CR_SUBBLOCK_SPI1 0x01400000 +#define QE_CR_SUBBLOCK_SPI2 0x01600000 +#define QE_CR_SUBBLOCK_RAND 0x01c00000 +#define QE_CR_SUBBLOCK_TIMER 0x01e00000 +#define QE_CR_SUBBLOCK_GENERAL 0x03c00000 + +/* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command. +*/ +#define QE_CR_PROTOCOL_UNSPECIFIED 0x00 /* For all other protocols */ +#define QE_CR_PROTOCOL_HDLC_TRANSPARENT 0x00 +#define QE_CR_PROTOCOL_ATM_POS 0x0A +#define QE_CR_PROTOCOL_ETHERNET 0x0C +#define QE_CR_PROTOCOL_L2_SWITCH 0x0D +#define QE_CR_PROTOCOL_SHIFT 6 + +/* QE ASSIGN PAGE command +*/ +#define QE_CR_ASSIGN_PAGE_SNUM_SHIFT 17 + +/* Communication Direction. +*/ +typedef enum comm_dir { + COMM_DIR_NONE = 0, + COMM_DIR_RX = 1, + COMM_DIR_TX = 2, + COMM_DIR_RX_AND_TX = 3 +} comm_dir_e; + +/* Clocks and BRG's +*/ +typedef enum qe_clock { + QE_CLK_NONE = 0, + QE_BRG1, /* Baud Rate Generator 1 */ + QE_BRG2, /* Baud Rate Generator 2 */ + QE_BRG3, /* Baud Rate Generator 3 */ + QE_BRG4, /* Baud Rate Generator 4 */ + QE_BRG5, /* Baud Rate Generator 5 */ + QE_BRG6, /* Baud Rate Generator 6 */ + QE_BRG7, /* Baud Rate Generator 7 */ + QE_BRG8, /* Baud Rate Generator 8 */ + QE_BRG9, /* Baud Rate Generator 9 */ + QE_BRG10, /* Baud Rate Generator 10 */ + QE_BRG11, /* Baud Rate Generator 11 */ + QE_BRG12, /* Baud Rate Generator 12 */ + QE_BRG13, /* Baud Rate Generator 13 */ + QE_BRG14, /* Baud Rate Generator 14 */ + QE_BRG15, /* Baud Rate Generator 15 */ + QE_BRG16, /* Baud Rate Generator 16 */ + QE_CLK1, /* Clock 1 */ + QE_CLK2, /* Clock 2 */ + QE_CLK3, /* Clock 3 */ + QE_CLK4, /* Clock 4 */ + QE_CLK5, /* Clock 5 */ + QE_CLK6, /* Clock 6 */ + QE_CLK7, /* Clock 7 */ + QE_CLK8, /* Clock 8 */ + QE_CLK9, /* Clock 9 */ + QE_CLK10, /* Clock 10 */ + QE_CLK11, /* Clock 11 */ + QE_CLK12, /* Clock 12 */ + QE_CLK13, /* Clock 13 */ + QE_CLK14, /* Clock 14 */ + QE_CLK15, /* Clock 15 */ + QE_CLK16, /* Clock 16 */ + QE_CLK17, /* Clock 17 */ + QE_CLK18, /* Clock 18 */ + QE_CLK19, /* Clock 19 */ + QE_CLK20, /* Clock 20 */ + QE_CLK21, /* Clock 21 */ + QE_CLK22, /* Clock 22 */ + QE_CLK23, /* Clock 23 */ + QE_CLK24, /* Clock 24 */ + QE_CLK_DUMMY +} qe_clock_e; + +/* QE CMXGCR register +*/ +#define QE_CMXGCR_MII_ENET_MNG_MASK 0x00007000 +#define QE_CMXGCR_MII_ENET_MNG_SHIFT 12 + +/* QE CMXUCR registers + */ +#define QE_CMXUCR_TX_CLK_SRC_MASK 0x0000000F + +/* QE BRG configuration register +*/ +#define QE_BRGC_ENABLE 0x00010000 +#define QE_BRGC_DIVISOR_SHIFT 1 +#define QE_BRGC_DIVISOR_MAX 0xFFF +#define QE_BRGC_DIV16 1 + +/* QE SDMA registers +*/ +#define QE_SDSR_BER1 0x02000000 +#define QE_SDSR_BER2 0x01000000 + +#define QE_SDMR_GLB_1_MSK 0x80000000 +#define QE_SDMR_ADR_SEL 0x20000000 +#define QE_SDMR_BER1_MSK 0x02000000 +#define QE_SDMR_BER2_MSK 0x01000000 +#define QE_SDMR_EB1_MSK 0x00800000 +#define QE_SDMR_ER1_MSK 0x00080000 +#define QE_SDMR_ER2_MSK 0x00040000 +#define QE_SDMR_CEN_MASK 0x0000E000 +#define QE_SDMR_SBER_1 0x00000200 +#define QE_SDMR_SBER_2 0x00000200 +#define QE_SDMR_EB1_PR_MASK 0x000000C0 +#define QE_SDMR_ER1_PR 0x00000008 + +#define QE_SDMR_CEN_SHIFT 13 +#define QE_SDMR_EB1_PR_SHIFT 6 + +#define QE_SDTM_MSNUM_SHIFT 24 + +#define QE_SDEBCR_BA_MASK 0x01FFFFFF + +/* Communication Processor */ +#define QE_CP_CERCR_MEE 0x8000 /* Multi-user RAM ECC enable */ +#define QE_CP_CERCR_IEE 0x4000 /* Instruction RAM ECC enable */ +#define QE_CP_CERCR_CIR 0x0800 /* Common instruction RAM */ + +/* I-RAM */ +#define QE_IRAM_IADD_AIE 0x80000000 /* Auto Increment Enable */ +#define QE_IRAM_IADD_BADDR 0x00080000 /* Base Address */ +#define QE_IRAM_READY 0x80000000 + +/* Structure that defines QE firmware binary files. + * + * See doc/README.qe_firmware for a description of these fields. + */ +struct qe_firmware { + struct qe_header { + u32 length; /* Length of the entire structure, in bytes */ + u8 magic[3]; /* Set to { 'Q', 'E', 'F' } */ + u8 version; /* Version of this layout. First ver is '1' */ + } header; + u8 id[62]; /* Null-terminated identifier string */ + u8 split; /* 0 = shared I-RAM, 1 = split I-RAM */ + u8 count; /* Number of microcode[] structures */ + struct { + u16 model; /* The SOC model */ + u8 major; /* The SOC revision major */ + u8 minor; /* The SOC revision minor */ + } __attribute__ ((packed)) soc; + u8 padding[4]; /* Reserved, for alignment */ + u64 extended_modes; /* Extended modes */ + u32 vtraps[8]; /* Virtual trap addresses */ + u8 reserved[4]; /* Reserved, for future expansion */ + struct qe_microcode { + u8 id[32]; /* Null-terminated identifier */ + u32 traps[16]; /* Trap addresses, 0 == ignore */ + u32 eccr; /* The value for the ECCR register */ + u32 iram_offset;/* Offset into I-RAM for the code */ + u32 count; /* Number of 32-bit words of the code */ + u32 code_offset;/* Offset of the actual microcode */ + u8 major; /* The microcode version major */ + u8 minor; /* The microcode version minor */ + u8 revision; /* The microcode version revision */ + u8 padding; /* Reserved, for alignment */ + u8 reserved[4]; /* Reserved, for future expansion */ + } __attribute__ ((packed)) microcode[1]; + /* All microcode binaries should be located here */ + /* CRC32 should be located here, after the microcode binaries */ +} __attribute__ ((packed)); + +struct qe_firmware_info { + char id[64]; /* Firmware name */ + u32 vtraps[8]; /* Virtual trap addresses */ + u64 extended_modes; /* Extended modes */ +}; + +void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign); +void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data); +uint qe_muram_alloc(uint size, uint align); +void *qe_muram_addr(uint offset); +int qe_get_snum(void); +void qe_put_snum(u8 snum); +void qe_init(uint qe_base); +void qe_reset(void); +void qe_assign_page(uint snum, uint para_ram_base); +int qe_set_brg(uint brg, uint rate); +int qe_set_mii_clk_src(int ucc_num); +int qe_upload_firmware(const struct qe_firmware *firmware); +struct qe_firmware_info *qe_get_firmware_info(void); +void ft_qe_setup(void *blob); +void qe_init(uint qe_base); +void qe_reset(void); + +#ifdef CONFIG_U_QE +void u_qe_init(void); +int u_qe_upload_firmware(const struct qe_firmware *firmware); +void u_qe_resume(void); +int u_qe_firmware_resume(const struct qe_firmware *firmware, + qe_map_t *qe_immrr); +#endif + +#endif /* __QE_H__ */ diff --git a/include/power/tps65218.h b/include/power/tps65218.h index 63fc7b343f8..4d68faacafd 100644 --- a/include/power/tps65218.h +++ b/include/power/tps65218.h @@ -8,6 +8,8 @@ #ifndef __POWER_TPS65218_H__ #define __POWER_TPS65218_H__ +#include <linux/bitops.h> + /* I2C chip address */ #define TPS65218_CHIP_PM 0x24 @@ -60,8 +62,18 @@ enum { #define TPS65218_DCDC_VOLT_SEL_1260MV 0x29 #define TPS65218_DCDC_VOLT_SEL_1330MV 0x30 +#define TPS65218_CC_STAT (BIT(0) | BIT(1)) +#define TPS65218_STATE (BIT(2) | BIT(3)) +#define TPS65218_PB_STATE BIT(4) +#define TPS65218_AC_STATE BIT(5) +#define TPS65218_EE BIT(6) +#define TPS65218_FSEAL BIT(7) + +int tps65218_reg_read(uchar dest_reg, uchar *dest_val); int tps65218_reg_write(uchar prot_level, uchar dest_reg, uchar dest_val, uchar mask); int tps65218_voltage_update(uchar dc_cntrl_reg, uchar volt_sel); +int tps65218_toggle_fseal(void); +int tps65218_lock_fseal(void); int power_tps65218_init(unsigned char bus); #endif /* __POWER_TPS65218_H__ */ |