diff options
Diffstat (limited to 'include')
156 files changed, 4634 insertions, 1574 deletions
diff --git a/include/acpi/acpi_table.h b/include/acpi/acpi_table.h index e67562ef654..15fd61a51d7 100644 --- a/include/acpi/acpi_table.h +++ b/include/acpi/acpi_table.h @@ -57,17 +57,41 @@ struct __packed acpi_table_header { char oem_id[6]; /* OEM identification */ char oem_table_id[8]; /* OEM table identification */ u32 oem_revision; /* OEM revision number */ - char aslc_id[4]; /* ASL compiler vendor ID */ - u32 aslc_revision; /* ASL compiler revision number */ + char creator_id[4]; /* ASL compiler vendor ID */ + u32 creator_revision; /* ASL compiler revision number */ }; +/** + * struct acpi_gen_regaddr - generic address structure (GAS) + */ struct acpi_gen_regaddr { - u8 space_id; /* Address space ID */ - u8 bit_width; /* Register size in bits */ - u8 bit_offset; /* Register bit offset */ - u8 access_size; /* Access size */ - u32 addrl; /* Register address, low 32 bits */ - u32 addrh; /* Register address, high 32 bits */ + /** + * @space_id: address space ID + * + * See table "Operation Region Address Space Identifiers" in the ACPI + * specification. + */ + u8 space_id; + /** @bit_width: size in bits of the register */ + u8 bit_width; + /** @bit_offset: bit offset of the register */ + u8 bit_offset; + /** + * @access_size: access size + * + * * 0 - undefined + * * 1 - byte access + * * 2 - word (2 bytes) access + * * 3 - Dword (4 bytes) access + * * 4 - Qword (8 bytes) access + * + * See ACPI_ACCESS_SIZE_*_ACCESS macros. + */ + u8 access_size; + /** @addrl: register address, low 32 bits */ + u32 addrl; + /** @addrh: register address, high 32 bits */ + u32 addrh; }; /* A maximum number of 32 ACPI tables ought to be enough for now */ @@ -85,15 +109,26 @@ struct __packed acpi_xsdt { u64 entry[MAX_ACPI_TABLES]; }; -/* HPET timers */ -struct __packed acpi_hpet { +/** + * struct acpi_hpet: High Precision Event Timers (HETP) + * + * The structure is defined in the + * "IA-PC HPET (High Precision Event Timers) Specification", rev 1.0a, Oct 2004 + */ +struct acpi_hpet { + /** @header: table header */ struct acpi_table_header header; + /** @id hardware ID of Event Timer Block */ u32 id; + /** @addr: address of Event Timer Block */ struct acpi_gen_regaddr addr; + /** @number: HPET sequence number */ u8 number; + /** @min_tick: minimum clock ticks without lost interrupts */ u16 min_tick; + /** @attributes: page protection and OEM atttribute */ u8 attributes; -}; +} __packed; struct __packed acpi_tpm2 { struct acpi_table_header header; @@ -364,7 +399,7 @@ enum { * This holds information about the Generic Interrupt Controller (GIC) CPU * interface. See ACPI Spec v6.3 section 5.2.12.14 */ -struct __packed acpi_madr_gicc { +struct acpi_madr_gicc { u8 type; u8 length; u16 reserved; @@ -383,7 +418,7 @@ struct __packed acpi_madr_gicc { u8 efficiency; u8 reserved2; u16 spi_overflow_irq; -}; +} __packed; /** * struct __packed acpi_madr_gicc - GIC distributor (type 0xc) @@ -391,7 +426,7 @@ struct __packed acpi_madr_gicc { * This holds information about the Generic Interrupt Controller (GIC) * Distributor interface. See ACPI Spec v6.3 section 5.2.12.15 */ -struct __packed acpi_madr_gicd { +struct acpi_madr_gicd { u8 type; u8 length; u16 reserved; @@ -400,7 +435,7 @@ struct __packed acpi_madr_gicd { u32 reserved2; u8 gic_version; u8 reserved3[3]; -}; +} __packed; /* MCFG (PCI Express MMIO config space BAR description table) */ struct acpi_mcfg { @@ -653,7 +688,7 @@ struct __packed acpi_spcr { * * See ACPI Spec v6.3 section 5.2.24 for details */ -struct __packed acpi_gtdt { +struct acpi_gtdt { struct acpi_table_header header; u64 cnt_ctrl_base; u32 reserved0; @@ -670,7 +705,7 @@ struct __packed acpi_gtdt { u32 plat_timer_offset; u32 virt_el2_gsiv; u32 virt_el2_flags; -}; +} __packed; /** * struct acpi_bgrt - Boot Graphics Resource Table (BGRT) @@ -680,7 +715,7 @@ struct __packed acpi_gtdt { * * See ACPI Spec v6.3 section 5.2.22 for details */ -struct __packed acpi_bgrt { +struct acpi_bgrt { struct acpi_table_header header; u16 version; u8 status; @@ -688,7 +723,7 @@ struct __packed acpi_bgrt { u64 addr; u32 offset_x; u32 offset_y; -}; +} __packed; /* Types for PPTT */ #define ACPI_PPTT_TYPE_PROC 0 @@ -709,22 +744,22 @@ struct __packed acpi_bgrt { * * See ACPI Spec v6.3 section 5.2.29 for details */ -struct __packed acpi_pptt_header { +struct acpi_pptt_header { u8 type; /* ACPI_PPTT_TYPE_... */ u8 length; u16 reserved; -}; +} __packed; /** * struct acpi_pptt_proc - a processor as described by PPTT */ -struct __packed acpi_pptt_proc { +struct acpi_pptt_proc { struct acpi_pptt_header hdr; u32 flags; u32 parent; u32 proc_id; u32 num_resources; -}; +} __packed; /* Cache flags for acpi_pptt_cache */ #define ACPI_PPTT_SIZE_VALID BIT(0) @@ -751,7 +786,7 @@ struct __packed acpi_pptt_proc { /** * struct acpi_pptt_cache - a cache as described by PPTT */ -struct __packed acpi_pptt_cache { +struct acpi_pptt_cache { struct acpi_pptt_header hdr; u32 flags; u32 next_cache_level; @@ -760,7 +795,7 @@ struct __packed acpi_pptt_cache { u8 assoc; u8 attributes; u16 line_size; -}; +} __packed; /* Tables defined/reserved by ACPI and generated by U-Boot */ enum acpi_tables { @@ -829,16 +864,6 @@ void acpi_create_dbg2(struct acpi_dbg2_header *dbg2, const char *device_path); /** - * acpi_fill_header() - Set up a new table header - * - * This sets all fields except length, revision, checksum and aslc_revision - * - * @header: ACPI header to update - * @signature: Table signature to use (4 characters) - */ -void acpi_fill_header(struct acpi_table_header *header, char *signature); - -/** * acpi_align() - Align the ACPI output pointer to a 16-byte boundary * * @ctx: ACPI context diff --git a/include/acpi/acpigen.h b/include/acpi/acpigen.h index 2c269ed6627..3aa94d70b9c 100644 --- a/include/acpi/acpigen.h +++ b/include/acpi/acpigen.h @@ -121,7 +121,7 @@ struct acpi_cstate { * * @percent: Percent of the core CPU operating frequency that will be * available when this throttling state is invoked - * @power: Throttling state’s maximum power dissipation (mw) + * @power: Throttling state's maximum power dissipation (mw) * @latency: Worst-case latency (uS) that the CPU is unavailable during a * transition from any throttling state to this throttling state * @control: Value to be written to the Processor Control Register @@ -920,7 +920,7 @@ void acpigen_write_pss_package(struct acpi_ctx *ctx, uint corefreq, uint power, * @ctx: ACPI context pointer * @domain: Dependency domain number to which this P state entry belongs * @numprocs: Number of processors belonging to the domain for this logical - * processor’s P-states + * processor's P-states * @coordtype: Coordination type */ void acpigen_write_psd_package(struct acpi_ctx *ctx, uint domain, uint numprocs, @@ -972,7 +972,7 @@ void acpigen_write_tss_package(struct acpi_ctx *ctx, * @ctx: ACPI context pointer * @domain: dependency domain number to which this T state entry belongs * @numprocs: Number of processors belonging to the domain for this logical - * processor’s T-states + * processor's T-states * @coordtype: Coordination type */ void acpigen_write_tsd_package(struct acpi_ctx *ctx, uint domain, uint numprocs, diff --git a/include/asm-generic/pe.h b/include/asm-generic/pe.h index b9d674b6da4..cd5b6ad62bf 100644 --- a/include/asm-generic/pe.h +++ b/include/asm-generic/pe.h @@ -51,6 +51,9 @@ #define IMAGE_SUBSYSTEM_EFI_RUNTIME_DRIVER 12 #define IMAGE_SUBSYSTEM_EFI_ROM 13 +/* DLL characteristics */ +#define IMAGE_DLLCHARACTERISTICS_NX_COMPAT 0x100 + /* Section flags */ #define IMAGE_SCN_CNT_CODE 0x00000020 #define IMAGE_SCN_CNT_INITIALIZED_DATA 0x00000040 diff --git a/include/asm-generic/sections.h b/include/asm-generic/sections.h index 1e1657a0167..b6bca53db10 100644 --- a/include/asm-generic/sections.h +++ b/include/asm-generic/sections.h @@ -34,6 +34,9 @@ extern char __priv_data_start[], __priv_data_end[]; /* Start and end of .ctors section - used for constructor calls. */ extern char __ctors_start[], __ctors_end[]; +extern char __efi_runtime_rel_start[], __efi_runtime_rel_stop[]; +extern char __efi_runtime_start[], __efi_runtime_stop[]; + /* function descriptor handling (if any). Override * in asm/sections.h */ #ifndef dereference_function_descriptor diff --git a/include/bloblist.h b/include/bloblist.h index 84fc9438191..7fbdd622bcf 100644 --- a/include/bloblist.h +++ b/include/bloblist.h @@ -78,6 +78,13 @@ enum { BLOBLIST_VERSION = 1, BLOBLIST_MAGIC = 0x4a0fb10b, + /* + * FIXME: + * Register convention version should be placed into a higher byte + * https://github.com/FirmwareHandoff/firmware_handoff/issues/32 + */ + BLOBLIST_REGCONV_VER = 1 << 24, + BLOBLIST_BLOB_ALIGN_LOG2 = 3, BLOBLIST_BLOB_ALIGN = 1 << BLOBLIST_BLOB_ALIGN_LOG2, @@ -341,12 +348,13 @@ int bloblist_new(ulong addr, uint size, uint flags, uint align_log2); * bloblist_check() - Check if a bloblist exists * * @addr: Address of bloblist - * @size: Expected size of blobsize, or 0 to detect the size + * @size: Reserved space size for blobsize, or 0 to use the total size * Return: 0 if OK, -ENOENT if the magic number doesn't match (indicating that - * there problem is no bloblist at the given address), -EPROTONOSUPPORT + * there problem is no bloblist at the given address) or any fields for header + * size, used size and total size do not match, -EPROTONOSUPPORT * if the version does not match, -EIO if the checksum does not match, - * -EFBIG if the expected size does not match the detected size, -ENOSPC - * if the size is not large enough to hold the headers + * -EFBIG if the reserved space size is small than the total size or total size + * is 0 */ int bloblist_check(ulong addr, uint size); @@ -418,11 +426,11 @@ const char *bloblist_tag_name(enum bloblist_tag_t tag); * bloblist_reloc() - Relocate the bloblist and optionally resize it * * @to: Pointer to new bloblist location (must not overlap old location) - * @to_size: New size for bloblist (must be larger than from_size) - * @from: Pointer to bloblist to relocate - * @from_size: Size of bloblist to relocate + * @to_size: New size for bloblist + * Return: 0 if OK, -ENOSPC if the new size is small than the bloblist total + * size. */ -void bloblist_reloc(void *to, uint to_size, void *from, uint from_size); +int bloblist_reloc(void *to, uint to_size); /** * bloblist_init() - Init the bloblist system with a single bloblist @@ -461,4 +469,27 @@ static inline int bloblist_maybe_init(void) } #endif /* BLOBLIST */ +/** + * bloblist_check_reg_conv() - Check whether the bloblist is compliant to + * the register conventions according to the + * Firmware Handoff spec. + * + * @rfdt: Register that holds the FDT base address. + * @rzero: Register that must be zero. + * @rsig: Register that holds signature and register conventions version. + * Return: 0 if OK, -EIO if the bloblist is not compliant to the register + * conventions. + */ +int bloblist_check_reg_conv(ulong rfdt, ulong rzero, ulong rsig); + +/** + * xferlist_from_boot_arg() - Get bloblist from the boot args and relocate it + * to the specified address. + * + * @addr: Address for the bloblist + * @size: Size of space reserved for the bloblist + * Return: 0 if OK, else on error + */ +int xferlist_from_boot_arg(ulong addr, ulong size); + #endif /* __BLOBLIST_H */ diff --git a/include/bootflow.h b/include/bootflow.h index 42112874f64..080ee850122 100644 --- a/include/bootflow.h +++ b/include/bootflow.h @@ -133,6 +133,8 @@ struct bootflow { * this uclass (used with things like "mmc") * @BOOTFLOWIF_SINGLE_MEDIA: (internal) Scan one media device in the uclass (used * with things like "mmc1") + * @BOOTFLOWIF_SINGLE_PARTITION: (internal) Scan one partition in media device + * (used with things like "mmc1:3") */ enum bootflow_iter_flags_t { BOOTFLOWIF_FIXED = 1 << 0, @@ -148,6 +150,7 @@ enum bootflow_iter_flags_t { BOOTFLOWIF_SKIP_GLOBAL = 1 << 17, BOOTFLOWIF_SINGLE_UCLASS = 1 << 18, BOOTFLOWIF_SINGLE_MEDIA = 1 << 19, + BOOTFLOWIF_SINGLE_PARTITION = 1 << 20, }; /** diff --git a/include/bootm.h b/include/bootm.h index 9e0f8d60de0..61160705215 100644 --- a/include/bootm.h +++ b/include/bootm.h @@ -273,21 +273,24 @@ int bootm_process_cmdline(char *buf, int maxlen, int flags); int bootm_process_cmdline_env(int flags); /** - * zboot_start() - Boot a zimage + * zboot_run() - Run through the various steps to boot a zimage * * Boot a zimage, given the component parts * * @addr: Address where the bzImage is moved before booting, either * BZIMAGE_LOAD_ADDR or ZIMAGE_LOAD_ADDR - * @base: Pointer to the boot parameters, typically at address - * DEFAULT_SETUP_BASE + * @size: Size of bzImage, or 0 to detect this * @initrd: Address of the initial ramdisk, or 0 if none * @initrd_size: Size of the initial ramdisk, or 0 if none - * @cmdline: Command line to use for booting + * @base_addr: If non-zero, this indicates that the boot parameters have already + * been loaded by the caller to this address, so the load_zimage() call + * in zboot_load() will be skipped when booting + * @cmdline: If non-NULL, the environment variable containing the command line + * to use for booting * Return: -EFAULT on error (normally it does not return) */ -int zboot_start(ulong addr, ulong size, ulong initrd, ulong initrd_size, - ulong base, char *cmdline); +int zboot_run(ulong addr, ulong size, ulong initrd, ulong initrd_size, + ulong base, char *cmdline); /* * zimage_get_kernel_version() - Get the version string from a kernel diff --git a/include/charset.h b/include/charset.h index f1050c903d6..348bad5883a 100644 --- a/include/charset.h +++ b/include/charset.h @@ -16,7 +16,7 @@ /* * codepage_437 - Unicode to codepage 437 translation table */ -extern const u16 codepage_437[128]; +extern const u16 codepage_437[160]; /** * console_read_unicode() - read Unicode code point from console diff --git a/include/configs/am62px_evm.h b/include/configs/am62px_evm.h new file mode 100644 index 00000000000..06b12860e21 --- /dev/null +++ b/include/configs/am62px_evm.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration header file for K3 AM62Px SoC family + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef __CONFIG_AM62PX_EVM_H +#define __CONFIG_AM62PX_EVM_H + +/* Now for the remaining common defines */ +#include <configs/ti_armv7_common.h> + +#endif /* __CONFIG_AM62PX_EVM_H */ diff --git a/include/configs/apalis-imx8.h b/include/configs/apalis-imx8.h index 845705c86db..c8ec034fc97 100644 --- a/include/configs/apalis-imx8.h +++ b/include/configs/apalis-imx8.h @@ -46,8 +46,6 @@ "fdt_board=eval\0" \ "initrd_addr=0x83800000\0" \ "initrd_high=0xffffffffffffffff\0" \ - "setup=setenv setupargs console=tty1 console=${console},${baudrate} " \ - "consoleblank=0 earlycon\0" \ "update_uboot=askenv confirm Did you load flash.bin resp. u-boot-dtb.imx (y/N)?; " \ "if test \"$confirm\" = \"y\"; then " \ "setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \ diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h index 8a9f3ef75a7..0df3917e200 100644 --- a/include/configs/apalis_imx6.h +++ b/include/configs/apalis_imx6.h @@ -64,12 +64,9 @@ #define CFG_EXTRA_ENV_SETTINGS \ BOOTENV \ - "boot_file=zImage\0" \ "boot_script_dhcp=boot.scr\0" \ "console=ttymxc0\0" \ - "defargs=enable_wait_mode=off vmalloc=400M\0" \ "fdt_board=eval\0" \ - "fdt_fixup=;\0" \ MEM_LAYOUT_ENV_SETTINGS \ UBOOT_UPDATE \ "setethupdate=if env exists ethaddr; then; else setenv ethaddr " \ @@ -80,16 +77,12 @@ "|| setenv drive 2; mmc rescan; load ${interface} ${drive}:1" \ " ${loadaddr} flash_blk.img && " \ "source ${loadaddr}\0" \ - "setup=setenv setupargs fec_mac=${ethaddr} " \ - "consoleblank=0 no_console_suspend=1 console=tty1 " \ - "console=${console},${baudrate}n8\0 " \ "setupdate=run setsdupdate || run setusbupdate || run setethupdate\0" \ "setusbupdate=usb start && setenv interface usb; setenv drive 0; " \ "load ${interface} ${drive}:1 ${loadaddr} flash_blk.img && " \ "source ${loadaddr}\0" \ "splashpos=m,m\0" \ - "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ - "vidargs=mxc_hdmi.only_cea=1 fbmem=32M\0" + "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" /* Miscellaneous configurable options */ diff --git a/include/configs/bayleybay.h b/include/configs/bayleybay.h deleted file mode 100644 index 9b0f5cedcd7..00000000000 --- a/include/configs/bayleybay.h +++ /dev/null @@ -1,4 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> - */ diff --git a/include/configs/cherryhill.h b/include/configs/cherryhill.h deleted file mode 100644 index a3009571de9..00000000000 --- a/include/configs/cherryhill.h +++ /dev/null @@ -1,4 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com> - */ diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h index 561a61ebc03..7c9d633b68d 100644 --- a/include/configs/colibri-imx6ull.h +++ b/include/configs/colibri-imx6ull.h @@ -48,8 +48,8 @@ "ubiargs=ubi.mtd=ubi root=ubi0:rootfs rw rootfstype=ubifs " \ "ubi.fm_autoconvert=1\0" \ "ubiboot=run setup; " \ - "setenv bootargs ${defargs} ${ubiargs} " \ - "${setupargs} ${vidargs} ${tdxargs}; echo Booting from NAND...; " \ + "setenv bootargs ${ubiargs} " \ + "${setupargs} ${tdxargs}; echo Booting from NAND...; " \ "ubi part ubi &&" \ "ubi read ${kernel_addr_r} kernel && " \ "ubi read ${fdt_addr_r} dtb && " \ @@ -86,11 +86,7 @@ UBOOT_UPDATE \ "boot_script_dhcp=boot.scr\0" \ "console=ttymxc0\0" \ - "defargs=user_debug=30\0" \ "fdt_board=eval-v3\0" \ - "fdt_fixup=;\0" \ - "ip_dyn=yes\0" \ - "kernel_file=zImage\0" \ "setethupdate=if env exists ethaddr; then; else setenv ethaddr " \ "00:14:2d:00:00:00; fi; tftpboot ${loadaddr} " \ "${board}/flash_eth.img && source ${loadaddr}\0" \ @@ -99,7 +95,7 @@ "${board}/flash_blk.img && source ${loadaddr}\0" \ "setup=setenv setupargs " \ "console=tty1 console=${console}" \ - ",${baudrate}n8 ${memargs} ${mtdparts} consoleblank=0\0" \ + ",${baudrate}n8 ${memargs} ${mtdparts}\0" \ "setupdate=run setsdupdate || run setusbupdate || run setethupdate\0" \ "setusbupdate=usb start && setenv interface usb && " \ "fatload ${interface} 0:1 ${loadaddr} " \ diff --git a/include/configs/colibri-imx8x.h b/include/configs/colibri-imx8x.h index 042fcb8757f..2b7fea30116 100644 --- a/include/configs/colibri-imx8x.h +++ b/include/configs/colibri-imx8x.h @@ -40,8 +40,6 @@ "fdt_board=eval-v3\0" \ "initrd_addr=0x83800000\0" \ "initrd_high=0xffffffffffffffff\0" \ - "setup=setenv setupargs console=tty1 console=${console},${baudrate} " \ - "consoleblank=0 earlycon\0" \ "update_uboot=askenv confirm Did you load flash.bin resp. u-boot-dtb.imx (y/N)?; " \ "if test \"$confirm\" = \"y\"; then " \ "setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \ diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h index 4b2841833b5..79e5b870b81 100644 --- a/include/configs/colibri_imx6.h +++ b/include/configs/colibri_imx6.h @@ -58,12 +58,9 @@ #define CFG_EXTRA_ENV_SETTINGS \ BOOTENV \ - "boot_file=zImage\0" \ "boot_script_dhcp=boot.scr\0" \ "console=ttymxc0\0" \ - "defargs=enable_wait_mode=off galcore.contiguousSize=50331648\0" \ "fdt_board=eval-v3\0" \ - "fdt_fixup=;\0" \ MEM_LAYOUT_ENV_SETTINGS \ UBOOT_UPDATE \ "setethupdate=if env exists ethaddr; then; else setenv ethaddr " \ @@ -72,16 +69,12 @@ "setsdupdate=setenv interface mmc; setenv drive 1; mmc rescan; load " \ "${interface} ${drive}:1 ${loadaddr} flash_blk.img && " \ "source ${loadaddr}\0" \ - "setup=setenv setupargs fec_mac=${ethaddr} " \ - "consoleblank=0 no_console_suspend=1 console=tty1 " \ - "console=${console},${baudrate}n8\0 " \ "setupdate=run setsdupdate || run setusbupdate || run setethupdate\0" \ "setusbupdate=usb start && setenv interface usb; setenv drive 0; " \ "load ${interface} ${drive}:1 ${loadaddr} flash_blk.img && " \ "source ${loadaddr}\0" \ "splashpos=m,m\0" \ - "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ - "vidargs=fbmem=8M\0" + "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" /* Miscellaneous configurable options */ diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index 7a9f4afe7d1..c34f1f903df 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -89,8 +89,8 @@ "ubiargs=ubi.mtd=ubi root=ubi0:rootfs rootfstype=ubifs " \ "ubi.fm_autoconvert=1\0" \ "ubiboot=run setup; " \ - "setenv bootargs ${defargs} ${ubiargs} " \ - "${setupargs} ${vidargs} ${tdxargs}; echo Booting from NAND...; " \ + "setenv bootargs ${ubiargs} " \ + "${setupargs} ${tdxargs}; echo Booting from NAND...; " \ "ubi part ubi && run m4boot && " \ "ubi read ${kernel_addr_r} kernel && " \ "ubi read ${fdt_addr_r} dtb && " \ @@ -123,15 +123,10 @@ MEM_LAYOUT_ENV_SETTINGS \ MODULE_EXTRA_ENV_SETTINGS \ UBOOT_UPDATE \ - "boot_file=zImage\0" \ "boot_script_dhcp=boot.scr\0" \ "console=ttymxc0\0" \ - "defargs=\0" \ "fdt_board=eval-v3\0" \ - "fdt_fixup=;\0" \ "m4boot=;\0" \ - "ip_dyn=yes\0" \ - "kernel_file=zImage\0" \ "setethupdate=if env exists ethaddr; then; else setenv ethaddr " \ "00:14:2d:00:00:00; fi; tftpboot ${loadaddr} " \ "${board}/flash_eth.img && source ${loadaddr}\0" \ @@ -140,7 +135,7 @@ "${board}/flash_blk.img && source ${loadaddr}\0" \ "setup=setenv setupargs " \ "console=tty1 console=${console}" \ - ",${baudrate}n8 ${memargs} ${mtdparts} consoleblank=0\0" \ + ",${baudrate}n8 ${memargs} ${mtdparts}\0" \ "setupdate=run setsdupdate || run setusbupdate || run setethupdate\0" \ "setusbupdate=usb start && setenv interface usb && " \ "fatload ${interface} 0:1 ${loadaddr} " \ diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h deleted file mode 100644 index e00c408f29a..00000000000 --- a/include/configs/coreboot.h +++ /dev/null @@ -1,4 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> - */ diff --git a/include/configs/cougarcanyon2.h b/include/configs/cougarcanyon2.h deleted file mode 100644 index 0406786f7c6..00000000000 --- a/include/configs/cougarcanyon2.h +++ /dev/null @@ -1,4 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> - */ diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h deleted file mode 100644 index 0c842dd01eb..00000000000 --- a/include/configs/crownbay.h +++ /dev/null @@ -1,4 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> - */ diff --git a/include/configs/dragonboard845c.h b/include/configs/dragonboard845c.h deleted file mode 100644 index 14a8a2ca049..00000000000 --- a/include/configs/dragonboard845c.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration file for Dragonboard 845c, based on Qualcomm SDA845 chip - * - * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org> - */ - -#ifndef __CONFIGS_SDM845_H -#define __CONFIGS_SDM845_H - -#include <linux/sizes.h> - -#define CFG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 } - -#define CFG_EXTRA_ENV_SETTINGS \ - "bootm_size=0x5000000\0" \ - "bootm_low=0x80000000\0" \ - "bootcmd=bootm $prevbl_initrd_start_addr\0" - -#endif diff --git a/include/configs/edison.h b/include/configs/edison.h deleted file mode 100644 index 127c2c4546e..00000000000 --- a/include/configs/edison.h +++ /dev/null @@ -1,4 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2017 Intel Corp. - */ diff --git a/include/configs/efi-x86_app.h b/include/configs/efi-x86_app.h deleted file mode 100644 index d5824049d69..00000000000 --- a/include/configs/efi-x86_app.h +++ /dev/null @@ -1,4 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2015 Google, Inc - */ diff --git a/include/configs/efi-x86_payload.h b/include/configs/efi-x86_payload.h deleted file mode 100644 index e00c408f29a..00000000000 --- a/include/configs/efi-x86_payload.h +++ /dev/null @@ -1,4 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> - */ diff --git a/include/configs/endeavoru.h b/include/configs/endeavoru.h index 46c582e963e..348078f9770 100644 --- a/include/configs/endeavoru.h +++ b/include/configs/endeavoru.h @@ -53,7 +53,8 @@ "boot_block_size_r=0x200000\0" \ "boot_block_size=0x1000\0" \ "bootloader_file=u-boot-dtb-tegra.bin\0" \ - "check_button=gpio input 179; test $? -eq 0\0" \ + "button_cmd_0_name=Volume Down\0" \ + "button_cmd_0=bootmenu\0" \ "partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs}\0" \ ENDEAVORU_BOOTMENU diff --git a/include/configs/evb_rk3328.h b/include/configs/evb_rk3328.h index d10e5b1d2e0..c985080f7b3 100644 --- a/include/configs/evb_rk3328.h +++ b/include/configs/evb_rk3328.h @@ -6,6 +6,11 @@ #ifndef __EVB_RK3328_H #define __EVB_RK3328_H +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdin=serial,usbkbd\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + #include <configs/rk3328_common.h> #endif diff --git a/include/configs/galileo.h b/include/configs/galileo.h deleted file mode 100644 index 9b0f5cedcd7..00000000000 --- a/include/configs/galileo.h +++ /dev/null @@ -1,4 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> - */ diff --git a/include/configs/grouper.h b/include/configs/grouper.h index 93304ddc6e8..8064b88902e 100644 --- a/include/configs/grouper.h +++ b/include/configs/grouper.h @@ -49,7 +49,10 @@ "boot_block_size_r=0x200000\0" \ "boot_block_size=0x1000\0" \ "bootloader_file=u-boot-dtb-tegra.bin\0" \ - "check_button=gpio input 131; test $? -eq 0;\0" \ + "button_cmd_0_name=Volume Down\0" \ + "button_cmd_0=bootmenu\0" \ + "button_cmd_1_name=Lid\0" \ + "button_cmd_1=poweroff\0" \ "partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs}\0" \ GROUPER_BOOTMENU diff --git a/include/configs/hc2910-2aghd05.h b/include/configs/hc2910-2aghd05.h deleted file mode 100644 index 3db9a474ec7..00000000000 --- a/include/configs/hc2910-2aghd05.h +++ /dev/null @@ -1,6 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ - -#ifndef __HC2910_2AGHD05_CONFIG_H__ -#define __HC2910_2AGHD05_CONFIG_H__ - -#endif diff --git a/include/configs/j784s4_evm.h b/include/configs/j784s4_evm.h new file mode 100644 index 00000000000..4a2ccdce144 --- /dev/null +++ b/include/configs/j784s4_evm.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Configuration header file for K3 J784S4 EVM + * + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ + * Hari Nagalla <hnagalla@ti.com> + */ + +#ifndef __CONFIG_J784S4_EVM_H +#define __CONFIG_J784S4_EVM_H + +/* Now for the remaining common defines */ +#include <configs/ti_armv7_common.h> + +#endif /* __CONFIG_J784S4_EVM_H */ diff --git a/include/configs/jaguar_rk3588.h b/include/configs/jaguar_rk3588.h new file mode 100644 index 00000000000..843028c5385 --- /dev/null +++ b/include/configs/jaguar_rk3588.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2023 Theobroma Systems Design und Consulting GmbH + */ + +#ifndef __JAGUAR_RK3588_H +#define __JAGUAR_RK3588_H + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#include <configs/rk3588_common.h> + +#endif /* __JAGUAR_RK3588_H */ diff --git a/include/configs/jethub.h b/include/configs/jethub.h index e22db4991de..2c44bfc853e 100644 --- a/include/configs/jethub.h +++ b/include/configs/jethub.h @@ -11,7 +11,7 @@ #if defined(CONFIG_MESON_AXG) #define BOOTENV_DEV_RESCUE(devtypeu, devtypel, instance) \ "bootcmd_rescue=" \ - "if gpio input 10; then " \ + "if gpio input periphs-banks10; then " \ "run bootcmd_mmc0; " \ "run bootcmd_usb0;" \ "fi;\0" diff --git a/include/configs/meson64.h b/include/configs/meson64.h index efab9a624dc..65fa5f3d6dd 100644 --- a/include/configs/meson64.h +++ b/include/configs/meson64.h @@ -120,6 +120,12 @@ #include <config_distro_bootcmd.h> +#ifdef CONFIG_OF_UPSTREAM +#define FDTFILE_NAME CONFIG_DEFAULT_DEVICE_TREE ".dtb" +#else +#define FDTFILE_NAME "amlogic/" CONFIG_DEFAULT_DEVICE_TREE ".dtb" +#endif + #ifndef CFG_EXTRA_ENV_SETTINGS #define CFG_EXTRA_ENV_SETTINGS \ "stdin=" STDIN_CFG "\0" \ @@ -133,7 +139,7 @@ "pxefile_addr_r=" PXEFILE_ADDR_R "\0" \ "fdtoverlay_addr_r=" FDTOVERLAY_ADDR_R "\0" \ "ramdisk_addr_r=" RAMDISK_ADDR_R "\0" \ - "fdtfile=amlogic/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ + "fdtfile=" FDTFILE_NAME "\0" \ "dfu_alt_info=fitimage ram " KERNEL_ADDR_R " 0x4000000 \0" \ BOOTENV #endif diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h deleted file mode 100644 index 068a2af2c1f..00000000000 --- a/include/configs/minnowmax.h +++ /dev/null @@ -1,4 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015 Google, Inc - */ diff --git a/include/configs/phycore_am64x.h b/include/configs/phycore_am64x.h new file mode 100644 index 00000000000..9377db30a91 --- /dev/null +++ b/include/configs/phycore_am64x.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration header file for PHYTEC phyCORE-AM64x kit + * + * Copyright (C) 2022 - 2024 PHYTEC Messtechnik GmbH + * Author: Wadim Egorov <w.egorov@phytec.de> + */ + +#ifndef __PHYCORE_AM64X_H +#define __PHYCORE_AM64X_H + +/* DDR Configuration */ +#define CFG_SYS_SDRAM_BASE 0x80000000 + +#endif /* __PHYCORE_AM64X_H */ diff --git a/include/configs/phycore_imx8mp.h b/include/configs/phycore_imx8mp.h index 11a17be7fe1..206c4d50d27 100644 --- a/include/configs/phycore_imx8mp.h +++ b/include/configs/phycore_imx8mp.h @@ -13,49 +13,6 @@ #define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) -#define CFG_EXTRA_ENV_SETTINGS \ - "image=Image\0" \ - "console=ttymxc0,115200\0" \ - "fdt_addr=0x48000000\0" \ - "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "ip_dyn=yes\0" \ - "dofastboot=0\0" \ - "fastboot_raw_partition_bootloader=64 8128\0" \ - "fastboot_raw_partition_all=0 4194304\0" \ - "emmc_dev=2\0" \ - "sd_dev=1\0" \ - "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ - "mmcpart=1\0" \ - "mmcroot=2\0" \ - "mmcautodetect=yes\0" \ - "mmcargs=setenv bootargs console=${console} " \ - "root=/dev/mmcblk${mmcdev}p${mmcroot} rootwait rw\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "if run loadfdt; then " \ - "booti ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi;\0 " \ - "nfsroot=/nfs\0" \ - "netargs=setenv bootargs console=${console} root=/dev/nfs ip=dhcp " \ - "nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${loadaddr} ${image}; " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "booti ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi;\0" \ - /* Link Definitions */ #define CFG_SYS_INIT_RAM_ADDR 0x40000000 diff --git a/include/configs/qcom.h b/include/configs/qcom.h new file mode 100644 index 00000000000..e50b3bce5cd --- /dev/null +++ b/include/configs/qcom.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration file for Qualcomm Snapdragon boards + * + * (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com> + * (C) Copyright 2023 Linaro Ltd. + */ + +#ifndef __CONFIGS_SNAPDRAGON_H +#define __CONFIGS_SNAPDRAGON_H + +#define CFG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 } + +/* Load addressed are calculated during board_late_init(). See arm/mach-snapdragon/board.c */ +#define CFG_EXTRA_ENV_SETTINGS \ + "stdin=serial,button-kbd\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" \ + "bootcmd=bootm $prevbl_initrd_start_addr\0" + +#endif diff --git a/include/configs/qcs404-evb.h b/include/configs/qcs404-evb.h deleted file mode 100644 index 9501d43665e..00000000000 --- a/include/configs/qcs404-evb.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration file for QCS404 evaluation board - * - * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org> - */ - -#ifndef __CONFIGS_QCS404EVB_H -#define __CONFIGS_QCS404EVB_H - -#include <linux/sizes.h> - -#define CFG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 } - -#define CFG_EXTRA_ENV_SETTINGS \ - "bootm_size=0x5000000\0" \ - "bootm_low=0x80000000\0" \ - "bootcmd=bootm $prevbl_initrd_start_addr\0" - -#endif diff --git a/include/configs/qemu-x86.h b/include/configs/qemu-x86.h deleted file mode 100644 index 9b0f5cedcd7..00000000000 --- a/include/configs/qemu-x86.h +++ /dev/null @@ -1,4 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> - */ diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h index c2abd14e114..0bf9e8b9a2e 100644 --- a/include/configs/rk3036_common.h +++ b/include/configs/rk3036_common.h @@ -5,7 +5,6 @@ #ifndef __CONFIG_RK3036_COMMON_H #define __CONFIG_RK3036_COMMON_H -#include <asm/arch-rockchip/hardware.h> #include "rockchip-common.h" #define CFG_SYS_HZ_CLOCK 24000000 diff --git a/include/configs/rk3066_common.h b/include/configs/rk3066_common.h index d70c8f77d48..6a3b6900463 100644 --- a/include/configs/rk3066_common.h +++ b/include/configs/rk3066_common.h @@ -6,7 +6,6 @@ #ifndef __CONFIG_RK3066_COMMON_H #define __CONFIG_RK3066_COMMON_H -#include <asm/arch-rockchip/hardware.h> #include "rockchip-common.h" #define CFG_IRAM_BASE 0x10080000 diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h index a8cee1e44d4..98f2c25f3cf 100644 --- a/include/configs/rk3188_common.h +++ b/include/configs/rk3188_common.h @@ -6,7 +6,6 @@ #ifndef __CONFIG_RK3188_COMMON_H #define __CONFIG_RK3188_COMMON_H -#include <asm/arch-rockchip/hardware.h> #include "rockchip-common.h" #define CFG_IRAM_BASE 0x10080000 diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h index 15f77df3e17..bab4ca015f7 100644 --- a/include/configs/rk322x_common.h +++ b/include/configs/rk322x_common.h @@ -5,7 +5,6 @@ #ifndef __CONFIG_RK322X_COMMON_H #define __CONFIG_RK322X_COMMON_H -#include <asm/arch-rockchip/hardware.h> #include "rockchip-common.h" #define CFG_SYS_HZ_CLOCK 24000000 diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index 3063076a97a..0c449e31099 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -6,7 +6,6 @@ #ifndef __CONFIG_RK3288_COMMON_H #define __CONFIG_RK3288_COMMON_H -#include <asm/arch-rockchip/hardware.h> #include "rockchip-common.h" #define CFG_SYS_HZ_CLOCK 24000000 diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h index e920ec7e5dd..2c40674b224 100644 --- a/include/configs/rk3328_common.h +++ b/include/configs/rk3328_common.h @@ -26,6 +26,7 @@ ENV_MEM_LAYOUT_SETTINGS \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ "partitions=" PARTS_DEFAULT \ + ROCKCHIP_DEVICE_SETTINGS \ "boot_targets=" BOOT_TARGETS "\0" #endif diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h index ccb5369b901..d488f8d477a 100644 --- a/include/configs/rk3368_common.h +++ b/include/configs/rk3368_common.h @@ -8,7 +8,6 @@ #include "rockchip-common.h" -#include <asm/arch-rockchip/hardware.h> #include <linux/sizes.h> #define CFG_SYS_SDRAM_BASE 0 diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index 96ba19c659b..4e75771055b 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -13,22 +13,6 @@ #define CFG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xf8000000 -#define ROCKPI_4B_IDBLOADER_IMAGE_GUID \ - EFI_GUID(0x02f4d760, 0xcfd5, 0x43bd, 0x8e, 0x2d, \ - 0xa4, 0x2a, 0xcb, 0x33, 0xc6, 0x60) - -#define ROCKPI_4B_UBOOT_IMAGE_GUID \ - EFI_GUID(0x4ce292da, 0x1dd8, 0x428d, 0xa1, 0xc2, \ - 0x77, 0x74, 0x3e, 0xf8, 0xb9, 0x6e) - -#define ROCKPI_4C_IDBLOADER_IMAGE_GUID \ - EFI_GUID(0xfd68510c, 0x12d3, 0x4f0a, 0xb8, 0xd3, \ - 0xd8, 0x79, 0xe1, 0xd3, 0xa5, 0x40) - -#define ROCKPI_4C_UBOOT_IMAGE_GUID \ - EFI_GUID(0xb81fb4ae, 0xe4f3, 0x471b, 0x99, 0xb4, \ - 0x0b, 0x3d, 0xa5, 0x49, 0xce, 0x13) - #ifndef CONFIG_SPL_BUILD #define ENV_MEM_LAYOUT_SETTINGS \ diff --git a/include/configs/rockpi4-rk3399.h b/include/configs/rockpi4-rk3399.h new file mode 100644 index 00000000000..1936e06ab3c --- /dev/null +++ b/include/configs/rockpi4-rk3399.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + */ + +#ifndef __ROCKPI4_RK3399_H +#define __ROCKPI4_RK3399_H + +#define ROCKPI_4B_IDBLOADER_IMAGE_GUID \ + EFI_GUID(0x02f4d760, 0xcfd5, 0x43bd, 0x8e, 0x2d, \ + 0xa4, 0x2a, 0xcb, 0x33, 0xc6, 0x60) + +#define ROCKPI_4B_UBOOT_IMAGE_GUID \ + EFI_GUID(0x4ce292da, 0x1dd8, 0x428d, 0xa1, 0xc2, \ + 0x77, 0x74, 0x3e, 0xf8, 0xb9, 0x6e) + +#define ROCKPI_4C_IDBLOADER_IMAGE_GUID \ + EFI_GUID(0xfd68510c, 0x12d3, 0x4f0a, 0xb8, 0xd3, \ + 0xd8, 0x79, 0xe1, 0xd3, 0xa5, 0x40) + +#define ROCKPI_4C_UBOOT_IMAGE_GUID \ + EFI_GUID(0xb81fb4ae, 0xe4f3, 0x471b, 0x99, 0xb4, \ + 0x0b, 0x3d, 0xa5, 0x49, 0xce, 0x13) + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdin=serial,usbkbd\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#include <configs/rk3399_common.h> + +#endif diff --git a/include/configs/rv1108_common.h b/include/configs/rv1108_common.h index 3bf70a0e0ae..ff28236a21d 100644 --- a/include/configs/rv1108_common.h +++ b/include/configs/rv1108_common.h @@ -5,7 +5,6 @@ #ifndef __CONFIG_RV1108_COMMON_H #define __CONFIG_RV1108_COMMON_H -#include <asm/arch-rockchip/hardware.h> #include "rockchip-common.h" #define CFG_IRAM_BASE 0x10080000 diff --git a/include/configs/sama7g54_curiosity.h b/include/configs/sama7g54_curiosity.h new file mode 100644 index 00000000000..fe47236158e --- /dev/null +++ b/include/configs/sama7g54_curiosity.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration file for the SAMA7G54 CURIOSITY board. + * + * Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries + * + * Author: Mihai Sain <mihai.sain@microchip.com> + * + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CFG_SYS_AT91_SLOW_CLOCK 32768 +#define CFG_SYS_AT91_MAIN_CLOCK 24000000 + +#endif diff --git a/include/configs/sdm845.h b/include/configs/sdm845.h deleted file mode 100644 index 5ad8569b215..00000000000 --- a/include/configs/sdm845.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration file for boards, based on Qualcomm SDM845 chip - * - * (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com> - */ - -#ifndef __CONFIGS_SDM845_H -#define __CONFIGS_SDM845_H - -#include <linux/sizes.h> - -#define CFG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 } - -#define CFG_EXTRA_ENV_SETTINGS \ - "bootm_size=0x4000000\0" \ - "bootm_low=0x80000000\0" \ - "stdin=serial,button-kbd\0" \ - "stdout=serial,vidconsole\0" \ - "stderr=serial,vidconsole\0" \ - "preboot=source $prevbl_initrd_start_addr:prebootscript\0" \ - "bootcmd=source $prevbl_initrd_start_addr:bootscript\0" - -/* Size of malloc() pool */ - -#endif diff --git a/include/configs/slimbootloader.h b/include/configs/slimbootloader.h deleted file mode 100644 index 85f6a968e04..00000000000 --- a/include/configs/slimbootloader.h +++ /dev/null @@ -1,4 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2019 Intel Corporation <www.intel.com> - */ diff --git a/include/configs/socfpga_agilex5_socdk.h b/include/configs/socfpga_agilex5_socdk.h new file mode 100644 index 00000000000..b5b5bd767fb --- /dev/null +++ b/include/configs/socfpga_agilex5_socdk.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2024 Intel Corporation <www.intel.com> + * + */ + +#ifndef __CONFIG_SOCFGPA_AGILEX5_H__ +#define __CONFIG_SOCFGPA_AGILEX5_H__ + +#include <configs/socfpga_soc64_common.h> + +#endif /* __CONFIG_SOCFGPA_AGILEX5_H__ */ diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index 820372c28b3..b7ee1dbf201 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 * - * Copyright (C) 2017-2019 Intel Corporation <www.intel.com> + * Copyright (C) 2017-2024 Intel Corporation <www.intel.com> * */ @@ -26,8 +26,13 @@ /* * U-Boot run time memory configurations */ +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#define CFG_SYS_INIT_RAM_ADDR 0x0 +#define CFG_SYS_INIT_RAM_SIZE 0x80000 +#else #define CFG_SYS_INIT_RAM_ADDR 0xFFE00000 #define CFG_SYS_INIT_RAM_SIZE 0x40000 +#endif /* * U-Boot environment configurations @@ -36,9 +41,121 @@ /* * Environment variable */ +#if IS_ENABLED(CONFIG_DISTRO_DEFAULTS) +#if IS_ENABLED(CONFIG_CMD_MMC) +#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) +#else +#define BOOT_TARGET_DEVICES_MMC(func) +#endif + +#if IS_ENABLED(CONFIG_CMD_SF) +#define BOOT_TARGET_DEVICES_QSPI(func) func(QSPI, qspi, na) +#else +#define BOOT_TARGET_DEVICES_QSPI(func) +#endif + +#define BOOTENV_DEV_QSPI(devtypeu, devtypel, instance) \ + "bootcmd_qspi=ubi detach; sf probe && " \ + "if ubi part root && ubi readvol ${scriptaddr} script; " \ + "then echo QSPI: Running script from UBIFS; " \ + "elif sf read ${scriptaddr} ${qspiscriptaddr} ${scriptsize}; " \ + "then echo QSPI: Running script from JFFS2; fi; " \ + "echo QSPI: Trying to boot script at ${scriptaddr} && " \ + "source ${scriptaddr}; " \ + "echo QSPI: SCRIPT FAILED: continuing...; ubi detach;\0" + +#define BOOTENV_DEV_NAME_QSPI(devtypeu, devtypel, instance) \ + "qspi " + +#define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_DEVICES_MMC(func) \ + BOOT_TARGET_DEVICES_QSPI(func) + +#include <config_distro_bootcmd.h> + +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) + #define CFG_EXTRA_ENV_SETTINGS \ + "kernel_addr_r=0x82000000\0" \ + "fdt_addr_r=0x86000000\0" \ + "qspiscriptaddr=0x02110000\0" \ + "scriptsize=0x00010000\0" \ + "qspibootimageaddr=0x02120000\0" \ + "bootimagesize=0x03200000\0" \ "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "bootfile=" CONFIG_BOOTFILE "\0" \ + "mmcroot=/dev/mmcblk0p2\0" \ + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + "linux_qspi_enable=if sf probe; then " \ + "echo Enabling QSPI at Linux DTB...;" \ + "fdt addr ${fdt_addr}; fdt resize;" \ + "fdt set /soc/spi@108d2000 status okay;" \ + "if fdt set /clocks/qspi-clk clock-frequency" \ + " ${qspi_clock}; then echo QSPI clock frequency updated;" \ + " elif fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency" \ + " ${qspi_clock}; then echo QSPI clock frequency updated;" \ + " else fdt set /clocks/qspi-clk clock-frequency" \ + " ${qspi_clock}; echo QSPI clock frequency updated; fi; fi\0" \ + "scriptaddr=0x81000000\0" \ + "scriptfile=boot.scr\0" \ + "socfpga_legacy_reset_compat=1\0" \ + "smc_fid_rd=0xC2000007\0" \ + "smc_fid_wr=0xC2000008\0" \ + "smc_fid_upd=0xC2000009\0 " \ + BOOTENV + +#else + +#define CFG_EXTRA_ENV_SETTINGS \ + "kernel_addr_r=0x2000000\0" \ + "fdt_addr_r=0x6000000\0" \ + "qspiscriptaddr=0x02110000\0" \ + "scriptsize=0x00010000\0" \ + "qspibootimageaddr=0x02120000\0" \ + "bootimagesize=0x03200000\0" \ + "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "bootfile=" CONFIG_BOOTFILE "\0" \ + "mmcroot=/dev/mmcblk0p2\0" \ + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + "linux_qspi_enable=if sf probe; then " \ + "echo Enabling QSPI at Linux DTB...;" \ + "fdt addr ${fdt_addr}; fdt resize;" \ + "fdt set /soc/spi@ff8d2000 status okay;" \ + "if fdt set /soc/clocks/qspi-clk clock-frequency" \ + " ${qspi_clock}; then echo QSPI clock frequency updated;" \ + " elif fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency" \ + " ${qspi_clock}; then echo QSPI clock frequency updated;" \ + " else fdt set /clocks/qspi-clk clock-frequency" \ + " ${qspi_clock}; echo QSPI clock frequency updated; fi; fi\0" \ + "scriptaddr=0x05FF0000\0" \ + "scriptfile=boot.scr\0" \ + "socfpga_legacy_reset_compat=1\0" \ + "smc_fid_rd=0xC2000007\0" \ + "smc_fid_wr=0xC2000008\0" \ + "smc_fid_upd=0xC2000009\0 " \ + BOOTENV +#endif /*#IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)*/ + +#else + +#define CFG_EXTRA_ENV_SETTINGS \ + "kernel_comp_addr_r=0x9000000\0" \ + "kernel_comp_size=0x01000000\0" \ + "qspibootimageaddr=0x020E0000\0" \ + "qspifdtaddr=0x020D0000\0" \ + "bootimagesize=0x01F00000\0" \ + "fdtimagesize=0x00010000\0" \ + "qspiload=sf read ${loadaddr} ${qspibootimageaddr} ${bootimagesize};" \ + "sf read ${fdt_addr} ${qspifdtaddr} ${fdtimagesize}\0" \ + "qspiboot=setenv bootargs earlycon root=/dev/mtdblock1 rw " \ + "rootfstype=jffs2 rootwait;booti ${loadaddr} - ${fdt_addr}\0" \ + "qspifitload=sf read ${loadaddr} ${qspibootimageaddr} ${bootimagesize}\0" \ + "qspifitboot=setenv bootargs earlycon root=/dev/mtdblock1 rw " \ + "rootfstype=jffs2 rootwait;bootm ${loadaddr}\0" \ + "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "bootfile=" CONFIG_BOOTFILE "\0" \ "fdt_addr=8000000\0" \ "fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ "mmcroot=/dev/mmcblk0p2\0" \ @@ -53,24 +170,40 @@ "bootm ${loadaddr}\0" \ "mmcfitload=mmc rescan;" \ "load mmc 0:1 ${loadaddr} ${bootfile}\0" \ + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "linux_qspi_enable=if sf probe; then " \ "echo Enabling QSPI at Linux DTB...;" \ "fdt addr ${fdt_addr}; fdt resize;" \ "fdt set /soc/spi@ff8d2000 status okay;" \ - "fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency " \ - " ${qspi_clock}; fi; \0" \ + "if fdt set /soc/clocks/qspi-clk clock-frequency" \ + " ${qspi_clock}; then echo QSPI clock frequency updated;" \ + " elif fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency" \ + " ${qspi_clock}; then echo QSPI clock frequency updated;" \ + " else fdt set /clocks/qspi-clk clock-frequency" \ + " ${qspi_clock}; echo QSPI clock frequency updated; fi; fi\0" \ "scriptaddr=0x02100000\0" \ "scriptfile=u-boot.scr\0" \ "fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \ - "then source ${scriptaddr}; fi\0" \ - "socfpga_legacy_reset_compat=1\0" + "then source ${scriptaddr}:script; fi\0" \ + "socfpga_legacy_reset_compat=1\0" \ + "smc_fid_rd=0xC2000007\0" \ + "smc_fid_wr=0xC2000008\0" \ + "smc_fid_upd=0xC2000009\0 " +#endif /*#if IS_ENABLED(CONFIG_DISTRO_DEFAULTS)*/ /* * External memory configurations */ +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_1_SIZE (1 * 1024 * 1024 * 1024) +#define CFG_SYS_SDRAM_BASE 0x80000000 +#else #define PHYS_SDRAM_1 0x0 #define PHYS_SDRAM_1_SIZE (1 * 1024 * 1024 * 1024) #define CFG_SYS_SDRAM_BASE 0 +#endif /* * Serial / UART configurations diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h deleted file mode 100644 index 7eadb6d421e..00000000000 --- a/include/configs/stv0991.h +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014, STMicroelectronics - All Rights Reserved - * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. - */ - -#ifndef __CONFIG_STV0991_H -#define __CONFIG_STV0991_H -#define CFG_SYS_EXCEPTION_VECTORS_HIGH - -/* ram memory-related information */ -#define PHYS_SDRAM_1 0x00000000 -#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define PHYS_SDRAM_1_SIZE 0x00198000 - -/* user interface */ - -/* MISC */ -#define CFG_SYS_INIT_RAM_SIZE 0x8000 -#define CFG_SYS_INIT_RAM_ADDR 0x00190000 -/* U-Boot Load Address */ - -/* Misc configuration */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/synquacer.h b/include/configs/synquacer.h index e36e63e81e4..f0867227acc 100644 --- a/include/configs/synquacer.h +++ b/include/configs/synquacer.h @@ -21,6 +21,7 @@ /* * Boot info */ +#define SCB_PLAT_METADATA_OFFSET (0x510000) /* * Hardware drivers support diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h index 0d0965ecce2..fc74980f7ca 100644 --- a/include/configs/tegra-common-post.h +++ b/include/configs/tegra-common-post.h @@ -7,33 +7,7 @@ #ifndef __TEGRA_COMMON_POST_H #define __TEGRA_COMMON_POST_H -#if IS_ENABLED(CONFIG_CMD_USB) -#define BOOT_TARGET_USB(func) func(USB, usb, 0) -#else -#define BOOT_TARGET_USB(func) -#endif - -#if CONFIG_IS_ENABLED(CMD_DHCP) && CONFIG_IS_ENABLED(CMD_PXE) -#define BOOT_TARGET_PXE(func) func(PXE, pxe, na) -#else -#define BOOT_TARGET_PXE(func) -#endif - -#if CONFIG_IS_ENABLED(CMD_DHCP) -#define BOOT_TARGET_DHCP(func) func(DHCP, dhcp, na) -#else -#define BOOT_TARGET_DHCP(func) -#endif - -#ifndef BOOT_TARGET_DEVICES -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 1) \ - func(MMC, mmc, 0) \ - BOOT_TARGET_USB(func) \ - BOOT_TARGET_PXE(func) \ - BOOT_TARGET_DHCP(func) -#endif -#include <config_distro_bootcmd.h> +#define BOOT_TARGETS "mmc1 mmc0 usb pxe dhcp" #ifdef CONFIG_TEGRA_KEYBOARD #define STDIN_KBD_KBC ",tegra-kbc" @@ -88,7 +62,7 @@ MEM_LAYOUT_ENV_SETTINGS \ "fdt_high=" FDT_HIGH "\0" \ "initrd_high=" INITRD_HIGH "\0" \ - BOOTENV \ + "boot_targets=" BOOT_TARGETS "\0" \ BOARD_EXTRA_ENV_SETTINGS #endif /* __TEGRA_COMMON_POST_H */ diff --git a/include/configs/toybrick_rk3588.h b/include/configs/toybrick_rk3588.h new file mode 100644 index 00000000000..faa2e6c19c3 --- /dev/null +++ b/include/configs/toybrick_rk3588.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + */ + +#ifndef __TOYBRICK_RK3588_H +#define __TOYBRICK_RK3588_H + +#include <configs/rk3588_common.h> + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#endif diff --git a/include/configs/transformer-common.h b/include/configs/transformer-common.h index 3b7db0ab142..bb6817c8d2b 100644 --- a/include/configs/transformer-common.h +++ b/include/configs/transformer-common.h @@ -71,18 +71,20 @@ "bootmenu_1=mount external storage=usb start && ums 0 mmc 1; bootmenu\0" \ "bootmenu_2=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu\0" \ "bootmenu_3=update bootloader=run flash_uboot\0" \ - "bootmenu_4=enter console=usb start; setenv skip_boot 1; exit\0" \ - "bootmenu_5=reboot RCM=enterrcm\0" \ - "bootmenu_6=reboot=reset\0" \ - "bootmenu_7=power off=poweroff\0" \ + "bootmenu_4=reboot RCM=enterrcm\0" \ + "bootmenu_5=reboot=reset\0" \ + "bootmenu_6=power off=poweroff\0" \ "bootmenu_delay=-1\0" #define BOARD_EXTRA_ENV_SETTINGS \ "spi_size=0x400000\0" \ "boot_block_size_r=0x200000\0" \ "boot_block_size=0x1000\0" \ - "check_button=gpio input ${gpio_button}; test $? -eq 0;\0" \ "bootloader_file=u-boot-dtb-tegra.bin\0" \ + "button_cmd_0_name=Volume Down\0" \ + "button_cmd_0=bootmenu\0" \ + "button_cmd_1_name=Lid sensor\0" \ + "button_cmd_1=poweroff\0" \ "partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs}\0" \ TRANSFORMER_BOOTMENU diff --git a/include/configs/verdin-imx8mm.h b/include/configs/verdin-imx8mm.h index a7ea02807dd..34238d3b505 100644 --- a/include/configs/verdin-imx8mm.h +++ b/include/configs/verdin-imx8mm.h @@ -37,14 +37,11 @@ #define CFG_EXTRA_ENV_SETTINGS \ BOOTENV \ MEM_LAYOUT_ENV_SETTINGS \ - "boot_file=Image\0" \ "boot_script_dhcp=boot.scr\0" \ "console=ttymxc0\0" \ "fdt_board=dev\0" \ "initrd_addr=0x43800000\0" \ "initrd_high=0xffffffffffffffff\0" \ - "setup=setenv setupargs console=tty1 console=${console},${baudrate} " \ - "consoleblank=0 earlycon\0" \ "update_uboot=askenv confirm Did you load flash.bin (y/N)?; " \ "if test \"$confirm\" = \"y\"; then " \ "setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \ diff --git a/include/configs/verdin-imx8mp.h b/include/configs/verdin-imx8mp.h index 256bab089ff..0b88e95603d 100644 --- a/include/configs/verdin-imx8mp.h +++ b/include/configs/verdin-imx8mp.h @@ -13,7 +13,6 @@ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD -/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CFG_MALLOC_F_ADDR 0x184000 @@ -40,15 +39,11 @@ #define CFG_EXTRA_ENV_SETTINGS \ BOOTENV \ MEM_LAYOUT_ENV_SETTINGS \ - "boot_file=Image\0" \ - "boot_scripts=boot.scr\0" \ "boot_script_dhcp=boot.scr\0" \ "console=ttymxc2\0" \ "fdt_board=dev\0" \ "initrd_addr=0x43800000\0" \ "initrd_high=0xffffffffffffffff\0" \ - "setup=setenv setupargs console=tty1 console=${console},${baudrate} " \ - "consoleblank=0 earlycon\0" \ "update_uboot=askenv confirm Did you load flash.bin (y/N)?; " \ "if test \"$confirm\" = \"y\"; then " \ "setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \ diff --git a/include/configs/x3-t30.h b/include/configs/x3-t30.h index 14532542ea6..78a20128611 100644 --- a/include/configs/x3-t30.h +++ b/include/configs/x3-t30.h @@ -54,7 +54,8 @@ "boot_block_size_r=0x200000\0" \ "boot_block_size=0x1000\0" \ "bootloader_file=u-boot-dtb-tegra.bin\0" \ - "check_button=gpio input 116; test $? -eq 0\0" \ + "button_cmd_0_name=Volume Down\0" \ + "button_cmd_0=bootmenu\0" \ "partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs}\0" \ X3_BOOTMENU diff --git a/include/configs/xilinx_mbv.h b/include/configs/xilinx_mbv.h deleted file mode 100644 index dba398aeec4..00000000000 --- a/include/configs/xilinx_mbv.h +++ /dev/null @@ -1,6 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * (C) Copyright 2023, Advanced Micro Devices, Inc. - * - * Michal Simek <michal.simek@amd.com> - */ diff --git a/include/cp1250.h b/include/cp1250.h index adacf8a9580..b762c78d9f6 100644 --- a/include/cp1250.h +++ b/include/cp1250.h @@ -1,10 +1,18 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Constant CP1250 contains the Unicode code points for characters 0x80 - 0xff - * of the code page 1250. + * Constant CP1250 contains the Unicode code points for characters 0x00 - 0x1f + * and 0x80 - 0xff of the code page 1250. */ #define CP1250 { \ + 0x0000, 0x0000, 0x0000, 0x0000, \ + 0x0000, 0x0000, 0x0000, 0x0000, \ + 0x0000, 0x0000, 0x0000, 0x0000, \ + 0x0000, 0x0000, 0x0000, 0x0000, \ + 0x0000, 0x0000, 0x0000, 0x0000, \ + 0x0000, 0x0000, 0x0000, 0x0000, \ + 0x0000, 0x0000, 0x0000, 0x0000, \ + 0x0000, 0x0000, 0x0000, 0x0000, \ 0x20ac, 0x0000, 0x201a, 0x0000, \ 0x201e, 0x2026, 0x2020, 0x2021, \ 0x0000, 0x2030, 0x0160, 0x2039, \ diff --git a/include/cp437.h b/include/cp437.h index 0b2b97132e3..5093130f5ed 100644 --- a/include/cp437.h +++ b/include/cp437.h @@ -1,10 +1,18 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Constant CP437 contains the Unicode code points for characters 0x80 - 0xff - * of the code page 437. + * Constant CP437 contains the Unicode code points for characters 0x00 - 0x1f + * and 0x80 - 0xff of the code page 437. */ #define CP437 { \ + 0x0000, 0x263a, 0x263b, 0x2665, \ + 0x2666, 0x2663, 0x2660, 0x2022, \ + 0x25d8, 0x25cb, 0x25d9, 0x2642, \ + 0x2640, 0x266a, 0x266b, 0x263c, \ + 0x25ba, 0x25c4, 0x2195, 0x203c, \ + 0x00b6, 0x00a7, 0x25ac, 0x21a8, \ + 0x2191, 0x2193, 0x2192, 0x2190, \ + 0x221f, 0x2194, 0x25b2, 0x25bc, \ 0x00c7, 0x00fc, 0x00e9, 0x00e2, \ 0x00e4, 0x00e0, 0x00e5, 0x00e7, \ 0x00ea, 0x00eb, 0x00e8, 0x00ef, \ diff --git a/include/dt-bindings/arm/coresight-cti-dt.h b/include/dt-bindings/arm/coresight-cti-dt.h new file mode 100644 index 00000000000..61e7bdf8ea6 --- /dev/null +++ b/include/dt-bindings/arm/coresight-cti-dt.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides constants for the defined trigger signal + * types on CoreSight CTI. + */ + +#ifndef _DT_BINDINGS_ARM_CORESIGHT_CTI_DT_H +#define _DT_BINDINGS_ARM_CORESIGHT_CTI_DT_H + +#define GEN_IO 0 +#define GEN_INTREQ 1 +#define GEN_INTACK 2 +#define GEN_HALTREQ 3 +#define GEN_RESTARTREQ 4 +#define PE_EDBGREQ 5 +#define PE_DBGRESTART 6 +#define PE_CTIIRQ 7 +#define PE_PMUIRQ 8 +#define PE_DBGTRIGGER 9 +#define ETM_EXTOUT 10 +#define ETM_EXTIN 11 +#define SNK_FULL 12 +#define SNK_ACQCOMP 13 +#define SNK_FLUSHCOMP 14 +#define SNK_FLUSHIN 15 +#define SNK_TRIGIN 16 +#define STM_ASYNCOUT 17 +#define STM_TOUT_SPTE 18 +#define STM_TOUT_SW 19 +#define STM_TOUT_HETE 20 +#define STM_HWEVENT 21 +#define ELA_TSTART 22 +#define ELA_TSTOP 23 +#define ELA_DBGREQ 24 +#define CTI_TRIG_MAX 25 + +#endif /*_DT_BINDINGS_ARM_CORESIGHT_CTI_DT_H */ diff --git a/include/dt-bindings/clock/agilex5-clock.h b/include/dt-bindings/clock/agilex5-clock.h new file mode 100644 index 00000000000..c84fa51540c --- /dev/null +++ b/include/dt-bindings/clock/agilex5-clock.h @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2024, Intel Corporation + */ + +#ifndef __AGILEX5_CLOCK_H +#define __AGILEX5_CLOCK_H + +/* fixed rate clocks */ +#define AGILEX5_OSC1 0 +#define AGILEX5_CB_INTOSC_HS_DIV2_CLK 1 +#define AGILEX5_CB_INTOSC_LS_CLK 2 +#define AGILEX5_L4_SYS_FREE_CLK 3 +#define AGILEX5_F2S_FREE_CLK 4 + +/* PLL clocks */ +#define AGILEX5_MAIN_PLL_CLK 5 +#define AGILEX5_MAIN_PLL_C0_CLK 6 +#define AGILEX5_MAIN_PLL_C1_CLK 7 +#define AGILEX5_MAIN_PLL_C2_CLK 8 +#define AGILEX5_MAIN_PLL_C3_CLK 9 +#define AGILEX5_PERIPH_PLL_CLK 10 +#define AGILEX5_PERIPH_PLL_C0_CLK 11 +#define AGILEX5_PERIPH_PLL_C1_CLK 12 +#define AGILEX5_PERIPH_PLL_C2_CLK 13 +#define AGILEX5_PERIPH_PLL_C3_CLK 14 +#define AGILEX5_MPU_FREE_CLK 15 +#define AGILEX5_MPU_CCU_CLK 16 +#define AGILEX5_BOOT_CLK 17 + +/* fixed factor clocks */ +#define AGILEX5_L3_MAIN_FREE_CLK 18 +#define AGILEX5_NOC_FREE_CLK 19 +#define AGILEX5_S2F_USR0_CLK 20 +#define AGILEX5_NOC_CLK 21 +#define AGILEX5_EMAC_A_FREE_CLK 22 +#define AGILEX5_EMAC_B_FREE_CLK 23 +#define AGILEX5_EMAC_PTP_FREE_CLK 24 +#define AGILEX5_GPIO_DB_FREE_CLK 25 +#define AGILEX5_SDMMC_FREE_CLK 26 +#define AGILEX5_S2F_USER0_FREE_CLK 27 +#define AGILEX5_S2F_USER1_FREE_CLK 28 +#define AGILEX5_PSI_REF_FREE_CLK 29 + +/* Gate clocks */ +#define AGILEX5_MPU_CLK 30 +#define AGILEX5_MPU_PERIPH_CLK 31 +#define AGILEX5_L4_MAIN_CLK 32 +#define AGILEX5_L4_MP_CLK 33 +#define AGILEX5_L4_SP_CLK 34 +#define AGILEX5_CS_AT_CLK 35 +#define AGILEX5_CS_TRACE_CLK 36 +#define AGILEX5_CS_PDBG_CLK 37 +#define AGILEX5_CS_TIMER_CLK 38 +#define AGILEX5_S2F_USER0_CLK 39 +#define AGILEX5_EMAC0_CLK 40 +#define AGILEX5_EMAC1_CLK 41 +#define AGILEX5_EMAC2_CLK 42 +#define AGILEX5_EMAC_PTP_CLK 43 +#define AGILEX5_GPIO_DB_CLK 44 +#define AGILEX5_NAND_CLK 45 +#define AGILEX5_PSI_REF_CLK 46 +#define AGILEX5_S2F_USER1_CLK 47 +#define AGILEX5_SDMMC_CLK 48 +#define AGILEX5_SPI_M_CLK 49 +#define AGILEX5_USB_CLK 50 +#define AGILEX5_NAND_X_CLK 51 +#define AGILEX5_NAND_ECC_CLK 52 +#define AGILEX5_NUM_CLKS 53 + +#endif /* __AGILEX5_CLOCK_H */ diff --git a/include/dt-bindings/clock/qcom,camcc-sdm845.h b/include/dt-bindings/clock/qcom,camcc-sdm845.h new file mode 100644 index 00000000000..4f7a2d2320b --- /dev/null +++ b/include/dt-bindings/clock/qcom,camcc-sdm845.h @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_SDM_CAM_CC_SDM845_H +#define _DT_BINDINGS_CLK_SDM_CAM_CC_SDM845_H + +/* CAM_CC clock registers */ +#define CAM_CC_BPS_AHB_CLK 0 +#define CAM_CC_BPS_AREG_CLK 1 +#define CAM_CC_BPS_AXI_CLK 2 +#define CAM_CC_BPS_CLK 3 +#define CAM_CC_BPS_CLK_SRC 4 +#define CAM_CC_CAMNOC_ATB_CLK 5 +#define CAM_CC_CAMNOC_AXI_CLK 6 +#define CAM_CC_CCI_CLK 7 +#define CAM_CC_CCI_CLK_SRC 8 +#define CAM_CC_CPAS_AHB_CLK 9 +#define CAM_CC_CPHY_RX_CLK_SRC 10 +#define CAM_CC_CSI0PHYTIMER_CLK 11 +#define CAM_CC_CSI0PHYTIMER_CLK_SRC 12 +#define CAM_CC_CSI1PHYTIMER_CLK 13 +#define CAM_CC_CSI1PHYTIMER_CLK_SRC 14 +#define CAM_CC_CSI2PHYTIMER_CLK 15 +#define CAM_CC_CSI2PHYTIMER_CLK_SRC 16 +#define CAM_CC_CSI3PHYTIMER_CLK 17 +#define CAM_CC_CSI3PHYTIMER_CLK_SRC 18 +#define CAM_CC_CSIPHY0_CLK 19 +#define CAM_CC_CSIPHY1_CLK 20 +#define CAM_CC_CSIPHY2_CLK 21 +#define CAM_CC_CSIPHY3_CLK 22 +#define CAM_CC_FAST_AHB_CLK_SRC 23 +#define CAM_CC_FD_CORE_CLK 24 +#define CAM_CC_FD_CORE_CLK_SRC 25 +#define CAM_CC_FD_CORE_UAR_CLK 26 +#define CAM_CC_ICP_APB_CLK 27 +#define CAM_CC_ICP_ATB_CLK 28 +#define CAM_CC_ICP_CLK 29 +#define CAM_CC_ICP_CLK_SRC 30 +#define CAM_CC_ICP_CTI_CLK 31 +#define CAM_CC_ICP_TS_CLK 32 +#define CAM_CC_IFE_0_AXI_CLK 33 +#define CAM_CC_IFE_0_CLK 34 +#define CAM_CC_IFE_0_CLK_SRC 35 +#define CAM_CC_IFE_0_CPHY_RX_CLK 36 +#define CAM_CC_IFE_0_CSID_CLK 37 +#define CAM_CC_IFE_0_CSID_CLK_SRC 38 +#define CAM_CC_IFE_0_DSP_CLK 39 +#define CAM_CC_IFE_1_AXI_CLK 40 +#define CAM_CC_IFE_1_CLK 41 +#define CAM_CC_IFE_1_CLK_SRC 42 +#define CAM_CC_IFE_1_CPHY_RX_CLK 43 +#define CAM_CC_IFE_1_CSID_CLK 44 +#define CAM_CC_IFE_1_CSID_CLK_SRC 45 +#define CAM_CC_IFE_1_DSP_CLK 46 +#define CAM_CC_IFE_LITE_CLK 47 +#define CAM_CC_IFE_LITE_CLK_SRC 48 +#define CAM_CC_IFE_LITE_CPHY_RX_CLK 49 +#define CAM_CC_IFE_LITE_CSID_CLK 50 +#define CAM_CC_IFE_LITE_CSID_CLK_SRC 51 +#define CAM_CC_IPE_0_AHB_CLK 52 +#define CAM_CC_IPE_0_AREG_CLK 53 +#define CAM_CC_IPE_0_AXI_CLK 54 +#define CAM_CC_IPE_0_CLK 55 +#define CAM_CC_IPE_0_CLK_SRC 56 +#define CAM_CC_IPE_1_AHB_CLK 57 +#define CAM_CC_IPE_1_AREG_CLK 58 +#define CAM_CC_IPE_1_AXI_CLK 59 +#define CAM_CC_IPE_1_CLK 60 +#define CAM_CC_IPE_1_CLK_SRC 61 +#define CAM_CC_JPEG_CLK 62 +#define CAM_CC_JPEG_CLK_SRC 63 +#define CAM_CC_LRME_CLK 64 +#define CAM_CC_LRME_CLK_SRC 65 +#define CAM_CC_MCLK0_CLK 66 +#define CAM_CC_MCLK0_CLK_SRC 67 +#define CAM_CC_MCLK1_CLK 68 +#define CAM_CC_MCLK1_CLK_SRC 69 +#define CAM_CC_MCLK2_CLK 70 +#define CAM_CC_MCLK2_CLK_SRC 71 +#define CAM_CC_MCLK3_CLK 72 +#define CAM_CC_MCLK3_CLK_SRC 73 +#define CAM_CC_PLL0 74 +#define CAM_CC_PLL0_OUT_EVEN 75 +#define CAM_CC_PLL1 76 +#define CAM_CC_PLL1_OUT_EVEN 77 +#define CAM_CC_PLL2 78 +#define CAM_CC_PLL2_OUT_EVEN 79 +#define CAM_CC_PLL3 80 +#define CAM_CC_PLL3_OUT_EVEN 81 +#define CAM_CC_SLOW_AHB_CLK_SRC 82 +#define CAM_CC_SOC_AHB_CLK 83 +#define CAM_CC_SYS_TMR_CLK 84 + +/* CAM_CC Resets */ +#define TITAN_CAM_CC_CCI_BCR 0 +#define TITAN_CAM_CC_CPAS_BCR 1 +#define TITAN_CAM_CC_CSI0PHY_BCR 2 +#define TITAN_CAM_CC_CSI1PHY_BCR 3 +#define TITAN_CAM_CC_CSI2PHY_BCR 4 +#define TITAN_CAM_CC_MCLK0_BCR 5 +#define TITAN_CAM_CC_MCLK1_BCR 6 +#define TITAN_CAM_CC_MCLK2_BCR 7 +#define TITAN_CAM_CC_MCLK3_BCR 8 +#define TITAN_CAM_CC_TITAN_TOP_BCR 9 + +/* CAM_CC GDSCRs */ +#define BPS_GDSC 0 +#define IPE_0_GDSC 1 +#define IPE_1_GDSC 2 +#define IFE_0_GDSC 3 +#define IFE_1_GDSC 4 +#define TITAN_TOP_GDSC 5 + +#endif diff --git a/include/dt-bindings/clock/qcom,dispcc-sdm845.h b/include/dt-bindings/clock/qcom,dispcc-sdm845.h new file mode 100644 index 00000000000..4016fd1d5b4 --- /dev/null +++ b/include/dt-bindings/clock/qcom,dispcc-sdm845.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_SDM_DISP_CC_SDM845_H +#define _DT_BINDINGS_CLK_SDM_DISP_CC_SDM845_H + +/* DISP_CC clock registers */ +#define DISP_CC_MDSS_AHB_CLK 0 +#define DISP_CC_MDSS_AXI_CLK 1 +#define DISP_CC_MDSS_BYTE0_CLK 2 +#define DISP_CC_MDSS_BYTE0_CLK_SRC 3 +#define DISP_CC_MDSS_BYTE0_INTF_CLK 4 +#define DISP_CC_MDSS_BYTE1_CLK 5 +#define DISP_CC_MDSS_BYTE1_CLK_SRC 6 +#define DISP_CC_MDSS_BYTE1_INTF_CLK 7 +#define DISP_CC_MDSS_ESC0_CLK 8 +#define DISP_CC_MDSS_ESC0_CLK_SRC 9 +#define DISP_CC_MDSS_ESC1_CLK 10 +#define DISP_CC_MDSS_ESC1_CLK_SRC 11 +#define DISP_CC_MDSS_MDP_CLK 12 +#define DISP_CC_MDSS_MDP_CLK_SRC 13 +#define DISP_CC_MDSS_MDP_LUT_CLK 14 +#define DISP_CC_MDSS_PCLK0_CLK 15 +#define DISP_CC_MDSS_PCLK0_CLK_SRC 16 +#define DISP_CC_MDSS_PCLK1_CLK 17 +#define DISP_CC_MDSS_PCLK1_CLK_SRC 18 +#define DISP_CC_MDSS_ROT_CLK 19 +#define DISP_CC_MDSS_ROT_CLK_SRC 20 +#define DISP_CC_MDSS_RSCC_AHB_CLK 21 +#define DISP_CC_MDSS_RSCC_VSYNC_CLK 22 +#define DISP_CC_MDSS_VSYNC_CLK 23 +#define DISP_CC_MDSS_VSYNC_CLK_SRC 24 +#define DISP_CC_PLL0 25 +#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 26 +#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 27 +#define DISP_CC_MDSS_DP_AUX_CLK 28 +#define DISP_CC_MDSS_DP_AUX_CLK_SRC 29 +#define DISP_CC_MDSS_DP_CRYPTO_CLK 30 +#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC 31 +#define DISP_CC_MDSS_DP_LINK_CLK 32 +#define DISP_CC_MDSS_DP_LINK_CLK_SRC 33 +#define DISP_CC_MDSS_DP_LINK_INTF_CLK 34 +#define DISP_CC_MDSS_DP_PIXEL1_CLK 35 +#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC 36 +#define DISP_CC_MDSS_DP_PIXEL_CLK 37 +#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 38 + +/* DISP_CC Reset */ +#define DISP_CC_MDSS_RSCC_BCR 0 + +/* DISP_CC GDSCR */ +#define MDSS_GDSC 0 + +#endif diff --git a/include/dt-bindings/clock/qcom,gcc-msm8916.h b/include/dt-bindings/clock/qcom,gcc-msm8916.h new file mode 100644 index 00000000000..56303440618 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-msm8916.h @@ -0,0 +1,179 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright 2015 Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_MSM_GCC_8916_H +#define _DT_BINDINGS_CLK_MSM_GCC_8916_H + +#define GPLL0 0 +#define GPLL0_VOTE 1 +#define BIMC_PLL 2 +#define BIMC_PLL_VOTE 3 +#define GPLL1 4 +#define GPLL1_VOTE 5 +#define GPLL2 6 +#define GPLL2_VOTE 7 +#define PCNOC_BFDCD_CLK_SRC 8 +#define SYSTEM_NOC_BFDCD_CLK_SRC 9 +#define CAMSS_AHB_CLK_SRC 10 +#define APSS_AHB_CLK_SRC 11 +#define CSI0_CLK_SRC 12 +#define CSI1_CLK_SRC 13 +#define GFX3D_CLK_SRC 14 +#define VFE0_CLK_SRC 15 +#define BLSP1_QUP1_I2C_APPS_CLK_SRC 16 +#define BLSP1_QUP1_SPI_APPS_CLK_SRC 17 +#define BLSP1_QUP2_I2C_APPS_CLK_SRC 18 +#define BLSP1_QUP2_SPI_APPS_CLK_SRC 19 +#define BLSP1_QUP3_I2C_APPS_CLK_SRC 20 +#define BLSP1_QUP3_SPI_APPS_CLK_SRC 21 +#define BLSP1_QUP4_I2C_APPS_CLK_SRC 22 +#define BLSP1_QUP4_SPI_APPS_CLK_SRC 23 +#define BLSP1_QUP5_I2C_APPS_CLK_SRC 24 +#define BLSP1_QUP5_SPI_APPS_CLK_SRC 25 +#define BLSP1_QUP6_I2C_APPS_CLK_SRC 26 +#define BLSP1_QUP6_SPI_APPS_CLK_SRC 27 +#define BLSP1_UART1_APPS_CLK_SRC 28 +#define BLSP1_UART2_APPS_CLK_SRC 29 +#define CCI_CLK_SRC 30 +#define CAMSS_GP0_CLK_SRC 31 +#define CAMSS_GP1_CLK_SRC 32 +#define JPEG0_CLK_SRC 33 +#define MCLK0_CLK_SRC 34 +#define MCLK1_CLK_SRC 35 +#define CSI0PHYTIMER_CLK_SRC 36 +#define CSI1PHYTIMER_CLK_SRC 37 +#define CPP_CLK_SRC 38 +#define CRYPTO_CLK_SRC 39 +#define GP1_CLK_SRC 40 +#define GP2_CLK_SRC 41 +#define GP3_CLK_SRC 42 +#define BYTE0_CLK_SRC 43 +#define ESC0_CLK_SRC 44 +#define MDP_CLK_SRC 45 +#define PCLK0_CLK_SRC 46 +#define VSYNC_CLK_SRC 47 +#define PDM2_CLK_SRC 48 +#define SDCC1_APPS_CLK_SRC 49 +#define SDCC2_APPS_CLK_SRC 50 +#define APSS_TCU_CLK_SRC 51 +#define USB_HS_SYSTEM_CLK_SRC 52 +#define VCODEC0_CLK_SRC 53 +#define GCC_BLSP1_AHB_CLK 54 +#define GCC_BLSP1_SLEEP_CLK 55 +#define GCC_BLSP1_QUP1_I2C_APPS_CLK 56 +#define GCC_BLSP1_QUP1_SPI_APPS_CLK 57 +#define GCC_BLSP1_QUP2_I2C_APPS_CLK 58 +#define GCC_BLSP1_QUP2_SPI_APPS_CLK 59 +#define GCC_BLSP1_QUP3_I2C_APPS_CLK 60 +#define GCC_BLSP1_QUP3_SPI_APPS_CLK 61 +#define GCC_BLSP1_QUP4_I2C_APPS_CLK 62 +#define GCC_BLSP1_QUP4_SPI_APPS_CLK 63 +#define GCC_BLSP1_QUP5_I2C_APPS_CLK 64 +#define GCC_BLSP1_QUP5_SPI_APPS_CLK 65 +#define GCC_BLSP1_QUP6_I2C_APPS_CLK 66 +#define GCC_BLSP1_QUP6_SPI_APPS_CLK 67 +#define GCC_BLSP1_UART1_APPS_CLK 68 +#define GCC_BLSP1_UART2_APPS_CLK 69 +#define GCC_BOOT_ROM_AHB_CLK 70 +#define GCC_CAMSS_CCI_AHB_CLK 71 +#define GCC_CAMSS_CCI_CLK 72 +#define GCC_CAMSS_CSI0_AHB_CLK 73 +#define GCC_CAMSS_CSI0_CLK 74 +#define GCC_CAMSS_CSI0PHY_CLK 75 +#define GCC_CAMSS_CSI0PIX_CLK 76 +#define GCC_CAMSS_CSI0RDI_CLK 77 +#define GCC_CAMSS_CSI1_AHB_CLK 78 +#define GCC_CAMSS_CSI1_CLK 79 +#define GCC_CAMSS_CSI1PHY_CLK 80 +#define GCC_CAMSS_CSI1PIX_CLK 81 +#define GCC_CAMSS_CSI1RDI_CLK 82 +#define GCC_CAMSS_CSI_VFE0_CLK 83 +#define GCC_CAMSS_GP0_CLK 84 +#define GCC_CAMSS_GP1_CLK 85 +#define GCC_CAMSS_ISPIF_AHB_CLK 86 +#define GCC_CAMSS_JPEG0_CLK 87 +#define GCC_CAMSS_JPEG_AHB_CLK 88 +#define GCC_CAMSS_JPEG_AXI_CLK 89 +#define GCC_CAMSS_MCLK0_CLK 90 +#define GCC_CAMSS_MCLK1_CLK 91 +#define GCC_CAMSS_MICRO_AHB_CLK 92 +#define GCC_CAMSS_CSI0PHYTIMER_CLK 93 +#define GCC_CAMSS_CSI1PHYTIMER_CLK 94 +#define GCC_CAMSS_AHB_CLK 95 +#define GCC_CAMSS_TOP_AHB_CLK 96 +#define GCC_CAMSS_CPP_AHB_CLK 97 +#define GCC_CAMSS_CPP_CLK 98 +#define GCC_CAMSS_VFE0_CLK 99 +#define GCC_CAMSS_VFE_AHB_CLK 100 +#define GCC_CAMSS_VFE_AXI_CLK 101 +#define GCC_CRYPTO_AHB_CLK 102 +#define GCC_CRYPTO_AXI_CLK 103 +#define GCC_CRYPTO_CLK 104 +#define GCC_OXILI_GMEM_CLK 105 +#define GCC_GP1_CLK 106 +#define GCC_GP2_CLK 107 +#define GCC_GP3_CLK 108 +#define GCC_MDSS_AHB_CLK 109 +#define GCC_MDSS_AXI_CLK 110 +#define GCC_MDSS_BYTE0_CLK 111 +#define GCC_MDSS_ESC0_CLK 112 +#define GCC_MDSS_MDP_CLK 113 +#define GCC_MDSS_PCLK0_CLK 114 +#define GCC_MDSS_VSYNC_CLK 115 +#define GCC_MSS_CFG_AHB_CLK 116 +#define GCC_OXILI_AHB_CLK 117 +#define GCC_OXILI_GFX3D_CLK 118 +#define GCC_PDM2_CLK 119 +#define GCC_PDM_AHB_CLK 120 +#define GCC_PRNG_AHB_CLK 121 +#define GCC_SDCC1_AHB_CLK 122 +#define GCC_SDCC1_APPS_CLK 123 +#define GCC_SDCC2_AHB_CLK 124 +#define GCC_SDCC2_APPS_CLK 125 +#define GCC_GTCU_AHB_CLK 126 +#define GCC_JPEG_TBU_CLK 127 +#define GCC_MDP_TBU_CLK 128 +#define GCC_SMMU_CFG_CLK 129 +#define GCC_VENUS_TBU_CLK 130 +#define GCC_VFE_TBU_CLK 131 +#define GCC_USB2A_PHY_SLEEP_CLK 132 +#define GCC_USB_HS_AHB_CLK 133 +#define GCC_USB_HS_SYSTEM_CLK 134 +#define GCC_VENUS0_AHB_CLK 135 +#define GCC_VENUS0_AXI_CLK 136 +#define GCC_VENUS0_VCODEC0_CLK 137 +#define BIMC_DDR_CLK_SRC 138 +#define GCC_APSS_TCU_CLK 139 +#define GCC_GFX_TCU_CLK 140 +#define BIMC_GPU_CLK_SRC 141 +#define GCC_BIMC_GFX_CLK 142 +#define GCC_BIMC_GPU_CLK 143 +#define ULTAUDIO_LPAIF_PRI_I2S_CLK_SRC 144 +#define ULTAUDIO_LPAIF_SEC_I2S_CLK_SRC 145 +#define ULTAUDIO_LPAIF_AUX_I2S_CLK_SRC 146 +#define ULTAUDIO_XO_CLK_SRC 147 +#define ULTAUDIO_AHBFABRIC_CLK_SRC 148 +#define CODEC_DIGCODEC_CLK_SRC 149 +#define GCC_ULTAUDIO_PCNOC_MPORT_CLK 150 +#define GCC_ULTAUDIO_PCNOC_SWAY_CLK 151 +#define GCC_ULTAUDIO_AVSYNC_XO_CLK 152 +#define GCC_ULTAUDIO_STC_XO_CLK 153 +#define GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK 154 +#define GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CLK 155 +#define GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK 156 +#define GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK 157 +#define GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK 158 +#define GCC_CODEC_DIGCODEC_CLK 159 +#define GCC_MSS_Q6_BIMC_AXI_CLK 160 + +/* Indexes for GDSCs */ +#define BIMC_GDSC 0 +#define VENUS_GDSC 1 +#define MDSS_GDSC 2 +#define JPEG_GDSC 3 +#define VFE_GDSC 4 +#define OXILI_GDSC 5 + +#endif diff --git a/include/dt-bindings/clock/qcom,gcc-msm8996.h b/include/dt-bindings/clock/qcom,gcc-msm8996.h new file mode 100644 index 00000000000..ddfd6fd7308 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-msm8996.h @@ -0,0 +1,362 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2015, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_MSM_GCC_8996_H +#define _DT_BINDINGS_CLK_MSM_GCC_8996_H + +#define GPLL0_EARLY 0 +#define GPLL0 1 +#define GPLL1_EARLY 2 +#define GPLL1 3 +#define GPLL2_EARLY 4 +#define GPLL2 5 +#define GPLL3_EARLY 6 +#define GPLL3 7 +#define GPLL4_EARLY 8 +#define GPLL4 9 +#define SYSTEM_NOC_CLK_SRC 10 +/* U-Boot: KConfig check in CI erroneously picks this up, it's unused + * anyway so comment it out for now + */ +//#define CONFIG _NOC_CLK_SRC 11 +#define PERIPH_NOC_CLK_SRC 12 +#define MMSS_BIMC_GFX_CLK_SRC 13 +#define USB30_MASTER_CLK_SRC 14 +#define USB30_MOCK_UTMI_CLK_SRC 15 +#define USB3_PHY_AUX_CLK_SRC 16 +#define USB20_MASTER_CLK_SRC 17 +#define USB20_MOCK_UTMI_CLK_SRC 18 +#define SDCC1_APPS_CLK_SRC 19 +#define SDCC1_ICE_CORE_CLK_SRC 20 +#define SDCC2_APPS_CLK_SRC 21 +#define SDCC3_APPS_CLK_SRC 22 +#define SDCC4_APPS_CLK_SRC 23 +#define BLSP1_QUP1_SPI_APPS_CLK_SRC 24 +#define BLSP1_QUP1_I2C_APPS_CLK_SRC 25 +#define BLSP1_UART1_APPS_CLK_SRC 26 +#define BLSP1_QUP2_SPI_APPS_CLK_SRC 27 +#define BLSP1_QUP2_I2C_APPS_CLK_SRC 28 +#define BLSP1_UART2_APPS_CLK_SRC 29 +#define BLSP1_QUP3_SPI_APPS_CLK_SRC 30 +#define BLSP1_QUP3_I2C_APPS_CLK_SRC 31 +#define BLSP1_UART3_APPS_CLK_SRC 32 +#define BLSP1_QUP4_SPI_APPS_CLK_SRC 33 +#define BLSP1_QUP4_I2C_APPS_CLK_SRC 34 +#define BLSP1_UART4_APPS_CLK_SRC 35 +#define BLSP1_QUP5_SPI_APPS_CLK_SRC 36 +#define BLSP1_QUP5_I2C_APPS_CLK_SRC 37 +#define BLSP1_UART5_APPS_CLK_SRC 38 +#define BLSP1_QUP6_SPI_APPS_CLK_SRC 39 +#define BLSP1_QUP6_I2C_APPS_CLK_SRC 40 +#define BLSP1_UART6_APPS_CLK_SRC 41 +#define BLSP2_QUP1_SPI_APPS_CLK_SRC 42 +#define BLSP2_QUP1_I2C_APPS_CLK_SRC 43 +#define BLSP2_UART1_APPS_CLK_SRC 44 +#define BLSP2_QUP2_SPI_APPS_CLK_SRC 45 +#define BLSP2_QUP2_I2C_APPS_CLK_SRC 46 +#define BLSP2_UART2_APPS_CLK_SRC 47 +#define BLSP2_QUP3_SPI_APPS_CLK_SRC 48 +#define BLSP2_QUP3_I2C_APPS_CLK_SRC 49 +#define BLSP2_UART3_APPS_CLK_SRC 50 +#define BLSP2_QUP4_SPI_APPS_CLK_SRC 51 +#define BLSP2_QUP4_I2C_APPS_CLK_SRC 52 +#define BLSP2_UART4_APPS_CLK_SRC 53 +#define BLSP2_QUP5_SPI_APPS_CLK_SRC 54 +#define BLSP2_QUP5_I2C_APPS_CLK_SRC 55 +#define BLSP2_UART5_APPS_CLK_SRC 56 +#define BLSP2_QUP6_SPI_APPS_CLK_SRC 57 +#define BLSP2_QUP6_I2C_APPS_CLK_SRC 58 +#define BLSP2_UART6_APPS_CLK_SRC 59 +#define PDM2_CLK_SRC 60 +#define TSIF_REF_CLK_SRC 61 +#define CE1_CLK_SRC 62 +#define GCC_SLEEP_CLK_SRC 63 +#define BIMC_CLK_SRC 64 +#define HMSS_AHB_CLK_SRC 65 +#define BIMC_HMSS_AXI_CLK_SRC 66 +#define HMSS_RBCPR_CLK_SRC 67 +#define HMSS_GPLL0_CLK_SRC 68 +#define GP1_CLK_SRC 69 +#define GP2_CLK_SRC 70 +#define GP3_CLK_SRC 71 +#define PCIE_AUX_CLK_SRC 72 +#define UFS_AXI_CLK_SRC 73 +#define UFS_ICE_CORE_CLK_SRC 74 +#define QSPI_SER_CLK_SRC 75 +#define GCC_SYS_NOC_AXI_CLK 76 +#define GCC_SYS_NOC_HMSS_AHB_CLK 77 +#define GCC_SNOC_CNOC_AHB_CLK 78 +#define GCC_SNOC_PNOC_AHB_CLK 79 +#define GCC_SYS_NOC_AT_CLK 80 +#define GCC_SYS_NOC_USB3_AXI_CLK 81 +#define GCC_SYS_NOC_UFS_AXI_CLK 82 +#define GCC_CFG_NOC_AHB_CLK 83 +#define GCC_PERIPH_NOC_AHB_CLK 84 +#define GCC_PERIPH_NOC_USB20_AHB_CLK 85 +#define GCC_TIC_CLK 86 +#define GCC_IMEM_AXI_CLK 87 +#define GCC_MMSS_SYS_NOC_AXI_CLK 88 +#define GCC_MMSS_NOC_CFG_AHB_CLK 89 +#define GCC_MMSS_BIMC_GFX_CLK 90 +#define GCC_USB30_MASTER_CLK 91 +#define GCC_USB30_SLEEP_CLK 92 +#define GCC_USB30_MOCK_UTMI_CLK 93 +#define GCC_USB3_PHY_AUX_CLK 94 +#define GCC_USB3_PHY_PIPE_CLK 95 +#define GCC_USB20_MASTER_CLK 96 +#define GCC_USB20_SLEEP_CLK 97 +#define GCC_USB20_MOCK_UTMI_CLK 98 +#define GCC_USB_PHY_CFG_AHB2PHY_CLK 99 +#define GCC_SDCC1_APPS_CLK 100 +#define GCC_SDCC1_AHB_CLK 101 +#define GCC_SDCC1_ICE_CORE_CLK 102 +#define GCC_SDCC2_APPS_CLK 103 +#define GCC_SDCC2_AHB_CLK 104 +#define GCC_SDCC3_APPS_CLK 105 +#define GCC_SDCC3_AHB_CLK 106 +#define GCC_SDCC4_APPS_CLK 107 +#define GCC_SDCC4_AHB_CLK 108 +#define GCC_BLSP1_AHB_CLK 109 +#define GCC_BLSP1_SLEEP_CLK 110 +#define GCC_BLSP1_QUP1_SPI_APPS_CLK 111 +#define GCC_BLSP1_QUP1_I2C_APPS_CLK 112 +#define GCC_BLSP1_UART1_APPS_CLK 113 +#define GCC_BLSP1_QUP2_SPI_APPS_CLK 114 +#define GCC_BLSP1_QUP2_I2C_APPS_CLK 115 +#define GCC_BLSP1_UART2_APPS_CLK 116 +#define GCC_BLSP1_QUP3_SPI_APPS_CLK 117 +#define GCC_BLSP1_QUP3_I2C_APPS_CLK 118 +#define GCC_BLSP1_UART3_APPS_CLK 119 +#define GCC_BLSP1_QUP4_SPI_APPS_CLK 120 +#define GCC_BLSP1_QUP4_I2C_APPS_CLK 121 +#define GCC_BLSP1_UART4_APPS_CLK 122 +#define GCC_BLSP1_QUP5_SPI_APPS_CLK 123 +#define GCC_BLSP1_QUP5_I2C_APPS_CLK 124 +#define GCC_BLSP1_UART5_APPS_CLK 125 +#define GCC_BLSP1_QUP6_SPI_APPS_CLK 126 +#define GCC_BLSP1_QUP6_I2C_APPS_CLK 127 +#define GCC_BLSP1_UART6_APPS_CLK 128 +#define GCC_BLSP2_AHB_CLK 129 +#define GCC_BLSP2_SLEEP_CLK 130 +#define GCC_BLSP2_QUP1_SPI_APPS_CLK 131 +#define GCC_BLSP2_QUP1_I2C_APPS_CLK 132 +#define GCC_BLSP2_UART1_APPS_CLK 133 +#define GCC_BLSP2_QUP2_SPI_APPS_CLK 134 +#define GCC_BLSP2_QUP2_I2C_APPS_CLK 135 +#define GCC_BLSP2_UART2_APPS_CLK 136 +#define GCC_BLSP2_QUP3_SPI_APPS_CLK 137 +#define GCC_BLSP2_QUP3_I2C_APPS_CLK 138 +#define GCC_BLSP2_UART3_APPS_CLK 139 +#define GCC_BLSP2_QUP4_SPI_APPS_CLK 140 +#define GCC_BLSP2_QUP4_I2C_APPS_CLK 141 +#define GCC_BLSP2_UART4_APPS_CLK 142 +#define GCC_BLSP2_QUP5_SPI_APPS_CLK 143 +#define GCC_BLSP2_QUP5_I2C_APPS_CLK 144 +#define GCC_BLSP2_UART5_APPS_CLK 145 +#define GCC_BLSP2_QUP6_SPI_APPS_CLK 146 +#define GCC_BLSP2_QUP6_I2C_APPS_CLK 147 +#define GCC_BLSP2_UART6_APPS_CLK 148 +#define GCC_PDM_AHB_CLK 149 +#define GCC_PDM_XO4_CLK 150 +#define GCC_PDM2_CLK 151 +#define GCC_PRNG_AHB_CLK 152 +#define GCC_TSIF_AHB_CLK 153 +#define GCC_TSIF_REF_CLK 154 +#define GCC_TSIF_INACTIVITY_TIMERS_CLK 155 +#define GCC_TCSR_AHB_CLK 156 +#define GCC_BOOT_ROM_AHB_CLK 157 +#define GCC_MSG_RAM_AHB_CLK 158 +#define GCC_TLMM_AHB_CLK 159 +#define GCC_TLMM_CLK 160 +#define GCC_MPM_AHB_CLK 161 +#define GCC_SPMI_SER_CLK 162 +#define GCC_SPMI_CNOC_AHB_CLK 163 +#define GCC_CE1_CLK 164 +#define GCC_CE1_AXI_CLK 165 +#define GCC_CE1_AHB_CLK 166 +#define GCC_BIMC_HMSS_AXI_CLK 167 +#define GCC_BIMC_GFX_CLK 168 +#define GCC_HMSS_AHB_CLK 169 +#define GCC_HMSS_SLV_AXI_CLK 170 +#define GCC_HMSS_MSTR_AXI_CLK 171 +#define GCC_HMSS_RBCPR_CLK 172 +#define GCC_GP1_CLK 173 +#define GCC_GP2_CLK 174 +#define GCC_GP3_CLK 175 +#define GCC_PCIE_0_SLV_AXI_CLK 176 +#define GCC_PCIE_0_MSTR_AXI_CLK 177 +#define GCC_PCIE_0_CFG_AHB_CLK 178 +#define GCC_PCIE_0_AUX_CLK 179 +#define GCC_PCIE_0_PIPE_CLK 180 +#define GCC_PCIE_1_SLV_AXI_CLK 181 +#define GCC_PCIE_1_MSTR_AXI_CLK 182 +#define GCC_PCIE_1_CFG_AHB_CLK 183 +#define GCC_PCIE_1_AUX_CLK 184 +#define GCC_PCIE_1_PIPE_CLK 185 +#define GCC_PCIE_2_SLV_AXI_CLK 186 +#define GCC_PCIE_2_MSTR_AXI_CLK 187 +#define GCC_PCIE_2_CFG_AHB_CLK 188 +#define GCC_PCIE_2_AUX_CLK 189 +#define GCC_PCIE_2_PIPE_CLK 190 +#define GCC_PCIE_PHY_CFG_AHB_CLK 191 +#define GCC_PCIE_PHY_AUX_CLK 192 +#define GCC_UFS_AXI_CLK 193 +#define GCC_UFS_AHB_CLK 194 +#define GCC_UFS_TX_CFG_CLK 195 +#define GCC_UFS_RX_CFG_CLK 196 +#define GCC_UFS_TX_SYMBOL_0_CLK 197 +#define GCC_UFS_RX_SYMBOL_0_CLK 198 +#define GCC_UFS_RX_SYMBOL_1_CLK 199 +#define GCC_UFS_UNIPRO_CORE_CLK 200 +#define GCC_UFS_ICE_CORE_CLK 201 +#define GCC_UFS_SYS_CLK_CORE_CLK 202 +#define GCC_UFS_TX_SYMBOL_CLK_CORE_CLK 203 +#define GCC_AGGRE0_SNOC_AXI_CLK 204 +#define GCC_AGGRE0_CNOC_AHB_CLK 205 +#define GCC_SMMU_AGGRE0_AXI_CLK 206 +#define GCC_SMMU_AGGRE0_AHB_CLK 207 +#define GCC_AGGRE1_PNOC_AHB_CLK 208 +#define GCC_AGGRE2_UFS_AXI_CLK 209 +#define GCC_AGGRE2_USB3_AXI_CLK 210 +#define GCC_QSPI_AHB_CLK 211 +#define GCC_QSPI_SER_CLK 212 +#define GCC_USB3_CLKREF_CLK 213 +#define GCC_HDMI_CLKREF_CLK 214 +#define GCC_UFS_CLKREF_CLK 215 +#define GCC_PCIE_CLKREF_CLK 216 +#define GCC_RX2_USB2_CLKREF_CLK 217 +#define GCC_RX1_USB2_CLKREF_CLK 218 +#define GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK 219 +#define GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK 220 +#define GCC_EDP_CLKREF_CLK 221 +#define GCC_MSS_CFG_AHB_CLK 222 +#define GCC_MSS_Q6_BIMC_AXI_CLK 223 +#define GCC_MSS_SNOC_AXI_CLK 224 +#define GCC_MSS_MNOC_BIMC_AXI_CLK 225 +#define GCC_DCC_AHB_CLK 226 +#define GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK 227 +#define GCC_MMSS_GPLL0_DIV_CLK 228 +#define GCC_MSS_GPLL0_DIV_CLK 229 + +#define GCC_SYSTEM_NOC_BCR 0 +#define GCC_CONFIG_NOC_BCR 1 +#define GCC_PERIPH_NOC_BCR 2 +#define GCC_IMEM_BCR 3 +#define GCC_MMSS_BCR 4 +#define GCC_PIMEM_BCR 5 +#define GCC_QDSS_BCR 6 +#define GCC_USB_30_BCR 7 +#define GCC_USB_20_BCR 8 +#define GCC_QUSB2PHY_PRIM_BCR 9 +#define GCC_QUSB2PHY_SEC_BCR 10 +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 11 +#define GCC_SDCC1_BCR 12 +#define GCC_SDCC2_BCR 13 +#define GCC_SDCC3_BCR 14 +#define GCC_SDCC4_BCR 15 +#define GCC_BLSP1_BCR 16 +#define GCC_BLSP1_QUP1_BCR 17 +#define GCC_BLSP1_UART1_BCR 18 +#define GCC_BLSP1_QUP2_BCR 19 +#define GCC_BLSP1_UART2_BCR 20 +#define GCC_BLSP1_QUP3_BCR 21 +#define GCC_BLSP1_UART3_BCR 22 +#define GCC_BLSP1_QUP4_BCR 23 +#define GCC_BLSP1_UART4_BCR 24 +#define GCC_BLSP1_QUP5_BCR 25 +#define GCC_BLSP1_UART5_BCR 26 +#define GCC_BLSP1_QUP6_BCR 27 +#define GCC_BLSP1_UART6_BCR 28 +#define GCC_BLSP2_BCR 29 +#define GCC_BLSP2_QUP1_BCR 30 +#define GCC_BLSP2_UART1_BCR 31 +#define GCC_BLSP2_QUP2_BCR 32 +#define GCC_BLSP2_UART2_BCR 33 +#define GCC_BLSP2_QUP3_BCR 34 +#define GCC_BLSP2_UART3_BCR 35 +#define GCC_BLSP2_QUP4_BCR 36 +#define GCC_BLSP2_UART4_BCR 37 +#define GCC_BLSP2_QUP5_BCR 38 +#define GCC_BLSP2_UART5_BCR 39 +#define GCC_BLSP2_QUP6_BCR 40 +#define GCC_BLSP2_UART6_BCR 41 +#define GCC_PDM_BCR 42 +#define GCC_PRNG_BCR 43 +#define GCC_TSIF_BCR 44 +#define GCC_TCSR_BCR 45 +#define GCC_BOOT_ROM_BCR 46 +#define GCC_MSG_RAM_BCR 47 +#define GCC_TLMM_BCR 48 +#define GCC_MPM_BCR 49 +#define GCC_SEC_CTRL_BCR 50 +#define GCC_SPMI_BCR 51 +#define GCC_SPDM_BCR 52 +#define GCC_CE1_BCR 53 +#define GCC_BIMC_BCR 54 +#define GCC_SNOC_BUS_TIMEOUT0_BCR 55 +#define GCC_SNOC_BUS_TIMEOUT2_BCR 56 +#define GCC_SNOC_BUS_TIMEOUT1_BCR 57 +#define GCC_SNOC_BUS_TIMEOUT3_BCR 58 +#define GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR 59 +#define GCC_PNOC_BUS_TIMEOUT0_BCR 60 +#define GCC_PNOC_BUS_TIMEOUT1_BCR 61 +#define GCC_PNOC_BUS_TIMEOUT2_BCR 62 +#define GCC_PNOC_BUS_TIMEOUT3_BCR 63 +#define GCC_PNOC_BUS_TIMEOUT4_BCR 64 +#define GCC_CNOC_BUS_TIMEOUT0_BCR 65 +#define GCC_CNOC_BUS_TIMEOUT1_BCR 66 +#define GCC_CNOC_BUS_TIMEOUT2_BCR 67 +#define GCC_CNOC_BUS_TIMEOUT3_BCR 68 +#define GCC_CNOC_BUS_TIMEOUT4_BCR 69 +#define GCC_CNOC_BUS_TIMEOUT5_BCR 70 +#define GCC_CNOC_BUS_TIMEOUT6_BCR 71 +#define GCC_CNOC_BUS_TIMEOUT7_BCR 72 +#define GCC_CNOC_BUS_TIMEOUT8_BCR 73 +#define GCC_CNOC_BUS_TIMEOUT9_BCR 74 +#define GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR 75 +#define GCC_APB2JTAG_BCR 76 +#define GCC_RBCPR_CX_BCR 77 +#define GCC_RBCPR_MX_BCR 78 +#define GCC_PCIE_0_BCR 79 +#define GCC_PCIE_0_PHY_BCR 80 +#define GCC_PCIE_1_BCR 81 +#define GCC_PCIE_1_PHY_BCR 82 +#define GCC_PCIE_2_BCR 83 +#define GCC_PCIE_2_PHY_BCR 84 +#define GCC_PCIE_PHY_BCR 85 +#define GCC_DCD_BCR 86 +#define GCC_OBT_ODT_BCR 87 +#define GCC_UFS_BCR 88 +#define GCC_SSC_BCR 89 +#define GCC_VS_BCR 90 +#define GCC_AGGRE0_NOC_BCR 91 +#define GCC_AGGRE1_NOC_BCR 92 +#define GCC_AGGRE2_NOC_BCR 93 +#define GCC_DCC_BCR 94 +#define GCC_IPA_BCR 95 +#define GCC_QSPI_BCR 96 +#define GCC_SKL_BCR 97 +#define GCC_MSMPU_BCR 98 +#define GCC_MSS_Q6_BCR 99 +#define GCC_QREFS_VBG_CAL_BCR 100 +#define GCC_PCIE_PHY_COM_BCR 101 +#define GCC_PCIE_PHY_COM_NOCSR_BCR 102 +#define GCC_USB3_PHY_BCR 103 +#define GCC_USB3PHY_PHY_BCR 104 +#define GCC_MSS_RESTART 105 + + +/* Indexes for GDSCs */ +#define AGGRE0_NOC_GDSC 0 +#define HLOS1_VOTE_AGGRE0_NOC_GDSC 1 +#define HLOS1_VOTE_LPASS_ADSP_GDSC 2 +#define HLOS1_VOTE_LPASS_CORE_GDSC 3 +#define USB30_GDSC 4 +#define PCIE0_GDSC 5 +#define PCIE1_GDSC 6 +#define PCIE2_GDSC 7 +#define UFS_GDSC 8 + +#endif diff --git a/include/dt-bindings/clock/qcom,gpucc-sdm845.h b/include/dt-bindings/clock/qcom,gpucc-sdm845.h new file mode 100644 index 00000000000..9690d901b50 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gpucc-sdm845.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_SDM_GPU_CC_SDM845_H +#define _DT_BINDINGS_CLK_SDM_GPU_CC_SDM845_H + +/* GPU_CC clock registers */ +#define GPU_CC_CX_GMU_CLK 0 +#define GPU_CC_CXO_CLK 1 +#define GPU_CC_GMU_CLK_SRC 2 +#define GPU_CC_PLL1 3 + +/* GPU_CC Resets */ +#define GPUCC_GPU_CC_CX_BCR 0 +#define GPUCC_GPU_CC_GMU_BCR 1 +#define GPUCC_GPU_CC_XO_BCR 2 + +/* GPU_CC GDSCRs */ +#define GPU_CX_GDSC 0 +#define GPU_GX_GDSC 1 + +#endif diff --git a/include/dt-bindings/clock/qcom,lpass-sdm845.h b/include/dt-bindings/clock/qcom,lpass-sdm845.h new file mode 100644 index 00000000000..659050846f6 --- /dev/null +++ b/include/dt-bindings/clock/qcom,lpass-sdm845.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_SDM_LPASS_SDM845_H +#define _DT_BINDINGS_CLK_SDM_LPASS_SDM845_H + +#define LPASS_Q6SS_AHBM_AON_CLK 0 +#define LPASS_Q6SS_AHBS_AON_CLK 1 +#define LPASS_QDSP6SS_XO_CLK 2 +#define LPASS_QDSP6SS_SLEEP_CLK 3 +#define LPASS_QDSP6SS_CORE_CLK 4 + +#endif diff --git a/include/dt-bindings/clock/qcom,mmcc-msm8996.h b/include/dt-bindings/clock/qcom,mmcc-msm8996.h new file mode 100644 index 00000000000..d51f9ac7056 --- /dev/null +++ b/include/dt-bindings/clock/qcom,mmcc-msm8996.h @@ -0,0 +1,295 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2015, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_MSM_MMCC_8996_H +#define _DT_BINDINGS_CLK_MSM_MMCC_8996_H + +#define MMPLL0_EARLY 0 +#define MMPLL0_PLL 1 +#define MMPLL1_EARLY 2 +#define MMPLL1_PLL 3 +#define MMPLL2_EARLY 4 +#define MMPLL2_PLL 5 +#define MMPLL3_EARLY 6 +#define MMPLL3_PLL 7 +#define MMPLL4_EARLY 8 +#define MMPLL4_PLL 9 +#define MMPLL5_EARLY 10 +#define MMPLL5_PLL 11 +#define MMPLL8_EARLY 12 +#define MMPLL8_PLL 13 +#define MMPLL9_EARLY 14 +#define MMPLL9_PLL 15 +#define AHB_CLK_SRC 16 +#define AXI_CLK_SRC 17 +#define MAXI_CLK_SRC 18 +#define DSA_CORE_CLK_SRC 19 +#define GFX3D_CLK_SRC 20 +#define RBBMTIMER_CLK_SRC 21 +#define ISENSE_CLK_SRC 22 +#define RBCPR_CLK_SRC 23 +#define VIDEO_CORE_CLK_SRC 24 +#define VIDEO_SUBCORE0_CLK_SRC 25 +#define VIDEO_SUBCORE1_CLK_SRC 26 +#define PCLK0_CLK_SRC 27 +#define PCLK1_CLK_SRC 28 +#define MDP_CLK_SRC 29 +#define EXTPCLK_CLK_SRC 30 +#define VSYNC_CLK_SRC 31 +#define HDMI_CLK_SRC 32 +#define BYTE0_CLK_SRC 33 +#define BYTE1_CLK_SRC 34 +#define ESC0_CLK_SRC 35 +#define ESC1_CLK_SRC 36 +#define CAMSS_GP0_CLK_SRC 37 +#define CAMSS_GP1_CLK_SRC 38 +#define MCLK0_CLK_SRC 39 +#define MCLK1_CLK_SRC 40 +#define MCLK2_CLK_SRC 41 +#define MCLK3_CLK_SRC 42 +#define CCI_CLK_SRC 43 +#define CSI0PHYTIMER_CLK_SRC 44 +#define CSI1PHYTIMER_CLK_SRC 45 +#define CSI2PHYTIMER_CLK_SRC 46 +#define CSIPHY0_3P_CLK_SRC 47 +#define CSIPHY1_3P_CLK_SRC 48 +#define CSIPHY2_3P_CLK_SRC 49 +#define JPEG0_CLK_SRC 50 +#define JPEG2_CLK_SRC 51 +#define JPEG_DMA_CLK_SRC 52 +#define VFE0_CLK_SRC 53 +#define VFE1_CLK_SRC 54 +#define CPP_CLK_SRC 55 +#define CSI0_CLK_SRC 56 +#define CSI1_CLK_SRC 57 +#define CSI2_CLK_SRC 58 +#define CSI3_CLK_SRC 59 +#define FD_CORE_CLK_SRC 60 +#define MMSS_CXO_CLK 61 +#define MMSS_SLEEPCLK_CLK 62 +#define MMSS_MMAGIC_AHB_CLK 63 +#define MMSS_MMAGIC_CFG_AHB_CLK 64 +#define MMSS_MISC_AHB_CLK 65 +#define MMSS_MISC_CXO_CLK 66 +#define MMSS_BTO_AHB_CLK 67 +#define MMSS_MMAGIC_AXI_CLK 68 +#define MMSS_S0_AXI_CLK 69 +#define MMSS_MMAGIC_MAXI_CLK 70 +#define DSA_CORE_CLK 71 +#define DSA_NOC_CFG_AHB_CLK 72 +#define MMAGIC_CAMSS_AXI_CLK 73 +#define MMAGIC_CAMSS_NOC_CFG_AHB_CLK 74 +#define THROTTLE_CAMSS_CXO_CLK 75 +#define THROTTLE_CAMSS_AHB_CLK 76 +#define THROTTLE_CAMSS_AXI_CLK 77 +#define SMMU_VFE_AHB_CLK 78 +#define SMMU_VFE_AXI_CLK 79 +#define SMMU_CPP_AHB_CLK 80 +#define SMMU_CPP_AXI_CLK 81 +#define SMMU_JPEG_AHB_CLK 82 +#define SMMU_JPEG_AXI_CLK 83 +#define MMAGIC_MDSS_AXI_CLK 84 +#define MMAGIC_MDSS_NOC_CFG_AHB_CLK 85 +#define THROTTLE_MDSS_CXO_CLK 86 +#define THROTTLE_MDSS_AHB_CLK 87 +#define THROTTLE_MDSS_AXI_CLK 88 +#define SMMU_ROT_AHB_CLK 89 +#define SMMU_ROT_AXI_CLK 90 +#define SMMU_MDP_AHB_CLK 91 +#define SMMU_MDP_AXI_CLK 92 +#define MMAGIC_VIDEO_AXI_CLK 93 +#define MMAGIC_VIDEO_NOC_CFG_AHB_CLK 94 +#define THROTTLE_VIDEO_CXO_CLK 95 +#define THROTTLE_VIDEO_AHB_CLK 96 +#define THROTTLE_VIDEO_AXI_CLK 97 +#define SMMU_VIDEO_AHB_CLK 98 +#define SMMU_VIDEO_AXI_CLK 99 +#define MMAGIC_BIMC_AXI_CLK 100 +#define MMAGIC_BIMC_NOC_CFG_AHB_CLK 101 +#define GPU_GX_GFX3D_CLK 102 +#define GPU_GX_RBBMTIMER_CLK 103 +#define GPU_AHB_CLK 104 +#define GPU_AON_ISENSE_CLK 105 +#define VMEM_MAXI_CLK 106 +#define VMEM_AHB_CLK 107 +#define MMSS_RBCPR_CLK 108 +#define MMSS_RBCPR_AHB_CLK 109 +#define VIDEO_CORE_CLK 110 +#define VIDEO_AXI_CLK 111 +#define VIDEO_MAXI_CLK 112 +#define VIDEO_AHB_CLK 113 +#define VIDEO_SUBCORE0_CLK 114 +#define VIDEO_SUBCORE1_CLK 115 +#define MDSS_AHB_CLK 116 +#define MDSS_HDMI_AHB_CLK 117 +#define MDSS_AXI_CLK 118 +#define MDSS_PCLK0_CLK 119 +#define MDSS_PCLK1_CLK 120 +#define MDSS_MDP_CLK 121 +#define MDSS_EXTPCLK_CLK 122 +#define MDSS_VSYNC_CLK 123 +#define MDSS_HDMI_CLK 124 +#define MDSS_BYTE0_CLK 125 +#define MDSS_BYTE1_CLK 126 +#define MDSS_ESC0_CLK 127 +#define MDSS_ESC1_CLK 128 +#define CAMSS_TOP_AHB_CLK 129 +#define CAMSS_AHB_CLK 130 +#define CAMSS_MICRO_AHB_CLK 131 +#define CAMSS_GP0_CLK 132 +#define CAMSS_GP1_CLK 133 +#define CAMSS_MCLK0_CLK 134 +#define CAMSS_MCLK1_CLK 135 +#define CAMSS_MCLK2_CLK 136 +#define CAMSS_MCLK3_CLK 137 +#define CAMSS_CCI_CLK 138 +#define CAMSS_CCI_AHB_CLK 139 +#define CAMSS_CSI0PHYTIMER_CLK 140 +#define CAMSS_CSI1PHYTIMER_CLK 141 +#define CAMSS_CSI2PHYTIMER_CLK 142 +#define CAMSS_CSIPHY0_3P_CLK 143 +#define CAMSS_CSIPHY1_3P_CLK 144 +#define CAMSS_CSIPHY2_3P_CLK 145 +#define CAMSS_JPEG0_CLK 146 +#define CAMSS_JPEG2_CLK 147 +#define CAMSS_JPEG_DMA_CLK 148 +#define CAMSS_JPEG_AHB_CLK 149 +#define CAMSS_JPEG_AXI_CLK 150 +#define CAMSS_VFE_AHB_CLK 151 +#define CAMSS_VFE_AXI_CLK 152 +#define CAMSS_VFE0_CLK 153 +#define CAMSS_VFE0_STREAM_CLK 154 +#define CAMSS_VFE0_AHB_CLK 155 +#define CAMSS_VFE1_CLK 156 +#define CAMSS_VFE1_STREAM_CLK 157 +#define CAMSS_VFE1_AHB_CLK 158 +#define CAMSS_CSI_VFE0_CLK 159 +#define CAMSS_CSI_VFE1_CLK 160 +#define CAMSS_CPP_VBIF_AHB_CLK 161 +#define CAMSS_CPP_AXI_CLK 162 +#define CAMSS_CPP_CLK 163 +#define CAMSS_CPP_AHB_CLK 164 +#define CAMSS_CSI0_CLK 165 +#define CAMSS_CSI0_AHB_CLK 166 +#define CAMSS_CSI0PHY_CLK 167 +#define CAMSS_CSI0RDI_CLK 168 +#define CAMSS_CSI0PIX_CLK 169 +#define CAMSS_CSI1_CLK 170 +#define CAMSS_CSI1_AHB_CLK 171 +#define CAMSS_CSI1PHY_CLK 172 +#define CAMSS_CSI1RDI_CLK 173 +#define CAMSS_CSI1PIX_CLK 174 +#define CAMSS_CSI2_CLK 175 +#define CAMSS_CSI2_AHB_CLK 176 +#define CAMSS_CSI2PHY_CLK 177 +#define CAMSS_CSI2RDI_CLK 178 +#define CAMSS_CSI2PIX_CLK 179 +#define CAMSS_CSI3_CLK 180 +#define CAMSS_CSI3_AHB_CLK 181 +#define CAMSS_CSI3PHY_CLK 182 +#define CAMSS_CSI3RDI_CLK 183 +#define CAMSS_CSI3PIX_CLK 184 +#define CAMSS_ISPIF_AHB_CLK 185 +#define FD_CORE_CLK 186 +#define FD_CORE_UAR_CLK 187 +#define FD_AHB_CLK 188 +#define MMSS_SPDM_CSI0_CLK 189 +#define MMSS_SPDM_JPEG_DMA_CLK 190 +#define MMSS_SPDM_CPP_CLK 191 +#define MMSS_SPDM_PCLK0_CLK 192 +#define MMSS_SPDM_AHB_CLK 193 +#define MMSS_SPDM_GFX3D_CLK 194 +#define MMSS_SPDM_PCLK1_CLK 195 +#define MMSS_SPDM_JPEG2_CLK 196 +#define MMSS_SPDM_DEBUG_CLK 197 +#define MMSS_SPDM_VFE1_CLK 198 +#define MMSS_SPDM_VFE0_CLK 199 +#define MMSS_SPDM_VIDEO_CORE_CLK 200 +#define MMSS_SPDM_AXI_CLK 201 +#define MMSS_SPDM_MDP_CLK 202 +#define MMSS_SPDM_JPEG0_CLK 203 +#define MMSS_SPDM_RM_AXI_CLK 204 +#define MMSS_SPDM_RM_MAXI_CLK 205 + +#define MMAGICAHB_BCR 0 +#define MMAGIC_CFG_BCR 1 +#define MISC_BCR 2 +#define BTO_BCR 3 +#define MMAGICAXI_BCR 4 +#define MMAGICMAXI_BCR 5 +#define DSA_BCR 6 +#define MMAGIC_CAMSS_BCR 7 +#define THROTTLE_CAMSS_BCR 8 +#define SMMU_VFE_BCR 9 +#define SMMU_CPP_BCR 10 +#define SMMU_JPEG_BCR 11 +#define MMAGIC_MDSS_BCR 12 +#define THROTTLE_MDSS_BCR 13 +#define SMMU_ROT_BCR 14 +#define SMMU_MDP_BCR 15 +#define MMAGIC_VIDEO_BCR 16 +#define THROTTLE_VIDEO_BCR 17 +#define SMMU_VIDEO_BCR 18 +#define MMAGIC_BIMC_BCR 19 +#define GPU_GX_BCR 20 +#define GPU_BCR 21 +#define GPU_AON_BCR 22 +#define VMEM_BCR 23 +#define MMSS_RBCPR_BCR 24 +#define VIDEO_BCR 25 +#define MDSS_BCR 26 +#define CAMSS_TOP_BCR 27 +#define CAMSS_AHB_BCR 28 +#define CAMSS_MICRO_BCR 29 +#define CAMSS_CCI_BCR 30 +#define CAMSS_PHY0_BCR 31 +#define CAMSS_PHY1_BCR 32 +#define CAMSS_PHY2_BCR 33 +#define CAMSS_CSIPHY0_3P_BCR 34 +#define CAMSS_CSIPHY1_3P_BCR 35 +#define CAMSS_CSIPHY2_3P_BCR 36 +#define CAMSS_JPEG_BCR 37 +#define CAMSS_VFE_BCR 38 +#define CAMSS_VFE0_BCR 39 +#define CAMSS_VFE1_BCR 40 +#define CAMSS_CSI_VFE0_BCR 41 +#define CAMSS_CSI_VFE1_BCR 42 +#define CAMSS_CPP_TOP_BCR 43 +#define CAMSS_CPP_BCR 44 +#define CAMSS_CSI0_BCR 45 +#define CAMSS_CSI0RDI_BCR 46 +#define CAMSS_CSI0PIX_BCR 47 +#define CAMSS_CSI1_BCR 48 +#define CAMSS_CSI1RDI_BCR 49 +#define CAMSS_CSI1PIX_BCR 50 +#define CAMSS_CSI2_BCR 51 +#define CAMSS_CSI2RDI_BCR 52 +#define CAMSS_CSI2PIX_BCR 53 +#define CAMSS_CSI3_BCR 54 +#define CAMSS_CSI3RDI_BCR 55 +#define CAMSS_CSI3PIX_BCR 56 +#define CAMSS_ISPIF_BCR 57 +#define FD_BCR 58 +#define MMSS_SPDM_RM_BCR 59 + +/* Indexes for GDSCs */ +#define MMAGIC_VIDEO_GDSC 0 +#define MMAGIC_MDSS_GDSC 1 +#define MMAGIC_CAMSS_GDSC 2 +#define GPU_GDSC 3 +#define VENUS_GDSC 4 +#define VENUS_CORE0_GDSC 5 +#define VENUS_CORE1_GDSC 6 +#define CAMSS_GDSC 7 +#define VFE0_GDSC 8 +#define VFE1_GDSC 9 +#define JPEG_GDSC 10 +#define CPP_GDSC 11 +#define FD_GDSC 12 +#define MDSS_GDSC 13 +#define GPU_GX_GDSC 14 +#define MMAGIC_BIMC_GDSC 15 + +#endif diff --git a/include/dt-bindings/clock/qcom,rpmcc.h b/include/dt-bindings/clock/qcom,rpmcc.h new file mode 100644 index 00000000000..46309c9953b --- /dev/null +++ b/include/dt-bindings/clock/qcom,rpmcc.h @@ -0,0 +1,174 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright 2015 Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_MSM_RPMCC_H +#define _DT_BINDINGS_CLK_MSM_RPMCC_H + +/* RPM clocks */ +#define RPM_PXO_CLK 0 +#define RPM_PXO_A_CLK 1 +#define RPM_CXO_CLK 2 +#define RPM_CXO_A_CLK 3 +#define RPM_APPS_FABRIC_CLK 4 +#define RPM_APPS_FABRIC_A_CLK 5 +#define RPM_CFPB_CLK 6 +#define RPM_CFPB_A_CLK 7 +#define RPM_QDSS_CLK 8 +#define RPM_QDSS_A_CLK 9 +#define RPM_DAYTONA_FABRIC_CLK 10 +#define RPM_DAYTONA_FABRIC_A_CLK 11 +#define RPM_EBI1_CLK 12 +#define RPM_EBI1_A_CLK 13 +#define RPM_MM_FABRIC_CLK 14 +#define RPM_MM_FABRIC_A_CLK 15 +#define RPM_MMFPB_CLK 16 +#define RPM_MMFPB_A_CLK 17 +#define RPM_SYS_FABRIC_CLK 18 +#define RPM_SYS_FABRIC_A_CLK 19 +#define RPM_SFPB_CLK 20 +#define RPM_SFPB_A_CLK 21 +#define RPM_SMI_CLK 22 +#define RPM_SMI_A_CLK 23 +#define RPM_PLL4_CLK 24 +#define RPM_XO_D0 25 +#define RPM_XO_D1 26 +#define RPM_XO_A0 27 +#define RPM_XO_A1 28 +#define RPM_XO_A2 29 +#define RPM_NSS_FABRIC_0_CLK 30 +#define RPM_NSS_FABRIC_0_A_CLK 31 +#define RPM_NSS_FABRIC_1_CLK 32 +#define RPM_NSS_FABRIC_1_A_CLK 33 + +/* SMD RPM clocks */ +#define RPM_SMD_XO_CLK_SRC 0 +#define RPM_SMD_XO_A_CLK_SRC 1 +#define RPM_SMD_PCNOC_CLK 2 +#define RPM_SMD_PCNOC_A_CLK 3 +#define RPM_SMD_SNOC_CLK 4 +#define RPM_SMD_SNOC_A_CLK 5 +#define RPM_SMD_BIMC_CLK 6 +#define RPM_SMD_BIMC_A_CLK 7 +#define RPM_SMD_QDSS_CLK 8 +#define RPM_SMD_QDSS_A_CLK 9 +#define RPM_SMD_BB_CLK1 10 +#define RPM_SMD_BB_CLK1_A 11 +#define RPM_SMD_BB_CLK2 12 +#define RPM_SMD_BB_CLK2_A 13 +#define RPM_SMD_RF_CLK1 14 +#define RPM_SMD_RF_CLK1_A 15 +#define RPM_SMD_RF_CLK2 16 +#define RPM_SMD_RF_CLK2_A 17 +#define RPM_SMD_BB_CLK1_PIN 18 +#define RPM_SMD_BB_CLK1_A_PIN 19 +#define RPM_SMD_BB_CLK2_PIN 20 +#define RPM_SMD_BB_CLK2_A_PIN 21 +#define RPM_SMD_RF_CLK1_PIN 22 +#define RPM_SMD_RF_CLK1_A_PIN 23 +#define RPM_SMD_RF_CLK2_PIN 24 +#define RPM_SMD_RF_CLK2_A_PIN 25 +#define RPM_SMD_PNOC_CLK 26 +#define RPM_SMD_PNOC_A_CLK 27 +#define RPM_SMD_CNOC_CLK 28 +#define RPM_SMD_CNOC_A_CLK 29 +#define RPM_SMD_MMSSNOC_AHB_CLK 30 +#define RPM_SMD_MMSSNOC_AHB_A_CLK 31 +#define RPM_SMD_GFX3D_CLK_SRC 32 +#define RPM_SMD_GFX3D_A_CLK_SRC 33 +#define RPM_SMD_OCMEMGX_CLK 34 +#define RPM_SMD_OCMEMGX_A_CLK 35 +#define RPM_SMD_CXO_D0 36 +#define RPM_SMD_CXO_D0_A 37 +#define RPM_SMD_CXO_D1 38 +#define RPM_SMD_CXO_D1_A 39 +#define RPM_SMD_CXO_A0 40 +#define RPM_SMD_CXO_A0_A 41 +#define RPM_SMD_CXO_A1 42 +#define RPM_SMD_CXO_A1_A 43 +#define RPM_SMD_CXO_A2 44 +#define RPM_SMD_CXO_A2_A 45 +#define RPM_SMD_DIV_CLK1 46 +#define RPM_SMD_DIV_A_CLK1 47 +#define RPM_SMD_DIV_CLK2 48 +#define RPM_SMD_DIV_A_CLK2 49 +#define RPM_SMD_DIFF_CLK 50 +#define RPM_SMD_DIFF_A_CLK 51 +#define RPM_SMD_CXO_D0_PIN 52 +#define RPM_SMD_CXO_D0_A_PIN 53 +#define RPM_SMD_CXO_D1_PIN 54 +#define RPM_SMD_CXO_D1_A_PIN 55 +#define RPM_SMD_CXO_A0_PIN 56 +#define RPM_SMD_CXO_A0_A_PIN 57 +#define RPM_SMD_CXO_A1_PIN 58 +#define RPM_SMD_CXO_A1_A_PIN 59 +#define RPM_SMD_CXO_A2_PIN 60 +#define RPM_SMD_CXO_A2_A_PIN 61 +#define RPM_SMD_AGGR1_NOC_CLK 62 +#define RPM_SMD_AGGR1_NOC_A_CLK 63 +#define RPM_SMD_AGGR2_NOC_CLK 64 +#define RPM_SMD_AGGR2_NOC_A_CLK 65 +#define RPM_SMD_MMAXI_CLK 66 +#define RPM_SMD_MMAXI_A_CLK 67 +#define RPM_SMD_IPA_CLK 68 +#define RPM_SMD_IPA_A_CLK 69 +#define RPM_SMD_CE1_CLK 70 +#define RPM_SMD_CE1_A_CLK 71 +#define RPM_SMD_DIV_CLK3 72 +#define RPM_SMD_DIV_A_CLK3 73 +#define RPM_SMD_LN_BB_CLK 74 +#define RPM_SMD_LN_BB_A_CLK 75 +#define RPM_SMD_BIMC_GPU_CLK 76 +#define RPM_SMD_BIMC_GPU_A_CLK 77 +#define RPM_SMD_QPIC_CLK 78 +#define RPM_SMD_QPIC_CLK_A 79 +#define RPM_SMD_LN_BB_CLK1 80 +#define RPM_SMD_LN_BB_CLK1_A 81 +#define RPM_SMD_LN_BB_CLK2 82 +#define RPM_SMD_LN_BB_CLK2_A 83 +#define RPM_SMD_LN_BB_CLK3_PIN 84 +#define RPM_SMD_LN_BB_CLK3_A_PIN 85 +#define RPM_SMD_RF_CLK3 86 +#define RPM_SMD_RF_CLK3_A 87 +#define RPM_SMD_RF_CLK3_PIN 88 +#define RPM_SMD_RF_CLK3_A_PIN 89 +#define RPM_SMD_MMSSNOC_AXI_CLK 90 +#define RPM_SMD_MMSSNOC_AXI_CLK_A 91 +#define RPM_SMD_CNOC_PERIPH_CLK 92 +#define RPM_SMD_CNOC_PERIPH_A_CLK 93 +#define RPM_SMD_LN_BB_CLK3 94 +#define RPM_SMD_LN_BB_CLK3_A 95 +#define RPM_SMD_LN_BB_CLK1_PIN 96 +#define RPM_SMD_LN_BB_CLK1_A_PIN 97 +#define RPM_SMD_LN_BB_CLK2_PIN 98 +#define RPM_SMD_LN_BB_CLK2_A_PIN 99 +#define RPM_SMD_SYSMMNOC_CLK 100 +#define RPM_SMD_SYSMMNOC_A_CLK 101 +#define RPM_SMD_CE2_CLK 102 +#define RPM_SMD_CE2_A_CLK 103 +#define RPM_SMD_CE3_CLK 104 +#define RPM_SMD_CE3_A_CLK 105 +#define RPM_SMD_QUP_CLK 106 +#define RPM_SMD_QUP_A_CLK 107 +#define RPM_SMD_MMRT_CLK 108 +#define RPM_SMD_MMRT_A_CLK 109 +#define RPM_SMD_MMNRT_CLK 110 +#define RPM_SMD_MMNRT_A_CLK 111 +#define RPM_SMD_SNOC_PERIPH_CLK 112 +#define RPM_SMD_SNOC_PERIPH_A_CLK 113 +#define RPM_SMD_SNOC_LPASS_CLK 114 +#define RPM_SMD_SNOC_LPASS_A_CLK 115 +#define RPM_SMD_HWKM_CLK 116 +#define RPM_SMD_HWKM_A_CLK 117 +#define RPM_SMD_PKA_CLK 118 +#define RPM_SMD_PKA_A_CLK 119 +#define RPM_SMD_CPUSS_GNOC_CLK 120 +#define RPM_SMD_CPUSS_GNOC_A_CLK 121 +#define RPM_SMD_MSS_CFG_AHB_CLK 122 +#define RPM_SMD_MSS_CFG_AHB_A_CLK 123 +#define RPM_SMD_BIMC_FREQ_LOG 124 +#define RPM_SMD_LN_BB_CLK_PIN 125 +#define RPM_SMD_LN_BB_A_CLK_PIN 126 + +#endif diff --git a/include/dt-bindings/clock/qcom,rpmh.h b/include/dt-bindings/clock/qcom,rpmh.h new file mode 100644 index 00000000000..0a7d1be0d12 --- /dev/null +++ b/include/dt-bindings/clock/qcom,rpmh.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved. */ + + +#ifndef _DT_BINDINGS_CLK_MSM_RPMH_H +#define _DT_BINDINGS_CLK_MSM_RPMH_H + +/* RPMh controlled clocks */ +#define RPMH_CXO_CLK 0 +#define RPMH_CXO_CLK_A 1 +#define RPMH_LN_BB_CLK2 2 +#define RPMH_LN_BB_CLK2_A 3 +#define RPMH_LN_BB_CLK3 4 +#define RPMH_LN_BB_CLK3_A 5 +#define RPMH_RF_CLK1 6 +#define RPMH_RF_CLK1_A 7 +#define RPMH_RF_CLK2 8 +#define RPMH_RF_CLK2_A 9 +#define RPMH_RF_CLK3 10 +#define RPMH_RF_CLK3_A 11 +#define RPMH_IPA_CLK 12 +#define RPMH_LN_BB_CLK1 13 +#define RPMH_LN_BB_CLK1_A 14 +#define RPMH_CE_CLK 15 +#define RPMH_QPIC_CLK 16 +#define RPMH_DIV_CLK1 17 +#define RPMH_DIV_CLK1_A 18 +#define RPMH_RF_CLK4 19 +#define RPMH_RF_CLK4_A 20 +#define RPMH_RF_CLK5 21 +#define RPMH_RF_CLK5_A 22 +#define RPMH_PKA_CLK 23 +#define RPMH_HWKM_CLK 24 +#define RPMH_QLINK_CLK 25 +#define RPMH_QLINK_CLK_A 26 + +#endif diff --git a/include/dt-bindings/clock/qcom,turingcc-qcs404.h b/include/dt-bindings/clock/qcom,turingcc-qcs404.h new file mode 100644 index 00000000000..838faef57c6 --- /dev/null +++ b/include/dt-bindings/clock/qcom,turingcc-qcs404.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2019, Linaro Ltd + */ + +#ifndef _DT_BINDINGS_CLK_TURING_QCS404_H +#define _DT_BINDINGS_CLK_TURING_QCS404_H + +#define TURING_Q6SS_Q6_AXIM_CLK 0 +#define TURING_Q6SS_AHBM_AON_CLK 1 +#define TURING_WRAPPER_AON_CLK 2 +#define TURING_Q6SS_AHBS_AON_CLK 3 +#define TURING_WRAPPER_QOS_AHBS_AON_CLK 4 + +#endif diff --git a/include/dt-bindings/clock/qcom,videocc-sdm845.h b/include/dt-bindings/clock/qcom,videocc-sdm845.h new file mode 100644 index 00000000000..1b868165e8c --- /dev/null +++ b/include/dt-bindings/clock/qcom,videocc-sdm845.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_SDM_VIDEO_CC_SDM845_H +#define _DT_BINDINGS_CLK_SDM_VIDEO_CC_SDM845_H + +/* VIDEO_CC clock registers */ +#define VIDEO_CC_APB_CLK 0 +#define VIDEO_CC_AT_CLK 1 +#define VIDEO_CC_QDSS_TRIG_CLK 2 +#define VIDEO_CC_QDSS_TSCTR_DIV8_CLK 3 +#define VIDEO_CC_VCODEC0_AXI_CLK 4 +#define VIDEO_CC_VCODEC0_CORE_CLK 5 +#define VIDEO_CC_VCODEC1_AXI_CLK 6 +#define VIDEO_CC_VCODEC1_CORE_CLK 7 +#define VIDEO_CC_VENUS_AHB_CLK 8 +#define VIDEO_CC_VENUS_CLK_SRC 9 +#define VIDEO_CC_VENUS_CTL_AXI_CLK 10 +#define VIDEO_CC_VENUS_CTL_CORE_CLK 11 +#define VIDEO_PLL0 12 + +/* VIDEO_CC Resets */ +#define VIDEO_CC_VENUS_BCR 0 +#define VIDEO_CC_VCODEC0_BCR 1 +#define VIDEO_CC_VCODEC1_BCR 2 +#define VIDEO_CC_INTERFACE_BCR 3 + +/* VIDEO_CC GDSCRs */ +#define VENUS_GDSC 0 +#define VCODEC0_GDSC 1 +#define VCODEC1_GDSC 2 + +#endif diff --git a/include/dt-bindings/dma/qcom-gpi.h b/include/dt-bindings/dma/qcom-gpi.h new file mode 100644 index 00000000000..ebda2a37f52 --- /dev/null +++ b/include/dt-bindings/dma/qcom-gpi.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ +/* Copyright (c) 2020, Linaro Ltd. */ + +#ifndef __DT_BINDINGS_DMA_QCOM_GPI_H__ +#define __DT_BINDINGS_DMA_QCOM_GPI_H__ + +#define QCOM_GPI_SPI 1 +#define QCOM_GPI_UART 2 +#define QCOM_GPI_I2C 3 + +#endif /* __DT_BINDINGS_DMA_QCOM_GPI_H__ */ diff --git a/include/dt-bindings/firmware/qcom,scm.h b/include/dt-bindings/firmware/qcom,scm.h new file mode 100644 index 00000000000..6de8b08e1e7 --- /dev/null +++ b/include/dt-bindings/firmware/qcom,scm.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Copyright (c) 2010-2015, 2018-2019 The Linux Foundation. All rights reserved. + * Copyright (C) 2015 Linaro Ltd. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_FIRMWARE_QCOM_SCM_H +#define _DT_BINDINGS_FIRMWARE_QCOM_SCM_H + +#define QCOM_SCM_VMID_TZ 0x1 +#define QCOM_SCM_VMID_HLOS 0x3 +#define QCOM_SCM_VMID_SSC_Q6 0x5 +#define QCOM_SCM_VMID_ADSP_Q6 0x6 +#define QCOM_SCM_VMID_CP_TOUCH 0x8 +#define QCOM_SCM_VMID_CP_BITSTREAM 0x9 +#define QCOM_SCM_VMID_CP_PIXEL 0xA +#define QCOM_SCM_VMID_CP_NON_PIXEL 0xB +#define QCOM_SCM_VMID_CP_CAMERA 0xD +#define QCOM_SCM_VMID_HLOS_FREE 0xE +#define QCOM_SCM_VMID_MSS_MSA 0xF +#define QCOM_SCM_VMID_MSS_NONMSA 0x10 +#define QCOM_SCM_VMID_CP_SEC_DISPLAY 0x11 +#define QCOM_SCM_VMID_CP_APP 0x12 +#define QCOM_SCM_VMID_LPASS 0x16 +#define QCOM_SCM_VMID_WLAN 0x18 +#define QCOM_SCM_VMID_WLAN_CE 0x19 +#define QCOM_SCM_VMID_CP_SPSS_SP 0x1A +#define QCOM_SCM_VMID_CP_CAMERA_PREVIEW 0x1D +#define QCOM_SCM_VMID_CDSP 0x1E +#define QCOM_SCM_VMID_CP_SPSS_SP_SHARED 0x22 +#define QCOM_SCM_VMID_CP_SPSS_HLOS_SHARED 0x24 +#define QCOM_SCM_VMID_ADSP_HEAP 0x25 +#define QCOM_SCM_VMID_CP_CDSP 0x2A +#define QCOM_SCM_VMID_NAV 0x2B +#define QCOM_SCM_VMID_TVM 0x2D +#define QCOM_SCM_VMID_OEMVM 0x31 + +#endif diff --git a/include/dt-bindings/gpio/meson-axg-gpio.h b/include/dt-bindings/gpio/meson-axg-gpio.h deleted file mode 100644 index 25bb1fffa97..00000000000 --- a/include/dt-bindings/gpio/meson-axg-gpio.h +++ /dev/null @@ -1,116 +0,0 @@ -/* - * Copyright (c) 2017 Amlogic, Inc. All rights reserved. - * Author: Xingyu Chen <xingyu.chen@amlogic.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _DT_BINDINGS_MESON_AXG_GPIO_H -#define _DT_BINDINGS_MESON_AXG_GPIO_H - -/* First GPIO chip */ -#define GPIOAO_0 0 -#define GPIOAO_1 1 -#define GPIOAO_2 2 -#define GPIOAO_3 3 -#define GPIOAO_4 4 -#define GPIOAO_5 5 -#define GPIOAO_6 6 -#define GPIOAO_7 7 -#define GPIOAO_8 8 -#define GPIOAO_9 9 -#define GPIOAO_10 10 -#define GPIOAO_11 11 -#define GPIOAO_12 12 -#define GPIOAO_13 13 -#define GPIO_TEST_N 14 - -/* Second GPIO chip */ -#define GPIOZ_0 0 -#define GPIOZ_1 1 -#define GPIOZ_2 2 -#define GPIOZ_3 3 -#define GPIOZ_4 4 -#define GPIOZ_5 5 -#define GPIOZ_6 6 -#define GPIOZ_7 7 -#define GPIOZ_8 8 -#define GPIOZ_9 9 -#define GPIOZ_10 10 -#define BOOT_0 11 -#define BOOT_1 12 -#define BOOT_2 13 -#define BOOT_3 14 -#define BOOT_4 15 -#define BOOT_5 16 -#define BOOT_6 17 -#define BOOT_7 18 -#define BOOT_8 19 -#define BOOT_9 20 -#define BOOT_10 21 -#define BOOT_11 22 -#define BOOT_12 23 -#define BOOT_13 24 -#define BOOT_14 25 -#define GPIOA_0 26 -#define GPIOA_1 27 -#define GPIOA_2 28 -#define GPIOA_3 29 -#define GPIOA_4 30 -#define GPIOA_5 31 -#define GPIOA_6 32 -#define GPIOA_7 33 -#define GPIOA_8 34 -#define GPIOA_9 35 -#define GPIOA_10 36 -#define GPIOA_11 37 -#define GPIOA_12 38 -#define GPIOA_13 39 -#define GPIOA_14 40 -#define GPIOA_15 41 -#define GPIOA_16 42 -#define GPIOA_17 43 -#define GPIOA_18 44 -#define GPIOA_19 45 -#define GPIOA_20 46 -#define GPIOX_0 47 -#define GPIOX_1 48 -#define GPIOX_2 49 -#define GPIOX_3 50 -#define GPIOX_4 51 -#define GPIOX_5 52 -#define GPIOX_6 53 -#define GPIOX_7 54 -#define GPIOX_8 55 -#define GPIOX_9 56 -#define GPIOX_10 57 -#define GPIOX_11 58 -#define GPIOX_12 59 -#define GPIOX_13 60 -#define GPIOX_14 61 -#define GPIOX_15 62 -#define GPIOX_16 63 -#define GPIOX_17 64 -#define GPIOX_18 65 -#define GPIOX_19 66 -#define GPIOX_20 67 -#define GPIOX_21 68 -#define GPIOX_22 69 -#define GPIOY_0 70 -#define GPIOY_1 71 -#define GPIOY_2 72 -#define GPIOY_3 73 -#define GPIOY_4 74 -#define GPIOY_5 75 -#define GPIOY_6 76 -#define GPIOY_7 77 -#define GPIOY_8 78 -#define GPIOY_9 79 -#define GPIOY_10 80 -#define GPIOY_11 81 -#define GPIOY_12 82 -#define GPIOY_13 83 -#define GPIOY_14 84 -#define GPIOY_15 85 - -#endif /* _DT_BINDINGS_MESON_AXG_GPIO_H */ diff --git a/include/dt-bindings/gpio/meson-g12a-gpio.h b/include/dt-bindings/gpio/meson-g12a-gpio.h deleted file mode 100644 index f7bd69350d1..00000000000 --- a/include/dt-bindings/gpio/meson-g12a-gpio.h +++ /dev/null @@ -1,114 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ -/* - * Copyright (c) 2018 Amlogic, Inc. All rights reserved. - * Author: Xingyu Chen <xingyu.chen@amlogic.com> - */ - -#ifndef _DT_BINDINGS_MESON_G12A_GPIO_H -#define _DT_BINDINGS_MESON_G12A_GPIO_H - -/* First GPIO chip */ -#define GPIOAO_0 0 -#define GPIOAO_1 1 -#define GPIOAO_2 2 -#define GPIOAO_3 3 -#define GPIOAO_4 4 -#define GPIOAO_5 5 -#define GPIOAO_6 6 -#define GPIOAO_7 7 -#define GPIOAO_8 8 -#define GPIOAO_9 9 -#define GPIOAO_10 10 -#define GPIOAO_11 11 -#define GPIOE_0 12 -#define GPIOE_1 13 -#define GPIOE_2 14 - -/* Second GPIO chip */ -#define GPIOZ_0 0 -#define GPIOZ_1 1 -#define GPIOZ_2 2 -#define GPIOZ_3 3 -#define GPIOZ_4 4 -#define GPIOZ_5 5 -#define GPIOZ_6 6 -#define GPIOZ_7 7 -#define GPIOZ_8 8 -#define GPIOZ_9 9 -#define GPIOZ_10 10 -#define GPIOZ_11 11 -#define GPIOZ_12 12 -#define GPIOZ_13 13 -#define GPIOZ_14 14 -#define GPIOZ_15 15 -#define GPIOH_0 16 -#define GPIOH_1 17 -#define GPIOH_2 18 -#define GPIOH_3 19 -#define GPIOH_4 20 -#define GPIOH_5 21 -#define GPIOH_6 22 -#define GPIOH_7 23 -#define GPIOH_8 24 -#define BOOT_0 25 -#define BOOT_1 26 -#define BOOT_2 27 -#define BOOT_3 28 -#define BOOT_4 29 -#define BOOT_5 30 -#define BOOT_6 31 -#define BOOT_7 32 -#define BOOT_8 33 -#define BOOT_9 34 -#define BOOT_10 35 -#define BOOT_11 36 -#define BOOT_12 37 -#define BOOT_13 38 -#define BOOT_14 39 -#define BOOT_15 40 -#define GPIOC_0 41 -#define GPIOC_1 42 -#define GPIOC_2 43 -#define GPIOC_3 44 -#define GPIOC_4 45 -#define GPIOC_5 46 -#define GPIOC_6 47 -#define GPIOC_7 48 -#define GPIOA_0 49 -#define GPIOA_1 50 -#define GPIOA_2 51 -#define GPIOA_3 52 -#define GPIOA_4 53 -#define GPIOA_5 54 -#define GPIOA_6 55 -#define GPIOA_7 56 -#define GPIOA_8 57 -#define GPIOA_9 58 -#define GPIOA_10 59 -#define GPIOA_11 60 -#define GPIOA_12 61 -#define GPIOA_13 62 -#define GPIOA_14 63 -#define GPIOA_15 64 -#define GPIOX_0 65 -#define GPIOX_1 66 -#define GPIOX_2 67 -#define GPIOX_3 68 -#define GPIOX_4 69 -#define GPIOX_5 70 -#define GPIOX_6 71 -#define GPIOX_7 72 -#define GPIOX_8 73 -#define GPIOX_9 74 -#define GPIOX_10 75 -#define GPIOX_11 76 -#define GPIOX_12 77 -#define GPIOX_13 78 -#define GPIOX_14 79 -#define GPIOX_15 80 -#define GPIOX_16 81 -#define GPIOX_17 82 -#define GPIOX_18 83 -#define GPIOX_19 84 - -#endif /* _DT_BINDINGS_MESON_G12A_GPIO_H */ diff --git a/include/dt-bindings/gpio/meson-gxbb-gpio.h b/include/dt-bindings/gpio/meson-gxbb-gpio.h deleted file mode 100644 index 489c75b2764..00000000000 --- a/include/dt-bindings/gpio/meson-gxbb-gpio.h +++ /dev/null @@ -1,148 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * GPIO definitions for Amlogic Meson GXBB SoCs - * - * Copyright (C) 2016 Endless Mobile, Inc. - * Author: Carlo Caione <carlo@endlessm.com> - */ - -#ifndef _DT_BINDINGS_MESON_GXBB_GPIO_H -#define _DT_BINDINGS_MESON_GXBB_GPIO_H - -#define GPIOAO_0 0 -#define GPIOAO_1 1 -#define GPIOAO_2 2 -#define GPIOAO_3 3 -#define GPIOAO_4 4 -#define GPIOAO_5 5 -#define GPIOAO_6 6 -#define GPIOAO_7 7 -#define GPIOAO_8 8 -#define GPIOAO_9 9 -#define GPIOAO_10 10 -#define GPIOAO_11 11 -#define GPIOAO_12 12 -#define GPIOAO_13 13 -#define GPIO_TEST_N 14 - -#define GPIOZ_0 0 -#define GPIOZ_1 1 -#define GPIOZ_2 2 -#define GPIOZ_3 3 -#define GPIOZ_4 4 -#define GPIOZ_5 5 -#define GPIOZ_6 6 -#define GPIOZ_7 7 -#define GPIOZ_8 8 -#define GPIOZ_9 9 -#define GPIOZ_10 10 -#define GPIOZ_11 11 -#define GPIOZ_12 12 -#define GPIOZ_13 13 -#define GPIOZ_14 14 -#define GPIOZ_15 15 -#define GPIOH_0 16 -#define GPIOH_1 17 -#define GPIOH_2 18 -#define GPIOH_3 19 -#define BOOT_0 20 -#define BOOT_1 21 -#define BOOT_2 22 -#define BOOT_3 23 -#define BOOT_4 24 -#define BOOT_5 25 -#define BOOT_6 26 -#define BOOT_7 27 -#define BOOT_8 28 -#define BOOT_9 29 -#define BOOT_10 30 -#define BOOT_11 31 -#define BOOT_12 32 -#define BOOT_13 33 -#define BOOT_14 34 -#define BOOT_15 35 -#define BOOT_16 36 -#define BOOT_17 37 -#define CARD_0 38 -#define CARD_1 39 -#define CARD_2 40 -#define CARD_3 41 -#define CARD_4 42 -#define CARD_5 43 -#define CARD_6 44 -#define GPIODV_0 45 -#define GPIODV_1 46 -#define GPIODV_2 47 -#define GPIODV_3 48 -#define GPIODV_4 49 -#define GPIODV_5 50 -#define GPIODV_6 51 -#define GPIODV_7 52 -#define GPIODV_8 53 -#define GPIODV_9 54 -#define GPIODV_10 55 -#define GPIODV_11 56 -#define GPIODV_12 57 -#define GPIODV_13 58 -#define GPIODV_14 59 -#define GPIODV_15 60 -#define GPIODV_16 61 -#define GPIODV_17 62 -#define GPIODV_18 63 -#define GPIODV_19 64 -#define GPIODV_20 65 -#define GPIODV_21 66 -#define GPIODV_22 67 -#define GPIODV_23 68 -#define GPIODV_24 69 -#define GPIODV_25 70 -#define GPIODV_26 71 -#define GPIODV_27 72 -#define GPIODV_28 73 -#define GPIODV_29 74 -#define GPIOY_0 75 -#define GPIOY_1 76 -#define GPIOY_2 77 -#define GPIOY_3 78 -#define GPIOY_4 79 -#define GPIOY_5 80 -#define GPIOY_6 81 -#define GPIOY_7 82 -#define GPIOY_8 83 -#define GPIOY_9 84 -#define GPIOY_10 85 -#define GPIOY_11 86 -#define GPIOY_12 87 -#define GPIOY_13 88 -#define GPIOY_14 89 -#define GPIOY_15 90 -#define GPIOY_16 91 -#define GPIOX_0 92 -#define GPIOX_1 93 -#define GPIOX_2 94 -#define GPIOX_3 95 -#define GPIOX_4 96 -#define GPIOX_5 97 -#define GPIOX_6 98 -#define GPIOX_7 99 -#define GPIOX_8 100 -#define GPIOX_9 101 -#define GPIOX_10 102 -#define GPIOX_11 103 -#define GPIOX_12 104 -#define GPIOX_13 105 -#define GPIOX_14 106 -#define GPIOX_15 107 -#define GPIOX_16 108 -#define GPIOX_17 109 -#define GPIOX_18 110 -#define GPIOX_19 111 -#define GPIOX_20 112 -#define GPIOX_21 113 -#define GPIOX_22 114 -#define GPIOCLK_0 115 -#define GPIOCLK_1 116 -#define GPIOCLK_2 117 -#define GPIOCLK_3 118 - -#endif diff --git a/include/dt-bindings/gpio/meson-gxl-gpio.h b/include/dt-bindings/gpio/meson-gxl-gpio.h deleted file mode 100644 index 0a001ae4827..00000000000 --- a/include/dt-bindings/gpio/meson-gxl-gpio.h +++ /dev/null @@ -1,125 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * GPIO definitions for Amlogic Meson GXL SoCs - * - * Copyright (C) 2016 Endless Mobile, Inc. - * Author: Carlo Caione <carlo@endlessm.com> - */ - -#ifndef _DT_BINDINGS_MESON_GXL_GPIO_H -#define _DT_BINDINGS_MESON_GXL_GPIO_H - -#define GPIOAO_0 0 -#define GPIOAO_1 1 -#define GPIOAO_2 2 -#define GPIOAO_3 3 -#define GPIOAO_4 4 -#define GPIOAO_5 5 -#define GPIOAO_6 6 -#define GPIOAO_7 7 -#define GPIOAO_8 8 -#define GPIOAO_9 9 -#define GPIO_TEST_N 10 - -#define GPIOZ_0 0 -#define GPIOZ_1 1 -#define GPIOZ_2 2 -#define GPIOZ_3 3 -#define GPIOZ_4 4 -#define GPIOZ_5 5 -#define GPIOZ_6 6 -#define GPIOZ_7 7 -#define GPIOZ_8 8 -#define GPIOZ_9 9 -#define GPIOZ_10 10 -#define GPIOZ_11 11 -#define GPIOZ_12 12 -#define GPIOZ_13 13 -#define GPIOZ_14 14 -#define GPIOZ_15 15 -#define GPIOH_0 16 -#define GPIOH_1 17 -#define GPIOH_2 18 -#define GPIOH_3 19 -#define GPIOH_4 20 -#define GPIOH_5 21 -#define GPIOH_6 22 -#define GPIOH_7 23 -#define GPIOH_8 24 -#define GPIOH_9 25 -#define BOOT_0 26 -#define BOOT_1 27 -#define BOOT_2 28 -#define BOOT_3 29 -#define BOOT_4 30 -#define BOOT_5 31 -#define BOOT_6 32 -#define BOOT_7 33 -#define BOOT_8 34 -#define BOOT_9 35 -#define BOOT_10 36 -#define BOOT_11 37 -#define BOOT_12 38 -#define BOOT_13 39 -#define BOOT_14 40 -#define BOOT_15 41 -#define CARD_0 42 -#define CARD_1 43 -#define CARD_2 44 -#define CARD_3 45 -#define CARD_4 46 -#define CARD_5 47 -#define CARD_6 48 -#define GPIODV_0 49 -#define GPIODV_1 50 -#define GPIODV_2 51 -#define GPIODV_3 52 -#define GPIODV_4 53 -#define GPIODV_5 54 -#define GPIODV_6 55 -#define GPIODV_7 56 -#define GPIODV_8 57 -#define GPIODV_9 58 -#define GPIODV_10 59 -#define GPIODV_11 60 -#define GPIODV_12 61 -#define GPIODV_13 62 -#define GPIODV_14 63 -#define GPIODV_15 64 -#define GPIODV_16 65 -#define GPIODV_17 66 -#define GPIODV_18 67 -#define GPIODV_19 68 -#define GPIODV_20 69 -#define GPIODV_21 70 -#define GPIODV_22 71 -#define GPIODV_23 72 -#define GPIODV_24 73 -#define GPIODV_25 74 -#define GPIODV_26 75 -#define GPIODV_27 76 -#define GPIODV_28 77 -#define GPIODV_29 78 -#define GPIOX_0 79 -#define GPIOX_1 80 -#define GPIOX_2 81 -#define GPIOX_3 82 -#define GPIOX_4 83 -#define GPIOX_5 84 -#define GPIOX_6 85 -#define GPIOX_7 86 -#define GPIOX_8 87 -#define GPIOX_9 88 -#define GPIOX_10 89 -#define GPIOX_11 90 -#define GPIOX_12 91 -#define GPIOX_13 92 -#define GPIOX_14 93 -#define GPIOX_15 94 -#define GPIOX_16 95 -#define GPIOX_17 96 -#define GPIOX_18 97 -#define GPIOCLK_0 98 -#define GPIOCLK_1 99 - -#endif diff --git a/include/dt-bindings/iio/qcom,spmi-vadc.h b/include/dt-bindings/iio/qcom,spmi-vadc.h new file mode 100644 index 00000000000..08adfe25964 --- /dev/null +++ b/include/dt-bindings/iio/qcom,spmi-vadc.h @@ -0,0 +1,300 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2012-2014,2018,2020 The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_H +#define _DT_BINDINGS_QCOM_SPMI_VADC_H + +/* Voltage ADC channels */ +#define VADC_USBIN 0x00 +#define VADC_DCIN 0x01 +#define VADC_VCHG_SNS 0x02 +#define VADC_SPARE1_03 0x03 +#define VADC_USB_ID_MV 0x04 +#define VADC_VCOIN 0x05 +#define VADC_VBAT_SNS 0x06 +#define VADC_VSYS 0x07 +#define VADC_DIE_TEMP 0x08 +#define VADC_REF_625MV 0x09 +#define VADC_REF_1250MV 0x0a +#define VADC_CHG_TEMP 0x0b +#define VADC_SPARE1 0x0c +#define VADC_SPARE2 0x0d +#define VADC_GND_REF 0x0e +#define VADC_VDD_VADC 0x0f + +#define VADC_P_MUX1_1_1 0x10 +#define VADC_P_MUX2_1_1 0x11 +#define VADC_P_MUX3_1_1 0x12 +#define VADC_P_MUX4_1_1 0x13 +#define VADC_P_MUX5_1_1 0x14 +#define VADC_P_MUX6_1_1 0x15 +#define VADC_P_MUX7_1_1 0x16 +#define VADC_P_MUX8_1_1 0x17 +#define VADC_P_MUX9_1_1 0x18 +#define VADC_P_MUX10_1_1 0x19 +#define VADC_P_MUX11_1_1 0x1a +#define VADC_P_MUX12_1_1 0x1b +#define VADC_P_MUX13_1_1 0x1c +#define VADC_P_MUX14_1_1 0x1d +#define VADC_P_MUX15_1_1 0x1e +#define VADC_P_MUX16_1_1 0x1f + +#define VADC_P_MUX1_1_3 0x20 +#define VADC_P_MUX2_1_3 0x21 +#define VADC_P_MUX3_1_3 0x22 +#define VADC_P_MUX4_1_3 0x23 +#define VADC_P_MUX5_1_3 0x24 +#define VADC_P_MUX6_1_3 0x25 +#define VADC_P_MUX7_1_3 0x26 +#define VADC_P_MUX8_1_3 0x27 +#define VADC_P_MUX9_1_3 0x28 +#define VADC_P_MUX10_1_3 0x29 +#define VADC_P_MUX11_1_3 0x2a +#define VADC_P_MUX12_1_3 0x2b +#define VADC_P_MUX13_1_3 0x2c +#define VADC_P_MUX14_1_3 0x2d +#define VADC_P_MUX15_1_3 0x2e +#define VADC_P_MUX16_1_3 0x2f + +#define VADC_LR_MUX1_BAT_THERM 0x30 +#define VADC_LR_MUX2_BAT_ID 0x31 +#define VADC_LR_MUX3_XO_THERM 0x32 +#define VADC_LR_MUX4_AMUX_THM1 0x33 +#define VADC_LR_MUX5_AMUX_THM2 0x34 +#define VADC_LR_MUX6_AMUX_THM3 0x35 +#define VADC_LR_MUX7_HW_ID 0x36 +#define VADC_LR_MUX8_AMUX_THM4 0x37 +#define VADC_LR_MUX9_AMUX_THM5 0x38 +#define VADC_LR_MUX10_USB_ID 0x39 +#define VADC_AMUX_PU1 0x3a +#define VADC_AMUX_PU2 0x3b +#define VADC_LR_MUX3_BUF_XO_THERM 0x3c + +#define VADC_LR_MUX1_PU1_BAT_THERM 0x70 +#define VADC_LR_MUX2_PU1_BAT_ID 0x71 +#define VADC_LR_MUX3_PU1_XO_THERM 0x72 +#define VADC_LR_MUX4_PU1_AMUX_THM1 0x73 +#define VADC_LR_MUX5_PU1_AMUX_THM2 0x74 +#define VADC_LR_MUX6_PU1_AMUX_THM3 0x75 +#define VADC_LR_MUX7_PU1_AMUX_HW_ID 0x76 +#define VADC_LR_MUX8_PU1_AMUX_THM4 0x77 +#define VADC_LR_MUX9_PU1_AMUX_THM5 0x78 +#define VADC_LR_MUX10_PU1_AMUX_USB_ID 0x79 +#define VADC_LR_MUX3_BUF_PU1_XO_THERM 0x7c + +#define VADC_LR_MUX1_PU2_BAT_THERM 0xb0 +#define VADC_LR_MUX2_PU2_BAT_ID 0xb1 +#define VADC_LR_MUX3_PU2_XO_THERM 0xb2 +#define VADC_LR_MUX4_PU2_AMUX_THM1 0xb3 +#define VADC_LR_MUX5_PU2_AMUX_THM2 0xb4 +#define VADC_LR_MUX6_PU2_AMUX_THM3 0xb5 +#define VADC_LR_MUX7_PU2_AMUX_HW_ID 0xb6 +#define VADC_LR_MUX8_PU2_AMUX_THM4 0xb7 +#define VADC_LR_MUX9_PU2_AMUX_THM5 0xb8 +#define VADC_LR_MUX10_PU2_AMUX_USB_ID 0xb9 +#define VADC_LR_MUX3_BUF_PU2_XO_THERM 0xbc + +#define VADC_LR_MUX1_PU1_PU2_BAT_THERM 0xf0 +#define VADC_LR_MUX2_PU1_PU2_BAT_ID 0xf1 +#define VADC_LR_MUX3_PU1_PU2_XO_THERM 0xf2 +#define VADC_LR_MUX4_PU1_PU2_AMUX_THM1 0xf3 +#define VADC_LR_MUX5_PU1_PU2_AMUX_THM2 0xf4 +#define VADC_LR_MUX6_PU1_PU2_AMUX_THM3 0xf5 +#define VADC_LR_MUX7_PU1_PU2_AMUX_HW_ID 0xf6 +#define VADC_LR_MUX8_PU1_PU2_AMUX_THM4 0xf7 +#define VADC_LR_MUX9_PU1_PU2_AMUX_THM5 0xf8 +#define VADC_LR_MUX10_PU1_PU2_AMUX_USB_ID 0xf9 +#define VADC_LR_MUX3_BUF_PU1_PU2_XO_THERM 0xfc + +/* ADC channels for SPMI PMIC5 */ + +#define ADC5_REF_GND 0x00 +#define ADC5_1P25VREF 0x01 +#define ADC5_VREF_VADC 0x02 +#define ADC5_VREF_VADC5_DIV_3 0x82 +#define ADC5_VPH_PWR 0x83 +#define ADC5_VBAT_SNS 0x84 +#define ADC5_VCOIN 0x85 +#define ADC5_DIE_TEMP 0x06 +#define ADC5_USB_IN_I 0x07 +#define ADC5_USB_IN_V_16 0x08 +#define ADC5_CHG_TEMP 0x09 +#define ADC5_BAT_THERM 0x0a +#define ADC5_BAT_ID 0x0b +#define ADC5_XO_THERM 0x0c +#define ADC5_AMUX_THM1 0x0d +#define ADC5_AMUX_THM2 0x0e +#define ADC5_AMUX_THM3 0x0f +#define ADC5_AMUX_THM4 0x10 +#define ADC5_AMUX_THM5 0x11 +#define ADC5_GPIO1 0x12 +#define ADC5_GPIO2 0x13 +#define ADC5_GPIO3 0x14 +#define ADC5_GPIO4 0x15 +#define ADC5_GPIO5 0x16 +#define ADC5_GPIO6 0x17 +#define ADC5_GPIO7 0x18 +#define ADC5_SBUx 0x99 +#define ADC5_MID_CHG_DIV6 0x1e +#define ADC5_OFF 0xff + +/* 30k pull-up1 */ +#define ADC5_BAT_THERM_30K_PU 0x2a +#define ADC5_BAT_ID_30K_PU 0x2b +#define ADC5_XO_THERM_30K_PU 0x2c +#define ADC5_AMUX_THM1_30K_PU 0x2d +#define ADC5_AMUX_THM2_30K_PU 0x2e +#define ADC5_AMUX_THM3_30K_PU 0x2f +#define ADC5_AMUX_THM4_30K_PU 0x30 +#define ADC5_AMUX_THM5_30K_PU 0x31 +#define ADC5_GPIO1_30K_PU 0x32 +#define ADC5_GPIO2_30K_PU 0x33 +#define ADC5_GPIO3_30K_PU 0x34 +#define ADC5_GPIO4_30K_PU 0x35 +#define ADC5_GPIO5_30K_PU 0x36 +#define ADC5_GPIO6_30K_PU 0x37 +#define ADC5_GPIO7_30K_PU 0x38 +#define ADC5_SBUx_30K_PU 0x39 + +/* 100k pull-up2 */ +#define ADC5_BAT_THERM_100K_PU 0x4a +#define ADC5_BAT_ID_100K_PU 0x4b +#define ADC5_XO_THERM_100K_PU 0x4c +#define ADC5_AMUX_THM1_100K_PU 0x4d +#define ADC5_AMUX_THM2_100K_PU 0x4e +#define ADC5_AMUX_THM3_100K_PU 0x4f +#define ADC5_AMUX_THM4_100K_PU 0x50 +#define ADC5_AMUX_THM5_100K_PU 0x51 +#define ADC5_GPIO1_100K_PU 0x52 +#define ADC5_GPIO2_100K_PU 0x53 +#define ADC5_GPIO3_100K_PU 0x54 +#define ADC5_GPIO4_100K_PU 0x55 +#define ADC5_GPIO5_100K_PU 0x56 +#define ADC5_GPIO6_100K_PU 0x57 +#define ADC5_GPIO7_100K_PU 0x58 +#define ADC5_SBUx_100K_PU 0x59 + +/* 400k pull-up3 */ +#define ADC5_BAT_THERM_400K_PU 0x6a +#define ADC5_BAT_ID_400K_PU 0x6b +#define ADC5_XO_THERM_400K_PU 0x6c +#define ADC5_AMUX_THM1_400K_PU 0x6d +#define ADC5_AMUX_THM2_400K_PU 0x6e +#define ADC5_AMUX_THM3_400K_PU 0x6f +#define ADC5_AMUX_THM4_400K_PU 0x70 +#define ADC5_AMUX_THM5_400K_PU 0x71 +#define ADC5_GPIO1_400K_PU 0x72 +#define ADC5_GPIO2_400K_PU 0x73 +#define ADC5_GPIO3_400K_PU 0x74 +#define ADC5_GPIO4_400K_PU 0x75 +#define ADC5_GPIO5_400K_PU 0x76 +#define ADC5_GPIO6_400K_PU 0x77 +#define ADC5_GPIO7_400K_PU 0x78 +#define ADC5_SBUx_400K_PU 0x79 + +/* 1/3 Divider */ +#define ADC5_GPIO1_DIV3 0x92 +#define ADC5_GPIO2_DIV3 0x93 +#define ADC5_GPIO3_DIV3 0x94 +#define ADC5_GPIO4_DIV3 0x95 +#define ADC5_GPIO5_DIV3 0x96 +#define ADC5_GPIO6_DIV3 0x97 +#define ADC5_GPIO7_DIV3 0x98 +#define ADC5_SBUx_DIV3 0x99 + +/* Current and combined current/voltage channels */ +#define ADC5_INT_EXT_ISENSE 0xa1 +#define ADC5_PARALLEL_ISENSE 0xa5 +#define ADC5_CUR_REPLICA_VDS 0xa7 +#define ADC5_CUR_SENS_BATFET_VDS_OFFSET 0xa9 +#define ADC5_CUR_SENS_REPLICA_VDS_OFFSET 0xab +#define ADC5_EXT_SENS_OFFSET 0xad + +#define ADC5_INT_EXT_ISENSE_VBAT_VDATA 0xb0 +#define ADC5_INT_EXT_ISENSE_VBAT_IDATA 0xb1 +#define ADC5_EXT_ISENSE_VBAT_VDATA 0xb2 +#define ADC5_EXT_ISENSE_VBAT_IDATA 0xb3 +#define ADC5_PARALLEL_ISENSE_VBAT_VDATA 0xb4 +#define ADC5_PARALLEL_ISENSE_VBAT_IDATA 0xb5 + +#define ADC5_MAX_CHANNEL 0xc0 + +/* ADC channels for ADC for PMIC7 */ + +#define ADC7_REF_GND 0x00 +#define ADC7_1P25VREF 0x01 +#define ADC7_VREF_VADC 0x02 +#define ADC7_DIE_TEMP 0x03 + +#define ADC7_AMUX_THM1 0x04 +#define ADC7_AMUX_THM2 0x05 +#define ADC7_AMUX_THM3 0x06 +#define ADC7_AMUX_THM4 0x07 +#define ADC7_AMUX_THM5 0x08 +#define ADC7_AMUX_THM6 0x09 +#define ADC7_GPIO1 0x0a +#define ADC7_GPIO2 0x0b +#define ADC7_GPIO3 0x0c +#define ADC7_GPIO4 0x0d + +#define ADC7_CHG_TEMP 0x10 +#define ADC7_USB_IN_V_16 0x11 +#define ADC7_VDC_16 0x12 +#define ADC7_CC1_ID 0x13 +#define ADC7_VREF_BAT_THERM 0x15 +#define ADC7_IIN_FB 0x17 + +/* 30k pull-up1 */ +#define ADC7_AMUX_THM1_30K_PU 0x24 +#define ADC7_AMUX_THM2_30K_PU 0x25 +#define ADC7_AMUX_THM3_30K_PU 0x26 +#define ADC7_AMUX_THM4_30K_PU 0x27 +#define ADC7_AMUX_THM5_30K_PU 0x28 +#define ADC7_AMUX_THM6_30K_PU 0x29 +#define ADC7_GPIO1_30K_PU 0x2a +#define ADC7_GPIO2_30K_PU 0x2b +#define ADC7_GPIO3_30K_PU 0x2c +#define ADC7_GPIO4_30K_PU 0x2d +#define ADC7_CC1_ID_30K_PU 0x33 + +/* 100k pull-up2 */ +#define ADC7_AMUX_THM1_100K_PU 0x44 +#define ADC7_AMUX_THM2_100K_PU 0x45 +#define ADC7_AMUX_THM3_100K_PU 0x46 +#define ADC7_AMUX_THM4_100K_PU 0x47 +#define ADC7_AMUX_THM5_100K_PU 0x48 +#define ADC7_AMUX_THM6_100K_PU 0x49 +#define ADC7_GPIO1_100K_PU 0x4a +#define ADC7_GPIO2_100K_PU 0x4b +#define ADC7_GPIO3_100K_PU 0x4c +#define ADC7_GPIO4_100K_PU 0x4d +#define ADC7_CC1_ID_100K_PU 0x53 + +/* 400k pull-up3 */ +#define ADC7_AMUX_THM1_400K_PU 0x64 +#define ADC7_AMUX_THM2_400K_PU 0x65 +#define ADC7_AMUX_THM3_400K_PU 0x66 +#define ADC7_AMUX_THM4_400K_PU 0x67 +#define ADC7_AMUX_THM5_400K_PU 0x68 +#define ADC7_AMUX_THM6_400K_PU 0x69 +#define ADC7_GPIO1_400K_PU 0x6a +#define ADC7_GPIO2_400K_PU 0x6b +#define ADC7_GPIO3_400K_PU 0x6c +#define ADC7_GPIO4_400K_PU 0x6d +#define ADC7_CC1_ID_400K_PU 0x73 + +/* 1/3 Divider */ +#define ADC7_GPIO1_DIV3 0x8a +#define ADC7_GPIO2_DIV3 0x8b +#define ADC7_GPIO3_DIV3 0x8c +#define ADC7_GPIO4_DIV3 0x8d + +#define ADC7_VPH_PWR 0x8e +#define ADC7_VBAT_SNS 0x8f + +#define ADC7_SBUx 0x94 +#define ADC7_VBAT_2S_MID 0x96 + +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_H */ diff --git a/include/dt-bindings/interconnect/qcom,msm8916.h b/include/dt-bindings/interconnect/qcom,msm8916.h new file mode 100644 index 00000000000..359a75feb19 --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,msm8916.h @@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Qualcomm interconnect IDs + * + * Copyright (c) 2019, Linaro Ltd. + * Author: Georgi Djakov <georgi.djakov@linaro.org> + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MSM8916_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_MSM8916_H + +#define BIMC_SNOC_SLV 0 +#define MASTER_JPEG 1 +#define MASTER_MDP_PORT0 2 +#define MASTER_QDSS_BAM 3 +#define MASTER_QDSS_ETR 4 +#define MASTER_SNOC_CFG 5 +#define MASTER_VFE 6 +#define MASTER_VIDEO_P0 7 +#define SNOC_MM_INT_0 8 +#define SNOC_MM_INT_1 9 +#define SNOC_MM_INT_2 10 +#define SNOC_MM_INT_BIMC 11 +#define PCNOC_SNOC_SLV 12 +#define SLAVE_APSS 13 +#define SLAVE_CATS_128 14 +#define SLAVE_OCMEM_64 15 +#define SLAVE_IMEM 16 +#define SLAVE_QDSS_STM 17 +#define SLAVE_SRVC_SNOC 18 +#define SNOC_BIMC_0_MAS 19 +#define SNOC_BIMC_1_MAS 20 +#define SNOC_INT_0 21 +#define SNOC_INT_1 22 +#define SNOC_INT_BIMC 23 +#define SNOC_PCNOC_MAS 24 +#define SNOC_QDSS_INT 25 + +#define BIMC_SNOC_MAS 0 +#define MASTER_AMPSS_M0 1 +#define MASTER_GRAPHICS_3D 2 +#define MASTER_TCU0 3 +#define MASTER_TCU1 4 +#define SLAVE_AMPSS_L2 5 +#define SLAVE_EBI_CH0 6 +#define SNOC_BIMC_0_SLV 7 +#define SNOC_BIMC_1_SLV 8 + +#define MASTER_BLSP_1 0 +#define MASTER_DEHR 1 +#define MASTER_LPASS 2 +#define MASTER_CRYPTO_CORE0 3 +#define MASTER_SDCC_1 4 +#define MASTER_SDCC_2 5 +#define MASTER_SPDM 6 +#define MASTER_USB_HS 7 +#define PCNOC_INT_0 8 +#define PCNOC_INT_1 9 +#define PCNOC_MAS_0 10 +#define PCNOC_MAS_1 11 +#define PCNOC_SLV_0 12 +#define PCNOC_SLV_1 13 +#define PCNOC_SLV_2 14 +#define PCNOC_SLV_3 15 +#define PCNOC_SLV_4 16 +#define PCNOC_SLV_8 17 +#define PCNOC_SLV_9 18 +#define PCNOC_SNOC_MAS 19 +#define SLAVE_BIMC_CFG 20 +#define SLAVE_BLSP_1 21 +#define SLAVE_BOOT_ROM 22 +#define SLAVE_CAMERA_CFG 23 +#define SLAVE_CLK_CTL 24 +#define SLAVE_CRYPTO_0_CFG 25 +#define SLAVE_DEHR_CFG 26 +#define SLAVE_DISPLAY_CFG 27 +#define SLAVE_GRAPHICS_3D_CFG 28 +#define SLAVE_IMEM_CFG 29 +#define SLAVE_LPASS 30 +#define SLAVE_MPM 31 +#define SLAVE_MSG_RAM 32 +#define SLAVE_MSS 33 +#define SLAVE_PDM 34 +#define SLAVE_PMIC_ARB 35 +#define SLAVE_PCNOC_CFG 36 +#define SLAVE_PRNG 37 +#define SLAVE_QDSS_CFG 38 +#define SLAVE_RBCPR_CFG 39 +#define SLAVE_SDCC_1 40 +#define SLAVE_SDCC_2 41 +#define SLAVE_SECURITY 42 +#define SLAVE_SNOC_CFG 43 +#define SLAVE_SPDM 44 +#define SLAVE_TCSR 45 +#define SLAVE_TLMM 46 +#define SLAVE_USB_HS 47 +#define SLAVE_VENUS_CFG 48 +#define SNOC_PCNOC_SLV 49 + +#endif diff --git a/include/dt-bindings/interconnect/qcom,msm8996-cbf.h b/include/dt-bindings/interconnect/qcom,msm8996-cbf.h new file mode 100644 index 00000000000..aac5e69f6bd --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,msm8996-cbf.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2023 Linaro Ltd. All rights reserved. + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MSM8996_CBF_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_MSM8996_CBF_H + +#define MASTER_CBF_M4M 0 +#define SLAVE_CBF_M4M 1 + +#endif diff --git a/include/dt-bindings/interconnect/qcom,msm8996.h b/include/dt-bindings/interconnect/qcom,msm8996.h new file mode 100644 index 00000000000..a0b7c0ec7be --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,msm8996.h @@ -0,0 +1,163 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/* + * Qualcomm MSM8996 interconnect IDs + * + * Copyright (c) 2021 Yassine Oudjana <y.oudjana@protonmail.com> + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MSM8996_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_MSM8996_H + +/* A0NOC */ +#define MASTER_PCIE_0 0 +#define MASTER_PCIE_1 1 +#define MASTER_PCIE_2 2 + +/* A1NOC */ +#define MASTER_CNOC_A1NOC 0 +#define MASTER_CRYPTO_CORE0 1 +#define MASTER_PNOC_A1NOC 2 + +/* A2NOC */ +#define MASTER_USB3 0 +#define MASTER_IPA 1 +#define MASTER_UFS 2 + +/* BIMC */ +#define MASTER_AMPSS_M0 0 +#define MASTER_GRAPHICS_3D 1 +#define MASTER_MNOC_BIMC 2 +#define MASTER_SNOC_BIMC 3 +#define SLAVE_EBI_CH0 4 +#define SLAVE_HMSS_L3 5 +#define SLAVE_BIMC_SNOC_0 6 +#define SLAVE_BIMC_SNOC_1 7 + +/* CNOC */ +#define MASTER_SNOC_CNOC 0 +#define MASTER_QDSS_DAP 1 +#define SLAVE_CNOC_A1NOC 2 +#define SLAVE_CLK_CTL 3 +#define SLAVE_TCSR 4 +#define SLAVE_TLMM 5 +#define SLAVE_CRYPTO_0_CFG 6 +#define SLAVE_MPM 7 +#define SLAVE_PIMEM_CFG 8 +#define SLAVE_IMEM_CFG 9 +#define SLAVE_MESSAGE_RAM 10 +#define SLAVE_BIMC_CFG 11 +#define SLAVE_PMIC_ARB 12 +#define SLAVE_PRNG 13 +#define SLAVE_DCC_CFG 14 +#define SLAVE_RBCPR_MX 15 +#define SLAVE_QDSS_CFG 16 +#define SLAVE_RBCPR_CX 17 +#define SLAVE_QDSS_RBCPR_APU 18 +#define SLAVE_CNOC_MNOC_CFG 19 +#define SLAVE_SNOC_CFG 20 +#define SLAVE_SNOC_MPU_CFG 21 +#define SLAVE_EBI1_PHY_CFG 22 +#define SLAVE_A0NOC_CFG 23 +#define SLAVE_PCIE_1_CFG 24 +#define SLAVE_PCIE_2_CFG 25 +#define SLAVE_PCIE_0_CFG 26 +#define SLAVE_PCIE20_AHB2PHY 27 +#define SLAVE_A0NOC_MPU_CFG 28 +#define SLAVE_UFS_CFG 29 +#define SLAVE_A1NOC_CFG 30 +#define SLAVE_A1NOC_MPU_CFG 31 +#define SLAVE_A2NOC_CFG 32 +#define SLAVE_A2NOC_MPU_CFG 33 +#define SLAVE_SSC_CFG 34 +#define SLAVE_A0NOC_SMMU_CFG 35 +#define SLAVE_A1NOC_SMMU_CFG 36 +#define SLAVE_A2NOC_SMMU_CFG 37 +#define SLAVE_LPASS_SMMU_CFG 38 +#define SLAVE_CNOC_MNOC_MMSS_CFG 39 + +/* MNOC */ +#define MASTER_CNOC_MNOC_CFG 0 +#define MASTER_CPP 1 +#define MASTER_JPEG 2 +#define MASTER_MDP_PORT0 3 +#define MASTER_MDP_PORT1 4 +#define MASTER_ROTATOR 5 +#define MASTER_VIDEO_P0 6 +#define MASTER_VFE 7 +#define MASTER_SNOC_VMEM 8 +#define MASTER_VIDEO_P0_OCMEM 9 +#define MASTER_CNOC_MNOC_MMSS_CFG 10 +#define SLAVE_MNOC_BIMC 11 +#define SLAVE_VMEM 12 +#define SLAVE_SERVICE_MNOC 13 +#define SLAVE_MMAGIC_CFG 14 +#define SLAVE_CPR_CFG 15 +#define SLAVE_MISC_CFG 16 +#define SLAVE_VENUS_THROTTLE_CFG 17 +#define SLAVE_VENUS_CFG 18 +#define SLAVE_VMEM_CFG 19 +#define SLAVE_DSA_CFG 20 +#define SLAVE_MMSS_CLK_CFG 21 +#define SLAVE_DSA_MPU_CFG 22 +#define SLAVE_MNOC_MPU_CFG 23 +#define SLAVE_DISPLAY_CFG 24 +#define SLAVE_DISPLAY_THROTTLE_CFG 25 +#define SLAVE_CAMERA_CFG 26 +#define SLAVE_CAMERA_THROTTLE_CFG 27 +#define SLAVE_GRAPHICS_3D_CFG 28 +#define SLAVE_SMMU_MDP_CFG 29 +#define SLAVE_SMMU_ROT_CFG 30 +#define SLAVE_SMMU_VENUS_CFG 31 +#define SLAVE_SMMU_CPP_CFG 32 +#define SLAVE_SMMU_JPEG_CFG 33 +#define SLAVE_SMMU_VFE_CFG 34 + +/* PNOC */ +#define MASTER_SNOC_PNOC 0 +#define MASTER_SDCC_1 1 +#define MASTER_SDCC_2 2 +#define MASTER_SDCC_4 3 +#define MASTER_USB_HS 4 +#define MASTER_BLSP_1 5 +#define MASTER_BLSP_2 6 +#define MASTER_TSIF 7 +#define SLAVE_PNOC_A1NOC 8 +#define SLAVE_USB_HS 9 +#define SLAVE_SDCC_2 10 +#define SLAVE_SDCC_4 11 +#define SLAVE_TSIF 12 +#define SLAVE_BLSP_2 13 +#define SLAVE_SDCC_1 14 +#define SLAVE_BLSP_1 15 +#define SLAVE_PDM 16 +#define SLAVE_AHB2PHY 17 + +/* SNOC */ +#define MASTER_HMSS 0 +#define MASTER_QDSS_BAM 1 +#define MASTER_SNOC_CFG 2 +#define MASTER_BIMC_SNOC_0 3 +#define MASTER_BIMC_SNOC_1 4 +#define MASTER_A0NOC_SNOC 5 +#define MASTER_A1NOC_SNOC 6 +#define MASTER_A2NOC_SNOC 7 +#define MASTER_QDSS_ETR 8 +#define SLAVE_A0NOC_SNOC 9 +#define SLAVE_A1NOC_SNOC 10 +#define SLAVE_A2NOC_SNOC 11 +#define SLAVE_HMSS 12 +#define SLAVE_LPASS 13 +#define SLAVE_USB3 14 +#define SLAVE_SNOC_BIMC 15 +#define SLAVE_SNOC_CNOC 16 +#define SLAVE_IMEM 17 +#define SLAVE_PIMEM 18 +#define SLAVE_SNOC_VMEM 19 +#define SLAVE_SNOC_PNOC 20 +#define SLAVE_QDSS_STM 21 +#define SLAVE_PCIE_0 22 +#define SLAVE_PCIE_1 23 +#define SLAVE_PCIE_2 24 +#define SLAVE_SERVICE_SNOC 25 + +#endif diff --git a/include/dt-bindings/interconnect/qcom,osm-l3.h b/include/dt-bindings/interconnect/qcom,osm-l3.h new file mode 100644 index 00000000000..61ef649ae56 --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,osm-l3.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 The Linux Foundation. All rights reserved. + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_OSM_L3_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_OSM_L3_H + +#define MASTER_OSM_L3_APPS 0 +#define SLAVE_OSM_L3 1 + +#define MASTER_EPSS_L3_APPS 0 +#define SLAVE_EPSS_L3_SHARED 1 + +#endif diff --git a/include/dt-bindings/interconnect/qcom,sdm845.h b/include/dt-bindings/interconnect/qcom,sdm845.h new file mode 100644 index 00000000000..67b500e2491 --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,sdm845.h @@ -0,0 +1,150 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Qualcomm SDM845 interconnect IDs + * + * Copyright (c) 2018, Linaro Ltd. + * Author: Georgi Djakov <georgi.djakov@linaro.org> + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SDM845_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_SDM845_H + +#define MASTER_A1NOC_CFG 0 +#define MASTER_TSIF 1 +#define MASTER_SDCC_2 2 +#define MASTER_SDCC_4 3 +#define MASTER_UFS_CARD 4 +#define MASTER_UFS_MEM 5 +#define MASTER_PCIE_0 6 +#define SLAVE_A1NOC_SNOC 7 +#define SLAVE_SERVICE_A1NOC 8 +#define SLAVE_ANOC_PCIE_A1NOC_SNOC 9 +#define MASTER_QUP_1 10 + +#define MASTER_A2NOC_CFG 0 +#define MASTER_QDSS_BAM 1 +#define MASTER_CNOC_A2NOC 2 +#define MASTER_CRYPTO 3 +#define MASTER_IPA 4 +#define MASTER_PCIE_1 5 +#define MASTER_QDSS_ETR 6 +#define MASTER_USB3_0 7 +#define MASTER_USB3_1 8 +#define SLAVE_A2NOC_SNOC 9 +#define SLAVE_ANOC_PCIE_SNOC 10 +#define SLAVE_SERVICE_A2NOC 11 +#define MASTER_QUP_2 12 + +#define MASTER_SPDM 0 +#define MASTER_TIC 1 +#define MASTER_SNOC_CNOC 2 +#define MASTER_QDSS_DAP 3 +#define SLAVE_A1NOC_CFG 4 +#define SLAVE_A2NOC_CFG 5 +#define SLAVE_AOP 6 +#define SLAVE_AOSS 7 +#define SLAVE_CAMERA_CFG 8 +#define SLAVE_CLK_CTL 9 +#define SLAVE_CDSP_CFG 10 +#define SLAVE_RBCPR_CX_CFG 11 +#define SLAVE_CRYPTO_0_CFG 12 +#define SLAVE_DCC_CFG 13 +#define SLAVE_CNOC_DDRSS 14 +#define SLAVE_DISPLAY_CFG 15 +#define SLAVE_GLM 16 +#define SLAVE_GFX3D_CFG 17 +#define SLAVE_IMEM_CFG 18 +#define SLAVE_IPA_CFG 19 +#define SLAVE_CNOC_MNOC_CFG 20 +#define SLAVE_PCIE_0_CFG 21 +#define SLAVE_PCIE_1_CFG 22 +#define SLAVE_PDM 23 +#define SLAVE_SOUTH_PHY_CFG 24 +#define SLAVE_PIMEM_CFG 25 +#define SLAVE_PRNG 26 +#define SLAVE_QDSS_CFG 27 +#define SLAVE_BLSP_2 28 +#define SLAVE_BLSP_1 29 +#define SLAVE_SDCC_2 30 +#define SLAVE_SDCC_4 31 +#define SLAVE_SNOC_CFG 32 +#define SLAVE_SPDM_WRAPPER 33 +#define SLAVE_SPSS_CFG 34 +#define SLAVE_TCSR 35 +#define SLAVE_TLMM_NORTH 36 +#define SLAVE_TLMM_SOUTH 37 +#define SLAVE_TSIF 38 +#define SLAVE_UFS_CARD_CFG 39 +#define SLAVE_UFS_MEM_CFG 40 +#define SLAVE_USB3_0 41 +#define SLAVE_USB3_1 42 +#define SLAVE_VENUS_CFG 43 +#define SLAVE_VSENSE_CTRL_CFG 44 +#define SLAVE_CNOC_A2NOC 45 +#define SLAVE_SERVICE_CNOC 46 + +#define MASTER_CNOC_DC_NOC 0 +#define SLAVE_LLCC_CFG 1 +#define SLAVE_MEM_NOC_CFG 2 + +#define MASTER_APPSS_PROC 0 +#define MASTER_GNOC_CFG 1 +#define SLAVE_GNOC_SNOC 2 +#define SLAVE_GNOC_MEM_NOC 3 +#define SLAVE_SERVICE_GNOC 4 + +#define MASTER_TCU_0 0 +#define MASTER_MEM_NOC_CFG 1 +#define MASTER_GNOC_MEM_NOC 2 +#define MASTER_MNOC_HF_MEM_NOC 3 +#define MASTER_MNOC_SF_MEM_NOC 4 +#define MASTER_SNOC_GC_MEM_NOC 5 +#define MASTER_SNOC_SF_MEM_NOC 6 +#define MASTER_GFX3D 7 +#define SLAVE_MSS_PROC_MS_MPU_CFG 8 +#define SLAVE_MEM_NOC_GNOC 9 +#define SLAVE_LLCC 10 +#define SLAVE_MEM_NOC_SNOC 11 +#define SLAVE_SERVICE_MEM_NOC 12 +#define MASTER_LLCC 13 +#define SLAVE_EBI1 14 + +#define MASTER_CNOC_MNOC_CFG 0 +#define MASTER_CAMNOC_HF0 1 +#define MASTER_CAMNOC_HF1 2 +#define MASTER_CAMNOC_SF 3 +#define MASTER_MDP0 4 +#define MASTER_MDP1 5 +#define MASTER_ROTATOR 6 +#define MASTER_VIDEO_P0 7 +#define MASTER_VIDEO_P1 8 +#define MASTER_VIDEO_PROC 9 +#define SLAVE_MNOC_SF_MEM_NOC 10 +#define SLAVE_MNOC_HF_MEM_NOC 11 +#define SLAVE_SERVICE_MNOC 12 +#define MASTER_CAMNOC_HF0_UNCOMP 13 +#define MASTER_CAMNOC_HF1_UNCOMP 14 +#define MASTER_CAMNOC_SF_UNCOMP 15 +#define SLAVE_CAMNOC_UNCOMP 16 + +#define MASTER_SNOC_CFG 0 +#define MASTER_A1NOC_SNOC 1 +#define MASTER_A2NOC_SNOC 2 +#define MASTER_GNOC_SNOC 3 +#define MASTER_MEM_NOC_SNOC 4 +#define MASTER_ANOC_PCIE_SNOC 5 +#define MASTER_PIMEM 6 +#define MASTER_GIC 7 +#define SLAVE_APPSS 8 +#define SLAVE_SNOC_CNOC 9 +#define SLAVE_SNOC_MEM_NOC_GC 10 +#define SLAVE_SNOC_MEM_NOC_SF 11 +#define SLAVE_IMEM 12 +#define SLAVE_PCIE_0 13 +#define SLAVE_PCIE_1 14 +#define SLAVE_PIMEM 15 +#define SLAVE_SERVICE_SNOC 16 +#define SLAVE_QDSS_STM 17 +#define SLAVE_TCU 18 + +#endif diff --git a/include/dt-bindings/phy/phy-qcom-qmp.h b/include/dt-bindings/phy/phy-qcom-qmp.h new file mode 100644 index 00000000000..4edec4c5b22 --- /dev/null +++ b/include/dt-bindings/phy/phy-qcom-qmp.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ +/* + * Qualcomm QMP PHY constants + * + * Copyright (C) 2022 Linaro Limited + */ + +#ifndef _DT_BINDINGS_PHY_QMP +#define _DT_BINDINGS_PHY_QMP + +/* QMP USB4-USB3-DP clocks */ +#define QMP_USB43DP_USB3_PIPE_CLK 0 +#define QMP_USB43DP_DP_LINK_CLK 1 +#define QMP_USB43DP_DP_VCO_DIV_CLK 2 + +/* QMP USB4-USB3-DP PHYs */ +#define QMP_USB43DP_USB3_PHY 0 +#define QMP_USB43DP_DP_PHY 1 + +#endif /* _DT_BINDINGS_PHY_QMP */ diff --git a/include/dt-bindings/phy/phy-qcom-qusb2.h b/include/dt-bindings/phy/phy-qcom-qusb2.h new file mode 100644 index 00000000000..5c5e4d800ca --- /dev/null +++ b/include/dt-bindings/phy/phy-qcom-qusb2.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_QCOM_PHY_QUSB2_H_ +#define _DT_BINDINGS_QCOM_PHY_QUSB2_H_ + +/* PHY HSTX TRIM bit values (24mA to 15mA) */ +#define QUSB2_V2_HSTX_TRIM_24_0_MA 0x0 +#define QUSB2_V2_HSTX_TRIM_23_4_MA 0x1 +#define QUSB2_V2_HSTX_TRIM_22_8_MA 0x2 +#define QUSB2_V2_HSTX_TRIM_22_2_MA 0x3 +#define QUSB2_V2_HSTX_TRIM_21_6_MA 0x4 +#define QUSB2_V2_HSTX_TRIM_21_0_MA 0x5 +#define QUSB2_V2_HSTX_TRIM_20_4_MA 0x6 +#define QUSB2_V2_HSTX_TRIM_19_8_MA 0x7 +#define QUSB2_V2_HSTX_TRIM_19_2_MA 0x8 +#define QUSB2_V2_HSTX_TRIM_18_6_MA 0x9 +#define QUSB2_V2_HSTX_TRIM_18_0_MA 0xa +#define QUSB2_V2_HSTX_TRIM_17_4_MA 0xb +#define QUSB2_V2_HSTX_TRIM_16_8_MA 0xc +#define QUSB2_V2_HSTX_TRIM_16_2_MA 0xd +#define QUSB2_V2_HSTX_TRIM_15_6_MA 0xe +#define QUSB2_V2_HSTX_TRIM_15_0_MA 0xf + +/* PHY PREEMPHASIS bit values */ +#define QUSB2_V2_PREEMPHASIS_NONE 0 +#define QUSB2_V2_PREEMPHASIS_5_PERCENT 1 +#define QUSB2_V2_PREEMPHASIS_10_PERCENT 2 +#define QUSB2_V2_PREEMPHASIS_15_PERCENT 3 + +/* PHY PREEMPHASIS-WIDTH bit values */ +#define QUSB2_V2_PREEMPHASIS_WIDTH_FULL_BIT 0 +#define QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT 1 + +#endif diff --git a/include/dt-bindings/pinctrl/qcom,pmic-gpio.h b/include/dt-bindings/pinctrl/qcom,pmic-gpio.h new file mode 100644 index 00000000000..e5df5ce45a0 --- /dev/null +++ b/include/dt-bindings/pinctrl/qcom,pmic-gpio.h @@ -0,0 +1,164 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides constants for the Qualcomm PMIC GPIO binding. + */ + +#ifndef _DT_BINDINGS_PINCTRL_QCOM_PMIC_GPIO_H +#define _DT_BINDINGS_PINCTRL_QCOM_PMIC_GPIO_H + +#define PMIC_GPIO_PULL_UP_30 0 +#define PMIC_GPIO_PULL_UP_1P5 1 +#define PMIC_GPIO_PULL_UP_31P5 2 +#define PMIC_GPIO_PULL_UP_1P5_30 3 + +#define PMIC_GPIO_STRENGTH_NO 0 +#define PMIC_GPIO_STRENGTH_HIGH 1 +#define PMIC_GPIO_STRENGTH_MED 2 +#define PMIC_GPIO_STRENGTH_LOW 3 + +/* + * Note: PM8018 GPIO3 and GPIO4 are supporting + * only S3 and L2 options (1.8V) + */ +#define PM8018_GPIO_L6 0 +#define PM8018_GPIO_L5 1 +#define PM8018_GPIO_S3 2 +#define PM8018_GPIO_L14 3 +#define PM8018_GPIO_L2 4 +#define PM8018_GPIO_L4 5 +#define PM8018_GPIO_VDD 6 + +/* + * Note: PM8038 GPIO7 and GPIO8 are supporting + * only L11 and L4 options (1.8V) + */ +#define PM8038_GPIO_VPH 0 +#define PM8038_GPIO_BB 1 +#define PM8038_GPIO_L11 2 +#define PM8038_GPIO_L15 3 +#define PM8038_GPIO_L4 4 +#define PM8038_GPIO_L3 5 +#define PM8038_GPIO_L17 6 + +#define PM8058_GPIO_VPH 0 +#define PM8058_GPIO_BB 1 +#define PM8058_GPIO_S3 2 +#define PM8058_GPIO_L3 3 +#define PM8058_GPIO_L7 4 +#define PM8058_GPIO_L6 5 +#define PM8058_GPIO_L5 6 +#define PM8058_GPIO_L2 7 + +/* + * Note: PM8916 GPIO1 and GPIO2 are supporting + * only L2(1.15V) and L5(1.8V) options + */ +#define PM8916_GPIO_VPH 0 +#define PM8916_GPIO_L2 2 +#define PM8916_GPIO_L5 3 + +#define PM8917_GPIO_VPH 0 +#define PM8917_GPIO_S4 2 +#define PM8917_GPIO_L15 3 +#define PM8917_GPIO_L4 4 +#define PM8917_GPIO_L3 5 +#define PM8917_GPIO_L17 6 + +#define PM8921_GPIO_VPH 0 +#define PM8921_GPIO_BB 1 +#define PM8921_GPIO_S4 2 +#define PM8921_GPIO_L15 3 +#define PM8921_GPIO_L4 4 +#define PM8921_GPIO_L3 5 +#define PM8921_GPIO_L17 6 + +/* + * Note: PM8941 gpios from 15 to 18 are supporting + * only S3 and L6 options (1.8V) + */ +#define PM8941_GPIO_VPH 0 +#define PM8941_GPIO_L1 1 +#define PM8941_GPIO_S3 2 +#define PM8941_GPIO_L6 3 + +/* + * Note: PMA8084 gpios from 15 to 18 are supporting + * only S4 and L6 options (1.8V) + */ +#define PMA8084_GPIO_VPH 0 +#define PMA8084_GPIO_L1 1 +#define PMA8084_GPIO_S4 2 +#define PMA8084_GPIO_L6 3 + +#define PM8994_GPIO_VPH 0 +#define PM8994_GPIO_S4 2 +#define PM8994_GPIO_L12 3 + +/* To be used with "function" */ +#define PMIC_GPIO_FUNC_NORMAL "normal" +#define PMIC_GPIO_FUNC_PAIRED "paired" +#define PMIC_GPIO_FUNC_FUNC1 "func1" +#define PMIC_GPIO_FUNC_FUNC2 "func2" +#define PMIC_GPIO_FUNC_FUNC3 "func3" +#define PMIC_GPIO_FUNC_FUNC4 "func4" +#define PMIC_GPIO_FUNC_DTEST1 "dtest1" +#define PMIC_GPIO_FUNC_DTEST2 "dtest2" +#define PMIC_GPIO_FUNC_DTEST3 "dtest3" +#define PMIC_GPIO_FUNC_DTEST4 "dtest4" + +#define PM8038_GPIO1_2_LPG_DRV PMIC_GPIO_FUNC_FUNC1 +#define PM8038_GPIO3_5V_BOOST_EN PMIC_GPIO_FUNC_FUNC1 +#define PM8038_GPIO4_SSBI_ALT_CLK PMIC_GPIO_FUNC_FUNC1 +#define PM8038_GPIO5_6_EXT_REG_EN PMIC_GPIO_FUNC_FUNC1 +#define PM8038_GPIO10_11_EXT_REG_EN PMIC_GPIO_FUNC_FUNC1 +#define PM8038_GPIO6_7_CLK PMIC_GPIO_FUNC_FUNC1 +#define PM8038_GPIO9_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1 +#define PM8038_GPIO6_12_KYPD_DRV PMIC_GPIO_FUNC_FUNC2 + +#define PM8058_GPIO7_8_MP3_CLK PMIC_GPIO_FUNC_FUNC1 +#define PM8058_GPIO7_8_BCLK_19P2MHZ PMIC_GPIO_FUNC_FUNC2 +#define PM8058_GPIO9_26_KYPD_DRV PMIC_GPIO_FUNC_FUNC1 +#define PM8058_GPIO21_23_UART_TX PMIC_GPIO_FUNC_FUNC2 +#define PM8058_GPIO24_26_LPG_DRV PMIC_GPIO_FUNC_FUNC2 +#define PM8058_GPIO33_BCLK_19P2MHZ PMIC_GPIO_FUNC_FUNC1 +#define PM8058_GPIO34_35_MP3_CLK PMIC_GPIO_FUNC_FUNC1 +#define PM8058_GPIO36_BCLK_19P2MHZ PMIC_GPIO_FUNC_FUNC1 +#define PM8058_GPIO37_UPL_OUT PMIC_GPIO_FUNC_FUNC1 +#define PM8058_GPIO37_UART_M_RX PMIC_GPIO_FUNC_FUNC2 +#define PM8058_GPIO38_XO_SLEEP_CLK PMIC_GPIO_FUNC_FUNC1 +#define PM8058_GPIO38_39_CLK_32KHZ PMIC_GPIO_FUNC_FUNC2 +#define PM8058_GPIO39_MP3_CLK PMIC_GPIO_FUNC_FUNC1 +#define PM8058_GPIO40_EXT_BB_EN PMIC_GPIO_FUNC_FUNC1 + +#define PM8916_GPIO1_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1 +#define PM8916_GPIO1_KEYP_DRV PMIC_GPIO_FUNC_FUNC2 +#define PM8916_GPIO2_DIV_CLK PMIC_GPIO_FUNC_FUNC1 +#define PM8916_GPIO2_SLEEP_CLK PMIC_GPIO_FUNC_FUNC2 +#define PM8916_GPIO3_KEYP_DRV PMIC_GPIO_FUNC_FUNC1 +#define PM8916_GPIO4_KEYP_DRV PMIC_GPIO_FUNC_FUNC2 + +#define PM8917_GPIO9_18_KEYP_DRV PMIC_GPIO_FUNC_FUNC1 +#define PM8917_GPIO20_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1 +#define PM8917_GPIO21_23_UART_TX PMIC_GPIO_FUNC_FUNC2 +#define PM8917_GPIO25_26_EXT_REG_EN PMIC_GPIO_FUNC_FUNC1 +#define PM8917_GPIO37_38_XO_SLEEP_CLK PMIC_GPIO_FUNC_FUNC1 +#define PM8917_GPIO37_38_MP3_CLK PMIC_GPIO_FUNC_FUNC2 + +#define PM8941_GPIO9_14_KYPD_DRV PMIC_GPIO_FUNC_FUNC1 +#define PM8941_GPIO15_18_DIV_CLK PMIC_GPIO_FUNC_FUNC1 +#define PM8941_GPIO15_18_SLEEP_CLK PMIC_GPIO_FUNC_FUNC2 +#define PM8941_GPIO23_26_KYPD_DRV PMIC_GPIO_FUNC_FUNC1 +#define PM8941_GPIO23_26_LPG_DRV_HI PMIC_GPIO_FUNC_FUNC2 +#define PM8941_GPIO31_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1 +#define PM8941_GPIO33_36_LPG_DRV_3D PMIC_GPIO_FUNC_FUNC1 +#define PM8941_GPIO33_36_LPG_DRV_HI PMIC_GPIO_FUNC_FUNC2 + +#define PMA8084_GPIO4_5_LPG_DRV PMIC_GPIO_FUNC_FUNC1 +#define PMA8084_GPIO7_10_LPG_DRV PMIC_GPIO_FUNC_FUNC1 +#define PMA8084_GPIO5_14_KEYP_DRV PMIC_GPIO_FUNC_FUNC2 +#define PMA8084_GPIO19_21_KEYP_DRV PMIC_GPIO_FUNC_FUNC2 +#define PMA8084_GPIO15_18_DIV_CLK PMIC_GPIO_FUNC_FUNC1 +#define PMA8084_GPIO15_18_SLEEP_CLK PMIC_GPIO_FUNC_FUNC2 +#define PMA8084_GPIO22_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1 + +#endif diff --git a/include/dt-bindings/pinctrl/qcom,pmic-mpp.h b/include/dt-bindings/pinctrl/qcom,pmic-mpp.h new file mode 100644 index 00000000000..32e66ee7e83 --- /dev/null +++ b/include/dt-bindings/pinctrl/qcom,pmic-mpp.h @@ -0,0 +1,106 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides constants for the Qualcomm PMIC's + * Multi-Purpose Pin binding. + */ + +#ifndef _DT_BINDINGS_PINCTRL_QCOM_PMIC_MPP_H +#define _DT_BINDINGS_PINCTRL_QCOM_PMIC_MPP_H + +/* power-source */ + +/* Digital Input/Output: level [PM8058] */ +#define PM8058_MPP_VPH 0 +#define PM8058_MPP_S3 1 +#define PM8058_MPP_L2 2 +#define PM8058_MPP_L3 3 + +/* Digital Input/Output: level [PM8901] */ +#define PM8901_MPP_MSMIO 0 +#define PM8901_MPP_DIG 1 +#define PM8901_MPP_L5 2 +#define PM8901_MPP_S4 3 +#define PM8901_MPP_VPH 4 + +/* Digital Input/Output: level [PM8921] */ +#define PM8921_MPP_S4 1 +#define PM8921_MPP_L15 3 +#define PM8921_MPP_L17 4 +#define PM8921_MPP_VPH 7 + +/* Digital Input/Output: level [PM8821] */ +#define PM8821_MPP_1P8 0 +#define PM8821_MPP_VPH 7 + +/* Digital Input/Output: level [PM8018] */ +#define PM8018_MPP_L4 0 +#define PM8018_MPP_L14 1 +#define PM8018_MPP_S3 2 +#define PM8018_MPP_L6 3 +#define PM8018_MPP_L2 4 +#define PM8018_MPP_L5 5 +#define PM8018_MPP_VPH 7 + +/* Digital Input/Output: level [PM8038] */ +#define PM8038_MPP_L20 0 +#define PM8038_MPP_L11 1 +#define PM8038_MPP_L5 2 +#define PM8038_MPP_L15 3 +#define PM8038_MPP_L17 4 +#define PM8038_MPP_VPH 7 + +#define PM8841_MPP_VPH 0 +#define PM8841_MPP_S3 2 + +#define PM8916_MPP_VPH 0 +#define PM8916_MPP_L2 2 +#define PM8916_MPP_L5 3 + +#define PM8941_MPP_VPH 0 +#define PM8941_MPP_L1 1 +#define PM8941_MPP_S3 2 +#define PM8941_MPP_L6 3 + +#define PMA8084_MPP_VPH 0 +#define PMA8084_MPP_L1 1 +#define PMA8084_MPP_S4 2 +#define PMA8084_MPP_L6 3 + +#define PM8994_MPP_VPH 0 +/* Only supported for MPP_05-MPP_08 */ +#define PM8994_MPP_L19 1 +#define PM8994_MPP_S4 2 +#define PM8994_MPP_L12 3 + +/* + * Analog Input - Set the source for analog input. + * To be used with "qcom,amux-route" property + */ +#define PMIC_MPP_AMUX_ROUTE_CH5 0 +#define PMIC_MPP_AMUX_ROUTE_CH6 1 +#define PMIC_MPP_AMUX_ROUTE_CH7 2 +#define PMIC_MPP_AMUX_ROUTE_CH8 3 +#define PMIC_MPP_AMUX_ROUTE_ABUS1 4 +#define PMIC_MPP_AMUX_ROUTE_ABUS2 5 +#define PMIC_MPP_AMUX_ROUTE_ABUS3 6 +#define PMIC_MPP_AMUX_ROUTE_ABUS4 7 + +/* Analog Output: level */ +#define PMIC_MPP_AOUT_LVL_1V25 0 +#define PMIC_MPP_AOUT_LVL_1V25_2 1 +#define PMIC_MPP_AOUT_LVL_0V625 2 +#define PMIC_MPP_AOUT_LVL_0V3125 3 +#define PMIC_MPP_AOUT_LVL_MPP 4 +#define PMIC_MPP_AOUT_LVL_ABUS1 5 +#define PMIC_MPP_AOUT_LVL_ABUS2 6 +#define PMIC_MPP_AOUT_LVL_ABUS3 7 + +/* To be used with "function" */ +#define PMIC_MPP_FUNC_NORMAL "normal" +#define PMIC_MPP_FUNC_PAIRED "paired" +#define PMIC_MPP_FUNC_DTEST1 "dtest1" +#define PMIC_MPP_FUNC_DTEST2 "dtest2" +#define PMIC_MPP_FUNC_DTEST3 "dtest3" +#define PMIC_MPP_FUNC_DTEST4 "dtest4" + +#endif diff --git a/include/dt-bindings/power/meson-axg-power.h b/include/dt-bindings/power/meson-axg-power.h deleted file mode 100644 index e5243884b24..00000000000 --- a/include/dt-bindings/power/meson-axg-power.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ -/* - * Copyright (c) 2020 BayLibre, SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ - -#ifndef _DT_BINDINGS_MESON_AXG_POWER_H -#define _DT_BINDINGS_MESON_AXG_POWER_H - -#define PWRC_AXG_VPU_ID 0 -#define PWRC_AXG_ETHERNET_MEM_ID 1 -#define PWRC_AXG_AUDIO_ID 2 - -#endif diff --git a/include/dt-bindings/power/meson-g12a-power.h b/include/dt-bindings/power/meson-g12a-power.h deleted file mode 100644 index bb5e67a842d..00000000000 --- a/include/dt-bindings/power/meson-g12a-power.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ - -#ifndef _DT_BINDINGS_MESON_G12A_POWER_H -#define _DT_BINDINGS_MESON_G12A_POWER_H - -#define PWRC_G12A_VPU_ID 0 -#define PWRC_G12A_ETH_ID 1 - -#endif diff --git a/include/dt-bindings/power/meson-gxbb-power.h b/include/dt-bindings/power/meson-gxbb-power.h deleted file mode 100644 index 1262dac696c..00000000000 --- a/include/dt-bindings/power/meson-gxbb-power.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ - -#ifndef _DT_BINDINGS_MESON_GXBB_POWER_H -#define _DT_BINDINGS_MESON_GXBB_POWER_H - -#define PWRC_GXBB_VPU_ID 0 -#define PWRC_GXBB_ETHERNET_MEM_ID 1 - -#endif diff --git a/include/dt-bindings/power/meson-sm1-power.h b/include/dt-bindings/power/meson-sm1-power.h deleted file mode 100644 index a020ab00c13..00000000000 --- a/include/dt-bindings/power/meson-sm1-power.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ - -#ifndef _DT_BINDINGS_MESON_SM1_POWER_H -#define _DT_BINDINGS_MESON_SM1_POWER_H - -#define PWRC_SM1_VPU_ID 0 -#define PWRC_SM1_NNA_ID 1 -#define PWRC_SM1_USB_ID 2 -#define PWRC_SM1_PCIE_ID 3 -#define PWRC_SM1_GE2D_ID 4 -#define PWRC_SM1_AUDIO_ID 5 -#define PWRC_SM1_ETH_ID 6 - -#endif diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h new file mode 100644 index 00000000000..7f4e2983a4c --- /dev/null +++ b/include/dt-bindings/power/qcom-rpmpd.h @@ -0,0 +1,412 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. */ + +#ifndef _DT_BINDINGS_POWER_QCOM_RPMPD_H +#define _DT_BINDINGS_POWER_QCOM_RPMPD_H + +/* SA8775P Power Domain Indexes */ +#define SA8775P_CX 0 +#define SA8775P_CX_AO 1 +#define SA8775P_DDR 2 +#define SA8775P_EBI 3 +#define SA8775P_GFX 4 +#define SA8775P_LCX 5 +#define SA8775P_LMX 6 +#define SA8775P_MMCX 7 +#define SA8775P_MMCX_AO 8 +#define SA8775P_MSS 9 +#define SA8775P_MX 10 +#define SA8775P_MX_AO 11 +#define SA8775P_MXC 12 +#define SA8775P_MXC_AO 13 +#define SA8775P_NSP0 14 +#define SA8775P_NSP1 15 +#define SA8775P_XO 16 + +/* SDM670 Power Domain Indexes */ +#define SDM670_MX 0 +#define SDM670_MX_AO 1 +#define SDM670_CX 2 +#define SDM670_CX_AO 3 +#define SDM670_LMX 4 +#define SDM670_LCX 5 +#define SDM670_GFX 6 +#define SDM670_MSS 7 + +/* SDM845 Power Domain Indexes */ +#define SDM845_EBI 0 +#define SDM845_MX 1 +#define SDM845_MX_AO 2 +#define SDM845_CX 3 +#define SDM845_CX_AO 4 +#define SDM845_LMX 5 +#define SDM845_LCX 6 +#define SDM845_GFX 7 +#define SDM845_MSS 8 + +/* SDX55 Power Domain Indexes */ +#define SDX55_MSS 0 +#define SDX55_MX 1 +#define SDX55_CX 2 + +/* SDX65 Power Domain Indexes */ +#define SDX65_MSS 0 +#define SDX65_MX 1 +#define SDX65_MX_AO 2 +#define SDX65_CX 3 +#define SDX65_CX_AO 4 +#define SDX65_MXC 5 + +/* SM6350 Power Domain Indexes */ +#define SM6350_CX 0 +#define SM6350_GFX 1 +#define SM6350_LCX 2 +#define SM6350_LMX 3 +#define SM6350_MSS 4 +#define SM6350_MX 5 + +/* SM6350 Power Domain Indexes */ +#define SM6375_VDDCX 0 +#define SM6375_VDDCX_AO 1 +#define SM6375_VDDCX_VFL 2 +#define SM6375_VDDMX 3 +#define SM6375_VDDMX_AO 4 +#define SM6375_VDDMX_VFL 5 +#define SM6375_VDDGX 6 +#define SM6375_VDDGX_AO 7 +#define SM6375_VDD_LPI_CX 8 +#define SM6375_VDD_LPI_MX 9 + +/* SM8150 Power Domain Indexes */ +#define SM8150_MSS 0 +#define SM8150_EBI 1 +#define SM8150_LMX 2 +#define SM8150_LCX 3 +#define SM8150_GFX 4 +#define SM8150_MX 5 +#define SM8150_MX_AO 6 +#define SM8150_CX 7 +#define SM8150_CX_AO 8 +#define SM8150_MMCX 9 +#define SM8150_MMCX_AO 10 + +/* SA8155P is a special case, kept for backwards compatibility */ +#define SA8155P_CX SM8150_CX +#define SA8155P_CX_AO SM8150_CX_AO +#define SA8155P_EBI SM8150_EBI +#define SA8155P_GFX SM8150_GFX +#define SA8155P_MSS SM8150_MSS +#define SA8155P_MX SM8150_MX +#define SA8155P_MX_AO SM8150_MX_AO + +/* SM8250 Power Domain Indexes */ +#define SM8250_CX 0 +#define SM8250_CX_AO 1 +#define SM8250_EBI 2 +#define SM8250_GFX 3 +#define SM8250_LCX 4 +#define SM8250_LMX 5 +#define SM8250_MMCX 6 +#define SM8250_MMCX_AO 7 +#define SM8250_MX 8 +#define SM8250_MX_AO 9 + +/* SM8350 Power Domain Indexes */ +#define SM8350_CX 0 +#define SM8350_CX_AO 1 +#define SM8350_EBI 2 +#define SM8350_GFX 3 +#define SM8350_LCX 4 +#define SM8350_LMX 5 +#define SM8350_MMCX 6 +#define SM8350_MMCX_AO 7 +#define SM8350_MX 8 +#define SM8350_MX_AO 9 +#define SM8350_MXC 10 +#define SM8350_MXC_AO 11 +#define SM8350_MSS 12 + +/* SM8450 Power Domain Indexes */ +#define SM8450_CX 0 +#define SM8450_CX_AO 1 +#define SM8450_EBI 2 +#define SM8450_GFX 3 +#define SM8450_LCX 4 +#define SM8450_LMX 5 +#define SM8450_MMCX 6 +#define SM8450_MMCX_AO 7 +#define SM8450_MX 8 +#define SM8450_MX_AO 9 +#define SM8450_MXC 10 +#define SM8450_MXC_AO 11 +#define SM8450_MSS 12 + +/* SM8550 Power Domain Indexes */ +#define SM8550_CX 0 +#define SM8550_CX_AO 1 +#define SM8550_EBI 2 +#define SM8550_GFX 3 +#define SM8550_LCX 4 +#define SM8550_LMX 5 +#define SM8550_MMCX 6 +#define SM8550_MMCX_AO 7 +#define SM8550_MX 8 +#define SM8550_MX_AO 9 +#define SM8550_MXC 10 +#define SM8550_MXC_AO 11 +#define SM8550_MSS 12 +#define SM8550_NSP 13 + +/* QDU1000/QRU1000 Power Domain Indexes */ +#define QDU1000_EBI 0 +#define QDU1000_MSS 1 +#define QDU1000_CX 2 +#define QDU1000_MX 3 + +/* SC7180 Power Domain Indexes */ +#define SC7180_CX 0 +#define SC7180_CX_AO 1 +#define SC7180_GFX 2 +#define SC7180_MX 3 +#define SC7180_MX_AO 4 +#define SC7180_LMX 5 +#define SC7180_LCX 6 +#define SC7180_MSS 7 + +/* SC7280 Power Domain Indexes */ +#define SC7280_CX 0 +#define SC7280_CX_AO 1 +#define SC7280_EBI 2 +#define SC7280_GFX 3 +#define SC7280_MX 4 +#define SC7280_MX_AO 5 +#define SC7280_LMX 6 +#define SC7280_LCX 7 +#define SC7280_MSS 8 + +/* SC8180X Power Domain Indexes */ +#define SC8180X_CX 0 +#define SC8180X_CX_AO 1 +#define SC8180X_EBI 2 +#define SC8180X_GFX 3 +#define SC8180X_LCX 4 +#define SC8180X_LMX 5 +#define SC8180X_MMCX 6 +#define SC8180X_MMCX_AO 7 +#define SC8180X_MSS 8 +#define SC8180X_MX 9 +#define SC8180X_MX_AO 10 + +/* SC8280XP Power Domain Indexes */ +#define SC8280XP_CX 0 +#define SC8280XP_CX_AO 1 +#define SC8280XP_DDR 2 +#define SC8280XP_EBI 3 +#define SC8280XP_GFX 4 +#define SC8280XP_LCX 5 +#define SC8280XP_LMX 6 +#define SC8280XP_MMCX 7 +#define SC8280XP_MMCX_AO 8 +#define SC8280XP_MSS 9 +#define SC8280XP_MX 10 +#define SC8280XP_MXC 12 +#define SC8280XP_MX_AO 11 +#define SC8280XP_NSP 13 +#define SC8280XP_QPHY 14 +#define SC8280XP_XO 15 + +/* SDM845 Power Domain performance levels */ +#define RPMH_REGULATOR_LEVEL_RETENTION 16 +#define RPMH_REGULATOR_LEVEL_MIN_SVS 48 +#define RPMH_REGULATOR_LEVEL_LOW_SVS_D2 52 +#define RPMH_REGULATOR_LEVEL_LOW_SVS_D1 56 +#define RPMH_REGULATOR_LEVEL_LOW_SVS_D0 60 +#define RPMH_REGULATOR_LEVEL_LOW_SVS 64 +#define RPMH_REGULATOR_LEVEL_LOW_SVS_P1 72 +#define RPMH_REGULATOR_LEVEL_LOW_SVS_L1 80 +#define RPMH_REGULATOR_LEVEL_LOW_SVS_L2 96 +#define RPMH_REGULATOR_LEVEL_SVS 128 +#define RPMH_REGULATOR_LEVEL_SVS_L0 144 +#define RPMH_REGULATOR_LEVEL_SVS_L1 192 +#define RPMH_REGULATOR_LEVEL_SVS_L2 224 +#define RPMH_REGULATOR_LEVEL_NOM 256 +#define RPMH_REGULATOR_LEVEL_NOM_L0 288 +#define RPMH_REGULATOR_LEVEL_NOM_L1 320 +#define RPMH_REGULATOR_LEVEL_NOM_L2 336 +#define RPMH_REGULATOR_LEVEL_TURBO 384 +#define RPMH_REGULATOR_LEVEL_TURBO_L0 400 +#define RPMH_REGULATOR_LEVEL_TURBO_L1 416 +#define RPMH_REGULATOR_LEVEL_TURBO_L2 432 +#define RPMH_REGULATOR_LEVEL_TURBO_L3 448 +#define RPMH_REGULATOR_LEVEL_SUPER_TURBO 464 +#define RPMH_REGULATOR_LEVEL_SUPER_TURBO_NO_CPR 480 + +/* MDM9607 Power Domains */ +#define MDM9607_VDDCX 0 +#define MDM9607_VDDCX_AO 1 +#define MDM9607_VDDCX_VFL 2 +#define MDM9607_VDDMX 3 +#define MDM9607_VDDMX_AO 4 +#define MDM9607_VDDMX_VFL 5 + +/* MSM8226 Power Domain Indexes */ +#define MSM8226_VDDCX 0 +#define MSM8226_VDDCX_AO 1 +#define MSM8226_VDDCX_VFC 2 + +/* MSM8939 Power Domains */ +#define MSM8939_VDDMDCX 0 +#define MSM8939_VDDMDCX_AO 1 +#define MSM8939_VDDMDCX_VFC 2 +#define MSM8939_VDDCX 3 +#define MSM8939_VDDCX_AO 4 +#define MSM8939_VDDCX_VFC 5 +#define MSM8939_VDDMX 6 +#define MSM8939_VDDMX_AO 7 + +/* MSM8916 Power Domain Indexes */ +#define MSM8916_VDDCX 0 +#define MSM8916_VDDCX_AO 1 +#define MSM8916_VDDCX_VFC 2 +#define MSM8916_VDDMX 3 +#define MSM8916_VDDMX_AO 4 + +/* MSM8909 Power Domain Indexes */ +#define MSM8909_VDDCX MSM8916_VDDCX +#define MSM8909_VDDCX_AO MSM8916_VDDCX_AO +#define MSM8909_VDDCX_VFC MSM8916_VDDCX_VFC +#define MSM8909_VDDMX MSM8916_VDDMX +#define MSM8909_VDDMX_AO MSM8916_VDDMX_AO + +/* MSM8917 Power Domain Indexes */ +#define MSM8917_VDDCX 0 +#define MSM8917_VDDCX_AO 1 +#define MSM8917_VDDCX_VFL 2 +#define MSM8917_VDDMX 3 +#define MSM8917_VDDMX_AO 4 + +/* MSM8937 Power Domain Indexes */ +#define MSM8937_VDDCX MSM8917_VDDCX +#define MSM8937_VDDCX_AO MSM8917_VDDCX_AO +#define MSM8937_VDDCX_VFL MSM8917_VDDCX_VFL +#define MSM8937_VDDMX MSM8917_VDDMX +#define MSM8937_VDDMX_AO MSM8917_VDDMX_AO + +/* QM215 Power Domain Indexes */ +#define QM215_VDDCX MSM8917_VDDCX +#define QM215_VDDCX_AO MSM8917_VDDCX_AO +#define QM215_VDDCX_VFL MSM8917_VDDCX_VFL +#define QM215_VDDMX MSM8917_VDDMX +#define QM215_VDDMX_AO MSM8917_VDDMX_AO + +/* MSM8953 Power Domain Indexes */ +#define MSM8953_VDDMD 0 +#define MSM8953_VDDMD_AO 1 +#define MSM8953_VDDCX 2 +#define MSM8953_VDDCX_AO 3 +#define MSM8953_VDDCX_VFL 4 +#define MSM8953_VDDMX 5 +#define MSM8953_VDDMX_AO 6 + +/* MSM8976 Power Domain Indexes */ +#define MSM8976_VDDCX 0 +#define MSM8976_VDDCX_AO 1 +#define MSM8976_VDDCX_VFL 2 +#define MSM8976_VDDMX 3 +#define MSM8976_VDDMX_AO 4 +#define MSM8976_VDDMX_VFL 5 + +/* MSM8994 Power Domain Indexes */ +#define MSM8994_VDDCX 0 +#define MSM8994_VDDCX_AO 1 +#define MSM8994_VDDCX_VFC 2 +#define MSM8994_VDDMX 3 +#define MSM8994_VDDMX_AO 4 +#define MSM8994_VDDGFX 5 +#define MSM8994_VDDGFX_VFC 6 + +/* MSM8996 Power Domain Indexes */ +#define MSM8996_VDDCX 0 +#define MSM8996_VDDCX_AO 1 +#define MSM8996_VDDCX_VFC 2 +#define MSM8996_VDDMX 3 +#define MSM8996_VDDMX_AO 4 +#define MSM8996_VDDSSCX 5 +#define MSM8996_VDDSSCX_VFC 6 + +/* MSM8998 Power Domain Indexes */ +#define MSM8998_VDDCX 0 +#define MSM8998_VDDCX_AO 1 +#define MSM8998_VDDCX_VFL 2 +#define MSM8998_VDDMX 3 +#define MSM8998_VDDMX_AO 4 +#define MSM8998_VDDMX_VFL 5 +#define MSM8998_SSCCX 6 +#define MSM8998_SSCCX_VFL 7 +#define MSM8998_SSCMX 8 +#define MSM8998_SSCMX_VFL 9 + +/* QCS404 Power Domains */ +#define QCS404_VDDMX 0 +#define QCS404_VDDMX_AO 1 +#define QCS404_VDDMX_VFL 2 +#define QCS404_LPICX 3 +#define QCS404_LPICX_VFL 4 +#define QCS404_LPIMX 5 +#define QCS404_LPIMX_VFL 6 + +/* SDM660 Power Domains */ +#define SDM660_VDDCX 0 +#define SDM660_VDDCX_AO 1 +#define SDM660_VDDCX_VFL 2 +#define SDM660_VDDMX 3 +#define SDM660_VDDMX_AO 4 +#define SDM660_VDDMX_VFL 5 +#define SDM660_SSCCX 6 +#define SDM660_SSCCX_VFL 7 +#define SDM660_SSCMX 8 +#define SDM660_SSCMX_VFL 9 + +/* SM6115 Power Domains */ +#define SM6115_VDDCX 0 +#define SM6115_VDDCX_AO 1 +#define SM6115_VDDCX_VFL 2 +#define SM6115_VDDMX 3 +#define SM6115_VDDMX_AO 4 +#define SM6115_VDDMX_VFL 5 +#define SM6115_VDD_LPI_CX 6 +#define SM6115_VDD_LPI_MX 7 + +/* SM6125 Power Domains */ +#define SM6125_VDDCX 0 +#define SM6125_VDDCX_AO 1 +#define SM6125_VDDCX_VFL 2 +#define SM6125_VDDMX 3 +#define SM6125_VDDMX_AO 4 +#define SM6125_VDDMX_VFL 5 + +/* QCM2290 Power Domains */ +#define QCM2290_VDDCX 0 +#define QCM2290_VDDCX_AO 1 +#define QCM2290_VDDCX_VFL 2 +#define QCM2290_VDDMX 3 +#define QCM2290_VDDMX_AO 4 +#define QCM2290_VDDMX_VFL 5 +#define QCM2290_VDD_LPI_CX 6 +#define QCM2290_VDD_LPI_MX 7 + +/* RPM SMD Power Domain performance levels */ +#define RPM_SMD_LEVEL_RETENTION 16 +#define RPM_SMD_LEVEL_RETENTION_PLUS 32 +#define RPM_SMD_LEVEL_MIN_SVS 48 +#define RPM_SMD_LEVEL_LOW_SVS 64 +#define RPM_SMD_LEVEL_SVS 128 +#define RPM_SMD_LEVEL_SVS_PLUS 192 +#define RPM_SMD_LEVEL_NOM 256 +#define RPM_SMD_LEVEL_NOM_PLUS 320 +#define RPM_SMD_LEVEL_TURBO 384 +#define RPM_SMD_LEVEL_TURBO_NO_CPR 416 +#define RPM_SMD_LEVEL_TURBO_HIGH 448 +#define RPM_SMD_LEVEL_BINNING 512 + +#endif diff --git a/include/dt-bindings/regulator/qcom,rpmh-regulator.h b/include/dt-bindings/regulator/qcom,rpmh-regulator.h new file mode 100644 index 00000000000..86713dcf9e0 --- /dev/null +++ b/include/dt-bindings/regulator/qcom,rpmh-regulator.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. */ + +#ifndef __QCOM_RPMH_REGULATOR_H +#define __QCOM_RPMH_REGULATOR_H + +/* + * These mode constants may be used to specify modes for various RPMh regulator + * device tree properties (e.g. regulator-initial-mode). Each type of regulator + * supports a subset of the possible modes. + * + * %RPMH_REGULATOR_MODE_RET: Retention mode in which only an extremely small + * load current is allowed. This mode is supported + * by LDO and SMPS type regulators. + * %RPMH_REGULATOR_MODE_LPM: Low power mode in which a small load current is + * allowed. This mode corresponds to PFM for SMPS + * and BOB type regulators. This mode is supported + * by LDO, HFSMPS, BOB, and PMIC4 FTSMPS type + * regulators. + * %RPMH_REGULATOR_MODE_AUTO: Auto mode in which the regulator hardware + * automatically switches between LPM and HPM based + * upon the real-time load current. This mode is + * supported by HFSMPS, BOB, and PMIC4 FTSMPS type + * regulators. + * %RPMH_REGULATOR_MODE_HPM: High power mode in which the full rated current + * of the regulator is allowed. This mode + * corresponds to PWM for SMPS and BOB type + * regulators. This mode is supported by all types + * of regulators. + */ +#define RPMH_REGULATOR_MODE_RET 0 +#define RPMH_REGULATOR_MODE_LPM 1 +#define RPMH_REGULATOR_MODE_AUTO 2 +#define RPMH_REGULATOR_MODE_HPM 3 + +#endif diff --git a/include/dt-bindings/reset/altr,rst-mgr-agx5.h b/include/dt-bindings/reset/altr,rst-mgr-agx5.h new file mode 100644 index 00000000000..1dba270aed4 --- /dev/null +++ b/include/dt-bindings/reset/altr,rst-mgr-agx5.h @@ -0,0 +1,80 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2024 Intel Corporation. All rights reserved + */ + +#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_AGX_EDGE_H +#define _DT_BINDINGS_RESET_ALTR_RST_MGR_AGX_EDGE_H + +/* PER0MODRST */ +#define EMAC0_RESET 0 +#define EMAC1_RESET 1 +#define EMAC2_RESET 2 +#define USB0_RESET 3 +#define USB1_RESET 4 +#define NAND_RESET 5 +#define COMBOPHY_RESET 6 +#define SDMMC_RESET 7 +#define EMAC0_OCP_RESET 8 +#define EMAC1_OCP_RESET 9 +#define EMAC2_OCP_RESET 10 +#define USB0_OCP_RESET 11 +#define USB1_OCP_RESET 12 +#define NAND_OCP_RESET 13 +/* 14 is empty */ +#define SDMMC_OCP_RESET 15 +#define DMA_RESET 16 +#define SPIM0_RESET 17 +#define SPIM1_RESET 18 +#define SPIS0_RESET 19 +#define SPIS1_RESET 20 +#define DMA_OCP_RESET 21 +#define EMAC_PTP_RESET 22 +/* 23 is empty*/ +#define DMAIF0_RESET 24 +#define DMAIF1_RESET 25 +#define DMAIF2_RESET 26 +#define DMAIF3_RESET 27 +#define DMAIF4_RESET 28 +#define DMAIF5_RESET 29 +#define DMAIF6_RESET 30 +#define DMAIF7_RESET 31 + +/* PER1MODRST */ +#define WATCHDOG0_RESET 32 +#define WATCHDOG1_RESET 33 +#define WATCHDOG2_RESET 34 +#define WATCHDOG3_RESET 35 +#define L4SYSTIMER0_RESET 36 +#define L4SYSTIMER1_RESET 37 +#define SPTIMER0_RESET 38 +#define SPTIMER1_RESET 39 +#define I2C0_RESET 40 +#define I2C1_RESET 41 +#define I2C2_RESET 42 +#define I2C3_RESET 43 +#define I2C4_RESET 44 +#define I3C0_RESET 45 +#define I3C1_RESET 46 +/* 47 is empty */ +#define UART0_RESET 48 +#define UART1_RESET 49 +/* 50-55 is empty */ +#define GPIO0_RESET 56 +#define GPIO1_RESET 57 +#define WATCHDOG4_RESET 58 +/* 59-63 is empty */ + +/* BRGMODRST */ +#define SOC2FPGA_RESET 64 +#define LWHPS2FPGA_RESET 65 +#define FPGA2SOC_RESET 66 +#define F2SSDRAM_RESET 67 +/* 68-69 is empty */ +#define DDRSCH_RESET 70 +/* 71-95 is empty */ + +/* DBGMODRST */ +#define DBG_RESET 192 + +#endif diff --git a/include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h b/include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h deleted file mode 100644 index 1ef807856cb..00000000000 --- a/include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0 OR MIT) - * - * Copyright (c) 2018 Baylibre SAS. - * Author: Jerome Brunet <jbrunet@baylibre.com> - */ - -#ifndef _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H -#define _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H - -#define AXG_ARB_TODDR_A 0 -#define AXG_ARB_TODDR_B 1 -#define AXG_ARB_TODDR_C 2 -#define AXG_ARB_FRDDR_A 3 -#define AXG_ARB_FRDDR_B 4 -#define AXG_ARB_FRDDR_C 5 -#define AXG_ARB_TODDR_D 6 -#define AXG_ARB_FRDDR_D 7 - -#endif /* _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H */ diff --git a/include/dt-bindings/reset/amlogic,meson-axg-reset.h b/include/dt-bindings/reset/amlogic,meson-axg-reset.h deleted file mode 100644 index 0f2e0fe45ca..00000000000 --- a/include/dt-bindings/reset/amlogic,meson-axg-reset.h +++ /dev/null @@ -1,123 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ -/* - * Copyright (c) 2016 BayLibre, SAS. - * Author: Neil Armstrong <narmstrong@baylibre.com> - * - * Copyright (c) 2017 Amlogic, inc. - * Author: Yixun Lan <yixun.lan@amlogic.com> - * - */ - -#ifndef _DT_BINDINGS_AMLOGIC_MESON_AXG_RESET_H -#define _DT_BINDINGS_AMLOGIC_MESON_AXG_RESET_H - -/* RESET0 */ -#define RESET_HIU 0 -#define RESET_PCIE_A 1 -#define RESET_PCIE_B 2 -#define RESET_DDR_TOP 3 -/* 4 */ -#define RESET_VIU 5 -#define RESET_PCIE_PHY 6 -#define RESET_PCIE_APB 7 -/* 8 */ -/* 9 */ -#define RESET_VENC 10 -#define RESET_ASSIST 11 -/* 12 */ -#define RESET_VCBUS 13 -/* 14 */ -/* 15 */ -#define RESET_GIC 16 -#define RESET_CAPB3_DECODE 17 -/* 18-21 */ -#define RESET_SYS_CPU_CAPB3 22 -#define RESET_CBUS_CAPB3 23 -#define RESET_AHB_CNTL 24 -#define RESET_AHB_DATA 25 -#define RESET_VCBUS_CLK81 26 -#define RESET_MMC 27 -/* 28-31 */ -/* RESET1 */ -/* 32 */ -/* 33 */ -#define RESET_USB_OTG 34 -#define RESET_DDR 35 -#define RESET_AO_RESET 36 -/* 37 */ -#define RESET_AHB_SRAM 38 -/* 39 */ -/* 40 */ -#define RESET_DMA 41 -#define RESET_ISA 42 -#define RESET_ETHERNET 43 -/* 44 */ -#define RESET_SD_EMMC_B 45 -#define RESET_SD_EMMC_C 46 -#define RESET_ROM_BOOT 47 -#define RESET_SYS_CPU_0 48 -#define RESET_SYS_CPU_1 49 -#define RESET_SYS_CPU_2 50 -#define RESET_SYS_CPU_3 51 -#define RESET_SYS_CPU_CORE_0 52 -#define RESET_SYS_CPU_CORE_1 53 -#define RESET_SYS_CPU_CORE_2 54 -#define RESET_SYS_CPU_CORE_3 55 -#define RESET_SYS_PLL_DIV 56 -#define RESET_SYS_CPU_AXI 57 -#define RESET_SYS_CPU_L2 58 -#define RESET_SYS_CPU_P 59 -#define RESET_SYS_CPU_MBIST 60 -/* 61-63 */ -/* RESET2 */ -/* 64 */ -/* 65 */ -#define RESET_AUDIO 66 -/* 67 */ -#define RESET_MIPI_HOST 68 -#define RESET_AUDIO_LOCKER 69 -#define RESET_GE2D 70 -/* 71-76 */ -#define RESET_AO_CPU_RESET 77 -/* 78-95 */ -/* RESET3 */ -#define RESET_RING_OSCILLATOR 96 -/* 97-127 */ -/* RESET4 */ -/* 128 */ -/* 129 */ -#define RESET_MIPI_PHY 130 -/* 131-140 */ -#define RESET_VENCL 141 -#define RESET_I2C_MASTER_2 142 -#define RESET_I2C_MASTER_1 143 -/* 144-159 */ -/* RESET5 */ -/* 160-191 */ -/* RESET6 */ -#define RESET_PERIPHS_GENERAL 192 -#define RESET_PERIPHS_SPICC 193 -/* 194 */ -/* 195 */ -#define RESET_PERIPHS_I2C_MASTER_0 196 -/* 197-200 */ -#define RESET_PERIPHS_UART_0 201 -#define RESET_PERIPHS_UART_1 202 -/* 203-204 */ -#define RESET_PERIPHS_SPI_0 205 -#define RESET_PERIPHS_I2C_MASTER_3 206 -/* 207-223 */ -/* RESET7 */ -#define RESET_USB_DDR_0 224 -#define RESET_USB_DDR_1 225 -#define RESET_USB_DDR_2 226 -#define RESET_USB_DDR_3 227 -/* 228 */ -#define RESET_DEVICE_MMC_ARB 229 -/* 230 */ -#define RESET_VID_LOCK 231 -#define RESET_A9_DMC_PIPEL 232 -#define RESET_DMC_VPU_PIPEL 233 -/* 234-255 */ - -#endif diff --git a/include/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h b/include/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h deleted file mode 100644 index f805129ca7a..00000000000 --- a/include/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h +++ /dev/null @@ -1,53 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2019 BayLibre, SAS. - * Author: Jerome Brunet <jbrunet@baylibre.com> - * - */ - -#ifndef _DT_BINDINGS_AMLOGIC_MESON_G12A_AUDIO_RESET_H -#define _DT_BINDINGS_AMLOGIC_MESON_G12A_AUDIO_RESET_H - -#define AUD_RESET_PDM 0 -#define AUD_RESET_TDMIN_A 1 -#define AUD_RESET_TDMIN_B 2 -#define AUD_RESET_TDMIN_C 3 -#define AUD_RESET_TDMIN_LB 4 -#define AUD_RESET_LOOPBACK 5 -#define AUD_RESET_TODDR_A 6 -#define AUD_RESET_TODDR_B 7 -#define AUD_RESET_TODDR_C 8 -#define AUD_RESET_FRDDR_A 9 -#define AUD_RESET_FRDDR_B 10 -#define AUD_RESET_FRDDR_C 11 -#define AUD_RESET_TDMOUT_A 12 -#define AUD_RESET_TDMOUT_B 13 -#define AUD_RESET_TDMOUT_C 14 -#define AUD_RESET_SPDIFOUT 15 -#define AUD_RESET_SPDIFOUT_B 16 -#define AUD_RESET_SPDIFIN 17 -#define AUD_RESET_EQDRC 18 -#define AUD_RESET_RESAMPLE 19 -#define AUD_RESET_DDRARB 20 -#define AUD_RESET_POWDET 21 -#define AUD_RESET_TORAM 22 -#define AUD_RESET_TOACODEC 23 -#define AUD_RESET_TOHDMITX 24 -#define AUD_RESET_CLKTREE 25 - -/* SM1 added resets */ -#define AUD_RESET_RESAMPLE_B 26 -#define AUD_RESET_TOVAD 27 -#define AUD_RESET_LOCKER 28 -#define AUD_RESET_SPDIFIN_LB 29 -#define AUD_RESET_FRATV 30 -#define AUD_RESET_FRHDMIRX 31 -#define AUD_RESET_FRDDR_D 32 -#define AUD_RESET_TODDR_D 33 -#define AUD_RESET_LOOPBACK_B 34 -#define AUD_RESET_EARCTX 35 -#define AUD_RESET_EARCRX 36 -#define AUD_RESET_FRDDR_E 37 -#define AUD_RESET_TODDR_E 38 - -#endif diff --git a/include/dt-bindings/reset/amlogic,meson-g12a-reset.h b/include/dt-bindings/reset/amlogic,meson-g12a-reset.h deleted file mode 100644 index 6d487c5eba2..00000000000 --- a/include/dt-bindings/reset/amlogic,meson-g12a-reset.h +++ /dev/null @@ -1,137 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ -/* - * Copyright (c) 2019 BayLibre, SAS. - * Author: Jerome Brunet <jbrunet@baylibre.com> - * - */ - -#ifndef _DT_BINDINGS_AMLOGIC_MESON_G12A_RESET_H -#define _DT_BINDINGS_AMLOGIC_MESON_G12A_RESET_H - -/* RESET0 */ -#define RESET_HIU 0 -/* 1 */ -#define RESET_DOS 2 -/* 3-4 */ -#define RESET_VIU 5 -#define RESET_AFIFO 6 -#define RESET_VID_PLL_DIV 7 -/* 8-9 */ -#define RESET_VENC 10 -#define RESET_ASSIST 11 -#define RESET_PCIE_CTRL_A 12 -#define RESET_VCBUS 13 -#define RESET_PCIE_PHY 14 -#define RESET_PCIE_APB 15 -#define RESET_GIC 16 -#define RESET_CAPB3_DECODE 17 -/* 18 */ -#define RESET_HDMITX_CAPB3 19 -#define RESET_DVALIN_CAPB3 20 -#define RESET_DOS_CAPB3 21 -/* 22 */ -#define RESET_CBUS_CAPB3 23 -#define RESET_AHB_CNTL 24 -#define RESET_AHB_DATA 25 -#define RESET_VCBUS_CLK81 26 -/* 27-31 */ -/* RESET1 */ -/* 32 */ -#define RESET_DEMUX 33 -#define RESET_USB 34 -#define RESET_DDR 35 -/* 36 */ -#define RESET_BT656 37 -#define RESET_AHB_SRAM 38 -/* 39 */ -#define RESET_PARSER 40 -/* 41 */ -#define RESET_ISA 42 -#define RESET_ETHERNET 43 -#define RESET_SD_EMMC_A 44 -#define RESET_SD_EMMC_B 45 -#define RESET_SD_EMMC_C 46 -/* 47 */ -#define RESET_USB_PHY20 48 -#define RESET_USB_PHY21 49 -/* 50-60 */ -#define RESET_AUDIO_CODEC 61 -/* 62-63 */ -/* RESET2 */ -/* 64 */ -#define RESET_AUDIO 65 -#define RESET_HDMITX_PHY 66 -/* 67 */ -#define RESET_MIPI_DSI_HOST 68 -#define RESET_ALOCKER 69 -#define RESET_GE2D 70 -#define RESET_PARSER_REG 71 -#define RESET_PARSER_FETCH 72 -#define RESET_CTL 73 -#define RESET_PARSER_TOP 74 -/* 75-77 */ -#define RESET_DVALIN 78 -#define RESET_HDMITX 79 -/* 80-95 */ -/* RESET3 */ -/* 96-95 */ -#define RESET_DEMUX_TOP 105 -#define RESET_DEMUX_DES_PL 106 -#define RESET_DEMUX_S2P_0 107 -#define RESET_DEMUX_S2P_1 108 -#define RESET_DEMUX_0 109 -#define RESET_DEMUX_1 110 -#define RESET_DEMUX_2 111 -/* 112-127 */ -/* RESET4 */ -/* 128-129 */ -#define RESET_MIPI_DSI_PHY 130 -/* 131-132 */ -#define RESET_RDMA 133 -#define RESET_VENCI 134 -#define RESET_VENCP 135 -/* 136 */ -#define RESET_VDAC 137 -/* 138-139 */ -#define RESET_VDI6 140 -#define RESET_VENCL 141 -#define RESET_I2C_M1 142 -#define RESET_I2C_M2 143 -/* 144-159 */ -/* RESET5 */ -/* 160-191 */ -/* RESET6 */ -#define RESET_GEN 192 -#define RESET_SPICC0 193 -#define RESET_SC 194 -#define RESET_SANA_3 195 -#define RESET_I2C_M0 196 -#define RESET_TS_PLL 197 -#define RESET_SPICC1 198 -#define RESET_STREAM 199 -#define RESET_TS_CPU 200 -#define RESET_UART0 201 -#define RESET_UART1_2 202 -#define RESET_ASYNC0 203 -#define RESET_ASYNC1 204 -#define RESET_SPIFC0 205 -#define RESET_I2C_M3 206 -/* 207-223 */ -/* RESET7 */ -#define RESET_USB_DDR_0 224 -#define RESET_USB_DDR_1 225 -#define RESET_USB_DDR_2 226 -#define RESET_USB_DDR_3 227 -#define RESET_TS_GPU 228 -#define RESET_DEVICE_MMC_ARB 229 -#define RESET_DVALIN_DMC_PIPL 230 -#define RESET_VID_LOCK 231 -#define RESET_NIC_DMC_PIPL 232 -#define RESET_DMC_VPU_PIPL 233 -#define RESET_GE2D_DMC_PIPL 234 -#define RESET_HCODEC_DMC_PIPL 235 -#define RESET_WAVE420_DMC_PIPL 236 -#define RESET_HEVCF_DMC_PIPL 237 -/* 238-255 */ - -#endif diff --git a/include/dt-bindings/reset/amlogic,meson-gxbb-reset.h b/include/dt-bindings/reset/amlogic,meson-gxbb-reset.h deleted file mode 100644 index 883bfd3bcba..00000000000 --- a/include/dt-bindings/reset/amlogic,meson-gxbb-reset.h +++ /dev/null @@ -1,161 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ -/* - * Copyright (c) 2016 BayLibre, SAS. - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ -#ifndef _DT_BINDINGS_AMLOGIC_MESON_GXBB_RESET_H -#define _DT_BINDINGS_AMLOGIC_MESON_GXBB_RESET_H - -/* RESET0 */ -#define RESET_HIU 0 -/* 1 */ -#define RESET_DOS_RESET 2 -#define RESET_DDR_TOP 3 -#define RESET_DCU_RESET 4 -#define RESET_VIU 5 -#define RESET_AIU 6 -#define RESET_VID_PLL_DIV 7 -/* 8 */ -#define RESET_PMUX 9 -#define RESET_VENC 10 -#define RESET_ASSIST 11 -#define RESET_AFIFO2 12 -#define RESET_VCBUS 13 -/* 14 */ -/* 15 */ -#define RESET_GIC 16 -#define RESET_CAPB3_DECODE 17 -#define RESET_NAND_CAPB3 18 -#define RESET_HDMITX_CAPB3 19 -#define RESET_MALI_CAPB3 20 -#define RESET_DOS_CAPB3 21 -#define RESET_SYS_CPU_CAPB3 22 -#define RESET_CBUS_CAPB3 23 -#define RESET_AHB_CNTL 24 -#define RESET_AHB_DATA 25 -#define RESET_VCBUS_CLK81 26 -#define RESET_MMC 27 -#define RESET_MIPI_0 28 -#define RESET_MIPI_1 29 -#define RESET_MIPI_2 30 -#define RESET_MIPI_3 31 -/* RESET1 */ -#define RESET_CPPM 32 -#define RESET_DEMUX 33 -#define RESET_USB_OTG 34 -#define RESET_DDR 35 -#define RESET_AO_RESET 36 -#define RESET_BT656 37 -#define RESET_AHB_SRAM 38 -/* 39 */ -#define RESET_PARSER 40 -#define RESET_BLKMV 41 -#define RESET_ISA 42 -#define RESET_ETHERNET 43 -#define RESET_SD_EMMC_A 44 -#define RESET_SD_EMMC_B 45 -#define RESET_SD_EMMC_C 46 -#define RESET_ROM_BOOT 47 -#define RESET_SYS_CPU_0 48 -#define RESET_SYS_CPU_1 49 -#define RESET_SYS_CPU_2 50 -#define RESET_SYS_CPU_3 51 -#define RESET_SYS_CPU_CORE_0 52 -#define RESET_SYS_CPU_CORE_1 53 -#define RESET_SYS_CPU_CORE_2 54 -#define RESET_SYS_CPU_CORE_3 55 -#define RESET_SYS_PLL_DIV 56 -#define RESET_SYS_CPU_AXI 57 -#define RESET_SYS_CPU_L2 58 -#define RESET_SYS_CPU_P 59 -#define RESET_SYS_CPU_MBIST 60 -#define RESET_ACODEC 61 -/* 62 */ -/* 63 */ -/* RESET2 */ -#define RESET_VD_RMEM 64 -#define RESET_AUDIN 65 -#define RESET_HDMI_TX 66 -/* 67 */ -/* 68 */ -/* 69 */ -#define RESET_GE2D 70 -#define RESET_PARSER_REG 71 -#define RESET_PARSER_FETCH 72 -#define RESET_PARSER_CTL 73 -#define RESET_PARSER_TOP 74 -/* 75 */ -/* 76 */ -#define RESET_AO_CPU_RESET 77 -#define RESET_MALI 78 -#define RESET_HDMI_SYSTEM_RESET 79 -/* 80-95 */ -/* RESET3 */ -#define RESET_RING_OSCILLATOR 96 -#define RESET_SYS_CPU 97 -#define RESET_EFUSE 98 -#define RESET_SYS_CPU_BVCI 99 -#define RESET_AIFIFO 100 -#define RESET_TVFE 101 -#define RESET_AHB_BRIDGE_CNTL 102 -/* 103 */ -#define RESET_AUDIO_DAC 104 -#define RESET_DEMUX_TOP 105 -#define RESET_DEMUX_DES 106 -#define RESET_DEMUX_S2P_0 107 -#define RESET_DEMUX_S2P_1 108 -#define RESET_DEMUX_RESET_0 109 -#define RESET_DEMUX_RESET_1 110 -#define RESET_DEMUX_RESET_2 111 -/* 112-127 */ -/* RESET4 */ -/* 128 */ -/* 129 */ -/* 130 */ -/* 131 */ -#define RESET_DVIN_RESET 132 -#define RESET_RDMA 133 -#define RESET_VENCI 134 -#define RESET_VENCP 135 -/* 136 */ -#define RESET_VDAC 137 -#define RESET_RTC 138 -/* 139 */ -#define RESET_VDI6 140 -#define RESET_VENCL 141 -#define RESET_I2C_MASTER_2 142 -#define RESET_I2C_MASTER_1 143 -/* 144-159 */ -/* RESET5 */ -/* 160-191 */ -/* RESET6 */ -#define RESET_PERIPHS_GENERAL 192 -#define RESET_PERIPHS_SPICC 193 -#define RESET_PERIPHS_SMART_CARD 194 -#define RESET_PERIPHS_SAR_ADC 195 -#define RESET_PERIPHS_I2C_MASTER_0 196 -#define RESET_SANA 197 -/* 198 */ -#define RESET_PERIPHS_STREAM_INTERFACE 199 -#define RESET_PERIPHS_SDIO 200 -#define RESET_PERIPHS_UART_0 201 -#define RESET_PERIPHS_UART_1_2 202 -#define RESET_PERIPHS_ASYNC_0 203 -#define RESET_PERIPHS_ASYNC_1 204 -#define RESET_PERIPHS_SPI_0 205 -#define RESET_PERIPHS_SDHC 206 -#define RESET_UART_SLIP 207 -/* 208-223 */ -/* RESET7 */ -#define RESET_USB_DDR_0 224 -#define RESET_USB_DDR_1 225 -#define RESET_USB_DDR_2 226 -#define RESET_USB_DDR_3 227 -/* 228 */ -#define RESET_DEVICE_MMC_ARB 229 -/* 230 */ -#define RESET_VID_LOCK 231 -#define RESET_A9_DMC_PIPEL 232 -/* 233-255 */ - -#endif diff --git a/include/dt-bindings/reset/qcom,gcc-msm8916.h b/include/dt-bindings/reset/qcom,gcc-msm8916.h new file mode 100644 index 00000000000..1f9be10872d --- /dev/null +++ b/include/dt-bindings/reset/qcom,gcc-msm8916.h @@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright 2015 Linaro Limited + */ + +#ifndef _DT_BINDINGS_RESET_MSM_GCC_8916_H +#define _DT_BINDINGS_RESET_MSM_GCC_8916_H + +#define GCC_BLSP1_BCR 0 +#define GCC_BLSP1_QUP1_BCR 1 +#define GCC_BLSP1_UART1_BCR 2 +#define GCC_BLSP1_QUP2_BCR 3 +#define GCC_BLSP1_UART2_BCR 4 +#define GCC_BLSP1_QUP3_BCR 5 +#define GCC_BLSP1_QUP4_BCR 6 +#define GCC_BLSP1_QUP5_BCR 7 +#define GCC_BLSP1_QUP6_BCR 8 +#define GCC_IMEM_BCR 9 +#define GCC_SMMU_BCR 10 +#define GCC_APSS_TCU_BCR 11 +#define GCC_SMMU_XPU_BCR 12 +#define GCC_PCNOC_TBU_BCR 13 +#define GCC_PRNG_BCR 14 +#define GCC_BOOT_ROM_BCR 15 +#define GCC_CRYPTO_BCR 16 +#define GCC_SEC_CTRL_BCR 17 +#define GCC_AUDIO_CORE_BCR 18 +#define GCC_ULT_AUDIO_BCR 19 +#define GCC_DEHR_BCR 20 +#define GCC_SYSTEM_NOC_BCR 21 +#define GCC_PCNOC_BCR 22 +#define GCC_TCSR_BCR 23 +#define GCC_QDSS_BCR 24 +#define GCC_DCD_BCR 25 +#define GCC_MSG_RAM_BCR 26 +#define GCC_MPM_BCR 27 +#define GCC_SPMI_BCR 28 +#define GCC_SPDM_BCR 29 +#define GCC_MM_SPDM_BCR 30 +#define GCC_BIMC_BCR 31 +#define GCC_RBCPR_BCR 32 +#define GCC_TLMM_BCR 33 +#define GCC_USB_HS_BCR 34 +#define GCC_USB2A_PHY_BCR 35 +#define GCC_SDCC1_BCR 36 +#define GCC_SDCC2_BCR 37 +#define GCC_PDM_BCR 38 +#define GCC_SNOC_BUS_TIMEOUT0_BCR 39 +#define GCC_PCNOC_BUS_TIMEOUT0_BCR 40 +#define GCC_PCNOC_BUS_TIMEOUT1_BCR 41 +#define GCC_PCNOC_BUS_TIMEOUT2_BCR 42 +#define GCC_PCNOC_BUS_TIMEOUT3_BCR 43 +#define GCC_PCNOC_BUS_TIMEOUT4_BCR 44 +#define GCC_PCNOC_BUS_TIMEOUT5_BCR 45 +#define GCC_PCNOC_BUS_TIMEOUT6_BCR 46 +#define GCC_PCNOC_BUS_TIMEOUT7_BCR 47 +#define GCC_PCNOC_BUS_TIMEOUT8_BCR 48 +#define GCC_PCNOC_BUS_TIMEOUT9_BCR 49 +#define GCC_MMSS_BCR 50 +#define GCC_VENUS0_BCR 51 +#define GCC_MDSS_BCR 52 +#define GCC_CAMSS_PHY0_BCR 53 +#define GCC_CAMSS_CSI0_BCR 54 +#define GCC_CAMSS_CSI0PHY_BCR 55 +#define GCC_CAMSS_CSI0RDI_BCR 56 +#define GCC_CAMSS_CSI0PIX_BCR 57 +#define GCC_CAMSS_PHY1_BCR 58 +#define GCC_CAMSS_CSI1_BCR 59 +#define GCC_CAMSS_CSI1PHY_BCR 60 +#define GCC_CAMSS_CSI1RDI_BCR 61 +#define GCC_CAMSS_CSI1PIX_BCR 62 +#define GCC_CAMSS_ISPIF_BCR 63 +#define GCC_CAMSS_CCI_BCR 64 +#define GCC_CAMSS_MCLK0_BCR 65 +#define GCC_CAMSS_MCLK1_BCR 66 +#define GCC_CAMSS_GP0_BCR 67 +#define GCC_CAMSS_GP1_BCR 68 +#define GCC_CAMSS_TOP_BCR 69 +#define GCC_CAMSS_MICRO_BCR 70 +#define GCC_CAMSS_JPEG_BCR 71 +#define GCC_CAMSS_VFE_BCR 72 +#define GCC_CAMSS_CSI_VFE0_BCR 73 +#define GCC_OXILI_BCR 74 +#define GCC_GMEM_BCR 75 +#define GCC_CAMSS_AHB_BCR 76 +#define GCC_MDP_TBU_BCR 77 +#define GCC_GFX_TBU_BCR 78 +#define GCC_GFX_TCU_BCR 79 +#define GCC_MSS_TBU_AXI_BCR 80 +#define GCC_MSS_TBU_GSS_AXI_BCR 81 +#define GCC_MSS_TBU_Q6_AXI_BCR 82 +#define GCC_GTCU_AHB_BCR 83 +#define GCC_SMMU_CFG_BCR 84 +#define GCC_VFE_TBU_BCR 85 +#define GCC_VENUS_TBU_BCR 86 +#define GCC_JPEG_TBU_BCR 87 +#define GCC_PRONTO_TBU_BCR 88 +#define GCC_SMMU_CATS_BCR 89 + +#endif diff --git a/include/dt-bindings/reset/qcom,sdm845-aoss.h b/include/dt-bindings/reset/qcom,sdm845-aoss.h new file mode 100644 index 00000000000..476c5fc873b --- /dev/null +++ b/include/dt-bindings/reset/qcom,sdm845-aoss.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_RESET_AOSS_SDM_845_H +#define _DT_BINDINGS_RESET_AOSS_SDM_845_H + +#define AOSS_CC_MSS_RESTART 0 +#define AOSS_CC_CAMSS_RESTART 1 +#define AOSS_CC_VENUS_RESTART 2 +#define AOSS_CC_GPU_RESTART 3 +#define AOSS_CC_DISPSS_RESTART 4 +#define AOSS_CC_WCSS_RESTART 5 +#define AOSS_CC_LPASS_RESTART 6 + +#endif diff --git a/include/dt-bindings/reset/qcom,sdm845-pdc.h b/include/dt-bindings/reset/qcom,sdm845-pdc.h new file mode 100644 index 00000000000..03a0c0eb814 --- /dev/null +++ b/include/dt-bindings/reset/qcom,sdm845-pdc.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_RESET_PDC_SDM_845_H +#define _DT_BINDINGS_RESET_PDC_SDM_845_H + +#define PDC_APPS_SYNC_RESET 0 +#define PDC_SP_SYNC_RESET 1 +#define PDC_AUDIO_SYNC_RESET 2 +#define PDC_SENSORS_SYNC_RESET 3 +#define PDC_AOP_SYNC_RESET 4 +#define PDC_DEBUG_SYNC_RESET 5 +#define PDC_GPU_SYNC_RESET 6 +#define PDC_DISPLAY_SYNC_RESET 7 +#define PDC_COMPUTE_SYNC_RESET 8 +#define PDC_MODEM_SYNC_RESET 9 +#define PDC_WLAN_RF_SYNC_RESET 10 +#define PDC_WPSS_SYNC_RESET 11 + +#endif diff --git a/include/dt-bindings/soc/qcom,apr.h b/include/dt-bindings/soc/qcom,apr.h new file mode 100644 index 00000000000..006362400c0 --- /dev/null +++ b/include/dt-bindings/soc/qcom,apr.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_QCOM_APR_H +#define __DT_BINDINGS_QCOM_APR_H + +/* Domain IDs */ +#define APR_DOMAIN_SIM 0x1 +#define APR_DOMAIN_PC 0x2 +#define APR_DOMAIN_MODEM 0x3 +#define APR_DOMAIN_ADSP 0x4 +#define APR_DOMAIN_APPS 0x5 +#define APR_DOMAIN_MAX 0x6 + +/* ADSP service IDs */ +#define APR_SVC_ADSP_CORE 0x3 +#define APR_SVC_AFE 0x4 +#define APR_SVC_VSM 0x5 +#define APR_SVC_VPM 0x6 +#define APR_SVC_ASM 0x7 +#define APR_SVC_ADM 0x8 +#define APR_SVC_ADSP_MVM 0x09 +#define APR_SVC_ADSP_CVS 0x0A +#define APR_SVC_ADSP_CVP 0x0B +#define APR_SVC_USM 0x0C +#define APR_SVC_LSM 0x0D +#define APR_SVC_VIDC 0x16 +#define APR_SVC_MAX 0x17 + +#endif /* __DT_BINDINGS_QCOM_APR_H */ diff --git a/include/dt-bindings/soc/qcom,rpmh-rsc.h b/include/dt-bindings/soc/qcom,rpmh-rsc.h new file mode 100644 index 00000000000..868f998ea99 --- /dev/null +++ b/include/dt-bindings/soc/qcom,rpmh-rsc.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. + */ + +#ifndef __DT_QCOM_RPMH_RSC_H__ +#define __DT_QCOM_RPMH_RSC_H__ + +#define SLEEP_TCS 0 +#define WAKE_TCS 1 +#define ACTIVE_TCS 2 +#define CONTROL_TCS 3 + +#endif /* __DT_QCOM_RPMH_RSC_H__ */ diff --git a/include/dt-bindings/sound/apq8016-lpass.h b/include/dt-bindings/sound/apq8016-lpass.h new file mode 100644 index 00000000000..dc605c4bc22 --- /dev/null +++ b/include/dt-bindings/sound/apq8016-lpass.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_APQ8016_LPASS_H +#define __DT_APQ8016_LPASS_H + +#include <dt-bindings/sound/qcom,lpass.h> + +/* NOTE: Use qcom,lpass.h to define any AIF ID's for LPASS */ + +#endif /* __DT_APQ8016_LPASS_H */ diff --git a/include/dt-bindings/sound/meson-aiu.h b/include/dt-bindings/sound/meson-aiu.h deleted file mode 100644 index 1051b8af298..00000000000 --- a/include/dt-bindings/sound/meson-aiu.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_MESON_AIU_H -#define __DT_MESON_AIU_H - -#define AIU_CPU 0 -#define AIU_HDMI 1 -#define AIU_ACODEC 2 - -#define CPU_I2S_FIFO 0 -#define CPU_SPDIF_FIFO 1 -#define CPU_I2S_ENCODER 2 -#define CPU_SPDIF_ENCODER 3 - -#define CTRL_I2S 0 -#define CTRL_PCM 1 -#define CTRL_OUT 2 - -#endif /* __DT_MESON_AIU_H */ diff --git a/include/dt-bindings/sound/meson-g12a-toacodec.h b/include/dt-bindings/sound/meson-g12a-toacodec.h deleted file mode 100644 index 69d7a75592a..00000000000 --- a/include/dt-bindings/sound/meson-g12a-toacodec.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_MESON_G12A_TOACODEC_H -#define __DT_MESON_G12A_TOACODEC_H - -#define TOACODEC_IN_A 0 -#define TOACODEC_IN_B 1 -#define TOACODEC_IN_C 2 -#define TOACODEC_OUT 3 - -#endif /* __DT_MESON_G12A_TOACODEC_H */ diff --git a/include/dt-bindings/sound/meson-g12a-tohdmitx.h b/include/dt-bindings/sound/meson-g12a-tohdmitx.h deleted file mode 100644 index c5e1f48d30d..00000000000 --- a/include/dt-bindings/sound/meson-g12a-tohdmitx.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_MESON_G12A_TOHDMITX_H -#define __DT_MESON_G12A_TOHDMITX_H - -#define TOHDMITX_I2S_IN_A 0 -#define TOHDMITX_I2S_IN_B 1 -#define TOHDMITX_I2S_IN_C 2 -#define TOHDMITX_I2S_OUT 3 -#define TOHDMITX_SPDIF_IN_A 4 -#define TOHDMITX_SPDIF_IN_B 5 -#define TOHDMITX_SPDIF_OUT 6 - -#endif /* __DT_MESON_G12A_TOHDMITX_H */ diff --git a/include/dt-bindings/sound/qcom,lpass.h b/include/dt-bindings/sound/qcom,lpass.h new file mode 100644 index 00000000000..a9404c3b888 --- /dev/null +++ b/include/dt-bindings/sound/qcom,lpass.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_QCOM_LPASS_H +#define __DT_QCOM_LPASS_H + +#define MI2S_PRIMARY 0 +#define MI2S_SECONDARY 1 +#define MI2S_TERTIARY 2 +#define MI2S_QUATERNARY 3 +#define MI2S_QUINARY 4 + +#define LPASS_DP_RX 5 + +#define LPASS_CDC_DMA_RX0 6 +#define LPASS_CDC_DMA_RX1 7 +#define LPASS_CDC_DMA_RX2 8 +#define LPASS_CDC_DMA_RX3 9 +#define LPASS_CDC_DMA_RX4 10 +#define LPASS_CDC_DMA_RX5 11 +#define LPASS_CDC_DMA_RX6 12 +#define LPASS_CDC_DMA_RX7 13 +#define LPASS_CDC_DMA_RX8 14 +#define LPASS_CDC_DMA_RX9 15 + +#define LPASS_CDC_DMA_TX0 16 +#define LPASS_CDC_DMA_TX1 17 +#define LPASS_CDC_DMA_TX2 18 +#define LPASS_CDC_DMA_TX3 19 +#define LPASS_CDC_DMA_TX4 20 +#define LPASS_CDC_DMA_TX5 21 +#define LPASS_CDC_DMA_TX6 22 +#define LPASS_CDC_DMA_TX7 23 +#define LPASS_CDC_DMA_TX8 24 + +#define LPASS_CDC_DMA_VA_TX0 25 +#define LPASS_CDC_DMA_VA_TX1 26 +#define LPASS_CDC_DMA_VA_TX2 27 +#define LPASS_CDC_DMA_VA_TX3 28 +#define LPASS_CDC_DMA_VA_TX4 29 +#define LPASS_CDC_DMA_VA_TX5 30 +#define LPASS_CDC_DMA_VA_TX6 31 +#define LPASS_CDC_DMA_VA_TX7 32 +#define LPASS_CDC_DMA_VA_TX8 33 + +#define LPASS_MCLK0 0 + +#endif /* __DT_QCOM_LPASS_H */ diff --git a/include/dt-bindings/sound/qcom,q6afe.h b/include/dt-bindings/sound/qcom,q6afe.h new file mode 100644 index 00000000000..9d5d89cfabc --- /dev/null +++ b/include/dt-bindings/sound/qcom,q6afe.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_Q6_AFE_H__ +#define __DT_BINDINGS_Q6_AFE_H__ + +/* This file exists due to backward compatibility reasons, Please do not DELETE! */ + +#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> + +#endif /* __DT_BINDINGS_Q6_AFE_H__ */ diff --git a/include/dt-bindings/sound/qcom,q6asm.h b/include/dt-bindings/sound/qcom,q6asm.h new file mode 100644 index 00000000000..f59d74f1439 --- /dev/null +++ b/include/dt-bindings/sound/qcom,q6asm.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_Q6_ASM_H__ +#define __DT_BINDINGS_Q6_ASM_H__ + +#define MSM_FRONTEND_DAI_MULTIMEDIA1 0 +#define MSM_FRONTEND_DAI_MULTIMEDIA2 1 +#define MSM_FRONTEND_DAI_MULTIMEDIA3 2 +#define MSM_FRONTEND_DAI_MULTIMEDIA4 3 +#define MSM_FRONTEND_DAI_MULTIMEDIA5 4 +#define MSM_FRONTEND_DAI_MULTIMEDIA6 5 +#define MSM_FRONTEND_DAI_MULTIMEDIA7 6 +#define MSM_FRONTEND_DAI_MULTIMEDIA8 7 +#define MSM_FRONTEND_DAI_MULTIMEDIA9 8 +#define MSM_FRONTEND_DAI_MULTIMEDIA10 9 +#define MSM_FRONTEND_DAI_MULTIMEDIA11 10 +#define MSM_FRONTEND_DAI_MULTIMEDIA12 11 +#define MSM_FRONTEND_DAI_MULTIMEDIA13 12 +#define MSM_FRONTEND_DAI_MULTIMEDIA14 13 +#define MSM_FRONTEND_DAI_MULTIMEDIA15 14 +#define MSM_FRONTEND_DAI_MULTIMEDIA16 15 + +#define Q6ASM_DAI_TX_RX 0 +#define Q6ASM_DAI_TX 1 +#define Q6ASM_DAI_RX 2 + +#endif /* __DT_BINDINGS_Q6_ASM_H__ */ diff --git a/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h b/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h new file mode 100644 index 00000000000..39f203256c4 --- /dev/null +++ b/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h @@ -0,0 +1,234 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_Q6_AUDIO_PORTS_H__ +#define __DT_BINDINGS_Q6_AUDIO_PORTS_H__ + +/* LPASS Audio virtual ports IDs */ +#define HDMI_RX 1 +#define SLIMBUS_0_RX 2 +#define SLIMBUS_0_TX 3 +#define SLIMBUS_1_RX 4 +#define SLIMBUS_1_TX 5 +#define SLIMBUS_2_RX 6 +#define SLIMBUS_2_TX 7 +#define SLIMBUS_3_RX 8 +#define SLIMBUS_3_TX 9 +#define SLIMBUS_4_RX 10 +#define SLIMBUS_4_TX 11 +#define SLIMBUS_5_RX 12 +#define SLIMBUS_5_TX 13 +#define SLIMBUS_6_RX 14 +#define SLIMBUS_6_TX 15 +#define PRIMARY_MI2S_RX 16 +#define PRIMARY_MI2S_TX 17 +#define SECONDARY_MI2S_RX 18 +#define SECONDARY_MI2S_TX 19 +#define TERTIARY_MI2S_RX 20 +#define TERTIARY_MI2S_TX 21 +#define QUATERNARY_MI2S_RX 22 +#define QUATERNARY_MI2S_TX 23 +#define PRIMARY_TDM_RX_0 24 +#define PRIMARY_TDM_TX_0 25 +#define PRIMARY_TDM_RX_1 26 +#define PRIMARY_TDM_TX_1 27 +#define PRIMARY_TDM_RX_2 28 +#define PRIMARY_TDM_TX_2 29 +#define PRIMARY_TDM_RX_3 30 +#define PRIMARY_TDM_TX_3 31 +#define PRIMARY_TDM_RX_4 32 +#define PRIMARY_TDM_TX_4 33 +#define PRIMARY_TDM_RX_5 34 +#define PRIMARY_TDM_TX_5 35 +#define PRIMARY_TDM_RX_6 36 +#define PRIMARY_TDM_TX_6 37 +#define PRIMARY_TDM_RX_7 38 +#define PRIMARY_TDM_TX_7 39 +#define SECONDARY_TDM_RX_0 40 +#define SECONDARY_TDM_TX_0 41 +#define SECONDARY_TDM_RX_1 42 +#define SECONDARY_TDM_TX_1 43 +#define SECONDARY_TDM_RX_2 44 +#define SECONDARY_TDM_TX_2 45 +#define SECONDARY_TDM_RX_3 46 +#define SECONDARY_TDM_TX_3 47 +#define SECONDARY_TDM_RX_4 48 +#define SECONDARY_TDM_TX_4 49 +#define SECONDARY_TDM_RX_5 50 +#define SECONDARY_TDM_TX_5 51 +#define SECONDARY_TDM_RX_6 52 +#define SECONDARY_TDM_TX_6 53 +#define SECONDARY_TDM_RX_7 54 +#define SECONDARY_TDM_TX_7 55 +#define TERTIARY_TDM_RX_0 56 +#define TERTIARY_TDM_TX_0 57 +#define TERTIARY_TDM_RX_1 58 +#define TERTIARY_TDM_TX_1 59 +#define TERTIARY_TDM_RX_2 60 +#define TERTIARY_TDM_TX_2 61 +#define TERTIARY_TDM_RX_3 62 +#define TERTIARY_TDM_TX_3 63 +#define TERTIARY_TDM_RX_4 64 +#define TERTIARY_TDM_TX_4 65 +#define TERTIARY_TDM_RX_5 66 +#define TERTIARY_TDM_TX_5 67 +#define TERTIARY_TDM_RX_6 68 +#define TERTIARY_TDM_TX_6 69 +#define TERTIARY_TDM_RX_7 70 +#define TERTIARY_TDM_TX_7 71 +#define QUATERNARY_TDM_RX_0 72 +#define QUATERNARY_TDM_TX_0 73 +#define QUATERNARY_TDM_RX_1 74 +#define QUATERNARY_TDM_TX_1 75 +#define QUATERNARY_TDM_RX_2 76 +#define QUATERNARY_TDM_TX_2 77 +#define QUATERNARY_TDM_RX_3 78 +#define QUATERNARY_TDM_TX_3 79 +#define QUATERNARY_TDM_RX_4 80 +#define QUATERNARY_TDM_TX_4 81 +#define QUATERNARY_TDM_RX_5 82 +#define QUATERNARY_TDM_TX_5 83 +#define QUATERNARY_TDM_RX_6 84 +#define QUATERNARY_TDM_TX_6 85 +#define QUATERNARY_TDM_RX_7 86 +#define QUATERNARY_TDM_TX_7 87 +#define QUINARY_TDM_RX_0 88 +#define QUINARY_TDM_TX_0 89 +#define QUINARY_TDM_RX_1 90 +#define QUINARY_TDM_TX_1 91 +#define QUINARY_TDM_RX_2 92 +#define QUINARY_TDM_TX_2 93 +#define QUINARY_TDM_RX_3 94 +#define QUINARY_TDM_TX_3 95 +#define QUINARY_TDM_RX_4 96 +#define QUINARY_TDM_TX_4 97 +#define QUINARY_TDM_RX_5 98 +#define QUINARY_TDM_TX_5 99 +#define QUINARY_TDM_RX_6 100 +#define QUINARY_TDM_TX_6 101 +#define QUINARY_TDM_RX_7 102 +#define QUINARY_TDM_TX_7 103 +#define DISPLAY_PORT_RX 104 +#define WSA_CODEC_DMA_RX_0 105 +#define WSA_CODEC_DMA_TX_0 106 +#define WSA_CODEC_DMA_RX_1 107 +#define WSA_CODEC_DMA_TX_1 108 +#define WSA_CODEC_DMA_TX_2 109 +#define VA_CODEC_DMA_TX_0 110 +#define VA_CODEC_DMA_TX_1 111 +#define VA_CODEC_DMA_TX_2 112 +#define RX_CODEC_DMA_RX_0 113 +#define TX_CODEC_DMA_TX_0 114 +#define RX_CODEC_DMA_RX_1 115 +#define TX_CODEC_DMA_TX_1 116 +#define RX_CODEC_DMA_RX_2 117 +#define TX_CODEC_DMA_TX_2 118 +#define RX_CODEC_DMA_RX_3 119 +#define TX_CODEC_DMA_TX_3 120 +#define RX_CODEC_DMA_RX_4 121 +#define TX_CODEC_DMA_TX_4 122 +#define RX_CODEC_DMA_RX_5 123 +#define TX_CODEC_DMA_TX_5 124 +#define RX_CODEC_DMA_RX_6 125 +#define RX_CODEC_DMA_RX_7 126 +#define QUINARY_MI2S_RX 127 +#define QUINARY_MI2S_TX 128 +#define DISPLAY_PORT_RX_0 DISPLAY_PORT_RX +#define DISPLAY_PORT_RX_1 129 +#define DISPLAY_PORT_RX_2 130 +#define DISPLAY_PORT_RX_3 131 +#define DISPLAY_PORT_RX_4 132 +#define DISPLAY_PORT_RX_5 133 +#define DISPLAY_PORT_RX_6 134 +#define DISPLAY_PORT_RX_7 135 + +#define LPASS_CLK_ID_PRI_MI2S_IBIT 1 +#define LPASS_CLK_ID_PRI_MI2S_EBIT 2 +#define LPASS_CLK_ID_SEC_MI2S_IBIT 3 +#define LPASS_CLK_ID_SEC_MI2S_EBIT 4 +#define LPASS_CLK_ID_TER_MI2S_IBIT 5 +#define LPASS_CLK_ID_TER_MI2S_EBIT 6 +#define LPASS_CLK_ID_QUAD_MI2S_IBIT 7 +#define LPASS_CLK_ID_QUAD_MI2S_EBIT 8 +#define LPASS_CLK_ID_SPEAKER_I2S_IBIT 9 +#define LPASS_CLK_ID_SPEAKER_I2S_EBIT 10 +#define LPASS_CLK_ID_SPEAKER_I2S_OSR 11 +#define LPASS_CLK_ID_QUI_MI2S_IBIT 12 +#define LPASS_CLK_ID_QUI_MI2S_EBIT 13 +#define LPASS_CLK_ID_SEN_MI2S_IBIT 14 +#define LPASS_CLK_ID_SEN_MI2S_EBIT 15 +#define LPASS_CLK_ID_INT0_MI2S_IBIT 16 +#define LPASS_CLK_ID_INT1_MI2S_IBIT 17 +#define LPASS_CLK_ID_INT2_MI2S_IBIT 18 +#define LPASS_CLK_ID_INT3_MI2S_IBIT 19 +#define LPASS_CLK_ID_INT4_MI2S_IBIT 20 +#define LPASS_CLK_ID_INT5_MI2S_IBIT 21 +#define LPASS_CLK_ID_INT6_MI2S_IBIT 22 +#define LPASS_CLK_ID_QUI_MI2S_OSR 23 +#define LPASS_CLK_ID_PRI_PCM_IBIT 24 +#define LPASS_CLK_ID_PRI_PCM_EBIT 25 +#define LPASS_CLK_ID_SEC_PCM_IBIT 26 +#define LPASS_CLK_ID_SEC_PCM_EBIT 27 +#define LPASS_CLK_ID_TER_PCM_IBIT 28 +#define LPASS_CLK_ID_TER_PCM_EBIT 29 +#define LPASS_CLK_ID_QUAD_PCM_IBIT 30 +#define LPASS_CLK_ID_QUAD_PCM_EBIT 31 +#define LPASS_CLK_ID_QUIN_PCM_IBIT 32 +#define LPASS_CLK_ID_QUIN_PCM_EBIT 33 +#define LPASS_CLK_ID_QUI_PCM_OSR 34 +#define LPASS_CLK_ID_PRI_TDM_IBIT 35 +#define LPASS_CLK_ID_PRI_TDM_EBIT 36 +#define LPASS_CLK_ID_SEC_TDM_IBIT 37 +#define LPASS_CLK_ID_SEC_TDM_EBIT 38 +#define LPASS_CLK_ID_TER_TDM_IBIT 39 +#define LPASS_CLK_ID_TER_TDM_EBIT 40 +#define LPASS_CLK_ID_QUAD_TDM_IBIT 41 +#define LPASS_CLK_ID_QUAD_TDM_EBIT 42 +#define LPASS_CLK_ID_QUIN_TDM_IBIT 43 +#define LPASS_CLK_ID_QUIN_TDM_EBIT 44 +#define LPASS_CLK_ID_QUIN_TDM_OSR 45 +#define LPASS_CLK_ID_MCLK_1 46 +#define LPASS_CLK_ID_MCLK_2 47 +#define LPASS_CLK_ID_MCLK_3 48 +#define LPASS_CLK_ID_MCLK_4 49 +#define LPASS_CLK_ID_INTERNAL_DIGITAL_CODEC_CORE 50 +#define LPASS_CLK_ID_INT_MCLK_0 51 +#define LPASS_CLK_ID_INT_MCLK_1 52 +#define LPASS_CLK_ID_MCLK_5 53 +#define LPASS_CLK_ID_WSA_CORE_MCLK 54 +#define LPASS_CLK_ID_WSA_CORE_NPL_MCLK 55 +#define LPASS_CLK_ID_VA_CORE_MCLK 56 +#define LPASS_CLK_ID_TX_CORE_MCLK 57 +#define LPASS_CLK_ID_TX_CORE_NPL_MCLK 58 +#define LPASS_CLK_ID_RX_CORE_MCLK 59 +#define LPASS_CLK_ID_RX_CORE_NPL_MCLK 60 +#define LPASS_CLK_ID_VA_CORE_2X_MCLK 61 +/* Clock ID for MCLK for WSA2 core */ +#define LPASS_CLK_ID_WSA2_CORE_MCLK 62 +/* Clock ID for NPL MCLK for WSA2 core */ +#define LPASS_CLK_ID_WSA2_CORE_2X_MCLK 63 +/* Clock ID for RX Core TX MCLK */ +#define LPASS_CLK_ID_RX_CORE_TX_MCLK 64 +/* Clock ID for RX CORE TX 2X MCLK */ +#define LPASS_CLK_ID_RX_CORE_TX_2X_MCLK 65 +/* Clock ID for WSA core TX MCLK */ +#define LPASS_CLK_ID_WSA_CORE_TX_MCLK 66 +/* Clock ID for WSA core TX 2X MCLK */ +#define LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK 67 +/* Clock ID for WSA2 core TX MCLK */ +#define LPASS_CLK_ID_WSA2_CORE_TX_MCLK 68 +/* Clock ID for WSA2 core TX 2X MCLK */ +#define LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK 69 +/* Clock ID for RX CORE MCLK2 2X MCLK */ +#define LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK 70 + +#define LPASS_HW_AVTIMER_VOTE 101 +#define LPASS_HW_MACRO_VOTE 102 +#define LPASS_HW_DCODEC_VOTE 103 + +#define Q6AFE_MAX_CLK_ID 104 + +#define LPASS_CLK_ATTRIBUTE_INVALID 0x0 +#define LPASS_CLK_ATTRIBUTE_COUPLE_NO 0x1 +#define LPASS_CLK_ATTRIBUTE_COUPLE_DIVIDEND 0x2 +#define LPASS_CLK_ATTRIBUTE_COUPLE_DIVISOR 0x3 + +#endif /* __DT_BINDINGS_Q6_AUDIO_PORTS_H__ */ diff --git a/include/dt-bindings/sound/qcom,wcd9335.h b/include/dt-bindings/sound/qcom,wcd9335.h new file mode 100644 index 00000000000..f5e9f1db091 --- /dev/null +++ b/include/dt-bindings/sound/qcom,wcd9335.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef __DT_SOUND_QCOM_WCD9335_H +#define __DT_SOUND_QCOM_WCD9335_H + +#define AIF1_PB 0 +#define AIF1_CAP 1 +#define AIF2_PB 2 +#define AIF2_CAP 3 +#define AIF3_PB 4 +#define AIF3_CAP 5 +#define AIF4_PB 6 +#define NUM_CODEC_DAIS 7 + +#endif diff --git a/include/dw_hdmi.h b/include/dw_hdmi.h index 8acae3839fb..f4d66edacee 100644 --- a/include/dw_hdmi.h +++ b/include/dw_hdmi.h @@ -534,6 +534,14 @@ struct hdmi_data_info { struct hdmi_vmode video_mode; }; +struct dw_hdmi; + +struct dw_hdmi_phy_ops { + int (*phy_set)(struct dw_hdmi *hdmi, uint mpixelclock); + void (*read_hpd)(struct dw_hdmi *hdmi, bool hdp_status); + void (*setup_hpd)(struct dw_hdmi *hdmi); +}; + struct dw_hdmi { ulong ioaddr; const struct hdmi_mpll_config *mpll_cfg; @@ -543,8 +551,8 @@ struct dw_hdmi { u8 reg_io_width; struct hdmi_data_info hdmi_data; struct udevice *ddc_bus; + const struct dw_hdmi_phy_ops *ops; - int (*phy_set)(struct dw_hdmi *hdmi, uint mpixelclock); void (*write_reg)(struct dw_hdmi *hdmi, u8 val, int offset); u8 (*read_reg)(struct dw_hdmi *hdmi, int offset); }; @@ -556,5 +564,6 @@ void dw_hdmi_phy_init(struct dw_hdmi *hdmi); int dw_hdmi_enable(struct dw_hdmi *hdmi, const struct display_timing *edid); int dw_hdmi_read_edid(struct dw_hdmi *hdmi, u8 *buf, int buf_size); void dw_hdmi_init(struct dw_hdmi *hdmi); +int dw_hdmi_detect_hpd(struct dw_hdmi *hdmi); #endif diff --git a/include/dwc3-omap-uboot.h b/include/dwc3-omap-uboot.h index ed92bfc5a97..f220705ef7b 100644 --- a/include/dwc3-omap-uboot.h +++ b/include/dwc3-omap-uboot.h @@ -27,5 +27,4 @@ struct dwc3_omap_device { int dwc3_omap_uboot_init(struct dwc3_omap_device *dev); void dwc3_omap_uboot_exit(int index); -int dwc3_omap_uboot_interrupt_status(struct udevice *dev); #endif /* __DWC3_OMAP_UBOOT_H_ */ diff --git a/include/dwc3-uboot.h b/include/dwc3-uboot.h index 35cfbb93b29..3689d60ae7f 100644 --- a/include/dwc3-uboot.h +++ b/include/dwc3-uboot.h @@ -44,7 +44,7 @@ struct dwc3_device { int dwc3_uboot_init(struct dwc3_device *dev); void dwc3_uboot_exit(int index); -void dwc3_uboot_handle_interrupt(struct udevice *dev); +int dwc3_uboot_interrupt_status(struct udevice *dev); struct phy; #if CONFIG_IS_ENABLED(PHY) && CONFIG_IS_ENABLED(DM_USB) diff --git a/include/efi.h b/include/efi.h index f0e5faa7549..c3c4b93f860 100644 --- a/include/efi.h +++ b/include/efi.h @@ -492,13 +492,14 @@ extern char _binary_u_boot_bin_start[], _binary_u_boot_bin_end[]; /* * Variable Attributes */ -#define EFI_VARIABLE_NON_VOLATILE 0x0000000000000001 -#define EFI_VARIABLE_BOOTSERVICE_ACCESS 0x0000000000000002 -#define EFI_VARIABLE_RUNTIME_ACCESS 0x0000000000000004 -#define EFI_VARIABLE_HARDWARE_ERROR_RECORD 0x0000000000000008 -#define EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS 0x0000000000000010 -#define EFI_VARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACCESS 0x0000000000000020 -#define EFI_VARIABLE_APPEND_WRITE 0x0000000000000040 +#define EFI_VARIABLE_NON_VOLATILE 0x00000001 +#define EFI_VARIABLE_BOOTSERVICE_ACCESS 0x00000002 +#define EFI_VARIABLE_RUNTIME_ACCESS 0x00000004 +#define EFI_VARIABLE_HARDWARE_ERROR_RECORD 0x00000008 +#define EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS 0x00000010 +#define EFI_VARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACCESS 0x00000020 +#define EFI_VARIABLE_APPEND_WRITE 0x00000040 +#define EFI_VARIABLE_ENHANCED_AUTHENTICATED_ACCESS 0x00000080 #define EFI_VARIABLE_MASK (EFI_VARIABLE_NON_VOLATILE | \ EFI_VARIABLE_BOOTSERVICE_ACCESS | \ @@ -506,7 +507,8 @@ extern char _binary_u_boot_bin_start[], _binary_u_boot_bin_end[]; EFI_VARIABLE_HARDWARE_ERROR_RECORD | \ EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS | \ EFI_VARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACCESS | \ - EFI_VARIABLE_APPEND_WRITE) + EFI_VARIABLE_APPEND_WRITE | \ + EFI_VARIABLE_ENHANCED_AUTHENTICATED_ACCESS) /** * efi_get_priv() - Get access to the EFI-private information diff --git a/include/efi_loader.h b/include/efi_loader.h index 7daca0afba2..69442f4e58d 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -159,6 +159,10 @@ static inline void efi_set_bootdev(const char *dev, const char *devnr, #define EFICONFIG_AUTO_GENERATED_ENTRY_GUID \ EFI_GUID(0x8108ac4e, 0x9f11, 0x4d59, \ 0x85, 0x0e, 0xe2, 0x1a, 0x52, 0x2c, 0x59, 0xb2) +#define U_BOOT_EFI_RT_VAR_FILE_GUID \ + EFI_GUID(0xb2ac5fc9, 0x92b7, 0x4acd, \ + 0xae, 0xac, 0x11, 0xe8, 0x18, 0xc3, 0x13, 0x0c) + /* Use internal device tree when starting UEFI application */ #define EFI_FDT_USE_INTERNAL NULL @@ -345,9 +349,6 @@ extern const efi_guid_t smbios3_guid; extern const efi_guid_t efi_guid_text_input_protocol; extern const efi_guid_t efi_guid_text_output_protocol; -extern char __efi_runtime_start[], __efi_runtime_stop[]; -extern char __efi_runtime_rel_start[], __efi_runtime_rel_stop[]; - /** * struct efi_open_protocol_info_item - open protocol info item * diff --git a/include/efi_tcg2.h b/include/efi_tcg2.h index b21c5cb3dd6..a75b5a35b6e 100644 --- a/include/efi_tcg2.h +++ b/include/efi_tcg2.h @@ -150,16 +150,14 @@ struct efi_tcg2_final_events_table { * the variable. * @variable_data_length: The size of the variable data. * @unicode_name: The CHAR16 unicode name of the variable - * without NULL-terminator. - * @variable_data: The data parameter of the efi variable - * in the GetVariable() API. + * without NULL-terminator followed by data. */ struct efi_tcg2_uefi_variable_data { efi_guid_t variable_name; u64 unicode_name_length; u64 variable_data_length; - u16 unicode_name[1]; - u8 variable_data[1]; + u16 unicode_name[]; + // u8 variable_data[]; }; /** diff --git a/include/efi_variable.h b/include/efi_variable.h index 805e6c5f1e0..223bb9a4a5b 100644 --- a/include/efi_variable.h +++ b/include/efi_variable.h @@ -8,7 +8,7 @@ #include <linux/bitops.h> -#define EFI_VARIABLE_READ_ONLY BIT(31) +#define EFI_VARIABLE_READ_ONLY 0x80000000 enum efi_auth_var_type { EFI_AUTH_VAR_NONE = 0, @@ -271,13 +271,16 @@ const efi_guid_t *efi_auth_var_get_guid(const u16 *name); * * @variable_name_size: size of variable_name buffer in bytes * @variable_name: name of uefi variable's name in u16 + * @mask: bitmask with required attributes of variables to be collected. + * variables are only collected if all of the required + * attributes match. Use 0 to skip matching * @vendor: vendor's guid * * Return: status code */ efi_status_t __efi_runtime efi_get_next_variable_name_mem(efi_uintn_t *variable_name_size, u16 *variable_name, - efi_guid_t *vendor); + efi_guid_t *vendor, u32 mask); /** * efi_get_variable_mem() - Runtime common code across efi variable * implementations for GetVariable() from @@ -289,12 +292,15 @@ efi_get_next_variable_name_mem(efi_uintn_t *variable_name_size, u16 *variable_na * @data_size: size of the buffer to which the variable value is copied * @data: buffer to which the variable value is copied * @timep: authentication time (seconds since start of epoch) + * @mask: bitmask with required attributes of variables to be collected. + * variables are only collected if all of the required + * attributes match. Use 0 to skip matching * Return: status code */ efi_status_t __efi_runtime efi_get_variable_mem(const u16 *variable_name, const efi_guid_t *vendor, u32 *attributes, efi_uintn_t *data_size, void *data, - u64 *timep); + u64 *timep, u32 mask); /** * efi_get_variable_runtime() - runtime implementation of GetVariable() @@ -334,4 +340,10 @@ efi_get_next_variable_name_runtime(efi_uintn_t *variable_name_size, */ void efi_var_buf_update(struct efi_var_file *var_buf); +efi_status_t __efi_runtime efi_var_collect_mem(struct efi_var_file *buf, + efi_uintn_t *lenp, + u32 check_attr_mask); + +u32 efi_var_entry_len(struct efi_var_entry *var); + #endif diff --git a/include/env/phytec/rauc.env b/include/env/phytec/rauc.env new file mode 100644 index 00000000000..89e17ff70ec --- /dev/null +++ b/include/env/phytec/rauc.env @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +/* Logic to select a boot partition based on environment variables and switch + * to the other if the boot fails. */ + +doraucboot=0 + +raucbootpart0=1 +raucrootpart0=5 +raucbootpart1=2 +raucrootpart1=6 + +raucinit= + echo Booting RAUC A/B system; + test -n "${BOOT_ORDER}" || env set BOOT_ORDER "system0 system1"; + test -n "${BOOT_system0_LEFT}" || env set BOOT_system0_LEFT 3; + test -n "${BOOT_system1_LEFT}" || env set BOOT_system1_LEFT 3; + env set raucstatus; + for BOOT_SLOT in "${BOOT_ORDER}"; do + if test "x${raucstatus}" != "x"; then + echo Skipping remaing slots!; + elif test "x${BOOT_SLOT}" = "xsystem0"; then + if test ${BOOT_system0_LEFT} -gt 0; then + echo Found valid slot A, ${BOOT_system0_LEFT} attempts remaining; + setexpr BOOT_system0_LEFT ${BOOT_system0_LEFT} - 1; + env set mmcpart ${raucbootpart0}; + env set mmcroot ${raucrootpart0}; + env set raucargs rauc.slot=system0; + env set raucstatus success; + fi; + elif test "x${BOOT_SLOT}" = "xsystem1"; then + if test ${BOOT_system1_LEFT} -gt 0; then + echo Found valid slot B, ${BOOT_system1_LEFT} attempts remaining; + setexpr BOOT_system1_LEFT ${BOOT_system1_LEFT} - 1; + env set mmcpart ${raucbootpart1}; + env set mmcroot ${raucrootpart1}; + env set raucargs rauc.slot=system1; + env set raucstatus success; + fi; + fi; + done; + if test -n "${raucstatus}"; then + env delete raucstatus; + env save; + else + echo WARN: No valid slot found; + env set BOOT_system0_LEFT 3; + env set BOOT_system1_LEFT 3; + env delete raucstatus; + env save; + reset; + fi; diff --git a/include/env_default.h b/include/env_default.h index 2ca4a087d3b..8ee500d1709 100644 --- a/include/env_default.h +++ b/include/env_default.h @@ -99,6 +99,17 @@ const char default_environment[] = { #ifdef CONFIG_SYS_SOC "soc=" CONFIG_SYS_SOC "\0" #endif +#ifdef CONFIG_USB_HOST + "usb_ignorelist=" +#ifdef CONFIG_USB_KEYBOARD + /* Ignore Yubico devices. Currently only a single USB keyboard device is + * supported and the emulated HID keyboard Yubikeys present is useless + * as keyboard. + */ + "0x1050:*," +#endif + "\0" +#endif #ifdef CONFIG_ENV_IMPORT_FDT "env_fdt_path=" CONFIG_ENV_FDT_PATH "\0" #endif diff --git a/include/fastboot.h b/include/fastboot.h index 1e7920eb913..2ca1b907a54 100644 --- a/include/fastboot.h +++ b/include/fastboot.h @@ -48,6 +48,7 @@ enum { FASTBOOT_COMMAND_OEM_BOOTBUS, FASTBOOT_COMMAND_OEM_RUN, FASTBOOT_COMMAND_OEM_CONSOLE, + FASTBOOT_COMMAND_OEM_BOARD, FASTBOOT_COMMAND_ACMD, FASTBOOT_COMMAND_UCMD, FASTBOOT_COMMAND_COUNT diff --git a/include/fdt_support.h b/include/fdt_support.h index 25600d62f29..4b71b8948d9 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -423,6 +423,8 @@ int arch_fixup_memory_node(void *blob); int fdt_setup_simplefb_node(void *fdt, int node, u64 base_address, u32 width, u32 height, u32 stride, const char *format); +int fdt_add_fb_mem_rsv(void *blob); + int fdt_overlay_apply_verbose(void *fdt, void *fdto); int fdt_valid(struct fdt_header **blobp); diff --git a/include/host_arch.h b/include/host_arch.h index 169d4945136..261194bd7c6 100644 --- a/include/host_arch.h +++ b/include/host_arch.h @@ -16,6 +16,8 @@ export HOST_ARCH_X86=0x0386 export HOST_ARCH_X86_64=0x8664 #endif +#include <version.h> + #define HOST_ARCH_AARCH64 0xaa64 #define HOST_ARCH_ARM 0x00a7 #define HOST_ARCH_RISCV32 0x5032 diff --git a/include/image.h b/include/image.h index 21de70f0c9e..acffd17e0df 100644 --- a/include/image.h +++ b/include/image.h @@ -946,7 +946,7 @@ static inline void image_set_name(struct legacy_img_hdr *hdr, const char *name) int image_check_hcrc(const struct legacy_img_hdr *hdr); int image_check_dcrc(const struct legacy_img_hdr *hdr); #ifndef USE_HOSTCC -ulong env_get_bootm_low(void); +phys_addr_t env_get_bootm_low(void); phys_size_t env_get_bootm_size(void); phys_size_t env_get_bootm_mapsize(void); #endif diff --git a/include/imx_container.h b/include/imx_container.h index 54cd684e35d..691c764b3e5 100644 --- a/include/imx_container.h +++ b/include/imx_container.h @@ -50,10 +50,10 @@ struct signature_block_hdr { u8 length_lsb; u8 length_msb; u8 tag; - u16 srk_table_offset; u16 cert_offset; - u16 blob_offset; + u16 srk_table_offset; u16 signature_offset; + u16 blob_offset; u32 reserved; } __packed; diff --git a/include/init.h b/include/init.h index 9a1951d10a0..630d86729c4 100644 --- a/include/init.h +++ b/include/init.h @@ -168,6 +168,17 @@ defined(CONFIG_SAVE_PREV_BL_FDT_ADDR) * Return: 0 if ok; -ENODATA on error */ int save_prev_bl_data(void); + +/** + * get_prev_bl_fdt_addr - When u-boot is chainloaded, get the address + * of the FDT passed by the previous bootloader. + * + * Return: the address of the FDT passed by the previous bootloader + * or 0 if not found. + */ +phys_addr_t get_prev_bl_fdt_addr(void); +#else +#define get_prev_bl_fdt_addr() 0LLU #endif /** diff --git a/include/k3-clk.h b/include/k3-clk.h index 1b6ab8fe654..7bc42ecbb0c 100644 --- a/include/k3-clk.h +++ b/include/k3-clk.h @@ -176,6 +176,8 @@ extern const struct ti_k3_clk_platdata j7200_clk_platdata; extern const struct ti_k3_clk_platdata j721s2_clk_platdata; extern const struct ti_k3_clk_platdata am62x_clk_platdata; extern const struct ti_k3_clk_platdata am62ax_clk_platdata; +extern const struct ti_k3_clk_platdata j784s4_clk_platdata; +extern const struct ti_k3_clk_platdata am62px_clk_platdata; struct clk *clk_register_ti_pll(const char *name, const char *parent_name, void __iomem *reg); diff --git a/include/k3-dev.h b/include/k3-dev.h index 072e10ba632..0c5ae9aa426 100644 --- a/include/k3-dev.h +++ b/include/k3-dev.h @@ -80,6 +80,8 @@ extern const struct ti_k3_pd_platdata j7200_pd_platdata; extern const struct ti_k3_pd_platdata j721s2_pd_platdata; extern const struct ti_k3_pd_platdata am62x_pd_platdata; extern const struct ti_k3_pd_platdata am62ax_pd_platdata; +extern const struct ti_k3_pd_platdata j784s4_pd_platdata; +extern const struct ti_k3_pd_platdata am62px_pd_platdata; u8 ti_pd_state(struct ti_pd *pd); u8 lpsc_get_state(struct ti_lpsc *lpsc); diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h index f44e9e8f930..da3d29aabee 100644 --- a/include/linux/arm-smccc.h +++ b/include/linux/arm-smccc.h @@ -55,8 +55,14 @@ #define ARM_SMCCC_QUIRK_NONE 0 #define ARM_SMCCC_QUIRK_QCOM_A6 1 /* Save/restore register a6 */ +#define ARM_SMCCC_VERSION 0x80000000 #define ARM_SMCCC_ARCH_FEATURES 0x80000001 +#define ARM_SMCCC_VERSION_1_0 0x10000 +#define ARM_SMCCC_VERSION_1_1 0x10001 +#define ARM_SMCCC_VERSION_1_2 0x10002 +#define ARM_SMCCC_VERSION_1_3 0x10003 + #define ARM_SMCCC_RET_NOT_SUPPORTED ((unsigned long)-1) #ifndef __ASSEMBLY__ diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h index 7a66c7af749..ee18a63e460 100644 --- a/include/linux/mtd/mtd.h +++ b/include/linux/mtd/mtd.h @@ -153,7 +153,7 @@ struct mtd_info { uint32_t flags; uint64_t size; // Total size of the MTD - /* "Major" erase size for the device. Naïve users may take this + /* "Major" erase size for the device. Naive users may take this * to be the only erase size available, or may use the more detailed * information below if they desire */ diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index fb002ae6411..4abaf4734cf 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -249,6 +249,13 @@ enum nand_ecc_algo { */ #define NAND_USE_BOUNCE_BUFFER 0x00100000 +/* + * Do not try to tweak the timings at runtime. This is needed when the + * controller initializes the timings on itself or when it relies on + * configuration done by the bootloader. + */ +#define NAND_KEEP_TIMINGS 0x00800000 + /* Options set by nand scan */ /* bbt has already been read */ #define NAND_BBT_SCANNED 0x40000000 diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index 6f479fa5adc..13b5a52f8b9 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -251,6 +251,7 @@ extern const struct spinand_manufacturer paragon_spinand_manufacturer; extern const struct spinand_manufacturer toshiba_spinand_manufacturer; extern const struct spinand_manufacturer winbond_spinand_manufacturer; extern const struct spinand_manufacturer esmt_c8_spinand_manufacturer; +extern const struct spinand_manufacturer xtx_spinand_manufacturer; /** * struct spinand_op_variants - SPI NAND operation variants diff --git a/include/log.h b/include/log.h index 6e84f080ef3..fc0d5984472 100644 --- a/include/log.h +++ b/include/log.h @@ -688,4 +688,16 @@ static inline int log_get_default_format(void) (IS_ENABLED(CONFIG_LOGF_FUNC) ? BIT(LOGF_FUNC) : 0); } +struct global_data; +/** + * log_fixup_for_gd_move() - Handle global_data moving to a new place + * + * @new_gd: Pointer to the new global data + * + * The log_head list is part of global_data. Due to the way lists work, moving + * the list will cause it to become invalid. This function fixes that up so + * that the log_head list will work correctly. + */ +void log_fixup_for_gd_move(struct global_data *new_gd); + #endif diff --git a/include/mcheck.h b/include/mcheck.h new file mode 100644 index 00000000000..bd506ae6291 --- /dev/null +++ b/include/mcheck.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.1+ */ +/* + * Copyright (C) 1996-2024 Free Software Foundation, Inc. + * This file is part of the GNU C Library. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * <https://www.gnu.org/licenses/>. + */ +#ifndef _MCHECK_H +#define _MCHECK_H 1 + +/* + * Return values for `mprobe': these are the kinds of inconsistencies that + * `mcheck' enables detection of. + */ +enum mcheck_status { + MCHECK_DISABLED = -1, /* Consistency checking is not turned on. */ + MCHECK_OK, /* Block is fine. */ + MCHECK_FREE, /* Block freed twice. */ + MCHECK_HEAD, /* Memory before the block was clobbered. */ + MCHECK_TAIL /* Memory after the block was clobbered. */ +}; + +typedef void (*mcheck_abortfunc_t)(enum mcheck_status, const void *p); + +int mcheck(mcheck_abortfunc_t func); + +/* + * Similar to `mcheck' but performs checks for all block whenever one of + * the memory handling functions is called. This can be very slow. + */ +int mcheck_pedantic(mcheck_abortfunc_t f); + +/* Force check of all blocks now. */ +void mcheck_check_all(void); + +/* + * Check for aberrations in a particular malloc'd block. These are the + * same checks that `mcheck' does, when you free or reallocate a block. + */ +enum mcheck_status mprobe(void *__ptr); + +#endif diff --git a/include/mmc.h b/include/mmc.h index 1022db3ffa7..4b8327f1f93 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -590,7 +590,7 @@ struct mmc_config { uint f_max; uint b_max; unsigned char part_type; -#ifdef CONFIG_MMC_PWRSEQ +#if CONFIG_IS_ENABLED(MMC_PWRSEQ) struct udevice *pwr_dev; #endif }; @@ -736,7 +736,8 @@ struct mmc { * accessing the boot partitions */ u32 quirks; - u8 hs400_tuning; + bool tuning:1; + bool hs400_tuning:1; enum bus_mode user_speed_mode; /* input speed mode from user */ }; @@ -795,7 +796,7 @@ int mmc_unbind(struct udevice *dev); int mmc_initialize(struct bd_info *bis); int mmc_init_device(int num); int mmc_init(struct mmc *mmc); -int mmc_send_tuning(struct mmc *mmc, u32 opcode, int *cmd_error); +int mmc_send_tuning(struct mmc *mmc, u32 opcode); int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data); int mmc_deinit(struct mmc *mmc); @@ -808,7 +809,7 @@ int mmc_deinit(struct mmc *mmc); */ int mmc_of_parse(struct udevice *dev, struct mmc_config *cfg); -#ifdef CONFIG_MMC_PWRSEQ +#if CONFIG_IS_ENABLED(MMC_PWRSEQ) /** * mmc_pwrseq_get_power() - get a power device from device tree * diff --git a/include/pci_ids.h b/include/pci_ids.h index b63bf45168d..f1886c3a751 100644 --- a/include/pci_ids.h +++ b/include/pci_ids.h @@ -2710,6 +2710,8 @@ #define PCI_DEVICE_ID_INTEL_I211_COPPER 0x1539 #define PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS 0x157b #define PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS 0x157c +#define PCI_DEVICE_ID_INTEL_I225_UNPROGRAMMED 0x15dF +#define PCI_DEVICE_ID_INTEL_I225_IT 0x0d9f #define PCI_DEVICE_ID_INTEL_80960_RP 0x1960 #define PCI_DEVICE_ID_INTEL_82840_HB 0x1a21 #define PCI_DEVICE_ID_INTEL_82845_HB 0x1a30 diff --git a/include/phy.h b/include/phy.h index e02cbdb58c9..90b7e364101 100644 --- a/include/phy.h +++ b/include/phy.h @@ -9,6 +9,7 @@ #ifndef _PHY_H #define _PHY_H +#include <asm-generic/gpio.h> #include <log.h> #include <phy_interface.h> #include <dm/ofnode.h> @@ -76,6 +77,12 @@ struct mii_dev { int (*reset)(struct mii_dev *bus); struct phy_device *phymap[PHY_MAX_ADDR]; u32 phy_mask; + /** @reset_delay_us: Bus GPIO reset pulse width in microseconds */ + int reset_delay_us; + /** @reset_post_delay_us: Bus GPIO reset deassert delay in microseconds */ + int reset_post_delay_us; + /** @reset_gpiod: Bus Reset GPIO descriptor pointer */ + struct gpio_desc reset_gpiod; }; /* struct phy_driver: a structure which defines PHY behavior @@ -177,6 +184,15 @@ struct fixed_link { int phy_reset(struct phy_device *phydev); /** + * phy_gpio_reset() - Resets the specified PHY using GPIO reset + * Toggles the optional PHY reset GPIO + * + * @dev: PHY udevice to reset + * @return: 0 if OK, -ve on error + */ +int phy_gpio_reset(struct udevice *dev); + +/** * phy_find_by_mask() - Searches for a PHY on the specified MDIO bus * The function checks the PHY addresses flagged in phy_mask and returns a * phy_device pointer if it detects a PHY. diff --git a/include/power/rk8xx_pmic.h b/include/power/rk8xx_pmic.h index 3cbfc021956..31221aa46b6 100644 --- a/include/power/rk8xx_pmic.h +++ b/include/power/rk8xx_pmic.h @@ -183,7 +183,18 @@ enum { }; enum { + RK806_POWER_SLP_EN0 = 0x06, + RK806_POWER_SLP_EN1, + RK806_POWER_SLP_EN2, + RK806_REG_SYS_CFG3 = 0x72, + RK806_WDT_REG, + RK806_ON_SOURCE, + RK806_OFF_SOURCE +}; + +enum { RK805_ID = 0x8050, + RK806_ID = 0x8060, RK808_ID = 0x0000, RK809_ID = 0x8090, RK816_ID = 0x8160, @@ -201,6 +212,14 @@ enum { #define RK817_POWER_EN_SAVE0 0x99 #define RK817_POWER_EN_SAVE1 0xa4 +#define RK806_POWER_EN(x) (0x00 + (x)) +/* POWER_ENx register lower 4 bits are write-protected unless the associated top bit is set */ +#define RK806_POWER_EN_CLRSETBITS(bit, val) (((val) << (bit)) | (1 << ((bit) + 4))) + +#define RK806_POWER_SLP_EN(x) (0x06 + (x)) + +#define RK806_ID_MSB 0x5a +#define RK806_ID_LSB 0x5b #define RK817_ID_MSB 0xed #define RK817_ID_LSB 0xee #define RK8XX_ID_MSK 0xfff0 @@ -233,7 +252,5 @@ struct rk8xx_priv { }; int rk8xx_spl_configure_buck(struct udevice *pmic, int buck, int uvolt); -int rk818_spl_configure_usb_input_current(struct udevice *pmic, int current_ma); -int rk818_spl_configure_usb_chrg_shutdown(struct udevice *pmic, int uvolt); #endif diff --git a/include/reiserfs.h b/include/reiserfs.h deleted file mode 100644 index b61bb600679..00000000000 --- a/include/reiserfs.h +++ /dev/null @@ -1,72 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2000-2002 by Hans Reiser, licensing governed by reiserfs/README - * - * GRUB -- GRand Unified Bootloader - * Copyright (C) 2000, 2001 Free Software Foundation, Inc. - * - * (C) Copyright 2003 Sysgo Real-Time Solutions, AG <www.elinos.com> - * Pavel Bartusek <pba@sysgo.de> - */ - -/* An implementation for the ReiserFS filesystem ported from GRUB. - * Some parts of this code (mainly the structures and defines) are - * from the original reiser fs code, as found in the linux kernel. - */ - - -#define SECTOR_SIZE 0x200 -#define SECTOR_BITS 9 - -struct blk_desc; -struct disk_partition; - -/* Error codes */ -typedef enum -{ - ERR_NONE = 0, - ERR_BAD_FILENAME, - ERR_BAD_FILETYPE, - ERR_BAD_GZIP_DATA, - ERR_BAD_GZIP_HEADER, - ERR_BAD_PART_TABLE, - ERR_BAD_VERSION, - ERR_BELOW_1MB, - ERR_BOOT_COMMAND, - ERR_BOOT_FAILURE, - ERR_BOOT_FEATURES, - ERR_DEV_FORMAT, - ERR_DEV_VALUES, - ERR_EXEC_FORMAT, - ERR_FILELENGTH, - ERR_FILE_NOT_FOUND, - ERR_FSYS_CORRUPT, - ERR_FSYS_MOUNT, - ERR_GEOM, - ERR_NEED_LX_KERNEL, - ERR_NEED_MB_KERNEL, - ERR_NO_DISK, - ERR_NO_PART, - ERR_NUMBER_PARSING, - ERR_OUTSIDE_PART, - ERR_READ, - ERR_SYMLINK_LOOP, - ERR_UNRECOGNIZED, - ERR_WONT_FIT, - ERR_WRITE, - ERR_BAD_ARGUMENT, - ERR_UNALIGNED, - ERR_PRIVILEGED, - ERR_DEV_NEED_INIT, - ERR_NO_DISK_SPACE, - ERR_NUMBER_OVERFLOW, - - MAX_ERR_NUM -} reiserfs_error_t; - - -void reiserfs_set_blk_dev(struct blk_desc *rbdd, struct disk_partition *info); -extern int reiserfs_ls (char *dirname); -extern int reiserfs_open (char *filename); -extern int reiserfs_read (char *buf, unsigned len); -extern int reiserfs_mount (unsigned part_length); diff --git a/include/remoteproc.h b/include/remoteproc.h index 91a88791a47..6f8068e1496 100644 --- a/include/remoteproc.h +++ b/include/remoteproc.h @@ -403,6 +403,7 @@ enum rproc_mem_type { * @name: Platform-specific way of naming the Remote proc * @mem_type: one of 'enum rproc_mem_type' * @driver_plat_data: driver specific platform data that may be needed. + * @fw_name: firmware name * * This can be accessed with dev_get_uclass_plat() for any UCLASS_REMOTEPROC * device. @@ -412,6 +413,7 @@ struct dm_rproc_uclass_pdata { const char *name; enum rproc_mem_type mem_type; void *driver_plat_data; + char *fw_name; }; /** @@ -705,6 +707,34 @@ unsigned long rproc_parse_resource_table(struct udevice *dev, struct resource_table *rproc_find_resource_table(struct udevice *dev, unsigned int addr, int *tablesz); +/** + * rproc_set_firmware() - assign a new firmware name + * @rproc_dev: device for which new firmware name is being assigned + * @fw_name: new firmware name to be assigned + * + * This function allows remoteproc drivers or clients to configure a custom + * firmware name. The function does not trigger a remote processor boot, + * only sets the firmware name used for a subsequent boot. + * + * This function sets the fw_name field in uclass pdata of the Remote proc + * + * Return: 0 on success or a negative value upon failure + */ +int rproc_set_firmware(struct udevice *rproc_dev, const char *fw_name); + +/** + * rproc_boot() - boot a remote processor + * @rproc_dev: rproc device to boot + * + * Boot a remote processor (i.e. load its firmware, power it on, ...). + * + * This function first loads the firmware set in the uclass pdata of Remote + * processor to a buffer and then loads firmware to the remote processor + * using rproc_load(). + * + * Return: 0 on success, and an appropriate error value otherwise + */ +int rproc_boot(struct udevice *rproc_dev); #else static inline int rproc_init(void) { return -ENOSYS; } static inline int rproc_dev_init(int id) { return -ENOSYS; } @@ -744,6 +774,10 @@ static inline int rproc_elf_load_rsc_table(struct udevice *dev, ulong fw_addr, ulong fw_size, ulong *rsc_addr, ulong *rsc_size) { return -ENOSYS; } +static inline int rproc_set_firmware(struct udevice *rproc_dev, const char *fw_name) +{ return -ENOSYS; } +static inline int rproc_boot(struct udevice *rproc_dev) +{ return -ENOSYS; } #endif #endif /* _RPROC_H_ */ diff --git a/include/rng.h b/include/rng.h index 37af5543631..87e26f5647e 100644 --- a/include/rng.h +++ b/include/rng.h @@ -6,6 +6,8 @@ #if !defined _RNG_H_ #define _RNG_H_ +#include <linux/types.h> + struct udevice; /** diff --git a/include/smbios.h b/include/smbios.h index 3df8827b60d..a4fda9df7bd 100644 --- a/include/smbios.h +++ b/include/smbios.h @@ -108,6 +108,33 @@ struct __packed smbios_type0 { char eos[SMBIOS_STRUCT_EOS_BYTES]; }; +/** + * enum smbios_wakeup_type - wake-up type + * + * These constants are used for the Wake-Up Type field in the SMBIOS + * System Information (Type 1) structure. + */ +enum smbios_wakeup_type { + /** @SMBIOS_WAKEUP_TYPE_RESERVED: Reserved */ + SMBIOS_WAKEUP_TYPE_RESERVED, + /** @SMBIOS_WAKEUP_TYPE_OTHER: Other */ + SMBIOS_WAKEUP_TYPE_OTHER, + /** @SMBIOS_WAKEUP_TYPE_UNKNOWN: Unknown */ + SMBIOS_WAKEUP_TYPE_UNKNOWN, + /** @SMBIOS_WAKEUP_TYPE_APM_TIMER: APM Timer */ + SMBIOS_WAKEUP_TYPE_APM_TIMER, + /** @SMBIOS_WAKEUP_TYPE_MODEM_RING: Modem Ring */ + SMBIOS_WAKEUP_TYPE_MODEM_RING, + /** @SMBIOS_WAKEUP_TYPE_LAN_REMOTE: LAN Remote */ + SMBIOS_WAKEUP_TYPE_LAN_REMOTE, + /** @SMBIOS_WAKEUP_TYPE_POWER_SWITCH: Power Switch */ + SMBIOS_WAKEUP_TYPE_POWER_SWITCH, + /** @SMBIOS_WAKEUP_TYPE_PCI_PME: PCI PME# */ + SMBIOS_WAKEUP_TYPE_PCI_PME, + /** @SMBIOS_WAKEUP_TYPE_AC_POWER_RESTORED: AC Power Restored */ + SMBIOS_WAKEUP_TYPE_AC_POWER_RESTORED, +}; + struct __packed smbios_type1 { u8 type; u8 length; diff --git a/include/turris-omnia-mcu-interface.h b/include/turris-omnia-mcu-interface.h new file mode 100644 index 00000000000..3c4638f7329 --- /dev/null +++ b/include/turris-omnia-mcu-interface.h @@ -0,0 +1,248 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * CZ.NIC's Turris Omnia MCU I2C interface commands definitions + * + * 2023 by Marek Behún <kabel@kernel.org> + */ + +#ifndef __TURRIS_OMNIA_MCU_INTERFACE_H +#define __TURRIS_OMNIA_MCU_INTERFACE_H + +#include <linux/bitops.h> + +enum omnia_commands_e { + CMD_GET_STATUS_WORD = 0x01, /* slave sends status word back */ + CMD_GENERAL_CONTROL = 0x02, + CMD_LED_MODE = 0x03, /* default/user */ + CMD_LED_STATE = 0x04, /* LED on/off */ + CMD_LED_COLOR = 0x05, /* LED number + RED + GREEN + BLUE */ + CMD_USER_VOLTAGE = 0x06, + CMD_SET_BRIGHTNESS = 0x07, + CMD_GET_BRIGHTNESS = 0x08, + CMD_GET_RESET = 0x09, + CMD_GET_FW_VERSION_APP = 0x0A, /* 20B git hash number */ + CMD_SET_WATCHDOG_STATE = 0x0B, /* 0 - disable + * 1 - enable / ping + * after boot watchdog is started + * with 2 minutes timeout + */ + + /* CMD_WATCHDOG_STATUS = 0x0C, not implemented anymore */ + + CMD_GET_WATCHDOG_STATE = 0x0D, + CMD_GET_FW_VERSION_BOOT = 0x0E, /* 20B git hash number */ + CMD_GET_FW_CHECKSUM = 0x0F, /* 4B length, 4B checksum */ + + /* available if FEATURES_SUPPORTED bit set in status word */ + CMD_GET_FEATURES = 0x10, + + /* available if EXT_CMD bit set in features */ + CMD_GET_EXT_STATUS_DWORD = 0x11, + CMD_EXT_CONTROL = 0x12, + CMD_GET_EXT_CONTROL_STATUS = 0x13, + + /* available if NEW_INT_API bit set in features */ + CMD_GET_INT_AND_CLEAR = 0x14, + CMD_GET_INT_MASK = 0x15, + CMD_SET_INT_MASK = 0x16, + + /* available if FLASHING bit set in features */ + CMD_FLASH = 0x19, + + /* available if WDT_PING bit set in features */ + CMD_SET_WDT_TIMEOUT = 0x20, + CMD_GET_WDT_TIMELEFT = 0x21, + + /* available if POWEROFF_WAKEUP bit set in features */ + CMD_SET_WAKEUP = 0x22, + CMD_GET_UPTIME_AND_WAKEUP = 0x23, + CMD_POWER_OFF = 0x24, + + /* available if USB_OVC_PROT_SETTING bit set in features */ + CMD_SET_USB_OVC_PROT = 0x25, + CMD_GET_USB_OVC_PROT = 0x26, + + /* available if TRNG bit set in features */ + CMD_TRNG_COLLECT_ENTROPY = 0x28, + + /* available if CRYPTO bit set in features */ + CMD_CRYPTO_GET_PUBLIC_KEY = 0x29, + CMD_CRYPTO_SIGN_MESSAGE = 0x2A, + CMD_CRYPTO_COLLECT_SIGNATURE = 0x2B, + + /* available if BOARD_INFO it set in features */ + CMD_BOARD_INFO_GET = 0x2C, + CMD_BOARD_INFO_BURN = 0x2D, + + /* available only at address 0x2b (led-controller) */ + /* available only if LED_GAMMA_CORRECTION bit set in features */ + CMD_SET_GAMMA_CORRECTION = 0x30, + CMD_GET_GAMMA_CORRECTION = 0x31, + + /* available only at address 0x2b (led-controller) */ + /* available only if PER_LED_CORRECTION bit set in features */ + /* available only if FROM_BIT_16_INVALID bit NOT set in features */ + CMD_SET_LED_CORRECTIONS = 0x32, + CMD_GET_LED_CORRECTIONS = 0x33, +}; + +enum omnia_flashing_commands_e { + FLASH_CMD_UNLOCK = 0x01, + FLASH_CMD_SIZE_AND_CSUM = 0x02, + FLASH_CMD_PROGRAM = 0x03, + FLASH_CMD_RESET = 0x04, +}; + +enum omnia_sts_word_e { + STS_MCU_TYPE_MASK = GENMASK(1, 0), + STS_MCU_TYPE_STM32 = 0 << 0, + STS_MCU_TYPE_GD32 = 1 << 0, + STS_MCU_TYPE_MKL = 2 << 0, + STS_FEATURES_SUPPORTED = BIT(2), + STS_USER_REGULATOR_NOT_SUPPORTED = BIT(3), + STS_CARD_DET = BIT(4), + STS_MSATA_IND = BIT(5), + STS_USB30_OVC = BIT(6), + STS_USB31_OVC = BIT(7), + STS_USB30_PWRON = BIT(8), + STS_USB31_PWRON = BIT(9), + STS_ENABLE_4V5 = BIT(10), + STS_BUTTON_MODE = BIT(11), + STS_BUTTON_PRESSED = BIT(12), + STS_BUTTON_COUNTER_MASK = GENMASK(15, 13) +}; + +enum omnia_ctl_byte_e { + CTL_LIGHT_RST = BIT(0), + CTL_HARD_RST = BIT(1), + /* BIT(2) is currently reserved */ + CTL_USB30_PWRON = BIT(3), + CTL_USB31_PWRON = BIT(4), + CTL_ENABLE_4V5 = BIT(5), + CTL_BUTTON_MODE = BIT(6), + CTL_BOOTLOADER = BIT(7) +}; + +enum omnia_features_e { + FEAT_PERIPH_MCU = BIT(0), + FEAT_EXT_CMDS = BIT(1), + FEAT_WDT_PING = BIT(2), + FEAT_LED_STATE_EXT_MASK = GENMASK(4, 3), + FEAT_LED_STATE_EXT = 1 << 3, + FEAT_LED_STATE_EXT_V32 = 2 << 3, + FEAT_LED_GAMMA_CORRECTION = BIT(5), + FEAT_NEW_INT_API = BIT(6), + FEAT_BOOTLOADER = BIT(7), + FEAT_FLASHING = BIT(8), + FEAT_NEW_MESSAGE_API = BIT(9), + FEAT_BRIGHTNESS_INT = BIT(10), + FEAT_POWEROFF_WAKEUP = BIT(11), + FEAT_CAN_OLD_MESSAGE_API = BIT(12), + FEAT_TRNG = BIT(13), + FEAT_CRYPTO = BIT(14), + FEAT_BOARD_INFO = BIT(15), + + /* + * Orginally the features command replied only 16 bits. If more were + * read, either the I2C transaction failed or 0xff bytes were sent. + * Therefore to consider bits 16 - 31 valid, one bit (20) was reserved + * to be zero. + */ + + /* Bits 16 - 19 correspond to bits 0 - 3 of status word */ + FEAT_MCU_TYPE_MASK = GENMASK(17, 16), + FEAT_MCU_TYPE_STM32 = 0 << 16, + FEAT_MCU_TYPE_GD32 = 1 << 16, + FEAT_MCU_TYPE_MKL = 2 << 16, + FEAT_FEATURES_SUPPORTED = BIT(18), + FEAT_USER_REGULATOR_NOT_SUPPORTED = BIT(19), + + /* must not be set */ + FEAT_FROM_BIT_16_INVALID = BIT(20), + + FEAT_PER_LED_CORRECTION = BIT(21), + FEAT_USB_OVC_PROT_SETTING = BIT(22), +}; + +enum omnia_ext_sts_dword_e { + EXT_STS_SFP_nDET = BIT(0), + EXT_STS_LED_STATES_MASK = GENMASK(31, 12), + EXT_STS_WLAN0_MSATA_LED = BIT(12), + EXT_STS_WLAN1_LED = BIT(13), + EXT_STS_WLAN2_LED = BIT(14), + EXT_STS_WPAN0_LED = BIT(15), + EXT_STS_WPAN1_LED = BIT(16), + EXT_STS_WPAN2_LED = BIT(17), + EXT_STS_WAN_LED0 = BIT(18), + EXT_STS_WAN_LED1 = BIT(19), + EXT_STS_LAN0_LED0 = BIT(20), + EXT_STS_LAN0_LED1 = BIT(21), + EXT_STS_LAN1_LED0 = BIT(22), + EXT_STS_LAN1_LED1 = BIT(23), + EXT_STS_LAN2_LED0 = BIT(24), + EXT_STS_LAN2_LED1 = BIT(25), + EXT_STS_LAN3_LED0 = BIT(26), + EXT_STS_LAN3_LED1 = BIT(27), + EXT_STS_LAN4_LED0 = BIT(28), + EXT_STS_LAN4_LED1 = BIT(29), + EXT_STS_LAN5_LED0 = BIT(30), + EXT_STS_LAN5_LED1 = BIT(31), +}; + +enum omnia_ext_ctl_e { + EXT_CTL_nRES_MMC = BIT(0), + EXT_CTL_nRES_LAN = BIT(1), + EXT_CTL_nRES_PHY = BIT(2), + EXT_CTL_nPERST0 = BIT(3), + EXT_CTL_nPERST1 = BIT(4), + EXT_CTL_nPERST2 = BIT(5), + EXT_CTL_PHY_SFP = BIT(6), + EXT_CTL_PHY_SFP_AUTO = BIT(7), + EXT_CTL_nVHV_CTRL = BIT(8), +}; + +enum omnia_int_e { + INT_CARD_DET = BIT(0), + INT_MSATA_IND = BIT(1), + INT_USB30_OVC = BIT(2), + INT_USB31_OVC = BIT(3), + INT_BUTTON_PRESSED = BIT(4), + INT_SFP_nDET = BIT(5), + INT_BRIGHTNESS_CHANGED = BIT(6), + INT_TRNG = BIT(7), + INT_MESSAGE_SIGNED = BIT(8), + + INT_LED_STATES_MASK = GENMASK(31, 12), + INT_WLAN0_MSATA_LED = BIT(12), + INT_WLAN1_LED = BIT(13), + INT_WLAN2_LED = BIT(14), + INT_WPAN0_LED = BIT(15), + INT_WPAN1_LED = BIT(16), + INT_WPAN2_LED = BIT(17), + INT_WAN_LED0 = BIT(18), + INT_WAN_LED1 = BIT(19), + INT_LAN0_LED0 = BIT(20), + INT_LAN0_LED1 = BIT(21), + INT_LAN1_LED0 = BIT(22), + INT_LAN1_LED1 = BIT(23), + INT_LAN2_LED0 = BIT(24), + INT_LAN2_LED1 = BIT(25), + INT_LAN3_LED0 = BIT(26), + INT_LAN3_LED1 = BIT(27), + INT_LAN4_LED0 = BIT(28), + INT_LAN4_LED1 = BIT(29), + INT_LAN5_LED0 = BIT(30), + INT_LAN5_LED1 = BIT(31), +}; + +enum omnia_cmd_poweroff_e { + CMD_POWER_OFF_POWERON_BUTTON = BIT(0), + CMD_POWER_OFF_MAGIC = 0xdead, +}; + +enum cmd_usb_ovc_prot_e { + CMD_xET_USB_OVC_PROT_PORT_MASK = GENMASK(3, 0), + CMD_xET_USB_OVC_PROT_ENABLE = BIT(4), +}; + +#endif /* __TURRIS_OMNIA_MCU_INTERFACE_H */ diff --git a/include/u-boot/zlib.h b/include/u-boot/zlib.h index a33cc8780d3..ee19f460958 100644 --- a/include/u-boot/zlib.h +++ b/include/u-boot/zlib.h @@ -49,9 +49,6 @@ extern "C" { #endif -#define ZLIB_VERSION "1.2.3" -#define ZLIB_VERNUM 0x1230 - /* #include "zconf.h" */ /* included directly here */ /* zconf.h -- configuration of the zlib compression library * Copyright (C) 1995-2005 Jean-loup Gailly. @@ -484,7 +481,6 @@ typedef gz_header FAR *gz_headerp; #define Z_DATA_ERROR (-3) #define Z_MEM_ERROR (-4) #define Z_BUF_ERROR (-5) -#define Z_VERSION_ERROR (-6) /* Return codes for the compression/decompression functions. Negative * values are errors, positive values are used for special but normal events. */ @@ -523,11 +519,11 @@ typedef gz_header FAR *gz_headerp; ZEXTERN int ZEXPORT deflate OF((z_streamp strm, int flush)); ZEXTERN int ZEXPORT deflateInit_ OF((z_streamp strm, int level, - const char *version, int stream_size)); + int stream_size)); ZEXTERN int ZEXPORT deflateEnd OF((z_streamp strm)); ZEXTERN int ZEXPORT deflateInit2_ OF((z_streamp strm, int level, int method, int windowBits, int memLevel, - int strategy, const char *version, + int strategy, int stream_size)); ZEXTERN int ZEXPORT deflateReset OF((z_streamp strm)); ZEXTERN int ZEXPORT deflateSetDictionary OF((z_streamp strm, @@ -553,7 +549,7 @@ ZEXTERN int ZEXPORT deflateCopy OF((z_streamp dest, ZEXTERN int ZEXPORT inflateInit_ OF((z_streamp strm, - const char *version, int stream_size)); + int stream_size)); ZEXTERN int ZEXPORT inflate OF((z_streamp strm, int flush)); /* inflate decompresses as much data as possible, and stops when the input @@ -743,11 +739,11 @@ ZEXTERN int ZEXPORT uncompress2 OF((Bytef *dest, uLongf *destLen, */ ZEXTERN int ZEXPORT inflateInit2_ OF((z_streamp strm, int windowBits, - const char *version, int stream_size)); + int stream_size)); #define inflateInit(strm) \ - inflateInit_((strm), ZLIB_VERSION, sizeof(z_stream)) + inflateInit_((strm), sizeof(z_stream)) #define inflateInit2(strm, windowBits) \ - inflateInit2_((strm), (windowBits), ZLIB_VERSION, sizeof(z_stream)) + inflateInit2_((strm), (windowBits), sizeof(z_stream)) #if !defined(ZUTIL_H) && !defined(NO_DUMMY_DECL) struct internal_state {int dummy;}; /* hack for buggy compilers */ diff --git a/include/usb.h b/include/usb.h index 09e3f0cb309..3aafdc8bfd1 100644 --- a/include/usb.h +++ b/include/usb.h @@ -49,6 +49,12 @@ extern bool usb_started; /* flag for the started/stopped USB status */ */ #define USB_TIMEOUT_MS(pipe) (usb_pipebulk(pipe) ? 5000 : 1000) +/* + * The xhcd hcd driver prepares only a limited number interfaces / endpoints. + * Define this limit so that drivers do not exceed it. + */ +#define USB_MAX_ACTIVE_INTERFACES 2 + /* device request (setup) */ struct devrequest { __u8 requesttype; diff --git a/include/usb_mass_storage.h b/include/usb_mass_storage.h index 83ab93b530d..6d83d93cad7 100644 --- a/include/usb_mass_storage.h +++ b/include/usb_mass_storage.h @@ -7,7 +7,6 @@ #ifndef __USB_MASS_STORAGE_H__ #define __USB_MASS_STORAGE_H__ -#define SECTOR_SIZE 0x200 #include <part.h> #include <linux/usb/composite.h> diff --git a/include/video_console.h b/include/video_console.h index bde67fa9a5a..8b5928dc5eb 100644 --- a/include/video_console.h +++ b/include/video_console.h @@ -43,6 +43,7 @@ enum { * @col_saved: Saved X position, in fractional units (VID_TO_POS(x)) * @row_saved: Saved Y position in pixels (0=top) * @escape_buf: Buffer to accumulate escape sequence + * @utf8_buf: Buffer to accumulate UTF-8 byte sequence */ struct vidconsole_priv { struct stdio_dev sdev; @@ -66,6 +67,7 @@ struct vidconsole_priv { int row_saved; int col_saved; char escape_buf[32]; + char utf8_buf[5]; }; /** @@ -124,12 +126,12 @@ struct vidconsole_ops { * @x_frac: Fractional pixel X position (0=left-most pixel) which * is the X position multipled by VID_FRAC_DIV. * @y: Pixel Y position (0=top-most pixel) - * @ch: Character to write + * @cp: UTF-32 code point to write * @return number of fractional pixels that the cursor should move, * if all is OK, -EAGAIN if we ran out of space on this line, other -ve * on error */ - int (*putc_xy)(struct udevice *dev, uint x_frac, uint y, char ch); + int (*putc_xy)(struct udevice *dev, uint x_frac, uint y, int cp); /** * move_rows() - Move text rows from one place to another @@ -403,12 +405,12 @@ void vidconsole_pop_colour(struct udevice *dev, struct vidconsole_colour *old); * @x_frac: Fractional pixel X position (0=left-most pixel) which * is the X position multipled by VID_FRAC_DIV. * @y: Pixel Y position (0=top-most pixel) - * @ch: Character to write + * @cp: UTF-32 code point to write * Return: number of fractional pixels that the cursor should move, * if all is OK, -EAGAIN if we ran out of space on this line, other -ve * on error */ -int vidconsole_putc_xy(struct udevice *dev, uint x, uint y, char ch); +int vidconsole_putc_xy(struct udevice *dev, uint x, uint y, int cp); /** * vidconsole_move_rows() - Move text rows from one place to another |