diff options
Diffstat (limited to 'include')
90 files changed, 398 insertions, 1496 deletions
diff --git a/include/bcb.h b/include/bcb.h index 897e83d371f..5edb17aa47d 100644 --- a/include/bcb.h +++ b/include/bcb.h @@ -8,7 +8,7 @@ #ifndef __BCB_H__ #define __BCB_H__ -#if CONFIG_IS_ENABLED(CMD_BCB) +#if IS_ENABLED(CONFIG_CMD_BCB) int bcb_write_reboot_reason(int devnum, char *partp, const char *reasonp); #else #include <linux/errno.h> diff --git a/include/button.h b/include/button.h index 96e6b1901fc..207f4a0f4db 100644 --- a/include/button.h +++ b/include/button.h @@ -37,6 +37,14 @@ struct button_ops { * @return button state button_state_t, or -ve on error */ enum button_state_t (*get_state)(struct udevice *dev); + + /** + * get_code() - get linux event code of a button + * + * @dev: button device to change + * @return button code, or -ENODATA on error + */ + int (*get_code)(struct udevice *dev); }; #define button_get_ops(dev) ((struct button_ops *)(dev)->driver->ops) @@ -58,4 +66,12 @@ int button_get_by_label(const char *label, struct udevice **devp); */ enum button_state_t button_get_state(struct udevice *dev); +/** + * button_get_code() - get linux event code of a button + * + * @dev: button device to change + * @return button code, or -ve on error + */ +int button_get_code(struct udevice *dev); + #endif diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 1f473b5a150..5b477785174 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -47,7 +47,7 @@ #define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \ #devtypel #instance " " -#if CONFIG_IS_ENABLED(CMD_USB) +#if IS_ENABLED(CONFIG_CMD_USB) # define BOOT_TARGET_USB(func) func(USB, usb, 0) #else # define BOOT_TARGET_USB(func) diff --git a/include/configs/am62ax_evm.h b/include/configs/am62ax_evm.h index cdd639b9309..a18b1572b13 100644 --- a/include/configs/am62ax_evm.h +++ b/include/configs/am62ax_evm.h @@ -71,12 +71,12 @@ #define BOOTENV_DEV_NAME_TI_MMC(devtyeu, devtypel, instance) \ "ti_mmc " -#if CONFIG_IS_ENABLED(CMD_MMC) +#if IS_ENABLED(CONFIG_CMD_MMC) #define BOOT_TARGET_MMC(func) \ func(TI_MMC, ti_mmc, na) #else #define BOOT_TARGET_MMC(func) -#endif /* CONFIG_IS_ENABLED(CMD_MMC) */ +#endif /* IS_ENABLED(CONFIG_CMD_MMC) */ #define BOOT_TARGET_DEVICES(func) \ BOOT_TARGET_MMC(func) diff --git a/include/configs/am62x_evm.h b/include/configs/am62x_evm.h index 7fbefdece40..7bf07809b05 100644 --- a/include/configs/am62x_evm.h +++ b/include/configs/am62x_evm.h @@ -38,51 +38,8 @@ DISTRO_BOOT_DEV_PXE(func) \ DISTRO_BOOT_DEV_DHCP(func) -#define PARTS_DEFAULT \ - /* Linux partitions */ \ - "name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs}\0" - -/* U-Boot general configuration */ -#define EXTRA_ENV_AM625_BOARD_SETTINGS \ - "default_device_tree=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ - "findfdt=" \ - "setenv name_fdt ${default_device_tree};" \ - "setenv fdtfile ${name_fdt}\0" \ - "name_kern=Image\0" \ - "console=ttyS2,115200n8\0" \ - "args_all=setenv optargs ${optargs} earlycon=ns16550a,mmio32,0x02800000 " \ - "${mtdparts}\0" \ - "run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}\0" - -/* U-Boot MMC-specific configuration */ -#define EXTRA_ENV_AM625_BOARD_SETTINGS_MMC \ - "boot=mmc\0" \ - "mmcdev=1\0" \ - "bootpart=1:2\0" \ - "bootdir=/boot\0" \ - "rd_spec=-\0" \ - "init_mmc=run args_all args_mmc\0" \ - "get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${name_fdt}\0" \ - "get_overlay_mmc=" \ - "fdt address ${fdtaddr};" \ - "fdt resize 0x100000;" \ - "for overlay in $name_overlays;" \ - "do;" \ - "load mmc ${bootpart} ${dtboaddr} ${bootdir}/${overlay} && " \ - "fdt apply ${dtboaddr};" \ - "done;\0" \ - "get_kern_mmc=load mmc ${bootpart} ${loadaddr} " \ - "${bootdir}/${name_kern}\0" \ - "get_fit_mmc=load mmc ${bootpart} ${addr_fit} " \ - "${bootdir}/${name_fit}\0" \ - "partitions=" PARTS_DEFAULT - /* Incorporate settings into the U-Boot environment */ #define CFG_EXTRA_ENV_SETTINGS \ - DEFAULT_LINUX_BOOT_ENV \ - DEFAULT_MMC_TI_ARGS \ - EXTRA_ENV_AM625_BOARD_SETTINGS \ - EXTRA_ENV_AM625_BOARD_SETTINGS_MMC \ BOOTENV /* Now for the remaining common defines */ diff --git a/include/configs/apalis-imx8.h b/include/configs/apalis-imx8.h index 73d8d245a96..845705c86db 100644 --- a/include/configs/apalis-imx8.h +++ b/include/configs/apalis-imx8.h @@ -9,57 +9,51 @@ #include <asm/arch/imx-regs.h> #include <linux/sizes.h> -#define CFG_SYS_FSL_ESDHC_ADDR 0 -#define USDHC1_BASE_ADDR 0x5b010000 -#define USDHC2_BASE_ADDR 0x5b020000 - /* Networking */ #define MEM_LAYOUT_ENV_SETTINGS \ - "fdt_addr_r=0x84000000\0" \ - "kernel_addr_r=0x82000000\0" \ - "ramdisk_addr_r=0x94400000\0" \ - "scriptaddr=0x87000000\0" - + "fdt_addr_r=0x9d400000\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "kernel_comp_addr_r=0xf0000000\0" \ + "kernel_comp_size=0x08000000\0" \ + "ramdisk_addr_r=0x9d500000\0" \ + "scriptaddr=0x9d480000\0" + +/* Boot M4 */ +#define M4_BOOT_ENV \ + "m4_0_image=m4_0.bin\0" \ + "m4_1_image=m4_1.bin\0" \ + "loadm4image_0=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \ + "loadm4image_1=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_1_image}\0" \ + "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \ + "m4boot_1=run loadm4image_1; dcache flush; bootaux ${loadaddr} 1\0" \ + +/* Enable Distro Boot */ #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 2) \ func(MMC, mmc, 0) \ func(DHCP, dhcp, na) #include <config_distro_bootcmd.h> -#undef BOOTENV_RUN_NET_USB_START -#define BOOTENV_RUN_NET_USB_START "" /* Initial environment variables */ #define CFG_EXTRA_ENV_SETTINGS \ BOOTENV \ + M4_BOOT_ENV \ MEM_LAYOUT_ENV_SETTINGS \ - "boot_file=Image\0" \ "boot_script_dhcp=boot.scr\0" \ - "console=ttyLP1 earlycon\0" \ - "fdt_addr=0x83000000\0" \ - "fdt_file=fsl-imx8qm-apalis-eval.dtb\0" \ - "fdtfile=fsl-imx8qm-apalis-eval.dtb\0" \ - "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \ + "console=ttyLP1\0" \ + "fdt_board=eval\0" \ "initrd_addr=0x83800000\0" \ "initrd_high=0xffffffffffffffff\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=PARTUUID=${uuid} rootwait " \ - "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ - "mmcpart=1\0" \ - "panel=NULL\0" \ - "script=boot.scr\0" \ - "update_uboot=askenv confirm Did you load u-boot-dtb.imx (y/N)?; " \ + "setup=setenv setupargs console=tty1 console=${console},${baudrate} " \ + "consoleblank=0 earlycon\0" \ + "update_uboot=askenv confirm Did you load flash.bin resp. u-boot-dtb.imx (y/N)?; " \ "if test \"$confirm\" = \"y\"; then " \ "setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \ "${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x0 " \ "${blkcnt}; fi\0" -/* Link Definitions */ - -/* On Apalis iMX8 USDHC1 is eMMC, USDHC2 is 8-bit and USDHC3 is 4-bit MMC/SD */ -#define CFG_SYS_FSL_USDHC_NUM 3 - #define CFG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_2 0x880000000 diff --git a/include/configs/apple.h b/include/configs/apple.h index fe7d11bcdb3..0576bc04c94 100644 --- a/include/configs/apple.h +++ b/include/configs/apple.h @@ -9,13 +9,13 @@ "stdout=serial,vidconsole\0" \ "stderr=serial,vidconsole\0" -#if CONFIG_IS_ENABLED(CMD_NVME) +#if IS_ENABLED(CONFIG_CMD_NVME) #define BOOT_TARGET_NVME(func) func(NVME, nvme, 0) #else #define BOOT_TARGET_NVME(func) #endif -#if CONFIG_IS_ENABLED(CMD_USB) +#if IS_ENABLED(CONFIG_CMD_USB) #define BOOT_TARGET_USB(func) func(USB, usb, 0) #else #define BOOT_TARGET_USB(func) diff --git a/include/configs/bcm7260.h b/include/configs/bcm7260.h index 43edc91b101..dbe545c1759 100644 --- a/include/configs/bcm7260.h +++ b/include/configs/bcm7260.h @@ -10,8 +10,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CFG_SYS_NS16550_COM1 0xf040c000 - #define CFG_SYS_INIT_RAM_ADDR 0x10200000 #include "bcmstb.h" diff --git a/include/configs/bcm7445.h b/include/configs/bcm7445.h index 114337294e0..b59048d175b 100644 --- a/include/configs/bcm7445.h +++ b/include/configs/bcm7445.h @@ -10,8 +10,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CFG_SYS_NS16550_COM1 0xf040ab00 - #define CFG_SYS_INIT_RAM_ADDR 0x80200000 #include "bcmstb.h" diff --git a/include/configs/bcmstb.h b/include/configs/bcmstb.h index d1de3561af6..c9280927b3c 100644 --- a/include/configs/bcmstb.h +++ b/include/configs/bcmstb.h @@ -93,19 +93,6 @@ extern phys_addr_t prior_stage_fdt_address; */ /* - * NS16550 configuration. - */ -#define V_NS16550_CLK 81000000 - -#define CFG_SYS_NS16550_CLK V_NS16550_CLK - -/* - * Serial console configuration. - */ -#define CFG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ - 115200} - -/* * Informational display configuration. */ diff --git a/include/configs/colibri-imx8x.h b/include/configs/colibri-imx8x.h index 2de116c59da..3ec36aa773e 100644 --- a/include/configs/colibri-imx8x.h +++ b/include/configs/colibri-imx8x.h @@ -77,7 +77,6 @@ "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ "mmcpart=1\0" \ "panel=NULL\0" \ - "script=boot.scr\0" \ "update_uboot=askenv confirm Did you load u-boot-dtb.imx (y/N)?; " \ "if test \"$confirm\" = \"y\"; then " \ "setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \ diff --git a/include/configs/imx8mm-cl-iot-gate.h b/include/configs/imx8mm-cl-iot-gate.h index 2641d7bc960..09d87cf214b 100644 --- a/include/configs/imx8mm-cl-iot-gate.h +++ b/include/configs/imx8mm-cl-iot-gate.h @@ -30,7 +30,7 @@ EFI_GUID(0x0bf1165c, 0x1831, 0x4864, 0x94, 0x5e, \ 0xac, 0x3d, 0x38, 0x48, 0xf4, 0x99) -#if CONFIG_IS_ENABLED(CMD_MMC) +#if IS_ENABLED(CONFIG_CMD_MMC) # define BOOT_TARGET_MMC(func) \ func(MMC, mmc, 2) \ func(MMC, mmc, 0) @@ -38,7 +38,7 @@ # define BOOT_TARGET_MMC(func) #endif -#if CONFIG_IS_ENABLED(CMD_USB) +#if IS_ENABLED(CONFIG_CMD_USB) # define BOOT_TARGET_USB(func) func(USB, usb, 0) #else # define BOOT_TARGET_USB(func) diff --git a/include/configs/imx8mm_phg.h b/include/configs/imx8mm_phg.h new file mode 100644 index 00000000000..d2d7ffa0f5b --- /dev/null +++ b/include/configs/imx8mm_phg.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + */ + +#ifndef __IMX8MM_PHG_H +#define __IMX8MM_PHG_H + +#include <linux/sizes.h> +#include <linux/stringify.h> +#include <asm/arch/imx-regs.h> +#include <config_distro_bootcmd.h> + +#define CFG_SYS_UBOOT_BASE \ + (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + +#ifdef CONFIG_SPL_BUILD +/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ +#define CFG_MALLOC_F_ADDR 0x930000 +#endif + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 2) \ + func(DHCP, dhcp, na) + +#include <config_distro_bootcmd.h> + +/* Initial environment variables */ +#define CFG_EXTRA_ENV_SETTINGS BOOTENV + +/* Link Definitions */ + +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x200000 + +#define CFG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ + +#endif diff --git a/include/configs/imx8mn_beacon.h b/include/configs/imx8mn_beacon.h index bb3dfe3fa0d..1880d0311e4 100644 --- a/include/configs/imx8mn_beacon.h +++ b/include/configs/imx8mn_beacon.h @@ -80,7 +80,7 @@ #define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 -#if CONFIG_IS_ENABLED(IMX8MN_BEACON_2GB_LPDDR) +#if IS_ENABLED(CONFIG_IMX8MN_BEACON_2GB_LPDDR) #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ #else #define PHYS_SDRAM_SIZE 0x40000000 /* 1GB DDR */ diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h index 1fea5b72deb..1759318fdd3 100644 --- a/include/configs/imx8mp_evk.h +++ b/include/configs/imx8mp_evk.h @@ -46,9 +46,11 @@ #define CFG_SYS_INIT_RAM_SIZE 0x80000 -/* Totally 2GB DDR */ +/* Totally 6GB DDR */ #define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 -#define PHYS_SDRAM_SIZE 0x80000000 +#define PHYS_SDRAM_SIZE 0xC0000000 /* 3 GB */ +#define PHYS_SDRAM_2 0x100000000 +#define PHYS_SDRAM_2_SIZE 0xC0000000 /* 3 GB */ #endif diff --git a/include/configs/imx8mp_rsb3720.h b/include/configs/imx8mp_rsb3720.h index d4ab6a6207d..e577f60ae72 100644 --- a/include/configs/imx8mp_rsb3720.h +++ b/include/configs/imx8mp_rsb3720.h @@ -39,7 +39,7 @@ #endif -#if CONFIG_IS_ENABLED(CMD_MMC) +#if IS_ENABLED(CONFIG_CMD_MMC) # define BOOT_TARGET_MMC(func) \ func(MMC, mmc, 2) \ func(MMC, mmc, 1) diff --git a/include/configs/iot2050.h b/include/configs/iot2050.h index 7d087413362..cfff46ce339 100644 --- a/include/configs/iot2050.h +++ b/include/configs/iot2050.h @@ -19,7 +19,7 @@ #define EXTRA_ENV_IOT2050_BOARD_SETTINGS \ "usb_pgood_delay=900\0" -#if CONFIG_IS_ENABLED(CMD_USB) +#if IS_ENABLED(CONFIG_CMD_USB) # define BOOT_TARGET_USB(func) \ func(USB, usb, 0) \ func(USB, usb, 1) \ diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h index a7210b5cf3a..48b1cea6e39 100644 --- a/include/configs/j721e_evm.h +++ b/include/configs/j721e_evm.h @@ -161,7 +161,14 @@ # define BOOT_TARGET_DHCP(func) #endif +#ifdef CONFIG_CMD_USB +# define BOOT_TARGET_USB(func) func(USB, usb, 0) +#else +# define BOOT_TARGET_USB(func) +#endif + #define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_USB(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 0) \ BOOT_TARGET_PXE(func) \ diff --git a/include/configs/jethub.h b/include/configs/jethub.h index 35f85095aca..e22db4991de 100644 --- a/include/configs/jethub.h +++ b/include/configs/jethub.h @@ -12,6 +12,7 @@ #define BOOTENV_DEV_RESCUE(devtypeu, devtypel, instance) \ "bootcmd_rescue=" \ "if gpio input 10; then " \ + "run bootcmd_mmc0; " \ "run bootcmd_usb0;" \ "fi;\0" #else diff --git a/include/configs/km/km-mpc832x.h b/include/configs/km/km-mpc832x.h deleted file mode 100644 index f64c0eee1bb..00000000000 --- a/include/configs/km/km-mpc832x.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * System IO Config - */ -#define CFG_SYS_SICRL SICRL_IRQ_CKS - -#define CFG_SYS_DDRCDR (\ - DDRCDR_EN | \ - DDRCDR_PZ_MAXZ | \ - DDRCDR_NZ_MAXZ | \ - DDRCDR_M_ODR) - -#define CFG_SYS_DDR_CS0_BNDS 0x0000007f -#define CFG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ - SDRAM_CFG_32_BE | \ - SDRAM_CFG_SREN | \ - SDRAM_CFG_HSE) - -#define CFG_SYS_DDR_SDRAM_CFG2 0x00401000 -#define CFG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) -#define CFG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ - (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) - -#define CFG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ - CSCONFIG_ODT_WR_CFG | \ - CSCONFIG_ROW_BIT_13 | \ - CSCONFIG_COL_BIT_10) - -#define CFG_SYS_DDR_MODE 0x47860242 -#define CFG_SYS_DDR_MODE2 0x8080c000 - -#define CFG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ - (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ - (0 << TIMING_CFG0_WWT_SHIFT) | \ - (0 << TIMING_CFG0_RRT_SHIFT) | \ - (0 << TIMING_CFG0_WRT_SHIFT) | \ - (0 << TIMING_CFG0_RWT_SHIFT)) - -#define CFG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ - (2 << TIMING_CFG1_WRTORD_SHIFT) | \ - (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ - (3 << TIMING_CFG1_WRREC_SHIFT) | \ - (7 << TIMING_CFG1_REFREC_SHIFT) | \ - (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ - (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ - (3 << TIMING_CFG1_PRETOACT_SHIFT)) - -#define CFG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ - (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ - (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ - (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ - (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ - (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ - (5 << TIMING_CFG2_CPO_SHIFT)) - -#define CFG_SYS_DDR_TIMING_3 0x00000000 - -#define CFG_SYS_KMBEC_FPGA_BASE 0xE8000000 -#define CFG_SYS_KMBEC_FPGA_SIZE 128 diff --git a/include/configs/km/km-mpc8360.h b/include/configs/km/km-mpc8360.h deleted file mode 100644 index 04d3d352ee2..00000000000 --- a/include/configs/km/km-mpc8360.h +++ /dev/null @@ -1,68 +0,0 @@ -/* KMBEC FPGA (PRIO) */ -#define CFG_SYS_KMBEC_FPGA_BASE 0xE8000000 -#define CFG_SYS_KMBEC_FPGA_SIZE 64 - -/* - * High Level Configuration Options - */ - -/* - * System IO Setup - */ -#define CFG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI) - -/** - * DDR RAM settings - */ -#define CFG_SYS_DDR_SDRAM_CFG (\ - SDRAM_CFG_SDRAM_TYPE_DDR2 | \ - SDRAM_CFG_SREN | \ - SDRAM_CFG_HSE) - -#define CFG_SYS_DDR_SDRAM_CFG2 0x00401000 - -#define CFG_SYS_DDR_CLK_CNTL (\ - DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) - -#define CFG_SYS_DDR_INTERVAL (\ - (0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ - (0x203 << SDRAM_INTERVAL_REFINT_SHIFT)) - -#define CFG_SYS_DDR_CS0_BNDS 0x0000007f - -#define CFG_SYS_DDRCDR (\ - DDRCDR_EN | \ - DDRCDR_Q_DRN) -#define CFG_SYS_DDR_MODE 0x47860452 -#define CFG_SYS_DDR_MODE2 0x8080c000 - -#define CFG_SYS_DDR_TIMING_0 (\ - (2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ - (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ - (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ - (0 << TIMING_CFG0_WWT_SHIFT) | \ - (0 << TIMING_CFG0_RRT_SHIFT) | \ - (0 << TIMING_CFG0_WRT_SHIFT) | \ - (0 << TIMING_CFG0_RWT_SHIFT)) - -#define CFG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \ - (2 << TIMING_CFG1_WRTORD_SHIFT) | \ - (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ - (3 << TIMING_CFG1_WRREC_SHIFT) | \ - (7 << TIMING_CFG1_REFREC_SHIFT) | \ - (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ - (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ - (3 << TIMING_CFG1_PRETOACT_SHIFT)) - -#define CFG_SYS_DDR_TIMING_2 (\ - (0xa << TIMING_CFG2_FOUR_ACT_SHIFT) | \ - (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ - (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ - (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ - (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ - (5 << TIMING_CFG2_CPO_SHIFT) | \ - (0 << TIMING_CFG2_ADD_LAT_SHIFT)) - -#define CFG_SYS_DDR_TIMING_3 0x00000000 - diff --git a/include/configs/km/km-mpc83xx.h b/include/configs/km/km-mpc83xx.h index c939caf2a1f..21f707aaf83 100644 --- a/include/configs/km/km-mpc83xx.h +++ b/include/configs/km/km-mpc83xx.h @@ -1,10 +1,4 @@ /* - * Internal Definitions - */ -#include <linux/stringify.h> -#define BOOTFLASH_START 0xF0000000 - -/* * DDR Setup */ #define CFG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ @@ -12,13 +6,6 @@ #define CFG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) -#define CFG_83XX_DDR_USES_CS0 - -/* - * Manually set up DDR parameters - */ -#define CFG_SYS_SDRAM_SIZE 0x80000000 /* 2048 MiB */ - /* * The reserved memory */ @@ -48,10 +35,34 @@ #define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE } +#define CFG_SYS_KMBEC_FPGA_BASE 0xE8000000 + #if defined(CONFIG_CMD_NAND) #define CFG_SYS_NAND_BASE CFG_SYS_KMBEC_FPGA_BASE #endif +#if defined(CONFIG_TARGET_KMCOGE5NE) || defined(CONFIG_TARGET_KMETER1) +/* + * System IO Setup + */ +#define CFG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI) + +#define CFG_SYS_DDRCDR (\ + DDRCDR_EN | \ + DDRCDR_Q_DRN) +#else +/* + * System IO Config + */ +#define CFG_SYS_SICRL SICRL_IRQ_CKS + +#define CFG_SYS_DDRCDR (\ + DDRCDR_EN | \ + DDRCDR_PZ_MAXZ | \ + DDRCDR_NZ_MAXZ | \ + DDRCDR_M_ODR) +#endif + /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is diff --git a/include/configs/kmtepr2.h b/include/configs/km832x.h index d6a3844bcc5..69c28c20358 100644 --- a/include/configs/kmtepr2.h +++ b/include/configs/km832x.h @@ -22,6 +22,5 @@ /* include common defines/options for all Keymile boards */ #include "km/km-mpc83xx.h" -#include "km/km-mpc832x.h" #endif /* __CONFIG_H */ diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h index d52f45ba911..7835332fc01 100644 --- a/include/configs/kmcoge5ne.h +++ b/include/configs/kmcoge5ne.h @@ -13,7 +13,6 @@ /* include common defines/options for all Keymile boards */ #include "km/km-mpc83xx.h" -#include "km/km-mpc8360.h" /** * KMCOGE5NE has 512 MB RAM diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index 6f67e5a98ab..f9be06fd259 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -10,7 +10,6 @@ /* include common defines/options for all Keymile boards */ #include "km/km-mpc83xx.h" -#include "km/km-mpc8360.h" #define CFG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ CSCONFIG_ROW_BIT_13 | \ diff --git a/include/configs/kmopti2.h b/include/configs/kmopti2.h deleted file mode 100644 index d6a3844bcc5..00000000000 --- a/include/configs/kmopti2.h +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2006 Freescale Semiconductor, Inc. - * Dave Liu <daveliu@freescale.com> - * - * Copyright (C) 2007 Logic Product Development, Inc. - * Peter Barada <peterb@logicpd.com> - * - * Copyright (C) 2007 MontaVista Software, Inc. - * Anton Vorontsov <avorontsov@ru.mvista.com> - * - * (C) Copyright 2008 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * (C) Copyright 2010-2013 - * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com - * Holger Brunck, Keymile GmbH, holger.bruncl@keymile.com - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* include common defines/options for all Keymile boards */ -#include "km/km-mpc83xx.h" -#include "km/km-mpc832x.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h deleted file mode 100644 index d6a3844bcc5..00000000000 --- a/include/configs/kmsupx5.h +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2006 Freescale Semiconductor, Inc. - * Dave Liu <daveliu@freescale.com> - * - * Copyright (C) 2007 Logic Product Development, Inc. - * Peter Barada <peterb@logicpd.com> - * - * Copyright (C) 2007 MontaVista Software, Inc. - * Anton Vorontsov <avorontsov@ru.mvista.com> - * - * (C) Copyright 2008 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * (C) Copyright 2010-2013 - * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com - * Holger Brunck, Keymile GmbH, holger.bruncl@keymile.com - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* include common defines/options for all Keymile boards */ -#include "km/km-mpc83xx.h" -#include "km/km-mpc832x.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index 0b8233de8c4..3db8e09b42a 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -21,8 +21,4 @@ #include <asm/arch/imx-regs.h> #include <asm/mach-imx/gpio.h> -/* Miscellaneous configurable options */ - -/* MMC */ - #endif diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index 635ae78abcb..98b743b9364 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -13,7 +13,7 @@ #include "mx6_common.h" #include <asm/mach-imx/gpio.h> -#define is_mx6ul_9x9_evk() CONFIG_IS_ENABLED(TARGET_MX6UL_9X9_EVK) +#define is_mx6ul_9x9_evk() IS_ENABLED(CONFIG_TARGET_MX6UL_9X9_EVK) #define CFG_MXC_UART_BASE UART1_BASE diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h index a542839ce1d..d0718bfa03e 100644 --- a/include/configs/mx7_common.h +++ b/include/configs/mx7_common.h @@ -16,16 +16,4 @@ /* Timer settings */ #define CFG_SC_TIMER_CLK 8000000 /* 8Mhz */ -/* Miscellaneous configurable options */ - -/* UART */ - -/* MMC */ - -/* - * If we have defined the OPTEE ram size and not OPTEE it means that we were - * launched by OPTEE, because of that we shall skip all the low level - * initialization since it was already done by ATF or OPTEE - */ - #endif diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index 5774184300c..096e5bbe663 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -97,9 +97,6 @@ #define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE -/* PMIC */ -#define CFG_POWER_PFUZE3000_I2C_ADDR 0x08 - /* FLASH and environment organization */ /* Environment starts at 768k = 768 * 1024 = 786432 */ diff --git a/include/configs/qemu-arm.h b/include/configs/qemu-arm.h index 45bd94ee5c7..e296f398798 100644 --- a/include/configs/qemu-arm.h +++ b/include/configs/qemu-arm.h @@ -6,84 +6,9 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include <linux/sizes.h> - /* Physical memory map */ - #define CFG_SYS_SDRAM_BASE 0x40000000 -/* GUIDs for capsule updatable firmware images */ -#define QEMU_ARM_UBOOT_IMAGE_GUID \ - EFI_GUID(0xf885b085, 0x99f8, 0x45af, 0x84, 0x7d, \ - 0xd5, 0x14, 0x10, 0x7a, 0x4a, 0x2c) - -#define QEMU_ARM64_UBOOT_IMAGE_GUID \ - EFI_GUID(0x058b7d83, 0x50d5, 0x4c47, 0xa1, 0x95, \ - 0x60, 0xd8, 0x6a, 0xd3, 0x41, 0xc4) - -/* Try files from QEMU's -kernel/-initrd, through the QEMU firmware device. */ -#define BOOTENV_DEV_QFW(devtypeu, devtypel, instance) \ - "bootcmd_qfw= " \ - "if qfw load $kernel_addr_r $ramdisk_addr_r; then " \ - " booti $kernel_addr_r $ramdisk_addr_r:$filesize $fdtcontroladdr; " \ - " if test $? -eq 1; then " \ - " bootz $kernel_addr_r $ramdisk_addr_r:$filesize $fdtcontroladdr; " \ - " fi ; " \ - "fi\0" -#define BOOTENV_DEV_NAME_QFW(devtypeu, devtypel, instance) "qfw " - /* For timer, QEMU emulates an ARMv7/ARMv8 architected timer */ -/* Environment options */ - -#if CONFIG_IS_ENABLED(CMD_USB) -# define BOOT_TARGET_USB(func) func(USB, usb, 0) -#else -# define BOOT_TARGET_USB(func) -#endif - -#if CONFIG_IS_ENABLED(CMD_SCSI) -# define BOOT_TARGET_SCSI(func) func(SCSI, scsi, 0) -#else -# define BOOT_TARGET_SCSI(func) -#endif - -#if CONFIG_IS_ENABLED(CMD_VIRTIO) -# define BOOT_TARGET_VIRTIO(func) func(VIRTIO, virtio, 0) -#else -# define BOOT_TARGET_VIRTIO(func) -#endif - -#if CONFIG_IS_ENABLED(CMD_NVME) -# define BOOT_TARGET_NVME(func) func(NVME, nvme, 0) -#else -# define BOOT_TARGET_NVME(func) -#endif - -#if CONFIG_IS_ENABLED(CMD_DHCP) -# define BOOT_TARGET_DHCP(func) func(DHCP, dhcp, na) -#else -# define BOOT_TARGET_DHCP(func) -#endif - -#define BOOT_TARGET_DEVICES(func) \ - func(QFW, qfw, na) \ - BOOT_TARGET_USB(func) \ - BOOT_TARGET_SCSI(func) \ - BOOT_TARGET_VIRTIO(func) \ - BOOT_TARGET_NVME(func) \ - BOOT_TARGET_DHCP(func) - -#include <config_distro_bootcmd.h> - -#define CFG_EXTRA_ENV_SETTINGS \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "fdt_addr=0x40000000\0" \ - "scriptaddr=0x40200000\0" \ - "pxefile_addr_r=0x40300000\0" \ - "kernel_addr_r=0x40400000\0" \ - "ramdisk_addr_r=0x44000000\0" \ - BOOTENV - #endif /* __CONFIG_H */ diff --git a/include/configs/rockchip-common.h b/include/configs/rockchip-common.h index 0b23e4c0433..ff8123dabd6 100644 --- a/include/configs/rockchip-common.h +++ b/include/configs/rockchip-common.h @@ -12,7 +12,7 @@ #ifndef CONFIG_SPL_BUILD /* First try to boot from SD (index 1), then eMMC (index 0) */ -#if CONFIG_IS_ENABLED(CMD_MMC) +#if IS_ENABLED(CONFIG_CMD_MMC) #define BOOT_TARGET_MMC(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 0) @@ -20,19 +20,19 @@ #define BOOT_TARGET_MMC(func) #endif -#if CONFIG_IS_ENABLED(CMD_NVME) +#if IS_ENABLED(CONFIG_CMD_NVME) #define BOOT_TARGET_NVME(func) func(NVME, nvme, 0) #else #define BOOT_TARGET_NVME(func) #endif -#if CONFIG_IS_ENABLED(CMD_SCSI) +#if IS_ENABLED(CONFIG_CMD_SCSI) #define BOOT_TARGET_SCSI(func) func(SCSI, scsi, 0) #else #define BOOT_TARGET_SCSI(func) #endif -#if CONFIG_IS_ENABLED(CMD_USB) +#if IS_ENABLED(CONFIG_CMD_USB) #define BOOT_TARGET_USB(func) func(USB, usb, 0) #else #define BOOT_TARGET_USB(func) @@ -50,7 +50,7 @@ #define BOOT_TARGET_DHCP(func) #endif -#if CONFIG_IS_ENABLED(CMD_SF) +#if IS_ENABLED(CONFIG_CMD_SF) #define BOOT_TARGET_SF(func) func(SF, sf, 0) #else #define BOOT_TARGET_SF(func) diff --git a/include/configs/rpi.h b/include/configs/rpi.h index c3f8e7bf85c..4da982f7357 100644 --- a/include/configs/rpi.h +++ b/include/configs/rpi.h @@ -122,7 +122,7 @@ "fdt_addr_r=0x02600000\0" \ "ramdisk_addr_r=0x02700000\0" -#if CONFIG_IS_ENABLED(CMD_MMC) +#if IS_ENABLED(CONFIG_CMD_MMC) #define BOOT_TARGET_MMC(func) \ func(MMC, mmc, 0) \ func(MMC, mmc, 1) \ @@ -131,7 +131,7 @@ #define BOOT_TARGET_MMC(func) #endif -#if CONFIG_IS_ENABLED(CMD_USB) +#if IS_ENABLED(CONFIG_CMD_USB) #define BOOT_TARGET_USB(func) func(USB, usb, 0) #else #define BOOT_TARGET_USB(func) diff --git a/include/configs/sifive-unmatched.h b/include/configs/sifive-unmatched.h index 24904aa2387..74150b7d4b0 100644 --- a/include/configs/sifive-unmatched.h +++ b/include/configs/sifive-unmatched.h @@ -17,6 +17,7 @@ #define BOOT_TARGET_DEVICES(func) \ func(NVME, nvme, 0) \ + func(NVME, nvme, 1) \ func(USB, usb, 0) \ func(MMC, mmc, 0) \ func(SCSI, scsi, 0) \ diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 2b35be83ec6..64cc17ca7ca 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -66,10 +66,9 @@ * Flash on the LocalBus */ #define CFG_SYS_FLASH0 0xFE000000 -#define CFG_SYS_FLASH1 0xFC000000 -#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH1, CFG_SYS_FLASH0 } +#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH0 } -#define CFG_SYS_LBC_FLASH_BASE CFG_SYS_FLASH1 /* Localbus flash start */ +#define CFG_SYS_LBC_FLASH_BASE CFG_SYS_FLASH0 /* Localbus flash start */ #define CFG_SYS_FLASH_BASE CFG_SYS_LBC_FLASH_BASE /* start of FLASH */ #define CFG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ @@ -110,61 +109,7 @@ */ #define CFG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#define CFG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consdev=ttyS0\0" \ - "uboot_file=/home/tftp/syscon3/u-boot.bin\0" \ - "bootfile=/home/tftp/syscon3/uImage\0" \ - "fdt_file=/home/tftp/syscon3/socrates.dtb\0" \ - "initrd_file=/home/tftp/syscon3/uinitrd.gz\0" \ - "uboot_addr=FFF60000\0" \ - "kernel_addr=FE000000\0" \ - "fdt_addr=FE1E0000\0" \ - "ramdisk_addr=FE200000\0" \ - "fdt_addr_r=B00000\0" \ - "kernel_addr_r=200000\0" \ - "ramdisk_addr_r=400000\0" \ - "rootpath=/opt/eldk/ppc_85xxDP\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath\0" \ - "addcons=setenv bootargs $bootargs " \ - "console=$consdev,$baudrate\0" \ - "addip=setenv bootargs $bootargs " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask" \ - ":$hostname:$netdev:off panic=1\0" \ - "boot_nor=run ramargs addcons;" \ - "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ - "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ - "tftp ${fdt_addr_r} ${fdt_file}; " \ - "run nfsargs addip addcons;" \ - "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ - "update_uboot=tftp 100000 ${uboot_file};" \ - "protect off fff60000 ffffffff;" \ - "era fff60000 ffffffff;" \ - "cp.b 100000 fff60000 ${filesize};" \ - "setenv filesize;saveenv\0" \ - "update_kernel=tftp 100000 ${bootfile};" \ - "era fe000000 fe1dffff;" \ - "cp.b 100000 fe000000 ${filesize};" \ - "setenv filesize;saveenv\0" \ - "update_fdt=tftp 100000 ${fdt_file};" \ - "era fe1e0000 fe1fffff;" \ - "cp.b 100000 fe1e0000 ${filesize};" \ - "setenv filesize;saveenv\0" \ - "update_initrd=tftp 100000 ${initrd_file};" \ - "era fe200000 fe9fffff;" \ - "cp.b 100000 fe200000 ${filesize};" \ - "setenv filesize;saveenv\0" \ - "clean_data=era fea00000 fff5ffff\0" \ - "usbargs=setenv bootargs root=/dev/sda1 rw\0" \ - "load_usb=usb start;" \ - "ext2load usb 0:1 ${kernel_addr_r} /boot/uImage\0" \ - "boot_usb=run load_usb usbargs addcons;" \ - "bootm ${kernel_addr_r} - ${fdt_addr};" \ - "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ - "" +#define CFG_ENV_FLAGS_LIST_STATIC "ethaddr:mw,eth1addr:mw,system1_addr:xw,serial#:sw,ethact:sw,ethprime:sw" /* pass open firmware flat tree */ diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h index 0fdb5a81605..991ffbb7dff 100644 --- a/include/configs/tegra-common-post.h +++ b/include/configs/tegra-common-post.h @@ -7,7 +7,7 @@ #ifndef __TEGRA_COMMON_POST_H #define __TEGRA_COMMON_POST_H -#if CONFIG_IS_ENABLED(CMD_USB) +#if IS_ENABLED(CONFIG_CMD_USB) # define BOOT_TARGET_USB(func) func(USB, usb, 0) #else # define BOOT_TARGET_USB(func) diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index bde7ffce008..c558679d044 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -15,12 +15,6 @@ #include <asm/arch/tegra.h> /* get chip and board defs */ -/* Use the Tegra US timer on ARMv7, but the architected timer on ARMv8. */ -#ifndef CONFIG_ARM64 -#define CFG_SYS_TIMER_RATE 1000000 -#define CFG_SYS_TIMER_COUNTER NV_PA_TMRUS_BASE -#endif - /* Environment */ /* diff --git a/include/configs/tuge1.h b/include/configs/tuge1.h deleted file mode 100644 index d6a3844bcc5..00000000000 --- a/include/configs/tuge1.h +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2006 Freescale Semiconductor, Inc. - * Dave Liu <daveliu@freescale.com> - * - * Copyright (C) 2007 Logic Product Development, Inc. - * Peter Barada <peterb@logicpd.com> - * - * Copyright (C) 2007 MontaVista Software, Inc. - * Anton Vorontsov <avorontsov@ru.mvista.com> - * - * (C) Copyright 2008 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * (C) Copyright 2010-2013 - * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com - * Holger Brunck, Keymile GmbH, holger.bruncl@keymile.com - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* include common defines/options for all Keymile boards */ -#include "km/km-mpc83xx.h" -#include "km/km-mpc832x.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h deleted file mode 100644 index d6a3844bcc5..00000000000 --- a/include/configs/tuxx1.h +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2006 Freescale Semiconductor, Inc. - * Dave Liu <daveliu@freescale.com> - * - * Copyright (C) 2007 Logic Product Development, Inc. - * Peter Barada <peterb@logicpd.com> - * - * Copyright (C) 2007 MontaVista Software, Inc. - * Anton Vorontsov <avorontsov@ru.mvista.com> - * - * (C) Copyright 2008 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * (C) Copyright 2010-2013 - * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com - * Holger Brunck, Keymile GmbH, holger.bruncl@keymile.com - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* include common defines/options for all Keymile boards */ -#include "km/km-mpc83xx.h" -#include "km/km-mpc832x.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h index 80386414f89..4ecd71f9653 100644 --- a/include/configs/udoo_neo.h +++ b/include/configs/udoo_neo.h @@ -53,16 +53,10 @@ #include <config_distro_bootcmd.h> -/* Miscellaneous configurable options */ - /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE -/* PMIC */ -#define CFG_POWER_PFUZE3000_I2C_ADDR 0x08 -#define PFUZE3000_I2C_BUS 0 - #endif /* __CONFIG_H */ diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h index fa9865602d8..3f6b0843c58 100644 --- a/include/dm/ofnode.h +++ b/include/dm/ofnode.h @@ -975,6 +975,18 @@ int ofnode_decode_display_timing(ofnode node, int index, struct display_timing *config); /** + * ofnode_decode_panel_timing() - decode display timings + * + * Decode panel timings from the supplied 'panel-timings' node. + * + * @node: 'display-timing' node containing the timing subnodes + * @config: Place to put timings + * Return: 0 if OK, -FDT_ERR_NOTFOUND if not found + */ +int ofnode_decode_panel_timing(ofnode node, + struct display_timing *config); + +/** * ofnode_get_property() - get a pointer to the value of a node property * * @node: node to read diff --git a/include/dm/read.h b/include/dm/read.h index cc4f16196fd..56ac076c9f1 100644 --- a/include/dm/read.h +++ b/include/dm/read.h @@ -785,6 +785,20 @@ int dev_decode_display_timing(const struct udevice *dev, int index, struct display_timing *config); /** + * dev_decode_panel_timing() - decode panel timings + * + * Decode display timings from the supplied 'panel-timings' node. + * + * @dev: device to read DT display timings from. The node linked to the device + * contains a child node called 'display-timings' which in turn contains + * one or more display timing nodes. + * @config: place to put timings + * Return: 0 if OK, -FDT_ERR_NOTFOUND if not found + */ +int dev_decode_panel_timing(const struct udevice *dev, + struct display_timing *config); + +/** * dev_get_phy_node() - Get PHY node for a MAC (if not fixed-link) * * This function parses PHY handle from the Ethernet controller's ofnode @@ -1183,6 +1197,12 @@ static inline int dev_decode_display_timing(const struct udevice *dev, return ofnode_decode_display_timing(dev_ofnode(dev), index, config); } +static inline int dev_decode_panel_timing(const struct udevice *dev, + struct display_timing *config) +{ + return ofnode_decode_panel_timing(dev_ofnode(dev), config); +} + static inline ofnode dev_get_phy_node(const struct udevice *dev) { return ofnode_get_phy_node(dev_ofnode(dev)); diff --git a/include/dt-bindings/clock/r8a774a1-cpg-mssr.h b/include/dt-bindings/clock/r8a774a1-cpg-mssr.h index 67bf8cdf496..e355363f40c 100644 --- a/include/dt-bindings/clock/r8a774a1-cpg-mssr.h +++ b/include/dt-bindings/clock/r8a774a1-cpg-mssr.h @@ -1,6 +1,6 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2019 Renesas Electronics Corp. +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2018 Renesas Electronics Corp. */ #ifndef __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__ #define __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__ diff --git a/include/dt-bindings/clock/r8a774b1-cpg-mssr.h b/include/dt-bindings/clock/r8a774b1-cpg-mssr.h index 28e0f8f76ca..1355451b74b 100644 --- a/include/dt-bindings/clock/r8a774b1-cpg-mssr.h +++ b/include/dt-bindings/clock/r8a774b1-cpg-mssr.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 * - * Copyright (C) 2020 Renesas Electronics Corp. + * Copyright (C) 2019 Renesas Electronics Corp. */ #ifndef __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__ #define __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__ diff --git a/include/dt-bindings/clock/r8a774c0-cpg-mssr.h b/include/dt-bindings/clock/r8a774c0-cpg-mssr.h index 9db5c76e23f..8ad9cd6be8e 100644 --- a/include/dt-bindings/clock/r8a774c0-cpg-mssr.h +++ b/include/dt-bindings/clock/r8a774c0-cpg-mssr.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2020 Renesas Electronics Corp. + * Copyright (C) 2018 Renesas Electronics Corp. */ #ifndef __DT_BINDINGS_CLOCK_R8A774C0_CPG_MSSR_H__ #define __DT_BINDINGS_CLOCK_R8A774C0_CPG_MSSR_H__ diff --git a/include/dt-bindings/clock/r8a77961-cpg-mssr.h b/include/dt-bindings/clock/r8a77961-cpg-mssr.h new file mode 100644 index 00000000000..7921d785546 --- /dev/null +++ b/include/dt-bindings/clock/r8a77961-cpg-mssr.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * + * Copyright (C) 2019 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R8A77961_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R8A77961_CPG_MSSR_H__ + +#include <dt-bindings/clock/renesas-cpg-mssr.h> + +/* r8a77961 CPG Core Clocks */ +#define R8A77961_CLK_Z 0 +#define R8A77961_CLK_Z2 1 +#define R8A77961_CLK_ZR 2 +#define R8A77961_CLK_ZG 3 +#define R8A77961_CLK_ZTR 4 +#define R8A77961_CLK_ZTRD2 5 +#define R8A77961_CLK_ZT 6 +#define R8A77961_CLK_ZX 7 +#define R8A77961_CLK_S0D1 8 +#define R8A77961_CLK_S0D2 9 +#define R8A77961_CLK_S0D3 10 +#define R8A77961_CLK_S0D4 11 +#define R8A77961_CLK_S0D6 12 +#define R8A77961_CLK_S0D8 13 +#define R8A77961_CLK_S0D12 14 +#define R8A77961_CLK_S1D1 15 +#define R8A77961_CLK_S1D2 16 +#define R8A77961_CLK_S1D4 17 +#define R8A77961_CLK_S2D1 18 +#define R8A77961_CLK_S2D2 19 +#define R8A77961_CLK_S2D4 20 +#define R8A77961_CLK_S3D1 21 +#define R8A77961_CLK_S3D2 22 +#define R8A77961_CLK_S3D4 23 +#define R8A77961_CLK_LB 24 +#define R8A77961_CLK_CL 25 +#define R8A77961_CLK_ZB3 26 +#define R8A77961_CLK_ZB3D2 27 +#define R8A77961_CLK_ZB3D4 28 +#define R8A77961_CLK_CR 29 +#define R8A77961_CLK_CRD2 30 +#define R8A77961_CLK_SD0H 31 +#define R8A77961_CLK_SD0 32 +#define R8A77961_CLK_SD1H 33 +#define R8A77961_CLK_SD1 34 +#define R8A77961_CLK_SD2H 35 +#define R8A77961_CLK_SD2 36 +#define R8A77961_CLK_SD3H 37 +#define R8A77961_CLK_SD3 38 +#define R8A77961_CLK_SSP2 39 +#define R8A77961_CLK_SSP1 40 +#define R8A77961_CLK_SSPRS 41 +#define R8A77961_CLK_RPC 42 +#define R8A77961_CLK_RPCD2 43 +#define R8A77961_CLK_MSO 44 +#define R8A77961_CLK_CANFD 45 +#define R8A77961_CLK_HDMI 46 +#define R8A77961_CLK_CSI0 47 +/* CLK_CSIREF was removed */ +#define R8A77961_CLK_CP 49 +#define R8A77961_CLK_CPEX 50 +#define R8A77961_CLK_R 51 +#define R8A77961_CLK_OSC 52 + +#endif /* __DT_BINDINGS_CLOCK_R8A77961_CPG_MSSR_H__ */ diff --git a/include/dt-bindings/clock/r8a77970-cpg-mssr.h b/include/dt-bindings/clock/r8a77970-cpg-mssr.h index 4146395595b..6145ebe6636 100644 --- a/include/dt-bindings/clock/r8a77970-cpg-mssr.h +++ b/include/dt-bindings/clock/r8a77970-cpg-mssr.h @@ -1,11 +1,7 @@ -/* +/* SPDX-License-Identifier: GPL-2.0+ + * * Copyright (C) 2016 Renesas Electronics Corp. * Copyright (C) 2017 Cogent Embedded, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. */ #ifndef __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ #define __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ diff --git a/include/dt-bindings/clk/versaclock.h b/include/dt-bindings/clock/versaclock.h index c6a6a094656..c6a6a094656 100644 --- a/include/dt-bindings/clk/versaclock.h +++ b/include/dt-bindings/clock/versaclock.h diff --git a/include/dt-bindings/pinctrl/pinctrl-snapdragon.h b/include/dt-bindings/pinctrl/pinctrl-snapdragon.h deleted file mode 100644 index 615affb6f26..00000000000 --- a/include/dt-bindings/pinctrl/pinctrl-snapdragon.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * This header provides constants for Qualcomm Snapdragon pinctrl bindings. - * - * (C) Copyright 2018 Ramon Fried <ramon.fried@gmail.com> - * - */ - -#ifndef _DT_BINDINGS_PINCTRL_SNAPDRAGON_H -#define _DT_BINDINGS_PINCTRL_SNAPDRAGON_H - -/* GPIO Drive Strength */ -#define DRIVE_STRENGTH_2MA 0 -#define DRIVE_STRENGTH_4MA 1 -#define DRIVE_STRENGTH_6MA 2 -#define DRIVE_STRENGTH_8MA 3 -#define DRIVE_STRENGTH_10MA 4 -#define DRIVE_STRENGTH_12MA 5 -#define DRIVE_STRENGTH_14MA 6 -#define DRIVE_STRENGTH_16MA 7 - -#endif diff --git a/include/dt-bindings/power/r8a774a1-sysc.h b/include/dt-bindings/power/r8a774a1-sysc.h index d35183557c4..580f431cd32 100644 --- a/include/dt-bindings/power/r8a774a1-sysc.h +++ b/include/dt-bindings/power/r8a774a1-sysc.h @@ -1,6 +1,6 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2019 Renesas Electronics Corp. +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2018 Renesas Electronics Corp. */ #ifndef __DT_BINDINGS_POWER_R8A774A1_SYSC_H__ #define __DT_BINDINGS_POWER_R8A774A1_SYSC_H__ diff --git a/include/dt-bindings/power/r8a774b1-sysc.h b/include/dt-bindings/power/r8a774b1-sysc.h index 96afda0446b..373736402f0 100644 --- a/include/dt-bindings/power/r8a774b1-sysc.h +++ b/include/dt-bindings/power/r8a774b1-sysc.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 * - * Copyright (C) 2020 Renesas Electronics Corp. + * Copyright (C) 2019 Renesas Electronics Corp. */ #ifndef __DT_BINDINGS_POWER_R8A774B1_SYSC_H__ #define __DT_BINDINGS_POWER_R8A774B1_SYSC_H__ diff --git a/include/dt-bindings/power/r8a774c0-sysc.h b/include/dt-bindings/power/r8a774c0-sysc.h index dd0cd656d90..9922d4c6f87 100644 --- a/include/dt-bindings/power/r8a774c0-sysc.h +++ b/include/dt-bindings/power/r8a774c0-sysc.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 * - * Copyright (C) 2020 Renesas Electronics Corp. + * Copyright (C) 2018 Renesas Electronics Corp. */ #ifndef __DT_BINDINGS_POWER_R8A774C0_SYSC_H__ #define __DT_BINDINGS_POWER_R8A774C0_SYSC_H__ diff --git a/include/dt-bindings/power/r8a7794-sysc.h b/include/dt-bindings/power/r8a7794-sysc.h index 862241c2d27..4d6c708e6f3 100644 --- a/include/dt-bindings/power/r8a7794-sysc.h +++ b/include/dt-bindings/power/r8a7794-sysc.h @@ -1,9 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) 2016 Glider bvba - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. */ #ifndef __DT_BINDINGS_POWER_R8A7794_SYSC_H__ #define __DT_BINDINGS_POWER_R8A7794_SYSC_H__ diff --git a/include/dt-bindings/power/r8a7795-sysc.h b/include/dt-bindings/power/r8a7795-sysc.h index ad679eeda13..eea6ad69f0b 100644 --- a/include/dt-bindings/power/r8a7795-sysc.h +++ b/include/dt-bindings/power/r8a7795-sysc.h @@ -1,9 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) 2016 Glider bvba - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. */ #ifndef __DT_BINDINGS_POWER_R8A7795_SYSC_H__ #define __DT_BINDINGS_POWER_R8A7795_SYSC_H__ diff --git a/include/dt-bindings/power/r8a7796-sysc.h b/include/dt-bindings/power/r8a7796-sysc.h index 5b4daab44da..7e6fc06ebff 100644 --- a/include/dt-bindings/power/r8a7796-sysc.h +++ b/include/dt-bindings/power/r8a7796-sysc.h @@ -1,9 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) 2016 Glider bvba - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. */ #ifndef __DT_BINDINGS_POWER_R8A7796_SYSC_H__ #define __DT_BINDINGS_POWER_R8A7796_SYSC_H__ diff --git a/include/dt-bindings/power/r8a77961-sysc.h b/include/dt-bindings/power/r8a77961-sysc.h new file mode 100644 index 00000000000..7a3800996f7 --- /dev/null +++ b/include/dt-bindings/power/r8a77961-sysc.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2019 Glider bvba + */ +#ifndef __DT_BINDINGS_POWER_R8A77961_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A77961_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + */ + +#define R8A77961_PD_CA57_CPU0 0 +#define R8A77961_PD_CA57_CPU1 1 +#define R8A77961_PD_CA53_CPU0 5 +#define R8A77961_PD_CA53_CPU1 6 +#define R8A77961_PD_CA53_CPU2 7 +#define R8A77961_PD_CA53_CPU3 8 +#define R8A77961_PD_CA57_SCU 12 +#define R8A77961_PD_CR7 13 +#define R8A77961_PD_A3VC 14 +#define R8A77961_PD_3DG_A 17 +#define R8A77961_PD_3DG_B 18 +#define R8A77961_PD_CA53_SCU 21 +#define R8A77961_PD_A3IR 24 +#define R8A77961_PD_A2VC1 26 + +/* Always-on power area */ +#define R8A77961_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A77961_SYSC_H__ */ diff --git a/include/dt-bindings/power/r8a77970-sysc.h b/include/dt-bindings/power/r8a77970-sysc.h index 85cc5f23cf9..9dcdbd5a930 100644 --- a/include/dt-bindings/power/r8a77970-sysc.h +++ b/include/dt-bindings/power/r8a77970-sysc.h @@ -1,9 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) 2017 Cogent Embedded Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #ifndef __DT_BINDINGS_POWER_R8A77970_SYSC_H__ #define __DT_BINDINGS_POWER_R8A77970_SYSC_H__ diff --git a/include/dt-bindings/power/r8a77995-sysc.h b/include/dt-bindings/power/r8a77995-sysc.h index 09d0ed575b7..f2b35502f2b 100644 --- a/include/dt-bindings/power/r8a77995-sysc.h +++ b/include/dt-bindings/power/r8a77995-sysc.h @@ -1,9 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) 2017 Glider bvba - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. */ #ifndef __DT_BINDINGS_POWER_R8A77995_SYSC_H__ #define __DT_BINDINGS_POWER_R8A77995_SYSC_H__ diff --git a/include/efi.h b/include/efi.h index 42f4e58a917..c3087d3da28 100644 --- a/include/efi.h +++ b/include/efi.h @@ -54,9 +54,18 @@ struct efi_device_path; +/* + * The EFI spec defines the EFI_GUID as + * "128-bit buffer containing a unique identifier value. Unless otherwise specified, + * aligned on a 64-bit boundary". + * Page 163 of the UEFI specification v2.10 and + * EDK2 reference implementation both define EFI_GUID as + * struct { u32 a; u16; b; u16 c; u8 d[8]; }; which is 4-byte + * aligned. + */ typedef struct { u8 b[16]; -} efi_guid_t __attribute__((aligned(8))); +} efi_guid_t __attribute__((aligned(4))); #define EFI_BITS_PER_LONG (sizeof(long) * 8) diff --git a/include/efi_api.h b/include/efi_api.h index 9bd70b0f18c..2d18d25a713 100644 --- a/include/efi_api.h +++ b/include/efi_api.h @@ -513,6 +513,16 @@ struct efi_system_table { struct efi_configuration_table *tables; }; +/** + * efi_main() - entry point of EFI applications + * + * @image_handle: handle with the Loaded Image Protocol + * @systab: pointer to the system table + * Return: status code + */ +efi_status_t EFIAPI efi_main(efi_handle_t image_handle, + struct efi_system_table *systab); + #define EFI_LOADED_IMAGE_PROTOCOL_GUID \ EFI_GUID(0x5b1b31a1, 0x9562, 0x11d2, \ 0x8e, 0x3f, 0x00, 0xa0, 0xc9, 0x69, 0x72, 0x3b) @@ -817,7 +827,7 @@ struct efi_simple_text_output_protocol { struct efi_input_key { u16 scan_code; - s16 unicode_char; + u16 unicode_char; }; #define EFI_SHIFT_STATE_INVALID 0x00000000 diff --git a/include/efi_config.h b/include/efi_config.h index e5edbb5e090..01ce9b2b06d 100644 --- a/include/efi_config.h +++ b/include/efi_config.h @@ -11,7 +11,7 @@ #include <efi_loader.h> #include <menu.h> -#define EFICONFIG_ENTRY_NUM_MAX INT_MAX +#define EFICONFIG_ENTRY_NUM_MAX (INT_MAX - 1) #define EFICONFIG_VOLUME_PATH_MAX 512 #define EFICONFIG_FILE_PATH_MAX 512 #define EFICONFIG_FILE_PATH_BUF_SIZE (EFICONFIG_FILE_PATH_MAX * sizeof(u16)) diff --git a/include/efi_loader.h b/include/efi_loader.h index 4560b0d04cb..c664d6cdf2c 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -1137,4 +1137,11 @@ efi_status_t efi_console_get_u16_string efi_status_t efi_disk_get_device_name(const efi_handle_t handle, char *buf, int size); +/** + * efi_add_known_memory() - add memory banks to EFI memory map + * + * This weak function may be overridden for specific architectures. + */ +void efi_add_known_memory(void); + #endif /* _EFI_LOADER_H */ diff --git a/include/elf.h b/include/elf.h index aeda159f0c0..a4ba74d8abe 100644 --- a/include/elf.h +++ b/include/elf.h @@ -360,6 +360,15 @@ typedef struct { Elf32_Half st_shndx; /* section header index */ } Elf32_Sym; +typedef struct { + Elf64_Word st_name; /* name - index into string table */ + unsigned char st_info; /* type and binding */ + unsigned char st_other; /* 0 - no defined meaning */ + Elf64_Half st_shndx; /* section header index */ + Elf64_Addr st_value; /* symbol value */ + Elf64_Xword st_size; /* symbol size */ +} Elf64_Sym; + /* Symbol table index */ #define STN_UNDEF 0 /* undefined */ diff --git a/include/env_flags.h b/include/env_flags.h index 6bd574c2bdb..7de58cc57c3 100644 --- a/include/env_flags.h +++ b/include/env_flags.h @@ -12,7 +12,7 @@ enum env_flags_vartype { env_flags_vartype_decimal, env_flags_vartype_hex, env_flags_vartype_bool, -#ifdef CONFIG_CMD_NET +#ifdef CONFIG_NET env_flags_vartype_ipaddr, env_flags_vartype_macaddr, #endif @@ -121,7 +121,7 @@ enum env_flags_varaccess env_flags_parse_varaccess(const char *flags); */ enum env_flags_varaccess env_flags_parse_varaccess_from_binflags(int binflags); -#ifdef CONFIG_CMD_NET +#ifdef CONFIG_NET /* * Check if a string has the format of an Ethernet MAC address */ diff --git a/include/env_internal.h b/include/env_internal.h index aee6b3e48fa..6a694946468 100644 --- a/include/env_internal.h +++ b/include/env_internal.h @@ -189,7 +189,7 @@ struct env_driver { #endif #define ENV_SAVE_PTR(x) (CONFIG_IS_ENABLED(SAVEENV) ? (x) : NULL) -#define ENV_ERASE_PTR(x) (CONFIG_IS_ENABLED(CMD_ERASEENV) ? (x) : NULL) +#define ENV_ERASE_PTR(x) (IS_ENABLED(CONFIG_CMD_ERASEENV) ? (x) : NULL) extern struct hsearch_data env_htab; diff --git a/include/environment/distro/sf.h b/include/environment/distro/sf.h index 62624d553c0..ee48a8a4e8f 100644 --- a/include/environment/distro/sf.h +++ b/include/environment/distro/sf.h @@ -8,7 +8,7 @@ #ifndef __DISTRO_SF_CONFIG_H #define __DISTRO_SF_CONFIG_H -#if CONFIG_IS_ENABLED(CMD_SF) +#if IS_ENABLED(CONFIG_CMD_SF) #define BOOTENV_SHARED_SF(devtypel) \ #devtypel "_boot=" \ "if " #devtypel " probe ${busnum}; then " \ diff --git a/include/environment/pg-wcom/powerpc.env b/include/environment/pg-wcom/powerpc.env index a57fd93092d..744c07388c9 100644 --- a/include/environment/pg-wcom/powerpc.env +++ b/include/environment/pg-wcom/powerpc.env @@ -1,3 +1,5 @@ +#define BOOTFLASH_START 0xF0000000 + arch=ppc_82xx bootm_mapsize=CONFIG_SYS_BOOTM_LEN checkfdt=true diff --git a/include/faraday/ftpmu010.h b/include/faraday/ftpmu010.h deleted file mode 100644 index ccb7805375e..00000000000 --- a/include/faraday/ftpmu010.h +++ /dev/null @@ -1,234 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2009 Faraday Technology - * Po-Yu Chuang <ratbert@faraday-tech.com> - */ - -/* - * Power Management Unit - */ -#ifndef __FTPMU010_H -#define __FTPMU010_H - -#ifndef __ASSEMBLY__ -struct ftpmu010 { - unsigned int IDNMBR0; /* 0x00 */ - unsigned int reserved0; /* 0x04 */ - unsigned int OSCC; /* 0x08 */ - unsigned int PMODE; /* 0x0C */ - unsigned int PMCR; /* 0x10 */ - unsigned int PED; /* 0x14 */ - unsigned int PEDSR; /* 0x18 */ - unsigned int reserved1; /* 0x1C */ - unsigned int PMSR; /* 0x20 */ - unsigned int PGSR; /* 0x24 */ - unsigned int MFPSR; /* 0x28 */ - unsigned int MISC; /* 0x2C */ - unsigned int PDLLCR0; /* 0x30 */ - unsigned int PDLLCR1; /* 0x34 */ - unsigned int AHBMCLKOFF; /* 0x38 */ - unsigned int APBMCLKOFF; /* 0x3C */ - unsigned int DCSRCR0; /* 0x40 */ - unsigned int DCSRCR1; /* 0x44 */ - unsigned int DCSRCR2; /* 0x48 */ - unsigned int SDRAMHTC; /* 0x4C */ - unsigned int PSPR0; /* 0x50 */ - unsigned int PSPR1; /* 0x54 */ - unsigned int PSPR2; /* 0x58 */ - unsigned int PSPR3; /* 0x5C */ - unsigned int PSPR4; /* 0x60 */ - unsigned int PSPR5; /* 0x64 */ - unsigned int PSPR6; /* 0x68 */ - unsigned int PSPR7; /* 0x6C */ - unsigned int PSPR8; /* 0x70 */ - unsigned int PSPR9; /* 0x74 */ - unsigned int PSPR10; /* 0x78 */ - unsigned int PSPR11; /* 0x7C */ - unsigned int PSPR12; /* 0x80 */ - unsigned int PSPR13; /* 0x84 */ - unsigned int PSPR14; /* 0x88 */ - unsigned int PSPR15; /* 0x8C */ - unsigned int AHBDMA_RACCS; /* 0x90 */ - unsigned int reserved2; /* 0x94 */ - unsigned int reserved3; /* 0x98 */ - unsigned int JSS; /* 0x9C */ - unsigned int CFC_RACC; /* 0xA0 */ - unsigned int SSP1_RACC; /* 0xA4 */ - unsigned int UART1TX_RACC; /* 0xA8 */ - unsigned int UART1RX_RACC; /* 0xAC */ - unsigned int UART2TX_RACC; /* 0xB0 */ - unsigned int UART2RX_RACC; /* 0xB4 */ - unsigned int SDC_RACC; /* 0xB8 */ - unsigned int I2SAC97_RACC; /* 0xBC */ - unsigned int IRDATX_RACC; /* 0xC0 */ - unsigned int reserved4; /* 0xC4 */ - unsigned int USBD_RACC; /* 0xC8 */ - unsigned int IRDARX_RACC; /* 0xCC */ - unsigned int IRDA_RACC; /* 0xD0 */ - unsigned int ED0_RACC; /* 0xD4 */ - unsigned int ED1_RACC; /* 0xD8 */ -}; -#endif /* __ASSEMBLY__ */ - -/* - * ID Number 0 Register - */ -#define FTPMU010_ID_A320A 0x03200000 -#define FTPMU010_ID_A320C 0x03200010 -#define FTPMU010_ID_A320D 0x03200030 - -/* - * OSC Control Register - */ -#define FTPMU010_OSCC_OSCH_TRI (1 << 11) -#define FTPMU010_OSCC_OSCH_STABLE (1 << 9) -#define FTPMU010_OSCC_OSCH_OFF (1 << 8) - -#define FTPMU010_OSCC_OSCL_TRI (1 << 3) -#define FTPMU010_OSCC_OSCL_RTCLSEL (1 << 2) -#define FTPMU010_OSCC_OSCL_STABLE (1 << 1) -#define FTPMU010_OSCC_OSCL_OFF (1 << 0) - -/* - * Power Mode Register - */ -#define FTPMU010_PMODE_DIVAHBCLK_MASK (0x7 << 4) -#define FTPMU010_PMODE_DIVAHBCLK_2 (0x0 << 4) -#define FTPMU010_PMODE_DIVAHBCLK_3 (0x1 << 4) -#define FTPMU010_PMODE_DIVAHBCLK_4 (0x2 << 4) -#define FTPMU010_PMODE_DIVAHBCLK_6 (0x3 << 4) -#define FTPMU010_PMODE_DIVAHBCLK_8 (0x4 << 4) -#define FTPMU010_PMODE_DIVAHBCLK(pmode) (((pmode) >> 4) & 0x7) -#define FTPMU010_PMODE_FCS (1 << 2) -#define FTPMU010_PMODE_TURBO (1 << 1) -#define FTPMU010_PMODE_SLEEP (1 << 0) - -/* - * Power Manager Status Register - */ -#define FTPMU010_PMSR_SMR (1 << 10) - -#define FTPMU010_PMSR_RDH (1 << 2) -#define FTPMU010_PMSR_PH (1 << 1) -#define FTPMU010_PMSR_CKEHLOW (1 << 0) - -/* - * Multi-Function Port Setting Register - */ -#define FTPMU010_MFPSR_DEBUGSEL (1 << 17) -#define FTPMU010_MFPSR_DMA0PINSEL (1 << 16) -#define FTPMU010_MFPSR_DMA1PINSEL (1 << 15) -#define FTPMU010_MFPSR_MODEMPINSEL (1 << 14) -#define FTPMU010_MFPSR_AC97CLKOUTSEL (1 << 13) -#define FTPMU010_MFPSR_PWM1PINSEL (1 << 11) -#define FTPMU010_MFPSR_PWM0PINSEL (1 << 10) -#define FTPMU010_MFPSR_IRDACLKSEL (1 << 9) -#define FTPMU010_MFPSR_UARTCLKSEL (1 << 8) -#define FTPMU010_MFPSR_SSPCLKSEL (1 << 6) -#define FTPMU010_MFPSR_I2SCLKSEL (1 << 5) -#define FTPMU010_MFPSR_AC97CLKSEL (1 << 4) -#define FTPMU010_MFPSR_AC97PINSEL (1 << 3) -#define FTPMU010_MFPSR_TRIAHBDIS (1 << 1) -#define FTPMU010_MFPSR_TRIAHBDBG (1 << 0) - -/* - * PLL/DLL Control Register 0 - * Note: - * 1. FTPMU010_PDLLCR0_HCLKOUTDIS: - * Datasheet indicated it starts at bit #21 which was wrong. - * 2. FTPMU010_PDLLCR0_DLLFRAG: - * Datasheet indicated it has 2 bit which was wrong. - */ -#define FTPMU010_PDLLCR0_HCLKOUTDIS(cr0) (((cr0) & 0xf) << 20) -#define FTPMU010_PDLLCR0_DLLFRAG(cr0) (1 << 19) -#define FTPMU010_PDLLCR0_DLLSTSEL (1 << 18) -#define FTPMU010_PDLLCR0_DLLSTABLE (1 << 17) -#define FTPMU010_PDLLCR0_DLLDIS (1 << 16) -#define FTPMU010_PDLLCR0_PLL1FRANG(cr0) (((cr0) & 0x3) << 12) -#define FTPMU010_PDLLCR0_PLL1NS(cr0) (((cr0) & 0x1ff) << 3) -#define FTPMU010_PDLLCR0_PLL1STSEL (1 << 2) -#define FTPMU010_PDLLCR0_PLL1STABLE (1 << 1) -#define FTPMU010_PDLLCR0_PLL1DIS (1 << 0) - -/* - * SDRAM Signal Hold Time Control Register - */ -#define FTPMU010_SDRAMHTC_RCLK_DLY(x) (((x) & 0xf) << 28) -#define FTPMU010_SDRAMHTC_CTL_WCLK_DLY(x) (((x) & 0xf) << 24) -#define FTPMU010_SDRAMHTC_DAT_WCLK_DLY(x) (((x) & 0xf) << 20) -#define FTPMU010_SDRAMHTC_EBICTRL_DCSR (1 << 18) -#define FTPMU010_SDRAMHTC_EBIDATA_DCSR (1 << 17) -#define FTPMU010_SDRAMHTC_SDRAMCS_DCSR (1 << 16) -#define FTPMU010_SDRAMHTC_SDRAMCTL_DCSR (1 << 15) -#define FTPMU010_SDRAMHTC_CKE_DCSR (1 << 14) -#define FTPMU010_SDRAMHTC_DQM_DCSR (1 << 13) -#define FTPMU010_SDRAMHTC_SDCLK_DCSR (1 << 12) - -#ifndef __ASSEMBLY__ -void ftpmu010_32768osc_enable(void); -void ftpmu010_dlldis_disable(void); -void ftpmu010_mfpsr_diselect_dev(unsigned int dev); -void ftpmu010_mfpsr_select_dev(unsigned int dev); -void ftpmu010_sdram_clk_disable(unsigned int cr0); -void ftpmu010_sdramhtc_set(unsigned int val); -#endif - -#ifdef __ASSEMBLY__ -#define FTPMU010_IDNMBR0 0x00 -#define FTPMU010_reserved0 0x04 -#define FTPMU010_OSCC 0x08 -#define FTPMU010_PMODE 0x0C -#define FTPMU010_PMCR 0x10 -#define FTPMU010_PED 0x14 -#define FTPMU010_PEDSR 0x18 -#define FTPMU010_reserved1 0x1C -#define FTPMU010_PMSR 0x20 -#define FTPMU010_PGSR 0x24 -#define FTPMU010_MFPSR 0x28 -#define FTPMU010_MISC 0x2C -#define FTPMU010_PDLLCR0 0x30 -#define FTPMU010_PDLLCR1 0x34 -#define FTPMU010_AHBMCLKOFF 0x38 -#define FTPMU010_APBMCLKOFF 0x3C -#define FTPMU010_DCSRCR0 0x40 -#define FTPMU010_DCSRCR1 0x44 -#define FTPMU010_DCSRCR2 0x48 -#define FTPMU010_SDRAMHTC 0x4C -#define FTPMU010_PSPR0 0x50 -#define FTPMU010_PSPR1 0x54 -#define FTPMU010_PSPR2 0x58 -#define FTPMU010_PSPR3 0x5C -#define FTPMU010_PSPR4 0x60 -#define FTPMU010_PSPR5 0x64 -#define FTPMU010_PSPR6 0x68 -#define FTPMU010_PSPR7 0x6C -#define FTPMU010_PSPR8 0x70 -#define FTPMU010_PSPR9 0x74 -#define FTPMU010_PSPR10 0x78 -#define FTPMU010_PSPR11 0x7C -#define FTPMU010_PSPR12 0x80 -#define FTPMU010_PSPR13 0x84 -#define FTPMU010_PSPR14 0x88 -#define FTPMU010_PSPR15 0x8C -#define FTPMU010_AHBDMA_RACCS 0x90 -#define FTPMU010_reserved2 0x94 -#define FTPMU010_reserved3 0x98 -#define FTPMU010_JSS 0x9C -#define FTPMU010_CFC_RACC 0xA0 -#define FTPMU010_SSP1_RACC 0xA4 -#define FTPMU010_UART1TX_RACC 0xA8 -#define FTPMU010_UART1RX_RACC 0xAC -#define FTPMU010_UART2TX_RACC 0xB0 -#define FTPMU010_UART2RX_RACC 0xB4 -#define FTPMU010_SDC_RACC 0xB8 -#define FTPMU010_I2SAC97_RACC 0xBC -#define FTPMU010_IRDATX_RACC 0xC0 -#define FTPMU010_reserved4 0xC4 -#define FTPMU010_USBD_RACC 0xC8 -#define FTPMU010_IRDARX_RACC 0xCC -#define FTPMU010_IRDA_RACC 0xD0 -#define FTPMU010_ED0_RACC 0xD4 -#define FTPMU010_ED1_RACC 0xD8 -#endif /* __ASSEMBLY__ */ - -#endif /* __FTPMU010_H */ diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 2d04882d053..b8acacd49ee 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -65,7 +65,7 @@ struct clk_mux { */ const char * const *parent_names; u8 num_parents; -#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF) +#if IS_ENABLED(CONFIG_SANDBOX_CLK_CCF) u32 io_mux_val; #endif @@ -93,7 +93,7 @@ struct clk_gate { void __iomem *reg; u8 bit_idx; u8 flags; -#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF) +#if IS_ENABLED(CONFIG_SANDBOX_CLK_CCF) u32 io_gate_val; #endif }; @@ -121,7 +121,7 @@ struct clk_divider { u8 width; u8 flags; const struct clk_div_table *table; -#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF) +#if IS_ENABLED(CONFIG_SANDBOX_CLK_CCF) u32 io_divider_val; #endif }; diff --git a/include/linux/mtd/fsl_upm.h b/include/linux/mtd/fsl_upm.h deleted file mode 100644 index 9999993543b..00000000000 --- a/include/linux/mtd/fsl_upm.h +++ /dev/null @@ -1,44 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * FSL UPM NAND driver - * - * Copyright (C) 2007 MontaVista Software, Inc. - * Anton Vorontsov <avorontsov@ru.mvista.com> - */ - -#ifndef __LINUX_MTD_NAND_FSL_UPM -#define __LINUX_MTD_NAND_FSL_UPM - -#include <linux/mtd/rawnand.h> - -#define FSL_UPM_WAIT_RUN_PATTERN 0x1 -#define FSL_UPM_WAIT_WRITE_BYTE 0x2 -#define FSL_UPM_WAIT_WRITE_BUFFER 0x4 - -struct fsl_upm { - void __iomem *mdr; - void __iomem *mxmr; - void __iomem *mar; - void __iomem *io_addr; -}; - -struct fsl_upm_nand { - struct fsl_upm upm; - - int width; - int upm_cmd_offset; - int upm_addr_offset; - int upm_mar_chip_offset; - int wait_flags; - int (*dev_ready)(int chip_nr); - int chip_delay; - int chip_offset; - int chip_nr; - - /* no need to fill */ - int last_ctrl; -}; - -extern int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun); - -#endif diff --git a/include/linux/mtd/fsmc_nand.h b/include/linux/mtd/fsmc_nand.h deleted file mode 100644 index 1d8a067f17e..00000000000 --- a/include/linux/mtd/fsmc_nand.h +++ /dev/null @@ -1,84 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010 - * Vipin Kumar, STMicroelectronics, vipin.kumar@st.com. - */ - -#ifndef __FSMC_NAND_H__ -#define __FSMC_NAND_H__ - -#include <linux/mtd/rawnand.h> - -struct fsmc_regs { - u32 ctrl; /* 0x00 */ - u8 reserved_1[0x40 - 0x04]; - u32 pc; /* 0x40 */ - u32 sts; /* 0x44 */ - u32 comm; /* 0x48 */ - u32 attrib; /* 0x4c */ - u32 ioata; /* 0x50 */ - u32 ecc1; /* 0x54 */ - u32 ecc2; /* 0x58 */ - u32 ecc3; /* 0x5c */ - u8 reserved_2[0xfe0 - 0x60]; - u32 peripid0; /* 0xfe0 */ - u32 peripid1; /* 0xfe4 */ - u32 peripid2; /* 0xfe8 */ - u32 peripid3; /* 0xfec */ - u32 pcellid0; /* 0xff0 */ - u32 pcellid1; /* 0xff4 */ - u32 pcellid2; /* 0xff8 */ - u32 pcellid3; /* 0xffc */ -}; - -/* ctrl register definitions */ -#define FSMC_WP (1 << 7) - -/* pc register definitions */ -#define FSMC_RESET (1 << 0) -#define FSMC_WAITON (1 << 1) -#define FSMC_ENABLE (1 << 2) -#define FSMC_DEVTYPE_NAND (1 << 3) -#define FSMC_DEVWID_8 (0 << 4) -#define FSMC_DEVWID_16 (1 << 4) -#define FSMC_ECCEN (1 << 6) -#define FSMC_ECCPLEN_512 (0 << 7) -#define FSMC_ECCPLEN_256 (1 << 7) -#define FSMC_TCLR_1 (1 << 9) -#define FSMC_TAR_1 (1 << 13) - -/* sts register definitions */ -#define FSMC_CODE_RDY (1 << 15) - -/* comm register definitions */ -#define FSMC_TSET_0 (0 << 0) -#define FSMC_TWAIT_6 (6 << 8) -#define FSMC_THOLD_4 (4 << 16) -#define FSMC_THIZ_1 (1 << 24) - -/* peripid2 register definitions */ -#define FSMC_REVISION_MSK (0xf) -#define FSMC_REVISION_SHFT (0x4) - -#define FSMC_VER8 0x8 - -/* - * There are 13 bytes of ecc for every 512 byte block and it has to be read - * consecutively and immediately after the 512 byte data block for hardware to - * generate the error bit offsets - * Managing the ecc bytes in the following way is easier. This way is similar to - * oobfree structure maintained already in u-boot nand driver - */ -#define FSMC_MAX_ECCPLACE_ENTRIES 32 - -struct fsmc_nand_eccplace { - u32 offset; - u32 length; -}; - -struct fsmc_eccplace { - struct fsmc_nand_eccplace eccplace[FSMC_MAX_ECCPLACE_ENTRIES]; -}; - -extern int fsmc_nand_init(struct nand_chip *nand); -#endif diff --git a/include/log.h b/include/log.h index 8a7b961bbfb..3bab40b6171 100644 --- a/include/log.h +++ b/include/log.h @@ -100,6 +100,8 @@ enum log_category_t { LOGC_BOOT, /** @LOGC_EVENT: Related to event and event handling */ LOGC_EVENT, + /** @LOGC_FS: Related to filesystems */ + LOGC_FS, /** @LOGC_COUNT: Number of log categories */ LOGC_COUNT, /** @LOGC_END: Sentinel value for lists of log categories */ diff --git a/include/menu.h b/include/menu.h index 1e88141d6bf..64ce89b7d26 100644 --- a/include/menu.h +++ b/include/menu.h @@ -53,6 +53,7 @@ enum bootmenu_key { BKEY_PLUS, BKEY_MINUS, BKEY_SPACE, + BKEY_SAVE, BKEY_COUNT, }; diff --git a/include/mmc.h b/include/mmc.h index 571fa625d02..36dd841d5d1 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -892,9 +892,17 @@ int mmc_rpmb_write(struct mmc *mmc, void *addr, unsigned short blk, int mmc_rpmb_route_frames(struct mmc *mmc, void *req, unsigned long reqlen, void *rsp, unsigned long rsplen); -#ifdef CONFIG_CMD_BKOPS_ENABLE -int mmc_set_bkops_enable(struct mmc *mmc); -#endif +/** + * mmc_set_bkops_enable() - enable background operations + * @param mmc Pointer to a MMC device struct + * @param autobkops Enable automatic bkops, not manual bkops + * @param enable Enable bkops, not disable + * + * Enable or disable automatic or manual background operation of the eMMC. + * + * Return: 0 on success, <0 on error. + */ +int mmc_set_bkops_enable(struct mmc *mmc, bool autobkops, bool enable); /** * Start device initialization and return immediately; it does not block on diff --git a/include/net6.h b/include/net6.h index 9b3de028e6d..2d7c5a09604 100644 --- a/include/net6.h +++ b/include/net6.h @@ -24,7 +24,7 @@ struct in6_addr { #define s6_addr in6_u.u6_addr8 #define s6_addr16 in6_u.u6_addr16 #define s6_addr32 in6_u.u6_addr32 -}; +} __packed; #define IN6ADDRSZ sizeof(struct in6_addr) #define INETHADDRSZ sizeof(net_ethaddr) @@ -62,7 +62,7 @@ struct ip6_hdr { u8 hop_limit; struct in6_addr saddr; struct in6_addr daddr; -}; +} __packed; #define IP6_HDR_SIZE (sizeof(struct ip6_hdr)) /* struct udp_hdr - User Datagram Protocol header */ @@ -164,7 +164,7 @@ struct icmp6hdr { #define icmp6_addrconf_managed icmp6_dataun.u_nd_ra.managed #define icmp6_addrconf_other icmp6_dataun.u_nd_ra.other #define icmp6_rt_lifetime icmp6_dataun.u_nd_ra.rt_lifetime -}; +} __packed; extern struct in6_addr const net_null_addr_ip6; /* NULL IPv6 address */ extern struct in6_addr net_gateway6; /* Our gateways IPv6 address */ diff --git a/include/netdev.h b/include/netdev.h index 2b4e474ed08..2a7f40e5040 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -71,7 +71,6 @@ int skge_initialize(struct bd_info *bis); int smc91111_initialize(u8 dev_num, phys_addr_t base_addr); int smc911x_initialize(u8 dev_num, phys_addr_t base_addr); int uli526x_initialize(struct bd_info *bis); -int armada100_fec_register(unsigned long base_addr); /* Boards with PCI network controllers can call this from their board_eth_init() * function to initialize whatever's on board. diff --git a/include/pca9698.h b/include/pca9698.h deleted file mode 100644 index 48a5f756e28..00000000000 --- a/include/pca9698.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 - * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc - */ - -#ifndef __PCA9698_H_ -#define __PCA9698_H_ - -int pca9698_request(unsigned gpio, const char *label); -void pca9698_free(unsigned gpio); -int pca9698_direction_input(u8 addr, unsigned gpio); -int pca9698_direction_output(u8 addr, unsigned gpio, int value); -int pca9698_get_value(u8 addr, unsigned gpio); -int pca9698_set_value(u8 addr, unsigned gpio, int value); - -#endif /* __PCA9698_H_ */ diff --git a/include/power/act8846_pmic.h b/include/power/act8846_pmic.h index acd0fd671e7..84845c70f91 100644 --- a/include/power/act8846_pmic.h +++ b/include/power/act8846_pmic.h @@ -9,7 +9,7 @@ #include <asm/gpio.h> -#define ACT8846_NUM_OF_REGS 12 +#define ACT8846_NUM_OF_REGS 0xf6 #define BUCK_VOL_MASK 0x3f #define LDO_VOL_MASK 0x3f diff --git a/include/power/fg_battery_cell_params.h b/include/power/fg_battery_cell_params.h deleted file mode 100644 index 500c8ea7174..00000000000 --- a/include/power/fg_battery_cell_params.h +++ /dev/null @@ -1,73 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2012 Samsung Electronics - * Lukasz Majewski <l.majewski@samsung.com> - */ - -#ifndef __FG_BATTERY_CELL_PARAMS_H_ -#define __FG_BATTERY_CELL_PARAMS_H_ - -#if defined(CONFIG_POWER_FG_MAX17042) && defined(CONFIG_TARGET_TRATS) - -/* Cell characteristics - Exynos4 TRATS development board */ -/* Shall be written to addr 0x80h */ -u16 cell_character0[16] = { - 0xA2A0, - 0xB6E0, - 0xB850, - 0xBAD0, - 0xBB20, - 0xBB70, - 0xBBC0, - 0xBC20, - 0xBC80, - 0xBCE0, - 0xBD80, - 0xBE20, - 0xC090, - 0xC420, - 0xC910, - 0xD070 -}; - -/* Shall be written to addr 0x90h */ -u16 cell_character1[16] = { - 0x0090, - 0x1A50, - 0x02F0, - 0x2060, - 0x2060, - 0x2E60, - 0x26A0, - 0x2DB0, - 0x2DB0, - 0x1870, - 0x2A20, - 0x16F0, - 0x08F0, - 0x0D40, - 0x08C0, - 0x08C0 -}; - -/* Shall be written to addr 0xA0h */ -u16 cell_character2[16] = { - 0x0100, - 0x0100, - 0x0100, - 0x0100, - 0x0100, - 0x0100, - 0x0100, - 0x0100, - 0x0100, - 0x0100, - 0x0100, - 0x0100, - 0x0100, - 0x0100, - 0x0100, - 0x0100 -}; -#endif -#endif /* __FG_BATTERY_CELL_PARAMS_H_ */ diff --git a/include/power/pca9450.h b/include/power/pca9450.h index fa0405fcb87..6efecee96c8 100644 --- a/include/power/pca9450.h +++ b/include/power/pca9450.h @@ -67,4 +67,8 @@ enum { #define PCA9450_LDO34_MASK 0x1f #define PCA9450_LDO5_MASK 0x0f +#define PCA9450_PMIC_RESET_WDOG_B_CFG_MASK 0xc0 +#define PCA9450_PMIC_RESET_WDOG_B_CFG_WARM 0x40 +#define PCA9450_PMIC_RESET_WDOG_B_CFG_COLD_LDO12 0x80 + #endif diff --git a/include/qfw.h b/include/qfw.h index 7ca132e66a2..42798fea7db 100644 --- a/include/qfw.h +++ b/include/qfw.h @@ -316,4 +316,17 @@ bool qfw_file_iter_end(struct fw_cfg_file_iter *iter); */ int qemu_cpu_fixup(void); +/* + * qemu_fwcfg_setup_kernel() - Prepare the kernel for zboot + * + * Loads kernel data to 'load_addr', initrd to 'initrd_addr' and kernel command + * line using qemu fw_cfg interface + * + * @load_addr: Load address for kernel + * @initrd_addr: Load address for ramdisk + * @return 0 if OK, -ENOENT if no kernel + */ +int qemu_fwcfg_setup_kernel(struct udevice *qfw_dev, ulong load_addr, + ulong initrd_addr); + #endif diff --git a/include/scf0403_lcd.h b/include/scf0403_lcd.h deleted file mode 100644 index 07f8c643ba5..00000000000 --- a/include/scf0403_lcd.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2013, Compulab Inc. - */ -#ifndef SCF0403_LCD_H_ -#define SCF0403_LCD_H_ - -int scf0403_init(int reset_gpio); - -#endif diff --git a/include/sdhci.h b/include/sdhci.h index 24b4599b857..70fefca2a97 100644 --- a/include/sdhci.h +++ b/include/sdhci.h @@ -189,6 +189,7 @@ #define SDHCI_SUPPORT_SDR50 0x00000001 #define SDHCI_SUPPORT_SDR104 0x00000002 #define SDHCI_SUPPORT_DDR50 0x00000004 +#define SDHCI_SUPPORT_HS400 BIT(31) #define SDHCI_USE_SDR50_TUNING 0x00002000 #define SDHCI_CLOCK_MUL_MASK 0x00FF0000 @@ -248,6 +249,8 @@ #define SDHCI_QUIRK_USE_WIDE8 (1 << 8) #define SDHCI_QUIRK_NO_1_8_V (1 << 9) #define SDHCI_QUIRK_SUPPORT_SINGLE (1 << 10) +/* Capability register bit-63 indicates HS400 support */ +#define SDHCI_QUIRK_CAPS_BIT63_FOR_HS400 BIT(11) /* to make gcc happy */ struct sdhci_host; @@ -272,6 +275,8 @@ struct sdhci_ops { void (*set_clock)(struct sdhci_host *host, u32 div); int (*platform_execute_tuning)(struct mmc *host, u8 opcode); int (*set_delay)(struct sdhci_host *host); + /* Callback function to set DLL clock configuration */ + int (*config_dll)(struct sdhci_host *host, u32 clock, bool enable); int (*deferred_probe)(struct sdhci_host *host); /** diff --git a/include/tee.h b/include/tee.h index 13f6096b9a6..ab0c5832613 100644 --- a/include/tee.h +++ b/include/tee.h @@ -328,7 +328,7 @@ bool tee_shm_is_registered(struct tee_shm *shm, struct udevice *dev); * Returns a probed TEE device of the first TEE device matched by the * match() callback or NULL. */ -#if CONFIG_IS_ENABLED(TEE) +#if IS_ENABLED(CONFIG_TEE) struct udevice *tee_find_device(struct udevice *start, int (*match)(struct tee_version_data *vers, const void *data), diff --git a/include/test/suites.h b/include/test/suites.h index 9ce49cbb031..7c4960c004d 100644 --- a/include/test/suites.h +++ b/include/test/suites.h @@ -49,6 +49,7 @@ int do_ut_optee(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); int do_ut_overlay(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); int do_ut_print(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); +int do_ut_seama(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); int do_ut_setexpr(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); int do_ut_str(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); diff --git a/include/timer.h b/include/timer.h index d33a26e28fe..311ce6b2c3a 100644 --- a/include/timer.h +++ b/include/timer.h @@ -9,11 +9,16 @@ #define timer_get_ops(dev) ((struct timer_ops *)(dev)->driver->ops) /** - * dm_timer_init() - initialize a timer for time keeping. On success - * initializes gd->timer so that lib/timer can use it for future - * referrence. + * dm_timer_init() - set up a timer for time keeping * - * Return: 0 on success or error number + * Sets up gd->timer if the device is not already bound, making sure it is + * probed and ready for use + * + * On success, inits gd->timer so that lib/timer can use it for future reference + * + * Returns: 0 on success, -EAGAIN if driver model is not ready yet, -ENODEV if + * no timer could be found, other error if the timer could not be bound or + * probed */ int dm_timer_init(void); diff --git a/include/trace.h b/include/trace.h index e7aee024f03..763d6d1255a 100644 --- a/include/trace.h +++ b/include/trace.h @@ -6,6 +6,8 @@ #ifndef __TRACE_H #define __TRACE_H +/* this file is included from a tool so uses uint32_t instead of u32, etc. */ + enum { /* * This affects the granularity of our trace. We can bin function @@ -15,14 +17,18 @@ enum { * * The value here assumes a minimum instruction size of 4 bytes, * or that instructions are 2 bytes but there are at least 2 of - * them in every function. + * them in every function. Given that each function needs a call to + * __cyg_profile_func_enter() and __cyg_profile_func_exit() as well, + * we cannot have functions smaller that 16 bytes. * * Increasing this value reduces the number of functions we can * resolve, but reduces the size of the uintptr_t array used for * our function list, which is the length of the code divided by * this value. */ - FUNC_SITE_SIZE = 4, /* distance between function sites */ + FUNC_SITE_SIZE = 16, /* distance between function sites */ + + TRACE_VERSION = 1, }; enum trace_chunk_type { @@ -39,7 +45,11 @@ struct trace_output_func { /* A header at the start of the trace output buffer */ struct trace_output_hdr { enum trace_chunk_type type; /* Record type */ - size_t rec_count; /* Number of records */ + uint32_t version; /* Version (TRACE_VERSION) */ + uint32_t rec_count; /* Number of records */ + uint32_t spare; /* 0 */ + uint64_t text_base; /* Value of CONFIG_TEXT_BASE */ + uint64_t spare2; /* 0 */ }; /* Print statistics about traced function calls */ @@ -63,7 +73,7 @@ int trace_list_functions(void *buff, size_t buff_size, size_t *needed); enum ftrace_flags { FUNCF_EXIT = 0UL << 30, FUNCF_ENTRY = 1UL << 30, - FUNCF_TEXTBASE = 2UL << 30, + /* two more values are available */ FUNCF_TIMESTAMP_MASK = 0x3fffffff, }; diff --git a/include/usb/fotg210.h b/include/usb/fotg210.h deleted file mode 100644 index 292ce54e0c4..00000000000 --- a/include/usb/fotg210.h +++ /dev/null @@ -1,362 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Faraday USB 2.0 OTG Controller - * - * (C) Copyright 2010 Faraday Technology - * Dante Su <dantesu@faraday-tech.com> - */ - -#ifndef _FOTG210_H -#define _FOTG210_H - -struct fotg210_regs { - /* USB Host Controller */ - struct { - uint32_t data[4]; - } hccr; /* 0x00 - 0x0f: hccr */ - struct { - uint32_t data[9]; - } hcor; /* 0x10 - 0x33: hcor */ - uint32_t rsvd1[3]; - uint32_t miscr; /* 0x40: Miscellaneous Register */ - uint32_t rsvd2[15]; - /* USB OTG Controller */ - uint32_t otgcsr;/* 0x80: OTG Control Status Register */ - uint32_t otgisr;/* 0x84: OTG Interrupt Status Register */ - uint32_t otgier;/* 0x88: OTG Interrupt Enable Register */ - uint32_t rsvd3[13]; - uint32_t isr; /* 0xC0: Global Interrupt Status Register */ - uint32_t imr; /* 0xC4: Global Interrupt Mask Register */ - uint32_t rsvd4[14]; - /* USB Device Controller */ - uint32_t dev_ctrl;/* 0x100: Device Control Register */ - uint32_t dev_addr;/* 0x104: Device Address Register */ - uint32_t dev_test;/* 0x108: Device Test Register */ - uint32_t sof_fnr; /* 0x10c: SOF Frame Number Register */ - uint32_t sof_mtr; /* 0x110: SOF Mask Timer Register */ - uint32_t phy_tmsr;/* 0x114: PHY Test Mode Selector Register */ - uint32_t rsvd5[2]; - uint32_t cxfifo;/* 0x120: CX FIFO Register */ - uint32_t idle; /* 0x124: IDLE Counter Register */ - uint32_t rsvd6[2]; - uint32_t gimr; /* 0x130: Group Interrupt Mask Register */ - uint32_t gimr0; /* 0x134: Group Interrupt Mask Register 0 */ - uint32_t gimr1; /* 0x138: Group Interrupt Mask Register 1 */ - uint32_t gimr2; /* 0x13c: Group Interrupt Mask Register 2 */ - uint32_t gisr; /* 0x140: Group Interrupt Status Register */ - uint32_t gisr0; /* 0x144: Group Interrupt Status Register 0 */ - uint32_t gisr1; /* 0x148: Group Interrupt Status Register 1 */ - uint32_t gisr2; /* 0x14c: Group Interrupt Status Register 2 */ - uint32_t rxzlp; /* 0x150: Receive Zero-Length-Packet Register */ - uint32_t txzlp; /* 0x154: Transfer Zero-Length-Packet Register */ - uint32_t isoeasr;/* 0x158: ISOC Error/Abort Status Register */ - uint32_t rsvd7[1]; - uint32_t iep[8]; /* 0x160 - 0x17f: IN Endpoint Register */ - uint32_t oep[8]; /* 0x180 - 0x19f: OUT Endpoint Register */ - uint32_t epmap14;/* 0x1a0: Endpoint Map Register (EP1 ~ 4) */ - uint32_t epmap58;/* 0x1a4: Endpoint Map Register (EP5 ~ 8) */ - uint32_t fifomap;/* 0x1a8: FIFO Map Register */ - uint32_t fifocfg; /* 0x1ac: FIFO Configuration Register */ - uint32_t fifocsr[4];/* 0x1b0 - 0x1bf: FIFO Control Status Register */ - uint32_t dma_fifo; /* 0x1c0: DMA Target FIFO Register */ - uint32_t rsvd8[1]; - uint32_t dma_ctrl; /* 0x1c8: DMA Control Register */ - uint32_t dma_addr; /* 0x1cc: DMA Address Register */ - uint32_t ep0_data; /* 0x1d0: EP0 Setup Packet PIO Register */ -}; - -/* Miscellaneous Register */ -#define MISCR_SUSPEND (1 << 6) /* Put transceiver in suspend mode */ -#define MISCR_EOF2(x) (((x) & 0x3) << 4) /* EOF 2 Timing */ -#define MISCR_EOF1(x) (((x) & 0x3) << 2) /* EOF 1 Timing */ -#define MISCR_ASST(x) (((x) & 0x3) << 0) /* Async. Sched. Sleep Timer */ - -/* OTG Control Status Register */ -#define OTGCSR_SPD_HIGH (2 << 22) /* Speed of the attached device (host) */ -#define OTGCSR_SPD_LOW (1 << 22) -#define OTGCSR_SPD_FULL (0 << 22) -#define OTGCSR_SPD_MASK (3 << 22) -#define OTGCSR_SPD_SHIFT 22 -#define OTGCSR_SPD(x) (((x) >> 22) & 0x03) -#define OTGCSR_DEV_A (0 << 21) /* Acts as A-device */ -#define OTGCSR_DEV_B (1 << 21) /* Acts as B-device */ -#define OTGCSR_ROLE_H (0 << 20) /* Acts as Host */ -#define OTGCSR_ROLE_D (1 << 20) /* Acts as Device */ -#define OTGCSR_A_VBUS_VLD (1 << 19) /* A-device VBUS Valid */ -#define OTGCSR_A_SESS_VLD (1 << 18) /* A-device Session Valid */ -#define OTGCSR_B_SESS_VLD (1 << 17) /* B-device Session Valid */ -#define OTGCSR_B_SESS_END (1 << 16) /* B-device Session End */ -#define OTGCSR_HFT_LONG (1 << 11) /* HDISCON noise filter = 270 us*/ -#define OTGCSR_HFT (0 << 11) /* HDISCON noise filter = 135 us*/ -#define OTGCSR_VFT_LONG (1 << 10) /* VBUS noise filter = 472 us*/ -#define OTGCSR_VFT (0 << 10) /* VBUS noise filter = 135 us*/ -#define OTGCSR_IDFT_LONG (1 << 9) /* ID noise filter = 4 ms*/ -#define OTGCSR_IDFT (0 << 9) /* ID noise filter = 3 ms*/ -#define OTGCSR_A_SRPR_VBUS (0 << 8) /* A-device: SRP responds to VBUS */ -#define OTGCSR_A_SRPR_DATA (1 << 8) /* A-device: SRP responds to DATA-LINE */ -#define OTGCSR_A_SRP_EN (1 << 7) /* A-device SRP detection enabled */ -#define OTGCSR_A_HNP (1 << 6) /* Set role=A-device with HNP enabled */ -#define OTGCSR_A_BUSDROP (1 << 5) /* A-device drop bus (power-down) */ -#define OTGCSR_A_BUSREQ (1 << 4) /* A-device request bus */ -#define OTGCSR_B_VBUS_DISC (1 << 2) /* B-device discharges VBUS */ -#define OTGCSR_B_HNP (1 << 1) /* B-device enable HNP */ -#define OTGCSR_B_BUSREQ (1 << 0) /* B-device request bus */ - -/* OTG Interrupt Status Register */ -#define OTGISR_APRM (1 << 12) /* Mini-A plug removed */ -#define OTGISR_BPRM (1 << 11) /* Mini-B plug removed */ -#define OTGISR_OVD (1 << 10) /* over-current detected */ -#define OTGISR_IDCHG (1 << 9) /* ID(A/B) changed */ -#define OTGISR_RLCHG (1 << 8) /* Role(Host/Device) changed */ -#define OTGISR_BSESSEND (1 << 6) /* B-device Session End */ -#define OTGISR_AVBUSERR (1 << 5) /* A-device VBUS Error */ -#define OTGISR_ASRP (1 << 4) /* A-device SRP detected */ -#define OTGISR_BSRP (1 << 0) /* B-device SRP complete */ - -/* OTG Interrupt Enable Register */ -#define OTGIER_APRM (1 << 12) /* Mini-A plug removed */ -#define OTGIER_BPRM (1 << 11) /* Mini-B plug removed */ -#define OTGIER_OVD (1 << 10) /* over-current detected */ -#define OTGIER_IDCHG (1 << 9) /* ID(A/B) changed */ -#define OTGIER_RLCHG (1 << 8) /* Role(Host/Device) changed */ -#define OTGIER_BSESSEND (1 << 6) /* B-device Session End */ -#define OTGIER_AVBUSERR (1 << 5) /* A-device VBUS Error */ -#define OTGIER_ASRP (1 << 4) /* A-device SRP detected */ -#define OTGIER_BSRP (1 << 0) /* B-device SRP complete */ - -/* Global Interrupt Status Register (W1C) */ -#define ISR_HOST (1 << 2) /* USB Host interrupt */ -#define ISR_OTG (1 << 1) /* USB OTG interrupt */ -#define ISR_DEV (1 << 0) /* USB Device interrupt */ -#define ISR_MASK 0x07 - -/* Global Interrupt Mask Register */ -#define IMR_IRQLH (1 << 3) /* Interrupt triggered at level-high */ -#define IMR_IRQLL (0 << 3) /* Interrupt triggered at level-low */ -#define IMR_HOST (1 << 2) /* USB Host interrupt */ -#define IMR_OTG (1 << 1) /* USB OTG interrupt */ -#define IMR_DEV (1 << 0) /* USB Device interrupt */ -#define IMR_MASK 0x0f - -/* Device Control Register */ -#define DEVCTRL_FS_FORCED (1 << 9) /* Forced to be Full-Speed Mode */ -#define DEVCTRL_HS (1 << 6) /* High Speed Mode */ -#define DEVCTRL_FS (0 << 6) /* Full Speed Mode */ -#define DEVCTRL_EN (1 << 5) /* Chip Enable */ -#define DEVCTRL_RESET (1 << 4) /* Chip Software Reset */ -#define DEVCTRL_SUSPEND (1 << 3) /* Enter Suspend Mode */ -#define DEVCTRL_GIRQ_EN (1 << 2) /* Global Interrupt Enabled */ -#define DEVCTRL_HALFSPD (1 << 1) /* Half speed mode for FPGA test */ -#define DEVCTRL_RWAKEUP (1 << 0) /* Enable remote wake-up */ - -/* Device Address Register */ -#define DEVADDR_CONF (1 << 7) /* SET_CONFIGURATION has been executed */ -#define DEVADDR_ADDR(x) ((x) & 0x7f) -#define DEVADDR_ADDR_MASK 0x7f - -/* Device Test Register */ -#define DEVTEST_NOSOF (1 << 6) /* Do not generate SOF */ -#define DEVTEST_TST_MODE (1 << 5) /* Enter Test Mode */ -#define DEVTEST_TST_NOTS (1 << 4) /* Do not toggle sequence */ -#define DEVTEST_TST_NOCRC (1 << 3) /* Do not append CRC */ -#define DEVTEST_TST_CLREA (1 << 2) /* Clear External Side Address */ -#define DEVTEST_TST_CXLP (1 << 1) /* EP0 loopback test */ -#define DEVTEST_TST_CLRFF (1 << 0) /* Clear FIFO */ - -/* SOF Frame Number Register */ -#define SOFFNR_UFN(x) (((x) >> 11) & 0x7) /* SOF Micro-Frame Number */ -#define SOFFNR_FNR(x) ((x) & 0x7ff) /* SOF Frame Number */ - -/* SOF Mask Timer Register */ -#define SOFMTR_TMR(x) ((x) & 0xffff) - -/* PHY Test Mode Selector Register */ -#define PHYTMSR_TST_PKT (1 << 4) /* Packet send test */ -#define PHYTMSR_TST_SE0NAK (1 << 3) /* High-Speed quiescent state */ -#define PHYTMSR_TST_KSTA (1 << 2) /* High-Speed K state */ -#define PHYTMSR_TST_JSTA (1 << 1) /* High-Speed J state */ -#define PHYTMSR_UNPLUG (1 << 0) /* Enable soft-detachment */ - -/* CX FIFO Register */ -#define CXFIFO_BYTES(x) (((x) >> 24) & 0x7f) /* CX/EP0 FIFO byte count */ -#define CXFIFO_FIFOE(x) (1 << (((x) & 0x03) + 8)) /* EPx FIFO empty */ -#define CXFIFO_FIFOE_FIFO0 (1 << 8) -#define CXFIFO_FIFOE_FIFO1 (1 << 9) -#define CXFIFO_FIFOE_FIFO2 (1 << 10) -#define CXFIFO_FIFOE_FIFO3 (1 << 11) -#define CXFIFO_FIFOE_MASK (0x0f << 8) -#define CXFIFO_CXFIFOE (1 << 5) /* CX FIFO empty */ -#define CXFIFO_CXFIFOF (1 << 4) /* CX FIFO full */ -#define CXFIFO_CXFIFOCLR (1 << 3) /* CX FIFO clear */ -#define CXFIFO_CXSTALL (1 << 2) /* CX Stall */ -#define CXFIFO_TSTPKTFIN (1 << 1) /* Test packet data transfer finished */ -#define CXFIFO_CXFIN (1 << 0) /* CX data transfer finished */ - -/* IDLE Counter Register */ -#define IDLE_MS(x) ((x) & 0x07) /* PHY suspend delay = x ms */ - -/* Group Interrupt Mask(Disable) Register */ -#define GIMR_GRP2 (1 << 2) /* Disable interrupt group 2 */ -#define GIMR_GRP1 (1 << 1) /* Disable interrupt group 1 */ -#define GIMR_GRP0 (1 << 0) /* Disable interrupt group 0 */ -#define GIMR_MASK 0x07 - -/* Group Interrupt Mask(Disable) Register 0 (CX) */ -#define GIMR0_CXABORT (1 << 5) /* CX command abort interrupt */ -#define GIMR0_CXERR (1 << 4) /* CX command error interrupt */ -#define GIMR0_CXEND (1 << 3) /* CX command end interrupt */ -#define GIMR0_CXOUT (1 << 2) /* EP0-OUT packet interrupt */ -#define GIMR0_CXIN (1 << 1) /* EP0-IN packet interrupt */ -#define GIMR0_CXSETUP (1 << 0) /* EP0-SETUP packet interrupt */ -#define GIMR0_MASK 0x3f - -/* Group Interrupt Mask(Disable) Register 1 (FIFO) */ -#define GIMR1_FIFO_IN(x) (1 << (((x) & 3) + 16)) /* FIFOx IN */ -#define GIMR1_FIFO_TX(x) GIMR1_FIFO_IN(x) -#define GIMR1_FIFO_OUT(x) (1 << (((x) & 3) * 2)) /* FIFOx OUT */ -#define GIMR1_FIFO_SPK(x) (1 << (((x) & 3) * 2 + 1)) /* FIFOx SHORT PACKET */ -#define GIMR1_FIFO_RX(x) (GIMR1_FIFO_OUT(x) | GIMR1_FIFO_SPK(x)) -#define GIMR1_MASK 0xf00ff - -/* Group Interrupt Mask(Disable) Register 2 (Device) */ -#define GIMR2_WAKEUP (1 << 10) /* Device waked up */ -#define GIMR2_IDLE (1 << 9) /* Device idle */ -#define GIMR2_DMAERR (1 << 8) /* DMA error */ -#define GIMR2_DMAFIN (1 << 7) /* DMA finished */ -#define GIMR2_ZLPRX (1 << 6) /* Zero-Length-Packet Rx Interrupt */ -#define GIMR2_ZLPTX (1 << 5) /* Zero-Length-Packet Tx Interrupt */ -#define GIMR2_ISOCABT (1 << 4) /* ISOC Abort Interrupt */ -#define GIMR2_ISOCERR (1 << 3) /* ISOC Error Interrupt */ -#define GIMR2_RESUME (1 << 2) /* Resume state change Interrupt */ -#define GIMR2_SUSPEND (1 << 1) /* Suspend state change Interrupt */ -#define GIMR2_RESET (1 << 0) /* Reset Interrupt */ -#define GIMR2_MASK 0x7ff - -/* Group Interrupt Status Register */ -#define GISR_GRP2 (1 << 2) /* Interrupt group 2 */ -#define GISR_GRP1 (1 << 1) /* Interrupt group 1 */ -#define GISR_GRP0 (1 << 0) /* Interrupt group 0 */ - -/* Group Interrupt Status Register 0 (CX) */ -#define GISR0_CXABORT (1 << 5) /* CX command abort interrupt */ -#define GISR0_CXERR (1 << 4) /* CX command error interrupt */ -#define GISR0_CXEND (1 << 3) /* CX command end interrupt */ -#define GISR0_CXOUT (1 << 2) /* EP0-OUT packet interrupt */ -#define GISR0_CXIN (1 << 1) /* EP0-IN packet interrupt */ -#define GISR0_CXSETUP (1 << 0) /* EP0-SETUP packet interrupt */ - -/* Group Interrupt Status Register 1 (FIFO) */ -#define GISR1_IN_FIFO(x) (1 << (((x) & 0x03) + 16)) /* FIFOx IN */ -#define GISR1_OUT_FIFO(x) (1 << (((x) & 0x03) * 2)) /* FIFOx OUT */ -#define GISR1_SPK_FIFO(x) (1 << (((x) & 0x03) * 2 + 1)) /* FIFOx SPK */ -#define GISR1_RX_FIFO(x) (3 << (((x) & 0x03) * 2)) /* FIFOx OUT/SPK */ - -/* Group Interrupt Status Register 2 (Device) */ -#define GISR2_WAKEUP (1 << 10) /* Device waked up */ -#define GISR2_IDLE (1 << 9) /* Device idle */ -#define GISR2_DMAERR (1 << 8) /* DMA error */ -#define GISR2_DMAFIN (1 << 7) /* DMA finished */ -#define GISR2_ZLPRX (1 << 6) /* Zero-Length-Packet Rx Interrupt */ -#define GISR2_ZLPTX (1 << 5) /* Zero-Length-Packet Tx Interrupt */ -#define GISR2_ISOCABT (1 << 4) /* ISOC Abort Interrupt */ -#define GISR2_ISOCERR (1 << 3) /* ISOC Error Interrupt */ -#define GISR2_RESUME (1 << 2) /* Resume state change Interrupt */ -#define GISR2_SUSPEND (1 << 1) /* Suspend state change Interrupt */ -#define GISR2_RESET (1 << 0) /* Reset Interrupt */ - -/* Receive Zero-Length-Packet Register */ -#define RXZLP_EP(x) (1 << ((x) - 1)) /* EPx ZLP rx interrupt */ - -/* Transfer Zero-Length-Packet Register */ -#define TXZLP_EP(x) (1 << ((x) - 1)) /* EPx ZLP tx interrupt */ - -/* ISOC Error/Abort Status Register */ -#define ISOEASR_EP(x) (0x10001 << ((x) - 1)) /* EPx ISOC Error/Abort */ - -/* IN Endpoint Register */ -#define IEP_SENDZLP (1 << 15) /* Send Zero-Length-Packet */ -#define IEP_TNRHB(x) (((x) & 0x03) << 13) \ - /* Transaction Number for High-Bandwidth EP(ISOC) */ -#define IEP_RESET (1 << 12) /* Reset Toggle Sequence */ -#define IEP_STALL (1 << 11) /* Stall */ -#define IEP_MAXPS(x) ((x) & 0x7ff) /* Max. packet size */ - -/* OUT Endpoint Register */ -#define OEP_RESET (1 << 12) /* Reset Toggle Sequence */ -#define OEP_STALL (1 << 11) /* Stall */ -#define OEP_MAXPS(x) ((x) & 0x7ff) /* Max. packet size */ - -/* Endpoint Map Register (EP1 ~ EP4) */ -#define EPMAP14_SET_IN(ep, fifo) \ - ((fifo) & 3) << (((ep) - 1) << 3 + 0) -#define EPMAP14_SET_OUT(ep, fifo) \ - ((fifo) & 3) << (((ep) - 1) << 3 + 4) -#define EPMAP14_SET(ep, in, out) \ - do { \ - EPMAP14_SET_IN(ep, in); \ - EPMAP14_SET_OUT(ep, out); \ - } while (0) - -#define EPMAP14_DEFAULT 0x33221100 /* EP1->FIFO0, EP2->FIFO1... */ - -/* Endpoint Map Register (EP5 ~ EP8) */ -#define EPMAP58_SET_IN(ep, fifo) \ - ((fifo) & 3) << (((ep) - 5) << 3 + 0) -#define EPMAP58_SET_OUT(ep, fifo) \ - ((fifo) & 3) << (((ep) - 5) << 3 + 4) -#define EPMAP58_SET(ep, in, out) \ - do { \ - EPMAP58_SET_IN(ep, in); \ - EPMAP58_SET_OUT(ep, out); \ - } while (0) - -#define EPMAP58_DEFAULT 0x00000000 /* All EPx->FIFO0 */ - -/* FIFO Map Register */ -#define FIFOMAP_BIDIR (2 << 4) -#define FIFOMAP_IN (1 << 4) -#define FIFOMAP_OUT (0 << 4) -#define FIFOMAP_DIR_MASK 0x30 -#define FIFOMAP_EP(x) ((x) & 0x0f) -#define FIFOMAP_EP_MASK 0x0f -#define FIFOMAP_CFG_MASK 0x3f -#define FIFOMAP_DEFAULT 0x04030201 /* FIFO0->EP1, FIFO1->EP2... */ -#define FIFOMAP(fifo, cfg) (((cfg) & 0x3f) << (((fifo) & 3) << 3)) - -/* FIFO Configuration Register */ -#define FIFOCFG_EN (1 << 5) -#define FIFOCFG_BLKSZ_1024 (1 << 4) -#define FIFOCFG_BLKSZ_512 (0 << 4) -#define FIFOCFG_3BLK (2 << 2) -#define FIFOCFG_2BLK (1 << 2) -#define FIFOCFG_1BLK (0 << 2) -#define FIFOCFG_NBLK_MASK 3 -#define FIFOCFG_NBLK_SHIFT 2 -#define FIFOCFG_INTR (3 << 0) -#define FIFOCFG_BULK (2 << 0) -#define FIFOCFG_ISOC (1 << 0) -#define FIFOCFG_RSVD (0 << 0) /* Reserved */ -#define FIFOCFG_TYPE_MASK 3 -#define FIFOCFG_TYPE_SHIFT 0 -#define FIFOCFG_CFG_MASK 0x3f -#define FIFOCFG(fifo, cfg) (((cfg) & 0x3f) << (((fifo) & 3) << 3)) - -/* FIFO Control Status Register */ -#define FIFOCSR_RESET (1 << 12) /* FIFO Reset */ -#define FIFOCSR_BYTES(x) ((x) & 0x7ff) /* Length(bytes) for OUT-EP/FIFO */ - -/* DMA Target FIFO Register */ -#define DMAFIFO_CX (1 << 4) /* DMA FIFO = CX FIFO */ -#define DMAFIFO_FIFO(x) (1 << ((x) & 0x3)) /* DMA FIFO = FIFOx */ - -/* DMA Control Register */ -#define DMACTRL_LEN(x) (((x) & 0x1ffff) << 8) /* DMA length (Bytes) */ -#define DMACTRL_LEN_SHIFT 8 -#define DMACTRL_CLRFF (1 << 4) /* Clear FIFO upon DMA abort */ -#define DMACTRL_ABORT (1 << 3) /* DMA abort */ -#define DMACTRL_IO2IO (1 << 2) /* IO to IO */ -#define DMACTRL_FIFO2MEM (0 << 1) /* FIFO to Memory */ -#define DMACTRL_MEM2FIFO (1 << 1) /* Memory to FIFO */ -#define DMACTRL_START (1 << 0) /* DMA start */ - -#endif diff --git a/include/usb/fusbh200.h b/include/usb/fusbh200.h deleted file mode 100644 index 6ae1d848801..00000000000 --- a/include/usb/fusbh200.h +++ /dev/null @@ -1,59 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Faraday USB 2.0 EHCI Controller - * - * (C) Copyright 2010 Faraday Technology - * Dante Su <dantesu@faraday-tech.com> - */ - -#ifndef _FUSBH200_H -#define _FUSBH200_H - -struct fusbh200_regs { - struct { - uint32_t data[4]; - } hccr; /* 0x00 - 0x0f: hccr */ - struct { - uint32_t data[9]; - } hcor; /* 0x10 - 0x33: hcor */ - uint32_t easstr;/* 0x34: EOF&Async. Sched. Sleep Timer Register */ - uint32_t rsvd[2]; - uint32_t bmcsr; /* 0x40: Bus Monitor Control Status Register */ - uint32_t bmisr; /* 0x44: Bus Monitor Interrupt Status Register */ - uint32_t bmier; /* 0x48: Bus Monitor Interrupt Enable Register */ -}; - -/* EOF & Async. Schedule Sleep Timer Register */ -#define EASSTR_RUNNING (1 << 6) /* Put transceiver in running/resume mode */ -#define EASSTR_SUSPEND (0 << 6) /* Put transceiver in suspend mode */ -#define EASSTR_EOF2(x) (((x) & 0x3) << 4) /* EOF 2 Timing */ -#define EASSTR_EOF1(x) (((x) & 0x3) << 2) /* EOF 1 Timing */ -#define EASSTR_ASST(x) (((x) & 0x3) << 0) /* Async. Sched. Sleep Timer */ - -/* Bus Monitor Control Status Register */ -#define BMCSR_SPD_HIGH (2 << 9) /* Speed of the attached device */ -#define BMCSR_SPD_LOW (1 << 9) -#define BMCSR_SPD_FULL (0 << 9) -#define BMCSR_SPD_MASK (3 << 9) -#define BMCSR_SPD_SHIFT 9 -#define BMCSR_SPD(x) ((x >> 9) & 0x03) -#define BMCSR_VBUS (1 << 8) /* VBUS Valid */ -#define BMCSR_VBUS_OFF (1 << 4) /* VBUS Off */ -#define BMCSR_VBUS_ON (0 << 4) /* VBUS On */ -#define BMCSR_IRQLH (1 << 3) /* IRQ triggered at level-high */ -#define BMCSR_IRQLL (0 << 3) /* IRQ triggered at level-low */ -#define BMCSR_HALFSPD (1 << 2) /* Half speed mode for FPGA test */ -#define BMCSR_HFT_LONG (1 << 1) /* HDISCON noise filter = 270 us*/ -#define BMCSR_HFT (0 << 1) /* HDISCON noise filter = 135 us*/ -#define BMCSR_VFT_LONG (1 << 1) /* VBUS noise filter = 472 us*/ -#define BMCSR_VFT (0 << 1) /* VBUS noise filter = 135 us*/ - -/* Bus Monitor Interrupt Status Register */ -/* Bus Monitor Interrupt Enable Register */ -#define BMISR_DMAERR (1 << 4) /* DMA error */ -#define BMISR_DMA (1 << 3) /* DMA complete */ -#define BMISR_DEVRM (1 << 2) /* device removed */ -#define BMISR_OVD (1 << 1) /* over-current detected */ -#define BMISR_VBUSERR (1 << 0) /* VBUS error */ - -#endif |