diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-generic/sections.h | 2 | ||||
| -rw-r--r-- | include/cadence-nand.h | 529 | ||||
| -rw-r--r-- | include/configs/imxrt1020-evk.h | 2 | ||||
| -rw-r--r-- | include/configs/imxrt1050-evk.h | 2 | ||||
| -rw-r--r-- | include/configs/imxrt1170-evk.h | 2 | ||||
| -rw-r--r-- | include/configs/mocha.h | 25 | ||||
| -rw-r--r-- | include/configs/sandbox.h | 2 | ||||
| -rw-r--r-- | include/cpu_func.h | 17 | ||||
| -rw-r--r-- | include/crypto/mscode.h | 1 | ||||
| -rw-r--r-- | include/crypto/pkcs7_parser.h | 1 | ||||
| -rw-r--r-- | include/dm/ofnode_graph.h | 90 | ||||
| -rw-r--r-- | include/dt-bindings/pinctrl/adi-adsp.h | 21 | ||||
| -rw-r--r-- | include/efi_loader.h | 52 | ||||
| -rw-r--r-- | include/fat.h | 1 | ||||
| -rw-r--r-- | include/fs.h | 16 | ||||
| -rw-r--r-- | include/interrupt.h | 2 | ||||
| -rw-r--r-- | include/linux/mtd/rawnand.h | 12 | ||||
| -rw-r--r-- | include/mcheck.h | 13 | ||||
| -rw-r--r-- | include/miiphy.h | 29 | ||||
| -rw-r--r-- | include/net-common.h | 1 | ||||
| -rw-r--r-- | include/serial.h | 20 | ||||
| -rw-r--r-- | include/setjmp.h | 40 | ||||
| -rw-r--r-- | include/stdio_dev.h | 1 | ||||
| -rw-r--r-- | include/u-boot/sha1.h | 12 | ||||
| -rw-r--r-- | include/u-boot/sha256.h | 12 | ||||
| -rw-r--r-- | include/video_bridge.h | 54 |
26 files changed, 864 insertions, 95 deletions
diff --git a/include/asm-generic/sections.h b/include/asm-generic/sections.h index 3fd5c772a1a..024b1adde27 100644 --- a/include/asm-generic/sections.h +++ b/include/asm-generic/sections.h @@ -23,6 +23,7 @@ extern char __kprobes_text_start[], __kprobes_text_end[]; extern char __entry_text_start[], __entry_text_end[]; extern char __initdata_begin[], __initdata_end[]; extern char __start_rodata[], __end_rodata[]; +extern char __start_data[], __end_data[]; extern char __efi_helloworld_begin[]; extern char __efi_helloworld_end[]; extern char __efi_var_file_begin[]; @@ -63,6 +64,7 @@ static inline int arch_is_kernel_data(unsigned long addr) /* Start of U-Boot text region */ extern char __text_start[]; +extern char __text_end[]; /* This marks the text region which must be relocated */ extern char __image_copy_start[], __image_copy_end[]; diff --git a/include/cadence-nand.h b/include/cadence-nand.h new file mode 100644 index 00000000000..27ed217b1ed --- /dev/null +++ b/include/cadence-nand.h @@ -0,0 +1,529 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Cadence NAND flash controller driver + * + * Copyright (C) 2019 Cadence + * + * Author: Piotr Sroka <piotrs@cadence.com> + * + */ + +#ifndef _CADENCE_NAND_H_ +#define _CADENCE_NAND_H_ +#include <clk.h> +#include <reset.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/rawnand.h> + +/* + * HPNFC can work in 3 modes: + * - PIO - can work in master or slave DMA + * - CDMA - needs Master DMA for accessing command descriptors. + * - Generic mode - can use only slave DMA. + * CDMA and PIO modes can be used to execute only base commands. + * CDMA and PIO modes can be used to execute only base commands. + * Generic mode can be used to execute any command + * on NAND flash memory. Driver uses CDMA mode for + * block erasing, page reading, page programing. + * Generic mode is used for executing rest of commands. + */ + +#define DMA_DATA_SIZE_ALIGN 8 + +/* Register definition. */ +/* + * Command register 0. + * Writing data to this register will initiate a new transaction + * of the NF controller. + */ +#define CMD_REG0 0x0000 +/* Command type field mask. */ +#define CMD_REG0_CT GENMASK(31, 30) +/* Command type CDMA. */ +#define CMD_REG0_CT_CDMA 0uL +/* Command type generic. */ +#define CMD_REG0_CT_GEN 3uL +/* Command thread number field mask. */ +#define CMD_REG0_TN GENMASK(27, 24) + +/* Command register 2. */ +#define CMD_REG2 0x0008 +/* Command register 3. */ +#define CMD_REG3 0x000C +/* Pointer register to select which thread status will be selected. */ +#define CMD_STATUS_PTR 0x0010 +/* Command status register for selected thread. */ +#define CMD_STATUS 0x0014 + +/* Interrupt status register. */ +#define INTR_STATUS 0x0110 +#define INTR_STATUS_SDMA_ERR BIT(22) +#define INTR_STATUS_SDMA_TRIGG BIT(21) +#define INTR_STATUS_UNSUPP_CMD BIT(19) +#define INTR_STATUS_DDMA_TERR BIT(18) +#define INTR_STATUS_CDMA_TERR BIT(17) +#define INTR_STATUS_CDMA_IDL BIT(16) + +/* Interrupt enable register. */ +#define INTR_ENABLE 0x0114 +#define INTR_ENABLE_INTR_EN BIT(31) + +/* Controller internal state. */ +#define CTRL_STATUS 0x0118 +#define CTRL_STATUS_INIT_COMP BIT(9) +#define CTRL_STATUS_CTRL_BUSY BIT(8) + +/* Command Engine threads state. */ +#define TRD_STATUS 0x0120 + +/* Command Engine interrupt thread error status. */ +#define TRD_ERR_INT_STATUS 0x0128 +/* Command Engine interrupt thread error enable. */ +#define TRD_ERR_INT_STATUS_EN 0x0130 +/* Command Engine interrupt thread complete status. */ +#define TRD_COMP_INT_STATUS 0x0138 + +/* + * Transfer config 0 register. + * Configures data transfer parameters. + */ +#define TRAN_CFG_0 0x0400 +/* Offset value from the beginning of the page. */ +#define TRAN_CFG_0_OFFSET GENMASK(31, 16) +/* Numbers of sectors to transfer within singlNF device's page. */ +#define TRAN_CFG_0_SEC_CNT GENMASK(7, 0) + +/* + * Transfer config 1 register. + * Configures data transfer parameters. + */ +#define TRAN_CFG_1 0x0404 +/* Size of last data sector. */ +#define TRAN_CFG_1_LAST_SEC_SIZE GENMASK(31, 16) +/* Size of not-last data sector. */ +#define TRAN_CFG_1_SECTOR_SIZE GENMASK(15, 0) + +/* ECC engine configuration register 0. */ +#define ECC_CONFIG_0 0x0428 +/* Correction strength. */ +#define ECC_CONFIG_0_CORR_STR GENMASK(10, 8) +/* Enable erased pages detection mechanism. */ +#define ECC_CONFIG_0_ERASE_DET_EN BIT(1) +/* Enable controller ECC check bits generation and correction. */ +#define ECC_CONFIG_0_ECC_EN BIT(0) + +/* ECC engine configuration register 1. */ +#define ECC_CONFIG_1 0x042C + +/* Multiplane settings register. */ +#define MULTIPLANE_CFG 0x0434 +/* Cache operation settings. */ +#define CACHE_CFG 0x0438 + +/* Transferred data block size for the slave DMA module. */ +#define SDMA_SIZE 0x0440 + +/* Thread number associated with transferred data block + * for the slave DMA module. + */ +#define SDMA_TRD_NUM 0x0444 +/* Thread number mask. */ +#define SDMA_TRD_NUM_SDMA_TRD GENMASK(2, 0) + +#define CONTROL_DATA_CTRL 0x0494 +/* Thread number mask. */ +#define CONTROL_DATA_CTRL_SIZE GENMASK(15, 0) + +#define CTRL_VERSION 0x800 +#define CTRL_VERSION_REV GENMASK(7, 0) + +/* Available hardware features of the controller. */ +#define CTRL_FEATURES 0x804 +/* Support for NV-DDR2/3 work mode. */ +#define CTRL_FEATURES_NVDDR_2_3 BIT(28) +/* Support for NV-DDR work mode. */ +#define CTRL_FEATURES_NVDDR BIT(27) +/* Support for asynchronous work mode. */ +#define CTRL_FEATURES_ASYNC BIT(26) +/* Support for asynchronous work mode. */ +#define CTRL_FEATURES_N_BANKS GENMASK(25, 24) +/* Slave and Master DMA data width. */ +#define CTRL_FEATURES_DMA_DWITH64 BIT(21) +/* Availability of Control Data feature.*/ +#define CTRL_FEATURES_CONTROL_DATA BIT(10) + +/* BCH Engine identification register 0 - correction strengths. */ +#define BCH_CFG_0 0x838 +#define BCH_CFG_0_CORR_CAP_0 GENMASK(7, 0) +#define BCH_CFG_0_CORR_CAP_1 GENMASK(15, 8) +#define BCH_CFG_0_CORR_CAP_2 GENMASK(23, 16) +#define BCH_CFG_0_CORR_CAP_3 GENMASK(31, 24) + +/* BCH Engine identification register 1 - correction strengths. */ +#define BCH_CFG_1 0x83C +#define BCH_CFG_1_CORR_CAP_4 GENMASK(7, 0) +#define BCH_CFG_1_CORR_CAP_5 GENMASK(15, 8) +#define BCH_CFG_1_CORR_CAP_6 GENMASK(23, 16) +#define BCH_CFG_1_CORR_CAP_7 GENMASK(31, 24) + +/* BCH Engine identification register 2 - sector sizes. */ +#define BCH_CFG_2 0x840 +#define BCH_CFG_2_SECT_0 GENMASK(15, 0) +#define BCH_CFG_2_SECT_1 GENMASK(31, 16) + +/* BCH Engine identification register 3. */ +#define BCH_CFG_3 0x844 +#define BCH_CFG_3_METADATA_SIZE GENMASK(23, 16) + +/* Ready/Busy# line status. */ +#define RBN_SETINGS 0x1004 + +/* Common settings. */ +#define COMMON_SET 0x1008 +/* 16 bit device connected to the NAND Flash interface. */ +#define COMMON_SET_DEVICE_16BIT BIT(8) + +/* Skip_bytes registers. */ +#define SKIP_BYTES_CONF 0x100C +#define SKIP_BYTES_MARKER_VALUE GENMASK(31, 16) +#define SKIP_BYTES_NUM_OF_BYTES GENMASK(7, 0) + +#define SKIP_BYTES_OFFSET 0x1010 +#define SKIP_BYTES_OFFSET_VALUE GENMASK(23, 0) + +/* Timings configuration. */ +#define ASYNC_TOGGLE_TIMINGS 0x101c +#define ASYNC_TOGGLE_TIMINGS_TRH GENMASK(28, 24) +#define ASYNC_TOGGLE_TIMINGS_TRP GENMASK(20, 16) +#define ASYNC_TOGGLE_TIMINGS_TWH GENMASK(12, 8) +#define ASYNC_TOGGLE_TIMINGS_TWP GENMASK(4, 0) + +#define TIMINGS0 0x1024 +#define TIMINGS0_TADL GENMASK(31, 24) +#define TIMINGS0_TCCS GENMASK(23, 16) +#define TIMINGS0_TWHR GENMASK(15, 8) +#define TIMINGS0_TRHW GENMASK(7, 0) + +#define TIMINGS1 0x1028 +#define TIMINGS1_TRHZ GENMASK(31, 24) +#define TIMINGS1_TWB GENMASK(23, 16) +#define TIMINGS1_TVDLY GENMASK(7, 0) + +#define TIMINGS2 0x102c +#define TIMINGS2_TFEAT GENMASK(25, 16) +#define TIMINGS2_CS_HOLD_TIME GENMASK(13, 8) +#define TIMINGS2_CS_SETUP_TIME GENMASK(5, 0) + +/* Configuration of the resynchronization of slave DLL of PHY. */ +#define DLL_PHY_CTRL 0x1034 +#define DLL_PHY_CTRL_DLL_RST_N BIT(24) +#define DLL_PHY_CTRL_EXTENDED_WR_MODE BIT(17) +#define DLL_PHY_CTRL_EXTENDED_RD_MODE BIT(16) +#define DLL_PHY_CTRL_RS_HIGH_WAIT_CNT GENMASK(11, 8) +#define DLL_PHY_CTRL_RS_IDLE_CNT GENMASK(7, 0) + +/* TODO: - Identify better way to handle PHY address */ +#define PHY_OFFSET 0x10000 + +/* Register controlling DQ related timing. */ +#define PHY_DQ_TIMING PHY_OFFSET + 0x2000 +/* Register controlling DSQ related timing. */ +#define PHY_DQS_TIMING PHY_OFFSET + 0x2004 +#define PHY_DQS_TIMING_DQS_SEL_OE_END GENMASK(3, 0) +#define PHY_DQS_TIMING_PHONY_DQS_SEL BIT(16) +#define PHY_DQS_TIMING_USE_PHONY_DQS BIT(20) + +/* Register controlling the gate and loopback control related timing. */ +#define PHY_GATE_LPBK_CTRL PHY_OFFSET + 0x2008 +#define PHY_GATE_LPBK_CTRL_RDS GENMASK(24, 19) + +/* Register holds the control for the master DLL logic. */ +#define PHY_DLL_MASTER_CTRL PHY_OFFSET + 0x200C +#define PHY_DLL_MASTER_CTRL_BYPASS_MODE BIT(23) + +/* Register holds the control for the slave DLL logic. */ +#define PHY_DLL_SLAVE_CTRL PHY_OFFSET + 0x2010 + +/* This register handles the global control settings for the PHY. */ +#define PHY_CTRL PHY_OFFSET + 0x2080 +#define PHY_CTRL_SDR_DQS BIT(14) +#define PHY_CTRL_PHONY_DQS GENMASK(9, 4) + +/* + * This register handles the global control settings + * for the termination selects for reads. + */ +#define PHY_TSEL PHY_OFFSET + 0x2084 + +/* Generic command layout. */ +#define GCMD_LAY_CS GENMASK_ULL(11, 8) +/* + * This bit informs the minicotroller if it has to wait for tWB + * after sending the last CMD/ADDR/DATA in the sequence. + */ +#define GCMD_LAY_TWB BIT_ULL(6) +/* Type of generic instruction. */ +#define GCMD_LAY_INSTR GENMASK_ULL(5, 0) + +/* Generic CMD sequence type. */ +#define GCMD_LAY_INSTR_CMD 0 +/* Generic ADDR sequence type. */ +#define GCMD_LAY_INSTR_ADDR 1 +/* Generic data transfer sequence type. */ +#define GCMD_LAY_INSTR_DATA 2 + +/* Input part of generic command type of input is command. */ +#define GCMD_LAY_INPUT_CMD GENMASK_ULL(23, 16) + +/* Generic command address sequence - address fields. */ +#define GCMD_LAY_INPUT_ADDR GENMASK_ULL(63, 16) +/* Generic command address sequence - address size. */ +#define GCMD_LAY_INPUT_ADDR_SIZE GENMASK_ULL(13, 11) + +/* Transfer direction field of generic command data sequence. */ +#define GCMD_DIR BIT_ULL(11) +/* Read transfer direction of generic command data sequence. */ +#define GCMD_DIR_READ 0 +/* Write transfer direction of generic command data sequence. */ +#define GCMD_DIR_WRITE 1 + +/* ECC enabled flag of generic command data sequence - ECC enabled. */ +#define GCMD_ECC_EN BIT_ULL(12) +/* Generic command data sequence - sector size. */ +#define GCMD_SECT_SIZE GENMASK_ULL(31, 16) +/* Generic command data sequence - sector count. */ +#define GCMD_SECT_CNT GENMASK_ULL(39, 32) +/* Generic command data sequence - last sector size. */ +#define GCMD_LAST_SIZE GENMASK_ULL(55, 40) + +/* CDMA descriptor fields. */ +/* Erase command type of CDMA descriptor. */ +#define CDMA_CT_ERASE 0x1000 +/* Program page command type of CDMA descriptor. */ +#define CDMA_CT_WR 0x2100 +/* Read page command type of CDMA descriptor. */ +#define CDMA_CT_RD 0x2200 + +/* Flash pointer memory shift. */ +#define CDMA_CFPTR_MEM_SHIFT 24 +/* Flash pointer memory mask. */ +#define CDMA_CFPTR_MEM GENMASK(26, 24) + +/* + * Command DMA descriptor flags. If set causes issue interrupt after + * the completion of descriptor processing. + */ +#define CDMA_CF_INT BIT(8) +/* + * Command DMA descriptor flags - the next descriptor + * address field is valid and descriptor processing should continue. + */ +#define CDMA_CF_CONT BIT(9) +/* DMA master flag of command DMA descriptor. */ +#define CDMA_CF_DMA_MASTER BIT(10) + +/* Operation complete status of command descriptor. */ +#define CDMA_CS_COMP BIT(15) +/* Operation complete status of command descriptor. */ +/* Command descriptor status - operation fail. */ +#define CDMA_CS_FAIL BIT(14) +/* Command descriptor status - page erased. */ +#define CDMA_CS_ERP BIT(11) +/* Command descriptor status - timeout occurred. */ +#define CDMA_CS_TOUT BIT(10) +/* + * Maximum amount of correction applied to one ECC sector. + * It is part of command descriptor status. + */ +#define CDMA_CS_MAXERR GENMASK(9, 2) +/* Command descriptor status - uncorrectable ECC error. */ +#define CDMA_CS_UNCE BIT(1) +/* Command descriptor status - descriptor error. */ +#define CDMA_CS_ERR BIT(0) + +/* Status of operation - OK. */ +#define STAT_OK 0 +/* Status of operation - FAIL. */ +#define STAT_FAIL 2 +/* Status of operation - uncorrectable ECC error. */ +#define STAT_ECC_UNCORR 3 +/* Status of operation - page erased. */ +#define STAT_ERASED 5 +/* Status of operation - correctable ECC error. */ +#define STAT_ECC_CORR 6 +/* Status of operation - unsuspected state. */ +#define STAT_UNKNOWN 7 +/* Status of operation - operation is not completed yet. */ +#define STAT_BUSY 0xFF + +#define BCH_MAX_NUM_CORR_CAPS 8 +#define BCH_MAX_NUM_SECTOR_SIZES 2 + +#define ONE_CYCLE 1 +#define TIMEOUT_US 1000000 + +struct cadence_nand_timings { + u32 async_toggle_timings; + u32 timings0; + u32 timings1; + u32 timings2; + u32 dll_phy_ctrl; + u32 phy_ctrl; + u32 phy_dqs_timing; + u32 phy_gate_lpbk_ctrl; +}; + +/* Command DMA descriptor. */ +struct cadence_nand_cdma_desc { + /* Next descriptor address. */ + u64 next_pointer; + + /* Flash address is a 32-bit address comprising of BANK and ROW ADDR. */ + u32 flash_pointer; + /*field appears in HPNFC version 13*/ + u16 bank; + u16 rsvd0; + + /* Operation the controller needs to perform. */ + u16 command_type; + u16 rsvd1; + /* Flags for operation of this command. */ + u16 command_flags; + u16 rsvd2; + + /* System/host memory address required for data DMA commands. */ + u64 memory_pointer; + + /* Status of operation. */ + u32 status; + u32 rsvd3; + + /* Address pointer to sync buffer location. */ + u64 sync_flag_pointer; + + /* Controls the buffer sync mechanism. */ + u32 sync_arguments; + u32 rsvd4; + + /* Control data pointer. */ + u64 ctrl_data_ptr; +}; + +/* Interrupt status. */ +struct cadence_nand_irq_status { + /* Thread operation complete status. */ + u32 trd_status; + /* Thread operation error. */ + u32 trd_error; + /* Controller status. */ + u32 status; +}; + +/* Cadence NAND flash controller capabilities get from driver data. */ +struct cadence_nand_dt_devdata { + /* Skew value of the output signals of the NAND Flash interface. */ + u32 if_skew; + /* It informs if slave DMA interface is connected to DMA engine. */ + unsigned int has_dma:1; +}; + +/* Cadence NAND flash controller capabilities read from registers. */ +struct cdns_nand_caps { + /* Maximum number of banks supported by hardware. */ + u8 max_banks; + /* Slave and Master DMA data width in bytes (4 or 8). */ + u8 data_dma_width; + /* Control Data feature supported. */ + bool data_control_supp; + /* Is PHY type DLL. */ + bool is_phy_type_dll; +}; + +struct cadence_nand_info { + struct nand_hw_control controller; + struct udevice *dev; + struct reset_ctl softphy_reset; + struct reset_ctl nand_reset; + struct cadence_nand_cdma_desc *cdma_desc; + /* IP capability. */ + const struct cadence_nand_dt_devdata *caps1; + struct cdns_nand_caps caps2; + u8 ctrl_rev; + dma_addr_t dma_cdma_desc; + /* command interface buffers */ + u8 *buf; + u32 buf_size; + u8 *stat; + u8 cmd; + u32 buf_index; + + u8 curr_corr_str_idx; + + /* Register interface. */ + void __iomem *reg; + + struct { + void __iomem *virt; + dma_addr_t dma; + } io; + + int irq; + /* Interrupts that have happened. */ + struct cadence_nand_irq_status irq_status; + /* Interrupts we are waiting for. */ + struct cadence_nand_irq_status irq_mask; + + int ecc_strengths[BCH_MAX_NUM_CORR_CAPS]; + struct nand_ecc_step_info ecc_stepinfos[BCH_MAX_NUM_SECTOR_SIZES]; + struct nand_ecc_caps ecc_caps; + + int curr_trans_type; + + struct clk clk; + u32 nf_clk_rate; + /* + * Estimated Board delay. The value includes the total + * round trip delay for the signals and is used for deciding on values + * associated with data read capture. + */ + u32 board_delay; + + struct nand_chip *selected_chip; + + unsigned long assigned_cs; + struct list_head chips; + u8 bch_metadata_size; +}; + +struct cdns_nand_chip { + struct cadence_nand_timings timings; + struct nand_chip chip; + u8 nsels; + struct list_head node; + + /* + * part of oob area of NAND flash memory page. + * This part is available for user to read or write. + */ + u32 avail_oob_size; + + /* Sector size. There are few sectors per mtd->writesize */ + u32 sector_size; + u32 sector_count; + + /* Offset of BBM. */ + u8 bbm_offs; + /* Number of bytes reserved for BBM. */ + u8 bbm_len; + /* ECC strength index. */ + u8 corr_str_idx; + + u8 cs[]; +}; + +struct ecc_info { + int (*calc_ecc_bytes)(int step_size, int strength); + int max_step_size; +}; + +#endif /*_CADENCE_NAND_H_*/ diff --git a/include/configs/imxrt1020-evk.h b/include/configs/imxrt1020-evk.h index cd6af93454b..aec12082b95 100644 --- a/include/configs/imxrt1020-evk.h +++ b/include/configs/imxrt1020-evk.h @@ -9,8 +9,6 @@ #include <asm/arch/imx-regs.h> -#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 1 - #define PHYS_SDRAM 0x80000000 #define PHYS_SDRAM_SIZE (32 * 1024 * 1024) diff --git a/include/configs/imxrt1050-evk.h b/include/configs/imxrt1050-evk.h index c520c2fc203..5b8d6a7ac05 100644 --- a/include/configs/imxrt1050-evk.h +++ b/include/configs/imxrt1050-evk.h @@ -9,8 +9,6 @@ #include <asm/arch/imx-regs.h> -#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 1 - #define PHYS_SDRAM 0x80000000 #define PHYS_SDRAM_SIZE (32 * 1024 * 1024) diff --git a/include/configs/imxrt1170-evk.h b/include/configs/imxrt1170-evk.h index 1ccaa15bc11..f821212765c 100644 --- a/include/configs/imxrt1170-evk.h +++ b/include/configs/imxrt1170-evk.h @@ -10,8 +10,6 @@ #include <asm/arch/imx-regs.h> -#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 1 - /* * Configuration of the external SDRAM memory */ diff --git a/include/configs/mocha.h b/include/configs/mocha.h new file mode 100644 index 00000000000..1c2eb906085 --- /dev/null +++ b/include/configs/mocha.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + * + * Copyright (c) 2024, Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "tegra124-common.h" + +/* High-level configuration options */ +#define CFG_TEGRA_BOARD_STRING "Xiaomi Mocha" + +/* Board-specific serial config */ +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE + +#ifdef CONFIG_TEGRA_SUPPORT_NON_SECURE + #define CFG_PRAM 0x38400 /* 225 MB */ +#endif + +#include "tegra-common-post.h" + +#endif /* __CONFIG_H */ diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index 2372485c84e..db2ac7f83bb 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -6,7 +6,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CFG_MALLOC_F_ADDR 0x0010000 +#define CFG_MALLOC_F_ADDR 0x000f4000 /* Size of our emulated memory */ #define SB_CONCAT(x, y) x ## y diff --git a/include/cpu_func.h b/include/cpu_func.h index 7e81c4364a7..70a41ead3f7 100644 --- a/include/cpu_func.h +++ b/include/cpu_func.h @@ -69,6 +69,23 @@ void flush_dcache_range(unsigned long start, unsigned long stop); void invalidate_dcache_range(unsigned long start, unsigned long stop); void invalidate_dcache_all(void); void invalidate_icache_all(void); + +enum pgprot_attrs { + MMU_ATTR_RO, + MMU_ATTR_RX, + MMU_ATTR_RW, +}; + +/** pgprot_set_attrs() - Set page table permissions + * + * @addr: Physical address start + * @size: size of memory to change + * @perm: New permissions + * + * Return: 0 on success, error otherwise. + **/ +int pgprot_set_attrs(phys_addr_t addr, size_t size, enum pgprot_attrs perm); + /** * noncached_init() - Initialize non-cached memory region * diff --git a/include/crypto/mscode.h b/include/crypto/mscode.h index 678e69001b9..55501c22acb 100644 --- a/include/crypto/mscode.h +++ b/include/crypto/mscode.h @@ -10,6 +10,7 @@ #include <crypto/hash_info.h> #endif #if CONFIG_IS_ENABLED(MBEDTLS_LIB_X509) +#include "mbedtls_options.h" #include <mbedtls/asn1.h> #include <mbedtls/oid.h> #endif diff --git a/include/crypto/pkcs7_parser.h b/include/crypto/pkcs7_parser.h index 469c2711fa6..fd1e48da09e 100644 --- a/include/crypto/pkcs7_parser.h +++ b/include/crypto/pkcs7_parser.h @@ -12,6 +12,7 @@ #include <crypto/pkcs7.h> #include <crypto/x509_parser.h> #if CONFIG_IS_ENABLED(MBEDTLS_LIB_X509) +#include "mbedtls_options.h" #include <mbedtls/pkcs7.h> #include <library/x509_internal.h> #include <mbedtls/asn1.h> diff --git a/include/dm/ofnode_graph.h b/include/dm/ofnode_graph.h new file mode 100644 index 00000000000..908c990a3f3 --- /dev/null +++ b/include/dm/ofnode_graph.h @@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2025 Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#ifndef _DM_OFNODE_GRAPH_H +#define _DM_OFNODE_GRAPH_H + +#include <dm/of.h> + +/** + * ofnode_graph_get_endpoint_count() - get the number of endpoints in a device ofnode + * @parent: ofnode to the device containing ports and endpoints + * + * Return: count of endpoint of this device ofnode + */ +unsigned int ofnode_graph_get_endpoint_count(ofnode parent); + +/** + * ofnode_graph_get_port_count() - get the number of port in a device or ports ofnode + * @parent: ofnode to the device or ports node + * + * Return: count of port of this device or ports node + */ +unsigned int ofnode_graph_get_port_count(ofnode parent); + +/** + * ofnode_graph_get_port_by_id() - get the port matching a given id + * @parent: parent ofnode + * @id: id of the port + * + * Return: ofnode in given port. + */ +ofnode ofnode_graph_get_port_by_id(ofnode parent, u32 id); + +/** + * ofnode_graph_get_endpoint_by_regs() - get the endpoint matching a given id + * @parent: parent ofnode + * @reg_id: id of the port + * @id: id for the endpoint + * + * Return: ofnode in given endpoint or NULL if not found. + * reg and port_reg are ignored when they are -1. + */ +ofnode ofnode_graph_get_endpoint_by_regs(ofnode parent, u32 reg_id, u32 id); + +/** + * ofnode_graph_get_remote_endpoint() - get remote endpoint node + * @endoint: ofnode of a local endpoint + * + * Return: Remote endpoint ofnode linked with local endpoint. + */ +ofnode ofnode_graph_get_remote_endpoint(ofnode endpoint); + +/** + * ofnode_graph_get_port_parent() - get port's parent node + * @endpoint: ofnode of a local endpoint + * + * Return: device ofnode associated with endpoint + */ +ofnode ofnode_graph_get_port_parent(ofnode endpoint); + +/** + * ofnode_graph_get_remote_port_parent() - get remote port's parent ofnode + * @endoint: ofnode of a local endpoint + * + * Return: device ofnode associated with endpoint linked to local endpoint. + */ +ofnode ofnode_graph_get_remote_port_parent(ofnode endpoint); + +/** + * ofnode_graph_get_remote_port() - get remote port ofnode + * @endoint: ofnode of a local endpoint + * + * Return: port ofnode associated with remote endpoint node linked + * to local endpoint. + */ +ofnode ofnode_graph_get_remote_port(ofnode endpoint); + +/** + * ofnode_graph_get_remote_node() - get remote parent ofnode for given port/endpoint + * @parent: parent ofnode containing graph port/endpoint + * @port: identifier (value of reg property) of the parent port ofnode + * @endpoint: identifier (value of reg property) of the endpoint ofnode + * + * Return: device ofnode associated with endpoint linked to local endpoint. + */ +ofnode ofnode_graph_get_remote_node(ofnode parent, u32 port, u32 endpoint); + +#endif diff --git a/include/dt-bindings/pinctrl/adi-adsp.h b/include/dt-bindings/pinctrl/adi-adsp.h new file mode 100644 index 00000000000..7dc8a1ef5c4 --- /dev/null +++ b/include/dt-bindings/pinctrl/adi-adsp.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * (C) Copyright 2022 - Analog Devices, Inc. + * + * Written and/or maintained by Timesys Corporation + * + * Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com> + * Contact: Greg Malysa <greg.malysa@timesys.com> + * + */ + +#ifndef DT_BINDINGS_PINCTRL_ADI_ADSP +#define DT_BINDINGS_PINCTRL_ADI_ADSP + +#define ADI_ADSP_PIN(port, pin) (16 * ((port) - 'A') + (pin)) +#define ADI_ADSP_PINFUNC_ALT0 0 +#define ADI_ADSP_PINFUNC_ALT1 1 +#define ADI_ADSP_PINFUNC_ALT2 2 +#define ADI_ADSP_PINFUNC_ALT3 3 + +#endif diff --git a/include/efi_loader.h b/include/efi_loader.h index 1d75d97ebbc..e9c10819ba2 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -15,13 +15,13 @@ #include <efi_api.h> #include <image.h> #include <pe.h> +#include <setjmp.h> #include <linux/list.h> #include <linux/sizes.h> #include <linux/oid_registry.h> struct blk_desc; struct bootflow; -struct jmp_buf_data; #if CONFIG_IS_ENABLED(EFI_LOADER) @@ -129,17 +129,22 @@ static inline void efi_set_bootdev(const char *dev, const char *devnr, #if CONFIG_IS_ENABLED(NETDEVICES) && CONFIG_IS_ENABLED(EFI_LOADER) /* Call this to update the current device path of the efi net device */ -efi_status_t efi_net_set_dp(const char *dev, const char *server); +efi_status_t efi_net_new_dp(const char *dev, const char *server, struct udevice *udev); /* Call this to get the current device path of the efi net device */ -void efi_net_get_dp(struct efi_device_path **dp); +void efi_net_dp_from_dev(struct efi_device_path **dp, struct udevice *udev, bool cache_only); void efi_net_get_addr(struct efi_ipv4_address *ip, struct efi_ipv4_address *mask, - struct efi_ipv4_address *gw); + struct efi_ipv4_address *gw, + struct udevice *dev); void efi_net_set_addr(struct efi_ipv4_address *ip, struct efi_ipv4_address *mask, - struct efi_ipv4_address *gw); + struct efi_ipv4_address *gw, + struct udevice *dev); +#if IS_ENABLED(CONFIG_EFI_HTTP_PROTOCOL) efi_status_t efi_net_do_request(u8 *url, enum efi_http_method method, void **buffer, - u32 *status_code, ulong *file_size, char *headers_buffer); + u32 *status_code, ulong *file_size, char *headers_buffer, + struct efi_service_binding_protocol *parent); +#endif #define MAX_HTTP_HEADERS_SIZE SZ_64K #define MAX_HTTP_HEADERS 100 #define MAX_HTTP_HEADER_NAME 128 @@ -151,13 +156,16 @@ struct http_header { void efi_net_parse_headers(ulong *num_headers, struct http_header *headers); #else -static inline void efi_net_get_dp(struct efi_device_path **dp) { } +static inline void efi_net_dp_from_dev(struct efi_device_path **dp, + struct udevice *udev, bool cache_only) { } static inline void efi_net_get_addr(struct efi_ipv4_address *ip, struct efi_ipv4_address *mask, - struct efi_ipv4_address *gw) { } + struct efi_ipv4_address *gw, + struct udevice *dev) { } static inline void efi_net_set_addr(struct efi_ipv4_address *ip, struct efi_ipv4_address *mask, - struct efi_ipv4_address *gw) { } + struct efi_ipv4_address *gw, + struct udevice *dev) { } #endif /* Maximum number of configuration tables */ @@ -321,6 +329,8 @@ extern const efi_guid_t efi_guid_host_dev; #endif /* GUID of the EFI_BLOCK_IO_PROTOCOL */ extern const efi_guid_t efi_block_io_guid; +/* GUID of the EFI_SIMPLE_NETWORK_PROTOCOL */ +extern const efi_guid_t efi_net_guid; extern const efi_guid_t efi_global_variable_guid; extern const efi_guid_t efi_guid_console_control; extern const efi_guid_t efi_guid_device_path; @@ -485,7 +495,7 @@ struct efi_loaded_image_obj { efi_status_t *exit_status; efi_uintn_t *exit_data_size; u16 **exit_data; - struct jmp_buf_data *exit_jmp; + jmp_buf *exit_jmp; EFIAPI efi_status_t (*entry)(efi_handle_t image_handle, struct efi_system_table *st); u16 image_type; @@ -647,7 +657,8 @@ int efi_disk_create_partitions(efi_handle_t parent, struct blk_desc *desc, /* Called by bootefi to make GOP (graphical) interface available */ efi_status_t efi_gop_register(void); /* Called by bootefi to make the network interface available */ -efi_status_t efi_net_register(void); +efi_status_t efi_net_register(struct udevice *dev); +efi_status_t efi_net_do_start(struct udevice *dev); /* Called by efi_net_register to make the ip4 config2 protocol available */ efi_status_t efi_ipconfig_register(const efi_handle_t handle, struct efi_ip4_config2_protocol *ip4config); @@ -733,6 +744,10 @@ efi_status_t efi_search_protocol(const efi_handle_t handle, efi_status_t efi_add_protocol(const efi_handle_t handle, const efi_guid_t *protocol, void *protocol_interface); +/* Uninstall new protocol on a handle */ +efi_status_t efi_uninstall_protocol + (efi_handle_t handle, const efi_guid_t *protocol, + void *protocol_interface, bool preserve); /* Reinstall a protocol on a handle */ efi_status_t EFIAPI efi_reinstall_protocol_interface( efi_handle_t handle, @@ -748,6 +763,15 @@ efi_status_t EFIAPI efi_install_multiple_protocol_interfaces(efi_handle_t *handle, ...); efi_status_t EFIAPI efi_uninstall_multiple_protocol_interfaces(efi_handle_t handle, ...); +/* Connect and disconnect controller */ +efi_status_t EFIAPI efi_connect_controller(efi_handle_t controller_handle, + efi_handle_t *driver_image_handle, + struct efi_device_path *remain_device_path, + bool recursive); +efi_status_t EFIAPI efi_disconnect_controller( + efi_handle_t controller_handle, + efi_handle_t driver_image_handle, + efi_handle_t child_handle); /* Get handles that support a given protocol */ efi_status_t EFIAPI efi_locate_handle_buffer( enum efi_locate_search_type search_type, @@ -768,6 +792,8 @@ efi_status_t efi_create_event(uint32_t type, efi_uintn_t notify_tpl, void *context), void *notify_context, const efi_guid_t *group, struct efi_event **event); +/* Call this to close an event */ +efi_status_t EFIAPI efi_close_event(struct efi_event *event); /* Call this to set a timer */ efi_status_t efi_set_timer(struct efi_event *event, enum efi_timer_delay type, uint64_t trigger_time); @@ -907,8 +933,8 @@ struct efi_device_path *efi_dp_from_part(struct blk_desc *desc, int part); struct efi_device_path *efi_dp_part_node(struct blk_desc *desc, int part); struct efi_device_path *efi_dp_from_file(const struct efi_device_path *dp, const char *path); -struct efi_device_path *efi_dp_from_eth(void); -struct efi_device_path *efi_dp_from_http(const char *server); +struct efi_device_path *efi_dp_from_eth(struct udevice *dev); +struct efi_device_path *efi_dp_from_http(const char *server, struct udevice *dev); struct efi_device_path *efi_dp_from_mem(uint32_t mem_type, uint64_t start_address, size_t size); diff --git a/include/fat.h b/include/fat.h index 3dce99a23cf..ca97880de12 100644 --- a/include/fat.h +++ b/include/fat.h @@ -206,6 +206,7 @@ int fat_opendir(const char *filename, struct fs_dir_stream **dirsp); int fat_readdir(struct fs_dir_stream *dirs, struct fs_dirent **dentp); void fat_closedir(struct fs_dir_stream *dirs); int fat_unlink(const char *filename); +int fat_rename(const char *old_path, const char *new_path); int fat_mkdir(const char *dirname); void fat_close(void); void *fat_next_cluster(fat_itr *itr, unsigned int *nbytes); diff --git a/include/fs.h b/include/fs.h index 2474880385d..54449faf2e5 100644 --- a/include/fs.h +++ b/include/fs.h @@ -86,7 +86,7 @@ int fs_set_blk_dev_with_part(struct blk_desc *desc, int part); * * Many file functions implicitly call fs_close(), e.g. fs_closedir(), * fs_exist(), fs_ln(), fs_ls(), fs_mkdir(), fs_read(), fs_size(), fs_write(), - * fs_unlink(). + * fs_unlink(), fs_rename(). */ void fs_close(void); @@ -270,6 +270,18 @@ int fs_unlink(const char *filename); */ int fs_mkdir(const char *filename); +/** + * fs_rename - rename/move a file or directory + * + * @old_path: existing path of the file/directory to rename + * @new_path: new path of the file/directory. If this points to an existing + * file or empty directory, the existing file/directory will be unlinked. + * If this points to a non-empty directory, the rename will fail. + * + * Return: 0 on success, -1 on error conditions + */ +int fs_rename(const char *old_path, const char *new_path); + /* * Common implementation for various filesystem commands, optionally limited * to a specific filesystem type via the fstype parameter. @@ -290,6 +302,8 @@ int do_mkdir(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[], int fstype); int do_ln(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[], int fstype); +int do_mv(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[], + int fstype); /* * Determine the UUID of the specified filesystem and print it. Optionally it is diff --git a/include/interrupt.h b/include/interrupt.h index 46ef2e196d4..6ea28b54a56 100644 --- a/include/interrupt.h +++ b/include/interrupt.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include <asm/setjmp.h> +#include <setjmp.h> /** * struct resume_data - data for resume after interrupt diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index 2d85b392465..3e80b134063 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -132,6 +132,17 @@ void nand_wait_ready(struct mtd_info *mtd); #define NAND_DATA_IFACE_CHECK_ONLY -1 /* + * There are different places where the manufacturer stores the factory bad + * block markers. + * + * Position within the block: Each of these pages needs to be checked for a + * bad block marking pattern. + */ +#define NAND_BBM_FIRSTPAGE BIT(24) +#define NAND_BBM_SECONDPAGE BIT(25) +#define NAND_BBM_LASTPAGE BIT(26) + +/* * Constants for ECC_MODES */ typedef enum { @@ -981,6 +992,7 @@ struct nand_chip { struct nand_bbt_descr *bbt_md; struct nand_bbt_descr *badblock_pattern; + int cur_cs; void *priv; diff --git a/include/mcheck.h b/include/mcheck.h index bd506ae6291..4b11751ebcc 100644 --- a/include/mcheck.h +++ b/include/mcheck.h @@ -1,18 +1,7 @@ -/* SPDX-License-Identifier: GPL-2.1+ */ +/* SPDX-License-Identifier: LGPL-2.1-or-later */ /* * Copyright (C) 1996-2024 Free Software Foundation, Inc. * This file is part of the GNU C Library. - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * <https://www.gnu.org/licenses/>. */ #ifndef _MCHECK_H #define _MCHECK_H 1 diff --git a/include/miiphy.h b/include/miiphy.h index b879fd16ae3..00d0b9b6a43 100644 --- a/include/miiphy.h +++ b/include/miiphy.h @@ -33,8 +33,6 @@ int miiphy_is_1000base_x(const char *devname, unsigned char addr); int miiphy_link(const char *devname, unsigned char addr); #endif -void miiphy_init(void); - int miiphy_set_current_dev(const char *devname); const char *miiphy_get_current_dev(void); struct mii_dev *mdio_get_current_dev(void); @@ -44,7 +42,6 @@ struct phy_device *mdio_phydev_for_ethname(const char *devname); void miiphy_listdev(void); -void mdio_init(struct mii_dev *bus); struct mii_dev *mdio_alloc(void); void mdio_free(struct mii_dev *bus); int mdio_register(struct mii_dev *bus); @@ -64,23 +61,19 @@ void mdio_list_devices(void); #define BB_MII_DEVNAME "bb_miiphy" -struct bb_miiphy_bus { - int (*mdio_active)(struct bb_miiphy_bus *bus); - int (*mdio_tristate)(struct bb_miiphy_bus *bus); - int (*set_mdio)(struct bb_miiphy_bus *bus, int v); - int (*get_mdio)(struct bb_miiphy_bus *bus, int *v); - int (*set_mdc)(struct bb_miiphy_bus *bus, int v); - int (*delay)(struct bb_miiphy_bus *bus); - void *priv; - struct mii_dev mii; +struct bb_miiphy_bus_ops { + int (*mdio_active)(struct mii_dev *miidev); + int (*mdio_tristate)(struct mii_dev *miidev); + int (*set_mdio)(struct mii_dev *miidev, int v); + int (*get_mdio)(struct mii_dev *miidev, int *v); + int (*set_mdc)(struct mii_dev *miidev, int v); + int (*delay)(struct mii_dev *miidev); }; -struct bb_miiphy_bus *bb_miiphy_alloc(void); -void bb_miiphy_free(struct bb_miiphy_bus *bus); - -int bb_miiphy_read(struct mii_dev *miidev, int addr, int devad, int reg); -int bb_miiphy_write(struct mii_dev *miidev, int addr, int devad, int reg, - u16 value); +int bb_miiphy_read(struct mii_dev *miidev, const struct bb_miiphy_bus_ops *ops, + int addr, int devad, int reg); +int bb_miiphy_write(struct mii_dev *miidev, const struct bb_miiphy_bus_ops *ops, + int addr, int devad, int reg, u16 value); #endif /* phy seed setup */ diff --git a/include/net-common.h b/include/net-common.h index 29d31f37263..1d507b13b06 100644 --- a/include/net-common.h +++ b/include/net-common.h @@ -291,6 +291,7 @@ struct eth_ops { #define eth_get_ops(dev) ((struct eth_ops *)(dev)->driver->ops) struct udevice *eth_get_dev(void); /* get the current device */ +void eth_set_dev(struct udevice *dev); /* set a device */ unsigned char *eth_get_ethaddr(void); /* get the current device MAC */ int eth_rx(void); /* Check for received packets */ void eth_halt(void); /* stop SCC */ diff --git a/include/serial.h b/include/serial.h index e5f6d984d28..0a707ca730d 100644 --- a/include/serial.h +++ b/include/serial.h @@ -48,26 +48,6 @@ extern int serial_assign(const char *name); extern void serial_reinit_all(void); int serial_initialize(void); -/* For usbtty */ -#ifdef CONFIG_USB_TTY - -struct stdio_dev; - -int usbtty_getc(struct stdio_dev *dev); -void usbtty_putc(struct stdio_dev *dev, const char c); -void usbtty_puts(struct stdio_dev *dev, const char *str); -int usbtty_tstc(struct stdio_dev *dev); - -#else - -/* stubs */ -#define usbtty_getc(dev) 0 -#define usbtty_putc(dev, a) -#define usbtty_puts(dev, a) -#define usbtty_tstc(dev) 0 - -#endif /* CONFIG_USB_TTY */ - struct udevice; enum serial_par { diff --git a/include/setjmp.h b/include/setjmp.h new file mode 100644 index 00000000000..37d3a8af85d --- /dev/null +++ b/include/setjmp.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef _SETJMP_H_ +#define _SETJMP_H_ 1 + +#ifdef CONFIG_HAVE_SETJMP +#include <asm/setjmp.h> +#else +struct jmp_buf_data { +}; +#endif + +/** + * typedef jmp_buf - information needed to restore a calling environment + */ +typedef struct jmp_buf_data jmp_buf[1]; + +/** + * setjmp() - prepare for a long jump + * + * Registers, the stack pointer, and the return address are saved in the + * jump bufffer. The function returns zero afterwards. When longjmp() is + * executed the function returns a second time with a non-zero value. + * + * @env: jump buffer used to store register values + * Return: 0 after setting up jump buffer, non-zero after longjmp() + */ +int setjmp(jmp_buf env); + +/** + * longjmp() - long jump + * + * Jump back to the address and the register state saved by setjmp(). + * + * @env: jump buffer + * @val: value to be returned by setjmp(), 0 is replaced by 1 + */ +void longjmp(jmp_buf env, int val); + +#endif /* _SETJMP_H_ */ diff --git a/include/stdio_dev.h b/include/stdio_dev.h index 4e3c4708f80..f7f9c10199e 100644 --- a/include/stdio_dev.h +++ b/include/stdio_dev.h @@ -101,7 +101,6 @@ struct stdio_dev *stdio_clone(struct stdio_dev *dev); int drv_lcd_init(void); int drv_video_init(void); int drv_keyboard_init(void); -int drv_usbtty_init(void); int drv_usbacm_init(void); int drv_nc_init(void); int drv_jtag_console_init(void); diff --git a/include/u-boot/sha1.h b/include/u-boot/sha1.h index dd66258bbe9..c2d62e9cf0f 100644 --- a/include/u-boot/sha1.h +++ b/include/u-boot/sha1.h @@ -18,17 +18,7 @@ #include <linux/types.h> #if CONFIG_IS_ENABLED(MBEDTLS_LIB_CRYPTO) -/* - * FIXME: - * MbedTLS define the members of "mbedtls_sha256_context" as private, - * but "state" needs to be access by arch/arm/cpu/armv8/sha1_ce_glue. - * MBEDTLS_ALLOW_PRIVATE_ACCESS needs to be enabled to allow the external - * access. - * Directly including <external/mbedtls/library/common.h> is not allowed, - * since this will include <malloc.h> and break the sandbox test. - */ -#define MBEDTLS_ALLOW_PRIVATE_ACCESS - +#include "mbedtls_options.h" #include <mbedtls/sha1.h> #endif diff --git a/include/u-boot/sha256.h b/include/u-boot/sha256.h index d7a3403270b..2d86508332e 100644 --- a/include/u-boot/sha256.h +++ b/include/u-boot/sha256.h @@ -7,17 +7,7 @@ #include <linux/types.h> #if CONFIG_IS_ENABLED(MBEDTLS_LIB_CRYPTO) -/* - * FIXME: - * MbedTLS define the members of "mbedtls_sha256_context" as private, - * but "state" needs to be access by arch/arm/cpu/armv8/sha256_ce_glue. - * MBEDTLS_ALLOW_PRIVATE_ACCESS needs to be enabled to allow the external - * access. - * Directly including <external/mbedtls/library/common.h> is not allowed, - * since this will include <malloc.h> and break the sandbox test. - */ -#define MBEDTLS_ALLOW_PRIVATE_ACCESS - +#include "mbedtls_options.h" #include <mbedtls/sha256.h> #endif diff --git a/include/video_bridge.h b/include/video_bridge.h index 3b429eac578..00e9804565c 100644 --- a/include/video_bridge.h +++ b/include/video_bridge.h @@ -54,6 +54,19 @@ struct video_bridge_ops { int (*set_backlight)(struct udevice *dev, int percent); /** + * get_display_timing() - Get display timings from bridge. + * + * @dev: Bridge device containing the linked display timings + * @tim: Place to put timings + * @return 0 if OK, -ve on error + * + * This call it totally optional and useful mainly for integrated + * bridges with fixed output device. + */ + int (*get_display_timing)(struct udevice *dev, + struct display_timing *timing); + + /** * read_edid() - Read information from EDID * * @dev: Device to read from @@ -67,6 +80,7 @@ struct video_bridge_ops { #define video_bridge_get_ops(dev) \ ((struct video_bridge_ops *)(dev)->driver->ops) +#if CONFIG_IS_ENABLED(VIDEO_BRIDGE) /** * video_bridge_attach() - attach a video bridge * @@ -99,6 +113,14 @@ int video_bridge_set_active(struct udevice *dev, bool active); int video_bridge_check_attached(struct udevice *dev); /** + * video_bridge_get_display_timing() - Get display timings from bridge. + * + * @dev: Bridge device containing the linked display timings + * Return: 0 if OK, -ve on error + */ +int video_bridge_get_display_timing(struct udevice *dev, + struct display_timing *timing); +/** * video_bridge_read_edid() - Read information from EDID * * @dev: Device to read from @@ -107,5 +129,37 @@ int video_bridge_check_attached(struct udevice *dev); * Return: number of bytes read, <=0 for error */ int video_bridge_read_edid(struct udevice *dev, u8 *buf, int buf_size); +#else +static inline int video_bridge_attach(struct udevice *dev) +{ + return -ENOSYS; +} + +static inline int video_bridge_set_backlight(struct udevice *dev, int percent) +{ + return -ENOSYS; +} + +static inline int video_bridge_set_active(struct udevice *dev, bool active) +{ + return -ENOSYS; +} + +static inline int video_bridge_check_attached(struct udevice *dev) +{ + return -ENOSYS; +} + +static inline int video_bridge_get_display_timing(struct udevice *dev, + struct display_timing *timing) +{ + return -ENOSYS; +} + +static inline int video_bridge_read_edid(struct udevice *dev, u8 *buf, int buf_size) +{ + return -ENOSYS; +} +#endif /* CONFIG_VIDEO_BRIDGE */ #endif |