diff options
Diffstat (limited to 'include')
112 files changed, 1290 insertions, 5210 deletions
diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index 26277b93976..789adf2c3f9 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -400,6 +400,12 @@ struct global_data { */ struct bloblist_hdr *bloblist; #endif +#if CONFIG_IS_ENABLED(HANDOFF) + /** + * @spl_handoff: SPL hand-off information + */ + struct spl_handoff *spl_handoff; +#endif #if defined(CONFIG_TRANSLATION_OFFSET) /** * @translation_offset: optional translation offset diff --git a/include/asm-generic/u-boot.h b/include/asm-generic/u-boot.h index 70303acd558..8c619c1b74a 100644 --- a/include/asm-generic/u-boot.h +++ b/include/asm-generic/u-boot.h @@ -30,8 +30,6 @@ struct bd_info { unsigned long bi_flashstart; /* start of FLASH memory */ unsigned long bi_flashsize; /* size of FLASH memory */ unsigned long bi_flashoffset; /* reserved area for startup monitor */ - unsigned long bi_sramstart; /* start of SRAM memory */ - unsigned long bi_sramsize; /* size of SRAM memory */ #ifdef CONFIG_ARM unsigned long bi_arm_freq; /* arm frequency */ unsigned long bi_dsp_freq; /* dsp core frequency */ diff --git a/include/bloblist.h b/include/bloblist.h index ff32d3fecfd..f999391f74b 100644 --- a/include/bloblist.h +++ b/include/bloblist.h @@ -357,6 +357,7 @@ int bloblist_new(ulong addr, uint size, uint flags, uint align_log2); */ int bloblist_check(ulong addr, uint size); +#if CONFIG_IS_ENABLED(BLOBLIST) /** * bloblist_finish() - Set up the bloblist for the next U-Boot part * @@ -366,6 +367,12 @@ int bloblist_check(ulong addr, uint size); * Return: 0 */ int bloblist_finish(void); +#else +static inline int bloblist_finish(void) +{ + return 0; +} +#endif /* BLOBLIST */ /** * bloblist_get_stats() - Get information about the bloblist diff --git a/include/configs/bananapi-f3.h b/include/configs/bananapi-f3.h new file mode 100644 index 00000000000..97cf4d72df0 --- /dev/null +++ b/include/configs/bananapi-f3.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com> + * + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CFG_SYS_SDRAM_BASE 0x0 +#define CFG_SYS_NS16550_IER 0x40 /* UART Unit Enable */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/capricorn-common.h b/include/configs/capricorn-common.h index 1f61b2b6af6..4d95f3fd79b 100644 --- a/include/configs/capricorn-common.h +++ b/include/configs/capricorn-common.h @@ -95,7 +95,9 @@ #define CFG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_2 0x880000000 -/* DDR3 board total DDR is 1 GB */ +/* Set default values to the smallest DDR we have in capricorn modules + * Use it in case the system controller would return an error + */ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1 GB */ #define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 GB */ diff --git a/include/configs/deneb.h b/include/configs/deneb.h deleted file mode 100644 index f155bb8bf50..00000000000 --- a/include/configs/deneb.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2019 Siemens AG - * - */ - -#ifndef __DENEB_H -#define __DENEB_H - -#include "capricorn-common.h" - -/* DDR3 board total DDR is 2 GB */ -#undef PHYS_SDRAM_1_SIZE -#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */ - -#endif /* __DENEB_H */ diff --git a/include/configs/imx8mm_data_modul_edm_sbc.h b/include/configs/imx8mm_data_modul_edm_sbc.h index d323f84ac7a..57ecb5e2190 100644 --- a/include/configs/imx8mm_data_modul_edm_sbc.h +++ b/include/configs/imx8mm_data_modul_edm_sbc.h @@ -34,7 +34,7 @@ #define CFG_SYS_FSL_ESDHC_ADDR 0 #define CFG_EXTRA_ENV_SETTINGS \ - "altbootcmd=setenv devpart 2 && run bootcmd ; reset\0" \ + "altbootcmd=run bootcmd\0" \ "bootlimit=3\0" \ "devtype=mmc\0" \ "devpart=1\0" \ diff --git a/include/configs/imx8mp_data_modul_edm_sbc.h b/include/configs/imx8mp_data_modul_edm_sbc.h index f953847ce05..de5bdd30e18 100644 --- a/include/configs/imx8mp_data_modul_edm_sbc.h +++ b/include/configs/imx8mp_data_modul_edm_sbc.h @@ -24,7 +24,7 @@ #define FEC_QUIRK_ENET_MAC #define CFG_EXTRA_ENV_SETTINGS \ - "altbootcmd=setenv devpart 2 && run bootcmd ; reset\0" \ + "altbootcmd=run bootcmd\0" \ "bootlimit=3\0" \ "devtype=mmc\0" \ "devpart=1\0" \ diff --git a/include/configs/imx91_evk.h b/include/configs/imx91_evk.h new file mode 100644 index 00000000000..9c5014fd0a5 --- /dev/null +++ b/include/configs/imx91_evk.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2024 NXP + */ + +#ifndef __IMX91_EVK_H +#define __IMX91_EVK_H + +#define CFG_SYS_UBOOT_BASE \ + (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + +#define CFG_SYS_INIT_RAM_ADDR 0x80000000 +#define CFG_SYS_INIT_RAM_SIZE 0x200000 + +#define CFG_SYS_SDRAM_BASE 0x80000000 +#define PHYS_SDRAM 0x80000000 +#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ + +#define WDOG_BASE_ADDR WDG3_BASE_ADDR + +#endif diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h index bdf12ee8f7e..85120629529 100644 --- a/include/configs/j721e_evm.h +++ b/include/configs/j721e_evm.h @@ -15,11 +15,14 @@ #define CFG_SYS_FLASH_BASE 0x000000000 /* SPL Loader Configuration */ -#if defined(CONFIG_TARGET_J721E_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM) +#if defined(CONFIG_TARGET_J721E_A72_EVM) #define CFG_SYS_UBOOT_BASE 0x50280000 -/* Image load address in RAM for DFU boot*/ -#else +#elif defined(CONFIG_TARGET_J7200_A72_EVM) +#define CFG_SYS_UBOOT_BASE 0x50300000 +#elif defined(CONFIG_TARGET_J721E_R5_EVM) #define CFG_SYS_UBOOT_BASE 0x50080000 +#else +#define CFG_SYS_UBOOT_BASE 0x50100000 #endif /** diff --git a/include/configs/khadas-vim3_android.h b/include/configs/khadas-vim3_android.h index fc89efb4c36..551ab51c881 100644 --- a/include/configs/khadas-vim3_android.h +++ b/include/configs/khadas-vim3_android.h @@ -24,7 +24,7 @@ "name=boot_a,size=64M,bootable,uuid=${uuid_gpt_boot_a};" \ "name=boot_b,size=64M,bootable,uuid=${uuid_gpt_boot_b};" \ "name=super,size=3072M,uuid=${uuid_gpt_super};" \ - "name=userdata,size=11282M,uuid=${uuid_gpt_userdata};" \ + "name=userdata,size=11218M,uuid=${uuid_gpt_userdata};" \ "name=rootfs,size=-,uuid=" ROOT_UUID #else #define PARTS_DEFAULT \ @@ -37,14 +37,31 @@ "name=recovery,size=64M,uuid=${uuid_gpt_recovery};" \ "name=cache,size=256M,uuid=${uuid_gpt_cache};" \ "name=super,size=1792M,uuid=${uuid_gpt_super};" \ - "name=userdata,size=12786M,uuid=${uuid_gpt_userdata};" \ + "name=userdata,size=12722M,uuid=${uuid_gpt_userdata};" \ "name=rootfs,size=-,uuid=" ROOT_UUID #endif -#define EXTRA_ANDROID_ENV_SETTINGS \ - "board=vim3\0" \ - "board_name=vim3\0" \ +#define CFG_EXTRA_ENV_SETTINGS \ + "board=vim3\0" \ + "board_name=vim3\0" \ + "bootmeths=android\0" \ + "bootcmd=bootflow scan\0" \ + "adtb_idx=3\0" \ + "partitions=" PARTS_DEFAULT "\0" \ + "mmcdev=2\0" \ + "fastboot_raw_partition_bootloader=0x1 0xfff mmcpart 1\0" \ + "fastboot_raw_partition_bootenv=0x0 0xfff mmcpart 2\0" \ + "stdin=" STDIN_CFG "\0" \ + "stdout=" STDOUT_CFG "\0" \ + "stderr=" STDOUT_CFG "\0" \ + "dtboaddr=0x08200000\0" \ + "loadaddr=0x01080000\0" \ + "fdt_addr_r=0x01000000\0" \ + "scriptaddr=0x08000000\0" \ + "kernel_addr_r=0x01080000\0" \ + "pxefile_addr_r=0x01080000\0" \ + "ramdisk_addr_r=0x13000000\0" \ -#include <configs/meson64_android.h> +#include <configs/meson64.h> #endif /* __CONFIG_H */ diff --git a/include/configs/khadas-vim3l_android.h b/include/configs/khadas-vim3l_android.h index 5b2aed1cf62..1869249e7c9 100644 --- a/include/configs/khadas-vim3l_android.h +++ b/include/configs/khadas-vim3l_android.h @@ -24,7 +24,7 @@ "name=boot_a,size=64M,bootable,uuid=${uuid_gpt_boot_a};" \ "name=boot_b,size=64M,bootable,uuid=${uuid_gpt_boot_b};" \ "name=super,size=3072M,uuid=${uuid_gpt_super};" \ - "name=userdata,size=11282M,uuid=${uuid_gpt_userdata};" \ + "name=userdata,size=11218M,uuid=${uuid_gpt_userdata};" \ "name=rootfs,size=-,uuid=" ROOT_UUID #else #define PARTS_DEFAULT \ @@ -37,14 +37,31 @@ "name=recovery,size=64M,uuid=${uuid_gpt_recovery};" \ "name=cache,size=256M,uuid=${uuid_gpt_cache};" \ "name=super,size=1792M,uuid=${uuid_gpt_super};" \ - "name=userdata,size=12786M,uuid=${uuid_gpt_userdata};" \ + "name=userdata,size=12722M,uuid=${uuid_gpt_userdata};" \ "name=rootfs,size=-,uuid=" ROOT_UUID #endif -#define EXTRA_ANDROID_ENV_SETTINGS \ - "board=vim3l\0" \ - "board_name=vim3l\0" \ +#define CFG_EXTRA_ENV_SETTINGS \ + "board=vim3l\0" \ + "board_name=vim3l\0" \ + "bootmeths=android\0" \ + "bootcmd=bootflow scan\0" \ + "adtb_idx=2\0" \ + "partitions=" PARTS_DEFAULT "\0" \ + "mmcdev=2\0" \ + "fastboot_raw_partition_bootloader=0x1 0xfff mmcpart 1\0" \ + "fastboot_raw_partition_bootenv=0x0 0xfff mmcpart 2\0" \ + "stdin=" STDIN_CFG "\0" \ + "stdout=" STDOUT_CFG "\0" \ + "stderr=" STDOUT_CFG "\0" \ + "dtboaddr=0x08200000\0" \ + "loadaddr=0x01080000\0" \ + "fdt_addr_r=0x01000000\0" \ + "scriptaddr=0x08000000\0" \ + "kernel_addr_r=0x01080000\0" \ + "pxefile_addr_r=0x01080000\0" \ + "ramdisk_addr_r=0x13000000\0" \ -#include <configs/meson64_android.h> +#include <configs/meson64.h> #endif /* __CONFIG_H */ diff --git a/include/configs/licheerv_nano.h b/include/configs/licheerv_nano.h new file mode 100644 index 00000000000..2ea7943f66f --- /dev/null +++ b/include/configs/licheerv_nano.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2024, Thomas Bonnefille <thomas.bonnefille@bootlin.com> + * + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <config_distro_bootcmd.h> + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) + +#define CFG_SYS_SDRAM_BASE 0x80000000 + +#define CFG_EXTRA_ENV_SETTINGS "consoledev=ttyS0\0" \ + "baudrate=115200\0" \ + "fdt_addr_r=0x82000000\0" \ + "kernel_addr_r=0x81000000\0" \ + "scriptaddr=0x80c00000\0" \ + BOOTENV + +#endif /* __CONFIG_H */ diff --git a/include/configs/ls1028ardb.h b/include/configs/ls1028ardb.h index d44ce45fd6b..9c869ee6840 100644 --- a/include/configs/ls1028ardb.h +++ b/include/configs/ls1028ardb.h @@ -53,6 +53,7 @@ #define CFG_EXTRA_ENV_SETTINGS \ "board=ls1028ardb\0" \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ + "fdtfile=fsl-ls1028a-rdb.dtb\0" \ "ramdisk_addr=0x800000\0" \ "ramdisk_size=0x2000000\0" \ "bootm_size=0x10000000\0" \ diff --git a/include/configs/meson64_android.h b/include/configs/meson64_android.h index 77364bbf9cf..d6ef0a83a68 100644 --- a/include/configs/meson64_android.h +++ b/include/configs/meson64_android.h @@ -104,12 +104,6 @@ "elif test $board_name = sei610; then " \ "echo \" Reading DTB for sei610...\"; " \ "setenv dtb_index 1;" \ - "elif test $board_name = vim3l; then " \ - "echo \" Reading DTB for vim3l...\"; " \ - "setenv dtb_index 2;" \ - "elif test $board_name = vim3; then " \ - "echo \" Reading DTB for vim3...\"; " \ - "setenv dtb_index 3;" \ "else " \ "echo Error: Android boot is not supported for $board_name; " \ "exit; " \ diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 6740ab2be3e..3bcc4c48dc8 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -82,7 +82,7 @@ "nor0=flash-0\0"\ "mtdparts=mtdparts=flash-0:"\ "256k(u-boot),256k(env),3m(kernel),"\ - "1m(romfs),1m(cramfs),-(jffs2)\0"\ + "1m(romfs),1m(cramfs),-(fs)\0"\ "nc=setenv stdout nc;"\ "setenv stdin nc\0" \ "serial=setenv stdout serial;"\ diff --git a/include/configs/phycore_am62ax.h b/include/configs/phycore_am62ax.h new file mode 100644 index 00000000000..661ba8f73ca --- /dev/null +++ b/include/configs/phycore_am62ax.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later OR MIT */ +/* + * Configuration header file for PHYTEC phyCORE-AM62Ax + * + * Copyright (C) 2024 PHYTEC America LLC + * Author: Garrett Giordano <ggiordano@phytec.com> + */ + +#ifndef __PHYCORE_AM62AX_H +#define __PHYCORE_AM62AX_H + +/* DDR Configuration */ +#define CFG_SYS_SDRAM_BASE 0x80000000 + +#endif /* __PHYCORE_AM62AX_H */ diff --git a/include/configs/phycore_am62x.h b/include/configs/phycore_am62x.h index 10b78b6f537..2bc6e7e16f9 100644 --- a/include/configs/phycore_am62x.h +++ b/include/configs/phycore_am62x.h @@ -12,4 +12,8 @@ /* DDR Configuration */ #define CFG_SYS_SDRAM_BASE 0x80000000 +#define PHYCORE_AM6XX_FW_NAME_TIBOOT3 u"PHYCORE_AM62X_TIBOOT3" +#define PHYCORE_AM6XX_FW_NAME_SPL u"PHYCORE_AM62X_SPL" +#define PHYCORE_AM6XX_FW_NAME_UBOOT u"PHYCORE_AM62X_UBOOT" + #endif /* __PHYCORE_AM62X_H */ diff --git a/include/configs/phycore_am64x.h b/include/configs/phycore_am64x.h index 9377db30a91..dd3dfa94270 100644 --- a/include/configs/phycore_am64x.h +++ b/include/configs/phycore_am64x.h @@ -12,4 +12,8 @@ /* DDR Configuration */ #define CFG_SYS_SDRAM_BASE 0x80000000 +#define PHYCORE_AM6XX_FW_NAME_TIBOOT3 u"PHYCORE_AM64X_TIBOOT3" +#define PHYCORE_AM6XX_FW_NAME_SPL u"PHYCORE_AM64X_SPL" +#define PHYCORE_AM6XX_FW_NAME_UBOOT u"PHYCORE_AM64X_UBOOT" + #endif /* __PHYCORE_AM64X_H */ diff --git a/include/configs/phycore_imx8mm.h b/include/configs/phycore_imx8mm.h index e74a3f184c6..20e2ab832ee 100644 --- a/include/configs/phycore_imx8mm.h +++ b/include/configs/phycore_imx8mm.h @@ -20,52 +20,6 @@ /* For RAW image gives a error info not panic */ #endif -#define CFG_EXTRA_ENV_SETTINGS \ - "image=Image\0" \ - "console=ttymxc2,115200\0" \ - "fdt_addr=0x48000000\0" \ - "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "ip_dyn=yes\0" \ - "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ - "mmcpart=1\0" \ - "mmcroot=2\0" \ - "update_offset=0x42\0" \ - "update_filename=flash.bin\0" \ - "update_bootimg=" \ - "mmc dev ${mmcdev} ; " \ - "if dhcp ${loadaddr} ${update_filepath}/${update_filename} ; then " \ - "setexpr fw_sz ${filesize} / 0x200 ; " /* SD block size */ \ - "mmc write ${loadaddr} ${update_offset} ${fw_sz} ; " \ - "fi\0" \ - "mmcautodetect=yes\0" \ - "mmcargs=setenv bootargs console=${console} " \ - "root=/dev/mmcblk${mmcdev}p${mmcroot} rootwait rw\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "if run loadfdt; then " \ - "booti ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi;\0 " \ - "nfsroot=/nfs\0" \ - "netargs=setenv bootargs console=${console} root=/dev/nfs ip=dhcp " \ - "nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${loadaddr} ${image}; " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "booti ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi;\0" \ - /* Link Definitions */ #define CFG_SYS_INIT_RAM_ADDR 0x40000000 diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h index 0ae4fc55a97..8de930eab54 100644 --- a/include/configs/pic32mzdask.h +++ b/include/configs/pic32mzdask.h @@ -19,8 +19,11 @@ */ /* Initial RAM for temporary stack, global data */ #define CFG_SYS_INIT_RAM_SIZE 0x10000 +#define CFG_SYS_SRAM_BASE 0x80000000 +#define CFG_SYS_SRAM_SIZE 0x00080000 + #define CFG_SYS_INIT_RAM_ADDR \ - (CONFIG_SYS_SRAM_BASE + CONFIG_SYS_SRAM_SIZE - CFG_SYS_INIT_RAM_SIZE) + (CFG_SYS_SRAM_BASE + CFG_SYS_SRAM_SIZE - CFG_SYS_INIT_RAM_SIZE) /* SDRAM Configuration (for final code, data, stack, heap) */ #define CFG_SYS_SDRAM_BASE 0x88000000 diff --git a/include/configs/qcom.h b/include/configs/qcom.h index 5b5ebbd844d..9b41ab9e982 100644 --- a/include/configs/qcom.h +++ b/include/configs/qcom.h @@ -11,4 +11,9 @@ #define CFG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 } +// 2a5aa852-b856-4d97-baa9-5c5f4421551f +#define QUALCOMM_UBOOT_BOOT_IMAGE_GUID \ + EFI_GUID(0x2a5aa852, 0xb856, 0x4d97, 0xba, 0xa9, \ + 0x5c, 0x5f, 0x44, 0x21, 0x55, 0x1f) + #endif diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h index 67c9faeca57..020e79ca2a8 100644 --- a/include/configs/rcar-gen2-common.h +++ b/include/configs/rcar-gen2-common.h @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* * include/configs/rcar-gen2-common.h + * This file is R-Car Gen2 common configuration file. * - * Copyright (C) 2013,2014 Renesas Electronics Corporation + * Copyright (C) 2013-2024 Renesas Electronics Corporation */ #ifndef __RCAR_GEN2_COMMON_H @@ -10,14 +11,15 @@ #include <asm/arch/renesas.h> -/* console */ -#define CFG_SYS_BAUDRATE_TABLE { 38400, 115200 } +/* Console */ +#define CFG_SYS_BAUDRATE_TABLE { 38400, 115200 } +/* Memory */ #define CFG_SYS_SDRAM_BASE (RCAR_GEN2_SDRAM_BASE) #define CFG_SYS_SDRAM_SIZE (RCAR_GEN2_UBOOT_SDRAM_SIZE) /* Timer */ -#define CFG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */ +#define CFG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */ #define CFG_SYS_TIMER_RATE (get_board_sys_clk() / 8) #endif /* __RCAR_GEN2_COMMON_H */ diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h index 3f0831a901c..bedb1c0843e 100644 --- a/include/configs/rcar-gen3-common.h +++ b/include/configs/rcar-gen3-common.h @@ -3,7 +3,7 @@ * include/configs/rcar-gen3-common.h * This file is R-Car Gen3 common configuration file. * - * Copyright (C) 2015-2017 Renesas Electronics Corporation + * Copyright (C) 2015-2024 Renesas Electronics Corporation */ #ifndef __RCAR_GEN3_COMMON_H @@ -11,24 +11,17 @@ #include <asm/arch/renesas.h> -/* boot option */ +/* Console */ +#define CFG_SYS_BAUDRATE_TABLE { 115200, 38400 } -/* Generic Interrupt Controller Definitions */ -#define GICD_BASE 0xF1010000 -#define GICC_BASE 0xF1020000 - -/* console */ -#define CFG_SYS_BAUDRATE_TABLE { 115200, 38400 } - -/* MEMORY */ +/* Memory */ #define DRAM_RSV_SIZE 0x08000000 #define CFG_SYS_SDRAM_BASE (0x40000000 + DRAM_RSV_SIZE) #define CFG_SYS_SDRAM_SIZE (0x80000000u - DRAM_RSV_SIZE) #define CFG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE) -/* ENV setting */ - -#define CFG_EXTRA_ENV_SETTINGS \ +/* Environment setting */ +#define CFG_EXTRA_ENV_SETTINGS \ "bootm_size=0x10000000\0" #endif /* __RCAR_GEN3_COMMON_H */ diff --git a/include/configs/rcar-gen4-common.h b/include/configs/rcar-gen4-common.h index 37a37c013df..1a00adb79d1 100644 --- a/include/configs/rcar-gen4-common.h +++ b/include/configs/rcar-gen4-common.h @@ -3,7 +3,7 @@ * include/configs/rcar-gen4-common.h * This file is R-Car Gen4 common configuration file. * - * Copyright (C) 2021 Renesas Electronics Corporation + * Copyright (C) 2021-2024 Renesas Electronics Corporation */ #ifndef __RCAR_GEN4_COMMON_H @@ -12,7 +12,7 @@ #include <asm/arch/renesas.h> /* Console */ -#define CFG_SYS_BAUDRATE_TABLE { 38400, 115200, 921600, 1843200 } +#define CFG_SYS_BAUDRATE_TABLE { 38400, 115200, 921600, 1843200 } /* Memory */ #define DRAM_RSV_SIZE 0x08000000 @@ -20,10 +20,8 @@ #define CFG_SYS_SDRAM_SIZE (0x80000000u - DRAM_RSV_SIZE) #define CFG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE) -/* PHY needs a longer autoneg timeout */ - /* Environment setting */ -#define CFG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "bootm_size=0x10000000\0" #endif /* __RCAR_GEN4_COMMON_H */ diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h index 4e0b3c663c7..0a5f23e4c88 100644 --- a/include/configs/sheevaplug.h +++ b/include/configs/sheevaplug.h @@ -12,13 +12,4 @@ #include "mv-common.h" -/* - * Environment variables configurations - */ -#define CFG_EXTRA_ENV_SETTINGS "x_bootargs=console" \ - "=ttyS0,115200 mtdparts=" CONFIG_MTDPARTS_DEFAULT \ - "x_bootcmd_kernel=nand read 0x6400000 0x100000 0x400000\0" \ - "x_bootcmd_usb=usb start\0" \ - "x_bootargs_root=root=/dev/mtdblock3 rw rootfstype=jffs2\0" - #endif /* _CONFIG_SHEEVAPLUG_H */ diff --git a/include/configs/x240.h b/include/configs/x240.h index 3601df588d5..05241f33d74 100644 --- a/include/configs/x240.h +++ b/include/configs/x240.h @@ -11,22 +11,14 @@ /* additions for new ARM relocation support */ #define CFG_SYS_SDRAM_BASE 0x200000000 -#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ - 115200, 230400, 460800, 921600 } - /* Default Env vars */ - -#define BOOT_TARGET_DEVICES(func) \ - func(USB, usb, 0) \ - func(DHCP, dhcp, na) - -#include <config_distro_bootcmd.h> +#define BOOT_TARGETS "usb dhcp" #define CFG_EXTRA_ENV_SETTINGS \ - BOOTENV \ "kernel_addr_r=0x202000000\0" \ "fdt_addr_r=0x201000000\0" \ "ramdisk_addr_r=0x206000000\0" \ + "boot_targets=" BOOT_TARGETS "\0" \ "fdtfile=marvell/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" /* diff --git a/include/configs/x250.h b/include/configs/x250.h new file mode 100644 index 00000000000..39f523fa6c4 --- /dev/null +++ b/include/configs/x250.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2024 Allied Telesis + */ + +#ifndef __X250_H_ +#define __X250_H_ + +/* + * High Level Configuration Options (easy to change) + */ +#define CFG_SYS_TCLK 250000000 /* 250MHz */ + +/* additions for new ARM relocation support */ +#define CFG_SYS_SDRAM_BASE 0x00000000 + +#define BOOT_TARGETS "usb scsi pxe dhcp" + +#define CFG_EXTRA_ENV_SETTINGS \ + "scriptaddr=0x6d00000\0" \ + "pxefile_addr_r=0x6e00000\0" \ + "fdt_addr_r=0x6f00000\0" \ + "kernel_addr_r=0x7000000\0" \ + "ramdisk_addr_r=0xa000000\0" \ + "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ + "boot_targets=" BOOT_TARGETS "\0" + +#endif /* __X250_H_ */ diff --git a/include/configs/x530.h b/include/configs/x530.h index 982b1292873..c7bfd1de17c 100644 --- a/include/configs/x530.h +++ b/include/configs/x530.h @@ -18,30 +18,14 @@ #define CFG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE #endif -/* - * Serial Port configuration - * The following definitions let you select what serial you want to use - * for your console driver. - */ - /* NAND */ #define BBT_CUSTOM_SCAN #define BBT_CUSTOM_SCAN_PAGE 0 #define BBT_CUSTOM_SCAN_POSITION 2048 -/* SPI NOR flash default params, used by sf commands */ - #define MTDPARTS_MTDOOPS "errlog" -/* Partition support */ - -/* Additional FS support/configuration */ - -/* Environment in SPI NOR flash */ - -/* NAND */ - #include <asm/arch/config.h> /* Keep device tree and initrd in low memory so the kernel can access them */ diff --git a/include/dfu.h b/include/dfu.h index e25588c33cb..12f9dfcdfcd 100644 --- a/include/dfu.h +++ b/include/dfu.h @@ -24,6 +24,7 @@ enum dfu_device_type { DFU_DEV_SF, DFU_DEV_MTD, DFU_DEV_VIRT, + DFU_DEV_SCSI, }; enum dfu_layout { @@ -99,6 +100,19 @@ struct virt_internal_data { int dev_num; }; +struct scsi_internal_data { + int lun; + + /* RAW programming */ + unsigned int lba_start; + unsigned int lba_size; + unsigned int lba_blk_size; + + /* FAT/EXT */ + unsigned int dev; // Always 0??? + unsigned int part; +}; + #if defined(CONFIG_DFU_NAME_MAX_SIZE) #define DFU_NAME_SIZE CONFIG_DFU_NAME_MAX_SIZE #else @@ -126,6 +140,7 @@ struct dfu_entity { struct ram_internal_data ram; struct sf_internal_data sf; struct virt_internal_data virt; + struct scsi_internal_data scsi; } data; int (*get_medium_size)(struct dfu_entity *dfu, u64 *size); @@ -516,6 +531,18 @@ static inline int dfu_fill_entity_virt(struct dfu_entity *dfu, char *devstr, } #endif +#if CONFIG_IS_ENABLED(DFU_SCSI) +int dfu_fill_entity_scsi(struct dfu_entity *dfu, char *devstr, + char **argv, int argc); +#else +static inline int dfu_fill_entity_scsi(struct dfu_entity *dfu, char *devstr, + char **argv, int argc) +{ + puts("SCSI support not available!\n"); + return -1; +} +#endif + extern bool dfu_reinit_needed; extern bool dfu_alt_info_changed; diff --git a/include/dm/of_access.h b/include/dm/of_access.h index de740d44674..44143a5a391 100644 --- a/include/dm/of_access.h +++ b/include/dm/of_access.h @@ -454,6 +454,92 @@ static inline int of_property_count_strings(const struct device_node *np, } /** + * of_root_parse_phandle - Resolve a phandle property to a device_node pointer + * from a root node + * @root: Pointer to root device tree node (default root node if NULL) + * @np: Pointer to device node holding phandle property + * @phandle_name: Name of property holding a phandle value + * @index: For properties holding a table of phandles, this is the index into + * the table + * + * Return: + * the device_node pointer with refcount incremented. Use + * of_node_put() on it when done. + */ +struct device_node *of_root_parse_phandle(struct device_node *root, + const struct device_node *np, + const char *phandle_name, int index); + +/** + * of_root_parse_phandle_with_args() - Find a node pointed by phandle in a list + * from a root node + * + * @root: pointer to root device tree node (default root node if NULL) + * @np: pointer to a device tree node containing a list + * @list_name: property name that contains a list + * @cells_name: property name that specifies phandles' arguments count + * @cells_count: Cell count to use if @cells_name is NULL + * @index: index of a phandle to parse out + * @out_args: optional pointer to output arguments structure (will be filled) + * Return: + * 0 on success (with @out_args filled out if not NULL), -ENOENT if + * @list_name does not exist, -EINVAL if a phandle was not found, + * @cells_name could not be found, the arguments were truncated or there + * were too many arguments. + * + * This function is useful to parse lists of phandles and their arguments. + * Returns 0 on success and fills out_args, on error returns appropriate + * errno value. + * + * Caller is responsible to call of_node_put() on the returned out_args->np + * pointer. + * + * Example: + * + * .. code-block:: + * + * phandle1: node1 { + * #list-cells = <2>; + * }; + * phandle2: node2 { + * #list-cells = <1>; + * }; + * node3 { + * list = <&phandle1 1 2 &phandle2 3>; + * }; + * + * To get a device_node of the `node2' node you may call this: + * of_root_parse_phandle_with_args(node3, "list", "#list-cells", 1, &args); + */ +int of_root_parse_phandle_with_args(struct device_node *root, + const struct device_node *np, + const char *list_name, const char *cells_name, + int cells_count, int index, + struct of_phandle_args *out_args); + +/** + * of_root_count_phandle_with_args() - Count the number of phandle in a list + * from a root node + * + * @root: pointer to root device tree node (default root node if NULL) + * @np: pointer to a device tree node containing a list + * @list_name: property name that contains a list + * @cells_name: property name that specifies phandles' arguments count + * @cells_count: Cell count to use if @cells_name is NULL + * Return: + * number of phandle found, -ENOENT if @list_name does not exist, + * -EINVAL if a phandle was not found, @cells_name could not be found, + * the arguments were truncated or there were too many arguments. + * + * Returns number of phandle found on success, on error returns appropriate + * errno value. + */ +int of_root_count_phandle_with_args(struct device_node *root, + const struct device_node *np, + const char *list_name, const char *cells_name, + int cells_count); + +/** * of_parse_phandle - Resolve a phandle property to a device_node pointer * @np: Pointer to device node holding phandle property * @phandle_name: Name of property holding a phandle value diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h index 0787758926f..890f0e6cf40 100644 --- a/include/dm/ofnode.h +++ b/include/dm/ofnode.h @@ -848,6 +848,18 @@ int ofnode_read_string_list(ofnode node, const char *property, const char ***listp); /** + * ofnode_parse_phandle() - Resolve a phandle property to an ofnode + * + * @node: node to check + * @phandle_name: Name of property holding a phandle value + * @index: For properties holding a table of phandles, this is the index into + * the table + * Return: ofnode that the phandle points to or ofnode_null() on error. + */ +ofnode ofnode_parse_phandle(ofnode node, const char *phandle_name, + int index); + +/** * ofnode_parse_phandle_with_args() - Find a node pointed by phandle in a list * * This function is useful to parse lists of phandles and their arguments. @@ -910,6 +922,86 @@ int ofnode_count_phandle_with_args(ofnode node, const char *list_name, const char *cells_name, int cell_count); /** + * oftree_parse_phandle() - Resolve a phandle property to an ofnode + * from a root node + * + * @tree: device tree to use + * @node: node to check + * @phandle_name: Name of property holding a phandle value + * @index: For properties holding a table of phandles, this is the index into + * the table + * Return: ofnode that the phandle points to or ofnode_null() on error. + */ +ofnode oftree_parse_phandle(oftree tree, ofnode node, const char *phandle_name, + int index); + +/** + * oftree_parse_phandle_with_args() - Find a node pointed by phandle in a list + * from a root node + * + * This function is useful to parse lists of phandles and their arguments. + * Returns 0 on success and fills out_args, on error returns appropriate + * errno value. + * + * Caller is responsible to call of_node_put() on the returned out_args->np + * pointer. + * + * Example: + * + * .. code-block:: + * + * phandle1: node1 { + * #list-cells = <2>; + * }; + * phandle2: node2 { + * #list-cells = <1>; + * }; + * node3 { + * list = <&phandle1 1 2 &phandle2 3>; + * }; + * + * To get a device_node of the `node2' node you may call this: + * oftree_parse_phandle_with_args(node3, "list", "#list-cells", 0, 1, &args); + * + * @tree: device tree to use + * @node: device tree node containing a list + * @list_name: property name that contains a list + * @cells_name: property name that specifies phandles' arguments count + * @cell_count: Cell count to use if @cells_name is NULL + * @index: index of a phandle to parse out + * @out_args: optional pointer to output arguments structure (will be filled) + * Return: + * 0 on success (with @out_args filled out if not NULL), -ENOENT if + * @list_name does not exist, -EINVAL if a phandle was not found, + * @cells_name could not be found, the arguments were truncated or there + * were too many arguments. + */ +int oftree_parse_phandle_with_args(oftree tree, ofnode node, const char *list_name, + const char *cells_name, int cell_count, + int index, + struct ofnode_phandle_args *out_args); + +/** + * oftree_count_phandle_with_args() - Count number of phandle in a list + * from a root node + * + * This function is useful to count phandles into a list. + * Returns number of phandle on success, on error returns appropriate + * errno value. + * + * @tree: device tree to use + * @node: device tree node containing a list + * @list_name: property name that contains a list + * @cells_name: property name that specifies phandles' arguments count + * @cell_count: Cell count to use if @cells_name is NULL + * Return: + * number of phandle on success, -ENOENT if @list_name does not exist, + * -EINVAL if a phandle was not found, @cells_name could not be found. + */ +int oftree_count_phandle_with_args(oftree tree, ofnode node, const char *list_name, + const char *cells_name, int cell_count); + +/** * ofnode_path() - find a node by full path * * This uses the control FDT. @@ -1629,6 +1721,21 @@ int ofnode_options_read_int(const char *prop_name, int default_val); const char *ofnode_options_read_str(const char *prop_name); /** + * ofnode_options_get_by_phandle() - Get a ofnode from phandle from the U-Boot options + * + * This reads a property from the /options/u-boot/ node of the devicetree. + * + * This only works with the control FDT. + * + * See dtschema/schemas/options/u-boot.yaml in dt-schema project for bindings + * + * @prop_name: property name to look up + * @nodep: pointer to ofnode where node is stored + * Return: 0, if found, or negative error if not + */ +int ofnode_options_get_by_phandle(const char *prop_name, ofnode *nodep); + +/** * ofnode_read_bootscript_address() - Read bootscr-address or bootscr-ram-offset * * @bootscr_address: pointer to 64bit address where bootscr-address property value diff --git a/include/dm/root.h b/include/dm/root.h index b2f30a842f5..5651b868c8b 100644 --- a/include/dm/root.h +++ b/include/dm/root.h @@ -167,8 +167,18 @@ int dm_uninit(void); * Return: 0 if OK, -ve on error */ int dm_remove_devices_flags(uint flags); + +/** + * dm_remove_devices_active - Call remove function of all active drivers heeding + * device dependencies as far as know, i.e. removing + * devices marked with DM_FLAG_VITAL last. + * + * All active devices will be removed + */ +void dm_remove_devices_active(void); #else static inline int dm_remove_devices_flags(uint flags) { return 0; } +static inline void dm_remove_devices_active(void) { } #endif /** diff --git a/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h b/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h deleted file mode 100644 index 06f198ee762..00000000000 --- a/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h +++ /dev/null @@ -1,168 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ -/* - * Copyright (c) 2019 Amlogic, Inc. All rights reserved. - * Author: Jian Hu <jian.hu@amlogic.com> - * - * Copyright (c) 2023, SberDevices. All Rights Reserved. - * Author: Dmitry Rokosov <ddrokosov@sberdevices.ru> - */ - -#ifndef __A1_PERIPHERALS_CLKC_H -#define __A1_PERIPHERALS_CLKC_H - -#define CLKID_XTAL_IN 0 -#define CLKID_FIXPLL_IN 1 -#define CLKID_USB_PHY_IN 2 -#define CLKID_USB_CTRL_IN 3 -#define CLKID_HIFIPLL_IN 4 -#define CLKID_SYSPLL_IN 5 -#define CLKID_DDS_IN 6 -#define CLKID_SYS 7 -#define CLKID_CLKTREE 8 -#define CLKID_RESET_CTRL 9 -#define CLKID_ANALOG_CTRL 10 -#define CLKID_PWR_CTRL 11 -#define CLKID_PAD_CTRL 12 -#define CLKID_SYS_CTRL 13 -#define CLKID_TEMP_SENSOR 14 -#define CLKID_AM2AXI_DIV 15 -#define CLKID_SPICC_B 16 -#define CLKID_SPICC_A 17 -#define CLKID_MSR 18 -#define CLKID_AUDIO 19 -#define CLKID_JTAG_CTRL 20 -#define CLKID_SARADC_EN 21 -#define CLKID_PWM_EF 22 -#define CLKID_PWM_CD 23 -#define CLKID_PWM_AB 24 -#define CLKID_CEC 25 -#define CLKID_I2C_S 26 -#define CLKID_IR_CTRL 27 -#define CLKID_I2C_M_D 28 -#define CLKID_I2C_M_C 29 -#define CLKID_I2C_M_B 30 -#define CLKID_I2C_M_A 31 -#define CLKID_ACODEC 32 -#define CLKID_OTP 33 -#define CLKID_SD_EMMC_A 34 -#define CLKID_USB_PHY 35 -#define CLKID_USB_CTRL 36 -#define CLKID_SYS_DSPB 37 -#define CLKID_SYS_DSPA 38 -#define CLKID_DMA 39 -#define CLKID_IRQ_CTRL 40 -#define CLKID_NIC 41 -#define CLKID_GIC 42 -#define CLKID_UART_C 43 -#define CLKID_UART_B 44 -#define CLKID_UART_A 45 -#define CLKID_SYS_PSRAM 46 -#define CLKID_RSA 47 -#define CLKID_CORESIGHT 48 -#define CLKID_AM2AXI_VAD 49 -#define CLKID_AUDIO_VAD 50 -#define CLKID_AXI_DMC 51 -#define CLKID_AXI_PSRAM 52 -#define CLKID_RAMB 53 -#define CLKID_RAMA 54 -#define CLKID_AXI_SPIFC 55 -#define CLKID_AXI_NIC 56 -#define CLKID_AXI_DMA 57 -#define CLKID_CPU_CTRL 58 -#define CLKID_ROM 59 -#define CLKID_PROC_I2C 60 -#define CLKID_DSPA_SEL 61 -#define CLKID_DSPB_SEL 62 -#define CLKID_DSPA_EN 63 -#define CLKID_DSPA_EN_NIC 64 -#define CLKID_DSPB_EN 65 -#define CLKID_DSPB_EN_NIC 66 -#define CLKID_RTC 67 -#define CLKID_CECA_32K 68 -#define CLKID_CECB_32K 69 -#define CLKID_24M 70 -#define CLKID_12M 71 -#define CLKID_FCLK_DIV2_DIVN 72 -#define CLKID_GEN 73 -#define CLKID_SARADC_SEL 74 -#define CLKID_SARADC 75 -#define CLKID_PWM_A 76 -#define CLKID_PWM_B 77 -#define CLKID_PWM_C 78 -#define CLKID_PWM_D 79 -#define CLKID_PWM_E 80 -#define CLKID_PWM_F 81 -#define CLKID_SPICC 82 -#define CLKID_TS 83 -#define CLKID_SPIFC 84 -#define CLKID_USB_BUS 85 -#define CLKID_SD_EMMC 86 -#define CLKID_PSRAM 87 -#define CLKID_DMC 88 -#define CLKID_SYS_A_SEL 89 -#define CLKID_SYS_A_DIV 90 -#define CLKID_SYS_A 91 -#define CLKID_SYS_B_SEL 92 -#define CLKID_SYS_B_DIV 93 -#define CLKID_SYS_B 94 -#define CLKID_DSPA_A_SEL 95 -#define CLKID_DSPA_A_DIV 96 -#define CLKID_DSPA_A 97 -#define CLKID_DSPA_B_SEL 98 -#define CLKID_DSPA_B_DIV 99 -#define CLKID_DSPA_B 100 -#define CLKID_DSPB_A_SEL 101 -#define CLKID_DSPB_A_DIV 102 -#define CLKID_DSPB_A 103 -#define CLKID_DSPB_B_SEL 104 -#define CLKID_DSPB_B_DIV 105 -#define CLKID_DSPB_B 106 -#define CLKID_RTC_32K_IN 107 -#define CLKID_RTC_32K_DIV 108 -#define CLKID_RTC_32K_XTAL 109 -#define CLKID_RTC_32K_SEL 110 -#define CLKID_CECB_32K_IN 111 -#define CLKID_CECB_32K_DIV 112 -#define CLKID_CECB_32K_SEL_PRE 113 -#define CLKID_CECB_32K_SEL 114 -#define CLKID_CECA_32K_IN 115 -#define CLKID_CECA_32K_DIV 116 -#define CLKID_CECA_32K_SEL_PRE 117 -#define CLKID_CECA_32K_SEL 118 -#define CLKID_DIV2_PRE 119 -#define CLKID_24M_DIV2 120 -#define CLKID_GEN_SEL 121 -#define CLKID_GEN_DIV 122 -#define CLKID_SARADC_DIV 123 -#define CLKID_PWM_A_SEL 124 -#define CLKID_PWM_A_DIV 125 -#define CLKID_PWM_B_SEL 126 -#define CLKID_PWM_B_DIV 127 -#define CLKID_PWM_C_SEL 128 -#define CLKID_PWM_C_DIV 129 -#define CLKID_PWM_D_SEL 130 -#define CLKID_PWM_D_DIV 131 -#define CLKID_PWM_E_SEL 132 -#define CLKID_PWM_E_DIV 133 -#define CLKID_PWM_F_SEL 134 -#define CLKID_PWM_F_DIV 135 -#define CLKID_SPICC_SEL 136 -#define CLKID_SPICC_DIV 137 -#define CLKID_SPICC_SEL2 138 -#define CLKID_TS_DIV 139 -#define CLKID_SPIFC_SEL 140 -#define CLKID_SPIFC_DIV 141 -#define CLKID_SPIFC_SEL2 142 -#define CLKID_USB_BUS_SEL 143 -#define CLKID_USB_BUS_DIV 144 -#define CLKID_SD_EMMC_SEL 145 -#define CLKID_SD_EMMC_DIV 146 -#define CLKID_SD_EMMC_SEL2 147 -#define CLKID_PSRAM_SEL 148 -#define CLKID_PSRAM_DIV 149 -#define CLKID_PSRAM_SEL2 150 -#define CLKID_DMC_SEL 151 -#define CLKID_DMC_DIV 152 -#define CLKID_DMC_SEL2 153 - -#endif /* __A1_PERIPHERALS_CLKC_H */ diff --git a/include/dt-bindings/clock/amlogic,a1-pll-clkc.h b/include/dt-bindings/clock/amlogic,a1-pll-clkc.h deleted file mode 100644 index 2b660c0f2c9..00000000000 --- a/include/dt-bindings/clock/amlogic,a1-pll-clkc.h +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ -/* - * Copyright (c) 2019 Amlogic, Inc. All rights reserved. - * Author: Jian Hu <jian.hu@amlogic.com> - * - * Copyright (c) 2023, SberDevices. All Rights Reserved. - * Author: Dmitry Rokosov <ddrokosov@sberdevices.ru> - */ - -#ifndef __A1_PLL_CLKC_H -#define __A1_PLL_CLKC_H - -#define CLKID_FIXED_PLL_DCO 0 -#define CLKID_FIXED_PLL 1 -#define CLKID_FCLK_DIV2_DIV 2 -#define CLKID_FCLK_DIV3_DIV 3 -#define CLKID_FCLK_DIV5_DIV 4 -#define CLKID_FCLK_DIV7_DIV 5 -#define CLKID_FCLK_DIV2 6 -#define CLKID_FCLK_DIV3 7 -#define CLKID_FCLK_DIV5 8 -#define CLKID_FCLK_DIV7 9 -#define CLKID_HIFI_PLL 10 - -#endif /* __A1_PLL_CLKC_H */ diff --git a/include/dt-bindings/clock/axg-audio-clkc.h b/include/dt-bindings/clock/axg-audio-clkc.h deleted file mode 100644 index f561f5c5ef8..00000000000 --- a/include/dt-bindings/clock/axg-audio-clkc.h +++ /dev/null @@ -1,94 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ -/* - * Copyright (c) 2018 Baylibre SAS. - * Author: Jerome Brunet <jbrunet@baylibre.com> - */ - -#ifndef __AXG_AUDIO_CLKC_BINDINGS_H -#define __AXG_AUDIO_CLKC_BINDINGS_H - -#define AUD_CLKID_DDR_ARB 29 -#define AUD_CLKID_PDM 30 -#define AUD_CLKID_TDMIN_A 31 -#define AUD_CLKID_TDMIN_B 32 -#define AUD_CLKID_TDMIN_C 33 -#define AUD_CLKID_TDMIN_LB 34 -#define AUD_CLKID_TDMOUT_A 35 -#define AUD_CLKID_TDMOUT_B 36 -#define AUD_CLKID_TDMOUT_C 37 -#define AUD_CLKID_FRDDR_A 38 -#define AUD_CLKID_FRDDR_B 39 -#define AUD_CLKID_FRDDR_C 40 -#define AUD_CLKID_TODDR_A 41 -#define AUD_CLKID_TODDR_B 42 -#define AUD_CLKID_TODDR_C 43 -#define AUD_CLKID_LOOPBACK 44 -#define AUD_CLKID_SPDIFIN 45 -#define AUD_CLKID_SPDIFOUT 46 -#define AUD_CLKID_RESAMPLE 47 -#define AUD_CLKID_POWER_DETECT 48 -#define AUD_CLKID_MST_A_MCLK 49 -#define AUD_CLKID_MST_B_MCLK 50 -#define AUD_CLKID_MST_C_MCLK 51 -#define AUD_CLKID_MST_D_MCLK 52 -#define AUD_CLKID_MST_E_MCLK 53 -#define AUD_CLKID_MST_F_MCLK 54 -#define AUD_CLKID_SPDIFOUT_CLK 55 -#define AUD_CLKID_SPDIFIN_CLK 56 -#define AUD_CLKID_PDM_DCLK 57 -#define AUD_CLKID_PDM_SYSCLK 58 -#define AUD_CLKID_MST_A_SCLK 79 -#define AUD_CLKID_MST_B_SCLK 80 -#define AUD_CLKID_MST_C_SCLK 81 -#define AUD_CLKID_MST_D_SCLK 82 -#define AUD_CLKID_MST_E_SCLK 83 -#define AUD_CLKID_MST_F_SCLK 84 -#define AUD_CLKID_MST_A_LRCLK 86 -#define AUD_CLKID_MST_B_LRCLK 87 -#define AUD_CLKID_MST_C_LRCLK 88 -#define AUD_CLKID_MST_D_LRCLK 89 -#define AUD_CLKID_MST_E_LRCLK 90 -#define AUD_CLKID_MST_F_LRCLK 91 -#define AUD_CLKID_TDMIN_A_SCLK_SEL 116 -#define AUD_CLKID_TDMIN_B_SCLK_SEL 117 -#define AUD_CLKID_TDMIN_C_SCLK_SEL 118 -#define AUD_CLKID_TDMIN_LB_SCLK_SEL 119 -#define AUD_CLKID_TDMOUT_A_SCLK_SEL 120 -#define AUD_CLKID_TDMOUT_B_SCLK_SEL 121 -#define AUD_CLKID_TDMOUT_C_SCLK_SEL 122 -#define AUD_CLKID_TDMIN_A_SCLK 123 -#define AUD_CLKID_TDMIN_B_SCLK 124 -#define AUD_CLKID_TDMIN_C_SCLK 125 -#define AUD_CLKID_TDMIN_LB_SCLK 126 -#define AUD_CLKID_TDMOUT_A_SCLK 127 -#define AUD_CLKID_TDMOUT_B_SCLK 128 -#define AUD_CLKID_TDMOUT_C_SCLK 129 -#define AUD_CLKID_TDMIN_A_LRCLK 130 -#define AUD_CLKID_TDMIN_B_LRCLK 131 -#define AUD_CLKID_TDMIN_C_LRCLK 132 -#define AUD_CLKID_TDMIN_LB_LRCLK 133 -#define AUD_CLKID_TDMOUT_A_LRCLK 134 -#define AUD_CLKID_TDMOUT_B_LRCLK 135 -#define AUD_CLKID_TDMOUT_C_LRCLK 136 -#define AUD_CLKID_SPDIFOUT_B 151 -#define AUD_CLKID_SPDIFOUT_B_CLK 152 -#define AUD_CLKID_TDM_MCLK_PAD0 155 -#define AUD_CLKID_TDM_MCLK_PAD1 156 -#define AUD_CLKID_TDM_LRCLK_PAD0 157 -#define AUD_CLKID_TDM_LRCLK_PAD1 158 -#define AUD_CLKID_TDM_LRCLK_PAD2 159 -#define AUD_CLKID_TDM_SCLK_PAD0 160 -#define AUD_CLKID_TDM_SCLK_PAD1 161 -#define AUD_CLKID_TDM_SCLK_PAD2 162 -#define AUD_CLKID_TOP 163 -#define AUD_CLKID_TORAM 164 -#define AUD_CLKID_EQDRC 165 -#define AUD_CLKID_RESAMPLE_B 166 -#define AUD_CLKID_TOVAD 167 -#define AUD_CLKID_LOCKER 168 -#define AUD_CLKID_SPDIFIN_LB 169 -#define AUD_CLKID_FRDDR_D 170 -#define AUD_CLKID_TODDR_D 171 -#define AUD_CLKID_LOOPBACK_B 172 - -#endif /* __AXG_AUDIO_CLKC_BINDINGS_H */ diff --git a/include/dt-bindings/clock/axg-clkc.h b/include/dt-bindings/clock/axg-clkc.h deleted file mode 100644 index 93752ea107e..00000000000 --- a/include/dt-bindings/clock/axg-clkc.h +++ /dev/null @@ -1,100 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * Meson-AXG clock tree IDs - * - * Copyright (c) 2017 Amlogic, Inc. All rights reserved. - */ - -#ifndef __AXG_CLKC_H -#define __AXG_CLKC_H - -#define CLKID_SYS_PLL 0 -#define CLKID_FIXED_PLL 1 -#define CLKID_FCLK_DIV2 2 -#define CLKID_FCLK_DIV3 3 -#define CLKID_FCLK_DIV4 4 -#define CLKID_FCLK_DIV5 5 -#define CLKID_FCLK_DIV7 6 -#define CLKID_GP0_PLL 7 -#define CLKID_CLK81 10 -#define CLKID_MPLL0 11 -#define CLKID_MPLL1 12 -#define CLKID_MPLL2 13 -#define CLKID_MPLL3 14 -#define CLKID_DDR 15 -#define CLKID_AUDIO_LOCKER 16 -#define CLKID_MIPI_DSI_HOST 17 -#define CLKID_ISA 18 -#define CLKID_PL301 19 -#define CLKID_PERIPHS 20 -#define CLKID_SPICC0 21 -#define CLKID_I2C 22 -#define CLKID_RNG0 23 -#define CLKID_UART0 24 -#define CLKID_MIPI_DSI_PHY 25 -#define CLKID_SPICC1 26 -#define CLKID_PCIE_A 27 -#define CLKID_PCIE_B 28 -#define CLKID_HIU_IFACE 29 -#define CLKID_ASSIST_MISC 30 -#define CLKID_SD_EMMC_B 31 -#define CLKID_SD_EMMC_C 32 -#define CLKID_DMA 33 -#define CLKID_SPI 34 -#define CLKID_AUDIO 35 -#define CLKID_ETH 36 -#define CLKID_UART1 37 -#define CLKID_G2D 38 -#define CLKID_USB0 39 -#define CLKID_USB1 40 -#define CLKID_RESET 41 -#define CLKID_USB 42 -#define CLKID_AHB_ARB0 43 -#define CLKID_EFUSE 44 -#define CLKID_BOOT_ROM 45 -#define CLKID_AHB_DATA_BUS 46 -#define CLKID_AHB_CTRL_BUS 47 -#define CLKID_USB1_DDR_BRIDGE 48 -#define CLKID_USB0_DDR_BRIDGE 49 -#define CLKID_MMC_PCLK 50 -#define CLKID_VPU_INTR 51 -#define CLKID_SEC_AHB_AHB3_BRIDGE 52 -#define CLKID_GIC 53 -#define CLKID_AO_MEDIA_CPU 54 -#define CLKID_AO_AHB_SRAM 55 -#define CLKID_AO_AHB_BUS 56 -#define CLKID_AO_IFACE 57 -#define CLKID_AO_I2C 58 -#define CLKID_SD_EMMC_B_CLK0 59 -#define CLKID_SD_EMMC_C_CLK0 60 -#define CLKID_HIFI_PLL 69 -#define CLKID_PCIE_CML_EN0 79 -#define CLKID_PCIE_CML_EN1 80 -#define CLKID_GEN_CLK 84 -#define CLKID_VPU_0_SEL 92 -#define CLKID_VPU_0 93 -#define CLKID_VPU_1_SEL 95 -#define CLKID_VPU_1 96 -#define CLKID_VPU 97 -#define CLKID_VAPB_0_SEL 99 -#define CLKID_VAPB_0 100 -#define CLKID_VAPB_1_SEL 102 -#define CLKID_VAPB_1 103 -#define CLKID_VAPB_SEL 104 -#define CLKID_VAPB 105 -#define CLKID_VCLK 106 -#define CLKID_VCLK2 107 -#define CLKID_VCLK_DIV1 122 -#define CLKID_VCLK_DIV2 123 -#define CLKID_VCLK_DIV4 124 -#define CLKID_VCLK_DIV6 125 -#define CLKID_VCLK_DIV12 126 -#define CLKID_VCLK2_DIV1 127 -#define CLKID_VCLK2_DIV2 128 -#define CLKID_VCLK2_DIV4 129 -#define CLKID_VCLK2_DIV6 130 -#define CLKID_VCLK2_DIV12 131 -#define CLKID_CTS_ENCL 133 -#define CLKID_VDIN_MEAS 136 - -#endif /* __AXG_CLKC_H */ diff --git a/include/dt-bindings/clock/qcom,camcc-sdm845.h b/include/dt-bindings/clock/qcom,camcc-sdm845.h deleted file mode 100644 index 4f7a2d2320b..00000000000 --- a/include/dt-bindings/clock/qcom,camcc-sdm845.h +++ /dev/null @@ -1,116 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_SDM_CAM_CC_SDM845_H -#define _DT_BINDINGS_CLK_SDM_CAM_CC_SDM845_H - -/* CAM_CC clock registers */ -#define CAM_CC_BPS_AHB_CLK 0 -#define CAM_CC_BPS_AREG_CLK 1 -#define CAM_CC_BPS_AXI_CLK 2 -#define CAM_CC_BPS_CLK 3 -#define CAM_CC_BPS_CLK_SRC 4 -#define CAM_CC_CAMNOC_ATB_CLK 5 -#define CAM_CC_CAMNOC_AXI_CLK 6 -#define CAM_CC_CCI_CLK 7 -#define CAM_CC_CCI_CLK_SRC 8 -#define CAM_CC_CPAS_AHB_CLK 9 -#define CAM_CC_CPHY_RX_CLK_SRC 10 -#define CAM_CC_CSI0PHYTIMER_CLK 11 -#define CAM_CC_CSI0PHYTIMER_CLK_SRC 12 -#define CAM_CC_CSI1PHYTIMER_CLK 13 -#define CAM_CC_CSI1PHYTIMER_CLK_SRC 14 -#define CAM_CC_CSI2PHYTIMER_CLK 15 -#define CAM_CC_CSI2PHYTIMER_CLK_SRC 16 -#define CAM_CC_CSI3PHYTIMER_CLK 17 -#define CAM_CC_CSI3PHYTIMER_CLK_SRC 18 -#define CAM_CC_CSIPHY0_CLK 19 -#define CAM_CC_CSIPHY1_CLK 20 -#define CAM_CC_CSIPHY2_CLK 21 -#define CAM_CC_CSIPHY3_CLK 22 -#define CAM_CC_FAST_AHB_CLK_SRC 23 -#define CAM_CC_FD_CORE_CLK 24 -#define CAM_CC_FD_CORE_CLK_SRC 25 -#define CAM_CC_FD_CORE_UAR_CLK 26 -#define CAM_CC_ICP_APB_CLK 27 -#define CAM_CC_ICP_ATB_CLK 28 -#define CAM_CC_ICP_CLK 29 -#define CAM_CC_ICP_CLK_SRC 30 -#define CAM_CC_ICP_CTI_CLK 31 -#define CAM_CC_ICP_TS_CLK 32 -#define CAM_CC_IFE_0_AXI_CLK 33 -#define CAM_CC_IFE_0_CLK 34 -#define CAM_CC_IFE_0_CLK_SRC 35 -#define CAM_CC_IFE_0_CPHY_RX_CLK 36 -#define CAM_CC_IFE_0_CSID_CLK 37 -#define CAM_CC_IFE_0_CSID_CLK_SRC 38 -#define CAM_CC_IFE_0_DSP_CLK 39 -#define CAM_CC_IFE_1_AXI_CLK 40 -#define CAM_CC_IFE_1_CLK 41 -#define CAM_CC_IFE_1_CLK_SRC 42 -#define CAM_CC_IFE_1_CPHY_RX_CLK 43 -#define CAM_CC_IFE_1_CSID_CLK 44 -#define CAM_CC_IFE_1_CSID_CLK_SRC 45 -#define CAM_CC_IFE_1_DSP_CLK 46 -#define CAM_CC_IFE_LITE_CLK 47 -#define CAM_CC_IFE_LITE_CLK_SRC 48 -#define CAM_CC_IFE_LITE_CPHY_RX_CLK 49 -#define CAM_CC_IFE_LITE_CSID_CLK 50 -#define CAM_CC_IFE_LITE_CSID_CLK_SRC 51 -#define CAM_CC_IPE_0_AHB_CLK 52 -#define CAM_CC_IPE_0_AREG_CLK 53 -#define CAM_CC_IPE_0_AXI_CLK 54 -#define CAM_CC_IPE_0_CLK 55 -#define CAM_CC_IPE_0_CLK_SRC 56 -#define CAM_CC_IPE_1_AHB_CLK 57 -#define CAM_CC_IPE_1_AREG_CLK 58 -#define CAM_CC_IPE_1_AXI_CLK 59 -#define CAM_CC_IPE_1_CLK 60 -#define CAM_CC_IPE_1_CLK_SRC 61 -#define CAM_CC_JPEG_CLK 62 -#define CAM_CC_JPEG_CLK_SRC 63 -#define CAM_CC_LRME_CLK 64 -#define CAM_CC_LRME_CLK_SRC 65 -#define CAM_CC_MCLK0_CLK 66 -#define CAM_CC_MCLK0_CLK_SRC 67 -#define CAM_CC_MCLK1_CLK 68 -#define CAM_CC_MCLK1_CLK_SRC 69 -#define CAM_CC_MCLK2_CLK 70 -#define CAM_CC_MCLK2_CLK_SRC 71 -#define CAM_CC_MCLK3_CLK 72 -#define CAM_CC_MCLK3_CLK_SRC 73 -#define CAM_CC_PLL0 74 -#define CAM_CC_PLL0_OUT_EVEN 75 -#define CAM_CC_PLL1 76 -#define CAM_CC_PLL1_OUT_EVEN 77 -#define CAM_CC_PLL2 78 -#define CAM_CC_PLL2_OUT_EVEN 79 -#define CAM_CC_PLL3 80 -#define CAM_CC_PLL3_OUT_EVEN 81 -#define CAM_CC_SLOW_AHB_CLK_SRC 82 -#define CAM_CC_SOC_AHB_CLK 83 -#define CAM_CC_SYS_TMR_CLK 84 - -/* CAM_CC Resets */ -#define TITAN_CAM_CC_CCI_BCR 0 -#define TITAN_CAM_CC_CPAS_BCR 1 -#define TITAN_CAM_CC_CSI0PHY_BCR 2 -#define TITAN_CAM_CC_CSI1PHY_BCR 3 -#define TITAN_CAM_CC_CSI2PHY_BCR 4 -#define TITAN_CAM_CC_MCLK0_BCR 5 -#define TITAN_CAM_CC_MCLK1_BCR 6 -#define TITAN_CAM_CC_MCLK2_BCR 7 -#define TITAN_CAM_CC_MCLK3_BCR 8 -#define TITAN_CAM_CC_TITAN_TOP_BCR 9 - -/* CAM_CC GDSCRs */ -#define BPS_GDSC 0 -#define IPE_0_GDSC 1 -#define IPE_1_GDSC 2 -#define IFE_0_GDSC 3 -#define IFE_1_GDSC 4 -#define TITAN_TOP_GDSC 5 - -#endif diff --git a/include/dt-bindings/clock/qcom,dispcc-sdm845.h b/include/dt-bindings/clock/qcom,dispcc-sdm845.h deleted file mode 100644 index 4016fd1d5b4..00000000000 --- a/include/dt-bindings/clock/qcom,dispcc-sdm845.h +++ /dev/null @@ -1,56 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_SDM_DISP_CC_SDM845_H -#define _DT_BINDINGS_CLK_SDM_DISP_CC_SDM845_H - -/* DISP_CC clock registers */ -#define DISP_CC_MDSS_AHB_CLK 0 -#define DISP_CC_MDSS_AXI_CLK 1 -#define DISP_CC_MDSS_BYTE0_CLK 2 -#define DISP_CC_MDSS_BYTE0_CLK_SRC 3 -#define DISP_CC_MDSS_BYTE0_INTF_CLK 4 -#define DISP_CC_MDSS_BYTE1_CLK 5 -#define DISP_CC_MDSS_BYTE1_CLK_SRC 6 -#define DISP_CC_MDSS_BYTE1_INTF_CLK 7 -#define DISP_CC_MDSS_ESC0_CLK 8 -#define DISP_CC_MDSS_ESC0_CLK_SRC 9 -#define DISP_CC_MDSS_ESC1_CLK 10 -#define DISP_CC_MDSS_ESC1_CLK_SRC 11 -#define DISP_CC_MDSS_MDP_CLK 12 -#define DISP_CC_MDSS_MDP_CLK_SRC 13 -#define DISP_CC_MDSS_MDP_LUT_CLK 14 -#define DISP_CC_MDSS_PCLK0_CLK 15 -#define DISP_CC_MDSS_PCLK0_CLK_SRC 16 -#define DISP_CC_MDSS_PCLK1_CLK 17 -#define DISP_CC_MDSS_PCLK1_CLK_SRC 18 -#define DISP_CC_MDSS_ROT_CLK 19 -#define DISP_CC_MDSS_ROT_CLK_SRC 20 -#define DISP_CC_MDSS_RSCC_AHB_CLK 21 -#define DISP_CC_MDSS_RSCC_VSYNC_CLK 22 -#define DISP_CC_MDSS_VSYNC_CLK 23 -#define DISP_CC_MDSS_VSYNC_CLK_SRC 24 -#define DISP_CC_PLL0 25 -#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 26 -#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 27 -#define DISP_CC_MDSS_DP_AUX_CLK 28 -#define DISP_CC_MDSS_DP_AUX_CLK_SRC 29 -#define DISP_CC_MDSS_DP_CRYPTO_CLK 30 -#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC 31 -#define DISP_CC_MDSS_DP_LINK_CLK 32 -#define DISP_CC_MDSS_DP_LINK_CLK_SRC 33 -#define DISP_CC_MDSS_DP_LINK_INTF_CLK 34 -#define DISP_CC_MDSS_DP_PIXEL1_CLK 35 -#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC 36 -#define DISP_CC_MDSS_DP_PIXEL_CLK 37 -#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 38 - -/* DISP_CC Reset */ -#define DISP_CC_MDSS_RSCC_BCR 0 - -/* DISP_CC GDSCR */ -#define MDSS_GDSC 0 - -#endif diff --git a/include/dt-bindings/clock/qcom,gcc-msm8916.h b/include/dt-bindings/clock/qcom,gcc-msm8916.h deleted file mode 100644 index 56303440618..00000000000 --- a/include/dt-bindings/clock/qcom,gcc-msm8916.h +++ /dev/null @@ -1,179 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2015 Linaro Limited - */ - -#ifndef _DT_BINDINGS_CLK_MSM_GCC_8916_H -#define _DT_BINDINGS_CLK_MSM_GCC_8916_H - -#define GPLL0 0 -#define GPLL0_VOTE 1 -#define BIMC_PLL 2 -#define BIMC_PLL_VOTE 3 -#define GPLL1 4 -#define GPLL1_VOTE 5 -#define GPLL2 6 -#define GPLL2_VOTE 7 -#define PCNOC_BFDCD_CLK_SRC 8 -#define SYSTEM_NOC_BFDCD_CLK_SRC 9 -#define CAMSS_AHB_CLK_SRC 10 -#define APSS_AHB_CLK_SRC 11 -#define CSI0_CLK_SRC 12 -#define CSI1_CLK_SRC 13 -#define GFX3D_CLK_SRC 14 -#define VFE0_CLK_SRC 15 -#define BLSP1_QUP1_I2C_APPS_CLK_SRC 16 -#define BLSP1_QUP1_SPI_APPS_CLK_SRC 17 -#define BLSP1_QUP2_I2C_APPS_CLK_SRC 18 -#define BLSP1_QUP2_SPI_APPS_CLK_SRC 19 -#define BLSP1_QUP3_I2C_APPS_CLK_SRC 20 -#define BLSP1_QUP3_SPI_APPS_CLK_SRC 21 -#define BLSP1_QUP4_I2C_APPS_CLK_SRC 22 -#define BLSP1_QUP4_SPI_APPS_CLK_SRC 23 -#define BLSP1_QUP5_I2C_APPS_CLK_SRC 24 -#define BLSP1_QUP5_SPI_APPS_CLK_SRC 25 -#define BLSP1_QUP6_I2C_APPS_CLK_SRC 26 -#define BLSP1_QUP6_SPI_APPS_CLK_SRC 27 -#define BLSP1_UART1_APPS_CLK_SRC 28 -#define BLSP1_UART2_APPS_CLK_SRC 29 -#define CCI_CLK_SRC 30 -#define CAMSS_GP0_CLK_SRC 31 -#define CAMSS_GP1_CLK_SRC 32 -#define JPEG0_CLK_SRC 33 -#define MCLK0_CLK_SRC 34 -#define MCLK1_CLK_SRC 35 -#define CSI0PHYTIMER_CLK_SRC 36 -#define CSI1PHYTIMER_CLK_SRC 37 -#define CPP_CLK_SRC 38 -#define CRYPTO_CLK_SRC 39 -#define GP1_CLK_SRC 40 -#define GP2_CLK_SRC 41 -#define GP3_CLK_SRC 42 -#define BYTE0_CLK_SRC 43 -#define ESC0_CLK_SRC 44 -#define MDP_CLK_SRC 45 -#define PCLK0_CLK_SRC 46 -#define VSYNC_CLK_SRC 47 -#define PDM2_CLK_SRC 48 -#define SDCC1_APPS_CLK_SRC 49 -#define SDCC2_APPS_CLK_SRC 50 -#define APSS_TCU_CLK_SRC 51 -#define USB_HS_SYSTEM_CLK_SRC 52 -#define VCODEC0_CLK_SRC 53 -#define GCC_BLSP1_AHB_CLK 54 -#define GCC_BLSP1_SLEEP_CLK 55 -#define GCC_BLSP1_QUP1_I2C_APPS_CLK 56 -#define GCC_BLSP1_QUP1_SPI_APPS_CLK 57 -#define GCC_BLSP1_QUP2_I2C_APPS_CLK 58 -#define GCC_BLSP1_QUP2_SPI_APPS_CLK 59 -#define GCC_BLSP1_QUP3_I2C_APPS_CLK 60 -#define GCC_BLSP1_QUP3_SPI_APPS_CLK 61 -#define GCC_BLSP1_QUP4_I2C_APPS_CLK 62 -#define GCC_BLSP1_QUP4_SPI_APPS_CLK 63 -#define GCC_BLSP1_QUP5_I2C_APPS_CLK 64 -#define GCC_BLSP1_QUP5_SPI_APPS_CLK 65 -#define GCC_BLSP1_QUP6_I2C_APPS_CLK 66 -#define GCC_BLSP1_QUP6_SPI_APPS_CLK 67 -#define GCC_BLSP1_UART1_APPS_CLK 68 -#define GCC_BLSP1_UART2_APPS_CLK 69 -#define GCC_BOOT_ROM_AHB_CLK 70 -#define GCC_CAMSS_CCI_AHB_CLK 71 -#define GCC_CAMSS_CCI_CLK 72 -#define GCC_CAMSS_CSI0_AHB_CLK 73 -#define GCC_CAMSS_CSI0_CLK 74 -#define GCC_CAMSS_CSI0PHY_CLK 75 -#define GCC_CAMSS_CSI0PIX_CLK 76 -#define GCC_CAMSS_CSI0RDI_CLK 77 -#define GCC_CAMSS_CSI1_AHB_CLK 78 -#define GCC_CAMSS_CSI1_CLK 79 -#define GCC_CAMSS_CSI1PHY_CLK 80 -#define GCC_CAMSS_CSI1PIX_CLK 81 -#define GCC_CAMSS_CSI1RDI_CLK 82 -#define GCC_CAMSS_CSI_VFE0_CLK 83 -#define GCC_CAMSS_GP0_CLK 84 -#define GCC_CAMSS_GP1_CLK 85 -#define GCC_CAMSS_ISPIF_AHB_CLK 86 -#define GCC_CAMSS_JPEG0_CLK 87 -#define GCC_CAMSS_JPEG_AHB_CLK 88 -#define GCC_CAMSS_JPEG_AXI_CLK 89 -#define GCC_CAMSS_MCLK0_CLK 90 -#define GCC_CAMSS_MCLK1_CLK 91 -#define GCC_CAMSS_MICRO_AHB_CLK 92 -#define GCC_CAMSS_CSI0PHYTIMER_CLK 93 -#define GCC_CAMSS_CSI1PHYTIMER_CLK 94 -#define GCC_CAMSS_AHB_CLK 95 -#define GCC_CAMSS_TOP_AHB_CLK 96 -#define GCC_CAMSS_CPP_AHB_CLK 97 -#define GCC_CAMSS_CPP_CLK 98 -#define GCC_CAMSS_VFE0_CLK 99 -#define GCC_CAMSS_VFE_AHB_CLK 100 -#define GCC_CAMSS_VFE_AXI_CLK 101 -#define GCC_CRYPTO_AHB_CLK 102 -#define GCC_CRYPTO_AXI_CLK 103 -#define GCC_CRYPTO_CLK 104 -#define GCC_OXILI_GMEM_CLK 105 -#define GCC_GP1_CLK 106 -#define GCC_GP2_CLK 107 -#define GCC_GP3_CLK 108 -#define GCC_MDSS_AHB_CLK 109 -#define GCC_MDSS_AXI_CLK 110 -#define GCC_MDSS_BYTE0_CLK 111 -#define GCC_MDSS_ESC0_CLK 112 -#define GCC_MDSS_MDP_CLK 113 -#define GCC_MDSS_PCLK0_CLK 114 -#define GCC_MDSS_VSYNC_CLK 115 -#define GCC_MSS_CFG_AHB_CLK 116 -#define GCC_OXILI_AHB_CLK 117 -#define GCC_OXILI_GFX3D_CLK 118 -#define GCC_PDM2_CLK 119 -#define GCC_PDM_AHB_CLK 120 -#define GCC_PRNG_AHB_CLK 121 -#define GCC_SDCC1_AHB_CLK 122 -#define GCC_SDCC1_APPS_CLK 123 -#define GCC_SDCC2_AHB_CLK 124 -#define GCC_SDCC2_APPS_CLK 125 -#define GCC_GTCU_AHB_CLK 126 -#define GCC_JPEG_TBU_CLK 127 -#define GCC_MDP_TBU_CLK 128 -#define GCC_SMMU_CFG_CLK 129 -#define GCC_VENUS_TBU_CLK 130 -#define GCC_VFE_TBU_CLK 131 -#define GCC_USB2A_PHY_SLEEP_CLK 132 -#define GCC_USB_HS_AHB_CLK 133 -#define GCC_USB_HS_SYSTEM_CLK 134 -#define GCC_VENUS0_AHB_CLK 135 -#define GCC_VENUS0_AXI_CLK 136 -#define GCC_VENUS0_VCODEC0_CLK 137 -#define BIMC_DDR_CLK_SRC 138 -#define GCC_APSS_TCU_CLK 139 -#define GCC_GFX_TCU_CLK 140 -#define BIMC_GPU_CLK_SRC 141 -#define GCC_BIMC_GFX_CLK 142 -#define GCC_BIMC_GPU_CLK 143 -#define ULTAUDIO_LPAIF_PRI_I2S_CLK_SRC 144 -#define ULTAUDIO_LPAIF_SEC_I2S_CLK_SRC 145 -#define ULTAUDIO_LPAIF_AUX_I2S_CLK_SRC 146 -#define ULTAUDIO_XO_CLK_SRC 147 -#define ULTAUDIO_AHBFABRIC_CLK_SRC 148 -#define CODEC_DIGCODEC_CLK_SRC 149 -#define GCC_ULTAUDIO_PCNOC_MPORT_CLK 150 -#define GCC_ULTAUDIO_PCNOC_SWAY_CLK 151 -#define GCC_ULTAUDIO_AVSYNC_XO_CLK 152 -#define GCC_ULTAUDIO_STC_XO_CLK 153 -#define GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK 154 -#define GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CLK 155 -#define GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK 156 -#define GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK 157 -#define GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK 158 -#define GCC_CODEC_DIGCODEC_CLK 159 -#define GCC_MSS_Q6_BIMC_AXI_CLK 160 - -/* Indexes for GDSCs */ -#define BIMC_GDSC 0 -#define VENUS_GDSC 1 -#define MDSS_GDSC 2 -#define JPEG_GDSC 3 -#define VFE_GDSC 4 -#define OXILI_GDSC 5 - -#endif diff --git a/include/dt-bindings/clock/qcom,gcc-msm8996.h b/include/dt-bindings/clock/qcom,gcc-msm8996.h deleted file mode 100644 index de5c36c7800..00000000000 --- a/include/dt-bindings/clock/qcom,gcc-msm8996.h +++ /dev/null @@ -1,361 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2015, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_MSM_GCC_8996_H -#define _DT_BINDINGS_CLK_MSM_GCC_8996_H - -#define GPLL0_EARLY 0 -#define GPLL0 1 -#define GPLL1_EARLY 2 -#define GPLL1 3 -#define GPLL2_EARLY 4 -#define GPLL2 5 -#define GPLL3_EARLY 6 -#define GPLL3 7 -#define GPLL4_EARLY 8 -#define GPLL4 9 -#define SYSTEM_NOC_CLK_SRC 10 -/* U-Boot: KConfig check in CI erroneously picks this up, it's unused - * anyway so comment it out for now - */ -//#define CONFIG _NOC_CLK_SRC 11 -#define PERIPH_NOC_CLK_SRC 12 -#define MMSS_BIMC_GFX_CLK_SRC 13 -#define USB30_MASTER_CLK_SRC 14 -#define USB30_MOCK_UTMI_CLK_SRC 15 -#define USB3_PHY_AUX_CLK_SRC 16 -#define USB20_MASTER_CLK_SRC 17 -#define USB20_MOCK_UTMI_CLK_SRC 18 -#define SDCC1_APPS_CLK_SRC 19 -#define SDCC1_ICE_CORE_CLK_SRC 20 -#define SDCC2_APPS_CLK_SRC 21 -#define SDCC3_APPS_CLK_SRC 22 -#define SDCC4_APPS_CLK_SRC 23 -#define BLSP1_QUP1_SPI_APPS_CLK_SRC 24 -#define BLSP1_QUP1_I2C_APPS_CLK_SRC 25 -#define BLSP1_UART1_APPS_CLK_SRC 26 -#define BLSP1_QUP2_SPI_APPS_CLK_SRC 27 -#define BLSP1_QUP2_I2C_APPS_CLK_SRC 28 -#define BLSP1_UART2_APPS_CLK_SRC 29 -#define BLSP1_QUP3_SPI_APPS_CLK_SRC 30 -#define BLSP1_QUP3_I2C_APPS_CLK_SRC 31 -#define BLSP1_UART3_APPS_CLK_SRC 32 -#define BLSP1_QUP4_SPI_APPS_CLK_SRC 33 -#define BLSP1_QUP4_I2C_APPS_CLK_SRC 34 -#define BLSP1_UART4_APPS_CLK_SRC 35 -#define BLSP1_QUP5_SPI_APPS_CLK_SRC 36 -#define BLSP1_QUP5_I2C_APPS_CLK_SRC 37 -#define BLSP1_UART5_APPS_CLK_SRC 38 -#define BLSP1_QUP6_SPI_APPS_CLK_SRC 39 -#define BLSP1_QUP6_I2C_APPS_CLK_SRC 40 -#define BLSP1_UART6_APPS_CLK_SRC 41 -#define BLSP2_QUP1_SPI_APPS_CLK_SRC 42 -#define BLSP2_QUP1_I2C_APPS_CLK_SRC 43 -#define BLSP2_UART1_APPS_CLK_SRC 44 -#define BLSP2_QUP2_SPI_APPS_CLK_SRC 45 -#define BLSP2_QUP2_I2C_APPS_CLK_SRC 46 -#define BLSP2_UART2_APPS_CLK_SRC 47 -#define BLSP2_QUP3_SPI_APPS_CLK_SRC 48 -#define BLSP2_QUP3_I2C_APPS_CLK_SRC 49 -#define BLSP2_UART3_APPS_CLK_SRC 50 -#define BLSP2_QUP4_SPI_APPS_CLK_SRC 51 -#define BLSP2_QUP4_I2C_APPS_CLK_SRC 52 -#define BLSP2_UART4_APPS_CLK_SRC 53 -#define BLSP2_QUP5_SPI_APPS_CLK_SRC 54 -#define BLSP2_QUP5_I2C_APPS_CLK_SRC 55 -#define BLSP2_UART5_APPS_CLK_SRC 56 -#define BLSP2_QUP6_SPI_APPS_CLK_SRC 57 -#define BLSP2_QUP6_I2C_APPS_CLK_SRC 58 -#define BLSP2_UART6_APPS_CLK_SRC 59 -#define PDM2_CLK_SRC 60 -#define TSIF_REF_CLK_SRC 61 -#define CE1_CLK_SRC 62 -#define GCC_SLEEP_CLK_SRC 63 -#define BIMC_CLK_SRC 64 -#define HMSS_AHB_CLK_SRC 65 -#define BIMC_HMSS_AXI_CLK_SRC 66 -#define HMSS_RBCPR_CLK_SRC 67 -#define HMSS_GPLL0_CLK_SRC 68 -#define GP1_CLK_SRC 69 -#define GP2_CLK_SRC 70 -#define GP3_CLK_SRC 71 -#define PCIE_AUX_CLK_SRC 72 -#define UFS_AXI_CLK_SRC 73 -#define UFS_ICE_CORE_CLK_SRC 74 -#define QSPI_SER_CLK_SRC 75 -#define GCC_SYS_NOC_AXI_CLK 76 -#define GCC_SYS_NOC_HMSS_AHB_CLK 77 -#define GCC_SNOC_CNOC_AHB_CLK 78 -#define GCC_SNOC_PNOC_AHB_CLK 79 -#define GCC_SYS_NOC_AT_CLK 80 -#define GCC_SYS_NOC_USB3_AXI_CLK 81 -#define GCC_SYS_NOC_UFS_AXI_CLK 82 -#define GCC_CFG_NOC_AHB_CLK 83 -#define GCC_PERIPH_NOC_AHB_CLK 84 -#define GCC_PERIPH_NOC_USB20_AHB_CLK 85 -#define GCC_TIC_CLK 86 -#define GCC_IMEM_AXI_CLK 87 -#define GCC_MMSS_SYS_NOC_AXI_CLK 88 -#define GCC_MMSS_NOC_CFG_AHB_CLK 89 -#define GCC_MMSS_BIMC_GFX_CLK 90 -#define GCC_USB30_MASTER_CLK 91 -#define GCC_USB30_SLEEP_CLK 92 -#define GCC_USB30_MOCK_UTMI_CLK 93 -#define GCC_USB3_PHY_AUX_CLK 94 -#define GCC_USB3_PHY_PIPE_CLK 95 -#define GCC_USB20_MASTER_CLK 96 -#define GCC_USB20_SLEEP_CLK 97 -#define GCC_USB20_MOCK_UTMI_CLK 98 -#define GCC_USB_PHY_CFG_AHB2PHY_CLK 99 -#define GCC_SDCC1_APPS_CLK 100 -#define GCC_SDCC1_AHB_CLK 101 -#define GCC_SDCC1_ICE_CORE_CLK 102 -#define GCC_SDCC2_APPS_CLK 103 -#define GCC_SDCC2_AHB_CLK 104 -#define GCC_SDCC3_APPS_CLK 105 -#define GCC_SDCC3_AHB_CLK 106 -#define GCC_SDCC4_APPS_CLK 107 -#define GCC_SDCC4_AHB_CLK 108 -#define GCC_BLSP1_AHB_CLK 109 -#define GCC_BLSP1_SLEEP_CLK 110 -#define GCC_BLSP1_QUP1_SPI_APPS_CLK 111 -#define GCC_BLSP1_QUP1_I2C_APPS_CLK 112 -#define GCC_BLSP1_UART1_APPS_CLK 113 -#define GCC_BLSP1_QUP2_SPI_APPS_CLK 114 -#define GCC_BLSP1_QUP2_I2C_APPS_CLK 115 -#define GCC_BLSP1_UART2_APPS_CLK 116 -#define GCC_BLSP1_QUP3_SPI_APPS_CLK 117 -#define GCC_BLSP1_QUP3_I2C_APPS_CLK 118 -#define GCC_BLSP1_UART3_APPS_CLK 119 -#define GCC_BLSP1_QUP4_SPI_APPS_CLK 120 -#define GCC_BLSP1_QUP4_I2C_APPS_CLK 121 -#define GCC_BLSP1_UART4_APPS_CLK 122 -#define GCC_BLSP1_QUP5_SPI_APPS_CLK 123 -#define GCC_BLSP1_QUP5_I2C_APPS_CLK 124 -#define GCC_BLSP1_UART5_APPS_CLK 125 -#define GCC_BLSP1_QUP6_SPI_APPS_CLK 126 -#define GCC_BLSP1_QUP6_I2C_APPS_CLK 127 -#define GCC_BLSP1_UART6_APPS_CLK 128 -#define GCC_BLSP2_AHB_CLK 129 -#define GCC_BLSP2_SLEEP_CLK 130 -#define GCC_BLSP2_QUP1_SPI_APPS_CLK 131 -#define GCC_BLSP2_QUP1_I2C_APPS_CLK 132 -#define GCC_BLSP2_UART1_APPS_CLK 133 -#define GCC_BLSP2_QUP2_SPI_APPS_CLK 134 -#define GCC_BLSP2_QUP2_I2C_APPS_CLK 135 -#define GCC_BLSP2_UART2_APPS_CLK 136 -#define GCC_BLSP2_QUP3_SPI_APPS_CLK 137 -#define GCC_BLSP2_QUP3_I2C_APPS_CLK 138 -#define GCC_BLSP2_UART3_APPS_CLK 139 -#define GCC_BLSP2_QUP4_SPI_APPS_CLK 140 -#define GCC_BLSP2_QUP4_I2C_APPS_CLK 141 -#define GCC_BLSP2_UART4_APPS_CLK 142 -#define GCC_BLSP2_QUP5_SPI_APPS_CLK 143 -#define GCC_BLSP2_QUP5_I2C_APPS_CLK 144 -#define GCC_BLSP2_UART5_APPS_CLK 145 -#define GCC_BLSP2_QUP6_SPI_APPS_CLK 146 -#define GCC_BLSP2_QUP6_I2C_APPS_CLK 147 -#define GCC_BLSP2_UART6_APPS_CLK 148 -#define GCC_PDM_AHB_CLK 149 -#define GCC_PDM_XO4_CLK 150 -#define GCC_PDM2_CLK 151 -#define GCC_PRNG_AHB_CLK 152 -#define GCC_TSIF_AHB_CLK 153 -#define GCC_TSIF_REF_CLK 154 -#define GCC_TSIF_INACTIVITY_TIMERS_CLK 155 -#define GCC_TCSR_AHB_CLK 156 -#define GCC_BOOT_ROM_AHB_CLK 157 -#define GCC_MSG_RAM_AHB_CLK 158 -#define GCC_TLMM_AHB_CLK 159 -#define GCC_TLMM_CLK 160 -#define GCC_MPM_AHB_CLK 161 -#define GCC_SPMI_SER_CLK 162 -#define GCC_SPMI_CNOC_AHB_CLK 163 -#define GCC_CE1_CLK 164 -#define GCC_CE1_AXI_CLK 165 -#define GCC_CE1_AHB_CLK 166 -#define GCC_BIMC_HMSS_AXI_CLK 167 -#define GCC_BIMC_GFX_CLK 168 -#define GCC_HMSS_AHB_CLK 169 -#define GCC_HMSS_SLV_AXI_CLK 170 -#define GCC_HMSS_MSTR_AXI_CLK 171 -#define GCC_HMSS_RBCPR_CLK 172 -#define GCC_GP1_CLK 173 -#define GCC_GP2_CLK 174 -#define GCC_GP3_CLK 175 -#define GCC_PCIE_0_SLV_AXI_CLK 176 -#define GCC_PCIE_0_MSTR_AXI_CLK 177 -#define GCC_PCIE_0_CFG_AHB_CLK 178 -#define GCC_PCIE_0_AUX_CLK 179 -#define GCC_PCIE_0_PIPE_CLK 180 -#define GCC_PCIE_1_SLV_AXI_CLK 181 -#define GCC_PCIE_1_MSTR_AXI_CLK 182 -#define GCC_PCIE_1_CFG_AHB_CLK 183 -#define GCC_PCIE_1_AUX_CLK 184 -#define GCC_PCIE_1_PIPE_CLK 185 -#define GCC_PCIE_2_SLV_AXI_CLK 186 -#define GCC_PCIE_2_MSTR_AXI_CLK 187 -#define GCC_PCIE_2_CFG_AHB_CLK 188 -#define GCC_PCIE_2_AUX_CLK 189 -#define GCC_PCIE_2_PIPE_CLK 190 -#define GCC_PCIE_PHY_CFG_AHB_CLK 191 -#define GCC_PCIE_PHY_AUX_CLK 192 -#define GCC_UFS_AXI_CLK 193 -#define GCC_UFS_AHB_CLK 194 -#define GCC_UFS_TX_CFG_CLK 195 -#define GCC_UFS_RX_CFG_CLK 196 -#define GCC_UFS_TX_SYMBOL_0_CLK 197 -#define GCC_UFS_RX_SYMBOL_0_CLK 198 -#define GCC_UFS_RX_SYMBOL_1_CLK 199 -#define GCC_UFS_UNIPRO_CORE_CLK 200 -#define GCC_UFS_ICE_CORE_CLK 201 -#define GCC_UFS_SYS_CLK_CORE_CLK 202 -#define GCC_UFS_TX_SYMBOL_CLK_CORE_CLK 203 -#define GCC_AGGRE0_SNOC_AXI_CLK 204 -#define GCC_AGGRE0_CNOC_AHB_CLK 205 -#define GCC_SMMU_AGGRE0_AXI_CLK 206 -#define GCC_SMMU_AGGRE0_AHB_CLK 207 -#define GCC_AGGRE1_PNOC_AHB_CLK 208 -#define GCC_AGGRE2_UFS_AXI_CLK 209 -#define GCC_AGGRE2_USB3_AXI_CLK 210 -#define GCC_QSPI_AHB_CLK 211 -#define GCC_QSPI_SER_CLK 212 -#define GCC_USB3_CLKREF_CLK 213 -#define GCC_HDMI_CLKREF_CLK 214 -#define GCC_UFS_CLKREF_CLK 215 -#define GCC_PCIE_CLKREF_CLK 216 -#define GCC_RX2_USB2_CLKREF_CLK 217 -#define GCC_RX1_USB2_CLKREF_CLK 218 -#define GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK 219 -#define GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK 220 -#define GCC_EDP_CLKREF_CLK 221 -#define GCC_MSS_CFG_AHB_CLK 222 -#define GCC_MSS_Q6_BIMC_AXI_CLK 223 -#define GCC_MSS_SNOC_AXI_CLK 224 -#define GCC_MSS_MNOC_BIMC_AXI_CLK 225 -#define GCC_DCC_AHB_CLK 226 -#define GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK 227 -#define GCC_MMSS_GPLL0_DIV_CLK 228 -#define GCC_MSS_GPLL0_DIV_CLK 229 - -#define GCC_SYSTEM_NOC_BCR 0 -#define GCC_CONFIG_NOC_BCR 1 -#define GCC_PERIPH_NOC_BCR 2 -#define GCC_IMEM_BCR 3 -#define GCC_MMSS_BCR 4 -#define GCC_PIMEM_BCR 5 -#define GCC_QDSS_BCR 6 -#define GCC_USB_30_BCR 7 -#define GCC_USB_20_BCR 8 -#define GCC_QUSB2PHY_PRIM_BCR 9 -#define GCC_QUSB2PHY_SEC_BCR 10 -#define GCC_USB_PHY_CFG_AHB2PHY_BCR 11 -#define GCC_SDCC1_BCR 12 -#define GCC_SDCC2_BCR 13 -#define GCC_SDCC3_BCR 14 -#define GCC_SDCC4_BCR 15 -#define GCC_BLSP1_BCR 16 -#define GCC_BLSP1_QUP1_BCR 17 -#define GCC_BLSP1_UART1_BCR 18 -#define GCC_BLSP1_QUP2_BCR 19 -#define GCC_BLSP1_UART2_BCR 20 -#define GCC_BLSP1_QUP3_BCR 21 -#define GCC_BLSP1_UART3_BCR 22 -#define GCC_BLSP1_QUP4_BCR 23 -#define GCC_BLSP1_UART4_BCR 24 -#define GCC_BLSP1_QUP5_BCR 25 -#define GCC_BLSP1_UART5_BCR 26 -#define GCC_BLSP1_QUP6_BCR 27 -#define GCC_BLSP1_UART6_BCR 28 -#define GCC_BLSP2_BCR 29 -#define GCC_BLSP2_QUP1_BCR 30 -#define GCC_BLSP2_UART1_BCR 31 -#define GCC_BLSP2_QUP2_BCR 32 -#define GCC_BLSP2_UART2_BCR 33 -#define GCC_BLSP2_QUP3_BCR 34 -#define GCC_BLSP2_UART3_BCR 35 -#define GCC_BLSP2_QUP4_BCR 36 -#define GCC_BLSP2_UART4_BCR 37 -#define GCC_BLSP2_QUP5_BCR 38 -#define GCC_BLSP2_UART5_BCR 39 -#define GCC_BLSP2_QUP6_BCR 40 -#define GCC_BLSP2_UART6_BCR 41 -#define GCC_PDM_BCR 42 -#define GCC_PRNG_BCR 43 -#define GCC_TSIF_BCR 44 -#define GCC_TCSR_BCR 45 -#define GCC_BOOT_ROM_BCR 46 -#define GCC_MSG_RAM_BCR 47 -#define GCC_TLMM_BCR 48 -#define GCC_MPM_BCR 49 -#define GCC_SEC_CTRL_BCR 50 -#define GCC_SPMI_BCR 51 -#define GCC_SPDM_BCR 52 -#define GCC_CE1_BCR 53 -#define GCC_BIMC_BCR 54 -#define GCC_SNOC_BUS_TIMEOUT0_BCR 55 -#define GCC_SNOC_BUS_TIMEOUT2_BCR 56 -#define GCC_SNOC_BUS_TIMEOUT1_BCR 57 -#define GCC_SNOC_BUS_TIMEOUT3_BCR 58 -#define GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR 59 -#define GCC_PNOC_BUS_TIMEOUT0_BCR 60 -#define GCC_PNOC_BUS_TIMEOUT1_BCR 61 -#define GCC_PNOC_BUS_TIMEOUT2_BCR 62 -#define GCC_PNOC_BUS_TIMEOUT3_BCR 63 -#define GCC_PNOC_BUS_TIMEOUT4_BCR 64 -#define GCC_CNOC_BUS_TIMEOUT0_BCR 65 -#define GCC_CNOC_BUS_TIMEOUT1_BCR 66 -#define GCC_CNOC_BUS_TIMEOUT2_BCR 67 -#define GCC_CNOC_BUS_TIMEOUT3_BCR 68 -#define GCC_CNOC_BUS_TIMEOUT4_BCR 69 -#define GCC_CNOC_BUS_TIMEOUT5_BCR 70 -#define GCC_CNOC_BUS_TIMEOUT6_BCR 71 -#define GCC_CNOC_BUS_TIMEOUT7_BCR 72 -#define GCC_CNOC_BUS_TIMEOUT8_BCR 73 -#define GCC_CNOC_BUS_TIMEOUT9_BCR 74 -#define GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR 75 -#define GCC_APB2JTAG_BCR 76 -#define GCC_RBCPR_CX_BCR 77 -#define GCC_RBCPR_MX_BCR 78 -#define GCC_PCIE_0_BCR 79 -#define GCC_PCIE_0_PHY_BCR 80 -#define GCC_PCIE_1_BCR 81 -#define GCC_PCIE_1_PHY_BCR 82 -#define GCC_PCIE_2_BCR 83 -#define GCC_PCIE_2_PHY_BCR 84 -#define GCC_PCIE_PHY_BCR 85 -#define GCC_DCD_BCR 86 -#define GCC_OBT_ODT_BCR 87 -#define GCC_UFS_BCR 88 -#define GCC_SSC_BCR 89 -#define GCC_VS_BCR 90 -#define GCC_AGGRE0_NOC_BCR 91 -#define GCC_AGGRE1_NOC_BCR 92 -#define GCC_AGGRE2_NOC_BCR 93 -#define GCC_DCC_BCR 94 -#define GCC_IPA_BCR 95 -#define GCC_QSPI_BCR 96 -#define GCC_SKL_BCR 97 -#define GCC_MSMPU_BCR 98 -#define GCC_MSS_Q6_BCR 99 -#define GCC_QREFS_VBG_CAL_BCR 100 -#define GCC_PCIE_PHY_COM_BCR 101 -#define GCC_PCIE_PHY_COM_NOCSR_BCR 102 -#define GCC_USB3_PHY_BCR 103 -#define GCC_USB3PHY_PHY_BCR 104 -#define GCC_MSS_RESTART 105 - -/* Indexes for GDSCs */ -#define AGGRE0_NOC_GDSC 0 -#define HLOS1_VOTE_AGGRE0_NOC_GDSC 1 -#define HLOS1_VOTE_LPASS_ADSP_GDSC 2 -#define HLOS1_VOTE_LPASS_CORE_GDSC 3 -#define USB30_GDSC 4 -#define PCIE0_GDSC 5 -#define PCIE1_GDSC 6 -#define PCIE2_GDSC 7 -#define UFS_GDSC 8 - -#endif diff --git a/include/dt-bindings/clock/qcom,gcc-qcs404.h b/include/dt-bindings/clock/qcom,gcc-qcs404.h deleted file mode 100644 index bc305154334..00000000000 --- a/include/dt-bindings/clock/qcom,gcc-qcs404.h +++ /dev/null @@ -1,180 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_QCOM_GCC_QCS404_H -#define _DT_BINDINGS_CLK_QCOM_GCC_QCS404_H - -#define GCC_APSS_AHB_CLK_SRC 0 -#define GCC_BLSP1_QUP0_I2C_APPS_CLK_SRC 1 -#define GCC_BLSP1_QUP0_SPI_APPS_CLK_SRC 2 -#define GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC 3 -#define GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC 4 -#define GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC 5 -#define GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC 6 -#define GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC 7 -#define GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC 8 -#define GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC 9 -#define GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC 10 -#define GCC_BLSP1_UART0_APPS_CLK_SRC 11 -#define GCC_BLSP1_UART1_APPS_CLK_SRC 12 -#define GCC_BLSP1_UART2_APPS_CLK_SRC 13 -#define GCC_BLSP1_UART3_APPS_CLK_SRC 14 -#define GCC_BLSP2_QUP0_I2C_APPS_CLK_SRC 15 -#define GCC_BLSP2_QUP0_SPI_APPS_CLK_SRC 16 -#define GCC_BLSP2_UART0_APPS_CLK_SRC 17 -#define GCC_BYTE0_CLK_SRC 18 -#define GCC_EMAC_CLK_SRC 19 -#define GCC_EMAC_PTP_CLK_SRC 20 -#define GCC_ESC0_CLK_SRC 21 -#define GCC_APSS_AHB_CLK 22 -#define GCC_APSS_AXI_CLK 23 -#define GCC_BIMC_APSS_AXI_CLK 24 -#define GCC_BIMC_GFX_CLK 25 -#define GCC_BIMC_MDSS_CLK 26 -#define GCC_BLSP1_AHB_CLK 27 -#define GCC_BLSP1_QUP0_I2C_APPS_CLK 28 -#define GCC_BLSP1_QUP0_SPI_APPS_CLK 29 -#define GCC_BLSP1_QUP1_I2C_APPS_CLK 30 -#define GCC_BLSP1_QUP1_SPI_APPS_CLK 31 -#define GCC_BLSP1_QUP2_I2C_APPS_CLK 32 -#define GCC_BLSP1_QUP2_SPI_APPS_CLK 33 -#define GCC_BLSP1_QUP3_I2C_APPS_CLK 34 -#define GCC_BLSP1_QUP3_SPI_APPS_CLK 35 -#define GCC_BLSP1_QUP4_I2C_APPS_CLK 36 -#define GCC_BLSP1_QUP4_SPI_APPS_CLK 37 -#define GCC_BLSP1_UART0_APPS_CLK 38 -#define GCC_BLSP1_UART1_APPS_CLK 39 -#define GCC_BLSP1_UART2_APPS_CLK 40 -#define GCC_BLSP1_UART3_APPS_CLK 41 -#define GCC_BLSP2_AHB_CLK 42 -#define GCC_BLSP2_QUP0_I2C_APPS_CLK 43 -#define GCC_BLSP2_QUP0_SPI_APPS_CLK 44 -#define GCC_BLSP2_UART0_APPS_CLK 45 -#define GCC_BOOT_ROM_AHB_CLK 46 -#define GCC_DCC_CLK 47 -#define GCC_GENI_IR_H_CLK 48 -#define GCC_ETH_AXI_CLK 49 -#define GCC_ETH_PTP_CLK 50 -#define GCC_ETH_RGMII_CLK 51 -#define GCC_ETH_SLAVE_AHB_CLK 52 -#define GCC_GENI_IR_S_CLK 53 -#define GCC_GP1_CLK 54 -#define GCC_GP2_CLK 55 -#define GCC_GP3_CLK 56 -#define GCC_MDSS_AHB_CLK 57 -#define GCC_MDSS_AXI_CLK 58 -#define GCC_MDSS_BYTE0_CLK 59 -#define GCC_MDSS_ESC0_CLK 60 -#define GCC_MDSS_HDMI_APP_CLK 61 -#define GCC_MDSS_HDMI_PCLK_CLK 62 -#define GCC_MDSS_MDP_CLK 63 -#define GCC_MDSS_PCLK0_CLK 64 -#define GCC_MDSS_VSYNC_CLK 65 -#define GCC_OXILI_AHB_CLK 66 -#define GCC_OXILI_GFX3D_CLK 67 -#define GCC_PCIE_0_AUX_CLK 68 -#define GCC_PCIE_0_CFG_AHB_CLK 69 -#define GCC_PCIE_0_MSTR_AXI_CLK 70 -#define GCC_PCIE_0_PIPE_CLK 71 -#define GCC_PCIE_0_SLV_AXI_CLK 72 -#define GCC_PCNOC_USB2_CLK 73 -#define GCC_PCNOC_USB3_CLK 74 -#define GCC_PDM2_CLK 75 -#define GCC_PDM_AHB_CLK 76 -#define GCC_VSYNC_CLK_SRC 77 -#define GCC_PRNG_AHB_CLK 78 -#define GCC_PWM0_XO512_CLK 79 -#define GCC_PWM1_XO512_CLK 80 -#define GCC_PWM2_XO512_CLK 81 -#define GCC_SDCC1_AHB_CLK 82 -#define GCC_SDCC1_APPS_CLK 83 -#define GCC_SDCC1_ICE_CORE_CLK 84 -#define GCC_SDCC2_AHB_CLK 85 -#define GCC_SDCC2_APPS_CLK 86 -#define GCC_SYS_NOC_USB3_CLK 87 -#define GCC_USB20_MOCK_UTMI_CLK 88 -#define GCC_USB2A_PHY_SLEEP_CLK 89 -#define GCC_USB30_MASTER_CLK 90 -#define GCC_USB30_MOCK_UTMI_CLK 91 -#define GCC_USB30_SLEEP_CLK 92 -#define GCC_USB3_PHY_AUX_CLK 93 -#define GCC_USB3_PHY_PIPE_CLK 94 -#define GCC_USB_HS_PHY_CFG_AHB_CLK 95 -#define GCC_USB_HS_SYSTEM_CLK 96 -#define GCC_GFX3D_CLK_SRC 97 -#define GCC_GP1_CLK_SRC 98 -#define GCC_GP2_CLK_SRC 99 -#define GCC_GP3_CLK_SRC 100 -#define GCC_GPLL0_OUT_MAIN 101 -#define GCC_GPLL1_OUT_MAIN 102 -#define GCC_GPLL3_OUT_MAIN 103 -#define GCC_GPLL4_OUT_MAIN 104 -#define GCC_HDMI_APP_CLK_SRC 105 -#define GCC_HDMI_PCLK_CLK_SRC 106 -#define GCC_MDP_CLK_SRC 107 -#define GCC_PCIE_0_AUX_CLK_SRC 108 -#define GCC_PCIE_0_PIPE_CLK_SRC 109 -#define GCC_PCLK0_CLK_SRC 110 -#define GCC_PDM2_CLK_SRC 111 -#define GCC_SDCC1_APPS_CLK_SRC 112 -#define GCC_SDCC1_ICE_CORE_CLK_SRC 113 -#define GCC_SDCC2_APPS_CLK_SRC 114 -#define GCC_USB20_MOCK_UTMI_CLK_SRC 115 -#define GCC_USB30_MASTER_CLK_SRC 116 -#define GCC_USB30_MOCK_UTMI_CLK_SRC 117 -#define GCC_USB3_PHY_AUX_CLK_SRC 118 -#define GCC_USB_HS_SYSTEM_CLK_SRC 119 -#define GCC_GPLL0_AO_CLK_SRC 120 -#define GCC_USB_HS_INACTIVITY_TIMERS_CLK 122 -#define GCC_GPLL0_AO_OUT_MAIN 123 -#define GCC_GPLL0_SLEEP_CLK_SRC 124 -#define GCC_GPLL6 125 -#define GCC_GPLL6_OUT_AUX 126 -#define GCC_MDSS_MDP_VOTE_CLK 127 -#define GCC_MDSS_ROTATOR_VOTE_CLK 128 -#define GCC_BIMC_GPU_CLK 129 -#define GCC_GTCU_AHB_CLK 130 -#define GCC_GFX_TCU_CLK 131 -#define GCC_GFX_TBU_CLK 132 -#define GCC_SMMU_CFG_CLK 133 -#define GCC_APSS_TCU_CLK 134 -#define GCC_CRYPTO_AHB_CLK 135 -#define GCC_CRYPTO_AXI_CLK 136 -#define GCC_CRYPTO_CLK 137 -#define GCC_MDP_TBU_CLK 138 -#define GCC_QDSS_DAP_CLK 139 -#define GCC_DCC_XO_CLK 140 -#define GCC_WCSS_Q6_AHB_CLK 141 -#define GCC_WCSS_Q6_AXIM_CLK 142 -#define GCC_CDSP_CFG_AHB_CLK 143 -#define GCC_BIMC_CDSP_CLK 144 -#define GCC_CDSP_TBU_CLK 145 -#define GCC_CDSP_BIMC_CLK_SRC 146 - -#define GCC_GENI_IR_BCR 0 -#define GCC_USB_HS_BCR 1 -#define GCC_USB2_HS_PHY_ONLY_BCR 2 -#define GCC_QUSB2_PHY_BCR 3 -#define GCC_USB_HS_PHY_CFG_AHB_BCR 4 -#define GCC_USB2A_PHY_BCR 5 -#define GCC_USB3_PHY_BCR 6 -#define GCC_USB_30_BCR 7 -#define GCC_USB3PHY_PHY_BCR 8 -#define GCC_PCIE_0_BCR 9 -#define GCC_PCIE_0_PHY_BCR 10 -#define GCC_PCIE_0_LINK_DOWN_BCR 11 -#define GCC_PCIEPHY_0_PHY_BCR 12 -#define GCC_EMAC_BCR 13 -#define GCC_CDSP_RESTART 14 -#define GCC_PCIE_0_AXI_MASTER_STICKY_ARES 15 -#define GCC_PCIE_0_AHB_ARES 16 -#define GCC_PCIE_0_AXI_SLAVE_ARES 17 -#define GCC_PCIE_0_AXI_MASTER_ARES 18 -#define GCC_PCIE_0_CORE_STICKY_ARES 19 -#define GCC_PCIE_0_SLEEP_ARES 20 -#define GCC_PCIE_0_PIPE_ARES 21 -#define GCC_WDSP_RESTART 22 - -#endif diff --git a/include/dt-bindings/clock/qcom,gcc-sdm845.h b/include/dt-bindings/clock/qcom,gcc-sdm845.h deleted file mode 100644 index 968fa65b9c4..00000000000 --- a/include/dt-bindings/clock/qcom,gcc-sdm845.h +++ /dev/null @@ -1,246 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_SDM_GCC_SDM845_H -#define _DT_BINDINGS_CLK_SDM_GCC_SDM845_H - -/* GCC clock registers */ -#define GCC_AGGRE_NOC_PCIE_TBU_CLK 0 -#define GCC_AGGRE_UFS_CARD_AXI_CLK 1 -#define GCC_AGGRE_UFS_PHY_AXI_CLK 2 -#define GCC_AGGRE_USB3_PRIM_AXI_CLK 3 -#define GCC_AGGRE_USB3_SEC_AXI_CLK 4 -#define GCC_BOOT_ROM_AHB_CLK 5 -#define GCC_CAMERA_AHB_CLK 6 -#define GCC_CAMERA_AXI_CLK 7 -#define GCC_CAMERA_XO_CLK 8 -#define GCC_CE1_AHB_CLK 9 -#define GCC_CE1_AXI_CLK 10 -#define GCC_CE1_CLK 11 -#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 12 -#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 13 -#define GCC_CPUSS_AHB_CLK 14 -#define GCC_CPUSS_AHB_CLK_SRC 15 -#define GCC_CPUSS_RBCPR_CLK 16 -#define GCC_CPUSS_RBCPR_CLK_SRC 17 -#define GCC_DDRSS_GPU_AXI_CLK 18 -#define GCC_DISP_AHB_CLK 19 -#define GCC_DISP_AXI_CLK 20 -#define GCC_DISP_GPLL0_CLK_SRC 21 -#define GCC_DISP_GPLL0_DIV_CLK_SRC 22 -#define GCC_DISP_XO_CLK 23 -#define GCC_GP1_CLK 24 -#define GCC_GP1_CLK_SRC 25 -#define GCC_GP2_CLK 26 -#define GCC_GP2_CLK_SRC 27 -#define GCC_GP3_CLK 28 -#define GCC_GP3_CLK_SRC 29 -#define GCC_GPU_CFG_AHB_CLK 30 -#define GCC_GPU_GPLL0_CLK_SRC 31 -#define GCC_GPU_GPLL0_DIV_CLK_SRC 32 -#define GCC_GPU_MEMNOC_GFX_CLK 33 -#define GCC_GPU_SNOC_DVM_GFX_CLK 34 -#define GCC_MSS_AXIS2_CLK 35 -#define GCC_MSS_CFG_AHB_CLK 36 -#define GCC_MSS_GPLL0_DIV_CLK_SRC 37 -#define GCC_MSS_MFAB_AXIS_CLK 38 -#define GCC_MSS_Q6_MEMNOC_AXI_CLK 39 -#define GCC_MSS_SNOC_AXI_CLK 40 -#define GCC_PCIE_0_AUX_CLK 41 -#define GCC_PCIE_0_AUX_CLK_SRC 42 -#define GCC_PCIE_0_CFG_AHB_CLK 43 -#define GCC_PCIE_0_CLKREF_CLK 44 -#define GCC_PCIE_0_MSTR_AXI_CLK 45 -#define GCC_PCIE_0_PIPE_CLK 46 -#define GCC_PCIE_0_SLV_AXI_CLK 47 -#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 48 -#define GCC_PCIE_1_AUX_CLK 49 -#define GCC_PCIE_1_AUX_CLK_SRC 50 -#define GCC_PCIE_1_CFG_AHB_CLK 51 -#define GCC_PCIE_1_CLKREF_CLK 52 -#define GCC_PCIE_1_MSTR_AXI_CLK 53 -#define GCC_PCIE_1_PIPE_CLK 54 -#define GCC_PCIE_1_SLV_AXI_CLK 55 -#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 56 -#define GCC_PCIE_PHY_AUX_CLK 57 -#define GCC_PCIE_PHY_REFGEN_CLK 58 -#define GCC_PCIE_PHY_REFGEN_CLK_SRC 59 -#define GCC_PDM2_CLK 60 -#define GCC_PDM2_CLK_SRC 61 -#define GCC_PDM_AHB_CLK 62 -#define GCC_PDM_XO4_CLK 63 -#define GCC_PRNG_AHB_CLK 64 -#define GCC_QMIP_CAMERA_AHB_CLK 65 -#define GCC_QMIP_DISP_AHB_CLK 66 -#define GCC_QMIP_VIDEO_AHB_CLK 67 -#define GCC_QUPV3_WRAP0_S0_CLK 68 -#define GCC_QUPV3_WRAP0_S0_CLK_SRC 69 -#define GCC_QUPV3_WRAP0_S1_CLK 70 -#define GCC_QUPV3_WRAP0_S1_CLK_SRC 71 -#define GCC_QUPV3_WRAP0_S2_CLK 72 -#define GCC_QUPV3_WRAP0_S2_CLK_SRC 73 -#define GCC_QUPV3_WRAP0_S3_CLK 74 -#define GCC_QUPV3_WRAP0_S3_CLK_SRC 75 -#define GCC_QUPV3_WRAP0_S4_CLK 76 -#define GCC_QUPV3_WRAP0_S4_CLK_SRC 77 -#define GCC_QUPV3_WRAP0_S5_CLK 78 -#define GCC_QUPV3_WRAP0_S5_CLK_SRC 79 -#define GCC_QUPV3_WRAP0_S6_CLK 80 -#define GCC_QUPV3_WRAP0_S6_CLK_SRC 81 -#define GCC_QUPV3_WRAP0_S7_CLK 82 -#define GCC_QUPV3_WRAP0_S7_CLK_SRC 83 -#define GCC_QUPV3_WRAP1_S0_CLK 84 -#define GCC_QUPV3_WRAP1_S0_CLK_SRC 85 -#define GCC_QUPV3_WRAP1_S1_CLK 86 -#define GCC_QUPV3_WRAP1_S1_CLK_SRC 87 -#define GCC_QUPV3_WRAP1_S2_CLK 88 -#define GCC_QUPV3_WRAP1_S2_CLK_SRC 89 -#define GCC_QUPV3_WRAP1_S3_CLK 90 -#define GCC_QUPV3_WRAP1_S3_CLK_SRC 91 -#define GCC_QUPV3_WRAP1_S4_CLK 92 -#define GCC_QUPV3_WRAP1_S4_CLK_SRC 93 -#define GCC_QUPV3_WRAP1_S5_CLK 94 -#define GCC_QUPV3_WRAP1_S5_CLK_SRC 95 -#define GCC_QUPV3_WRAP1_S6_CLK 96 -#define GCC_QUPV3_WRAP1_S6_CLK_SRC 97 -#define GCC_QUPV3_WRAP1_S7_CLK 98 -#define GCC_QUPV3_WRAP1_S7_CLK_SRC 99 -#define GCC_QUPV3_WRAP_0_M_AHB_CLK 100 -#define GCC_QUPV3_WRAP_0_S_AHB_CLK 101 -#define GCC_QUPV3_WRAP_1_M_AHB_CLK 102 -#define GCC_QUPV3_WRAP_1_S_AHB_CLK 103 -#define GCC_SDCC2_AHB_CLK 104 -#define GCC_SDCC2_APPS_CLK 105 -#define GCC_SDCC2_APPS_CLK_SRC 106 -#define GCC_SDCC4_AHB_CLK 107 -#define GCC_SDCC4_APPS_CLK 108 -#define GCC_SDCC4_APPS_CLK_SRC 109 -#define GCC_SYS_NOC_CPUSS_AHB_CLK 110 -#define GCC_TSIF_AHB_CLK 111 -#define GCC_TSIF_INACTIVITY_TIMERS_CLK 112 -#define GCC_TSIF_REF_CLK 113 -#define GCC_TSIF_REF_CLK_SRC 114 -#define GCC_UFS_CARD_AHB_CLK 115 -#define GCC_UFS_CARD_AXI_CLK 116 -#define GCC_UFS_CARD_AXI_CLK_SRC 117 -#define GCC_UFS_CARD_CLKREF_CLK 118 -#define GCC_UFS_CARD_ICE_CORE_CLK 119 -#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 120 -#define GCC_UFS_CARD_PHY_AUX_CLK 121 -#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 122 -#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 123 -#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 124 -#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 125 -#define GCC_UFS_CARD_UNIPRO_CORE_CLK 126 -#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 127 -#define GCC_UFS_MEM_CLKREF_CLK 128 -#define GCC_UFS_PHY_AHB_CLK 129 -#define GCC_UFS_PHY_AXI_CLK 130 -#define GCC_UFS_PHY_AXI_CLK_SRC 131 -#define GCC_UFS_PHY_ICE_CORE_CLK 132 -#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 133 -#define GCC_UFS_PHY_PHY_AUX_CLK 134 -#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 135 -#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 136 -#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 137 -#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 138 -#define GCC_UFS_PHY_UNIPRO_CORE_CLK 139 -#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 140 -#define GCC_USB30_PRIM_MASTER_CLK 141 -#define GCC_USB30_PRIM_MASTER_CLK_SRC 142 -#define GCC_USB30_PRIM_MOCK_UTMI_CLK 143 -#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 144 -#define GCC_USB30_PRIM_SLEEP_CLK 145 -#define GCC_USB30_SEC_MASTER_CLK 146 -#define GCC_USB30_SEC_MASTER_CLK_SRC 147 -#define GCC_USB30_SEC_MOCK_UTMI_CLK 148 -#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 149 -#define GCC_USB30_SEC_SLEEP_CLK 150 -#define GCC_USB3_PRIM_CLKREF_CLK 151 -#define GCC_USB3_PRIM_PHY_AUX_CLK 152 -#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 153 -#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 154 -#define GCC_USB3_PRIM_PHY_PIPE_CLK 155 -#define GCC_USB3_SEC_CLKREF_CLK 156 -#define GCC_USB3_SEC_PHY_AUX_CLK 157 -#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 158 -#define GCC_USB3_SEC_PHY_PIPE_CLK 159 -#define GCC_USB3_SEC_PHY_COM_AUX_CLK 160 -#define GCC_USB_PHY_CFG_AHB2PHY_CLK 161 -#define GCC_VIDEO_AHB_CLK 162 -#define GCC_VIDEO_AXI_CLK 163 -#define GCC_VIDEO_XO_CLK 164 -#define GPLL0 165 -#define GPLL0_OUT_EVEN 166 -#define GPLL0_OUT_MAIN 167 -#define GCC_GPU_IREF_CLK 168 -#define GCC_SDCC1_AHB_CLK 169 -#define GCC_SDCC1_APPS_CLK 170 -#define GCC_SDCC1_ICE_CORE_CLK 171 -#define GCC_SDCC1_APPS_CLK_SRC 172 -#define GCC_SDCC1_ICE_CORE_CLK_SRC 173 -#define GCC_APC_VS_CLK 174 -#define GCC_GPU_VS_CLK 175 -#define GCC_MSS_VS_CLK 176 -#define GCC_VDDA_VS_CLK 177 -#define GCC_VDDCX_VS_CLK 178 -#define GCC_VDDMX_VS_CLK 179 -#define GCC_VS_CTRL_AHB_CLK 180 -#define GCC_VS_CTRL_CLK 181 -#define GCC_VS_CTRL_CLK_SRC 182 -#define GCC_VSENSOR_CLK_SRC 183 -#define GPLL4 184 -#define GCC_CPUSS_DVM_BUS_CLK 185 -#define GCC_CPUSS_GNOC_CLK 186 -#define GCC_QSPI_CORE_CLK_SRC 187 -#define GCC_QSPI_CORE_CLK 188 -#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 189 -#define GCC_LPASS_Q6_AXI_CLK 190 -#define GCC_LPASS_SWAY_CLK 191 - -/* GCC Resets */ -#define GCC_MMSS_BCR 0 -#define GCC_PCIE_0_BCR 1 -#define GCC_PCIE_1_BCR 2 -#define GCC_PCIE_PHY_BCR 3 -#define GCC_PDM_BCR 4 -#define GCC_PRNG_BCR 5 -#define GCC_QUPV3_WRAPPER_0_BCR 6 -#define GCC_QUPV3_WRAPPER_1_BCR 7 -#define GCC_QUSB2PHY_PRIM_BCR 8 -#define GCC_QUSB2PHY_SEC_BCR 9 -#define GCC_SDCC2_BCR 10 -#define GCC_SDCC4_BCR 11 -#define GCC_TSIF_BCR 12 -#define GCC_UFS_CARD_BCR 13 -#define GCC_UFS_PHY_BCR 14 -#define GCC_USB30_PRIM_BCR 15 -#define GCC_USB30_SEC_BCR 16 -#define GCC_USB3_PHY_PRIM_BCR 17 -#define GCC_USB3PHY_PHY_PRIM_BCR 18 -#define GCC_USB3_DP_PHY_PRIM_BCR 19 -#define GCC_USB3_PHY_SEC_BCR 20 -#define GCC_USB3PHY_PHY_SEC_BCR 21 -#define GCC_USB3_DP_PHY_SEC_BCR 22 -#define GCC_USB_PHY_CFG_AHB2PHY_BCR 23 -#define GCC_PCIE_0_PHY_BCR 24 -#define GCC_PCIE_1_PHY_BCR 25 - -/* GCC GDSCRs */ -#define PCIE_0_GDSC 0 -#define PCIE_1_GDSC 1 -#define UFS_CARD_GDSC 2 -#define UFS_PHY_GDSC 3 -#define USB30_PRIM_GDSC 4 -#define USB30_SEC_GDSC 5 -#define HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC 6 -#define HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC 7 -#define HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC 8 -#define HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC 9 -#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 10 -#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 11 -#define HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC 12 - -#endif diff --git a/include/dt-bindings/clock/qcom,gpucc-sdm845.h b/include/dt-bindings/clock/qcom,gpucc-sdm845.h deleted file mode 100644 index 9690d901b50..00000000000 --- a/include/dt-bindings/clock/qcom,gpucc-sdm845.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_SDM_GPU_CC_SDM845_H -#define _DT_BINDINGS_CLK_SDM_GPU_CC_SDM845_H - -/* GPU_CC clock registers */ -#define GPU_CC_CX_GMU_CLK 0 -#define GPU_CC_CXO_CLK 1 -#define GPU_CC_GMU_CLK_SRC 2 -#define GPU_CC_PLL1 3 - -/* GPU_CC Resets */ -#define GPUCC_GPU_CC_CX_BCR 0 -#define GPUCC_GPU_CC_GMU_BCR 1 -#define GPUCC_GPU_CC_XO_BCR 2 - -/* GPU_CC GDSCRs */ -#define GPU_CX_GDSC 0 -#define GPU_GX_GDSC 1 - -#endif diff --git a/include/dt-bindings/clock/qcom,lpass-sdm845.h b/include/dt-bindings/clock/qcom,lpass-sdm845.h deleted file mode 100644 index 659050846f6..00000000000 --- a/include/dt-bindings/clock/qcom,lpass-sdm845.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_SDM_LPASS_SDM845_H -#define _DT_BINDINGS_CLK_SDM_LPASS_SDM845_H - -#define LPASS_Q6SS_AHBM_AON_CLK 0 -#define LPASS_Q6SS_AHBS_AON_CLK 1 -#define LPASS_QDSP6SS_XO_CLK 2 -#define LPASS_QDSP6SS_SLEEP_CLK 3 -#define LPASS_QDSP6SS_CORE_CLK 4 - -#endif diff --git a/include/dt-bindings/clock/qcom,mmcc-msm8996.h b/include/dt-bindings/clock/qcom,mmcc-msm8996.h deleted file mode 100644 index d51f9ac7056..00000000000 --- a/include/dt-bindings/clock/qcom,mmcc-msm8996.h +++ /dev/null @@ -1,295 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2015, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_MSM_MMCC_8996_H -#define _DT_BINDINGS_CLK_MSM_MMCC_8996_H - -#define MMPLL0_EARLY 0 -#define MMPLL0_PLL 1 -#define MMPLL1_EARLY 2 -#define MMPLL1_PLL 3 -#define MMPLL2_EARLY 4 -#define MMPLL2_PLL 5 -#define MMPLL3_EARLY 6 -#define MMPLL3_PLL 7 -#define MMPLL4_EARLY 8 -#define MMPLL4_PLL 9 -#define MMPLL5_EARLY 10 -#define MMPLL5_PLL 11 -#define MMPLL8_EARLY 12 -#define MMPLL8_PLL 13 -#define MMPLL9_EARLY 14 -#define MMPLL9_PLL 15 -#define AHB_CLK_SRC 16 -#define AXI_CLK_SRC 17 -#define MAXI_CLK_SRC 18 -#define DSA_CORE_CLK_SRC 19 -#define GFX3D_CLK_SRC 20 -#define RBBMTIMER_CLK_SRC 21 -#define ISENSE_CLK_SRC 22 -#define RBCPR_CLK_SRC 23 -#define VIDEO_CORE_CLK_SRC 24 -#define VIDEO_SUBCORE0_CLK_SRC 25 -#define VIDEO_SUBCORE1_CLK_SRC 26 -#define PCLK0_CLK_SRC 27 -#define PCLK1_CLK_SRC 28 -#define MDP_CLK_SRC 29 -#define EXTPCLK_CLK_SRC 30 -#define VSYNC_CLK_SRC 31 -#define HDMI_CLK_SRC 32 -#define BYTE0_CLK_SRC 33 -#define BYTE1_CLK_SRC 34 -#define ESC0_CLK_SRC 35 -#define ESC1_CLK_SRC 36 -#define CAMSS_GP0_CLK_SRC 37 -#define CAMSS_GP1_CLK_SRC 38 -#define MCLK0_CLK_SRC 39 -#define MCLK1_CLK_SRC 40 -#define MCLK2_CLK_SRC 41 -#define MCLK3_CLK_SRC 42 -#define CCI_CLK_SRC 43 -#define CSI0PHYTIMER_CLK_SRC 44 -#define CSI1PHYTIMER_CLK_SRC 45 -#define CSI2PHYTIMER_CLK_SRC 46 -#define CSIPHY0_3P_CLK_SRC 47 -#define CSIPHY1_3P_CLK_SRC 48 -#define CSIPHY2_3P_CLK_SRC 49 -#define JPEG0_CLK_SRC 50 -#define JPEG2_CLK_SRC 51 -#define JPEG_DMA_CLK_SRC 52 -#define VFE0_CLK_SRC 53 -#define VFE1_CLK_SRC 54 -#define CPP_CLK_SRC 55 -#define CSI0_CLK_SRC 56 -#define CSI1_CLK_SRC 57 -#define CSI2_CLK_SRC 58 -#define CSI3_CLK_SRC 59 -#define FD_CORE_CLK_SRC 60 -#define MMSS_CXO_CLK 61 -#define MMSS_SLEEPCLK_CLK 62 -#define MMSS_MMAGIC_AHB_CLK 63 -#define MMSS_MMAGIC_CFG_AHB_CLK 64 -#define MMSS_MISC_AHB_CLK 65 -#define MMSS_MISC_CXO_CLK 66 -#define MMSS_BTO_AHB_CLK 67 -#define MMSS_MMAGIC_AXI_CLK 68 -#define MMSS_S0_AXI_CLK 69 -#define MMSS_MMAGIC_MAXI_CLK 70 -#define DSA_CORE_CLK 71 -#define DSA_NOC_CFG_AHB_CLK 72 -#define MMAGIC_CAMSS_AXI_CLK 73 -#define MMAGIC_CAMSS_NOC_CFG_AHB_CLK 74 -#define THROTTLE_CAMSS_CXO_CLK 75 -#define THROTTLE_CAMSS_AHB_CLK 76 -#define THROTTLE_CAMSS_AXI_CLK 77 -#define SMMU_VFE_AHB_CLK 78 -#define SMMU_VFE_AXI_CLK 79 -#define SMMU_CPP_AHB_CLK 80 -#define SMMU_CPP_AXI_CLK 81 -#define SMMU_JPEG_AHB_CLK 82 -#define SMMU_JPEG_AXI_CLK 83 -#define MMAGIC_MDSS_AXI_CLK 84 -#define MMAGIC_MDSS_NOC_CFG_AHB_CLK 85 -#define THROTTLE_MDSS_CXO_CLK 86 -#define THROTTLE_MDSS_AHB_CLK 87 -#define THROTTLE_MDSS_AXI_CLK 88 -#define SMMU_ROT_AHB_CLK 89 -#define SMMU_ROT_AXI_CLK 90 -#define SMMU_MDP_AHB_CLK 91 -#define SMMU_MDP_AXI_CLK 92 -#define MMAGIC_VIDEO_AXI_CLK 93 -#define MMAGIC_VIDEO_NOC_CFG_AHB_CLK 94 -#define THROTTLE_VIDEO_CXO_CLK 95 -#define THROTTLE_VIDEO_AHB_CLK 96 -#define THROTTLE_VIDEO_AXI_CLK 97 -#define SMMU_VIDEO_AHB_CLK 98 -#define SMMU_VIDEO_AXI_CLK 99 -#define MMAGIC_BIMC_AXI_CLK 100 -#define MMAGIC_BIMC_NOC_CFG_AHB_CLK 101 -#define GPU_GX_GFX3D_CLK 102 -#define GPU_GX_RBBMTIMER_CLK 103 -#define GPU_AHB_CLK 104 -#define GPU_AON_ISENSE_CLK 105 -#define VMEM_MAXI_CLK 106 -#define VMEM_AHB_CLK 107 -#define MMSS_RBCPR_CLK 108 -#define MMSS_RBCPR_AHB_CLK 109 -#define VIDEO_CORE_CLK 110 -#define VIDEO_AXI_CLK 111 -#define VIDEO_MAXI_CLK 112 -#define VIDEO_AHB_CLK 113 -#define VIDEO_SUBCORE0_CLK 114 -#define VIDEO_SUBCORE1_CLK 115 -#define MDSS_AHB_CLK 116 -#define MDSS_HDMI_AHB_CLK 117 -#define MDSS_AXI_CLK 118 -#define MDSS_PCLK0_CLK 119 -#define MDSS_PCLK1_CLK 120 -#define MDSS_MDP_CLK 121 -#define MDSS_EXTPCLK_CLK 122 -#define MDSS_VSYNC_CLK 123 -#define MDSS_HDMI_CLK 124 -#define MDSS_BYTE0_CLK 125 -#define MDSS_BYTE1_CLK 126 -#define MDSS_ESC0_CLK 127 -#define MDSS_ESC1_CLK 128 -#define CAMSS_TOP_AHB_CLK 129 -#define CAMSS_AHB_CLK 130 -#define CAMSS_MICRO_AHB_CLK 131 -#define CAMSS_GP0_CLK 132 -#define CAMSS_GP1_CLK 133 -#define CAMSS_MCLK0_CLK 134 -#define CAMSS_MCLK1_CLK 135 -#define CAMSS_MCLK2_CLK 136 -#define CAMSS_MCLK3_CLK 137 -#define CAMSS_CCI_CLK 138 -#define CAMSS_CCI_AHB_CLK 139 -#define CAMSS_CSI0PHYTIMER_CLK 140 -#define CAMSS_CSI1PHYTIMER_CLK 141 -#define CAMSS_CSI2PHYTIMER_CLK 142 -#define CAMSS_CSIPHY0_3P_CLK 143 -#define CAMSS_CSIPHY1_3P_CLK 144 -#define CAMSS_CSIPHY2_3P_CLK 145 -#define CAMSS_JPEG0_CLK 146 -#define CAMSS_JPEG2_CLK 147 -#define CAMSS_JPEG_DMA_CLK 148 -#define CAMSS_JPEG_AHB_CLK 149 -#define CAMSS_JPEG_AXI_CLK 150 -#define CAMSS_VFE_AHB_CLK 151 -#define CAMSS_VFE_AXI_CLK 152 -#define CAMSS_VFE0_CLK 153 -#define CAMSS_VFE0_STREAM_CLK 154 -#define CAMSS_VFE0_AHB_CLK 155 -#define CAMSS_VFE1_CLK 156 -#define CAMSS_VFE1_STREAM_CLK 157 -#define CAMSS_VFE1_AHB_CLK 158 -#define CAMSS_CSI_VFE0_CLK 159 -#define CAMSS_CSI_VFE1_CLK 160 -#define CAMSS_CPP_VBIF_AHB_CLK 161 -#define CAMSS_CPP_AXI_CLK 162 -#define CAMSS_CPP_CLK 163 -#define CAMSS_CPP_AHB_CLK 164 -#define CAMSS_CSI0_CLK 165 -#define CAMSS_CSI0_AHB_CLK 166 -#define CAMSS_CSI0PHY_CLK 167 -#define CAMSS_CSI0RDI_CLK 168 -#define CAMSS_CSI0PIX_CLK 169 -#define CAMSS_CSI1_CLK 170 -#define CAMSS_CSI1_AHB_CLK 171 -#define CAMSS_CSI1PHY_CLK 172 -#define CAMSS_CSI1RDI_CLK 173 -#define CAMSS_CSI1PIX_CLK 174 -#define CAMSS_CSI2_CLK 175 -#define CAMSS_CSI2_AHB_CLK 176 -#define CAMSS_CSI2PHY_CLK 177 -#define CAMSS_CSI2RDI_CLK 178 -#define CAMSS_CSI2PIX_CLK 179 -#define CAMSS_CSI3_CLK 180 -#define CAMSS_CSI3_AHB_CLK 181 -#define CAMSS_CSI3PHY_CLK 182 -#define CAMSS_CSI3RDI_CLK 183 -#define CAMSS_CSI3PIX_CLK 184 -#define CAMSS_ISPIF_AHB_CLK 185 -#define FD_CORE_CLK 186 -#define FD_CORE_UAR_CLK 187 -#define FD_AHB_CLK 188 -#define MMSS_SPDM_CSI0_CLK 189 -#define MMSS_SPDM_JPEG_DMA_CLK 190 -#define MMSS_SPDM_CPP_CLK 191 -#define MMSS_SPDM_PCLK0_CLK 192 -#define MMSS_SPDM_AHB_CLK 193 -#define MMSS_SPDM_GFX3D_CLK 194 -#define MMSS_SPDM_PCLK1_CLK 195 -#define MMSS_SPDM_JPEG2_CLK 196 -#define MMSS_SPDM_DEBUG_CLK 197 -#define MMSS_SPDM_VFE1_CLK 198 -#define MMSS_SPDM_VFE0_CLK 199 -#define MMSS_SPDM_VIDEO_CORE_CLK 200 -#define MMSS_SPDM_AXI_CLK 201 -#define MMSS_SPDM_MDP_CLK 202 -#define MMSS_SPDM_JPEG0_CLK 203 -#define MMSS_SPDM_RM_AXI_CLK 204 -#define MMSS_SPDM_RM_MAXI_CLK 205 - -#define MMAGICAHB_BCR 0 -#define MMAGIC_CFG_BCR 1 -#define MISC_BCR 2 -#define BTO_BCR 3 -#define MMAGICAXI_BCR 4 -#define MMAGICMAXI_BCR 5 -#define DSA_BCR 6 -#define MMAGIC_CAMSS_BCR 7 -#define THROTTLE_CAMSS_BCR 8 -#define SMMU_VFE_BCR 9 -#define SMMU_CPP_BCR 10 -#define SMMU_JPEG_BCR 11 -#define MMAGIC_MDSS_BCR 12 -#define THROTTLE_MDSS_BCR 13 -#define SMMU_ROT_BCR 14 -#define SMMU_MDP_BCR 15 -#define MMAGIC_VIDEO_BCR 16 -#define THROTTLE_VIDEO_BCR 17 -#define SMMU_VIDEO_BCR 18 -#define MMAGIC_BIMC_BCR 19 -#define GPU_GX_BCR 20 -#define GPU_BCR 21 -#define GPU_AON_BCR 22 -#define VMEM_BCR 23 -#define MMSS_RBCPR_BCR 24 -#define VIDEO_BCR 25 -#define MDSS_BCR 26 -#define CAMSS_TOP_BCR 27 -#define CAMSS_AHB_BCR 28 -#define CAMSS_MICRO_BCR 29 -#define CAMSS_CCI_BCR 30 -#define CAMSS_PHY0_BCR 31 -#define CAMSS_PHY1_BCR 32 -#define CAMSS_PHY2_BCR 33 -#define CAMSS_CSIPHY0_3P_BCR 34 -#define CAMSS_CSIPHY1_3P_BCR 35 -#define CAMSS_CSIPHY2_3P_BCR 36 -#define CAMSS_JPEG_BCR 37 -#define CAMSS_VFE_BCR 38 -#define CAMSS_VFE0_BCR 39 -#define CAMSS_VFE1_BCR 40 -#define CAMSS_CSI_VFE0_BCR 41 -#define CAMSS_CSI_VFE1_BCR 42 -#define CAMSS_CPP_TOP_BCR 43 -#define CAMSS_CPP_BCR 44 -#define CAMSS_CSI0_BCR 45 -#define CAMSS_CSI0RDI_BCR 46 -#define CAMSS_CSI0PIX_BCR 47 -#define CAMSS_CSI1_BCR 48 -#define CAMSS_CSI1RDI_BCR 49 -#define CAMSS_CSI1PIX_BCR 50 -#define CAMSS_CSI2_BCR 51 -#define CAMSS_CSI2RDI_BCR 52 -#define CAMSS_CSI2PIX_BCR 53 -#define CAMSS_CSI3_BCR 54 -#define CAMSS_CSI3RDI_BCR 55 -#define CAMSS_CSI3PIX_BCR 56 -#define CAMSS_ISPIF_BCR 57 -#define FD_BCR 58 -#define MMSS_SPDM_RM_BCR 59 - -/* Indexes for GDSCs */ -#define MMAGIC_VIDEO_GDSC 0 -#define MMAGIC_MDSS_GDSC 1 -#define MMAGIC_CAMSS_GDSC 2 -#define GPU_GDSC 3 -#define VENUS_GDSC 4 -#define VENUS_CORE0_GDSC 5 -#define VENUS_CORE1_GDSC 6 -#define CAMSS_GDSC 7 -#define VFE0_GDSC 8 -#define VFE1_GDSC 9 -#define JPEG_GDSC 10 -#define CPP_GDSC 11 -#define FD_GDSC 12 -#define MDSS_GDSC 13 -#define GPU_GX_GDSC 14 -#define MMAGIC_BIMC_GDSC 15 - -#endif diff --git a/include/dt-bindings/clock/qcom,rpmcc.h b/include/dt-bindings/clock/qcom,rpmcc.h deleted file mode 100644 index 46309c9953b..00000000000 --- a/include/dt-bindings/clock/qcom,rpmcc.h +++ /dev/null @@ -1,174 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2015 Linaro Limited - */ - -#ifndef _DT_BINDINGS_CLK_MSM_RPMCC_H -#define _DT_BINDINGS_CLK_MSM_RPMCC_H - -/* RPM clocks */ -#define RPM_PXO_CLK 0 -#define RPM_PXO_A_CLK 1 -#define RPM_CXO_CLK 2 -#define RPM_CXO_A_CLK 3 -#define RPM_APPS_FABRIC_CLK 4 -#define RPM_APPS_FABRIC_A_CLK 5 -#define RPM_CFPB_CLK 6 -#define RPM_CFPB_A_CLK 7 -#define RPM_QDSS_CLK 8 -#define RPM_QDSS_A_CLK 9 -#define RPM_DAYTONA_FABRIC_CLK 10 -#define RPM_DAYTONA_FABRIC_A_CLK 11 -#define RPM_EBI1_CLK 12 -#define RPM_EBI1_A_CLK 13 -#define RPM_MM_FABRIC_CLK 14 -#define RPM_MM_FABRIC_A_CLK 15 -#define RPM_MMFPB_CLK 16 -#define RPM_MMFPB_A_CLK 17 -#define RPM_SYS_FABRIC_CLK 18 -#define RPM_SYS_FABRIC_A_CLK 19 -#define RPM_SFPB_CLK 20 -#define RPM_SFPB_A_CLK 21 -#define RPM_SMI_CLK 22 -#define RPM_SMI_A_CLK 23 -#define RPM_PLL4_CLK 24 -#define RPM_XO_D0 25 -#define RPM_XO_D1 26 -#define RPM_XO_A0 27 -#define RPM_XO_A1 28 -#define RPM_XO_A2 29 -#define RPM_NSS_FABRIC_0_CLK 30 -#define RPM_NSS_FABRIC_0_A_CLK 31 -#define RPM_NSS_FABRIC_1_CLK 32 -#define RPM_NSS_FABRIC_1_A_CLK 33 - -/* SMD RPM clocks */ -#define RPM_SMD_XO_CLK_SRC 0 -#define RPM_SMD_XO_A_CLK_SRC 1 -#define RPM_SMD_PCNOC_CLK 2 -#define RPM_SMD_PCNOC_A_CLK 3 -#define RPM_SMD_SNOC_CLK 4 -#define RPM_SMD_SNOC_A_CLK 5 -#define RPM_SMD_BIMC_CLK 6 -#define RPM_SMD_BIMC_A_CLK 7 -#define RPM_SMD_QDSS_CLK 8 -#define RPM_SMD_QDSS_A_CLK 9 -#define RPM_SMD_BB_CLK1 10 -#define RPM_SMD_BB_CLK1_A 11 -#define RPM_SMD_BB_CLK2 12 -#define RPM_SMD_BB_CLK2_A 13 -#define RPM_SMD_RF_CLK1 14 -#define RPM_SMD_RF_CLK1_A 15 -#define RPM_SMD_RF_CLK2 16 -#define RPM_SMD_RF_CLK2_A 17 -#define RPM_SMD_BB_CLK1_PIN 18 -#define RPM_SMD_BB_CLK1_A_PIN 19 -#define RPM_SMD_BB_CLK2_PIN 20 -#define RPM_SMD_BB_CLK2_A_PIN 21 -#define RPM_SMD_RF_CLK1_PIN 22 -#define RPM_SMD_RF_CLK1_A_PIN 23 -#define RPM_SMD_RF_CLK2_PIN 24 -#define RPM_SMD_RF_CLK2_A_PIN 25 -#define RPM_SMD_PNOC_CLK 26 -#define RPM_SMD_PNOC_A_CLK 27 -#define RPM_SMD_CNOC_CLK 28 -#define RPM_SMD_CNOC_A_CLK 29 -#define RPM_SMD_MMSSNOC_AHB_CLK 30 -#define RPM_SMD_MMSSNOC_AHB_A_CLK 31 -#define RPM_SMD_GFX3D_CLK_SRC 32 -#define RPM_SMD_GFX3D_A_CLK_SRC 33 -#define RPM_SMD_OCMEMGX_CLK 34 -#define RPM_SMD_OCMEMGX_A_CLK 35 -#define RPM_SMD_CXO_D0 36 -#define RPM_SMD_CXO_D0_A 37 -#define RPM_SMD_CXO_D1 38 -#define RPM_SMD_CXO_D1_A 39 -#define RPM_SMD_CXO_A0 40 -#define RPM_SMD_CXO_A0_A 41 -#define RPM_SMD_CXO_A1 42 -#define RPM_SMD_CXO_A1_A 43 -#define RPM_SMD_CXO_A2 44 -#define RPM_SMD_CXO_A2_A 45 -#define RPM_SMD_DIV_CLK1 46 -#define RPM_SMD_DIV_A_CLK1 47 -#define RPM_SMD_DIV_CLK2 48 -#define RPM_SMD_DIV_A_CLK2 49 -#define RPM_SMD_DIFF_CLK 50 -#define RPM_SMD_DIFF_A_CLK 51 -#define RPM_SMD_CXO_D0_PIN 52 -#define RPM_SMD_CXO_D0_A_PIN 53 -#define RPM_SMD_CXO_D1_PIN 54 -#define RPM_SMD_CXO_D1_A_PIN 55 -#define RPM_SMD_CXO_A0_PIN 56 -#define RPM_SMD_CXO_A0_A_PIN 57 -#define RPM_SMD_CXO_A1_PIN 58 -#define RPM_SMD_CXO_A1_A_PIN 59 -#define RPM_SMD_CXO_A2_PIN 60 -#define RPM_SMD_CXO_A2_A_PIN 61 -#define RPM_SMD_AGGR1_NOC_CLK 62 -#define RPM_SMD_AGGR1_NOC_A_CLK 63 -#define RPM_SMD_AGGR2_NOC_CLK 64 -#define RPM_SMD_AGGR2_NOC_A_CLK 65 -#define RPM_SMD_MMAXI_CLK 66 -#define RPM_SMD_MMAXI_A_CLK 67 -#define RPM_SMD_IPA_CLK 68 -#define RPM_SMD_IPA_A_CLK 69 -#define RPM_SMD_CE1_CLK 70 -#define RPM_SMD_CE1_A_CLK 71 -#define RPM_SMD_DIV_CLK3 72 -#define RPM_SMD_DIV_A_CLK3 73 -#define RPM_SMD_LN_BB_CLK 74 -#define RPM_SMD_LN_BB_A_CLK 75 -#define RPM_SMD_BIMC_GPU_CLK 76 -#define RPM_SMD_BIMC_GPU_A_CLK 77 -#define RPM_SMD_QPIC_CLK 78 -#define RPM_SMD_QPIC_CLK_A 79 -#define RPM_SMD_LN_BB_CLK1 80 -#define RPM_SMD_LN_BB_CLK1_A 81 -#define RPM_SMD_LN_BB_CLK2 82 -#define RPM_SMD_LN_BB_CLK2_A 83 -#define RPM_SMD_LN_BB_CLK3_PIN 84 -#define RPM_SMD_LN_BB_CLK3_A_PIN 85 -#define RPM_SMD_RF_CLK3 86 -#define RPM_SMD_RF_CLK3_A 87 -#define RPM_SMD_RF_CLK3_PIN 88 -#define RPM_SMD_RF_CLK3_A_PIN 89 -#define RPM_SMD_MMSSNOC_AXI_CLK 90 -#define RPM_SMD_MMSSNOC_AXI_CLK_A 91 -#define RPM_SMD_CNOC_PERIPH_CLK 92 -#define RPM_SMD_CNOC_PERIPH_A_CLK 93 -#define RPM_SMD_LN_BB_CLK3 94 -#define RPM_SMD_LN_BB_CLK3_A 95 -#define RPM_SMD_LN_BB_CLK1_PIN 96 -#define RPM_SMD_LN_BB_CLK1_A_PIN 97 -#define RPM_SMD_LN_BB_CLK2_PIN 98 -#define RPM_SMD_LN_BB_CLK2_A_PIN 99 -#define RPM_SMD_SYSMMNOC_CLK 100 -#define RPM_SMD_SYSMMNOC_A_CLK 101 -#define RPM_SMD_CE2_CLK 102 -#define RPM_SMD_CE2_A_CLK 103 -#define RPM_SMD_CE3_CLK 104 -#define RPM_SMD_CE3_A_CLK 105 -#define RPM_SMD_QUP_CLK 106 -#define RPM_SMD_QUP_A_CLK 107 -#define RPM_SMD_MMRT_CLK 108 -#define RPM_SMD_MMRT_A_CLK 109 -#define RPM_SMD_MMNRT_CLK 110 -#define RPM_SMD_MMNRT_A_CLK 111 -#define RPM_SMD_SNOC_PERIPH_CLK 112 -#define RPM_SMD_SNOC_PERIPH_A_CLK 113 -#define RPM_SMD_SNOC_LPASS_CLK 114 -#define RPM_SMD_SNOC_LPASS_A_CLK 115 -#define RPM_SMD_HWKM_CLK 116 -#define RPM_SMD_HWKM_A_CLK 117 -#define RPM_SMD_PKA_CLK 118 -#define RPM_SMD_PKA_A_CLK 119 -#define RPM_SMD_CPUSS_GNOC_CLK 120 -#define RPM_SMD_CPUSS_GNOC_A_CLK 121 -#define RPM_SMD_MSS_CFG_AHB_CLK 122 -#define RPM_SMD_MSS_CFG_AHB_A_CLK 123 -#define RPM_SMD_BIMC_FREQ_LOG 124 -#define RPM_SMD_LN_BB_CLK_PIN 125 -#define RPM_SMD_LN_BB_A_CLK_PIN 126 - -#endif diff --git a/include/dt-bindings/clock/qcom,rpmh.h b/include/dt-bindings/clock/qcom,rpmh.h deleted file mode 100644 index bf5b59b1008..00000000000 --- a/include/dt-bindings/clock/qcom,rpmh.h +++ /dev/null @@ -1,36 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved. */ - -#ifndef _DT_BINDINGS_CLK_MSM_RPMH_H -#define _DT_BINDINGS_CLK_MSM_RPMH_H - -/* RPMh controlled clocks */ -#define RPMH_CXO_CLK 0 -#define RPMH_CXO_CLK_A 1 -#define RPMH_LN_BB_CLK2 2 -#define RPMH_LN_BB_CLK2_A 3 -#define RPMH_LN_BB_CLK3 4 -#define RPMH_LN_BB_CLK3_A 5 -#define RPMH_RF_CLK1 6 -#define RPMH_RF_CLK1_A 7 -#define RPMH_RF_CLK2 8 -#define RPMH_RF_CLK2_A 9 -#define RPMH_RF_CLK3 10 -#define RPMH_RF_CLK3_A 11 -#define RPMH_IPA_CLK 12 -#define RPMH_LN_BB_CLK1 13 -#define RPMH_LN_BB_CLK1_A 14 -#define RPMH_CE_CLK 15 -#define RPMH_QPIC_CLK 16 -#define RPMH_DIV_CLK1 17 -#define RPMH_DIV_CLK1_A 18 -#define RPMH_RF_CLK4 19 -#define RPMH_RF_CLK4_A 20 -#define RPMH_RF_CLK5 21 -#define RPMH_RF_CLK5_A 22 -#define RPMH_PKA_CLK 23 -#define RPMH_HWKM_CLK 24 -#define RPMH_QLINK_CLK 25 -#define RPMH_QLINK_CLK_A 26 - -#endif diff --git a/include/dt-bindings/clock/qcom,turingcc-qcs404.h b/include/dt-bindings/clock/qcom,turingcc-qcs404.h deleted file mode 100644 index 838faef57c6..00000000000 --- a/include/dt-bindings/clock/qcom,turingcc-qcs404.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2019, Linaro Ltd - */ - -#ifndef _DT_BINDINGS_CLK_TURING_QCS404_H -#define _DT_BINDINGS_CLK_TURING_QCS404_H - -#define TURING_Q6SS_Q6_AXIM_CLK 0 -#define TURING_Q6SS_AHBM_AON_CLK 1 -#define TURING_WRAPPER_AON_CLK 2 -#define TURING_Q6SS_AHBS_AON_CLK 3 -#define TURING_WRAPPER_QOS_AHBS_AON_CLK 4 - -#endif diff --git a/include/dt-bindings/clock/qcom,videocc-sdm845.h b/include/dt-bindings/clock/qcom,videocc-sdm845.h deleted file mode 100644 index 1b868165e8c..00000000000 --- a/include/dt-bindings/clock/qcom,videocc-sdm845.h +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_SDM_VIDEO_CC_SDM845_H -#define _DT_BINDINGS_CLK_SDM_VIDEO_CC_SDM845_H - -/* VIDEO_CC clock registers */ -#define VIDEO_CC_APB_CLK 0 -#define VIDEO_CC_AT_CLK 1 -#define VIDEO_CC_QDSS_TRIG_CLK 2 -#define VIDEO_CC_QDSS_TSCTR_DIV8_CLK 3 -#define VIDEO_CC_VCODEC0_AXI_CLK 4 -#define VIDEO_CC_VCODEC0_CORE_CLK 5 -#define VIDEO_CC_VCODEC1_AXI_CLK 6 -#define VIDEO_CC_VCODEC1_CORE_CLK 7 -#define VIDEO_CC_VENUS_AHB_CLK 8 -#define VIDEO_CC_VENUS_CLK_SRC 9 -#define VIDEO_CC_VENUS_CTL_AXI_CLK 10 -#define VIDEO_CC_VENUS_CTL_CORE_CLK 11 -#define VIDEO_PLL0 12 - -/* VIDEO_CC Resets */ -#define VIDEO_CC_VENUS_BCR 0 -#define VIDEO_CC_VCODEC0_BCR 1 -#define VIDEO_CC_VCODEC1_BCR 2 -#define VIDEO_CC_INTERFACE_BCR 3 - -/* VIDEO_CC GDSCRs */ -#define VENUS_GDSC 0 -#define VCODEC0_GDSC 1 -#define VCODEC1_GDSC 2 - -#endif diff --git a/include/dt-bindings/clock/starfive,jh7110-crg.h b/include/dt-bindings/clock/starfive,jh7110-crg.h deleted file mode 100644 index b51e3829ff4..00000000000 --- a/include/dt-bindings/clock/starfive,jh7110-crg.h +++ /dev/null @@ -1,258 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2022 StarFive Technology Co., Ltd. - * - * Author: Yanhong Wang <yanhong.wang@starfivetech.com> - */ - -#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ -#define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ - -#define JH7110_SYSCLK_PLL0_OUT 0 -#define JH7110_SYSCLK_PLL1_OUT 1 -#define JH7110_SYSCLK_PLL2_OUT 2 -#define JH7110_PLLCLK_END 3 - -#define JH7110_SYSCLK_CPU_ROOT 0 -#define JH7110_SYSCLK_CPU_CORE 1 -#define JH7110_SYSCLK_CPU_BUS 2 -#define JH7110_SYSCLK_GPU_ROOT 3 -#define JH7110_SYSCLK_PERH_ROOT 4 -#define JH7110_SYSCLK_BUS_ROOT 5 -#define JH7110_SYSCLK_NOCSTG_BUS 6 -#define JH7110_SYSCLK_AXI_CFG0 7 -#define JH7110_SYSCLK_STG_AXIAHB 8 -#define JH7110_SYSCLK_AHB0 9 -#define JH7110_SYSCLK_AHB1 10 -#define JH7110_SYSCLK_APB_BUS 11 -#define JH7110_SYSCLK_APB0 12 -#define JH7110_SYSCLK_PLL0_DIV2 13 -#define JH7110_SYSCLK_PLL1_DIV2 14 -#define JH7110_SYSCLK_PLL2_DIV2 15 -#define JH7110_SYSCLK_AUDIO_ROOT 16 -#define JH7110_SYSCLK_MCLK_INNER 17 -#define JH7110_SYSCLK_MCLK 18 -#define JH7110_SYSCLK_MCLK_OUT 19 -#define JH7110_SYSCLK_ISP_2X 20 -#define JH7110_SYSCLK_ISP_AXI 21 -#define JH7110_SYSCLK_GCLK0 22 -#define JH7110_SYSCLK_GCLK1 23 -#define JH7110_SYSCLK_GCLK2 24 -#define JH7110_SYSCLK_CORE 25 -#define JH7110_SYSCLK_CORE1 26 -#define JH7110_SYSCLK_CORE2 27 -#define JH7110_SYSCLK_CORE3 28 -#define JH7110_SYSCLK_CORE4 29 -#define JH7110_SYSCLK_DEBUG 30 -#define JH7110_SYSCLK_RTC_TOGGLE 31 -#define JH7110_SYSCLK_TRACE0 32 -#define JH7110_SYSCLK_TRACE1 33 -#define JH7110_SYSCLK_TRACE2 34 -#define JH7110_SYSCLK_TRACE3 35 -#define JH7110_SYSCLK_TRACE4 36 -#define JH7110_SYSCLK_TRACE_COM 37 -#define JH7110_SYSCLK_NOC_BUS_CPU_AXI 38 -#define JH7110_SYSCLK_NOC_BUS_AXICFG0_AXI 39 -#define JH7110_SYSCLK_OSC_DIV2 40 -#define JH7110_SYSCLK_PLL1_DIV4 41 -#define JH7110_SYSCLK_PLL1_DIV8 42 -#define JH7110_SYSCLK_DDR_BUS 43 -#define JH7110_SYSCLK_DDR_AXI 44 -#define JH7110_SYSCLK_GPU_CORE 45 -#define JH7110_SYSCLK_GPU_CORE_CLK 46 -#define JH7110_SYSCLK_GPU_SYS_CLK 47 -#define JH7110_SYSCLK_GPU_APB 48 -#define JH7110_SYSCLK_GPU_RTC_TOGGLE 49 -#define JH7110_SYSCLK_NOC_BUS_GPU_AXI 50 -#define JH7110_SYSCLK_ISP_TOP_CLK_ISPCORE_2X 51 -#define JH7110_SYSCLK_ISP_TOP_CLK_ISP_AXI 52 -#define JH7110_SYSCLK_NOC_BUS_ISP_AXI 53 -#define JH7110_SYSCLK_HIFI4_CORE 54 -#define JH7110_SYSCLK_HIFI4_AXI 55 -#define JH7110_SYSCLK_AXI_CFG1_DEC_MAIN 56 -#define JH7110_SYSCLK_AXI_CFG1_DEC_AHB 57 -#define JH7110_SYSCLK_VOUT_SRC 58 -#define JH7110_SYSCLK_VOUT_AXI 59 -#define JH7110_SYSCLK_NOC_BUS_DISP_AXI 60 -#define JH7110_SYSCLK_VOUT_TOP_CLK_VOUT_AHB 61 -#define JH7110_SYSCLK_VOUT_TOP_CLK_VOUT_AXI 62 -#define JH7110_SYSCLK_VOUT_TOP_CLK_HDMITX0_MCLK 63 -#define JH7110_SYSCLK_VOUT_TOP_CLK_MIPIPHY_REF 64 -#define JH7110_SYSCLK_JPEGC_AXI 65 -#define JH7110_SYSCLK_CODAJ12_AXI 66 -#define JH7110_SYSCLK_CODAJ12_CORE 67 -#define JH7110_SYSCLK_CODAJ12_APB 68 -#define JH7110_SYSCLK_VDEC_AXI 69 -#define JH7110_SYSCLK_WAVE511_AXI 70 -#define JH7110_SYSCLK_WAVE511_BPU 71 -#define JH7110_SYSCLK_WAVE511_VCE 72 -#define JH7110_SYSCLK_WAVE511_APB 73 -#define JH7110_SYSCLK_VDEC_JPG_ARB_JPG 74 -#define JH7110_SYSCLK_VDEC_JPG_ARB_MAIN 75 -#define JH7110_SYSCLK_NOC_BUS_VDEC_AXI 76 -#define JH7110_SYSCLK_VENC_AXI 77 -#define JH7110_SYSCLK_WAVE420L_AXI 78 -#define JH7110_SYSCLK_WAVE420L_BPU 79 -#define JH7110_SYSCLK_WAVE420L_VCE 80 -#define JH7110_SYSCLK_WAVE420L_APB 81 -#define JH7110_SYSCLK_NOC_BUS_VENC_AXI 82 -#define JH7110_SYSCLK_AXI_CFG0_DEC_MAIN_DIV 83 -#define JH7110_SYSCLK_AXI_CFG0_DEC_MAIN 84 -#define JH7110_SYSCLK_AXI_CFG0_DEC_HIFI4 85 -#define JH7110_SYSCLK_AXIMEM2_AXI 86 -#define JH7110_SYSCLK_QSPI_AHB 87 -#define JH7110_SYSCLK_QSPI_APB 88 -#define JH7110_SYSCLK_QSPI_REF_SRC 89 -#define JH7110_SYSCLK_QSPI_REF 90 -#define JH7110_SYSCLK_SDIO0_AHB 91 -#define JH7110_SYSCLK_SDIO1_AHB 92 -#define JH7110_SYSCLK_SDIO0_SDCARD 93 -#define JH7110_SYSCLK_SDIO1_SDCARD 94 -#define JH7110_SYSCLK_USB_125M 95 -#define JH7110_SYSCLK_NOC_BUS_STG_AXI 96 -#define JH7110_SYSCLK_GMAC1_AHB 97 -#define JH7110_SYSCLK_GMAC1_AXI 98 -#define JH7110_SYSCLK_GMAC_SRC 99 -#define JH7110_SYSCLK_GMAC1_GTXCLK 100 -#define JH7110_SYSCLK_GMAC1_RMII_RTX 101 -#define JH7110_SYSCLK_GMAC1_PTP 102 -#define JH7110_SYSCLK_GMAC1_RX 103 -#define JH7110_SYSCLK_GMAC1_RX_INV 104 -#define JH7110_SYSCLK_GMAC1_TX 105 -#define JH7110_SYSCLK_GMAC1_TX_INV 106 -#define JH7110_SYSCLK_GMAC1_GTXC 107 -#define JH7110_SYSCLK_GMAC0_GTXCLK 108 -#define JH7110_SYSCLK_GMAC0_PTP 109 -#define JH7110_SYSCLK_GMAC_PHY 110 -#define JH7110_SYSCLK_GMAC0_GTXC 111 -#define JH7110_SYSCLK_IOMUX_APB 112 -#define JH7110_SYSCLK_MAILBOX 113 -#define JH7110_SYSCLK_INT_CTRL_APB 114 -#define JH7110_SYSCLK_CAN0_APB 115 -#define JH7110_SYSCLK_CAN0_TIMER 116 -#define JH7110_SYSCLK_CAN0_CAN 117 -#define JH7110_SYSCLK_CAN1_APB 118 -#define JH7110_SYSCLK_CAN1_TIMER 119 -#define JH7110_SYSCLK_CAN1_CAN 120 -#define JH7110_SYSCLK_PWM_APB 121 -#define JH7110_SYSCLK_WDT_APB 122 -#define JH7110_SYSCLK_WDT_CORE 123 -#define JH7110_SYSCLK_TIMER_APB 124 -#define JH7110_SYSCLK_TIMER0 125 -#define JH7110_SYSCLK_TIMER1 126 -#define JH7110_SYSCLK_TIMER2 127 -#define JH7110_SYSCLK_TIMER3 128 -#define JH7110_SYSCLK_TEMP_APB 129 -#define JH7110_SYSCLK_TEMP_CORE 130 -#define JH7110_SYSCLK_SPI0_APB 131 -#define JH7110_SYSCLK_SPI1_APB 132 -#define JH7110_SYSCLK_SPI2_APB 133 -#define JH7110_SYSCLK_SPI3_APB 134 -#define JH7110_SYSCLK_SPI4_APB 135 -#define JH7110_SYSCLK_SPI5_APB 136 -#define JH7110_SYSCLK_SPI6_APB 137 -#define JH7110_SYSCLK_I2C0_APB 138 -#define JH7110_SYSCLK_I2C1_APB 139 -#define JH7110_SYSCLK_I2C2_APB 140 -#define JH7110_SYSCLK_I2C3_APB 141 -#define JH7110_SYSCLK_I2C4_APB 142 -#define JH7110_SYSCLK_I2C5_APB 143 -#define JH7110_SYSCLK_I2C6_APB 144 -#define JH7110_SYSCLK_UART0_APB 145 -#define JH7110_SYSCLK_UART0_CORE 146 -#define JH7110_SYSCLK_UART1_APB 147 -#define JH7110_SYSCLK_UART1_CORE 148 -#define JH7110_SYSCLK_UART2_APB 149 -#define JH7110_SYSCLK_UART2_CORE 150 -#define JH7110_SYSCLK_UART3_APB 151 -#define JH7110_SYSCLK_UART3_CORE 152 -#define JH7110_SYSCLK_UART4_APB 153 -#define JH7110_SYSCLK_UART4_CORE 154 -#define JH7110_SYSCLK_UART5_APB 155 -#define JH7110_SYSCLK_UART5_CORE 156 -#define JH7110_SYSCLK_PWMDAC_APB 157 -#define JH7110_SYSCLK_PWMDAC_CORE 158 -#define JH7110_SYSCLK_SPDIF_APB 159 -#define JH7110_SYSCLK_SPDIF_CORE 160 -#define JH7110_SYSCLK_I2STX0_APB 161 -#define JH7110_SYSCLK_I2STX0_BCLK_MST 162 -#define JH7110_SYSCLK_I2STX0_BCLK_MST_INV 163 -#define JH7110_SYSCLK_I2STX0_LRCK_MST 164 -#define JH7110_SYSCLK_I2STX0_BCLK 165 -#define JH7110_SYSCLK_I2STX0_BCLK_INV 166 -#define JH7110_SYSCLK_I2STX0_LRCK 167 -#define JH7110_SYSCLK_I2STX1_APB 168 -#define JH7110_SYSCLK_I2STX1_BCLK_MST 169 -#define JH7110_SYSCLK_I2STX1_BCLK_MST_INV 170 -#define JH7110_SYSCLK_I2STX1_LRCK_MST 171 -#define JH7110_SYSCLK_I2STX1_BCLK 172 -#define JH7110_SYSCLK_I2STX1_BCLK_INV 173 -#define JH7110_SYSCLK_I2STX1_LRCK 174 -#define JH7110_SYSCLK_I2SRX_APB 175 -#define JH7110_SYSCLK_I2SRX_BCLK_MST 176 -#define JH7110_SYSCLK_I2SRX_BCLK_MST_INV 177 -#define JH7110_SYSCLK_I2SRX_LRCK_MST 178 -#define JH7110_SYSCLK_I2SRX_BCLK 179 -#define JH7110_SYSCLK_I2SRX_BCLK_INV 180 -#define JH7110_SYSCLK_I2SRX_LRCK 181 -#define JH7110_SYSCLK_PDM_DMIC 182 -#define JH7110_SYSCLK_PDM_APB 183 -#define JH7110_SYSCLK_TDM_AHB 184 -#define JH7110_SYSCLK_TDM_APB 185 -#define JH7110_SYSCLK_TDM_INTERNAL 186 -#define JH7110_SYSCLK_TDM_CLK_TDM 187 -#define JH7110_SYSCLK_TDM_CLK_TDM_N 188 -#define JH7110_SYSCLK_JTAG_CERTIFICATION_TRNG 189 - -#define JH7110_SYSCLK_END 190 - -#define JH7110_AONCLK_OSC_DIV4 0 -#define JH7110_AONCLK_APB_FUNC 1 -#define JH7110_AONCLK_GMAC0_AHB 2 -#define JH7110_AONCLK_GMAC0_AXI 3 -#define JH7110_AONCLK_GMAC0_RMII_RTX 4 -#define JH7110_AONCLK_GMAC0_TX 5 -#define JH7110_AONCLK_GMAC0_TX_INV 6 -#define JH7110_AONCLK_GMAC0_RX 7 -#define JH7110_AONCLK_GMAC0_RX_INV 8 -#define JH7110_AONCLK_OTPC_APB 9 -#define JH7110_AONCLK_RTC_APB 10 -#define JH7110_AONCLK_RTC_INTERNAL 11 -#define JH7110_AONCLK_RTC_32K 12 -#define JH7110_AONCLK_RTC_CAL 13 - -#define JH7110_AONCLK_END 14 - -#define JH7110_STGCLK_HIFI4_CORE 0 -#define JH7110_STGCLK_USB_APB 1 -#define JH7110_STGCLK_USB_UTMI_APB 2 -#define JH7110_STGCLK_USB_AXI 3 -#define JH7110_STGCLK_USB_LPM 4 -#define JH7110_STGCLK_USB_STB 5 -#define JH7110_STGCLK_USB_APP_125 6 -#define JH7110_STGCLK_USB_REFCLK 7 -#define JH7110_STGCLK_PCIE0_AXI 8 -#define JH7110_STGCLK_PCIE0_APB 9 -#define JH7110_STGCLK_PCIE0_TL 10 -#define JH7110_STGCLK_PCIE1_AXI 11 -#define JH7110_STGCLK_PCIE1_APB 12 -#define JH7110_STGCLK_PCIE1_TL 13 -#define JH7110_STGCLK_PCIE01_MAIN 14 -#define JH7110_STGCLK_SEC_HCLK 15 -#define JH7110_STGCLK_SEC_MISCAHB 16 -#define JH7110_STGCLK_MTRX_GRP0_MAIN 17 -#define JH7110_STGCLK_MTRX_GRP0_BUS 18 -#define JH7110_STGCLK_MTRX_GRP0_STG 19 -#define JH7110_STGCLK_MTRX_GRP1_MAIN 20 -#define JH7110_STGCLK_MTRX_GRP1_BUS 21 -#define JH7110_STGCLK_MTRX_GRP1_STG 22 -#define JH7110_STGCLK_MTRX_GRP1_HIFI 23 -#define JH7110_STGCLK_E2_RTC 24 -#define JH7110_STGCLK_E2_CORE 25 -#define JH7110_STGCLK_E2_DBG 26 -#define JH7110_STGCLK_DMA1P_AXI 27 -#define JH7110_STGCLK_DMA1P_AHB 28 - -#define JH7110_STGCLK_END 29 - -#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ */ diff --git a/include/dt-bindings/dma/qcom-gpi.h b/include/dt-bindings/dma/qcom-gpi.h deleted file mode 100644 index ebda2a37f52..00000000000 --- a/include/dt-bindings/dma/qcom-gpi.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ -/* Copyright (c) 2020, Linaro Ltd. */ - -#ifndef __DT_BINDINGS_DMA_QCOM_GPI_H__ -#define __DT_BINDINGS_DMA_QCOM_GPI_H__ - -#define QCOM_GPI_SPI 1 -#define QCOM_GPI_UART 2 -#define QCOM_GPI_I2C 3 - -#endif /* __DT_BINDINGS_DMA_QCOM_GPI_H__ */ diff --git a/include/dt-bindings/firmware/qcom,scm.h b/include/dt-bindings/firmware/qcom,scm.h deleted file mode 100644 index 6de8b08e1e7..00000000000 --- a/include/dt-bindings/firmware/qcom,scm.h +++ /dev/null @@ -1,39 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ -/* - * Copyright (c) 2010-2015, 2018-2019 The Linux Foundation. All rights reserved. - * Copyright (C) 2015 Linaro Ltd. - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. - */ - -#ifndef _DT_BINDINGS_FIRMWARE_QCOM_SCM_H -#define _DT_BINDINGS_FIRMWARE_QCOM_SCM_H - -#define QCOM_SCM_VMID_TZ 0x1 -#define QCOM_SCM_VMID_HLOS 0x3 -#define QCOM_SCM_VMID_SSC_Q6 0x5 -#define QCOM_SCM_VMID_ADSP_Q6 0x6 -#define QCOM_SCM_VMID_CP_TOUCH 0x8 -#define QCOM_SCM_VMID_CP_BITSTREAM 0x9 -#define QCOM_SCM_VMID_CP_PIXEL 0xA -#define QCOM_SCM_VMID_CP_NON_PIXEL 0xB -#define QCOM_SCM_VMID_CP_CAMERA 0xD -#define QCOM_SCM_VMID_HLOS_FREE 0xE -#define QCOM_SCM_VMID_MSS_MSA 0xF -#define QCOM_SCM_VMID_MSS_NONMSA 0x10 -#define QCOM_SCM_VMID_CP_SEC_DISPLAY 0x11 -#define QCOM_SCM_VMID_CP_APP 0x12 -#define QCOM_SCM_VMID_LPASS 0x16 -#define QCOM_SCM_VMID_WLAN 0x18 -#define QCOM_SCM_VMID_WLAN_CE 0x19 -#define QCOM_SCM_VMID_CP_SPSS_SP 0x1A -#define QCOM_SCM_VMID_CP_CAMERA_PREVIEW 0x1D -#define QCOM_SCM_VMID_CDSP 0x1E -#define QCOM_SCM_VMID_CP_SPSS_SP_SHARED 0x22 -#define QCOM_SCM_VMID_CP_SPSS_HLOS_SHARED 0x24 -#define QCOM_SCM_VMID_ADSP_HEAP 0x25 -#define QCOM_SCM_VMID_CP_CDSP 0x2A -#define QCOM_SCM_VMID_NAV 0x2B -#define QCOM_SCM_VMID_TVM 0x2D -#define QCOM_SCM_VMID_OEMVM 0x31 - -#endif diff --git a/include/dt-bindings/gpio/meson-a1-gpio.h b/include/dt-bindings/gpio/meson-a1-gpio.h deleted file mode 100644 index 40e57a5ff1d..00000000000 --- a/include/dt-bindings/gpio/meson-a1-gpio.h +++ /dev/null @@ -1,73 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * Copyright (c) 2019 Amlogic, Inc. All rights reserved. - * Author: Qianggui Song <qianggui.song@amlogic.com> - */ - -#ifndef _DT_BINDINGS_MESON_A1_GPIO_H -#define _DT_BINDINGS_MESON_A1_GPIO_H - -#define GPIOP_0 0 -#define GPIOP_1 1 -#define GPIOP_2 2 -#define GPIOP_3 3 -#define GPIOP_4 4 -#define GPIOP_5 5 -#define GPIOP_6 6 -#define GPIOP_7 7 -#define GPIOP_8 8 -#define GPIOP_9 9 -#define GPIOP_10 10 -#define GPIOP_11 11 -#define GPIOP_12 12 -#define GPIOB_0 13 -#define GPIOB_1 14 -#define GPIOB_2 15 -#define GPIOB_3 16 -#define GPIOB_4 17 -#define GPIOB_5 18 -#define GPIOB_6 19 -#define GPIOX_0 20 -#define GPIOX_1 21 -#define GPIOX_2 22 -#define GPIOX_3 23 -#define GPIOX_4 24 -#define GPIOX_5 25 -#define GPIOX_6 26 -#define GPIOX_7 27 -#define GPIOX_8 28 -#define GPIOX_9 29 -#define GPIOX_10 30 -#define GPIOX_11 31 -#define GPIOX_12 32 -#define GPIOX_13 33 -#define GPIOX_14 34 -#define GPIOX_15 35 -#define GPIOX_16 36 -#define GPIOF_0 37 -#define GPIOF_1 38 -#define GPIOF_2 39 -#define GPIOF_3 40 -#define GPIOF_4 41 -#define GPIOF_5 42 -#define GPIOF_6 43 -#define GPIOF_7 44 -#define GPIOF_8 45 -#define GPIOF_9 46 -#define GPIOF_10 47 -#define GPIOF_11 48 -#define GPIOF_12 49 -#define GPIOA_0 50 -#define GPIOA_1 51 -#define GPIOA_2 52 -#define GPIOA_3 53 -#define GPIOA_4 54 -#define GPIOA_5 55 -#define GPIOA_6 56 -#define GPIOA_7 57 -#define GPIOA_8 58 -#define GPIOA_9 59 -#define GPIOA_10 60 -#define GPIOA_11 61 - -#endif /* _DT_BINDINGS_MESON_A1_GPIO_H */ diff --git a/include/dt-bindings/iio/qcom,spmi-vadc.h b/include/dt-bindings/iio/qcom,spmi-vadc.h deleted file mode 100644 index 08adfe25964..00000000000 --- a/include/dt-bindings/iio/qcom,spmi-vadc.h +++ /dev/null @@ -1,300 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2012-2014,2018,2020 The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_H -#define _DT_BINDINGS_QCOM_SPMI_VADC_H - -/* Voltage ADC channels */ -#define VADC_USBIN 0x00 -#define VADC_DCIN 0x01 -#define VADC_VCHG_SNS 0x02 -#define VADC_SPARE1_03 0x03 -#define VADC_USB_ID_MV 0x04 -#define VADC_VCOIN 0x05 -#define VADC_VBAT_SNS 0x06 -#define VADC_VSYS 0x07 -#define VADC_DIE_TEMP 0x08 -#define VADC_REF_625MV 0x09 -#define VADC_REF_1250MV 0x0a -#define VADC_CHG_TEMP 0x0b -#define VADC_SPARE1 0x0c -#define VADC_SPARE2 0x0d -#define VADC_GND_REF 0x0e -#define VADC_VDD_VADC 0x0f - -#define VADC_P_MUX1_1_1 0x10 -#define VADC_P_MUX2_1_1 0x11 -#define VADC_P_MUX3_1_1 0x12 -#define VADC_P_MUX4_1_1 0x13 -#define VADC_P_MUX5_1_1 0x14 -#define VADC_P_MUX6_1_1 0x15 -#define VADC_P_MUX7_1_1 0x16 -#define VADC_P_MUX8_1_1 0x17 -#define VADC_P_MUX9_1_1 0x18 -#define VADC_P_MUX10_1_1 0x19 -#define VADC_P_MUX11_1_1 0x1a -#define VADC_P_MUX12_1_1 0x1b -#define VADC_P_MUX13_1_1 0x1c -#define VADC_P_MUX14_1_1 0x1d -#define VADC_P_MUX15_1_1 0x1e -#define VADC_P_MUX16_1_1 0x1f - -#define VADC_P_MUX1_1_3 0x20 -#define VADC_P_MUX2_1_3 0x21 -#define VADC_P_MUX3_1_3 0x22 -#define VADC_P_MUX4_1_3 0x23 -#define VADC_P_MUX5_1_3 0x24 -#define VADC_P_MUX6_1_3 0x25 -#define VADC_P_MUX7_1_3 0x26 -#define VADC_P_MUX8_1_3 0x27 -#define VADC_P_MUX9_1_3 0x28 -#define VADC_P_MUX10_1_3 0x29 -#define VADC_P_MUX11_1_3 0x2a -#define VADC_P_MUX12_1_3 0x2b -#define VADC_P_MUX13_1_3 0x2c -#define VADC_P_MUX14_1_3 0x2d -#define VADC_P_MUX15_1_3 0x2e -#define VADC_P_MUX16_1_3 0x2f - -#define VADC_LR_MUX1_BAT_THERM 0x30 -#define VADC_LR_MUX2_BAT_ID 0x31 -#define VADC_LR_MUX3_XO_THERM 0x32 -#define VADC_LR_MUX4_AMUX_THM1 0x33 -#define VADC_LR_MUX5_AMUX_THM2 0x34 -#define VADC_LR_MUX6_AMUX_THM3 0x35 -#define VADC_LR_MUX7_HW_ID 0x36 -#define VADC_LR_MUX8_AMUX_THM4 0x37 -#define VADC_LR_MUX9_AMUX_THM5 0x38 -#define VADC_LR_MUX10_USB_ID 0x39 -#define VADC_AMUX_PU1 0x3a -#define VADC_AMUX_PU2 0x3b -#define VADC_LR_MUX3_BUF_XO_THERM 0x3c - -#define VADC_LR_MUX1_PU1_BAT_THERM 0x70 -#define VADC_LR_MUX2_PU1_BAT_ID 0x71 -#define VADC_LR_MUX3_PU1_XO_THERM 0x72 -#define VADC_LR_MUX4_PU1_AMUX_THM1 0x73 -#define VADC_LR_MUX5_PU1_AMUX_THM2 0x74 -#define VADC_LR_MUX6_PU1_AMUX_THM3 0x75 -#define VADC_LR_MUX7_PU1_AMUX_HW_ID 0x76 -#define VADC_LR_MUX8_PU1_AMUX_THM4 0x77 -#define VADC_LR_MUX9_PU1_AMUX_THM5 0x78 -#define VADC_LR_MUX10_PU1_AMUX_USB_ID 0x79 -#define VADC_LR_MUX3_BUF_PU1_XO_THERM 0x7c - -#define VADC_LR_MUX1_PU2_BAT_THERM 0xb0 -#define VADC_LR_MUX2_PU2_BAT_ID 0xb1 -#define VADC_LR_MUX3_PU2_XO_THERM 0xb2 -#define VADC_LR_MUX4_PU2_AMUX_THM1 0xb3 -#define VADC_LR_MUX5_PU2_AMUX_THM2 0xb4 -#define VADC_LR_MUX6_PU2_AMUX_THM3 0xb5 -#define VADC_LR_MUX7_PU2_AMUX_HW_ID 0xb6 -#define VADC_LR_MUX8_PU2_AMUX_THM4 0xb7 -#define VADC_LR_MUX9_PU2_AMUX_THM5 0xb8 -#define VADC_LR_MUX10_PU2_AMUX_USB_ID 0xb9 -#define VADC_LR_MUX3_BUF_PU2_XO_THERM 0xbc - -#define VADC_LR_MUX1_PU1_PU2_BAT_THERM 0xf0 -#define VADC_LR_MUX2_PU1_PU2_BAT_ID 0xf1 -#define VADC_LR_MUX3_PU1_PU2_XO_THERM 0xf2 -#define VADC_LR_MUX4_PU1_PU2_AMUX_THM1 0xf3 -#define VADC_LR_MUX5_PU1_PU2_AMUX_THM2 0xf4 -#define VADC_LR_MUX6_PU1_PU2_AMUX_THM3 0xf5 -#define VADC_LR_MUX7_PU1_PU2_AMUX_HW_ID 0xf6 -#define VADC_LR_MUX8_PU1_PU2_AMUX_THM4 0xf7 -#define VADC_LR_MUX9_PU1_PU2_AMUX_THM5 0xf8 -#define VADC_LR_MUX10_PU1_PU2_AMUX_USB_ID 0xf9 -#define VADC_LR_MUX3_BUF_PU1_PU2_XO_THERM 0xfc - -/* ADC channels for SPMI PMIC5 */ - -#define ADC5_REF_GND 0x00 -#define ADC5_1P25VREF 0x01 -#define ADC5_VREF_VADC 0x02 -#define ADC5_VREF_VADC5_DIV_3 0x82 -#define ADC5_VPH_PWR 0x83 -#define ADC5_VBAT_SNS 0x84 -#define ADC5_VCOIN 0x85 -#define ADC5_DIE_TEMP 0x06 -#define ADC5_USB_IN_I 0x07 -#define ADC5_USB_IN_V_16 0x08 -#define ADC5_CHG_TEMP 0x09 -#define ADC5_BAT_THERM 0x0a -#define ADC5_BAT_ID 0x0b -#define ADC5_XO_THERM 0x0c -#define ADC5_AMUX_THM1 0x0d -#define ADC5_AMUX_THM2 0x0e -#define ADC5_AMUX_THM3 0x0f -#define ADC5_AMUX_THM4 0x10 -#define ADC5_AMUX_THM5 0x11 -#define ADC5_GPIO1 0x12 -#define ADC5_GPIO2 0x13 -#define ADC5_GPIO3 0x14 -#define ADC5_GPIO4 0x15 -#define ADC5_GPIO5 0x16 -#define ADC5_GPIO6 0x17 -#define ADC5_GPIO7 0x18 -#define ADC5_SBUx 0x99 -#define ADC5_MID_CHG_DIV6 0x1e -#define ADC5_OFF 0xff - -/* 30k pull-up1 */ -#define ADC5_BAT_THERM_30K_PU 0x2a -#define ADC5_BAT_ID_30K_PU 0x2b -#define ADC5_XO_THERM_30K_PU 0x2c -#define ADC5_AMUX_THM1_30K_PU 0x2d -#define ADC5_AMUX_THM2_30K_PU 0x2e -#define ADC5_AMUX_THM3_30K_PU 0x2f -#define ADC5_AMUX_THM4_30K_PU 0x30 -#define ADC5_AMUX_THM5_30K_PU 0x31 -#define ADC5_GPIO1_30K_PU 0x32 -#define ADC5_GPIO2_30K_PU 0x33 -#define ADC5_GPIO3_30K_PU 0x34 -#define ADC5_GPIO4_30K_PU 0x35 -#define ADC5_GPIO5_30K_PU 0x36 -#define ADC5_GPIO6_30K_PU 0x37 -#define ADC5_GPIO7_30K_PU 0x38 -#define ADC5_SBUx_30K_PU 0x39 - -/* 100k pull-up2 */ -#define ADC5_BAT_THERM_100K_PU 0x4a -#define ADC5_BAT_ID_100K_PU 0x4b -#define ADC5_XO_THERM_100K_PU 0x4c -#define ADC5_AMUX_THM1_100K_PU 0x4d -#define ADC5_AMUX_THM2_100K_PU 0x4e -#define ADC5_AMUX_THM3_100K_PU 0x4f -#define ADC5_AMUX_THM4_100K_PU 0x50 -#define ADC5_AMUX_THM5_100K_PU 0x51 -#define ADC5_GPIO1_100K_PU 0x52 -#define ADC5_GPIO2_100K_PU 0x53 -#define ADC5_GPIO3_100K_PU 0x54 -#define ADC5_GPIO4_100K_PU 0x55 -#define ADC5_GPIO5_100K_PU 0x56 -#define ADC5_GPIO6_100K_PU 0x57 -#define ADC5_GPIO7_100K_PU 0x58 -#define ADC5_SBUx_100K_PU 0x59 - -/* 400k pull-up3 */ -#define ADC5_BAT_THERM_400K_PU 0x6a -#define ADC5_BAT_ID_400K_PU 0x6b -#define ADC5_XO_THERM_400K_PU 0x6c -#define ADC5_AMUX_THM1_400K_PU 0x6d -#define ADC5_AMUX_THM2_400K_PU 0x6e -#define ADC5_AMUX_THM3_400K_PU 0x6f -#define ADC5_AMUX_THM4_400K_PU 0x70 -#define ADC5_AMUX_THM5_400K_PU 0x71 -#define ADC5_GPIO1_400K_PU 0x72 -#define ADC5_GPIO2_400K_PU 0x73 -#define ADC5_GPIO3_400K_PU 0x74 -#define ADC5_GPIO4_400K_PU 0x75 -#define ADC5_GPIO5_400K_PU 0x76 -#define ADC5_GPIO6_400K_PU 0x77 -#define ADC5_GPIO7_400K_PU 0x78 -#define ADC5_SBUx_400K_PU 0x79 - -/* 1/3 Divider */ -#define ADC5_GPIO1_DIV3 0x92 -#define ADC5_GPIO2_DIV3 0x93 -#define ADC5_GPIO3_DIV3 0x94 -#define ADC5_GPIO4_DIV3 0x95 -#define ADC5_GPIO5_DIV3 0x96 -#define ADC5_GPIO6_DIV3 0x97 -#define ADC5_GPIO7_DIV3 0x98 -#define ADC5_SBUx_DIV3 0x99 - -/* Current and combined current/voltage channels */ -#define ADC5_INT_EXT_ISENSE 0xa1 -#define ADC5_PARALLEL_ISENSE 0xa5 -#define ADC5_CUR_REPLICA_VDS 0xa7 -#define ADC5_CUR_SENS_BATFET_VDS_OFFSET 0xa9 -#define ADC5_CUR_SENS_REPLICA_VDS_OFFSET 0xab -#define ADC5_EXT_SENS_OFFSET 0xad - -#define ADC5_INT_EXT_ISENSE_VBAT_VDATA 0xb0 -#define ADC5_INT_EXT_ISENSE_VBAT_IDATA 0xb1 -#define ADC5_EXT_ISENSE_VBAT_VDATA 0xb2 -#define ADC5_EXT_ISENSE_VBAT_IDATA 0xb3 -#define ADC5_PARALLEL_ISENSE_VBAT_VDATA 0xb4 -#define ADC5_PARALLEL_ISENSE_VBAT_IDATA 0xb5 - -#define ADC5_MAX_CHANNEL 0xc0 - -/* ADC channels for ADC for PMIC7 */ - -#define ADC7_REF_GND 0x00 -#define ADC7_1P25VREF 0x01 -#define ADC7_VREF_VADC 0x02 -#define ADC7_DIE_TEMP 0x03 - -#define ADC7_AMUX_THM1 0x04 -#define ADC7_AMUX_THM2 0x05 -#define ADC7_AMUX_THM3 0x06 -#define ADC7_AMUX_THM4 0x07 -#define ADC7_AMUX_THM5 0x08 -#define ADC7_AMUX_THM6 0x09 -#define ADC7_GPIO1 0x0a -#define ADC7_GPIO2 0x0b -#define ADC7_GPIO3 0x0c -#define ADC7_GPIO4 0x0d - -#define ADC7_CHG_TEMP 0x10 -#define ADC7_USB_IN_V_16 0x11 -#define ADC7_VDC_16 0x12 -#define ADC7_CC1_ID 0x13 -#define ADC7_VREF_BAT_THERM 0x15 -#define ADC7_IIN_FB 0x17 - -/* 30k pull-up1 */ -#define ADC7_AMUX_THM1_30K_PU 0x24 -#define ADC7_AMUX_THM2_30K_PU 0x25 -#define ADC7_AMUX_THM3_30K_PU 0x26 -#define ADC7_AMUX_THM4_30K_PU 0x27 -#define ADC7_AMUX_THM5_30K_PU 0x28 -#define ADC7_AMUX_THM6_30K_PU 0x29 -#define ADC7_GPIO1_30K_PU 0x2a -#define ADC7_GPIO2_30K_PU 0x2b -#define ADC7_GPIO3_30K_PU 0x2c -#define ADC7_GPIO4_30K_PU 0x2d -#define ADC7_CC1_ID_30K_PU 0x33 - -/* 100k pull-up2 */ -#define ADC7_AMUX_THM1_100K_PU 0x44 -#define ADC7_AMUX_THM2_100K_PU 0x45 -#define ADC7_AMUX_THM3_100K_PU 0x46 -#define ADC7_AMUX_THM4_100K_PU 0x47 -#define ADC7_AMUX_THM5_100K_PU 0x48 -#define ADC7_AMUX_THM6_100K_PU 0x49 -#define ADC7_GPIO1_100K_PU 0x4a -#define ADC7_GPIO2_100K_PU 0x4b -#define ADC7_GPIO3_100K_PU 0x4c -#define ADC7_GPIO4_100K_PU 0x4d -#define ADC7_CC1_ID_100K_PU 0x53 - -/* 400k pull-up3 */ -#define ADC7_AMUX_THM1_400K_PU 0x64 -#define ADC7_AMUX_THM2_400K_PU 0x65 -#define ADC7_AMUX_THM3_400K_PU 0x66 -#define ADC7_AMUX_THM4_400K_PU 0x67 -#define ADC7_AMUX_THM5_400K_PU 0x68 -#define ADC7_AMUX_THM6_400K_PU 0x69 -#define ADC7_GPIO1_400K_PU 0x6a -#define ADC7_GPIO2_400K_PU 0x6b -#define ADC7_GPIO3_400K_PU 0x6c -#define ADC7_GPIO4_400K_PU 0x6d -#define ADC7_CC1_ID_400K_PU 0x73 - -/* 1/3 Divider */ -#define ADC7_GPIO1_DIV3 0x8a -#define ADC7_GPIO2_DIV3 0x8b -#define ADC7_GPIO3_DIV3 0x8c -#define ADC7_GPIO4_DIV3 0x8d - -#define ADC7_VPH_PWR 0x8e -#define ADC7_VBAT_SNS 0x8f - -#define ADC7_SBUx 0x94 -#define ADC7_VBAT_2S_MID 0x96 - -#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_H */ diff --git a/include/dt-bindings/interconnect/qcom,msm8916.h b/include/dt-bindings/interconnect/qcom,msm8916.h deleted file mode 100644 index 359a75feb19..00000000000 --- a/include/dt-bindings/interconnect/qcom,msm8916.h +++ /dev/null @@ -1,100 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Qualcomm interconnect IDs - * - * Copyright (c) 2019, Linaro Ltd. - * Author: Georgi Djakov <georgi.djakov@linaro.org> - */ - -#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MSM8916_H -#define __DT_BINDINGS_INTERCONNECT_QCOM_MSM8916_H - -#define BIMC_SNOC_SLV 0 -#define MASTER_JPEG 1 -#define MASTER_MDP_PORT0 2 -#define MASTER_QDSS_BAM 3 -#define MASTER_QDSS_ETR 4 -#define MASTER_SNOC_CFG 5 -#define MASTER_VFE 6 -#define MASTER_VIDEO_P0 7 -#define SNOC_MM_INT_0 8 -#define SNOC_MM_INT_1 9 -#define SNOC_MM_INT_2 10 -#define SNOC_MM_INT_BIMC 11 -#define PCNOC_SNOC_SLV 12 -#define SLAVE_APSS 13 -#define SLAVE_CATS_128 14 -#define SLAVE_OCMEM_64 15 -#define SLAVE_IMEM 16 -#define SLAVE_QDSS_STM 17 -#define SLAVE_SRVC_SNOC 18 -#define SNOC_BIMC_0_MAS 19 -#define SNOC_BIMC_1_MAS 20 -#define SNOC_INT_0 21 -#define SNOC_INT_1 22 -#define SNOC_INT_BIMC 23 -#define SNOC_PCNOC_MAS 24 -#define SNOC_QDSS_INT 25 - -#define BIMC_SNOC_MAS 0 -#define MASTER_AMPSS_M0 1 -#define MASTER_GRAPHICS_3D 2 -#define MASTER_TCU0 3 -#define MASTER_TCU1 4 -#define SLAVE_AMPSS_L2 5 -#define SLAVE_EBI_CH0 6 -#define SNOC_BIMC_0_SLV 7 -#define SNOC_BIMC_1_SLV 8 - -#define MASTER_BLSP_1 0 -#define MASTER_DEHR 1 -#define MASTER_LPASS 2 -#define MASTER_CRYPTO_CORE0 3 -#define MASTER_SDCC_1 4 -#define MASTER_SDCC_2 5 -#define MASTER_SPDM 6 -#define MASTER_USB_HS 7 -#define PCNOC_INT_0 8 -#define PCNOC_INT_1 9 -#define PCNOC_MAS_0 10 -#define PCNOC_MAS_1 11 -#define PCNOC_SLV_0 12 -#define PCNOC_SLV_1 13 -#define PCNOC_SLV_2 14 -#define PCNOC_SLV_3 15 -#define PCNOC_SLV_4 16 -#define PCNOC_SLV_8 17 -#define PCNOC_SLV_9 18 -#define PCNOC_SNOC_MAS 19 -#define SLAVE_BIMC_CFG 20 -#define SLAVE_BLSP_1 21 -#define SLAVE_BOOT_ROM 22 -#define SLAVE_CAMERA_CFG 23 -#define SLAVE_CLK_CTL 24 -#define SLAVE_CRYPTO_0_CFG 25 -#define SLAVE_DEHR_CFG 26 -#define SLAVE_DISPLAY_CFG 27 -#define SLAVE_GRAPHICS_3D_CFG 28 -#define SLAVE_IMEM_CFG 29 -#define SLAVE_LPASS 30 -#define SLAVE_MPM 31 -#define SLAVE_MSG_RAM 32 -#define SLAVE_MSS 33 -#define SLAVE_PDM 34 -#define SLAVE_PMIC_ARB 35 -#define SLAVE_PCNOC_CFG 36 -#define SLAVE_PRNG 37 -#define SLAVE_QDSS_CFG 38 -#define SLAVE_RBCPR_CFG 39 -#define SLAVE_SDCC_1 40 -#define SLAVE_SDCC_2 41 -#define SLAVE_SECURITY 42 -#define SLAVE_SNOC_CFG 43 -#define SLAVE_SPDM 44 -#define SLAVE_TCSR 45 -#define SLAVE_TLMM 46 -#define SLAVE_USB_HS 47 -#define SLAVE_VENUS_CFG 48 -#define SNOC_PCNOC_SLV 49 - -#endif diff --git a/include/dt-bindings/interconnect/qcom,msm8996-cbf.h b/include/dt-bindings/interconnect/qcom,msm8996-cbf.h deleted file mode 100644 index aac5e69f6bd..00000000000 --- a/include/dt-bindings/interconnect/qcom,msm8996-cbf.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -/* - * Copyright (C) 2023 Linaro Ltd. All rights reserved. - */ - -#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MSM8996_CBF_H -#define __DT_BINDINGS_INTERCONNECT_QCOM_MSM8996_CBF_H - -#define MASTER_CBF_M4M 0 -#define SLAVE_CBF_M4M 1 - -#endif diff --git a/include/dt-bindings/interconnect/qcom,msm8996.h b/include/dt-bindings/interconnect/qcom,msm8996.h deleted file mode 100644 index a0b7c0ec7be..00000000000 --- a/include/dt-bindings/interconnect/qcom,msm8996.h +++ /dev/null @@ -1,163 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ -/* - * Qualcomm MSM8996 interconnect IDs - * - * Copyright (c) 2021 Yassine Oudjana <y.oudjana@protonmail.com> - */ - -#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MSM8996_H -#define __DT_BINDINGS_INTERCONNECT_QCOM_MSM8996_H - -/* A0NOC */ -#define MASTER_PCIE_0 0 -#define MASTER_PCIE_1 1 -#define MASTER_PCIE_2 2 - -/* A1NOC */ -#define MASTER_CNOC_A1NOC 0 -#define MASTER_CRYPTO_CORE0 1 -#define MASTER_PNOC_A1NOC 2 - -/* A2NOC */ -#define MASTER_USB3 0 -#define MASTER_IPA 1 -#define MASTER_UFS 2 - -/* BIMC */ -#define MASTER_AMPSS_M0 0 -#define MASTER_GRAPHICS_3D 1 -#define MASTER_MNOC_BIMC 2 -#define MASTER_SNOC_BIMC 3 -#define SLAVE_EBI_CH0 4 -#define SLAVE_HMSS_L3 5 -#define SLAVE_BIMC_SNOC_0 6 -#define SLAVE_BIMC_SNOC_1 7 - -/* CNOC */ -#define MASTER_SNOC_CNOC 0 -#define MASTER_QDSS_DAP 1 -#define SLAVE_CNOC_A1NOC 2 -#define SLAVE_CLK_CTL 3 -#define SLAVE_TCSR 4 -#define SLAVE_TLMM 5 -#define SLAVE_CRYPTO_0_CFG 6 -#define SLAVE_MPM 7 -#define SLAVE_PIMEM_CFG 8 -#define SLAVE_IMEM_CFG 9 -#define SLAVE_MESSAGE_RAM 10 -#define SLAVE_BIMC_CFG 11 -#define SLAVE_PMIC_ARB 12 -#define SLAVE_PRNG 13 -#define SLAVE_DCC_CFG 14 -#define SLAVE_RBCPR_MX 15 -#define SLAVE_QDSS_CFG 16 -#define SLAVE_RBCPR_CX 17 -#define SLAVE_QDSS_RBCPR_APU 18 -#define SLAVE_CNOC_MNOC_CFG 19 -#define SLAVE_SNOC_CFG 20 -#define SLAVE_SNOC_MPU_CFG 21 -#define SLAVE_EBI1_PHY_CFG 22 -#define SLAVE_A0NOC_CFG 23 -#define SLAVE_PCIE_1_CFG 24 -#define SLAVE_PCIE_2_CFG 25 -#define SLAVE_PCIE_0_CFG 26 -#define SLAVE_PCIE20_AHB2PHY 27 -#define SLAVE_A0NOC_MPU_CFG 28 -#define SLAVE_UFS_CFG 29 -#define SLAVE_A1NOC_CFG 30 -#define SLAVE_A1NOC_MPU_CFG 31 -#define SLAVE_A2NOC_CFG 32 -#define SLAVE_A2NOC_MPU_CFG 33 -#define SLAVE_SSC_CFG 34 -#define SLAVE_A0NOC_SMMU_CFG 35 -#define SLAVE_A1NOC_SMMU_CFG 36 -#define SLAVE_A2NOC_SMMU_CFG 37 -#define SLAVE_LPASS_SMMU_CFG 38 -#define SLAVE_CNOC_MNOC_MMSS_CFG 39 - -/* MNOC */ -#define MASTER_CNOC_MNOC_CFG 0 -#define MASTER_CPP 1 -#define MASTER_JPEG 2 -#define MASTER_MDP_PORT0 3 -#define MASTER_MDP_PORT1 4 -#define MASTER_ROTATOR 5 -#define MASTER_VIDEO_P0 6 -#define MASTER_VFE 7 -#define MASTER_SNOC_VMEM 8 -#define MASTER_VIDEO_P0_OCMEM 9 -#define MASTER_CNOC_MNOC_MMSS_CFG 10 -#define SLAVE_MNOC_BIMC 11 -#define SLAVE_VMEM 12 -#define SLAVE_SERVICE_MNOC 13 -#define SLAVE_MMAGIC_CFG 14 -#define SLAVE_CPR_CFG 15 -#define SLAVE_MISC_CFG 16 -#define SLAVE_VENUS_THROTTLE_CFG 17 -#define SLAVE_VENUS_CFG 18 -#define SLAVE_VMEM_CFG 19 -#define SLAVE_DSA_CFG 20 -#define SLAVE_MMSS_CLK_CFG 21 -#define SLAVE_DSA_MPU_CFG 22 -#define SLAVE_MNOC_MPU_CFG 23 -#define SLAVE_DISPLAY_CFG 24 -#define SLAVE_DISPLAY_THROTTLE_CFG 25 -#define SLAVE_CAMERA_CFG 26 -#define SLAVE_CAMERA_THROTTLE_CFG 27 -#define SLAVE_GRAPHICS_3D_CFG 28 -#define SLAVE_SMMU_MDP_CFG 29 -#define SLAVE_SMMU_ROT_CFG 30 -#define SLAVE_SMMU_VENUS_CFG 31 -#define SLAVE_SMMU_CPP_CFG 32 -#define SLAVE_SMMU_JPEG_CFG 33 -#define SLAVE_SMMU_VFE_CFG 34 - -/* PNOC */ -#define MASTER_SNOC_PNOC 0 -#define MASTER_SDCC_1 1 -#define MASTER_SDCC_2 2 -#define MASTER_SDCC_4 3 -#define MASTER_USB_HS 4 -#define MASTER_BLSP_1 5 -#define MASTER_BLSP_2 6 -#define MASTER_TSIF 7 -#define SLAVE_PNOC_A1NOC 8 -#define SLAVE_USB_HS 9 -#define SLAVE_SDCC_2 10 -#define SLAVE_SDCC_4 11 -#define SLAVE_TSIF 12 -#define SLAVE_BLSP_2 13 -#define SLAVE_SDCC_1 14 -#define SLAVE_BLSP_1 15 -#define SLAVE_PDM 16 -#define SLAVE_AHB2PHY 17 - -/* SNOC */ -#define MASTER_HMSS 0 -#define MASTER_QDSS_BAM 1 -#define MASTER_SNOC_CFG 2 -#define MASTER_BIMC_SNOC_0 3 -#define MASTER_BIMC_SNOC_1 4 -#define MASTER_A0NOC_SNOC 5 -#define MASTER_A1NOC_SNOC 6 -#define MASTER_A2NOC_SNOC 7 -#define MASTER_QDSS_ETR 8 -#define SLAVE_A0NOC_SNOC 9 -#define SLAVE_A1NOC_SNOC 10 -#define SLAVE_A2NOC_SNOC 11 -#define SLAVE_HMSS 12 -#define SLAVE_LPASS 13 -#define SLAVE_USB3 14 -#define SLAVE_SNOC_BIMC 15 -#define SLAVE_SNOC_CNOC 16 -#define SLAVE_IMEM 17 -#define SLAVE_PIMEM 18 -#define SLAVE_SNOC_VMEM 19 -#define SLAVE_SNOC_PNOC 20 -#define SLAVE_QDSS_STM 21 -#define SLAVE_PCIE_0 22 -#define SLAVE_PCIE_1 23 -#define SLAVE_PCIE_2 24 -#define SLAVE_SERVICE_SNOC 25 - -#endif diff --git a/include/dt-bindings/interconnect/qcom,osm-l3.h b/include/dt-bindings/interconnect/qcom,osm-l3.h deleted file mode 100644 index 61ef649ae56..00000000000 --- a/include/dt-bindings/interconnect/qcom,osm-l3.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2019 The Linux Foundation. All rights reserved. - */ - -#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_OSM_L3_H -#define __DT_BINDINGS_INTERCONNECT_QCOM_OSM_L3_H - -#define MASTER_OSM_L3_APPS 0 -#define SLAVE_OSM_L3 1 - -#define MASTER_EPSS_L3_APPS 0 -#define SLAVE_EPSS_L3_SHARED 1 - -#endif diff --git a/include/dt-bindings/interconnect/qcom,sdm845.h b/include/dt-bindings/interconnect/qcom,sdm845.h deleted file mode 100644 index 67b500e2491..00000000000 --- a/include/dt-bindings/interconnect/qcom,sdm845.h +++ /dev/null @@ -1,150 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Qualcomm SDM845 interconnect IDs - * - * Copyright (c) 2018, Linaro Ltd. - * Author: Georgi Djakov <georgi.djakov@linaro.org> - */ - -#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SDM845_H -#define __DT_BINDINGS_INTERCONNECT_QCOM_SDM845_H - -#define MASTER_A1NOC_CFG 0 -#define MASTER_TSIF 1 -#define MASTER_SDCC_2 2 -#define MASTER_SDCC_4 3 -#define MASTER_UFS_CARD 4 -#define MASTER_UFS_MEM 5 -#define MASTER_PCIE_0 6 -#define SLAVE_A1NOC_SNOC 7 -#define SLAVE_SERVICE_A1NOC 8 -#define SLAVE_ANOC_PCIE_A1NOC_SNOC 9 -#define MASTER_QUP_1 10 - -#define MASTER_A2NOC_CFG 0 -#define MASTER_QDSS_BAM 1 -#define MASTER_CNOC_A2NOC 2 -#define MASTER_CRYPTO 3 -#define MASTER_IPA 4 -#define MASTER_PCIE_1 5 -#define MASTER_QDSS_ETR 6 -#define MASTER_USB3_0 7 -#define MASTER_USB3_1 8 -#define SLAVE_A2NOC_SNOC 9 -#define SLAVE_ANOC_PCIE_SNOC 10 -#define SLAVE_SERVICE_A2NOC 11 -#define MASTER_QUP_2 12 - -#define MASTER_SPDM 0 -#define MASTER_TIC 1 -#define MASTER_SNOC_CNOC 2 -#define MASTER_QDSS_DAP 3 -#define SLAVE_A1NOC_CFG 4 -#define SLAVE_A2NOC_CFG 5 -#define SLAVE_AOP 6 -#define SLAVE_AOSS 7 -#define SLAVE_CAMERA_CFG 8 -#define SLAVE_CLK_CTL 9 -#define SLAVE_CDSP_CFG 10 -#define SLAVE_RBCPR_CX_CFG 11 -#define SLAVE_CRYPTO_0_CFG 12 -#define SLAVE_DCC_CFG 13 -#define SLAVE_CNOC_DDRSS 14 -#define SLAVE_DISPLAY_CFG 15 -#define SLAVE_GLM 16 -#define SLAVE_GFX3D_CFG 17 -#define SLAVE_IMEM_CFG 18 -#define SLAVE_IPA_CFG 19 -#define SLAVE_CNOC_MNOC_CFG 20 -#define SLAVE_PCIE_0_CFG 21 -#define SLAVE_PCIE_1_CFG 22 -#define SLAVE_PDM 23 -#define SLAVE_SOUTH_PHY_CFG 24 -#define SLAVE_PIMEM_CFG 25 -#define SLAVE_PRNG 26 -#define SLAVE_QDSS_CFG 27 -#define SLAVE_BLSP_2 28 -#define SLAVE_BLSP_1 29 -#define SLAVE_SDCC_2 30 -#define SLAVE_SDCC_4 31 -#define SLAVE_SNOC_CFG 32 -#define SLAVE_SPDM_WRAPPER 33 -#define SLAVE_SPSS_CFG 34 -#define SLAVE_TCSR 35 -#define SLAVE_TLMM_NORTH 36 -#define SLAVE_TLMM_SOUTH 37 -#define SLAVE_TSIF 38 -#define SLAVE_UFS_CARD_CFG 39 -#define SLAVE_UFS_MEM_CFG 40 -#define SLAVE_USB3_0 41 -#define SLAVE_USB3_1 42 -#define SLAVE_VENUS_CFG 43 -#define SLAVE_VSENSE_CTRL_CFG 44 -#define SLAVE_CNOC_A2NOC 45 -#define SLAVE_SERVICE_CNOC 46 - -#define MASTER_CNOC_DC_NOC 0 -#define SLAVE_LLCC_CFG 1 -#define SLAVE_MEM_NOC_CFG 2 - -#define MASTER_APPSS_PROC 0 -#define MASTER_GNOC_CFG 1 -#define SLAVE_GNOC_SNOC 2 -#define SLAVE_GNOC_MEM_NOC 3 -#define SLAVE_SERVICE_GNOC 4 - -#define MASTER_TCU_0 0 -#define MASTER_MEM_NOC_CFG 1 -#define MASTER_GNOC_MEM_NOC 2 -#define MASTER_MNOC_HF_MEM_NOC 3 -#define MASTER_MNOC_SF_MEM_NOC 4 -#define MASTER_SNOC_GC_MEM_NOC 5 -#define MASTER_SNOC_SF_MEM_NOC 6 -#define MASTER_GFX3D 7 -#define SLAVE_MSS_PROC_MS_MPU_CFG 8 -#define SLAVE_MEM_NOC_GNOC 9 -#define SLAVE_LLCC 10 -#define SLAVE_MEM_NOC_SNOC 11 -#define SLAVE_SERVICE_MEM_NOC 12 -#define MASTER_LLCC 13 -#define SLAVE_EBI1 14 - -#define MASTER_CNOC_MNOC_CFG 0 -#define MASTER_CAMNOC_HF0 1 -#define MASTER_CAMNOC_HF1 2 -#define MASTER_CAMNOC_SF 3 -#define MASTER_MDP0 4 -#define MASTER_MDP1 5 -#define MASTER_ROTATOR 6 -#define MASTER_VIDEO_P0 7 -#define MASTER_VIDEO_P1 8 -#define MASTER_VIDEO_PROC 9 -#define SLAVE_MNOC_SF_MEM_NOC 10 -#define SLAVE_MNOC_HF_MEM_NOC 11 -#define SLAVE_SERVICE_MNOC 12 -#define MASTER_CAMNOC_HF0_UNCOMP 13 -#define MASTER_CAMNOC_HF1_UNCOMP 14 -#define MASTER_CAMNOC_SF_UNCOMP 15 -#define SLAVE_CAMNOC_UNCOMP 16 - -#define MASTER_SNOC_CFG 0 -#define MASTER_A1NOC_SNOC 1 -#define MASTER_A2NOC_SNOC 2 -#define MASTER_GNOC_SNOC 3 -#define MASTER_MEM_NOC_SNOC 4 -#define MASTER_ANOC_PCIE_SNOC 5 -#define MASTER_PIMEM 6 -#define MASTER_GIC 7 -#define SLAVE_APPSS 8 -#define SLAVE_SNOC_CNOC 9 -#define SLAVE_SNOC_MEM_NOC_GC 10 -#define SLAVE_SNOC_MEM_NOC_SF 11 -#define SLAVE_IMEM 12 -#define SLAVE_PCIE_0 13 -#define SLAVE_PCIE_1 14 -#define SLAVE_PIMEM 15 -#define SLAVE_SERVICE_SNOC 16 -#define SLAVE_QDSS_STM 17 -#define SLAVE_TCU 18 - -#endif diff --git a/include/dt-bindings/interrupt-controller/arm-gic.h b/include/dt-bindings/interrupt-controller/arm-gic.h deleted file mode 100644 index 35b6f69b7db..00000000000 --- a/include/dt-bindings/interrupt-controller/arm-gic.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 OR MIT */ -/* - * This header provides constants for the ARM GIC. - */ - -#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H -#define _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H - -#include <dt-bindings/interrupt-controller/irq.h> - -/* interrupt specifier cell 0 */ - -#define GIC_SPI 0 -#define GIC_PPI 1 - -/* - * Interrupt specifier cell 2. - * The flags in irq.h are valid, plus those below. - */ -#define GIC_CPU_MASK_RAW(x) ((x) << 8) -#define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1) - -#endif diff --git a/include/dt-bindings/phy/phy-qcom-qmp.h b/include/dt-bindings/phy/phy-qcom-qmp.h deleted file mode 100644 index 4edec4c5b22..00000000000 --- a/include/dt-bindings/phy/phy-qcom-qmp.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ -/* - * Qualcomm QMP PHY constants - * - * Copyright (C) 2022 Linaro Limited - */ - -#ifndef _DT_BINDINGS_PHY_QMP -#define _DT_BINDINGS_PHY_QMP - -/* QMP USB4-USB3-DP clocks */ -#define QMP_USB43DP_USB3_PIPE_CLK 0 -#define QMP_USB43DP_DP_LINK_CLK 1 -#define QMP_USB43DP_DP_VCO_DIV_CLK 2 - -/* QMP USB4-USB3-DP PHYs */ -#define QMP_USB43DP_USB3_PHY 0 -#define QMP_USB43DP_DP_PHY 1 - -#endif /* _DT_BINDINGS_PHY_QMP */ diff --git a/include/dt-bindings/phy/phy-qcom-qusb2.h b/include/dt-bindings/phy/phy-qcom-qusb2.h deleted file mode 100644 index 5c5e4d800ca..00000000000 --- a/include/dt-bindings/phy/phy-qcom-qusb2.h +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_QCOM_PHY_QUSB2_H_ -#define _DT_BINDINGS_QCOM_PHY_QUSB2_H_ - -/* PHY HSTX TRIM bit values (24mA to 15mA) */ -#define QUSB2_V2_HSTX_TRIM_24_0_MA 0x0 -#define QUSB2_V2_HSTX_TRIM_23_4_MA 0x1 -#define QUSB2_V2_HSTX_TRIM_22_8_MA 0x2 -#define QUSB2_V2_HSTX_TRIM_22_2_MA 0x3 -#define QUSB2_V2_HSTX_TRIM_21_6_MA 0x4 -#define QUSB2_V2_HSTX_TRIM_21_0_MA 0x5 -#define QUSB2_V2_HSTX_TRIM_20_4_MA 0x6 -#define QUSB2_V2_HSTX_TRIM_19_8_MA 0x7 -#define QUSB2_V2_HSTX_TRIM_19_2_MA 0x8 -#define QUSB2_V2_HSTX_TRIM_18_6_MA 0x9 -#define QUSB2_V2_HSTX_TRIM_18_0_MA 0xa -#define QUSB2_V2_HSTX_TRIM_17_4_MA 0xb -#define QUSB2_V2_HSTX_TRIM_16_8_MA 0xc -#define QUSB2_V2_HSTX_TRIM_16_2_MA 0xd -#define QUSB2_V2_HSTX_TRIM_15_6_MA 0xe -#define QUSB2_V2_HSTX_TRIM_15_0_MA 0xf - -/* PHY PREEMPHASIS bit values */ -#define QUSB2_V2_PREEMPHASIS_NONE 0 -#define QUSB2_V2_PREEMPHASIS_5_PERCENT 1 -#define QUSB2_V2_PREEMPHASIS_10_PERCENT 2 -#define QUSB2_V2_PREEMPHASIS_15_PERCENT 3 - -/* PHY PREEMPHASIS-WIDTH bit values */ -#define QUSB2_V2_PREEMPHASIS_WIDTH_FULL_BIT 0 -#define QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT 1 - -#endif diff --git a/include/dt-bindings/pinctrl/qcom,pmic-gpio.h b/include/dt-bindings/pinctrl/qcom,pmic-gpio.h deleted file mode 100644 index e5df5ce45a0..00000000000 --- a/include/dt-bindings/pinctrl/qcom,pmic-gpio.h +++ /dev/null @@ -1,164 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for the Qualcomm PMIC GPIO binding. - */ - -#ifndef _DT_BINDINGS_PINCTRL_QCOM_PMIC_GPIO_H -#define _DT_BINDINGS_PINCTRL_QCOM_PMIC_GPIO_H - -#define PMIC_GPIO_PULL_UP_30 0 -#define PMIC_GPIO_PULL_UP_1P5 1 -#define PMIC_GPIO_PULL_UP_31P5 2 -#define PMIC_GPIO_PULL_UP_1P5_30 3 - -#define PMIC_GPIO_STRENGTH_NO 0 -#define PMIC_GPIO_STRENGTH_HIGH 1 -#define PMIC_GPIO_STRENGTH_MED 2 -#define PMIC_GPIO_STRENGTH_LOW 3 - -/* - * Note: PM8018 GPIO3 and GPIO4 are supporting - * only S3 and L2 options (1.8V) - */ -#define PM8018_GPIO_L6 0 -#define PM8018_GPIO_L5 1 -#define PM8018_GPIO_S3 2 -#define PM8018_GPIO_L14 3 -#define PM8018_GPIO_L2 4 -#define PM8018_GPIO_L4 5 -#define PM8018_GPIO_VDD 6 - -/* - * Note: PM8038 GPIO7 and GPIO8 are supporting - * only L11 and L4 options (1.8V) - */ -#define PM8038_GPIO_VPH 0 -#define PM8038_GPIO_BB 1 -#define PM8038_GPIO_L11 2 -#define PM8038_GPIO_L15 3 -#define PM8038_GPIO_L4 4 -#define PM8038_GPIO_L3 5 -#define PM8038_GPIO_L17 6 - -#define PM8058_GPIO_VPH 0 -#define PM8058_GPIO_BB 1 -#define PM8058_GPIO_S3 2 -#define PM8058_GPIO_L3 3 -#define PM8058_GPIO_L7 4 -#define PM8058_GPIO_L6 5 -#define PM8058_GPIO_L5 6 -#define PM8058_GPIO_L2 7 - -/* - * Note: PM8916 GPIO1 and GPIO2 are supporting - * only L2(1.15V) and L5(1.8V) options - */ -#define PM8916_GPIO_VPH 0 -#define PM8916_GPIO_L2 2 -#define PM8916_GPIO_L5 3 - -#define PM8917_GPIO_VPH 0 -#define PM8917_GPIO_S4 2 -#define PM8917_GPIO_L15 3 -#define PM8917_GPIO_L4 4 -#define PM8917_GPIO_L3 5 -#define PM8917_GPIO_L17 6 - -#define PM8921_GPIO_VPH 0 -#define PM8921_GPIO_BB 1 -#define PM8921_GPIO_S4 2 -#define PM8921_GPIO_L15 3 -#define PM8921_GPIO_L4 4 -#define PM8921_GPIO_L3 5 -#define PM8921_GPIO_L17 6 - -/* - * Note: PM8941 gpios from 15 to 18 are supporting - * only S3 and L6 options (1.8V) - */ -#define PM8941_GPIO_VPH 0 -#define PM8941_GPIO_L1 1 -#define PM8941_GPIO_S3 2 -#define PM8941_GPIO_L6 3 - -/* - * Note: PMA8084 gpios from 15 to 18 are supporting - * only S4 and L6 options (1.8V) - */ -#define PMA8084_GPIO_VPH 0 -#define PMA8084_GPIO_L1 1 -#define PMA8084_GPIO_S4 2 -#define PMA8084_GPIO_L6 3 - -#define PM8994_GPIO_VPH 0 -#define PM8994_GPIO_S4 2 -#define PM8994_GPIO_L12 3 - -/* To be used with "function" */ -#define PMIC_GPIO_FUNC_NORMAL "normal" -#define PMIC_GPIO_FUNC_PAIRED "paired" -#define PMIC_GPIO_FUNC_FUNC1 "func1" -#define PMIC_GPIO_FUNC_FUNC2 "func2" -#define PMIC_GPIO_FUNC_FUNC3 "func3" -#define PMIC_GPIO_FUNC_FUNC4 "func4" -#define PMIC_GPIO_FUNC_DTEST1 "dtest1" -#define PMIC_GPIO_FUNC_DTEST2 "dtest2" -#define PMIC_GPIO_FUNC_DTEST3 "dtest3" -#define PMIC_GPIO_FUNC_DTEST4 "dtest4" - -#define PM8038_GPIO1_2_LPG_DRV PMIC_GPIO_FUNC_FUNC1 -#define PM8038_GPIO3_5V_BOOST_EN PMIC_GPIO_FUNC_FUNC1 -#define PM8038_GPIO4_SSBI_ALT_CLK PMIC_GPIO_FUNC_FUNC1 -#define PM8038_GPIO5_6_EXT_REG_EN PMIC_GPIO_FUNC_FUNC1 -#define PM8038_GPIO10_11_EXT_REG_EN PMIC_GPIO_FUNC_FUNC1 -#define PM8038_GPIO6_7_CLK PMIC_GPIO_FUNC_FUNC1 -#define PM8038_GPIO9_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1 -#define PM8038_GPIO6_12_KYPD_DRV PMIC_GPIO_FUNC_FUNC2 - -#define PM8058_GPIO7_8_MP3_CLK PMIC_GPIO_FUNC_FUNC1 -#define PM8058_GPIO7_8_BCLK_19P2MHZ PMIC_GPIO_FUNC_FUNC2 -#define PM8058_GPIO9_26_KYPD_DRV PMIC_GPIO_FUNC_FUNC1 -#define PM8058_GPIO21_23_UART_TX PMIC_GPIO_FUNC_FUNC2 -#define PM8058_GPIO24_26_LPG_DRV PMIC_GPIO_FUNC_FUNC2 -#define PM8058_GPIO33_BCLK_19P2MHZ PMIC_GPIO_FUNC_FUNC1 -#define PM8058_GPIO34_35_MP3_CLK PMIC_GPIO_FUNC_FUNC1 -#define PM8058_GPIO36_BCLK_19P2MHZ PMIC_GPIO_FUNC_FUNC1 -#define PM8058_GPIO37_UPL_OUT PMIC_GPIO_FUNC_FUNC1 -#define PM8058_GPIO37_UART_M_RX PMIC_GPIO_FUNC_FUNC2 -#define PM8058_GPIO38_XO_SLEEP_CLK PMIC_GPIO_FUNC_FUNC1 -#define PM8058_GPIO38_39_CLK_32KHZ PMIC_GPIO_FUNC_FUNC2 -#define PM8058_GPIO39_MP3_CLK PMIC_GPIO_FUNC_FUNC1 -#define PM8058_GPIO40_EXT_BB_EN PMIC_GPIO_FUNC_FUNC1 - -#define PM8916_GPIO1_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1 -#define PM8916_GPIO1_KEYP_DRV PMIC_GPIO_FUNC_FUNC2 -#define PM8916_GPIO2_DIV_CLK PMIC_GPIO_FUNC_FUNC1 -#define PM8916_GPIO2_SLEEP_CLK PMIC_GPIO_FUNC_FUNC2 -#define PM8916_GPIO3_KEYP_DRV PMIC_GPIO_FUNC_FUNC1 -#define PM8916_GPIO4_KEYP_DRV PMIC_GPIO_FUNC_FUNC2 - -#define PM8917_GPIO9_18_KEYP_DRV PMIC_GPIO_FUNC_FUNC1 -#define PM8917_GPIO20_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1 -#define PM8917_GPIO21_23_UART_TX PMIC_GPIO_FUNC_FUNC2 -#define PM8917_GPIO25_26_EXT_REG_EN PMIC_GPIO_FUNC_FUNC1 -#define PM8917_GPIO37_38_XO_SLEEP_CLK PMIC_GPIO_FUNC_FUNC1 -#define PM8917_GPIO37_38_MP3_CLK PMIC_GPIO_FUNC_FUNC2 - -#define PM8941_GPIO9_14_KYPD_DRV PMIC_GPIO_FUNC_FUNC1 -#define PM8941_GPIO15_18_DIV_CLK PMIC_GPIO_FUNC_FUNC1 -#define PM8941_GPIO15_18_SLEEP_CLK PMIC_GPIO_FUNC_FUNC2 -#define PM8941_GPIO23_26_KYPD_DRV PMIC_GPIO_FUNC_FUNC1 -#define PM8941_GPIO23_26_LPG_DRV_HI PMIC_GPIO_FUNC_FUNC2 -#define PM8941_GPIO31_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1 -#define PM8941_GPIO33_36_LPG_DRV_3D PMIC_GPIO_FUNC_FUNC1 -#define PM8941_GPIO33_36_LPG_DRV_HI PMIC_GPIO_FUNC_FUNC2 - -#define PMA8084_GPIO4_5_LPG_DRV PMIC_GPIO_FUNC_FUNC1 -#define PMA8084_GPIO7_10_LPG_DRV PMIC_GPIO_FUNC_FUNC1 -#define PMA8084_GPIO5_14_KEYP_DRV PMIC_GPIO_FUNC_FUNC2 -#define PMA8084_GPIO19_21_KEYP_DRV PMIC_GPIO_FUNC_FUNC2 -#define PMA8084_GPIO15_18_DIV_CLK PMIC_GPIO_FUNC_FUNC1 -#define PMA8084_GPIO15_18_SLEEP_CLK PMIC_GPIO_FUNC_FUNC2 -#define PMA8084_GPIO22_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1 - -#endif diff --git a/include/dt-bindings/pinctrl/qcom,pmic-mpp.h b/include/dt-bindings/pinctrl/qcom,pmic-mpp.h deleted file mode 100644 index 32e66ee7e83..00000000000 --- a/include/dt-bindings/pinctrl/qcom,pmic-mpp.h +++ /dev/null @@ -1,106 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for the Qualcomm PMIC's - * Multi-Purpose Pin binding. - */ - -#ifndef _DT_BINDINGS_PINCTRL_QCOM_PMIC_MPP_H -#define _DT_BINDINGS_PINCTRL_QCOM_PMIC_MPP_H - -/* power-source */ - -/* Digital Input/Output: level [PM8058] */ -#define PM8058_MPP_VPH 0 -#define PM8058_MPP_S3 1 -#define PM8058_MPP_L2 2 -#define PM8058_MPP_L3 3 - -/* Digital Input/Output: level [PM8901] */ -#define PM8901_MPP_MSMIO 0 -#define PM8901_MPP_DIG 1 -#define PM8901_MPP_L5 2 -#define PM8901_MPP_S4 3 -#define PM8901_MPP_VPH 4 - -/* Digital Input/Output: level [PM8921] */ -#define PM8921_MPP_S4 1 -#define PM8921_MPP_L15 3 -#define PM8921_MPP_L17 4 -#define PM8921_MPP_VPH 7 - -/* Digital Input/Output: level [PM8821] */ -#define PM8821_MPP_1P8 0 -#define PM8821_MPP_VPH 7 - -/* Digital Input/Output: level [PM8018] */ -#define PM8018_MPP_L4 0 -#define PM8018_MPP_L14 1 -#define PM8018_MPP_S3 2 -#define PM8018_MPP_L6 3 -#define PM8018_MPP_L2 4 -#define PM8018_MPP_L5 5 -#define PM8018_MPP_VPH 7 - -/* Digital Input/Output: level [PM8038] */ -#define PM8038_MPP_L20 0 -#define PM8038_MPP_L11 1 -#define PM8038_MPP_L5 2 -#define PM8038_MPP_L15 3 -#define PM8038_MPP_L17 4 -#define PM8038_MPP_VPH 7 - -#define PM8841_MPP_VPH 0 -#define PM8841_MPP_S3 2 - -#define PM8916_MPP_VPH 0 -#define PM8916_MPP_L2 2 -#define PM8916_MPP_L5 3 - -#define PM8941_MPP_VPH 0 -#define PM8941_MPP_L1 1 -#define PM8941_MPP_S3 2 -#define PM8941_MPP_L6 3 - -#define PMA8084_MPP_VPH 0 -#define PMA8084_MPP_L1 1 -#define PMA8084_MPP_S4 2 -#define PMA8084_MPP_L6 3 - -#define PM8994_MPP_VPH 0 -/* Only supported for MPP_05-MPP_08 */ -#define PM8994_MPP_L19 1 -#define PM8994_MPP_S4 2 -#define PM8994_MPP_L12 3 - -/* - * Analog Input - Set the source for analog input. - * To be used with "qcom,amux-route" property - */ -#define PMIC_MPP_AMUX_ROUTE_CH5 0 -#define PMIC_MPP_AMUX_ROUTE_CH6 1 -#define PMIC_MPP_AMUX_ROUTE_CH7 2 -#define PMIC_MPP_AMUX_ROUTE_CH8 3 -#define PMIC_MPP_AMUX_ROUTE_ABUS1 4 -#define PMIC_MPP_AMUX_ROUTE_ABUS2 5 -#define PMIC_MPP_AMUX_ROUTE_ABUS3 6 -#define PMIC_MPP_AMUX_ROUTE_ABUS4 7 - -/* Analog Output: level */ -#define PMIC_MPP_AOUT_LVL_1V25 0 -#define PMIC_MPP_AOUT_LVL_1V25_2 1 -#define PMIC_MPP_AOUT_LVL_0V625 2 -#define PMIC_MPP_AOUT_LVL_0V3125 3 -#define PMIC_MPP_AOUT_LVL_MPP 4 -#define PMIC_MPP_AOUT_LVL_ABUS1 5 -#define PMIC_MPP_AOUT_LVL_ABUS2 6 -#define PMIC_MPP_AOUT_LVL_ABUS3 7 - -/* To be used with "function" */ -#define PMIC_MPP_FUNC_NORMAL "normal" -#define PMIC_MPP_FUNC_PAIRED "paired" -#define PMIC_MPP_FUNC_DTEST1 "dtest1" -#define PMIC_MPP_FUNC_DTEST2 "dtest2" -#define PMIC_MPP_FUNC_DTEST3 "dtest3" -#define PMIC_MPP_FUNC_DTEST4 "dtest4" - -#endif diff --git a/include/dt-bindings/power/meson-a1-power.h b/include/dt-bindings/power/meson-a1-power.h deleted file mode 100644 index 8e39dfc0b62..00000000000 --- a/include/dt-bindings/power/meson-a1-power.h +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ -/* - * Copyright (c) 2023 SberDevices, Inc. - * Author: Alexey Romanov <avromanov@sberdevices.ru> - */ - -#ifndef _DT_BINDINGS_MESON_A1_POWER_H -#define _DT_BINDINGS_MESON_A1_POWER_H - -#define PWRC_DSPA_ID 8 -#define PWRC_DSPB_ID 9 -#define PWRC_UART_ID 10 -#define PWRC_DMC_ID 11 -#define PWRC_I2C_ID 12 -#define PWRC_PSRAM_ID 13 -#define PWRC_ACODEC_ID 14 -#define PWRC_AUDIO_ID 15 -#define PWRC_OTP_ID 16 -#define PWRC_DMA_ID 17 -#define PWRC_SD_EMMC_ID 18 -#define PWRC_RAMA_ID 19 -#define PWRC_RAMB_ID 20 -#define PWRC_IR_ID 21 -#define PWRC_SPICC_ID 22 -#define PWRC_SPIFC_ID 23 -#define PWRC_USB_ID 24 -#define PWRC_NIC_ID 25 -#define PWRC_PDMIN_ID 26 -#define PWRC_RSA_ID 27 -#define PWRC_MAX_ID 28 - -#endif diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h deleted file mode 100644 index 7f4e2983a4c..00000000000 --- a/include/dt-bindings/power/qcom-rpmpd.h +++ /dev/null @@ -1,412 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. */ - -#ifndef _DT_BINDINGS_POWER_QCOM_RPMPD_H -#define _DT_BINDINGS_POWER_QCOM_RPMPD_H - -/* SA8775P Power Domain Indexes */ -#define SA8775P_CX 0 -#define SA8775P_CX_AO 1 -#define SA8775P_DDR 2 -#define SA8775P_EBI 3 -#define SA8775P_GFX 4 -#define SA8775P_LCX 5 -#define SA8775P_LMX 6 -#define SA8775P_MMCX 7 -#define SA8775P_MMCX_AO 8 -#define SA8775P_MSS 9 -#define SA8775P_MX 10 -#define SA8775P_MX_AO 11 -#define SA8775P_MXC 12 -#define SA8775P_MXC_AO 13 -#define SA8775P_NSP0 14 -#define SA8775P_NSP1 15 -#define SA8775P_XO 16 - -/* SDM670 Power Domain Indexes */ -#define SDM670_MX 0 -#define SDM670_MX_AO 1 -#define SDM670_CX 2 -#define SDM670_CX_AO 3 -#define SDM670_LMX 4 -#define SDM670_LCX 5 -#define SDM670_GFX 6 -#define SDM670_MSS 7 - -/* SDM845 Power Domain Indexes */ -#define SDM845_EBI 0 -#define SDM845_MX 1 -#define SDM845_MX_AO 2 -#define SDM845_CX 3 -#define SDM845_CX_AO 4 -#define SDM845_LMX 5 -#define SDM845_LCX 6 -#define SDM845_GFX 7 -#define SDM845_MSS 8 - -/* SDX55 Power Domain Indexes */ -#define SDX55_MSS 0 -#define SDX55_MX 1 -#define SDX55_CX 2 - -/* SDX65 Power Domain Indexes */ -#define SDX65_MSS 0 -#define SDX65_MX 1 -#define SDX65_MX_AO 2 -#define SDX65_CX 3 -#define SDX65_CX_AO 4 -#define SDX65_MXC 5 - -/* SM6350 Power Domain Indexes */ -#define SM6350_CX 0 -#define SM6350_GFX 1 -#define SM6350_LCX 2 -#define SM6350_LMX 3 -#define SM6350_MSS 4 -#define SM6350_MX 5 - -/* SM6350 Power Domain Indexes */ -#define SM6375_VDDCX 0 -#define SM6375_VDDCX_AO 1 -#define SM6375_VDDCX_VFL 2 -#define SM6375_VDDMX 3 -#define SM6375_VDDMX_AO 4 -#define SM6375_VDDMX_VFL 5 -#define SM6375_VDDGX 6 -#define SM6375_VDDGX_AO 7 -#define SM6375_VDD_LPI_CX 8 -#define SM6375_VDD_LPI_MX 9 - -/* SM8150 Power Domain Indexes */ -#define SM8150_MSS 0 -#define SM8150_EBI 1 -#define SM8150_LMX 2 -#define SM8150_LCX 3 -#define SM8150_GFX 4 -#define SM8150_MX 5 -#define SM8150_MX_AO 6 -#define SM8150_CX 7 -#define SM8150_CX_AO 8 -#define SM8150_MMCX 9 -#define SM8150_MMCX_AO 10 - -/* SA8155P is a special case, kept for backwards compatibility */ -#define SA8155P_CX SM8150_CX -#define SA8155P_CX_AO SM8150_CX_AO -#define SA8155P_EBI SM8150_EBI -#define SA8155P_GFX SM8150_GFX -#define SA8155P_MSS SM8150_MSS -#define SA8155P_MX SM8150_MX -#define SA8155P_MX_AO SM8150_MX_AO - -/* SM8250 Power Domain Indexes */ -#define SM8250_CX 0 -#define SM8250_CX_AO 1 -#define SM8250_EBI 2 -#define SM8250_GFX 3 -#define SM8250_LCX 4 -#define SM8250_LMX 5 -#define SM8250_MMCX 6 -#define SM8250_MMCX_AO 7 -#define SM8250_MX 8 -#define SM8250_MX_AO 9 - -/* SM8350 Power Domain Indexes */ -#define SM8350_CX 0 -#define SM8350_CX_AO 1 -#define SM8350_EBI 2 -#define SM8350_GFX 3 -#define SM8350_LCX 4 -#define SM8350_LMX 5 -#define SM8350_MMCX 6 -#define SM8350_MMCX_AO 7 -#define SM8350_MX 8 -#define SM8350_MX_AO 9 -#define SM8350_MXC 10 -#define SM8350_MXC_AO 11 -#define SM8350_MSS 12 - -/* SM8450 Power Domain Indexes */ -#define SM8450_CX 0 -#define SM8450_CX_AO 1 -#define SM8450_EBI 2 -#define SM8450_GFX 3 -#define SM8450_LCX 4 -#define SM8450_LMX 5 -#define SM8450_MMCX 6 -#define SM8450_MMCX_AO 7 -#define SM8450_MX 8 -#define SM8450_MX_AO 9 -#define SM8450_MXC 10 -#define SM8450_MXC_AO 11 -#define SM8450_MSS 12 - -/* SM8550 Power Domain Indexes */ -#define SM8550_CX 0 -#define SM8550_CX_AO 1 -#define SM8550_EBI 2 -#define SM8550_GFX 3 -#define SM8550_LCX 4 -#define SM8550_LMX 5 -#define SM8550_MMCX 6 -#define SM8550_MMCX_AO 7 -#define SM8550_MX 8 -#define SM8550_MX_AO 9 -#define SM8550_MXC 10 -#define SM8550_MXC_AO 11 -#define SM8550_MSS 12 -#define SM8550_NSP 13 - -/* QDU1000/QRU1000 Power Domain Indexes */ -#define QDU1000_EBI 0 -#define QDU1000_MSS 1 -#define QDU1000_CX 2 -#define QDU1000_MX 3 - -/* SC7180 Power Domain Indexes */ -#define SC7180_CX 0 -#define SC7180_CX_AO 1 -#define SC7180_GFX 2 -#define SC7180_MX 3 -#define SC7180_MX_AO 4 -#define SC7180_LMX 5 -#define SC7180_LCX 6 -#define SC7180_MSS 7 - -/* SC7280 Power Domain Indexes */ -#define SC7280_CX 0 -#define SC7280_CX_AO 1 -#define SC7280_EBI 2 -#define SC7280_GFX 3 -#define SC7280_MX 4 -#define SC7280_MX_AO 5 -#define SC7280_LMX 6 -#define SC7280_LCX 7 -#define SC7280_MSS 8 - -/* SC8180X Power Domain Indexes */ -#define SC8180X_CX 0 -#define SC8180X_CX_AO 1 -#define SC8180X_EBI 2 -#define SC8180X_GFX 3 -#define SC8180X_LCX 4 -#define SC8180X_LMX 5 -#define SC8180X_MMCX 6 -#define SC8180X_MMCX_AO 7 -#define SC8180X_MSS 8 -#define SC8180X_MX 9 -#define SC8180X_MX_AO 10 - -/* SC8280XP Power Domain Indexes */ -#define SC8280XP_CX 0 -#define SC8280XP_CX_AO 1 -#define SC8280XP_DDR 2 -#define SC8280XP_EBI 3 -#define SC8280XP_GFX 4 -#define SC8280XP_LCX 5 -#define SC8280XP_LMX 6 -#define SC8280XP_MMCX 7 -#define SC8280XP_MMCX_AO 8 -#define SC8280XP_MSS 9 -#define SC8280XP_MX 10 -#define SC8280XP_MXC 12 -#define SC8280XP_MX_AO 11 -#define SC8280XP_NSP 13 -#define SC8280XP_QPHY 14 -#define SC8280XP_XO 15 - -/* SDM845 Power Domain performance levels */ -#define RPMH_REGULATOR_LEVEL_RETENTION 16 -#define RPMH_REGULATOR_LEVEL_MIN_SVS 48 -#define RPMH_REGULATOR_LEVEL_LOW_SVS_D2 52 -#define RPMH_REGULATOR_LEVEL_LOW_SVS_D1 56 -#define RPMH_REGULATOR_LEVEL_LOW_SVS_D0 60 -#define RPMH_REGULATOR_LEVEL_LOW_SVS 64 -#define RPMH_REGULATOR_LEVEL_LOW_SVS_P1 72 -#define RPMH_REGULATOR_LEVEL_LOW_SVS_L1 80 -#define RPMH_REGULATOR_LEVEL_LOW_SVS_L2 96 -#define RPMH_REGULATOR_LEVEL_SVS 128 -#define RPMH_REGULATOR_LEVEL_SVS_L0 144 -#define RPMH_REGULATOR_LEVEL_SVS_L1 192 -#define RPMH_REGULATOR_LEVEL_SVS_L2 224 -#define RPMH_REGULATOR_LEVEL_NOM 256 -#define RPMH_REGULATOR_LEVEL_NOM_L0 288 -#define RPMH_REGULATOR_LEVEL_NOM_L1 320 -#define RPMH_REGULATOR_LEVEL_NOM_L2 336 -#define RPMH_REGULATOR_LEVEL_TURBO 384 -#define RPMH_REGULATOR_LEVEL_TURBO_L0 400 -#define RPMH_REGULATOR_LEVEL_TURBO_L1 416 -#define RPMH_REGULATOR_LEVEL_TURBO_L2 432 -#define RPMH_REGULATOR_LEVEL_TURBO_L3 448 -#define RPMH_REGULATOR_LEVEL_SUPER_TURBO 464 -#define RPMH_REGULATOR_LEVEL_SUPER_TURBO_NO_CPR 480 - -/* MDM9607 Power Domains */ -#define MDM9607_VDDCX 0 -#define MDM9607_VDDCX_AO 1 -#define MDM9607_VDDCX_VFL 2 -#define MDM9607_VDDMX 3 -#define MDM9607_VDDMX_AO 4 -#define MDM9607_VDDMX_VFL 5 - -/* MSM8226 Power Domain Indexes */ -#define MSM8226_VDDCX 0 -#define MSM8226_VDDCX_AO 1 -#define MSM8226_VDDCX_VFC 2 - -/* MSM8939 Power Domains */ -#define MSM8939_VDDMDCX 0 -#define MSM8939_VDDMDCX_AO 1 -#define MSM8939_VDDMDCX_VFC 2 -#define MSM8939_VDDCX 3 -#define MSM8939_VDDCX_AO 4 -#define MSM8939_VDDCX_VFC 5 -#define MSM8939_VDDMX 6 -#define MSM8939_VDDMX_AO 7 - -/* MSM8916 Power Domain Indexes */ -#define MSM8916_VDDCX 0 -#define MSM8916_VDDCX_AO 1 -#define MSM8916_VDDCX_VFC 2 -#define MSM8916_VDDMX 3 -#define MSM8916_VDDMX_AO 4 - -/* MSM8909 Power Domain Indexes */ -#define MSM8909_VDDCX MSM8916_VDDCX -#define MSM8909_VDDCX_AO MSM8916_VDDCX_AO -#define MSM8909_VDDCX_VFC MSM8916_VDDCX_VFC -#define MSM8909_VDDMX MSM8916_VDDMX -#define MSM8909_VDDMX_AO MSM8916_VDDMX_AO - -/* MSM8917 Power Domain Indexes */ -#define MSM8917_VDDCX 0 -#define MSM8917_VDDCX_AO 1 -#define MSM8917_VDDCX_VFL 2 -#define MSM8917_VDDMX 3 -#define MSM8917_VDDMX_AO 4 - -/* MSM8937 Power Domain Indexes */ -#define MSM8937_VDDCX MSM8917_VDDCX -#define MSM8937_VDDCX_AO MSM8917_VDDCX_AO -#define MSM8937_VDDCX_VFL MSM8917_VDDCX_VFL -#define MSM8937_VDDMX MSM8917_VDDMX -#define MSM8937_VDDMX_AO MSM8917_VDDMX_AO - -/* QM215 Power Domain Indexes */ -#define QM215_VDDCX MSM8917_VDDCX -#define QM215_VDDCX_AO MSM8917_VDDCX_AO -#define QM215_VDDCX_VFL MSM8917_VDDCX_VFL -#define QM215_VDDMX MSM8917_VDDMX -#define QM215_VDDMX_AO MSM8917_VDDMX_AO - -/* MSM8953 Power Domain Indexes */ -#define MSM8953_VDDMD 0 -#define MSM8953_VDDMD_AO 1 -#define MSM8953_VDDCX 2 -#define MSM8953_VDDCX_AO 3 -#define MSM8953_VDDCX_VFL 4 -#define MSM8953_VDDMX 5 -#define MSM8953_VDDMX_AO 6 - -/* MSM8976 Power Domain Indexes */ -#define MSM8976_VDDCX 0 -#define MSM8976_VDDCX_AO 1 -#define MSM8976_VDDCX_VFL 2 -#define MSM8976_VDDMX 3 -#define MSM8976_VDDMX_AO 4 -#define MSM8976_VDDMX_VFL 5 - -/* MSM8994 Power Domain Indexes */ -#define MSM8994_VDDCX 0 -#define MSM8994_VDDCX_AO 1 -#define MSM8994_VDDCX_VFC 2 -#define MSM8994_VDDMX 3 -#define MSM8994_VDDMX_AO 4 -#define MSM8994_VDDGFX 5 -#define MSM8994_VDDGFX_VFC 6 - -/* MSM8996 Power Domain Indexes */ -#define MSM8996_VDDCX 0 -#define MSM8996_VDDCX_AO 1 -#define MSM8996_VDDCX_VFC 2 -#define MSM8996_VDDMX 3 -#define MSM8996_VDDMX_AO 4 -#define MSM8996_VDDSSCX 5 -#define MSM8996_VDDSSCX_VFC 6 - -/* MSM8998 Power Domain Indexes */ -#define MSM8998_VDDCX 0 -#define MSM8998_VDDCX_AO 1 -#define MSM8998_VDDCX_VFL 2 -#define MSM8998_VDDMX 3 -#define MSM8998_VDDMX_AO 4 -#define MSM8998_VDDMX_VFL 5 -#define MSM8998_SSCCX 6 -#define MSM8998_SSCCX_VFL 7 -#define MSM8998_SSCMX 8 -#define MSM8998_SSCMX_VFL 9 - -/* QCS404 Power Domains */ -#define QCS404_VDDMX 0 -#define QCS404_VDDMX_AO 1 -#define QCS404_VDDMX_VFL 2 -#define QCS404_LPICX 3 -#define QCS404_LPICX_VFL 4 -#define QCS404_LPIMX 5 -#define QCS404_LPIMX_VFL 6 - -/* SDM660 Power Domains */ -#define SDM660_VDDCX 0 -#define SDM660_VDDCX_AO 1 -#define SDM660_VDDCX_VFL 2 -#define SDM660_VDDMX 3 -#define SDM660_VDDMX_AO 4 -#define SDM660_VDDMX_VFL 5 -#define SDM660_SSCCX 6 -#define SDM660_SSCCX_VFL 7 -#define SDM660_SSCMX 8 -#define SDM660_SSCMX_VFL 9 - -/* SM6115 Power Domains */ -#define SM6115_VDDCX 0 -#define SM6115_VDDCX_AO 1 -#define SM6115_VDDCX_VFL 2 -#define SM6115_VDDMX 3 -#define SM6115_VDDMX_AO 4 -#define SM6115_VDDMX_VFL 5 -#define SM6115_VDD_LPI_CX 6 -#define SM6115_VDD_LPI_MX 7 - -/* SM6125 Power Domains */ -#define SM6125_VDDCX 0 -#define SM6125_VDDCX_AO 1 -#define SM6125_VDDCX_VFL 2 -#define SM6125_VDDMX 3 -#define SM6125_VDDMX_AO 4 -#define SM6125_VDDMX_VFL 5 - -/* QCM2290 Power Domains */ -#define QCM2290_VDDCX 0 -#define QCM2290_VDDCX_AO 1 -#define QCM2290_VDDCX_VFL 2 -#define QCM2290_VDDMX 3 -#define QCM2290_VDDMX_AO 4 -#define QCM2290_VDDMX_VFL 5 -#define QCM2290_VDD_LPI_CX 6 -#define QCM2290_VDD_LPI_MX 7 - -/* RPM SMD Power Domain performance levels */ -#define RPM_SMD_LEVEL_RETENTION 16 -#define RPM_SMD_LEVEL_RETENTION_PLUS 32 -#define RPM_SMD_LEVEL_MIN_SVS 48 -#define RPM_SMD_LEVEL_LOW_SVS 64 -#define RPM_SMD_LEVEL_SVS 128 -#define RPM_SMD_LEVEL_SVS_PLUS 192 -#define RPM_SMD_LEVEL_NOM 256 -#define RPM_SMD_LEVEL_NOM_PLUS 320 -#define RPM_SMD_LEVEL_TURBO 384 -#define RPM_SMD_LEVEL_TURBO_NO_CPR 416 -#define RPM_SMD_LEVEL_TURBO_HIGH 448 -#define RPM_SMD_LEVEL_BINNING 512 - -#endif diff --git a/include/dt-bindings/regulator/qcom,rpmh-regulator.h b/include/dt-bindings/regulator/qcom,rpmh-regulator.h deleted file mode 100644 index 86713dcf9e0..00000000000 --- a/include/dt-bindings/regulator/qcom,rpmh-regulator.h +++ /dev/null @@ -1,36 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. */ - -#ifndef __QCOM_RPMH_REGULATOR_H -#define __QCOM_RPMH_REGULATOR_H - -/* - * These mode constants may be used to specify modes for various RPMh regulator - * device tree properties (e.g. regulator-initial-mode). Each type of regulator - * supports a subset of the possible modes. - * - * %RPMH_REGULATOR_MODE_RET: Retention mode in which only an extremely small - * load current is allowed. This mode is supported - * by LDO and SMPS type regulators. - * %RPMH_REGULATOR_MODE_LPM: Low power mode in which a small load current is - * allowed. This mode corresponds to PFM for SMPS - * and BOB type regulators. This mode is supported - * by LDO, HFSMPS, BOB, and PMIC4 FTSMPS type - * regulators. - * %RPMH_REGULATOR_MODE_AUTO: Auto mode in which the regulator hardware - * automatically switches between LPM and HPM based - * upon the real-time load current. This mode is - * supported by HFSMPS, BOB, and PMIC4 FTSMPS type - * regulators. - * %RPMH_REGULATOR_MODE_HPM: High power mode in which the full rated current - * of the regulator is allowed. This mode - * corresponds to PWM for SMPS and BOB type - * regulators. This mode is supported by all types - * of regulators. - */ -#define RPMH_REGULATOR_MODE_RET 0 -#define RPMH_REGULATOR_MODE_LPM 1 -#define RPMH_REGULATOR_MODE_AUTO 2 -#define RPMH_REGULATOR_MODE_HPM 3 - -#endif diff --git a/include/dt-bindings/reset/amlogic,meson-a1-reset.h b/include/dt-bindings/reset/amlogic,meson-a1-reset.h deleted file mode 100644 index 2c749c655e1..00000000000 --- a/include/dt-bindings/reset/amlogic,meson-a1-reset.h +++ /dev/null @@ -1,76 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2019 Amlogic, Inc. All rights reserved. - * Author: Xingyu Chen <xingyu.chen@amlogic.com> - * - * Copyright (c) 2023, SberDevices, Inc. - * Author: Alexey Romanov <avromanov@salutedevices.com> - */ - -#ifndef _DT_BINDINGS_AMLOGIC_MESON_A1_RESET_H -#define _DT_BINDINGS_AMLOGIC_MESON_A1_RESET_H - -/* RESET0 */ -/* 0 */ -#define RESET_AM2AXI_VAD 1 -/* 2-3 */ -#define RESET_PSRAM 4 -#define RESET_PAD_CTRL 5 -/* 6 */ -#define RESET_TEMP_SENSOR 7 -#define RESET_AM2AXI_DEV 8 -/* 9 */ -#define RESET_SPICC_A 10 -#define RESET_MSR_CLK 11 -#define RESET_AUDIO 12 -#define RESET_ANALOG_CTRL 13 -#define RESET_SAR_ADC 14 -#define RESET_AUDIO_VAD 15 -#define RESET_CEC 16 -#define RESET_PWM_EF 17 -#define RESET_PWM_CD 18 -#define RESET_PWM_AB 19 -/* 20 */ -#define RESET_IR_CTRL 21 -#define RESET_I2C_S_A 22 -/* 23 */ -#define RESET_I2C_M_D 24 -#define RESET_I2C_M_C 25 -#define RESET_I2C_M_B 26 -#define RESET_I2C_M_A 27 -#define RESET_I2C_PROD_AHB 28 -#define RESET_I2C_PROD 29 -/* 30-31 */ - -/* RESET1 */ -#define RESET_ACODEC 32 -#define RESET_DMA 33 -#define RESET_SD_EMMC_A 34 -/* 35 */ -#define RESET_USBCTRL 36 -/* 37 */ -#define RESET_USBPHY 38 -/* 39-41 */ -#define RESET_RSA 42 -#define RESET_DMC 43 -/* 44 */ -#define RESET_IRQ_CTRL 45 -/* 46 */ -#define RESET_NIC_VAD 47 -#define RESET_NIC_AXI 48 -#define RESET_RAMA 49 -#define RESET_RAMB 50 -/* 51-52 */ -#define RESET_ROM 53 -#define RESET_SPIFC 54 -#define RESET_GIC 55 -#define RESET_UART_C 56 -#define RESET_UART_B 57 -#define RESET_UART_A 58 -#define RESET_OSC_RING 59 -/* 60-63 */ - -/* RESET2 */ -/* 64-95 */ - -#endif diff --git a/include/dt-bindings/reset/qcom,gcc-msm8916.h b/include/dt-bindings/reset/qcom,gcc-msm8916.h deleted file mode 100644 index 1f9be10872d..00000000000 --- a/include/dt-bindings/reset/qcom,gcc-msm8916.h +++ /dev/null @@ -1,100 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2015 Linaro Limited - */ - -#ifndef _DT_BINDINGS_RESET_MSM_GCC_8916_H -#define _DT_BINDINGS_RESET_MSM_GCC_8916_H - -#define GCC_BLSP1_BCR 0 -#define GCC_BLSP1_QUP1_BCR 1 -#define GCC_BLSP1_UART1_BCR 2 -#define GCC_BLSP1_QUP2_BCR 3 -#define GCC_BLSP1_UART2_BCR 4 -#define GCC_BLSP1_QUP3_BCR 5 -#define GCC_BLSP1_QUP4_BCR 6 -#define GCC_BLSP1_QUP5_BCR 7 -#define GCC_BLSP1_QUP6_BCR 8 -#define GCC_IMEM_BCR 9 -#define GCC_SMMU_BCR 10 -#define GCC_APSS_TCU_BCR 11 -#define GCC_SMMU_XPU_BCR 12 -#define GCC_PCNOC_TBU_BCR 13 -#define GCC_PRNG_BCR 14 -#define GCC_BOOT_ROM_BCR 15 -#define GCC_CRYPTO_BCR 16 -#define GCC_SEC_CTRL_BCR 17 -#define GCC_AUDIO_CORE_BCR 18 -#define GCC_ULT_AUDIO_BCR 19 -#define GCC_DEHR_BCR 20 -#define GCC_SYSTEM_NOC_BCR 21 -#define GCC_PCNOC_BCR 22 -#define GCC_TCSR_BCR 23 -#define GCC_QDSS_BCR 24 -#define GCC_DCD_BCR 25 -#define GCC_MSG_RAM_BCR 26 -#define GCC_MPM_BCR 27 -#define GCC_SPMI_BCR 28 -#define GCC_SPDM_BCR 29 -#define GCC_MM_SPDM_BCR 30 -#define GCC_BIMC_BCR 31 -#define GCC_RBCPR_BCR 32 -#define GCC_TLMM_BCR 33 -#define GCC_USB_HS_BCR 34 -#define GCC_USB2A_PHY_BCR 35 -#define GCC_SDCC1_BCR 36 -#define GCC_SDCC2_BCR 37 -#define GCC_PDM_BCR 38 -#define GCC_SNOC_BUS_TIMEOUT0_BCR 39 -#define GCC_PCNOC_BUS_TIMEOUT0_BCR 40 -#define GCC_PCNOC_BUS_TIMEOUT1_BCR 41 -#define GCC_PCNOC_BUS_TIMEOUT2_BCR 42 -#define GCC_PCNOC_BUS_TIMEOUT3_BCR 43 -#define GCC_PCNOC_BUS_TIMEOUT4_BCR 44 -#define GCC_PCNOC_BUS_TIMEOUT5_BCR 45 -#define GCC_PCNOC_BUS_TIMEOUT6_BCR 46 -#define GCC_PCNOC_BUS_TIMEOUT7_BCR 47 -#define GCC_PCNOC_BUS_TIMEOUT8_BCR 48 -#define GCC_PCNOC_BUS_TIMEOUT9_BCR 49 -#define GCC_MMSS_BCR 50 -#define GCC_VENUS0_BCR 51 -#define GCC_MDSS_BCR 52 -#define GCC_CAMSS_PHY0_BCR 53 -#define GCC_CAMSS_CSI0_BCR 54 -#define GCC_CAMSS_CSI0PHY_BCR 55 -#define GCC_CAMSS_CSI0RDI_BCR 56 -#define GCC_CAMSS_CSI0PIX_BCR 57 -#define GCC_CAMSS_PHY1_BCR 58 -#define GCC_CAMSS_CSI1_BCR 59 -#define GCC_CAMSS_CSI1PHY_BCR 60 -#define GCC_CAMSS_CSI1RDI_BCR 61 -#define GCC_CAMSS_CSI1PIX_BCR 62 -#define GCC_CAMSS_ISPIF_BCR 63 -#define GCC_CAMSS_CCI_BCR 64 -#define GCC_CAMSS_MCLK0_BCR 65 -#define GCC_CAMSS_MCLK1_BCR 66 -#define GCC_CAMSS_GP0_BCR 67 -#define GCC_CAMSS_GP1_BCR 68 -#define GCC_CAMSS_TOP_BCR 69 -#define GCC_CAMSS_MICRO_BCR 70 -#define GCC_CAMSS_JPEG_BCR 71 -#define GCC_CAMSS_VFE_BCR 72 -#define GCC_CAMSS_CSI_VFE0_BCR 73 -#define GCC_OXILI_BCR 74 -#define GCC_GMEM_BCR 75 -#define GCC_CAMSS_AHB_BCR 76 -#define GCC_MDP_TBU_BCR 77 -#define GCC_GFX_TBU_BCR 78 -#define GCC_GFX_TCU_BCR 79 -#define GCC_MSS_TBU_AXI_BCR 80 -#define GCC_MSS_TBU_GSS_AXI_BCR 81 -#define GCC_MSS_TBU_Q6_AXI_BCR 82 -#define GCC_GTCU_AHB_BCR 83 -#define GCC_SMMU_CFG_BCR 84 -#define GCC_VFE_TBU_BCR 85 -#define GCC_VENUS_TBU_BCR 86 -#define GCC_JPEG_TBU_BCR 87 -#define GCC_PRONTO_TBU_BCR 88 -#define GCC_SMMU_CATS_BCR 89 - -#endif diff --git a/include/dt-bindings/reset/qcom,sdm845-aoss.h b/include/dt-bindings/reset/qcom,sdm845-aoss.h deleted file mode 100644 index 476c5fc873b..00000000000 --- a/include/dt-bindings/reset/qcom,sdm845-aoss.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2018 The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_RESET_AOSS_SDM_845_H -#define _DT_BINDINGS_RESET_AOSS_SDM_845_H - -#define AOSS_CC_MSS_RESTART 0 -#define AOSS_CC_CAMSS_RESTART 1 -#define AOSS_CC_VENUS_RESTART 2 -#define AOSS_CC_GPU_RESTART 3 -#define AOSS_CC_DISPSS_RESTART 4 -#define AOSS_CC_WCSS_RESTART 5 -#define AOSS_CC_LPASS_RESTART 6 - -#endif diff --git a/include/dt-bindings/reset/qcom,sdm845-pdc.h b/include/dt-bindings/reset/qcom,sdm845-pdc.h deleted file mode 100644 index 03a0c0eb814..00000000000 --- a/include/dt-bindings/reset/qcom,sdm845-pdc.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2018 The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_RESET_PDC_SDM_845_H -#define _DT_BINDINGS_RESET_PDC_SDM_845_H - -#define PDC_APPS_SYNC_RESET 0 -#define PDC_SP_SYNC_RESET 1 -#define PDC_AUDIO_SYNC_RESET 2 -#define PDC_SENSORS_SYNC_RESET 3 -#define PDC_AOP_SYNC_RESET 4 -#define PDC_DEBUG_SYNC_RESET 5 -#define PDC_GPU_SYNC_RESET 6 -#define PDC_DISPLAY_SYNC_RESET 7 -#define PDC_COMPUTE_SYNC_RESET 8 -#define PDC_MODEM_SYNC_RESET 9 -#define PDC_WLAN_RF_SYNC_RESET 10 -#define PDC_WPSS_SYNC_RESET 11 - -#endif diff --git a/include/dt-bindings/reset/starfive,jh7110-crg.h b/include/dt-bindings/reset/starfive,jh7110-crg.h deleted file mode 100644 index 1d596581da7..00000000000 --- a/include/dt-bindings/reset/starfive,jh7110-crg.h +++ /dev/null @@ -1,183 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2022 StarFive Technology Co., Ltd. - * - * Author: Yanhong Wang <yanhong.wang@starfivetech.com> - */ - -#ifndef __DT_BINDINGS_RESET_STARFIVE_JH7110_H__ -#define __DT_BINDINGS_RESET_STARFIVE_JH7110_H__ - -/* SYSCRG resets */ -#define JH7110_SYSRST_JTAG2APB 0 -#define JH7110_SYSRST_SYSCON 1 -#define JH7110_SYSRST_IOMUX_APB 2 -#define JH7110_SYSRST_BUS 3 -#define JH7110_SYSRST_DEBUG 4 -#define JH7110_SYSRST_CORE0 5 -#define JH7110_SYSRST_CORE1 6 -#define JH7110_SYSRST_CORE2 7 -#define JH7110_SYSRST_CORE3 8 -#define JH7110_SYSRST_CORE4 9 -#define JH7110_SYSRST_CORE0_ST 10 -#define JH7110_SYSRST_CORE1_ST 11 -#define JH7110_SYSRST_CORE2_ST 12 -#define JH7110_SYSRST_CORE3_ST 13 -#define JH7110_SYSRST_CORE4_ST 14 -#define JH7110_SYSRST_TRACE0 15 -#define JH7110_SYSRST_TRACE1 16 -#define JH7110_SYSRST_TRACE2 17 -#define JH7110_SYSRST_TRACE3 18 -#define JH7110_SYSRST_TRACE4 19 -#define JH7110_SYSRST_TRACE_COM 20 -#define JH7110_SYSRST_GPU_APB 21 -#define JH7110_SYSRST_GPU_DOMA 22 -#define JH7110_SYSRST_NOC_BUS_APB_BUS 23 -#define JH7110_SYSRST_NOC_BUS_AXICFG0_AXI 24 -#define JH7110_SYSRST_NOC_BUS_CPU_AXI 25 -#define JH7110_SYSRST_NOC_BUS_DISP_AXI 26 -#define JH7110_SYSRST_NOC_BUS_GPU_AXI 27 -#define JH7110_SYSRST_NOC_BUS_ISP_AXI 28 -#define JH7110_SYSRST_NOC_BUS_DDRC 29 -#define JH7110_SYSRST_NOC_BUS_STG_AXI 30 -#define JH7110_SYSRST_NOC_BUS_VDEC_AXI 31 - -#define JH7110_SYSRST_NOC_BUS_VENC_AXI 32 -#define JH7110_SYSRST_AXI_CFG1_DEC_AHB 33 -#define JH7110_SYSRST_AXI_CFG1_DEC_MAIN 34 -#define JH7110_SYSRST_AXI_CFG0_DEC_MAIN 35 -#define JH7110_SYSRST_AXI_CFG0_DEC_MAIN_DIV 36 -#define JH7110_SYSRST_AXI_CFG0_DEC_HIFI4 37 -#define JH7110_SYSRST_DDR_AXI 38 -#define JH7110_SYSRST_DDR_OSC 39 -#define JH7110_SYSRST_DDR_APB 40 -#define JH7110_SYSRST_DOM_ISP_TOP_N 41 -#define JH7110_SYSRST_DOM_ISP_TOP_AXI 42 -#define JH7110_SYSRST_DOM_VOUT_TOP_SRC 43 -#define JH7110_SYSRST_CODAJ12_AXI 44 -#define JH7110_SYSRST_CODAJ12_CORE 45 -#define JH7110_SYSRST_CODAJ12_APB 46 -#define JH7110_SYSRST_WAVE511_AXI 47 -#define JH7110_SYSRST_WAVE511_BPU 48 -#define JH7110_SYSRST_WAVE511_VCE 49 -#define JH7110_SYSRST_WAVE511_APB 50 -#define JH7110_SYSRST_VDEC_JPG_ARB_JPG 51 -#define JH7110_SYSRST_VDEC_JPG_ARB_MAIN 52 -#define JH7110_SYSRST_AXIMEM0_AXI 53 -#define JH7110_SYSRST_WAVE420L_AXI 54 -#define JH7110_SYSRST_WAVE420L_BPU 55 -#define JH7110_SYSRST_WAVE420L_VCE 56 -#define JH7110_SYSRST_WAVE420L_APB 57 -#define JH7110_SYSRST_AXIMEM1_AXI 58 -#define JH7110_SYSRST_AXIMEM2_AXI 59 -#define JH7110_SYSRST_INTMEM 60 -#define JH7110_SYSRST_QSPI_AHB 61 -#define JH7110_SYSRST_QSPI_APB 62 -#define JH7110_SYSRST_QSPI_REF 63 - -#define JH7110_SYSRST_SDIO0_AHB 64 -#define JH7110_SYSRST_SDIO1_AHB 65 -#define JH7110_SYSRST_GMAC1_AXI 66 -#define JH7110_SYSRST_GMAC1_AHB 67 -#define JH7110_SYSRST_MAILBOX 68 -#define JH7110_SYSRST_SPI0_APB 69 -#define JH7110_SYSRST_SPI1_APB 70 -#define JH7110_SYSRST_SPI2_APB 71 -#define JH7110_SYSRST_SPI3_APB 72 -#define JH7110_SYSRST_SPI4_APB 73 -#define JH7110_SYSRST_SPI5_APB 74 -#define JH7110_SYSRST_SPI6_APB 75 -#define JH7110_SYSRST_I2C0_APB 76 -#define JH7110_SYSRST_I2C1_APB 77 -#define JH7110_SYSRST_I2C2_APB 78 -#define JH7110_SYSRST_I2C3_APB 79 -#define JH7110_SYSRST_I2C4_APB 80 -#define JH7110_SYSRST_I2C5_APB 81 -#define JH7110_SYSRST_I2C6_APB 82 -#define JH7110_SYSRST_UART0_APB 83 -#define JH7110_SYSRST_UART0_CORE 84 -#define JH7110_SYSRST_UART1_APB 85 -#define JH7110_SYSRST_UART1_CORE 86 -#define JH7110_SYSRST_UART2_APB 87 -#define JH7110_SYSRST_UART2_CORE 88 -#define JH7110_SYSRST_UART3_APB 89 -#define JH7110_SYSRST_UART3_CORE 90 -#define JH7110_SYSRST_UART4_APB 91 -#define JH7110_SYSRST_UART4_CORE 92 -#define JH7110_SYSRST_UART5_APB 93 -#define JH7110_SYSRST_UART5_CORE 94 -#define JH7110_SYSRST_SPDIF_APB 95 - -#define JH7110_SYSRST_PWMDAC_APB 96 -#define JH7110_SYSRST_PDM_DMIC 97 -#define JH7110_SYSRST_PDM_APB 98 -#define JH7110_SYSRST_I2SRX_APB 99 -#define JH7110_SYSRST_I2SRX_BCLK 100 -#define JH7110_SYSRST_I2STX0_APB 101 -#define JH7110_SYSRST_I2STX0_BCLK 102 -#define JH7110_SYSRST_I2STX1_APB 103 -#define JH7110_SYSRST_I2STX1_BCLK 104 -#define JH7110_SYSRST_TDM_AHB 105 -#define JH7110_SYSRST_TDM_CORE 106 -#define JH7110_SYSRST_TDM_APB 107 -#define JH7110_SYSRST_PWM_APB 108 -#define JH7110_SYSRST_WDT_APB 109 -#define JH7110_SYSRST_WDT_CORE 110 -#define JH7110_SYSRST_CAN0_APB 111 -#define JH7110_SYSRST_CAN0_CORE 112 -#define JH7110_SYSRST_CAN0_TIMER 113 -#define JH7110_SYSRST_CAN1_APB 114 -#define JH7110_SYSRST_CAN1_CORE 115 -#define JH7110_SYSRST_CAN1_TIMER 116 -#define JH7110_SYSRST_TIMER_APB 117 -#define JH7110_SYSRST_TIMER0 118 -#define JH7110_SYSRST_TIMER1 119 -#define JH7110_SYSRST_TIMER2 120 -#define JH7110_SYSRST_TIMER3 121 -#define JH7110_SYSRST_INT_CTRL_APB 122 -#define JH7110_SYSRST_TEMP_APB 123 -#define JH7110_SYSRST_TEMP_CORE 124 -#define JH7110_SYSRST_JTAG_CERTIFICATION 125 - -#define JH7110_SYSRST_END 126 - -/* AONCRG resets */ -#define JH7110_AONRST_GMAC0_AXI 0 -#define JH7110_AONRST_GMAC0_AHB 1 -#define JH7110_AONRST_IOMUX 2 -#define JH7110_AONRST_PMU_APB 3 -#define JH7110_AONRST_PMU_WKUP 4 -#define JH7110_AONRST_RTC_APB 5 -#define JH7110_AONRST_RTC_CAL 6 -#define JH7110_AONRST_RTC_32K 7 - -#define JH7110_AONRST_END 8 - -/* STGCRG resets */ -#define JH7110_STGRST_SYSCON_PRESETN 0 -#define JH7110_STGRST_HIFI4_CORE 1 -#define JH7110_STGRST_HIFI4_AXI 2 -#define JH7110_STGRST_SEC_TOP_HRESETN 3 -#define JH7110_STGRST_E24_CORE 4 -#define JH7110_STGRST_DMA1P_AXI 5 -#define JH7110_STGRST_DMA1P_AHB 6 -#define JH7110_STGRST_USB_AXI 7 -#define JH7110_STGRST_USB_APB 8 -#define JH7110_STGRST_USB_UTMI_APB 9 -#define JH7110_STGRST_USB_PWRUP 10 -#define JH7110_STGRST_PCIE0_MST0 11 -#define JH7110_STGRST_PCIE0_SLV0 12 -#define JH7110_STGRST_PCIE0_SLV 13 -#define JH7110_STGRST_PCIE0_BRG 14 -#define JH7110_STGRST_PCIE0_CORE 15 -#define JH7110_STGRST_PCIE0_APB 16 -#define JH7110_STGRST_PCIE1_MST0 17 -#define JH7110_STGRST_PCIE1_SLV0 18 -#define JH7110_STGRST_PCIE1_SLV 19 -#define JH7110_STGRST_PCIE1_BRG 20 -#define JH7110_STGRST_PCIE1_CORE 21 -#define JH7110_STGRST_PCIE1_APB 22 - -#define JH7110_STGRST_END 23 - -#endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_H__ */ diff --git a/include/dt-bindings/soc/qcom,apr.h b/include/dt-bindings/soc/qcom,apr.h deleted file mode 100644 index 006362400c0..00000000000 --- a/include/dt-bindings/soc/qcom,apr.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_BINDINGS_QCOM_APR_H -#define __DT_BINDINGS_QCOM_APR_H - -/* Domain IDs */ -#define APR_DOMAIN_SIM 0x1 -#define APR_DOMAIN_PC 0x2 -#define APR_DOMAIN_MODEM 0x3 -#define APR_DOMAIN_ADSP 0x4 -#define APR_DOMAIN_APPS 0x5 -#define APR_DOMAIN_MAX 0x6 - -/* ADSP service IDs */ -#define APR_SVC_ADSP_CORE 0x3 -#define APR_SVC_AFE 0x4 -#define APR_SVC_VSM 0x5 -#define APR_SVC_VPM 0x6 -#define APR_SVC_ASM 0x7 -#define APR_SVC_ADM 0x8 -#define APR_SVC_ADSP_MVM 0x09 -#define APR_SVC_ADSP_CVS 0x0A -#define APR_SVC_ADSP_CVP 0x0B -#define APR_SVC_USM 0x0C -#define APR_SVC_LSM 0x0D -#define APR_SVC_VIDC 0x16 -#define APR_SVC_MAX 0x17 - -#endif /* __DT_BINDINGS_QCOM_APR_H */ diff --git a/include/dt-bindings/soc/qcom,rpmh-rsc.h b/include/dt-bindings/soc/qcom,rpmh-rsc.h deleted file mode 100644 index 868f998ea99..00000000000 --- a/include/dt-bindings/soc/qcom,rpmh-rsc.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. - */ - -#ifndef __DT_QCOM_RPMH_RSC_H__ -#define __DT_QCOM_RPMH_RSC_H__ - -#define SLEEP_TCS 0 -#define WAKE_TCS 1 -#define ACTIVE_TCS 2 -#define CONTROL_TCS 3 - -#endif /* __DT_QCOM_RPMH_RSC_H__ */ diff --git a/include/dt-bindings/sound/qcom,lpass.h b/include/dt-bindings/sound/qcom,lpass.h deleted file mode 100644 index a9404c3b888..00000000000 --- a/include/dt-bindings/sound/qcom,lpass.h +++ /dev/null @@ -1,46 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_QCOM_LPASS_H -#define __DT_QCOM_LPASS_H - -#define MI2S_PRIMARY 0 -#define MI2S_SECONDARY 1 -#define MI2S_TERTIARY 2 -#define MI2S_QUATERNARY 3 -#define MI2S_QUINARY 4 - -#define LPASS_DP_RX 5 - -#define LPASS_CDC_DMA_RX0 6 -#define LPASS_CDC_DMA_RX1 7 -#define LPASS_CDC_DMA_RX2 8 -#define LPASS_CDC_DMA_RX3 9 -#define LPASS_CDC_DMA_RX4 10 -#define LPASS_CDC_DMA_RX5 11 -#define LPASS_CDC_DMA_RX6 12 -#define LPASS_CDC_DMA_RX7 13 -#define LPASS_CDC_DMA_RX8 14 -#define LPASS_CDC_DMA_RX9 15 - -#define LPASS_CDC_DMA_TX0 16 -#define LPASS_CDC_DMA_TX1 17 -#define LPASS_CDC_DMA_TX2 18 -#define LPASS_CDC_DMA_TX3 19 -#define LPASS_CDC_DMA_TX4 20 -#define LPASS_CDC_DMA_TX5 21 -#define LPASS_CDC_DMA_TX6 22 -#define LPASS_CDC_DMA_TX7 23 -#define LPASS_CDC_DMA_TX8 24 - -#define LPASS_CDC_DMA_VA_TX0 25 -#define LPASS_CDC_DMA_VA_TX1 26 -#define LPASS_CDC_DMA_VA_TX2 27 -#define LPASS_CDC_DMA_VA_TX3 28 -#define LPASS_CDC_DMA_VA_TX4 29 -#define LPASS_CDC_DMA_VA_TX5 30 -#define LPASS_CDC_DMA_VA_TX6 31 -#define LPASS_CDC_DMA_VA_TX7 32 -#define LPASS_CDC_DMA_VA_TX8 33 - -#define LPASS_MCLK0 0 - -#endif /* __DT_QCOM_LPASS_H */ diff --git a/include/dt-bindings/sound/qcom,q6afe.h b/include/dt-bindings/sound/qcom,q6afe.h deleted file mode 100644 index 9d5d89cfabc..00000000000 --- a/include/dt-bindings/sound/qcom,q6afe.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_BINDINGS_Q6_AFE_H__ -#define __DT_BINDINGS_Q6_AFE_H__ - -/* This file exists due to backward compatibility reasons, Please do not DELETE! */ - -#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> - -#endif /* __DT_BINDINGS_Q6_AFE_H__ */ diff --git a/include/dt-bindings/sound/qcom,q6asm.h b/include/dt-bindings/sound/qcom,q6asm.h deleted file mode 100644 index f59d74f1439..00000000000 --- a/include/dt-bindings/sound/qcom,q6asm.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_BINDINGS_Q6_ASM_H__ -#define __DT_BINDINGS_Q6_ASM_H__ - -#define MSM_FRONTEND_DAI_MULTIMEDIA1 0 -#define MSM_FRONTEND_DAI_MULTIMEDIA2 1 -#define MSM_FRONTEND_DAI_MULTIMEDIA3 2 -#define MSM_FRONTEND_DAI_MULTIMEDIA4 3 -#define MSM_FRONTEND_DAI_MULTIMEDIA5 4 -#define MSM_FRONTEND_DAI_MULTIMEDIA6 5 -#define MSM_FRONTEND_DAI_MULTIMEDIA7 6 -#define MSM_FRONTEND_DAI_MULTIMEDIA8 7 -#define MSM_FRONTEND_DAI_MULTIMEDIA9 8 -#define MSM_FRONTEND_DAI_MULTIMEDIA10 9 -#define MSM_FRONTEND_DAI_MULTIMEDIA11 10 -#define MSM_FRONTEND_DAI_MULTIMEDIA12 11 -#define MSM_FRONTEND_DAI_MULTIMEDIA13 12 -#define MSM_FRONTEND_DAI_MULTIMEDIA14 13 -#define MSM_FRONTEND_DAI_MULTIMEDIA15 14 -#define MSM_FRONTEND_DAI_MULTIMEDIA16 15 - -#define Q6ASM_DAI_TX_RX 0 -#define Q6ASM_DAI_TX 1 -#define Q6ASM_DAI_RX 2 - -#endif /* __DT_BINDINGS_Q6_ASM_H__ */ diff --git a/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h b/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h deleted file mode 100644 index 39f203256c4..00000000000 --- a/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h +++ /dev/null @@ -1,234 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_BINDINGS_Q6_AUDIO_PORTS_H__ -#define __DT_BINDINGS_Q6_AUDIO_PORTS_H__ - -/* LPASS Audio virtual ports IDs */ -#define HDMI_RX 1 -#define SLIMBUS_0_RX 2 -#define SLIMBUS_0_TX 3 -#define SLIMBUS_1_RX 4 -#define SLIMBUS_1_TX 5 -#define SLIMBUS_2_RX 6 -#define SLIMBUS_2_TX 7 -#define SLIMBUS_3_RX 8 -#define SLIMBUS_3_TX 9 -#define SLIMBUS_4_RX 10 -#define SLIMBUS_4_TX 11 -#define SLIMBUS_5_RX 12 -#define SLIMBUS_5_TX 13 -#define SLIMBUS_6_RX 14 -#define SLIMBUS_6_TX 15 -#define PRIMARY_MI2S_RX 16 -#define PRIMARY_MI2S_TX 17 -#define SECONDARY_MI2S_RX 18 -#define SECONDARY_MI2S_TX 19 -#define TERTIARY_MI2S_RX 20 -#define TERTIARY_MI2S_TX 21 -#define QUATERNARY_MI2S_RX 22 -#define QUATERNARY_MI2S_TX 23 -#define PRIMARY_TDM_RX_0 24 -#define PRIMARY_TDM_TX_0 25 -#define PRIMARY_TDM_RX_1 26 -#define PRIMARY_TDM_TX_1 27 -#define PRIMARY_TDM_RX_2 28 -#define PRIMARY_TDM_TX_2 29 -#define PRIMARY_TDM_RX_3 30 -#define PRIMARY_TDM_TX_3 31 -#define PRIMARY_TDM_RX_4 32 -#define PRIMARY_TDM_TX_4 33 -#define PRIMARY_TDM_RX_5 34 -#define PRIMARY_TDM_TX_5 35 -#define PRIMARY_TDM_RX_6 36 -#define PRIMARY_TDM_TX_6 37 -#define PRIMARY_TDM_RX_7 38 -#define PRIMARY_TDM_TX_7 39 -#define SECONDARY_TDM_RX_0 40 -#define SECONDARY_TDM_TX_0 41 -#define SECONDARY_TDM_RX_1 42 -#define SECONDARY_TDM_TX_1 43 -#define SECONDARY_TDM_RX_2 44 -#define SECONDARY_TDM_TX_2 45 -#define SECONDARY_TDM_RX_3 46 -#define SECONDARY_TDM_TX_3 47 -#define SECONDARY_TDM_RX_4 48 -#define SECONDARY_TDM_TX_4 49 -#define SECONDARY_TDM_RX_5 50 -#define SECONDARY_TDM_TX_5 51 -#define SECONDARY_TDM_RX_6 52 -#define SECONDARY_TDM_TX_6 53 -#define SECONDARY_TDM_RX_7 54 -#define SECONDARY_TDM_TX_7 55 -#define TERTIARY_TDM_RX_0 56 -#define TERTIARY_TDM_TX_0 57 -#define TERTIARY_TDM_RX_1 58 -#define TERTIARY_TDM_TX_1 59 -#define TERTIARY_TDM_RX_2 60 -#define TERTIARY_TDM_TX_2 61 -#define TERTIARY_TDM_RX_3 62 -#define TERTIARY_TDM_TX_3 63 -#define TERTIARY_TDM_RX_4 64 -#define TERTIARY_TDM_TX_4 65 -#define TERTIARY_TDM_RX_5 66 -#define TERTIARY_TDM_TX_5 67 -#define TERTIARY_TDM_RX_6 68 -#define TERTIARY_TDM_TX_6 69 -#define TERTIARY_TDM_RX_7 70 -#define TERTIARY_TDM_TX_7 71 -#define QUATERNARY_TDM_RX_0 72 -#define QUATERNARY_TDM_TX_0 73 -#define QUATERNARY_TDM_RX_1 74 -#define QUATERNARY_TDM_TX_1 75 -#define QUATERNARY_TDM_RX_2 76 -#define QUATERNARY_TDM_TX_2 77 -#define QUATERNARY_TDM_RX_3 78 -#define QUATERNARY_TDM_TX_3 79 -#define QUATERNARY_TDM_RX_4 80 -#define QUATERNARY_TDM_TX_4 81 -#define QUATERNARY_TDM_RX_5 82 -#define QUATERNARY_TDM_TX_5 83 -#define QUATERNARY_TDM_RX_6 84 -#define QUATERNARY_TDM_TX_6 85 -#define QUATERNARY_TDM_RX_7 86 -#define QUATERNARY_TDM_TX_7 87 -#define QUINARY_TDM_RX_0 88 -#define QUINARY_TDM_TX_0 89 -#define QUINARY_TDM_RX_1 90 -#define QUINARY_TDM_TX_1 91 -#define QUINARY_TDM_RX_2 92 -#define QUINARY_TDM_TX_2 93 -#define QUINARY_TDM_RX_3 94 -#define QUINARY_TDM_TX_3 95 -#define QUINARY_TDM_RX_4 96 -#define QUINARY_TDM_TX_4 97 -#define QUINARY_TDM_RX_5 98 -#define QUINARY_TDM_TX_5 99 -#define QUINARY_TDM_RX_6 100 -#define QUINARY_TDM_TX_6 101 -#define QUINARY_TDM_RX_7 102 -#define QUINARY_TDM_TX_7 103 -#define DISPLAY_PORT_RX 104 -#define WSA_CODEC_DMA_RX_0 105 -#define WSA_CODEC_DMA_TX_0 106 -#define WSA_CODEC_DMA_RX_1 107 -#define WSA_CODEC_DMA_TX_1 108 -#define WSA_CODEC_DMA_TX_2 109 -#define VA_CODEC_DMA_TX_0 110 -#define VA_CODEC_DMA_TX_1 111 -#define VA_CODEC_DMA_TX_2 112 -#define RX_CODEC_DMA_RX_0 113 -#define TX_CODEC_DMA_TX_0 114 -#define RX_CODEC_DMA_RX_1 115 -#define TX_CODEC_DMA_TX_1 116 -#define RX_CODEC_DMA_RX_2 117 -#define TX_CODEC_DMA_TX_2 118 -#define RX_CODEC_DMA_RX_3 119 -#define TX_CODEC_DMA_TX_3 120 -#define RX_CODEC_DMA_RX_4 121 -#define TX_CODEC_DMA_TX_4 122 -#define RX_CODEC_DMA_RX_5 123 -#define TX_CODEC_DMA_TX_5 124 -#define RX_CODEC_DMA_RX_6 125 -#define RX_CODEC_DMA_RX_7 126 -#define QUINARY_MI2S_RX 127 -#define QUINARY_MI2S_TX 128 -#define DISPLAY_PORT_RX_0 DISPLAY_PORT_RX -#define DISPLAY_PORT_RX_1 129 -#define DISPLAY_PORT_RX_2 130 -#define DISPLAY_PORT_RX_3 131 -#define DISPLAY_PORT_RX_4 132 -#define DISPLAY_PORT_RX_5 133 -#define DISPLAY_PORT_RX_6 134 -#define DISPLAY_PORT_RX_7 135 - -#define LPASS_CLK_ID_PRI_MI2S_IBIT 1 -#define LPASS_CLK_ID_PRI_MI2S_EBIT 2 -#define LPASS_CLK_ID_SEC_MI2S_IBIT 3 -#define LPASS_CLK_ID_SEC_MI2S_EBIT 4 -#define LPASS_CLK_ID_TER_MI2S_IBIT 5 -#define LPASS_CLK_ID_TER_MI2S_EBIT 6 -#define LPASS_CLK_ID_QUAD_MI2S_IBIT 7 -#define LPASS_CLK_ID_QUAD_MI2S_EBIT 8 -#define LPASS_CLK_ID_SPEAKER_I2S_IBIT 9 -#define LPASS_CLK_ID_SPEAKER_I2S_EBIT 10 -#define LPASS_CLK_ID_SPEAKER_I2S_OSR 11 -#define LPASS_CLK_ID_QUI_MI2S_IBIT 12 -#define LPASS_CLK_ID_QUI_MI2S_EBIT 13 -#define LPASS_CLK_ID_SEN_MI2S_IBIT 14 -#define LPASS_CLK_ID_SEN_MI2S_EBIT 15 -#define LPASS_CLK_ID_INT0_MI2S_IBIT 16 -#define LPASS_CLK_ID_INT1_MI2S_IBIT 17 -#define LPASS_CLK_ID_INT2_MI2S_IBIT 18 -#define LPASS_CLK_ID_INT3_MI2S_IBIT 19 -#define LPASS_CLK_ID_INT4_MI2S_IBIT 20 -#define LPASS_CLK_ID_INT5_MI2S_IBIT 21 -#define LPASS_CLK_ID_INT6_MI2S_IBIT 22 -#define LPASS_CLK_ID_QUI_MI2S_OSR 23 -#define LPASS_CLK_ID_PRI_PCM_IBIT 24 -#define LPASS_CLK_ID_PRI_PCM_EBIT 25 -#define LPASS_CLK_ID_SEC_PCM_IBIT 26 -#define LPASS_CLK_ID_SEC_PCM_EBIT 27 -#define LPASS_CLK_ID_TER_PCM_IBIT 28 -#define LPASS_CLK_ID_TER_PCM_EBIT 29 -#define LPASS_CLK_ID_QUAD_PCM_IBIT 30 -#define LPASS_CLK_ID_QUAD_PCM_EBIT 31 -#define LPASS_CLK_ID_QUIN_PCM_IBIT 32 -#define LPASS_CLK_ID_QUIN_PCM_EBIT 33 -#define LPASS_CLK_ID_QUI_PCM_OSR 34 -#define LPASS_CLK_ID_PRI_TDM_IBIT 35 -#define LPASS_CLK_ID_PRI_TDM_EBIT 36 -#define LPASS_CLK_ID_SEC_TDM_IBIT 37 -#define LPASS_CLK_ID_SEC_TDM_EBIT 38 -#define LPASS_CLK_ID_TER_TDM_IBIT 39 -#define LPASS_CLK_ID_TER_TDM_EBIT 40 -#define LPASS_CLK_ID_QUAD_TDM_IBIT 41 -#define LPASS_CLK_ID_QUAD_TDM_EBIT 42 -#define LPASS_CLK_ID_QUIN_TDM_IBIT 43 -#define LPASS_CLK_ID_QUIN_TDM_EBIT 44 -#define LPASS_CLK_ID_QUIN_TDM_OSR 45 -#define LPASS_CLK_ID_MCLK_1 46 -#define LPASS_CLK_ID_MCLK_2 47 -#define LPASS_CLK_ID_MCLK_3 48 -#define LPASS_CLK_ID_MCLK_4 49 -#define LPASS_CLK_ID_INTERNAL_DIGITAL_CODEC_CORE 50 -#define LPASS_CLK_ID_INT_MCLK_0 51 -#define LPASS_CLK_ID_INT_MCLK_1 52 -#define LPASS_CLK_ID_MCLK_5 53 -#define LPASS_CLK_ID_WSA_CORE_MCLK 54 -#define LPASS_CLK_ID_WSA_CORE_NPL_MCLK 55 -#define LPASS_CLK_ID_VA_CORE_MCLK 56 -#define LPASS_CLK_ID_TX_CORE_MCLK 57 -#define LPASS_CLK_ID_TX_CORE_NPL_MCLK 58 -#define LPASS_CLK_ID_RX_CORE_MCLK 59 -#define LPASS_CLK_ID_RX_CORE_NPL_MCLK 60 -#define LPASS_CLK_ID_VA_CORE_2X_MCLK 61 -/* Clock ID for MCLK for WSA2 core */ -#define LPASS_CLK_ID_WSA2_CORE_MCLK 62 -/* Clock ID for NPL MCLK for WSA2 core */ -#define LPASS_CLK_ID_WSA2_CORE_2X_MCLK 63 -/* Clock ID for RX Core TX MCLK */ -#define LPASS_CLK_ID_RX_CORE_TX_MCLK 64 -/* Clock ID for RX CORE TX 2X MCLK */ -#define LPASS_CLK_ID_RX_CORE_TX_2X_MCLK 65 -/* Clock ID for WSA core TX MCLK */ -#define LPASS_CLK_ID_WSA_CORE_TX_MCLK 66 -/* Clock ID for WSA core TX 2X MCLK */ -#define LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK 67 -/* Clock ID for WSA2 core TX MCLK */ -#define LPASS_CLK_ID_WSA2_CORE_TX_MCLK 68 -/* Clock ID for WSA2 core TX 2X MCLK */ -#define LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK 69 -/* Clock ID for RX CORE MCLK2 2X MCLK */ -#define LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK 70 - -#define LPASS_HW_AVTIMER_VOTE 101 -#define LPASS_HW_MACRO_VOTE 102 -#define LPASS_HW_DCODEC_VOTE 103 - -#define Q6AFE_MAX_CLK_ID 104 - -#define LPASS_CLK_ATTRIBUTE_INVALID 0x0 -#define LPASS_CLK_ATTRIBUTE_COUPLE_NO 0x1 -#define LPASS_CLK_ATTRIBUTE_COUPLE_DIVIDEND 0x2 -#define LPASS_CLK_ATTRIBUTE_COUPLE_DIVISOR 0x3 - -#endif /* __DT_BINDINGS_Q6_AUDIO_PORTS_H__ */ diff --git a/include/dt-bindings/sound/qcom,wcd9335.h b/include/dt-bindings/sound/qcom,wcd9335.h deleted file mode 100644 index f5e9f1db091..00000000000 --- a/include/dt-bindings/sound/qcom,wcd9335.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ - -#ifndef __DT_SOUND_QCOM_WCD9335_H -#define __DT_SOUND_QCOM_WCD9335_H - -#define AIF1_PB 0 -#define AIF1_CAP 1 -#define AIF2_PB 2 -#define AIF2_CAP 3 -#define AIF3_PB 4 -#define AIF3_CAP 5 -#define AIF4_PB 6 -#define NUM_CODEC_DAIS 7 - -#endif diff --git a/include/efi.h b/include/efi.h index c559fda3004..d50b3d3cec9 100644 --- a/include/efi.h +++ b/include/efi.h @@ -175,7 +175,7 @@ enum efi_allocate_type { EFI_ALLOCATE_MAX_ADDRESS, /** * @EFI_ALLOCATE_ADDRESS: - * Allocate a memory block starting at the indicatged adress. + * Allocate a memory block starting at the indicated address. */ EFI_ALLOCATE_ADDRESS, /** diff --git a/include/efi_api.h b/include/efi_api.h index f07d074f93b..61c4eda8f8a 100644 --- a/include/efi_api.h +++ b/include/efi_api.h @@ -616,6 +616,7 @@ struct efi_device_path_acpi_path { # define DEVICE_PATH_SUB_TYPE_MSG_SCSI 0x02 # define DEVICE_PATH_SUB_TYPE_MSG_USB 0x05 # define DEVICE_PATH_SUB_TYPE_MSG_MAC_ADDR 0x0b +# define DEVICE_PATH_SUB_TYPE_MSG_IPV4 0x0c # define DEVICE_PATH_SUB_TYPE_MSG_UART 0x0e # define DEVICE_PATH_SUB_TYPE_MSG_USB_CLASS 0x0f # define DEVICE_PATH_SUB_TYPE_MSG_USB_WWI 0x10 @@ -691,6 +692,22 @@ struct efi_device_path_uri { u8 uri[]; } __packed; +struct efi_ipv4_address { + u8 ip_addr[4]; +}; + +struct efi_device_path_ipv4 { + struct efi_device_path dp; + struct efi_ipv4_address local_ip_address; + struct efi_ipv4_address remote_ip_address; + u16 local_port; + u16 remote_port; + u16 protocol; + u8 static_ip_address; + struct efi_ipv4_address gateway_ip_address; + struct efi_ipv4_address subnet_mask; +} __packed; + #define DEVICE_PATH_TYPE_MEDIA_DEVICE 0x04 # define DEVICE_PATH_SUB_TYPE_HARD_DRIVE_PATH 0x01 # define DEVICE_PATH_SUB_TYPE_CDROM_PATH 0x02 @@ -1708,6 +1725,209 @@ struct efi_pxe_base_code_protocol { struct efi_pxe_mode *mode; }; +#define EFI_IP4_CONFIG2_PROTOCOL_GUID \ + EFI_GUID(0x5b446ed1, 0xe30b, 0x4faa, \ + 0x87, 0x1a, 0x36, 0x54, 0xec, 0xa3, 0x60, 0x80) + +enum efi_ip4_config2_data_type { + EFI_IP4_CONFIG2_DATA_TYPE_INTERFACEINFO, + EFI_IP4_CONFIG2_DATA_TYPE_POLICY, + EFI_IP4_CONFIG2_DATA_TYPE_MANUAL_ADDRESS, + EFI_IP4_CONFIG2_DATA_TYPE_GATEWAY, + EFI_IP4_CONFIG2_DATA_TYPE_DNSSERVER, + EFI_IP4_CONFIG2_DATA_TYPE_MAXIMUM, +}; + +struct efi_ip4_config2_protocol { + efi_status_t (EFIAPI * set_data)(struct efi_ip4_config2_protocol *this, + enum efi_ip4_config2_data_type data_type, + efi_uintn_t data_size, + void *data); + efi_status_t (EFIAPI * get_data)(struct efi_ip4_config2_protocol *this, + enum efi_ip4_config2_data_type data_type, + efi_uintn_t *data_size, + void *data); + efi_status_t (EFIAPI * register_data_notify)(struct efi_ip4_config2_protocol *this, + enum efi_ip4_config2_data_type data_type, + struct efi_event *event); + efi_status_t (EFIAPI * unregister_data_notify)(struct efi_ip4_config2_protocol *this, + enum efi_ip4_config2_data_type data_type, + struct efi_event *event); +}; + +struct efi_ip4_route_table { + struct efi_ipv4_address subnet_address; + struct efi_ipv4_address subnet_mask; + struct efi_ipv4_address gateway_address; +}; + +#define EFI_IP4_CONFIG2_INTERFACE_INFO_NAME_SIZE 32 + +struct efi_ip4_config2_interface_info { + u16 name[EFI_IP4_CONFIG2_INTERFACE_INFO_NAME_SIZE]; + u8 if_type; + u32 hw_address_size; + struct efi_mac_address hw_address; + struct efi_ipv4_address station_address; + struct efi_ipv4_address subnet_mask; + u32 route_table_size; + struct efi_ip4_route_table *route_table; +}; + +enum efi_ip4_config2_policy { + EFI_IP4_CONFIG2_POLICY_STATIC, + EFI_IP4_CONFIG2_POLICY_DHCP, + EFI_IP4_CONFIG2_POLICY_MAX +}; + +struct efi_ip4_config2_manual_address { + struct efi_ipv4_address address; + struct efi_ipv4_address subnet_mask; +}; + +#define EFI_HTTP_SERVICE_BINDING_PROTOCOL_GUID \ + EFI_GUID(0xbdc8e6af, 0xd9bc, 0x4379, \ + 0xa7, 0x2a, 0xe0, 0xc4, 0xe7, 0x5d, 0xae, 0x1c) + +struct efi_service_binding_protocol { + efi_status_t (EFIAPI * create_child)(struct efi_service_binding_protocol *this, + efi_handle_t *child_handle); + efi_status_t (EFIAPI * destroy_child)(struct efi_service_binding_protocol *this, + efi_handle_t child_handle); +}; + +#define EFI_HTTP_PROTOCOL_GUID \ + EFI_GUID(0x7A59B29B, 0x910B, 0x4171, \ + 0x82, 0x42, 0xA8, 0x5A, 0x0D, 0xF2, 0x5B, 0x5B) + +enum efi_http_version { + HTTPVERSION10, + HTTPVERSION11, + HTTPVERSIONUNSUPPORTED +}; + +struct efi_httpv4_access_point { + bool use_default_address; + struct efi_ipv4_address local_address; + struct efi_ipv4_address local_subnet; + u16 local_port; +}; + +union efi_http_access_point { + struct efi_httpv4_access_point *ipv4_node; + struct efi_httpv6_access_point *ipv6_node; +}; + +struct efi_http_config_data { + enum efi_http_version http_version; + u32 timeout; + bool is_ipv6; + union efi_http_access_point access_point; +}; + +enum efi_http_method { + HTTP_METHOD_GET, + HTTP_METHOD_POST, + HTTP_METHOD_PATCH, + HTTP_METHOD_OPTIONS, + HTTP_METHOD_CONNECT, + HTTP_METHOD_HEAD, + HTTP_METHOD_PUT, + HTTP_METHOD_DELETE, + HTTP_METHOD_TRACE, + HTTP_METHOD_MAX +}; + +enum efi_http_status_code { + HTTP_STATUS_UNSUPPORTED_STATUS = 0, + HTTP_STATUS_100_CONTINUE, + HTTP_STATUS_101_SWITCHING_PROTOCOLS, + HTTP_STATUS_200_OK, + HTTP_STATUS_201_CREATED, + HTTP_STATUS_202_ACCEPTED, + HTTP_STATUS_203_NON_AUTHORITATIVE_INFORMATION, + HTTP_STATUS_204_NO_CONTENT, + HTTP_STATUS_205_RESET_CONTENT, + HTTP_STATUS_206_PARTIAL_CONTENT, + HTTP_STATUS_300_MULTIPLE_CHOICES, + HTTP_STATUS_301_MOVED_PERMANENTLY, + HTTP_STATUS_302_FOUND, + HTTP_STATUS_303_SEE_OTHER, + HTTP_STATUS_304_NOT_MODIFIED, + HTTP_STATUS_305_USE_PROXY, + HTTP_STATUS_307_TEMPORARY_REDIRECT, + HTTP_STATUS_400_BAD_REQUEST, + HTTP_STATUS_401_UNAUTHORIZED, + HTTP_STATUS_402_PAYMENT_REQUIRED, + HTTP_STATUS_403_FORBIDDEN, + HTTP_STATUS_404_NOT_FOUND, + HTTP_STATUS_405_METHOD_NOT_ALLOWED, + HTTP_STATUS_406_NOT_ACCEPTABLE, + HTTP_STATUS_407_PROXY_AUTHENTICATION_REQUIRED, + HTTP_STATUS_408_REQUEST_TIME_OUT, + HTTP_STATUS_409_CONFLICT, + HTTP_STATUS_410_GONE, + HTTP_STATUS_411_LENGTH_REQUIRED, + HTTP_STATUS_412_PRECONDITION_FAILED, + HTTP_STATUS_413_REQUEST_ENTITY_TOO_LARGE, + HTTP_STATUS_414_REQUEST_URI_TOO_LARGE, + HTTP_STATUS_415_UNSUPPORTED_MEDIA_TYPE, + HTTP_STATUS_416_REQUESTED_RANGE_NOT_SATISFIED, + HTTP_STATUS_417_EXPECTATION_FAILED, + HTTP_STATUS_500_INTERNAL_SERVER_ERROR, + HTTP_STATUS_501_NOT_IMPLEMENTED, + HTTP_STATUS_502_BAD_GATEWAY, + HTTP_STATUS_503_SERVICE_UNAVAILABLE, + HTTP_STATUS_504_GATEWAY_TIME_OUT, + HTTP_STATUS_505_HTTP_VERSION_NOT_SUPPORTED, + HTTP_STATUS_308_PERMANENT_REDIRECT +}; + +struct efi_http_request_data { + enum efi_http_method method; + u16 *url; +}; + +struct efi_http_response_data { + enum efi_http_status_code status_code; +}; + +struct efi_http_header { + char *field_name; + char *field_value; +}; + +struct efi_http_message { + union { + struct efi_http_request_data *request; + struct efi_http_response_data *response; + } data; + efi_uintn_t header_count; + struct efi_http_header *headers; + efi_uintn_t body_length; + void *body; +}; + +struct efi_http_token { + struct efi_event *event; + efi_status_t status; + struct efi_http_message *message; +}; + +struct efi_http_protocol { + efi_status_t (EFIAPI * get_mode_data)(struct efi_http_protocol *this, + struct efi_http_config_data *data); + efi_status_t (EFIAPI * configure)(struct efi_http_protocol *this, + struct efi_http_config_data *data); + efi_status_t (EFIAPI * request)(struct efi_http_protocol *this, + struct efi_http_token *token); + efi_status_t (EFIAPI * cancel)(struct efi_http_protocol *this, + struct efi_http_token *token); + efi_status_t (EFIAPI * response)(struct efi_http_protocol *this, + struct efi_http_token *token); + efi_status_t (EFIAPI * poll)(struct efi_http_protocol *this); +}; + #define EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_GUID \ EFI_GUID(0x964e5b22, 0x6459, 0x11d2, \ 0x8e, 0x39, 0x0, 0xa0, 0xc9, 0x69, 0x72, 0x3b) diff --git a/include/efi_loader.h b/include/efi_loader.h index 39809eac1bc..9afbec35ebf 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -16,6 +16,7 @@ #include <image.h> #include <pe.h> #include <linux/list.h> +#include <linux/sizes.h> #include <linux/oid_registry.h> struct blk_desc; @@ -125,6 +126,39 @@ static inline void efi_set_bootdev(const char *dev, const char *devnr, size_t buffer_size) { } #endif +#if CONFIG_IS_ENABLED(NETDEVICES) && CONFIG_IS_ENABLED(EFI_LOADER) +/* Call this to update the current device path of the efi net device */ +efi_status_t efi_net_set_dp(const char *dev, const char *server); +/* Call this to get the current device path of the efi net device */ +void efi_net_get_dp(struct efi_device_path **dp); +void efi_net_get_addr(struct efi_ipv4_address *ip, + struct efi_ipv4_address *mask, + struct efi_ipv4_address *gw); +void efi_net_set_addr(struct efi_ipv4_address *ip, + struct efi_ipv4_address *mask, + struct efi_ipv4_address *gw); +efi_status_t efi_net_do_request(u8 *url, enum efi_http_method method, void **buffer, + u32 *status_code, ulong *file_size, char *headers_buffer); +#define MAX_HTTP_HEADERS_SIZE SZ_64K +#define MAX_HTTP_HEADERS 100 +#define MAX_HTTP_HEADER_NAME 128 +#define MAX_HTTP_HEADER_VALUE 512 +struct http_header { + uchar name[MAX_HTTP_HEADER_NAME]; + uchar value[MAX_HTTP_HEADER_VALUE]; +}; + +void efi_net_parse_headers(ulong *num_headers, struct http_header *headers); +#else +static inline void efi_net_get_dp(struct efi_device_path **dp) { } +static inline void efi_net_get_addr(struct efi_ipv4_address *ip, + struct efi_ipv4_address *mask, + struct efi_ipv4_address *gw) { } +static inline void efi_net_set_addr(struct efi_ipv4_address *ip, + struct efi_ipv4_address *mask, + struct efi_ipv4_address *gw) { } +#endif + /* Maximum number of configuration tables */ #define EFI_MAX_CONFIGURATION_TABLES 16 @@ -592,6 +626,12 @@ int efi_disk_create_partitions(efi_handle_t parent, struct blk_desc *desc, efi_status_t efi_gop_register(void); /* Called by bootefi to make the network interface available */ efi_status_t efi_net_register(void); +/* Called by efi_net_register to make the ip4 config2 protocol available */ +efi_status_t efi_ipconfig_register(const efi_handle_t handle, + struct efi_ip4_config2_protocol *ip4config); +/* Called by efi_net_register to make the http protocol available */ +efi_status_t efi_http_register(const efi_handle_t handle, + struct efi_service_binding_protocol *http_service_binding); /* Called by bootefi to make the watchdog available */ efi_status_t efi_watchdog_register(void); efi_status_t efi_initrd_register(void); @@ -856,6 +896,7 @@ struct efi_device_path *efi_dp_part_node(struct blk_desc *desc, int part); struct efi_device_path *efi_dp_from_file(const struct efi_device_path *dp, const char *path); struct efi_device_path *efi_dp_from_eth(void); +struct efi_device_path *efi_dp_from_http(const char *server); struct efi_device_path *efi_dp_from_mem(uint32_t mem_type, uint64_t start_address, size_t size); diff --git a/include/env_callback.h b/include/env_callback.h index bc8ff1923e1..47a31f6cf52 100644 --- a/include/env_callback.h +++ b/include/env_callback.h @@ -14,11 +14,6 @@ #define ENV_CALLBACK_VAR ".callbacks" -/* Board configs can define additional static callback bindings */ -#ifndef CFG_ENV_CALLBACK_LIST_STATIC -#define CFG_ENV_CALLBACK_LIST_STATIC -#endif - #ifdef CONFIG_SILENT_CONSOLE #define SILENT_CALLBACK "silent:silent," #else @@ -90,7 +85,7 @@ SILENT_CALLBACK \ "stdin:console,stdout:console,stderr:console," \ "serial#:serialno," \ - CFG_ENV_CALLBACK_LIST_STATIC + CONFIG_ENV_CALLBACK_LIST_STATIC #ifndef CONFIG_XPL_BUILD void env_callback_init(struct env_entry *var_entry); diff --git a/include/fdtdec.h b/include/fdtdec.h index 555c9520379..d9fcd037ed2 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -136,23 +136,6 @@ struct fdt_pci_addr { u32 phys_lo; }; -extern u8 __dtb_dt_begin[]; /* embedded device tree blob */ -extern u8 __dtb_dt_spl_begin[]; /* embedded device tree blob for SPL/TPL */ - -/* Get a pointer to the embedded devicetree, if there is one, else NULL */ -static inline u8 *dtb_dt_embedded(void) -{ -#ifdef CONFIG_OF_EMBED -# ifdef CONFIG_XPL_BUILD - return __dtb_dt_spl_begin; -# else - return __dtb_dt_begin; -# endif -#else - return NULL; -#endif -} - /** * Compute the size of a resource. * @@ -1156,6 +1139,13 @@ int fdtdec_set_carveout(void *blob, const char *node, const char *prop_name, unsigned int count, unsigned long flags); /** + * fdtdec_setup_embed - pick up embedded DTS + * + * Should be invoked under CONFIG_OF_EMBED guard. + */ +void fdtdec_setup_embed(void); + +/** * Set up the device tree ready for use */ int fdtdec_setup(void); @@ -1191,11 +1181,12 @@ int fdtdec_resetup(int *rescan); * * The existing devicetree is available at gd->fdt_blob * - * @err: 0 on success, -EEXIST if the devicetree is already correct, or other - * internal error code if we fail to setup a DTB - * @returns new devicetree blob pointer + * @fdtp: Existing devicetree blob pointer; update this and return 0 if a + * different devicetree should be used + * Return: 0 on success, -EEXIST if the existing FDT is OK, -ve error code if we + * fail to setup a DTB */ -void *board_fdt_blob_setup(int *err); +int board_fdt_blob_setup(void **fdtp); /* * Decode the size of memory diff --git a/include/firmware/imx/sci/rpc.h b/include/firmware/imx/sci/rpc.h index 28adec2a8e1..04acc7ff95b 100644 --- a/include/firmware/imx/sci/rpc.h +++ b/include/firmware/imx/sci/rpc.h @@ -231,4 +231,7 @@ struct sc_rpc_msg_s { #define TIMER_FUNC_SET_SYSCTR_PERIODIC_ALARM 17U /* Index for sc_timer_set_sysctr_periodic_alarm() RPC call */ #define TIMER_FUNC_CANCEL_SYSCTR_ALARM 18U /* Index for sc_timer_cancel_sysctr_alarm() RPC call */ +/* Siemens specific API extension */ +#define TIMER_FUNC_CTRL_SIEMENS_PMIC_WDOG 20U /*!< Index for sc_timer_ctrl_pmic_wdog() RPC call */ + #endif /* SC_RPC_H */ diff --git a/include/firmware/imx/sci/sci.h b/include/firmware/imx/sci/sci.h index 7d8499f070a..588f3671103 100644 --- a/include/firmware/imx/sci/sci.h +++ b/include/firmware/imx/sci/sci.h @@ -123,6 +123,7 @@ int sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource, sc_rm_sid_t sid); /* Timer API */ int sc_timer_set_wdog_window(sc_ipc_t ipc, sc_timer_wdog_time_t window); +int sc_timer_control_siemens_pmic_wdog(sc_ipc_t ipc, u8 cmd); /* SECO API */ int sc_seco_authenticate(sc_ipc_t ipc, sc_seco_auth_cmd_t cmd, diff --git a/include/fs.h b/include/fs.h index 63727567ccc..2474880385d 100644 --- a/include/fs.h +++ b/include/fs.h @@ -325,7 +325,7 @@ int do_fs_types(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]); * * @fname: Filename to read * @size: Size of file to read (must be correct!) - * @align: Alignment to use for memory allocation (0 for default) + * @align: Alignment to use for memory allocation (0 for default: ARCH_DMA_MINALIGN) * @bufp: On success, returns the allocated buffer with the nul-terminated file * in it * Return: 0 if OK, -ENOMEM if out of memory, -EIO if read failed diff --git a/include/handoff.h b/include/handoff.h index 0072ea832f8..c0ae7b19a75 100644 --- a/include/handoff.h +++ b/include/handoff.h @@ -32,13 +32,6 @@ void handoff_load_dram_size(struct spl_handoff *ho); void handoff_load_dram_banks(struct spl_handoff *ho); /** - * handoff_get() - Get the SPL handoff information - * - * Return: Pointer to SPL handoff if received, else NULL - */ -struct spl_handoff *handoff_get(void); - -/** * handoff_arch_save() - Save arch-specific info into the handoff area * * This is defined to an empty function by default, but arch-specific code can diff --git a/include/image.h b/include/image.h index c52fced9b40..0a61dfd556c 100644 --- a/include/image.h +++ b/include/image.h @@ -1172,6 +1172,18 @@ int fit_image_get_data_and_size(const void *fit, int noffset, const void **data, size_t *size); /** + * fit_image_get_phase() - Get the phase from a FIT image + * + * @fit: FIT to read from + * @offset: offset node to read + * @phasep: Returns phase, if any + * Return: 0 if read OK and *phasep is value, -ENOENT if there was no phase + * property in the node, other -ve value on other error + */ +int fit_image_get_phase(const void *fit, int offset, + enum image_phase_t *phasep); + +/** * fit_get_data_node() - Get verified image data for an image * @fit: Pointer to the FIT format image header * @image_uname: The name of the image node @@ -1399,7 +1411,9 @@ int fit_check_format(const void *fit, ulong size); * copied into the configuration node in the FIT image. This is required to * match configurations with compressed FDTs. * - * Returns: offset to the configuration to use if one was found, -1 otherwise + * Returns: offset to the configuration to use if one was found, -EINVAL if + * there a /configurations or /images node is missing, -ENOENT if no match was + * found, -ENXIO if the FDT node has no compatible string */ int fit_conf_find_compat(const void *fit, const void *fdt); @@ -1788,6 +1802,21 @@ struct cipher_algo { const unsigned char *data, int data_len, unsigned char **cipher, int *cipher_len); + /** + * add_cipher_data() - Add cipher data to the FIT and device tree + * + * This is used to add the ciphered data to the FIT and other cipher + * related information (key and initialization vector) to a device tree. + * + * @info: Pointer to image cipher information. + * @keydest: Pointer to a device tree where the key and IV can be + * stored. keydest can be NULL when the key is retrieved at + * runtime by another mean. + * @fit: Pointer to the FIT image. + * @node_noffset: Offset where the cipher information are stored in the + * FIT. + * return: 0 on success, a negative error code otherwise. + */ int (*add_cipher_data)(struct image_cipher_info *info, void *keydest, void *fit, int node_noffset); @@ -1802,6 +1831,30 @@ struct cipher_algo *image_get_cipher_algo(const char *full_name); struct andr_image_data; /** + * android_image_get_bootimg_size() - Extract size of Android boot image + * + * This is used to extract the size of an Android boot image + * from boot image header. + * + * @hdr: Pointer to boot image header + * @boot_img_size: On exit returns the size in bytes of the boot image + * Return: true if succeeded, false otherwise + */ +bool android_image_get_bootimg_size(const void *hdr, u32 *boot_img_size); + +/** + * android_image_get_vendor_bootimg_size() - Extract size of Android vendor-boot image + * + * This is used to extract the size of an Android vendor-boot image + * from vendor-boot image header. + * + * @hdr: Pointer to vendor-boot image header + * @vendor_boot_img_size: On exit returns the size in bytes of the vendor-boot image + * Return: true if succeeded, false otherwise + */ +bool android_image_get_vendor_bootimg_size(const void *hdr, u32 *vendor_boot_img_size); + +/** * android_image_get_data() - Parse Android boot images * * This is used to parse boot and vendor-boot header into diff --git a/include/k3-avs.h b/include/k3-avs.h index 1014d5d114d..5a973e4ed45 100644 --- a/include/k3-avs.h +++ b/include/k3-avs.h @@ -20,11 +20,13 @@ #define NUM_OPPS 4 +#define AM6_OPP_LOW 0 #define AM6_OPP_NOM 1 #define AM6_OPP_OD 2 #define AM6_OPP_TURBO 3 int k3_avs_set_opp(struct udevice *dev, int vdd_id, int opp_id); int k3_avs_notify_freq(int dev_id, int clk_id, u32 freq); +int k3_avs_check_opp(struct udevice *dev, int vdd_id, int opp_id); #endif diff --git a/include/limits.h b/include/limits.h index 4700cc7a59f..1d0bbf69be7 100644 --- a/include/limits.h +++ b/include/limits.h @@ -9,7 +9,8 @@ #define UINT32_MAX 0xffffffffU #define UINT64_MAX 0xffffffffffffffffULL -#ifdef CONFIG_64BIT +#if (defined(CONFIG_64BIT) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_64BIT) && defined(CONFIG_SPL_BUILD)) #define UINTPTR_MAX UINT64_MAX #else #define UINTPTR_MAX UINT32_MAX diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h index 6751fb52c5a..3ffcd40807d 100644 --- a/include/linux/mtd/mtd.h +++ b/include/linux/mtd/mtd.h @@ -339,7 +339,7 @@ static inline void mtd_set_ofnode(struct mtd_info *mtd, ofnode node) dev_set_ofnode(mtd->dev, node); } -static inline const ofnode mtd_get_ofnode(struct mtd_info *mtd) +static inline ofnode mtd_get_ofnode(struct mtd_info *mtd) { return dev_ofnode(mtd->dev); } diff --git a/include/lmb.h b/include/lmb.h index f221f0cce8f..d9d7435a431 100644 --- a/include/lmb.h +++ b/include/lmb.h @@ -1,6 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Logical memory blocks. + * + * Copyright (C) 2001 Peter Bergner, IBM Corp. + */ + #ifndef _LINUX_LMB_H #define _LINUX_LMB_H + #ifdef __KERNEL__ #include <alist.h> @@ -8,101 +15,106 @@ #include <asm/u-boot.h> #include <linux/bitops.h> -/* - * Logical memory blocks. - * - * Copyright (C) 2001 Peter Bergner, IBM Corp. - */ - -#define LMB_ALLOC_ANYWHERE 0 -#define LMB_ALIST_INITIAL_SIZE 4 +#define LMB_ALLOC_ANYWHERE 0 +#define LMB_ALIST_INITIAL_SIZE 4 /** - * enum lmb_flags - definition of memory region attributes - * @LMB_NONE: no special request - * @LMB_NOMAP: don't add to mmu configuration - * @LMB_NOOVERWRITE: the memory region cannot be overwritten/re-reserved - * @LMB_NONOTIFY: do not notify other modules of changes to this memory region - */ -enum lmb_flags { - LMB_NONE = 0, - LMB_NOMAP = BIT(1), - LMB_NOOVERWRITE = BIT(2), - LMB_NONOTIFY = BIT(3), -}; + * DOC: Memory region attribute flags. + * + * %LMB_NONE: No special request + * %LMB_NOMAP: Don't add to MMU configuration + * %LMB_NOOVERWRITE: The memory region cannot be overwritten/re-reserved + * %LMB_NONOTIFY: Do not notify other modules of changes to this memory region + */ +#define LMB_NONE 0 +#define LMB_NOMAP BIT(0) +#define LMB_NOOVERWRITE BIT(1) +#define LMB_NONOTIFY BIT(2) /** - * struct lmb_region - Description of one region. - * - * @base: Base address of the region. - * @size: Size of the region - * @flags: memory region attributes + * struct lmb_region - Description of one region + * @base: Base address of the region + * @size: Size of the region + * @flags: Memory region attributes */ struct lmb_region { phys_addr_t base; phys_size_t size; - enum lmb_flags flags; + u32 flags; }; /** * struct lmb - The LMB structure - * - * @free_mem: List of free memory regions - * @used_mem: List of used/reserved memory regions - * @test: Is structure being used for LMB tests + * @available_mem: List of memory available to LMB + * @used_mem: List of used/reserved memory regions + * @test: Is structure being used for LMB tests */ struct lmb { - struct alist free_mem; + struct alist available_mem; struct alist used_mem; bool test; }; /** - * lmb_init() - Initialise the LMB module + * lmb_init() - Initialise the LMB module. + * + * Return: 0 on success, negative error code on failure. * * Initialise the LMB lists needed for keeping the memory map. There - * are two lists, in form of alloced list data structure. One for the + * are two lists, in form of allocated list data structure. One for the * available memory, and one for the used memory. Initialise the two * lists as part of board init. Add memory to the available memory * list and reserve common areas by adding them to the used memory * list. - * - * Return: 0 on success, -ve on error */ int lmb_init(void); /** - * lmb_add_memory() - Add memory range for LMB allocations + * lmb_add_memory() - Add memory range for LMB allocations. * * Add the entire available memory range to the pool of memory that * can be used by the LMB module for allocations. - * - * Return: None */ void lmb_add_memory(void); long lmb_add(phys_addr_t base, phys_size_t size); -long lmb_reserve(phys_addr_t base, phys_size_t size); + /** - * lmb_reserve_flags - Reserve one region with a specific flags bitfield. - * - * @base: base address of the memory region - * @size: size of the memory region - * @flags: flags for the memory region - * Return: 0 if OK, > 0 for coalesced region or a negative error code. + * lmb_reserve() - Reserve one region with a specific flags bitfield + * @base: Base address of the memory region + * @size: Size of the memory region + * @flags: Flags for the memory region + * + * Return: + * * %0 - Added successfully, or it's already added (only if LMB_NONE) + * * %-EEXIST - The region is already added, and flags != LMB_NONE + * * %-1 - Failure */ -long lmb_reserve_flags(phys_addr_t base, phys_size_t size, - enum lmb_flags flags); +long lmb_reserve(phys_addr_t base, phys_size_t size, u32 flags); + phys_addr_t lmb_alloc(phys_size_t size, ulong align); -phys_addr_t lmb_alloc_base(phys_size_t size, ulong align, phys_addr_t max_addr); -phys_addr_t lmb_alloc_addr(phys_addr_t base, phys_size_t size); phys_size_t lmb_get_free_size(phys_addr_t addr); -phys_addr_t lmb_alloc_base_flags(phys_size_t size, ulong align, - phys_addr_t max_addr, uint flags); +/** + * lmb_alloc_base() - Allocate specified memory region with specified + * attributes + * @size: Size of the region requested + * @align: Alignment of the memory region requested + * @max_addr: Maximum address of the requested region + * @flags: Memory region attributes to be set + * + * Allocate a region of memory with the attributes specified through the + * parameter. The max_addr parameter is used to specify the maximum address + * below which the requested region should be allocated. + * + * Return: Base address on success, 0 on error. + */ +phys_addr_t lmb_alloc_base(phys_size_t size, ulong align, phys_addr_t max_addr, + uint flags); /** - * lmb_alloc_addr_flags() - Allocate specified memory address with specified attributes + * lmb_alloc_addr() - Allocate specified memory address with specified attributes + * * @base: Base Address requested * @size: Size of the region requested * @flags: Memory region attributes to be set @@ -111,20 +123,20 @@ phys_addr_t lmb_alloc_base_flags(phys_size_t size, ulong align, * parameter. The base parameter is used to specify the base address * of the requested region. * - * Return: base address on success, 0 on error + * Return: Base address on success, 0 on error. */ -phys_addr_t lmb_alloc_addr_flags(phys_addr_t base, phys_size_t size, - uint flags); +phys_addr_t lmb_alloc_addr(phys_addr_t base, phys_size_t size, u32 flags); /** - * lmb_is_reserved_flags() - test if address is in reserved region with flag bits set + * lmb_is_reserved_flags() - Test if address is in reserved region with flag + * bits set + * @addr: Address to be tested + * @flags: Bitmap with bits to be tested * * The function checks if a reserved region comprising @addr exists which has * all flag bits set which are set in @flags. * - * @addr: address to be tested - * @flags: bitmap with bits to be tested - * Return: 1 if matching reservation exists, 0 otherwise + * Return: 1 if matching reservation exists, 0 otherwise. */ int lmb_is_reserved_flags(phys_addr_t addr, int flags); @@ -134,9 +146,7 @@ int lmb_is_reserved_flags(phys_addr_t addr, int flags); * @size: Size of the region to be freed * @flags: Memory region attributes * - * Free up a region of memory. - * - * Return: 0 if successful, -1 on failure + * Return: 0 on success, negative error code on failure. */ long lmb_free_flags(phys_addr_t base, phys_size_t size, uint flags); @@ -153,14 +163,14 @@ void lmb_pop(struct lmb *store); static inline int lmb_read_check(phys_addr_t addr, phys_size_t len) { - return lmb_alloc_addr(addr, len) == addr ? 0 : -1; + return lmb_alloc_addr(addr, len, LMB_NONE) == addr ? 0 : -1; } /** * io_lmb_setup() - Initialize LMB struct * @io_lmb: IO LMB to initialize * - * Returns: 0 on success, negative error code on failure + * Return: 0 on success, negative error code on failure. */ int io_lmb_setup(struct lmb *io_lmb); @@ -178,12 +188,13 @@ void io_lmb_teardown(struct lmb *io_lmb); * * Add the IOVA space [base, base + size] to be managed by io_lmb. * - * Returns: 0 if the region addition was successful, -1 on failure + * Return: 0 on success, negative error code on failure. */ long io_lmb_add(struct lmb *io_lmb, phys_addr_t base, phys_size_t size); /** - * io_lmb_alloc() - Allocate specified IO memory address with specified alignment + * io_lmb_alloc() - Allocate specified IO memory address with specified + * alignment * @io_lmb: LMB to alloc from * @size: Size of the region requested * @align: Required address and size alignment @@ -191,7 +202,7 @@ long io_lmb_add(struct lmb *io_lmb, phys_addr_t base, phys_size_t size); * Allocate a region of IO memory. The base parameter is used to specify the * base address of the requested region. * - * Return: base IO address on success, 0 on error + * Return: Base IO address on success, 0 on error. */ phys_addr_t io_lmb_alloc(struct lmb *io_lmb, phys_size_t size, ulong align); @@ -201,9 +212,7 @@ phys_addr_t io_lmb_alloc(struct lmb *io_lmb, phys_size_t size, ulong align); * @base: Base Address of region to be freed * @size: Size of the region to be freed * - * Free up a region of IOVA space. - * - * Return: 0 if successful, -1 on failure + * Return: 0 on success, negative error code on failure. */ long io_lmb_free(struct lmb *io_lmb, phys_addr_t base, phys_size_t size); diff --git a/include/memtop.h b/include/memtop.h new file mode 100644 index 00000000000..28f62e24ea7 --- /dev/null +++ b/include/memtop.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2024, Linaro Limited + */ + +/** + * get_mem_top() - Compute the value of ram_top + * @ram_start: Start of RAM + * @ram_size: RAM size + * @size: Minimum RAM size requested + * @fdt: FDT blob + * + * The function computes the top address of RAM memory that can be + * used by U-Boot. This is being done by going through the list of + * reserved memory regions specified in the devicetree blob passed + * to the function. The logic used here is derived from the lmb + * allocation function. + * + * Return: address of ram top on success, 0 on failure + */ +phys_addr_t get_mem_top(phys_addr_t ram_start, phys_size_t ram_size, + phys_size_t size, void *fdt); diff --git a/include/net-common.h b/include/net-common.h index 524ed4ad131..8fc1bac47f5 100644 --- a/include/net-common.h +++ b/include/net-common.h @@ -8,6 +8,7 @@ #include <env.h> #include <hexdump.h> #include <linux/if_ether.h> +#include <linux/sizes.h> #include <linux/types.h> #include <rand.h> #include <time.h> @@ -425,6 +426,16 @@ void string_to_enetaddr(const char *addr, uint8_t *enetaddr); */ struct in_addr string_to_ip(const char *s); +/** + * ip_to_string() - Convert a string to ip address + * + * Implemented in lib/net_utils.c (built unconditionally) + * + * @x: Input ip to parse + * @s: string containing the parsed ip address + */ +void ip_to_string(struct in_addr x, char *s); + /* copy a filename (allow for "..." notation, limit length) */ void copy_filename(char *dst, const char *src, int size); @@ -490,13 +501,16 @@ int dhcp_run(ulong addr, const char *fname, bool autoload); int do_tftpb(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); /** - * wget_with_dns() - runs dns host IP address resulution before wget + * wget_do_request() - sends a wget request + * + * Sends a wget request, if DNS resolution is enabled it resolves the + * given uri. * * @dst_addr: destination address to download the file * @uri: uri string of target file of wget - * Return: downloaded file size, negative if failed + * Return: zero on success, negative if failed */ -int wget_with_dns(ulong dst_addr, char *uri); +int wget_do_request(ulong dst_addr, char *uri); /** * wget_validate_uri() - varidate the uri * @@ -506,4 +520,55 @@ int wget_with_dns(ulong dst_addr, char *uri); bool wget_validate_uri(char *uri); //int do_wget(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]); +/** + * enum wget_http_method - http method + */ +enum wget_http_method { + WGET_HTTP_METHOD_GET, + WGET_HTTP_METHOD_POST, + WGET_HTTP_METHOD_PATCH, + WGET_HTTP_METHOD_OPTIONS, + WGET_HTTP_METHOD_CONNECT, + WGET_HTTP_METHOD_HEAD, + WGET_HTTP_METHOD_PUT, + WGET_HTTP_METHOD_DELETE, + WGET_HTTP_METHOD_TRACE, + WGET_HTTP_METHOD_MAX +}; + +/** + * define MAX_HTTP_HEADERS_SIZE - maximum headers buffer size + * + * When receiving http headers, wget fills a buffer with up + * to MAX_HTTP_HEADERS_SIZE bytes of header information. + */ +#define MAX_HTTP_HEADERS_SIZE SZ_64K + +/** + * struct wget_http_info - wget parameters + * @method: HTTP Method. Filled by client. + * @status_code: HTTP status code. Filled by wget. + * @file_size: download size. Filled by wget. + * @buffer_size: size of client-provided buffer. Filled by client. + * @set_bootdev: set boot device with download. Filled by client. + * @check_buffer_size: check download does not exceed buffer size. + * Filled by client. + * @hdr_cont_len: content length according to headers. Filled by wget + * @headers: buffer for headers. Filled by wget. + */ +struct wget_http_info { + enum wget_http_method method; + u32 status_code; + ulong file_size; + ulong buffer_size; + bool set_bootdev; + bool check_buffer_size; + u32 hdr_cont_len; + char *headers; +}; + +extern struct wget_http_info default_wget_info; +extern struct wget_http_info *wget_info; +int wget_request(ulong dst_addr, char *uri, struct wget_http_info *info); + #endif /* __NET_COMMON_H__ */ diff --git a/include/net-legacy.h b/include/net-legacy.h index 1f62ebff51d..bc0f0cde9fe 100644 --- a/include/net-legacy.h +++ b/include/net-legacy.h @@ -416,6 +416,7 @@ int net_send_ip_packet(uchar *ether, struct in_addr dest, int dport, int sport, /** * net_send_tcp_packet() - Transmit TCP packet. * @payload_len: length of payload + * @dhost: Destination host * @dport: Destination TCP port * @sport: Source TCP port * @action: TCP action to be performed @@ -424,8 +425,8 @@ int net_send_ip_packet(uchar *ether, struct in_addr dest, int dport, int sport, * * Return: 0 on success, other value on failure */ -int net_send_tcp_packet(int payload_len, int dport, int sport, u8 action, - u32 tcp_seq_num, u32 tcp_ack_num); +int net_send_tcp_packet(int payload_len, struct in_addr dhost, int dport, + int sport, u8 action, u32 tcp_seq_num, u32 tcp_ack_num); int net_send_udp_packet(uchar *ether, struct in_addr dest, int dport, int sport, int payload_len); diff --git a/include/net-lwip.h b/include/net-lwip.h index 1c3583f82a1..4d7f9387d1d 100644 --- a/include/net-lwip.h +++ b/include/net-lwip.h @@ -17,15 +17,6 @@ struct netif *net_lwip_get_netif(void); int net_lwip_rx(struct udevice *udev, struct netif *netif); /** - * wget_with_dns() - runs dns host IP address resulution before wget - * - * @dst_addr: destination address to download the file - * @uri: uri string of target file of wget - * Return: downloaded file size, negative if failed - */ - -int wget_with_dns(ulong dst_addr, char *uri); -/** * wget_validate_uri() - varidate the uri * * @uri: uri string of target file of wget diff --git a/include/net/tcp.h b/include/net/tcp.h index c29d4ce24a7..5022fa9dc1b 100644 --- a/include/net/tcp.h +++ b/include/net/tcp.h @@ -265,6 +265,7 @@ union tcp_build_pkt { * @TCP_CLOSING: Rec FIN, sent FIN, ACK waiting for ACK * @TCP_FIN_WAIT_1: Sent FIN waiting for response * @TCP_FIN_WAIT_2: Rec ACK from FIN sent, waiting for FIN + * @TCP_LAST_ACK: Waiting for ACK of the connection termination */ enum tcp_state { TCP_CLOSED, @@ -274,30 +275,248 @@ enum tcp_state { TCP_CLOSE_WAIT, TCP_CLOSING, TCP_FIN_WAIT_1, - TCP_FIN_WAIT_2 + TCP_FIN_WAIT_2, + TCP_LAST_ACK, }; -enum tcp_state tcp_get_tcp_state(void); -void tcp_set_tcp_state(enum tcp_state new_state); -int tcp_set_tcp_header(uchar *pkt, int dport, int sport, int payload_len, - u8 action, u32 tcp_seq_num, u32 tcp_ack_num); +/** + * enum tcp_status - TCP stream status for connection + * @TCP_ERR_OK: no rx/tx errors + * @TCP_ERR_TOUT: rx/tx timeout happened + * @TCP_ERR_RST: connection was reset + * @TCP_ERR_IO: input/output error + */ +enum tcp_status { + TCP_ERR_OK = 0, + TCP_ERR_TOUT, + TCP_ERR_RST, + TCP_ERR_IO +}; /** - * rxhand_tcp() - An incoming packet handler. - * @pkt: pointer to the application packet - * @dport: destination TCP port - * @sip: source IP address - * @sport: source TCP port - * @tcp_seq_num: TCP sequential number - * @tcp_ack_num: TCP acknowledgment number - * @action: TCP action (SYN, ACK, FIN, etc) - * @len: packet length + * struct tcp_stream - TCP data stream structure + * @rhost: Remote host, network byte order + * @rport: Remote port, host byte order + * @lport: Local port, host byte order + * + * @priv: User private data (not used by tcp module) + * + * @max_retry_count: Maximum retransmit attempts (default 3) + * @initial_timeout: Timeout from initial TX to reTX (default 2 sec) + * @rx_inactiv_timeout: Maximum time from last rx till connection drop + * (default 30 sec) + * + * @on_closed: User callback, called just before destroying TCP stream + * @on_established: User callback, called when TCP stream enters + * TCP_ESTABLISHED state + * @on_rcv_nxt_update: User callback, called when all data in the segment + * [0..rx_bytes - 1] was received + * @on_snd_una_update: User callback, called when all data in the segment + * [0..tx_bytes - 1] were transferred and acknowledged + * @rx: User callback, called on receive of segment + * [rx_offs..rx_offs+len-1]. If NULL -- all incoming data + * will be ignored. User SHOULD store the segment and + * return the number of accepted bytes or negative value + * on error. + * WARNING: Previous segmengs may not be received yet + * @tx: User callback, called on transmit/retransmit of segment + * [tx_offs..tx_offs+maxlen-1]. If NULL -- no data will + * be transmitted. User SHOULD fill provided buffer and + * return the number of bytes in the buffer or negative + * value on error. + * WARNING: do not use tcp_stream_close() from this + * callback (it will break stream). Better use + * on_snd_una_update() callback for such purposes. + * + * @time_last_rx: Arrival time of last valid incoming package (ticks) + * @time_start: Timeout start time (ticks) + * @time_delta: Timeout duration (ticks) + * @time_handler Timeout handler for a stream + * + * @state: TCP connection state + * @status: TCP stream status (OK or ERR) + * @rx_packets: total number of received packets + * @tx_packets: total number of transmitted packets + * + * @fin_rx: Non-zero if TCP_FIN was received + * @fin_rx_seq: TCP sequence of rx FIN bit + * @fin_tx: Non-zero if TCP_FIN was sent (or planned to send) + * @fin_tx_seq: TCP sequence of tx FIN bit + * + * @iss: Initial send sequence number + * @snd_una: Send unacknowledged + * @snd_nxt: Send next + * @snd_wnd: Send window (in bytes) + * @snd_wl1: Segment sequence number used for last window update + * @snd_wl2: Segment acknowledgment number used for last window update + * + * @irs: Initial receive sequence number + * @rcv_nxt: Receive next + * @rcv_wnd: Receive window (in bytes) + * + * @loc_timestamp: Local timestamp + * @rmt_timestamp: Remote timestamp + * + * @rmt_win_scale: Remote window scale factor + * + * @lost: Used for SACK + * + * @retry_cnt: Number of retry attempts remaining. Only SYN, FIN + * or DATA segments are tried to retransmit. + * @retry_timeout: Current retry timeout (ms) + * @retry_action: TCP flags used for sending + * @retry_seq_num: TCP sequence for retransmit + * retry_tx_len: Number of data to transmit + * @retry_tx_offs: Position in the TX stream */ -typedef void rxhand_tcp(uchar *pkt, u16 dport, - struct in_addr sip, u16 sport, - u32 tcp_seq_num, u32 tcp_ack_num, - u8 action, unsigned int len); -void tcp_set_tcp_handler(rxhand_tcp *f); +struct tcp_stream { + struct in_addr rhost; + u16 rport; + u16 lport; + + void *priv; + + int max_retry_count; + int initial_timeout; + int rx_inactiv_timeout; + + void (*on_closed)(struct tcp_stream *tcp); + void (*on_established)(struct tcp_stream *tcp); + void (*on_rcv_nxt_update)(struct tcp_stream *tcp, u32 rx_bytes); + void (*on_snd_una_update)(struct tcp_stream *tcp, u32 tx_bytes); + int (*rx)(struct tcp_stream *tcp, u32 rx_offs, void *buf, int len); + int (*tx)(struct tcp_stream *tcp, u32 tx_offs, void *buf, int maxlen); + + ulong time_last_rx; + ulong time_start; + ulong time_delta; + void (*time_handler)(struct tcp_stream *tcp); + + enum tcp_state state; + enum tcp_status status; + u32 rx_packets; + u32 tx_packets; + + int fin_rx; + u32 fin_rx_seq; + + int fin_tx; + u32 fin_tx_seq; + + u32 iss; + u32 snd_una; + u32 snd_nxt; + u32 snd_wnd; + u32 snd_wl1; + u32 snd_wl2; + + u32 irs; + u32 rcv_nxt; + u32 rcv_wnd; + + /* TCP option timestamp */ + u32 loc_timestamp; + u32 rmt_timestamp; + + /* TCP window scale */ + u8 rmt_win_scale; + + /* TCP sliding window control used to request re-TX */ + struct tcp_sack_v lost; + + /* used for data retransmission */ + int retry_cnt; + int retry_timeout; + u8 retry_action; + u32 retry_seq_num; + u32 retry_tx_len; + u32 retry_tx_offs; +}; + +void tcp_init(void); + +/* + * This function sets user callback called on TCP stream creation. + * Callback should: + * + Check TCP stream endpoint and make connection verdict + * - return non-zero value to accept connection + * - return zero to drop connection + * + Setup TCP stream callbacks like: on_closed(), on_established(), + * n_rcv_nxt_update(), on_snd_una_update(), rx() and tx(). + * + Setup other stream related data + * + * WARNING: User MUST setup TCP stream on_create handler. Without it + * no connection (including outgoung) will be created. + */ +void tcp_stream_set_on_create_handler(int (*on_create)(struct tcp_stream *)); + +/* + * tcp_stream_get -- Get or create TCP stream + * @is_new: if non-zero and no stream found, then create a new one + * @rhost: Remote host, network byte order + * @rport: Remote port, host byte order + * @lport: Local port, host byte order + * + * Returns: TCP stream structure or NULL (if not found/created) + */ +struct tcp_stream *tcp_stream_get(int is_new, struct in_addr rhost, + u16 rport, u16 lport); + +/* + * tcp_stream_connect -- Create new TCP stream for remote connection. + * @rhost: Remote host, network byte order + * @rport: Remote port, host byte order + * + * Returns: TCP new stream structure or NULL (if not created). + * Random local port will be used. + */ +struct tcp_stream *tcp_stream_connect(struct in_addr rhost, u16 rport); + +/* + * tcp_stream_put -- Return stream to a TCP subsystem. Subsystem will + * check stream and destroy it (if stream was already + * closed). Otherwize no stream change will happen. + * @tcp: TCP stream to put + */ +void tcp_stream_put(struct tcp_stream *tcp); + +/* + * tcp_stream_restart_rx_timer -- Restart RX inactivity timer. Usually there + * is no needs to call this function. Timer + * will be restarted on receiving of any valid + * tcp packet belonging to a stream. + * + * This function may be used to prevent connection + * break in the following case: + * - u-boot is busy with very long data processing + * - remote side waits for u-boot reply + * + * @tcp: TCP stream to put + */ +void tcp_stream_restart_rx_timer(struct tcp_stream *tcp); + +enum tcp_state tcp_stream_get_state(struct tcp_stream *tcp); +enum tcp_status tcp_stream_get_status(struct tcp_stream *tcp); + +/* + * tcp_stream_rx_offs(), + * tcp_stream_tx_offs() -- Returns offset of first unacknowledged byte + * in receive/transmit stream correspondingly. + * The result is NOT affected by sin/fin flags. + * @tcp: TCP stream + */ +u32 tcp_stream_rx_offs(struct tcp_stream *tcp); +u32 tcp_stream_tx_offs(struct tcp_stream *tcp); + +/* reset tcp stream */ +void tcp_stream_reset(struct tcp_stream *tcp); +/* force TCP stream closing, do NOT use from tcp->tx callback */ +void tcp_stream_close(struct tcp_stream *tcp); + +void tcp_streams_poll(void); + +int tcp_set_tcp_header(struct tcp_stream *tcp, uchar *pkt, int payload_len, + u8 action, u32 tcp_seq_num, u32 tcp_ack_num); void rxhand_tcp_f(union tcp_build_pkt *b, unsigned int len); diff --git a/include/net/wget.h b/include/net/wget.h index 6714f7ea573..9a423b30414 100644 --- a/include/net/wget.h +++ b/include/net/wget.h @@ -8,14 +8,6 @@ */ void wget_start(void); -enum wget_state { - WGET_CLOSED, - WGET_CONNECTING, - WGET_CONNECTED, - WGET_TRANSFERRING, - WGET_TRANSFERRED -}; - #define DEBUG_WGET 0 /* Set to 1 for debug messages */ #define WGET_RETRY_COUNT 30 #define WGET_TIMEOUT 2000UL diff --git a/include/netdev.h b/include/netdev.h index 2a06d9a261b..949245ecdec 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -117,7 +117,7 @@ static inline int pci_eth_init(struct bd_info *bis) return num; } -struct mii_dev *fec_get_miibus(ulong base_addr, int dev_id); +struct mii_dev *fec_get_miibus(struct udevice *dev, ulong base_addr, int dev_id); #ifdef CONFIG_PHYLIB struct phy_device; diff --git a/include/ns16550.h b/include/ns16550.h index 7f481300083..5d9ff105411 100644 --- a/include/ns16550.h +++ b/include/ns16550.h @@ -25,6 +25,7 @@ #define __ns16550_h #include <linux/types.h> +#include <serial.h> #if CONFIG_IS_ENABLED(DM_SERIAL) || defined(CONFIG_NS16550_DYNAMIC) || \ defined(CONFIG_DEBUG_UART) @@ -116,6 +117,15 @@ struct ns16550 { #endif }; +#if CONFIG_IS_ENABLED(DM_SERIAL) +#define serial_out(value, addr) \ + ns16550_writeb(com_port, \ + (unsigned char *)(addr) - (unsigned char *)com_port, value) +#define serial_in(addr) \ + ns16550_readb(com_port, \ + (unsigned char *)(addr) - (unsigned char *)com_port) +#endif + #define thr rbr #define iir fcr #define dll rbr @@ -225,6 +235,14 @@ void ns16550_putc(struct ns16550 *com_port, char c); char ns16550_getc(struct ns16550 *com_port); int ns16550_tstc(struct ns16550 *com_port); void ns16550_reinit(struct ns16550 *com_port, int baud_divisor); +int ns16550_serial_putc(struct udevice *dev, const char ch); +int ns16550_serial_pending(struct udevice *dev, bool input); +int ns16550_serial_getc(struct udevice *dev); +int ns16550_serial_setbrg(struct udevice *dev, int baudrate); +int ns16550_serial_setconfig(struct udevice *dev, uint serial_config); +int ns16550_serial_getinfo(struct udevice *dev, struct serial_device_info *info); +void ns16550_writeb(struct ns16550 *port, int offset, int value); +void ns16550_setbrg(struct ns16550 *com_port, int baud_divisor); /** * ns16550_calc_divisor() - calculate the divisor given clock and baud rate diff --git a/include/part.h b/include/part.h index 92662677551..fcb3c13dea4 100644 --- a/include/part.h +++ b/include/part.h @@ -74,6 +74,7 @@ struct disk_partition { * PART_EFI_SYSTEM_PARTITION the partition is an EFI system partition */ int bootable; + u16 type_flags; /* top 16 bits of GPT partition attributes */ #if CONFIG_IS_ENABLED(PARTITION_UUIDS) char uuid[UUID_STR_LEN + 1]; /* filesystem UUID as string, if exists */ #endif diff --git a/include/ppc_asm.tmpl b/include/ppc_asm.tmpl index db7b1668d99..0b858c41e32 100644 --- a/include/ppc_asm.tmpl +++ b/include/ppc_asm.tmpl @@ -45,40 +45,40 @@ /*************************************************************************** - * Register names + * Register names. The %r1 offers some error-checking in GNU as. */ -#define r0 0 -#define r1 1 -#define r2 2 -#define r3 3 -#define r4 4 -#define r5 5 -#define r6 6 -#define r7 7 -#define r8 8 -#define r9 9 -#define r10 10 -#define r11 11 -#define r12 12 -#define r13 13 -#define r14 14 -#define r15 15 -#define r16 16 -#define r17 17 -#define r18 18 -#define r19 19 -#define r20 20 -#define r21 21 -#define r22 22 -#define r23 23 -#define r24 24 -#define r25 25 -#define r26 26 -#define r27 27 -#define r28 28 -#define r29 29 -#define r30 30 -#define r31 31 +#define r0 %r0 +#define r1 %r1 +#define r2 %r2 +#define r3 %r3 +#define r4 %r4 +#define r5 %r5 +#define r6 %r6 +#define r7 %r7 +#define r8 %r8 +#define r9 %r9 +#define r10 %r10 +#define r11 %r11 +#define r12 %r12 +#define r13 %r13 +#define r14 %r14 +#define r15 %r15 +#define r16 %r16 +#define r17 %r17 +#define r18 %r18 +#define r19 %r19 +#define r20 %r20 +#define r21 %r21 +#define r22 %r22 +#define r23 %r23 +#define r24 %r24 +#define r25 %r25 +#define r26 %r26 +#define r27 %r27 +#define r28 %r28 +#define r29 %r29 +#define r30 %r30 +#define r31 %r31 #if defined(CONFIG_MPC8xx) diff --git a/include/renesas/rzg2l-pfc.h b/include/renesas/rzg2l-pfc.h index 2df17ece2a3..0c94487754d 100644 --- a/include/renesas/rzg2l-pfc.h +++ b/include/renesas/rzg2l-pfc.h @@ -22,6 +22,7 @@ #define PIN_CFG_FILONOFF BIT(10) #define PIN_CFG_FILNUM BIT(11) #define PIN_CFG_FILCLKSEL BIT(12) +#define PIN_CFG_OEN BIT(13) #define RZG2L_MPXED_PIN_FUNCS (PIN_CFG_IOLH_A | \ PIN_CFG_SR | \ @@ -77,9 +78,12 @@ #define IEN(n) (0x1800 + (n) * 8) #define PWPR 0x3014 #define SD_CH(n) (0x3000 + (n) * 4) +#define ETH_POC(ch) (0x300c + (ch) * 4) #define QSPI 0x3008 +#define ETH_MODE 0x3018 #define PVDD_1800 1 /* I/O domain voltage <= 1.8V */ +#define PVDD_2500 2 /* I/O domain voltage 2.5V */ #define PVDD_3300 0 /* I/O domain voltage >= 3.3V */ #define PWPR_B0WI BIT(7) /* Bit Write Disable */ diff --git a/include/spl.h b/include/spl.h index 269e36bb441..43b344dbc55 100644 --- a/include/spl.h +++ b/include/spl.h @@ -268,8 +268,8 @@ enum spl_sandbox_flags { struct spl_image_info { const char *name; u8 os; - uintptr_t load_addr; - uintptr_t entry_point; + ulong load_addr; + ulong entry_point; #if CONFIG_IS_ENABLED(LOAD_FIT) || CONFIG_IS_ENABLED(LOAD_FIT_FULL) void *fdt_addr; #endif @@ -951,9 +951,9 @@ void __noreturn spl_invoke_atf(struct spl_image_info *spl_image); * * Return: bl31 params structure pointer */ -struct bl31_params *bl2_plat_get_bl31_params(uintptr_t bl32_entry, - uintptr_t bl33_entry, - uintptr_t fdt_addr); +struct bl31_params *bl2_plat_get_bl31_params(ulong bl32_entry, + ulong bl33_entry, + ulong fdt_addr); /** * bl2_plat_get_bl31_params_default() - prepare params for bl31. @@ -972,9 +972,9 @@ struct bl31_params *bl2_plat_get_bl31_params(uintptr_t bl32_entry, * * Return: bl31 params structure pointer */ -struct bl31_params *bl2_plat_get_bl31_params_default(uintptr_t bl32_entry, - uintptr_t bl33_entry, - uintptr_t fdt_addr); +struct bl31_params *bl2_plat_get_bl31_params_default(ulong bl32_entry, + ulong bl33_entry, + ulong fdt_addr); /** * bl2_plat_get_bl31_params_v2() - return params for bl31 @@ -988,9 +988,9 @@ struct bl31_params *bl2_plat_get_bl31_params_default(uintptr_t bl32_entry, * * Return: bl31 params structure pointer */ -struct bl_params *bl2_plat_get_bl31_params_v2(uintptr_t bl32_entry, - uintptr_t bl33_entry, - uintptr_t fdt_addr); +struct bl_params *bl2_plat_get_bl31_params_v2(ulong bl32_entry, + ulong bl33_entry, + ulong fdt_addr); /** * bl2_plat_get_bl31_params_v2_default() - prepare params for bl31. @@ -1007,9 +1007,9 @@ struct bl_params *bl2_plat_get_bl31_params_v2(uintptr_t bl32_entry, * * Return: bl31 params structure pointer */ -struct bl_params *bl2_plat_get_bl31_params_v2_default(uintptr_t bl32_entry, - uintptr_t bl33_entry, - uintptr_t fdt_addr); +struct bl_params *bl2_plat_get_bl31_params_v2_default(ulong bl32_entry, + ulong bl33_entry, + ulong fdt_addr); /** * spl_optee_entry - entry function for optee * diff --git a/include/sysinfo.h b/include/sysinfo.h index 8a77ef44856..027a463dc33 100644 --- a/include/sysinfo.h +++ b/include/sysinfo.h @@ -40,29 +40,29 @@ struct udevice; /** enum sysinfo_id - Standard IDs defined by U-Boot */ enum sysinfo_id { - SYSINFO_ID_NONE, + SYSID_NONE, /* For SMBIOS tables */ - SYSINFO_ID_SMBIOS_SYSTEM_MANUFACTURER, - SYSINFO_ID_SMBIOS_SYSTEM_PRODUCT, - SYSINFO_ID_SMBIOS_SYSTEM_VERSION, - SYSINFO_ID_SMBIOS_SYSTEM_SERIAL, - SYSINFO_ID_SMBIOS_SYSTEM_SKU, - SYSINFO_ID_SMBIOS_SYSTEM_FAMILY, - SYSINFO_ID_SMBIOS_BASEBOARD_MANUFACTURER, - SYSINFO_ID_SMBIOS_BASEBOARD_PRODUCT, - SYSINFO_ID_SMBIOS_BASEBOARD_VERSION, - SYSINFO_ID_SMBIOS_BASEBOARD_SERIAL, - SYSINFO_ID_SMBIOS_BASEBOARD_ASSET_TAG, + SYSID_SM_SYSTEM_MANUFACTURER, + SYSID_SM_SYSTEM_PRODUCT, + SYSID_SM_SYSTEM_VERSION, + SYSID_SM_SYSTEM_SERIAL, + SYSID_SM_SYSTEM_SKU, + SYSID_SM_SYSTEM_FAMILY, + SYSID_SM_BASEBOARD_MANUFACTURER, + SYSID_SM_BASEBOARD_PRODUCT, + SYSID_SM_BASEBOARD_VERSION, + SYSID_SM_BASEBOARD_SERIAL, + SYSID_SM_BASEBOARD_ASSET_TAG, /* For show_board_info() */ - SYSINFO_ID_BOARD_MODEL, - SYSINFO_ID_BOARD_MANUFACTURER, - SYSINFO_ID_PRIOR_STAGE_VERSION, - SYSINFO_ID_PRIOR_STAGE_DATE, + SYSID_BOARD_MODEL, + SYSID_BOARD_MANUFACTURER, + SYSID_PRIOR_STAGE_VERSION, + SYSID_PRIOR_STAGE_DATE, /* First value available for downstream/board used */ - SYSINFO_ID_USER = 0x1000, + SYSID_USER = 0x1000, }; struct sysinfo_ops { diff --git a/include/u-boot/crc.h b/include/u-boot/crc.h index 5174bd7ac41..b2badaf6a97 100644 --- a/include/u-boot/crc.h +++ b/include/u-boot/crc.h @@ -25,6 +25,9 @@ */ unsigned int crc8(unsigned int crc_start, const unsigned char *vptr, int len); +void crc8_wd_buf(const unsigned char *input, unsigned int len, + unsigned char output[1], unsigned int chunk_sz); + /* lib/crc16.c - 16 bit CRC with polynomial x^16 + x^15 + x^2 + 1 */ uint16_t crc16(uint16_t crc, const unsigned char *buffer, size_t len); diff --git a/include/u-boot/md5.h b/include/u-boot/md5.h index c98b1a58088..2a52e169051 100644 --- a/include/u-boot/md5.h +++ b/include/u-boot/md5.h @@ -6,7 +6,9 @@ #ifndef _MD5_H #define _MD5_H -#if defined(CONFIG_MBEDTLS_LIB_CRYPTO) +#include <linux/kconfig.h> + +#if CONFIG_IS_ENABLED(MBEDTLS_LIB_CRYPTO) #include <mbedtls/md5.h> #endif #include "compiler.h" @@ -14,7 +16,7 @@ #define MD5_SUM_LEN 16 #define MD5_DEF_CHUNK_SZ 0x10000 -#if defined(CONFIG_MBEDTLS_LIB_CRYPTO) +#if CONFIG_IS_ENABLED(MBEDTLS_LIB_CRYPTO) typedef mbedtls_md5_context MD5Context; #else typedef struct MD5Context { diff --git a/include/u-boot/sha1.h b/include/u-boot/sha1.h index 2fca7f1be16..dd66258bbe9 100644 --- a/include/u-boot/sha1.h +++ b/include/u-boot/sha1.h @@ -14,9 +14,10 @@ #ifndef _SHA1_H #define _SHA1_H +#include <linux/kconfig.h> #include <linux/types.h> -#if defined(CONFIG_MBEDTLS_LIB_CRYPTO) +#if CONFIG_IS_ENABLED(MBEDTLS_LIB_CRYPTO) /* * FIXME: * MbedTLS define the members of "mbedtls_sha256_context" as private, @@ -47,7 +48,7 @@ extern "C" { extern const uint8_t sha1_der_prefix[]; -#if defined(CONFIG_MBEDTLS_LIB_CRYPTO) +#if CONFIG_IS_ENABLED(MBEDTLS_LIB_CRYPTO) typedef mbedtls_sha1_context sha1_context; #else /** diff --git a/include/u-boot/sha256.h b/include/u-boot/sha256.h index b58d5b58d39..44a9b528b48 100644 --- a/include/u-boot/sha256.h +++ b/include/u-boot/sha256.h @@ -1,9 +1,10 @@ #ifndef _SHA256_H #define _SHA256_H +#include <linux/kconfig.h> #include <linux/types.h> -#if defined(CONFIG_MBEDTLS_LIB_CRYPTO) +#if CONFIG_IS_ENABLED(MBEDTLS_LIB_CRYPTO) /* * FIXME: * MbedTLS define the members of "mbedtls_sha256_context" as private, @@ -27,7 +28,7 @@ extern const uint8_t sha256_der_prefix[]; /* Reset watchdog each time we process this many bytes */ #define CHUNKSZ_SHA256 (64 * 1024) -#if defined(CONFIG_MBEDTLS_LIB_CRYPTO) +#if CONFIG_IS_ENABLED(MBEDTLS_LIB_CRYPTO) typedef mbedtls_sha256_context sha256_context; #else typedef struct { diff --git a/include/u-boot/sha512.h b/include/u-boot/sha512.h index 7e10f590a1d..92660d93357 100644 --- a/include/u-boot/sha512.h +++ b/include/u-boot/sha512.h @@ -1,9 +1,10 @@ #ifndef _SHA512_H #define _SHA512_H +#include <linux/kconfig.h> #include <linux/types.h> -#if defined(CONFIG_MBEDTLS_LIB_CRYPTO) +#if CONFIG_IS_ENABLED(MBEDTLS_LIB_CRYPTO) #include <mbedtls/sha512.h> #endif @@ -16,7 +17,7 @@ #define CHUNKSZ_SHA384 (16 * 1024) #define CHUNKSZ_SHA512 (16 * 1024) -#if defined(CONFIG_MBEDTLS_LIB_CRYPTO) +#if CONFIG_IS_ENABLED(MBEDTLS_LIB_CRYPTO) typedef mbedtls_sha512_context sha384_context; typedef mbedtls_sha512_context sha512_context; #else |