diff options
Diffstat (limited to 'include')
103 files changed, 1390 insertions, 1316 deletions
diff --git a/include/ahci.h b/include/ahci.h index d4f0f3ce0e7..eb05cc687f6 100644 --- a/include/ahci.h +++ b/include/ahci.h @@ -137,8 +137,8 @@ struct ahci_ioports { void __iomem *port_mmio; struct ahci_cmd_hdr *cmd_slot; struct ahci_sg *cmd_tbl_sg; - ulong cmd_tbl; - u32 rx_fis; + void *cmd_tbl; + void *rx_fis; }; /** diff --git a/include/asm-generic/sections.h b/include/asm-generic/sections.h index 024b1adde27..d59787948fd 100644 --- a/include/asm-generic/sections.h +++ b/include/asm-generic/sections.h @@ -28,6 +28,8 @@ extern char __efi_helloworld_begin[]; extern char __efi_helloworld_end[]; extern char __efi_var_file_begin[]; extern char __efi_var_file_end[]; +extern char __efi_capsule_sig_begin[]; +extern char __efi_capsule_sig_end[]; /* Private data used by of-platdata devices/uclasses */ extern char __priv_data_start[], __priv_data_end[]; diff --git a/include/axp221.h b/include/axp221.h index 32b988f3a9c..8a4a3cca82f 100644 --- a/include/axp221.h +++ b/include/axp221.h @@ -53,10 +53,6 @@ #ifdef CONFIG_AXP221_POWER #define AXP_POWER_STATUS 0x00 #define AXP_POWER_STATUS_ALDO_IN BIT(0) -#define AXP_VBUS_IPSOUT 0x30 -#define AXP_VBUS_IPSOUT_DRIVEBUS (1 << 2) -#define AXP_MISC_CTRL 0x8f -#define AXP_MISC_CTRL_N_VBUSEN_FUNC (1 << 4) #define AXP_GPIO0_CTRL 0x90 #define AXP_GPIO1_CTRL 0x92 #define AXP_GPIO_CTRL_OUTPUT_LOW 0x00 /* Drive pin low */ diff --git a/include/axp809.h b/include/axp809.h index 71a7cb2aaa1..3bd71b3d1a3 100644 --- a/include/axp809.h +++ b/include/axp809.h @@ -47,10 +47,6 @@ #ifdef CONFIG_AXP809_POWER #define AXP_POWER_STATUS 0x00 #define AXP_POWER_STATUS_ALDO_IN BIT(0) -#define AXP_VBUS_IPSOUT 0x30 -#define AXP_VBUS_IPSOUT_DRIVEBUS (1 << 2) -#define AXP_MISC_CTRL 0x8f -#define AXP_MISC_CTRL_N_VBUSEN_FUNC (1 << 4) #define AXP_GPIO0_CTRL 0x90 #define AXP_GPIO1_CTRL 0x92 #define AXP_GPIO_CTRL_OUTPUT_LOW 0x00 /* Drive pin low */ diff --git a/include/axp818.h b/include/axp818.h index 08ac35d15fa..b3a9686e0e5 100644 --- a/include/axp818.h +++ b/include/axp818.h @@ -61,10 +61,6 @@ #ifdef CONFIG_AXP818_POWER #define AXP_POWER_STATUS 0x00 #define AXP_POWER_STATUS_ALDO_IN BIT(0) -#define AXP_VBUS_IPSOUT 0x30 -#define AXP_VBUS_IPSOUT_DRIVEBUS (1 << 2) -#define AXP_MISC_CTRL 0x8f -#define AXP_MISC_CTRL_N_VBUSEN_FUNC (1 << 4) #define AXP_GPIO0_CTRL 0x90 #define AXP_GPIO1_CTRL 0x92 #define AXP_GPIO_CTRL_OUTPUT_LOW 0x00 /* Drive pin low */ diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 19d3c72a6f1..cf43fc05025 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -138,11 +138,10 @@ "setenv fdtfile am335x-evm.dtb; fi; " \ "if test $board_name = A335X_SK; then " \ "setenv fdtfile am335x-evmsk.dtb; fi; " \ - "if test $board_name = A335_ICE; then " \ - "setenv fdtfile am335x-icev2.dtb; " \ - "if test $ice_mii = mii; then " \ - "setenv pxe_label_override Pruss; fi;" \ - "fi; " \ + "if test $board_name = A335_ICE && test $ice_mii = rmii; then " \ + "setenv fdtfile am335x-icev2.dtb; fi; " \ + "if test $board_name = A335_ICE && test $ice_mii = mii; then " \ + "setenv fdtfile am335x-icev2-prueth.dtb; fi; " \ "if test $fdtfile = undefined; then " \ "echo WARNING: Could not determine device tree to use; fi; \0" \ "init_console=" \ diff --git a/include/configs/amd_versal2.h b/include/configs/amd_versal2.h index 6a40bbdf3a7..1ade6adfa0b 100644 --- a/include/configs/amd_versal2.h +++ b/include/configs/amd_versal2.h @@ -105,6 +105,14 @@ #define BOOTENV_DEV_NAME_JTAG(devtypeu, devtypel, instance) \ "jtag " +#define BOOT_TARGET_DEVICES_UFS(func) func(UFS, ufs, 0) + +#define BOOTENV_DEV_UFS(devtypeu, devtypel, instance) \ + "bootcmd_" #devtypel "=" #devtypel " init " #instance "; scsi scan;\0" + +#define BOOTENV_DEV_NAME_UFS(devtypeu, devtypel, instance) \ + "ufs " + #define BOOT_TARGET_DEVICES_DFU_USB(func) func(DFU_USB, dfu_usb, 0) #define BOOTENV_DEV_DFU_USB(devtypeu, devtypel, instance) \ @@ -117,11 +125,19 @@ #define BOOTENV_DEV_NAME_DFU_USB(devtypeu, devtypel, instance) \ "" +#if defined(CONFIG_USB_STORAGE) +#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0) func(USB, usb, 1) +#else +#define BOOT_TARGET_DEVICES_USB(func) +#endif + #define BOOT_TARGET_DEVICES(func) \ BOOT_TARGET_DEVICES_JTAG(func) \ BOOT_TARGET_DEVICES_MMC(func) \ + BOOT_TARGET_DEVICES_UFS(func) \ BOOT_TARGET_DEVICES_XSPI(func) \ BOOT_TARGET_DEVICES_DFU_USB(func) \ + BOOT_TARGET_DEVICES_USB(func) \ BOOT_TARGET_DEVICES_PXE(func) \ BOOT_TARGET_DEVICES_DHCP(func) diff --git a/include/configs/anbernic-rgxx3-rk3566.h b/include/configs/anbernic-rgxx3-rk3566.h index 3c4ea4e7d84..3d9e05a976a 100644 --- a/include/configs/anbernic-rgxx3-rk3566.h +++ b/include/configs/anbernic-rgxx3-rk3566.h @@ -3,10 +3,10 @@ #ifndef __ANBERNIC_RGXX3_RK3566_H #define __ANBERNIC_RGXX3_RK3566_H -#include <configs/rk3568_common.h> - #define ROCKCHIP_DEVICE_SETTINGS \ "stdout=serial,vidconsole\0" \ "stderr=serial,vidconsole\0" +#include <configs/rk3568_common.h> + #endif diff --git a/include/configs/apalis-tk1.h b/include/configs/apalis-tk1.h index 4c690a17856..dbb9881f6ab 100644 --- a/include/configs/apalis-tk1.h +++ b/include/configs/apalis-tk1.h @@ -12,9 +12,6 @@ #include "tegra124-common.h" -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE - #define FDT_MODULE "apalis-v1.2" #define FDT_MODULE_V1_0 "apalis" diff --git a/include/configs/apalis_t30.h b/include/configs/apalis_t30.h deleted file mode 100644 index 87a679efde6..00000000000 --- a/include/configs/apalis_t30.h +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2014-2016 Marcel Ziswiler - * - * Configuration settings for the Toradex Apalis T30 modules. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <linux/sizes.h> - -#include "tegra30-common.h" - -/* - * Board-specific serial config - * - * Apalis UART1: NVIDIA UARTA - * Apalis UART2: NVIDIA UARTD - * Apalis UART3: NVIDIA UARTB - * Apalis UART4: NVIDIA UARTC - */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE - -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/beaver.h b/include/configs/beaver.h deleted file mode 100644 index e622b7127e3..00000000000 --- a/include/configs/beaver.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <linux/sizes.h> - -#include "tegra30-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "NVIDIA Beaver" - -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE - -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/brzynq.h b/include/configs/brzynq.h new file mode 100644 index 00000000000..e2ebb2f1004 --- /dev/null +++ b/include/configs/brzynq.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Config file for BR Zynq board + * + * Copyright (C) 2024 + * B&R Industrial Automation GmbH - http://www.br-automation.com/ + */ + +#ifndef __CONFIG_BRZYNQ_H__ +#define __CONFIG_BRZYNQ_H__ + +/* Increase PHY_ANEG_TIMEOUT since the FPGA needs some setup time */ +#if IS_ENABLED(CONFIG_SPL_FPGA) +#define PHY_ANEG_TIMEOUT 8000 +#endif + +/* Use top mapped SRAM */ +#define CFG_SYS_INIT_RAM_ADDR 0xFFFF0000 +#define CFG_SYS_INIT_RAM_SIZE 0x2000 + +#endif /* __CONFIG_BRZYNQ_H__ */ diff --git a/include/configs/capricorn-common.h b/include/configs/capricorn-common.h index 4d95f3fd79b..7120a44d186 100644 --- a/include/configs/capricorn-common.h +++ b/include/configs/capricorn-common.h @@ -10,8 +10,6 @@ #include <linux/sizes.h> #include <asm/arch/imx-regs.h> -#include "siemens-env-common.h" - /* SPL config */ #ifdef CONFIG_XPL_BUILD #define CFG_MALLOC_F_ADDR 0x00120000 @@ -36,57 +34,9 @@ #define AHAB_ENV "sec_boot=no\0" #endif -#define MFG_ENV_SETTINGS_DEFAULT \ - "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ - "rdinit=/linuxrc " \ - "clk_ignore_unused "\ - "\0" \ - "kboot=booti\0"\ - "bootcmd_mfg=run mfgtool_args;" \ - "if iminfo ${initrd_addr}; then " \ - "if test ${tee} = yes; then " \ - "bootm ${tee_addr} ${initrd_addr} ${fdt_addr}; " \ - "else " \ - "booti ${loadaddr} ${initrd_addr} ${fdt_addr}; " \ - "fi; " \ - "else " \ - "echo \"Run fastboot ...\"; fastboot 0; " \ - "fi;\0" - -/* Boot M4 */ -#define M4_BOOT_ENV \ - "m4_0_image=m4_0.bin\0" \ - "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} " \ - "${loadaddr} ${m4_0_image}\0" \ - "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \ - -#define CFG_MFG_ENV_SETTINGS \ - MFG_ENV_SETTINGS_DEFAULT \ - "initrd_addr=0x83100000\0" \ - "initrd_high=0xffffffffffffffff\0" \ - "emmc_dev=0\0" - /* Initial environment variables */ #define CFG_EXTRA_ENV_SETTINGS \ - CFG_MFG_ENV_SETTINGS \ - M4_BOOT_ENV \ - AHAB_ENV \ - ENV_COMMON \ - "script=boot.scr\0" \ - "image=Image\0" \ - "panel=NULL\0" \ - "console=ttyLP2\0" \ - "fdt_addr=0x83000000\0" \ - "fdt_high=0xffffffffffffffff\0" \ - "cntr_addr=0x88000000\0" \ - "cntr_file=os_cntr_signed.bin\0" \ - "initrd_addr=0x83800000\0" \ - "initrd_high=0xffffffffffffffff\0" \ - "netdev=eth0\0" \ - "nfsopts=vers=3,udp,rsize=4096,wsize=4096,nolock rw\0" \ - "hostname=capricorn\0" \ - ENV_EMMC \ - ENV_NET + AHAB_ENV /* Default location for tftp and bootm */ diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h deleted file mode 100644 index 3412b883cbb..00000000000 --- a/include/configs/cardhu.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <linux/sizes.h> - -#include "tegra30-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "NVIDIA Cardhu" - -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE - -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/cei-tk1-som.h b/include/configs/cei-tk1-som.h deleted file mode 100644 index fbd38b77fe5..00000000000 --- a/include/configs/cei-tk1-som.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * (c) Copyright 2016, Data61 - * Commonwealth Scientific and Industrial Research Organisation (CSIRO) - * - * Based on jetson-tk1.h which is: - * (C) Copyright 2013-2014 - * NVIDIA Corporation <www.nvidia.com> - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <linux/sizes.h> - -#include "tegra124-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "CEI tk1-som" - -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE - -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/colibri_t20.h b/include/configs/colibri_t20.h deleted file mode 100644 index bc616d14368..00000000000 --- a/include/configs/colibri_t20.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2012 Lucas Stach - * - * Configuration settings for the Toradex Colibri T20 modules. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "tegra20-common.h" - -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE - -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/colibri_t30.h b/include/configs/colibri_t30.h deleted file mode 100644 index 1f474669a73..00000000000 --- a/include/configs/colibri_t30.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2013-2016 Stefan Agner - * - * Configuration settings for the Toradex Colibri T30 modules. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <linux/sizes.h> - -#include "tegra30-common.h" - -/* High-level configuration options */ - -/* - * Board-specific serial config - * - * Colibri UART-A: NVIDIA UARTA - * Colibri UART-B: NVIDIA UARTD - * Colibri UART-C: NVIDIA UARTB - */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE - -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h deleted file mode 100644 index 095554157fa..00000000000 --- a/include/configs/dalmore.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <linux/sizes.h> - -#include "tegra114-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "NVIDIA Dalmore" - -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE - -/* Environment in eMMC, at the end of 2nd "boot sector" */ - -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/dragonboard410c.h b/include/configs/dragonboard410c.h index 00102cd5c4f..c31c6c57c1a 100644 --- a/include/configs/dragonboard410c.h +++ b/include/configs/dragonboard410c.h @@ -18,15 +18,4 @@ #define PHYS_SDRAM_1_SIZE SZ_1G #define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 -/* Environment */ -#define BOOT_TARGET_DEVICES(func) \ - func(USB, usb, 0) \ - func(MMC, mmc, 1) \ - func(MMC, mmc, 0) \ - func(DHCP, dhcp, na) - -#include <config_distro_bootcmd.h> - -#define CFG_EXTRA_ENV_SETTINGS BOOTENV - #endif diff --git a/include/configs/endeavoru.h b/include/configs/endeavoru.h deleted file mode 100644 index 33d0021ec13..00000000000 --- a/include/configs/endeavoru.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * (C) Copyright 2010,2012 - * NVIDIA Corporation <www.nvidia.com> - * - * (C) Copyright 2022 - * Svyatoslav Ryhel <clamor95@gmail.com> - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "tegra30-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "HTC One X" - -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE - -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/evb_rk3568.h b/include/configs/evb_rk3568.h index a0f2383bf2f..9070160cf58 100644 --- a/include/configs/evb_rk3568.h +++ b/include/configs/evb_rk3568.h @@ -6,10 +6,10 @@ #ifndef __EVB_RK3568_H #define __EVB_RK3568_H -#include <configs/rk3568_common.h> - #define ROCKCHIP_DEVICE_SETTINGS \ "stdout=serial,vidconsole\0" \ "stderr=serial,vidconsole\0" +#include <configs/rk3568_common.h> + #endif diff --git a/include/configs/evb_rk3588.h b/include/configs/evb_rk3588.h index 4568e2cace6..5ff1ddbfcbe 100644 --- a/include/configs/evb_rk3588.h +++ b/include/configs/evb_rk3588.h @@ -6,10 +6,10 @@ #ifndef __EVB_RK3588_H #define __EVB_RK3588_H -#include <configs/rk3588_common.h> - #define ROCKCHIP_DEVICE_SETTINGS \ "stdout=serial,vidconsole\0" \ "stderr=serial,vidconsole\0" +#include <configs/rk3588_common.h> + #endif diff --git a/include/configs/giedi.h b/include/configs/giedi.h deleted file mode 100644 index 19a795bcf86..00000000000 --- a/include/configs/giedi.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2019 Siemens AG - * - */ - -#ifndef __GIEDI_H -#define __GIEDI_H - -#include "capricorn-common.h" - -/* DDR3 board total DDR is 1 GB */ -#undef PHYS_SDRAM_1_SIZE -#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1 GB */ - -#endif /* __GIEDI_H */ diff --git a/include/configs/grouper.h b/include/configs/grouper.h deleted file mode 100644 index b6ef6ff2ecb..00000000000 --- a/include/configs/grouper.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "tegra30-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "ASUS Google Nexus 7 (2012)" - -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE - -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/harmony.h b/include/configs/harmony.h deleted file mode 100644 index cae7acdb70b..00000000000 --- a/include/configs/harmony.h +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010-2012 - * NVIDIA Corporation <www.nvidia.com> - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <linux/sizes.h> -#include "tegra20-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "NVIDIA Harmony" - -/* Board-specific serial config */ - -/* UARTD: keyboard satellite board UART, default */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE -#ifdef CONFIG_TEGRA_ENABLE_UARTA -/* UARTA: debug board UART */ -#define CFG_SYS_NS16550_COM2 NV_PA_APB_UARTA_BASE -#endif - -/* NAND support */ - -/* Environment in NAND (which is 512M), aligned to start of last sector */ - -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/ideapad-yoga-11.h b/include/configs/ideapad-yoga-11.h deleted file mode 100644 index c4e6b2a647c..00000000000 --- a/include/configs/ideapad-yoga-11.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "tegra30-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "Lenovo Ideapad Yoga 11" - -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE - -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/jetson-tk1.h b/include/configs/jetson-tk1.h deleted file mode 100644 index 9858f8ff2b5..00000000000 --- a/include/configs/jetson-tk1.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * (C) Copyright 2013-2014 - * NVIDIA Corporation <www.nvidia.com> - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <linux/sizes.h> - -#include "tegra124-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "NVIDIA Jetson TK1" - -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE - -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/khadas-edge2-rk3588s.h b/include/configs/khadas-edge2-rk3588s.h index d279cf3826a..fe8461d6362 100644 --- a/include/configs/khadas-edge2-rk3588s.h +++ b/include/configs/khadas-edge2-rk3588s.h @@ -6,10 +6,10 @@ #ifndef __KHADAS_EDGE2_RK3588_H #define __KHADAS_EDGE2_RK3588_H -#include <configs/rk3588_common.h> - #define ROCKCHIP_DEVICE_SETTINGS \ "stdout=serial,vidconsole\0" \ "stderr=serial,vidconsole\0" +#include <configs/rk3588_common.h> + #endif /* __KHADAS_EDGE2_RK3588_H */ diff --git a/include/configs/medcom-wide.h b/include/configs/medcom-wide.h deleted file mode 100644 index 8dbe741278a..00000000000 --- a/include/configs/medcom-wide.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation <www.nvidia.com> - * (C) Copyright 2011-2012 - * Avionic Design GmbH <www.avionic-design.de> - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "tegra20-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "Avionic Design Medcom-Wide" - -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE - -/* NAND support */ - -/* Environment in NAND, aligned to start of last sector */ - -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/mocha.h b/include/configs/mocha.h index 1c2eb906085..7255f31baec 100644 --- a/include/configs/mocha.h +++ b/include/configs/mocha.h @@ -10,12 +10,6 @@ #include "tegra124-common.h" -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "Xiaomi Mocha" - -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE - #ifdef CONFIG_TEGRA_SUPPORT_NON_SECURE #define CFG_PRAM 0x38400 /* 225 MB */ #endif diff --git a/include/configs/mot.h b/include/configs/mot.h new file mode 100644 index 00000000000..018672cb28f --- /dev/null +++ b/include/configs/mot.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2023 + * Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <linux/sizes.h> +#include "tegra20-common.h" + +/* Tegra common post configuration overwrites text env in the board */ +#define BOARD_EXTRA_ENV_SETTINGS \ + "stdin=serial,tegra-kbc,button-kbd,cpcap-pwrbutton\0" + +#include "tegra-common-post.h" + +#endif /* __CONFIG_H */ diff --git a/include/configs/nyan-big.h b/include/configs/nyan-big.h deleted file mode 100644 index c04d402deb0..00000000000 --- a/include/configs/nyan-big.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2014 - * NVIDIA Corporation <www.nvidia.com> - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <linux/sizes.h> - -#include "tegra124-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "Google/NVIDIA Nyan-big" - -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE - -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/ouya.h b/include/configs/ouya.h deleted file mode 100644 index cc86c1002e3..00000000000 --- a/include/configs/ouya.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * (C) Copyright 2010,2012 - * NVIDIA Corporation <www.nvidia.com> - * - * (C) Copyright 2025 - * Svyatoslav Ryhel <clamor95@gmail.com> - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "tegra30-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "Ouya Game Console" - -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE - -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/p2371-0000.h b/include/configs/p2371-0000.h deleted file mode 100644 index a29d7135d0b..00000000000 --- a/include/configs/p2371-0000.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013-2015 - * NVIDIA Corporation <www.nvidia.com> - */ - -#ifndef _P2371_0000_H -#define _P2371_0000_H - -#include <linux/sizes.h> - -#include "tegra210-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "NVIDIA P2371-0000" - -/* Board-specific serial config */ - -/* Environment in eMMC, at the end of 2nd "boot sector" */ - -#include "tegra-common-post.h" - -#endif /* _P2371_0000_H */ diff --git a/include/configs/p2371-2180.h b/include/configs/p2371-2180.h deleted file mode 100644 index 0b077aba659..00000000000 --- a/include/configs/p2371-2180.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013-2015 - * NVIDIA Corporation <www.nvidia.com> - */ - -#ifndef _P2371_2180_H -#define _P2371_2180_H - -#include <linux/sizes.h> - -#include "tegra210-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "NVIDIA P2371-2180" - -/* Board-specific serial config */ - -/* Environment in eMMC, at the end of 2nd "boot sector" */ - -#include "tegra-common-post.h" - -#endif /* _P2371_2180_H */ diff --git a/include/configs/p2571.h b/include/configs/p2571.h deleted file mode 100644 index 5155aa7b1dd..00000000000 --- a/include/configs/p2571.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013-2015 - * NVIDIA Corporation <www.nvidia.com> - */ - -#ifndef _P2571_H -#define _P2571_H - -#include <linux/sizes.h> - -#include "tegra210-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "NVIDIA P2571" - -/* Board-specific serial config */ - -/* Environment in eMMC, at the end of 2nd "boot sector" */ - -#include "tegra-common-post.h" - -#endif /* _P2571_H */ diff --git a/include/configs/p2771-0000.h b/include/configs/p2771-0000.h deleted file mode 100644 index fc1b7c0302d..00000000000 --- a/include/configs/p2771-0000.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2013-2016, NVIDIA CORPORATION. - */ - -#ifndef _P2771_0000_H -#define _P2771_0000_H - -#include <linux/sizes.h> - -#include "tegra186-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "NVIDIA P2771-0000" - -/* Environment in eMMC, at the end of 2nd "boot sector" */ - -#include "tegra-common-post.h" - -#endif diff --git a/include/configs/p3450-0000.h b/include/configs/p3450-0000.h deleted file mode 100644 index 1138c1d306f..00000000000 --- a/include/configs/p3450-0000.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2018-2019 NVIDIA Corporation. - */ - -#ifndef _P3450_0000_H -#define _P3450_0000_H - -#include <linux/sizes.h> - -#include "tegra210-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "NVIDIA P3450-0000" - -/* Board-specific serial config */ - -/* General networking support */ -#include "tegra-common-post.h" - -#endif /* _P3450_0000_H */ diff --git a/include/configs/paz00.h b/include/configs/paz00.h deleted file mode 100644 index 950b3217642..00000000000 --- a/include/configs/paz00.h +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2010-2012 NVIDIA CORPORATION. All rights reserved. - * - * See file CREDITS for list of people who contributed to this - * project. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <linux/sizes.h> -#include "tegra20-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "Compal Paz00" - -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE - -/* Environment in eMMC, at the end of 2nd "boot sector" */ - -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/picasso.h b/include/configs/picasso.h deleted file mode 100644 index a58c7e5f353..00000000000 --- a/include/configs/picasso.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation <www.nvidia.com> - * - * (C) Copyright 2024 - * Svyatoslav Ryhel <clamor95@gmail.com> - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "tegra20-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "Acer Iconia Tab A500" - -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE - -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/plutux.h b/include/configs/plutux.h deleted file mode 100644 index 30bfce9f503..00000000000 --- a/include/configs/plutux.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation <www.nvidia.com> - * (C) Copyright 2011-2012 - * Avionic Design GmbH <www.avionic-design.de> - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "tegra20-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "Avionic Design Plutux" - -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE - -/* NAND support */ - -/* Environment in NAND, aligned to start of last sector */ - -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/powkiddy-x55-rk3566.h b/include/configs/powkiddy-x55-rk3566.h index 4b25c6a8774..8ace435434f 100644 --- a/include/configs/powkiddy-x55-rk3566.h +++ b/include/configs/powkiddy-x55-rk3566.h @@ -3,10 +3,10 @@ #ifndef __POWKIDDY_X55_RK3566_H #define __POWKIDDY_X55_RK3566_H -#include <configs/rk3568_common.h> - #define ROCKCHIP_DEVICE_SETTINGS \ "stdout=serial,vidconsole\0" \ "stderr=serial,vidconsole\0" +#include <configs/rk3568_common.h> + #endif diff --git a/include/configs/px30_common.h b/include/configs/px30_common.h index 13ed9011764..d0539003fd5 100644 --- a/include/configs/px30_common.h +++ b/include/configs/px30_common.h @@ -20,6 +20,7 @@ "scriptaddr=0x00500000\0" \ "pxefile_addr_r=0x00600000\0" \ "fdt_addr_r=0x08300000\0" \ + "fdtoverlay_addr_r=0x08400000\0" \ "kernel_addr_r=0x00280000\0" \ "ramdisk_addr_r=0x0a200000\0" \ "kernel_comp_addr_r=0x03e80000\0" \ diff --git a/include/configs/qc750.h b/include/configs/qc750.h deleted file mode 100644 index ad9f9146bb7..00000000000 --- a/include/configs/qc750.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * (C) Copyright 2010,2012 - * NVIDIA Corporation <www.nvidia.com> - * - * (C) Copyright 2023 - * Svyatoslav Ryhel <clamor95@gmail.com> - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "tegra30-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "Wexler QC750" - -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE - -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/rk3528_common.h b/include/configs/rk3528_common.h new file mode 100644 index 00000000000..f7dc6ecd594 --- /dev/null +++ b/include/configs/rk3528_common.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* Copyright Contributors to the U-Boot project. */ + +#ifndef __CONFIG_RK3528_COMMON_H +#define __CONFIG_RK3528_COMMON_H + +#define CFG_CPUID_OFFSET 0xa + +#include "rockchip-common.h" + +#define CFG_IRAM_BASE 0xfe480000 + +#define CFG_SYS_SDRAM_BASE 0 +#define SDRAM_MAX_SIZE 0xfc000000 + +#ifndef ROCKCHIP_DEVICE_SETTINGS +#define ROCKCHIP_DEVICE_SETTINGS +#endif + +#define ENV_MEM_LAYOUT_SETTINGS \ + "scriptaddr=0x00c00000\0" \ + "script_offset_f=0xffe000\0" \ + "script_size_f=0x2000\0" \ + "pxefile_addr_r=0x00e00000\0" \ + "kernel_addr_r=0x02000000\0" \ + "kernel_comp_addr_r=0x0a000000\0" \ + "fdt_addr_r=0x12000000\0" \ + "fdtoverlay_addr_r=0x12100000\0" \ + "ramdisk_addr_r=0x12180000\0" \ + "kernel_comp_size=0x8000000\0" + +#define CFG_EXTRA_ENV_SETTINGS \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + ENV_MEM_LAYOUT_SETTINGS \ + ROCKCHIP_DEVICE_SETTINGS \ + "boot_targets=" BOOT_TARGETS "\0" + +#endif /* __CONFIG_RK3528_COMMON_H */ diff --git a/include/configs/rk3568_common.h b/include/configs/rk3568_common.h index 09b7b71c6af..b2a35db0b94 100644 --- a/include/configs/rk3568_common.h +++ b/include/configs/rk3568_common.h @@ -15,6 +15,10 @@ #define CFG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xf0000000 +#ifndef ROCKCHIP_DEVICE_SETTINGS +#define ROCKCHIP_DEVICE_SETTINGS +#endif + #define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x00c00000\0" \ "script_offset_f=0xffe000\0" \ @@ -29,7 +33,6 @@ #define CFG_EXTRA_ENV_SETTINGS \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "partitions=" PARTS_DEFAULT \ ENV_MEM_LAYOUT_SETTINGS \ ROCKCHIP_DEVICE_SETTINGS \ "boot_targets=" BOOT_TARGETS "\0" diff --git a/include/configs/rk3576_common.h b/include/configs/rk3576_common.h new file mode 100644 index 00000000000..14d1d863609 --- /dev/null +++ b/include/configs/rk3576_common.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2024 Rockchip Electronics Co., Ltd + */ + +#ifndef __CONFIG_RK3576_COMMON_H +#define __CONFIG_RK3576_COMMON_H + +#define CFG_CPUID_OFFSET 0xa + +#include "rockchip-common.h" + +#define CFG_IRAM_BASE 0x3ff80000 + +#define CFG_SYS_SDRAM_BASE 0x40000000 +/* Used by board_get_usable_ram_top(), space below the 4G address boundary */ +#define SDRAM_MAX_SIZE (SZ_4G - CFG_SYS_SDRAM_BASE) + +#ifndef ROCKCHIP_DEVICE_SETTINGS +#define ROCKCHIP_DEVICE_SETTINGS +#endif + +#define ENV_MEM_LAYOUT_SETTINGS \ + "scriptaddr=0x40c00000\0" \ + "script_offset_f=0xffe000\0" \ + "script_size_f=0x2000\0" \ + "pxefile_addr_r=0x40e00000\0" \ + "kernel_addr_r=0x42000000\0" \ + "kernel_comp_addr_r=0x4a000000\0" \ + "fdt_addr_r=0x52000000\0" \ + "fdtoverlay_addr_r=0x52100000\0" \ + "ramdisk_addr_r=0x52180000\0" \ + "kernel_comp_size=0x8000000\0" + +#define CFG_EXTRA_ENV_SETTINGS \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + ENV_MEM_LAYOUT_SETTINGS \ + ROCKCHIP_DEVICE_SETTINGS \ + "boot_targets=" BOOT_TARGETS "\0" + +#endif /* __CONFIG_RK3576_COMMON_H */ diff --git a/include/configs/rk3588_common.h b/include/configs/rk3588_common.h index e6654c275ac..2f0d40deb64 100644 --- a/include/configs/rk3588_common.h +++ b/include/configs/rk3588_common.h @@ -14,6 +14,10 @@ #define CFG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xf0000000 +#ifndef ROCKCHIP_DEVICE_SETTINGS +#define ROCKCHIP_DEVICE_SETTINGS +#endif + #define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x00c00000\0" \ "script_offset_f=0xffe000\0" \ @@ -28,7 +32,6 @@ #define CFG_EXTRA_ENV_SETTINGS \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "partitions=" PARTS_DEFAULT \ ENV_MEM_LAYOUT_SETTINGS \ ROCKCHIP_DEVICE_SETTINGS \ "boot_targets=" BOOT_TARGETS "\0" diff --git a/include/configs/roc-pc-rk3576.h b/include/configs/roc-pc-rk3576.h new file mode 100644 index 00000000000..77c95f0c560 --- /dev/null +++ b/include/configs/roc-pc-rk3576.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + */ + +#ifndef __ROC_PC_RK3576_H +#define __ROC_PC_RK3576_H + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#include <configs/rk3576_common.h> + +#endif diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h deleted file mode 100644 index 8e98620422d..00000000000 --- a/include/configs/seaboard.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation <www.nvidia.com> - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <linux/sizes.h> - -#include "tegra20-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "NVIDIA Seaboard" - -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE - -/* Environment in eMMC, at the end of 2nd "boot sector" */ - -/* NAND support */ - -/* Max number of NAND devices */ - -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h index 00ec9efba57..e6f8dee668d 100644 --- a/include/configs/stm32f746-disco.h +++ b/include/configs/stm32f746-disco.h @@ -30,7 +30,7 @@ #include <config_distro_bootcmd.h> #define CFG_EXTRA_ENV_SETTINGS \ "kernel_addr_r=0xC0008000\0" \ - "fdtfile="CONFIG_DEFAULT_DEVICE_TREE".dtb\0" \ + "fdtfile="CONFIG_DEFAULT_FDT_FILE".dtb\0" \ "fdt_addr_r=0xC0408000\0" \ "scriptaddr=0xC0418000\0" \ "pxefile_addr_r=0xC0428000\0" \ diff --git a/include/configs/stm32mp25_common.h b/include/configs/stm32mp25_common.h index ec980eea856..b42316fd8ac 100644 --- a/include/configs/stm32mp25_common.h +++ b/include/configs/stm32mp25_common.h @@ -21,4 +21,106 @@ */ #define CFG_SYS_BOOTMAPSZ SZ_256M +/*****************************************************************************/ +#ifdef CONFIG_DISTRO_DEFAULTS +/*****************************************************************************/ + +#ifdef CONFIG_NET +#define BOOT_TARGET_PXE(func) func(PXE, pxe, na) +#else +#define BOOT_TARGET_PXE(func) +#endif + +#ifdef CONFIG_CMD_MMC +#define BOOT_TARGET_MMC0(func) func(MMC, mmc, 0) +#define BOOT_TARGET_MMC1(func) func(MMC, mmc, 1) +#define BOOT_TARGET_MMC2(func) func(MMC, mmc, 2) +#else +#define BOOT_TARGET_MMC0(func) +#define BOOT_TARGET_MMC1(func) +#define BOOT_TARGET_MMC2(func) +#endif + +#ifdef CONFIG_CMD_UBIFS +#define BOOT_TARGET_UBIFS(func) func(UBIFS, ubifs, 0, UBI, boot) +#else +#define BOOT_TARGET_UBIFS(func) +#endif + +#ifdef CONFIG_CMD_USB +#define BOOT_TARGET_USB(func) func(USB, usb, 0) +#else +#define BOOT_TARGET_USB(func) +#endif + +#define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_MMC1(func) \ + BOOT_TARGET_UBIFS(func) \ + BOOT_TARGET_MMC0(func) \ + BOOT_TARGET_MMC2(func) \ + BOOT_TARGET_USB(func) \ + BOOT_TARGET_PXE(func) + +/* + * default bootcmd for stm32mp25: + * for serial/usb: execute the stm32prog command + * for mmc boot (eMMC, SD card), distro boot on the same mmc device + * for NAND or SPI-NAND boot, distro boot with UBIFS on UBI partition + * for other boot, use the default distro order in ${boot_targets} + */ +#define STM32MP_BOOTCMD "bootcmd_stm32mp=" \ + "echo \"Boot over ${boot_device}${boot_instance}!\";" \ + "if test ${boot_device} = serial || test ${boot_device} = usb;" \ + "then stm32prog ${boot_device} ${boot_instance}; " \ + "else " \ + "run env_check;" \ + "if test ${boot_device} = mmc;" \ + "then env set boot_targets \"mmc${boot_instance}\"; fi;" \ + "if test ${boot_device} = nand ||" \ + " test ${boot_device} = spi-nand ;" \ + "then env set boot_targets ubifs0; fi;" \ + "run distro_bootcmd;" \ + "fi;\0" + +#ifndef STM32MP_BOARD_EXTRA_ENV +#define STM32MP_BOARD_EXTRA_ENV +#endif + +#define STM32MP_EXTRA \ + "env_check=if env info -p -d -q; then env save; fi\0" \ + "boot_net_usb_start=true\0" +/* + * memory layout for 96MB uncompressed/compressed kernel, + * 1M fdt, 1M script, 1M pxe and 1M for overlay + * and the ramdisk at the end. + */ +#define __KERNEL_COMP_ADDR_R __stringify(0x84000000) +#define __KERNEL_COMP_SIZE_R __stringify(0x04000000) +#define __KERNEL_ADDR_R __stringify(0x8a000000) +#define __FDT_ADDR_R __stringify(0x90000000) +#define __SCRIPT_ADDR_R __stringify(0x90100000) +#define __PXEFILE_ADDR_R __stringify(0x90200000) +#define __FDTOVERLAY_ADDR_R __stringify(0x90300000) +#define __RAMDISK_ADDR_R __stringify(0x90400000) + +#define STM32MP_MEM_LAYOUT \ + "kernel_addr_r=" __KERNEL_ADDR_R "\0" \ + "fdt_addr_r=" __FDT_ADDR_R "\0" \ + "scriptaddr=" __SCRIPT_ADDR_R "\0" \ + "pxefile_addr_r=" __PXEFILE_ADDR_R "\0" \ + "fdtoverlay_addr_r=" __FDTOVERLAY_ADDR_R "\0" \ + "ramdisk_addr_r=" __RAMDISK_ADDR_R "\0" \ + "kernel_comp_addr_r=" __KERNEL_COMP_ADDR_R "\0" \ + "kernel_comp_size=" __KERNEL_COMP_SIZE_R "\0" + +#include <config_distro_bootcmd.h> +#define CFG_EXTRA_ENV_SETTINGS \ + STM32MP_MEM_LAYOUT \ + STM32MP_BOOTCMD \ + BOOTENV \ + STM32MP_EXTRA \ + STM32MP_BOARD_EXTRA_ENV + +#endif + #endif /* __CONFIG_STM32MP25_COMMMON_H */ diff --git a/include/configs/stm32mp25_st_common.h b/include/configs/stm32mp25_st_common.h new file mode 100644 index 00000000000..ab5a4a91644 --- /dev/null +++ b/include/configs/stm32mp25_st_common.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause */ +/* + * Copyright (C) 2022, STMicroelectronics - All Rights Reserved + * + * Configuration settings for the STMicroelectonics STM32MP25x boards + */ + +#ifndef __CONFIG_STM32MP25_ST_COMMON_H__ +#define __CONFIG_STM32MP25_ST_COMMON_H__ + +#define STM32MP_BOARD_EXTRA_ENV \ + "usb_pgood_delay=2000\0" \ + "console=ttySTM0\0" + +#include <configs/stm32mp25_common.h> + +#ifdef CFG_EXTRA_ENV_SETTINGS +/* + * default bootcmd for stm32mp25 STMicroelectronics boards: + * for serial/usb: execute the stm32prog command + * for mmc boot (eMMC, SD card), distro boot on the same mmc device + * for nand or spi-nand boot, distro boot with ubifs on UBI partition or + * sdcard + * for nor boot, distro boot on SD card = mmc0 ONLY ! + */ +#define ST_STM32MP25_BOOTCMD "bootcmd_stm32mp=" \ + "echo \"Boot over ${boot_device}${boot_instance}!\";" \ + "if test ${boot_device} = serial || test ${boot_device} = usb;" \ + "then stm32prog ${boot_device} ${boot_instance}; " \ + "else " \ + "run env_check;" \ + "if test ${boot_device} = mmc;" \ + "then env set boot_targets \"mmc${boot_instance}\"; fi;" \ + "if test ${boot_device} = nand ||" \ + " test ${boot_device} = spi-nand ;" \ + "then env set boot_targets ubifs0 mmc0; fi;" \ + "if test ${boot_device} = nor;" \ + "then env set boot_targets mmc0; fi;" \ + "run distro_bootcmd;" \ + "fi;\0" + +#undef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ + STM32MP_MEM_LAYOUT \ + ST_STM32MP25_BOOTCMD \ + BOOTENV \ + STM32MP_EXTRA \ + STM32MP_BOARD_EXTRA_ENV + +#endif +#endif diff --git a/include/configs/surface-rt.h b/include/configs/surface-rt.h deleted file mode 100644 index 1f0837e179b..00000000000 --- a/include/configs/surface-rt.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. - * - * Copyright (c) 2021, Open Surface RT - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "tegra30-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "Microsoft Surface RT" - -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE - -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/tec-ng.h b/include/configs/tec-ng.h deleted file mode 100644 index 5e49abb49fa..00000000000 --- a/include/configs/tec-ng.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013 - * Avionic Design GmbH <www.avionic-design.de> - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "tegra30-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "Avionic Design Tamonten™ NG Evaluation Carrier" - -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE - -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/tec.h b/include/configs/tec.h deleted file mode 100644 index 05dd7c96f61..00000000000 --- a/include/configs/tec.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation <www.nvidia.com> - * (C) Copyright 2011-2012 - * Avionic Design GmbH <www.avionic-design.de> - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "tegra20-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "Avionic Design Tamonten Evaluation Carrier" - -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE - -/* NAND support */ - -/* Environment in NAND, aligned to start of last sector */ - -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/tegra.h b/include/configs/tegra.h new file mode 100644 index 00000000000..77bc38930d2 --- /dev/null +++ b/include/configs/tegra.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation <www.nvidia.com> + * + * (C) Copyright 2025 + * Svyatoslav Ryhel <clamor95@gmail.com> + * + * Generic device header which can be used with SYS_CONFIG_NAME + * for any Tegra device (T20, T30, T114, T124, T186 or T210). + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <linux/sizes.h> + +#ifdef CONFIG_TEGRA20 +#include "tegra20-common.h" +#elif CONFIG_TEGRA30 +#include "tegra30-common.h" +#elif CONFIG_TEGRA114 +#include "tegra114-common.h" +#elif CONFIG_TEGRA124 +#include "tegra124-common.h" +#elif CONFIG_TEGRA186 +#include "tegra186-common.h" +#elif CONFIG_TEGRA210 +#include "tegra210-common.h" +#endif + +#include "tegra-common-post.h" + +#endif /* __CONFIG_H */ diff --git a/include/configs/tegratab.h b/include/configs/tegratab.h new file mode 100644 index 00000000000..afab01ec09c --- /dev/null +++ b/include/configs/tegratab.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + * + * Copyright (c) 2023, Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "tegra114-common.h" + +#ifdef CONFIG_TEGRA_SUPPORT_NON_SECURE + #define CFG_PRAM 0x21c00 /* 135 MB */ +#endif + +#include "tegra-common-post.h" + +#endif /* __CONFIG_H */ diff --git a/include/configs/topic_miami.h b/include/configs/topic_miami.h index 06276175455..5530d36339c 100644 --- a/include/configs/topic_miami.h +++ b/include/configs/topic_miami.h @@ -9,75 +9,67 @@ #ifndef __CONFIG_TOPIC_MIAMI_H #define __CONFIG_TOPIC_MIAMI_H -/* Speed up boot time by ignoring the environment which we never used */ +#ifndef CONFIG_XPL_BUILD -#include "zynq-common.h" +#ifdef CONFIG_CMD_MMC +#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) +#else +#define BOOT_TARGET_DEVICES_MMC(func) +#endif -/* Fixup settings */ +#ifdef CONFIG_CMD_USB +#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0) +#else +#define BOOT_TARGET_DEVICES_USB(func) +#endif -/* Setup proper boot sequences for Miami boards */ +#if defined(CONFIG_ZYNQ_QSPI) +# define BOOT_TARGET_DEVICES_QSPI(func) func(QSPI, qspi, na) +#else +# define BOOT_TARGET_DEVICES_QSPI(func) +#endif -#if defined(CONFIG_USB_HOST) -# define EXTRA_ENV_USB \ - "usbreset=i2c dev 1 && i2c mw 41 1 ff && i2c mw 41 3 fe && "\ - "i2c mw 41 1 fe && i2c mw 41 1 ff\0" \ - "usbboot=run usbreset && if usb start; then " \ - "echo Booting from USB... && " \ - "if load usb 0 0x1900000 ${bootscript}; then "\ - "source 0x1900000; fi; " \ - "load usb 0 ${kernel_addr} ${kernel_image} && " \ - "load usb 0 ${devicetree_addr} ${devicetree_image} && " \ - "load usb 0 ${ramdisk_load_address} ${ramdisk_image} && " \ - "bootm ${kernel_addr} ${ramdisk_load_address} "\ - "${devicetree_addr}; " \ - "fi\0" - /* Note that addresses here should match the addresses in the env */ -# define DFU_ALT_INFO \ - "dfu_alt_info=" \ - "uImage ram 0x2080000 0x500000;" \ - "devicetree.dtb ram 0x2000000 0x20000;" \ - "uramdisk.image.gz ram 0x4000000 0x10000000\0" \ - "dfu_ram=run usbreset && dfu 0 ram 0\0" \ - "thor_ram=run usbreset && thordown 0 ram 0\0" +#ifdef CONFIG_CMD_UBIFS +# define BOOT_TARGET_DEVICES_UBIFS(func) func(UBIFS, ubifs, 0, qspi-rootfs, qspi-rootfs) #else -# define EXTRA_ENV_USB +# define BOOT_TARGET_DEVICES_UBIFS(func) #endif -#undef CFG_EXTRA_ENV_SETTINGS +#define BOOTENV_DEV_QSPI(devtypeu, devtypel, instance) \ + "bootcmd_qspi=sf probe && " \ + "sf read ${scriptaddr} ${script_offset_f} ${script_size_f} && " \ + "echo QSPI: Trying to boot script at ${scriptaddr} && " \ + "source ${scriptaddr}; echo QSPI: SCRIPT FAILED: continuing...;\0" + +#define BOOTENV_DEV_NAME_QSPI(devtypeu, devtypel, instance) \ + "qspi " + +#define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_DEVICES_MMC(func) \ + BOOT_TARGET_DEVICES_UBIFS(func) \ + BOOT_TARGET_DEVICES_QSPI(func) + +#include <config_distro_bootcmd.h> + +#endif /* CONFIG_XPL_BUILD */ + +/* Default environment */ +#ifndef CFG_EXTRA_ENV_SETTINGS #define CFG_EXTRA_ENV_SETTINGS \ - "kernel_image=uImage\0" \ - "kernel_addr=0x2080000\0" \ - "ramdisk_image=uramdisk.image.gz\0" \ - "ramdisk_load_address=0x4000000\0" \ - "devicetree_image=devicetree.dtb\0" \ - "devicetree_addr=0x2000000\0" \ - "bitstream_image=fpga.bin\0" \ - "bootscript=autorun.scr\0" \ - "loadbit_addr=0x100000\0" \ - "loadbootenv_addr=0x2000000\0" \ - "kernel_size=0x440000\0" \ - "devicetree_size=0x10000\0" \ - "boot_size=0xF00000\0" \ - "fdt_high=0x20000000\0" \ - "initrd_high=0x20000000\0" \ - "mmc_loadbit=echo Loading bitstream from SD/MMC/eMMC to RAM.. && " \ - "mmcinfo && " \ - "load mmc 0 ${loadbit_addr} ${bitstream_image} && " \ - "fpga load 0 ${loadbit_addr} ${filesize}\0" \ - "qspiboot=echo Booting from QSPI flash... && " \ - "sf probe && " \ - "sf read ${devicetree_addr} 0xA0000 ${devicetree_size} && " \ - "sf read ${kernel_addr} 0xC0000 ${kernel_size} && " \ - "bootm ${kernel_addr} - ${devicetree_addr}\0" \ - "sdboot=if mmcinfo; then " \ - "setenv bootargs console=ttyPS0,115200 " \ - "root=/dev/mmcblk0p2 rw rootfstype=ext4 " \ - "rootwait quiet ; " \ - "load mmc 0 ${kernel_addr} ${kernel_image}&& " \ - "load mmc 0 ${devicetree_addr} ${devicetree_image}&& " \ - "bootm ${kernel_addr} - ${devicetree_addr}; " \ - "fi\0" \ - EXTRA_ENV_USB \ - DFU_ALT_INFO + "scriptaddr=0x3000000\0" \ + "script_offset_f=0xf0000\0" \ + "script_size_f=0x10000\0" \ + "fdt_addr_r=0x1f00000\0" \ + "pxefile_addr_r=0x2000000\0" \ + "kernel_addr_r=0x2000000\0" \ + "ramdisk_addr_r=0x3100000\0" \ + BOOTENV +#endif + +#include "zynq-common.h" + +/* Detect RAM size */ +#define CFG_SYS_SDRAM_BASE 0 +#define CFG_SYS_SDRAM_SIZE 0x40000000 #endif /* __CONFIG_TOPIC_MIAMI_H */ diff --git a/include/configs/toradex-smarc-imx8mp.h b/include/configs/toradex-smarc-imx8mp.h new file mode 100644 index 00000000000..3d5fb854fc8 --- /dev/null +++ b/include/configs/toradex-smarc-imx8mp.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* Copyright (C) 2024 Toradex */ + +#ifndef __TORADEX_SMARC_IMX8MP_H +#define __TORADEX_SMARC_IMX8MP_H + +#include <asm/arch/imx-regs.h> +#include <linux/sizes.h> + +#define CFG_SYS_UBOOT_BASE \ + (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + +#ifdef CONFIG_SPL_BUILD +/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ +#define CFG_MALLOC_F_ADDR 0x184000 +#endif /* CONFIG_SPL_BUILD */ + +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE SZ_512K + +/* i.MX 8M Plus supports max. 8GB memory in two albeit consecutive banks */ +#define CFG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_SIZE (SZ_2G + SZ_1G) +#define PHYS_SDRAM_2 0x100000000 +#define PHYS_SDRAM_2_SIZE (SZ_4G + SZ_1G) + +#endif /* __TORADEX_SMARC_IMX8MP_H */ diff --git a/include/configs/toybrick_rk3588.h b/include/configs/toybrick_rk3588.h index faa2e6c19c3..00565089676 100644 --- a/include/configs/toybrick_rk3588.h +++ b/include/configs/toybrick_rk3588.h @@ -6,10 +6,10 @@ #ifndef __TOYBRICK_RK3588_H #define __TOYBRICK_RK3588_H -#include <configs/rk3588_common.h> - #define ROCKCHIP_DEVICE_SETTINGS \ "stdout=serial,vidconsole\0" \ "stderr=serial,vidconsole\0" +#include <configs/rk3588_common.h> + #endif diff --git a/include/configs/transformer-t114.h b/include/configs/transformer-t114.h new file mode 100644 index 00000000000..2fbf3417691 --- /dev/null +++ b/include/configs/transformer-t114.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + * + * Copyright (c) 2023, Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "tegra114-common.h" + +#ifdef CONFIG_TEGRA_SUPPORT_NON_SECURE + #define CFG_PRAM 0x20000 /* 128 MB */ +#endif + +#include "tegra-common-post.h" + +#endif /* __CONFIG_H */ diff --git a/include/configs/transformer-t20.h b/include/configs/transformer-t20.h deleted file mode 100644 index 6a3d9b24036..00000000000 --- a/include/configs/transformer-t20.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation <www.nvidia.com> - * - * (C) Copyright 2022 - * Svyatoslav Ryhel <clamor95@gmail.com> - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "tegra20-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "ASUS Transformer" - -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE - -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/transformer-t30.h b/include/configs/transformer-t30.h deleted file mode 100644 index 792b958a302..00000000000 --- a/include/configs/transformer-t30.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * (C) Copyright 2010,2012 - * NVIDIA Corporation <www.nvidia.com> - * - * (C) Copyright 2022 - * Svyatoslav Ryhel <clamor95@gmail.com> - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "tegra30-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "ASUS Transformer" - -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE - -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h deleted file mode 100644 index 7d1ff2afd14..00000000000 --- a/include/configs/trimslice.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010-2012 - * NVIDIA Corporation <www.nvidia.com> - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <linux/sizes.h> -#include "tegra20-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "Compulab Trimslice" - -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE - -/* SPI */ - -/* Environment in SPI */ -/* 1MiB flash, environment located as high as possible */ - -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/venice2.h b/include/configs/venice2.h deleted file mode 100644 index 353b5ea67c1..00000000000 --- a/include/configs/venice2.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013-2014 - * NVIDIA Corporation <www.nvidia.com> - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <linux/sizes.h> - -#include "tegra124-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "NVIDIA Venice2" - -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE - -/* Environment in eMMC, at the end of 2nd "boot sector" */ - -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/ventana.h b/include/configs/ventana.h deleted file mode 100644 index 1d9c60ca7c6..00000000000 --- a/include/configs/ventana.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation <www.nvidia.com> - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <linux/sizes.h> -#include "tegra20-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "NVIDIA Ventana" - -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE - -/* Environment in eMMC, at the end of 2nd "boot sector" */ - -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/x3-t30.h b/include/configs/x3-t30.h deleted file mode 100644 index c152af9b7e2..00000000000 --- a/include/configs/x3-t30.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * (C) Copyright 2010,2012 - * NVIDIA Corporation <www.nvidia.com> - * - * (C) Copyright 2022 - * Svyatoslav Ryhel <clamor95@gmail.com> - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "tegra30-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "LG X3 Board" - -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE - -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 93ae5891a07..94273d0deb9 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -46,7 +46,10 @@ #ifdef CONFIG_XPL_BUILD #define BOOTENV -#else +#endif + +/* Only use this section if no BOOTENV has been configured yet */ +#ifndef BOOTENV #ifdef CONFIG_CMD_MMC #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1) @@ -167,7 +170,8 @@ BOOT_TARGET_DEVICES_DHCP(func) #include <config_distro_bootcmd.h> -#endif /* CONFIG_XPL_BUILD */ + +#endif /* BOOTENV */ /* Default environment */ #ifndef CFG_EXTRA_ENV_SETTINGS diff --git a/include/dm/uclass.h b/include/dm/uclass.h index c2793040923..8fdd7272511 100644 --- a/include/dm/uclass.h +++ b/include/dm/uclass.h @@ -334,6 +334,30 @@ int uclass_get_device_by_driver(enum uclass_id id, const struct driver *drv, struct udevice **devp); /** + * uclass_get_device_by_endpoint() - Get a uclass device for a remote endpoint + * + * This searches through the parents of the specified remote endpoint + * for the first device matching the uclass. Said otherwise, this helper + * goes through the graph (endpoint) representation and searches for + * matching devices. Endpoints can be subnodes of the "port" node or + * subnodes of ports identified with a reg property, themselves in a + * "ports" container. + * + * The device is probed to activate it ready for use. + * + * @class_id: uclass ID to look up + * @dev: Device to start from + * @port_idx: Index of the port to follow, -1 if there is a single 'port' + * node without reg. + * @ep_idx: Index of the endpoint to follow, -1 if there is a single 'endpoint' + * node without reg. + * @target: Returns pointer to the first device matching the expected uclass. + * Return: 0 if OK, -ve on error + */ +int uclass_get_device_by_endpoint(enum uclass_id class_id, struct udevice *dev, + int port_idx, int ep_idx, struct udevice **target); + +/** * uclass_first_device() - Get the first device in a uclass * * The device returned is probed if necessary, and ready for use diff --git a/include/dt-bindings/clock/stih407-clks.h b/include/dt-bindings/clock/stih407-clks.h deleted file mode 100644 index 082edd9badf..00000000000 --- a/include/dt-bindings/clock/stih407-clks.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - * This header provides constants clk index STMicroelectronics - * STiH407 SoC. - */ -#ifndef _DT_BINDINGS_CLK_STIH407 -#define _DT_BINDINGS_CLK_STIH407 - -/* CLOCKGEN A0 */ -#define CLK_IC_LMI0 0 -#define CLK_IC_LMI1 1 - -/* CLOCKGEN C0 */ -#define CLK_ICN_GPU 0 -#define CLK_FDMA 1 -#define CLK_NAND 2 -#define CLK_HVA 3 -#define CLK_PROC_STFE 4 -#define CLK_PROC_TP 5 -#define CLK_RX_ICN_DMU 6 -#define CLK_RX_ICN_DISP_0 6 -#define CLK_RX_ICN_DISP_1 6 -#define CLK_RX_ICN_HVA 7 -#define CLK_RX_ICN_TS 7 -#define CLK_ICN_CPU 8 -#define CLK_TX_ICN_DMU 9 -#define CLK_TX_ICN_HVA 9 -#define CLK_TX_ICN_TS 9 -#define CLK_ICN_COMPO 9 -#define CLK_MMC_0 10 -#define CLK_MMC_1 11 -#define CLK_JPEGDEC 12 -#define CLK_ICN_REG 13 -#define CLK_TRACE_A9 13 -#define CLK_PTI_STM 13 -#define CLK_EXT2F_A9 13 -#define CLK_IC_BDISP_0 14 -#define CLK_IC_BDISP_1 15 -#define CLK_PP_DMU 16 -#define CLK_VID_DMU 17 -#define CLK_DSS_LPC 18 -#define CLK_ST231_AUD_0 19 -#define CLK_ST231_GP_0 19 -#define CLK_ST231_GP_1 20 -#define CLK_ST231_DMU 21 -#define CLK_ICN_LMI 22 -#define CLK_TX_ICN_DISP_0 23 -#define CLK_TX_ICN_DISP_1 23 -#define CLK_ICN_SBC 24 -#define CLK_STFE_FRC2 25 -#define CLK_ETH_PHY 26 -#define CLK_ETH_REF_PHYCLK 27 -#define CLK_FLASH_PROMIP 28 -#define CLK_MAIN_DISP 29 -#define CLK_AUX_DISP 30 -#define CLK_COMPO_DVP 31 - -/* CLOCKGEN D0 */ -#define CLK_PCM_0 0 -#define CLK_PCM_1 1 -#define CLK_PCM_2 2 -#define CLK_SPDIFF 3 - -/* CLOCKGEN D2 */ -#define CLK_PIX_MAIN_DISP 0 -#define CLK_PIX_PIP 1 -#define CLK_PIX_GDP1 2 -#define CLK_PIX_GDP2 3 -#define CLK_PIX_GDP3 4 -#define CLK_PIX_GDP4 5 -#define CLK_PIX_AUX_DISP 6 -#define CLK_DENC 7 -#define CLK_PIX_HDDAC 8 -#define CLK_HDDAC 9 -#define CLK_SDDAC 10 -#define CLK_PIX_DVO 11 -#define CLK_DVO 12 -#define CLK_PIX_HDMI 13 -#define CLK_TMDS_HDMI 14 -#define CLK_REF_HDMIPHY 15 - -/* CLOCKGEN D3 */ -#define CLK_STFE_FRC1 0 -#define CLK_TSOUT_0 1 -#define CLK_TSOUT_1 2 -#define CLK_MCHI 3 -#define CLK_VSENS_COMPO 4 -#define CLK_FRC1_REMOTE 5 -#define CLK_LPC_0 6 -#define CLK_LPC_1 7 -#endif diff --git a/include/dt-bindings/clock/stih410-clks.h b/include/dt-bindings/clock/stih410-clks.h deleted file mode 100644 index 2097a4bbe15..00000000000 --- a/include/dt-bindings/clock/stih410-clks.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This header provides constants clk index STMicroelectronics - * STiH410 SoC. - */ -#ifndef _DT_BINDINGS_CLK_STIH410 -#define _DT_BINDINGS_CLK_STIH410 - -#include "stih407-clks.h" - -/* STiH410 introduces new clock outputs compared to STiH407 */ - -/* CLOCKGEN C0 */ -#define CLK_TX_ICN_HADES 32 -#define CLK_RX_ICN_HADES 33 -#define CLK_ICN_REG_16 34 -#define CLK_PP_HADES 35 -#define CLK_CLUST_HADES 36 -#define CLK_HWPE_HADES 37 -#define CLK_FC_HADES 38 - -/* CLOCKGEN D0 */ -#define CLK_PCMR10_MASTER 4 -#define CLK_USB2_PHY 5 - -#endif diff --git a/include/dt-bindings/mfd/st-lpc.h b/include/dt-bindings/mfd/st-lpc.h deleted file mode 100644 index d05894afa7e..00000000000 --- a/include/dt-bindings/mfd/st-lpc.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * This header provides shared DT/Driver defines for ST's LPC device - * - * Copyright (C) 2014 STMicroelectronics -- All Rights Reserved - * - * Author: Lee Jones <lee.jones@linaro.org> for STMicroelectronics - */ - -#ifndef __DT_BINDINGS_ST_LPC_H__ -#define __DT_BINDINGS_ST_LPC_H__ - -#define ST_LPC_MODE_RTC 0 -#define ST_LPC_MODE_WDT 1 -#define ST_LPC_MODE_CLKSRC 2 - -#endif /* __DT_BINDINGS_ST_LPC_H__ */ diff --git a/include/dt-bindings/reset/stih407-resets.h b/include/dt-bindings/reset/stih407-resets.h deleted file mode 100644 index 4ab3a1c9495..00000000000 --- a/include/dt-bindings/reset/stih407-resets.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * This header provides constants for the reset controller - * based peripheral powerdown requests on the STMicroelectronics - * STiH407 SoC. - */ -#ifndef _DT_BINDINGS_RESET_CONTROLLER_STIH407 -#define _DT_BINDINGS_RESET_CONTROLLER_STIH407 - -/* Powerdown requests control 0 */ -#define STIH407_EMISS_POWERDOWN 0 -#define STIH407_NAND_POWERDOWN 1 - -/* Synp GMAC PowerDown */ -#define STIH407_ETH1_POWERDOWN 2 - -/* Powerdown requests control 1 */ -#define STIH407_USB3_POWERDOWN 3 -#define STIH407_USB2_PORT1_POWERDOWN 4 -#define STIH407_USB2_PORT0_POWERDOWN 5 -#define STIH407_PCIE1_POWERDOWN 6 -#define STIH407_PCIE0_POWERDOWN 7 -#define STIH407_SATA1_POWERDOWN 8 -#define STIH407_SATA0_POWERDOWN 9 - -/* Reset defines */ -#define STIH407_ETH1_SOFTRESET 0 -#define STIH407_MMC1_SOFTRESET 1 -#define STIH407_PICOPHY_SOFTRESET 2 -#define STIH407_IRB_SOFTRESET 3 -#define STIH407_PCIE0_SOFTRESET 4 -#define STIH407_PCIE1_SOFTRESET 5 -#define STIH407_SATA0_SOFTRESET 6 -#define STIH407_SATA1_SOFTRESET 7 -#define STIH407_MIPHY0_SOFTRESET 8 -#define STIH407_MIPHY1_SOFTRESET 9 -#define STIH407_MIPHY2_SOFTRESET 10 -#define STIH407_SATA0_PWR_SOFTRESET 11 -#define STIH407_SATA1_PWR_SOFTRESET 12 -#define STIH407_DELTA_SOFTRESET 13 -#define STIH407_BLITTER_SOFTRESET 14 -#define STIH407_HDTVOUT_SOFTRESET 15 -#define STIH407_HDQVDP_SOFTRESET 16 -#define STIH407_VDP_AUX_SOFTRESET 17 -#define STIH407_COMPO_SOFTRESET 18 -#define STIH407_HDMI_TX_PHY_SOFTRESET 19 -#define STIH407_JPEG_DEC_SOFTRESET 20 -#define STIH407_VP8_DEC_SOFTRESET 21 -#define STIH407_GPU_SOFTRESET 22 -#define STIH407_HVA_SOFTRESET 23 -#define STIH407_ERAM_HVA_SOFTRESET 24 -#define STIH407_LPM_SOFTRESET 25 -#define STIH407_KEYSCAN_SOFTRESET 26 -#define STIH407_USB2_PORT0_SOFTRESET 27 -#define STIH407_USB2_PORT1_SOFTRESET 28 -#define STIH407_ST231_AUD_SOFTRESET 29 -#define STIH407_ST231_DMU_SOFTRESET 30 -#define STIH407_ST231_GP0_SOFTRESET 31 -#define STIH407_ST231_GP1_SOFTRESET 32 - -/* Picophy reset defines */ -#define STIH407_PICOPHY0_RESET 0 -#define STIH407_PICOPHY1_RESET 1 -#define STIH407_PICOPHY2_RESET 2 - -#endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH407 */ diff --git a/include/efi_loader.h b/include/efi_loader.h index 5f769786786..84e8cfe320e 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -597,10 +597,12 @@ efi_status_t efi_env_set_load_options(efi_handle_t handle, const char *env_var, void *efi_get_configuration_table(const efi_guid_t *guid); /* Install device tree */ efi_status_t efi_install_fdt(void *fdt); +/* Install initrd */ +efi_status_t efi_install_initrd(void *initrd, size_t initd_sz); /* Execute loaded UEFI image */ efi_status_t do_bootefi_exec(efi_handle_t handle, void *load_options); /* Run loaded UEFI image with given fdt */ -efi_status_t efi_binary_run(void *image, size_t size, void *fdt); +efi_status_t efi_binary_run(void *image, size_t size, void *fdt, void *initrd, size_t initrd_sz); /** * efi_bootflow_run() - Run a bootflow containing an EFI application @@ -667,7 +669,7 @@ efi_status_t efi_http_register(const efi_handle_t handle, struct efi_service_binding_protocol *http_service_binding); /* Called by bootefi to make the watchdog available */ efi_status_t efi_watchdog_register(void); -efi_status_t efi_initrd_register(void); +efi_status_t efi_initrd_register(struct efi_device_path *dp_initrd); efi_status_t efi_initrd_deregister(void); /* Called by bootefi to make SMBIOS tables available */ /** diff --git a/include/exfat.h b/include/exfat.h index 7e43beeb348..75fce5b6566 100644 --- a/include/exfat.h +++ b/include/exfat.h @@ -20,5 +20,6 @@ int exfat_fs_unlink(const char *filename); int exfat_fs_mkdir(const char *dirname); int exfat_fs_write(const char *filename, void *buf, loff_t offset, loff_t len, loff_t *actwrite); +int exfat_fs_rename(const char *old_path, const char *new_path); #endif /* _EXFAT_H */ diff --git a/include/initcall.h b/include/initcall.h index 62d3bb67f08..220a55ad84d 100644 --- a/include/initcall.h +++ b/include/initcall.h @@ -8,31 +8,34 @@ #include <asm/types.h> #include <event.h> +#include <hang.h> _Static_assert(EVT_COUNT < 256, "Can only support 256 event types with 8 bits"); -/** - * init_fnc_t - Init function - * - * Return: 0 if OK -ve on error - */ -typedef int (*init_fnc_t)(void); - -/* Top bit indicates that the initcall is an event */ -#define INITCALL_IS_EVENT GENMASK(BITS_PER_LONG - 1, 8) -#define INITCALL_EVENT_TYPE GENMASK(7, 0) - -#define INITCALL_EVENT(_type) (void *)((_type) | INITCALL_IS_EVENT) - -/** - * initcall_run_list() - Run through a list of function calls - * - * This calls functions one after the other, stopping at the first error, or - * when NULL is obtained. - * - * @init_sequence: NULL-terminated init sequence to run - * Return: 0 if OK, or -ve error code from the first failure - */ -int initcall_run_list(const init_fnc_t init_sequence[]); +#define INITCALL(_call) \ + do { \ + if (_call()) { \ + printf("%s(): initcall %s() failed\n", __func__, \ + #_call); \ + hang(); \ + } \ + } while (0) + +#define INITCALL_EVT(_evt) \ + do { \ + if (event_notify_null(_evt)) { \ + printf("%s(): event %d/%s failed\n", __func__, _evt, \ + event_type_name(_evt)) ; \ + hang(); \ + } \ + } while (0) + +#if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG) +#define WATCHDOG_INIT() INITCALL(init_func_watchdog_init) +#define WATCHDOG_RESET() INITCALL(init_func_watchdog_reset) +#else +#define WATCHDOG_INIT() +#define WATCHDOG_RESET() +#endif #endif diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 5ea2171492e..267757939e0 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -219,6 +219,8 @@ struct clk_composite { const struct clk_ops *mux_ops; const struct clk_ops *rate_ops; const struct clk_ops *gate_ops; + + struct udevice *dev; }; #define to_clk_composite(_clk) container_of(_clk, struct clk_composite, clk) diff --git a/include/linux/intel-smc.h b/include/linux/intel-smc.h index a54eff43add..6455335bae4 100644 --- a/include/linux/intel-smc.h +++ b/include/linux/intel-smc.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2017-2018, Intel Corporation + * Copyright (C) 2025 Altera Corporation <www.altera.com> */ #ifndef __INTEL_SMC_H @@ -482,10 +483,16 @@ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE) * Call register usage: * a0 INTEL_SIP_SMC_HPS_SET_BRIDGES * a1 Set bridges status: - * 0 - Disable - * 1 - Enable - * a2-7 not used - * + * Bit 0: 0 - Disable, 1 - Enable + * Bit 1: 1 - Has mask value in a2 + * a2 Mask value + * Bit 0: soc2fpga + * Bit 1: lwhps2fpga + * Bit 2: fpga2soc + * Bit 3: f2sdram0 (For Stratix 10 only) + * Bit 4: f2sdram1 (For Stratix 10 only) + * Bit 5: f2sdram2 (For Stratix 10 only) + * a3-7 not used * Return status * a0 INTEL_SIP_SMC_STATUS_OK */ diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index b8b207f7b5c..4eef4ab0488 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -569,7 +569,7 @@ struct spi_nor { u8 rdsr_dummy; u8 rdsr_addr_nbytes; u8 addr_mode_nbytes; -#ifdef CONFIG_SPI_FLASH_BAR +#if CONFIG_IS_ENABLED(SPI_FLASH_BAR) u8 bank_read_cmd; u8 bank_write_cmd; u8 bank_curr; diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index 13b5a52f8b9..6fe6fd520a4 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -17,7 +17,7 @@ #include <linux/spi/spi.h> #include <linux/spi/spi-mem.h> #else -#include <spi.h> +#include <linux/bitops.h> #include <spi-mem.h> #include <linux/mtd/nand.h> #endif diff --git a/include/linux/soc/ti/ti_sci_protocol.h b/include/linux/soc/ti/ti_sci_protocol.h index 8e4c43cef31..aa4d105ee98 100644 --- a/include/linux/soc/ti/ti_sci_protocol.h +++ b/include/linux/soc/ti/ti_sci_protocol.h @@ -143,7 +143,7 @@ struct ti_sci_dev_ops { u32 reset_state); int (*get_device_resets)(const struct ti_sci_handle *handle, u32 id, u32 *reset_state); - int (*release_exclusive_devices)(const struct ti_sci_handle *handle); + int (*release_exclusive_devices)(void); }; /** diff --git a/include/linux/usb/gadget.h b/include/linux/usb/gadget.h index c7927df15aa..fe79bf64a0e 100644 --- a/include/linux/usb/gadget.h +++ b/include/linux/usb/gadget.h @@ -179,6 +179,7 @@ struct usb_ep { const struct usb_ep_ops *ops; struct list_head ep_list; struct usb_ep_caps caps; + bool enabled; unsigned maxpacket:16; unsigned maxpacket_limit:16; unsigned max_streams:16; @@ -230,7 +231,18 @@ static inline void usb_ep_set_maxpacket_limit(struct usb_ep *ep, static inline int usb_ep_enable(struct usb_ep *ep, const struct usb_endpoint_descriptor *desc) { - return ep->ops->enable(ep, desc); + int ret; + + if (ep->enabled) + return 0; + + ret = ep->ops->enable(ep, desc); + if (ret) + return ret; + + ep->enabled = true; + + return 0; } /** @@ -247,7 +259,18 @@ static inline int usb_ep_enable(struct usb_ep *ep, */ static inline int usb_ep_disable(struct usb_ep *ep) { - return ep->ops->disable(ep); + int ret; + + if (!ep->enabled) + return 0; + + ret = ep->ops->disable(ep); + if (ret) + return ret; + + ep->enabled = false; + + return 0; } /** diff --git a/include/lmb.h b/include/lmb.h index 0d316c64c0a..606a92cca48 100644 --- a/include/lmb.h +++ b/include/lmb.h @@ -27,9 +27,9 @@ * %LMB_NONOTIFY: Do not notify other modules of changes to this memory region */ #define LMB_NONE 0 -#define LMB_NOMAP BIT(0) -#define LMB_NOOVERWRITE BIT(1) -#define LMB_NONOTIFY BIT(2) +#define LMB_NOMAP BIT(1) +#define LMB_NOOVERWRITE BIT(2) +#define LMB_NONOTIFY BIT(3) /** * enum lmb_map_op - memory map operation diff --git a/include/mmc.h b/include/mmc.h index 81bccb4cf12..eead666ae44 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -79,6 +79,10 @@ struct bd_info; #define IS_SD(x) ((x)->version & SD_VERSION_SD) #define IS_MMC(x) ((x)->version & MMC_VERSION_MMC) +#define CID_MANFID_MICRON 0x13 +#define CID_MANFID_SAMSUNG 0x15 +#define CID_MANFID_SANDISK 0x45 + #define MMC_DATA_READ 1 #define MMC_DATA_WRITE 2 @@ -112,6 +116,7 @@ struct bd_info; #define MMC_CMD62_ARG1 0xefac62ec #define MMC_CMD62_ARG2 0xcbaea7 +#define MMC_CMD62_ARG_SANDISK 0x254ddec4 #define SD_CMD_SEND_RELATIVE_ADDR 3 #define SD_CMD_SWITCH_FUNC 6 @@ -205,6 +210,7 @@ static inline bool mmc_is_tuning_cmd(uint cmdidx) /* * EXT_CSD fields */ +#define EXT_CSD_BOOT_SIZE_MULT_MICRON 125 /* R/W, vendor specific field */ #define EXT_CSD_ENH_START_ADDR 136 /* R/W */ #define EXT_CSD_ENH_SIZE_MULT 140 /* R/W */ #define EXT_CSD_GP_SIZE_MULT 143 /* R/W */ @@ -488,6 +494,14 @@ struct dm_mmc_ops { int (*set_ios)(struct udevice *dev); /** + * send_init_stream() - send the initialization stream: 74 clock cycles + * This is used after power up before sending the first command + * + * @dev: Device to update + */ + void (*send_init_stream)(struct udevice *dev); + + /** * get_cd() - See whether a card is present * * @dev: Device to check @@ -566,6 +580,7 @@ struct dm_mmc_ops { /* Transition functions for compatibility */ int mmc_set_ios(struct mmc *mmc); +void mmc_send_init_stream(struct mmc *mmc); int mmc_getcd(struct mmc *mmc); int mmc_getwp(struct mmc *mmc); int mmc_execute_tuning(struct mmc *mmc, uint opcode); @@ -759,7 +774,11 @@ struct mmc { enum bus_mode user_speed_mode; /* input speed mode from user */ - CONFIG_IS_ENABLED(CYCLIC, (struct cyclic_info cyclic)); + /* + * If CONFIG_CYCLIC is not set, struct cyclic_info is + * zero-size structure and does not add any space here. + */ + struct cyclic_info cyclic; }; #if CONFIG_IS_ENABLED(DM_MMC) diff --git a/include/net-common.h b/include/net-common.h index 30860f5975a..e536968a92b 100644 --- a/include/net-common.h +++ b/include/net-common.h @@ -471,6 +471,9 @@ static inline struct in_addr env_get_ip(char *var) int net_init(void); +/* Called when a network operation fails to know if it should be re-tried */ +int net_start_again(void); + /* NET compatibility */ enum proto_t; int net_loop(enum proto_t protocol); @@ -490,6 +493,18 @@ int net_loop(enum proto_t protocol); */ int dhcp_run(ulong addr, const char *fname, bool autoload); + +/** + * do_ping - Run the ping command + * + * @cmdtp: Unused + * @flag: Command flags (CMD_FLAG_...) + * @argc: Number of arguments + * @argv: List of arguments + * Return: result (see enum command_ret_t) + */ +int do_ping(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); + /** * do_tftpb - Run the tftpboot command * diff --git a/include/net-legacy.h b/include/net-legacy.h index bc0f0cde9fe..51780999a88 100644 --- a/include/net-legacy.h +++ b/include/net-legacy.h @@ -347,9 +347,6 @@ extern int net_ntp_time_offset; /* offset time from UTC */ int net_loop(enum proto_t); -/* Load failed. Start again. */ -int net_start_again(void); - /* Get size of the ethernet header when we send */ int net_eth_hdr_size(void); diff --git a/include/net-lwip.h b/include/net-lwip.h index 64e5c720560..b762956e8fd 100644 --- a/include/net-lwip.h +++ b/include/net-lwip.h @@ -10,7 +10,14 @@ enum proto_t { TFTPGET }; -void net_lwip_set_current(void); +static inline int eth_is_on_demand_init(void) +{ + return 1; +} + +int eth_init_state_only(void); /* Set active state */ + +int net_lwip_eth_start(void); struct netif *net_lwip_new_netif(struct udevice *udev); struct netif *net_lwip_new_netif_noip(struct udevice *udev); void net_lwip_remove_netif(struct netif *netif); @@ -27,7 +34,6 @@ bool wget_validate_uri(char *uri); int do_dhcp(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); int do_dns(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); -int do_ping(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); int do_wget(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]); #endif /* __NET_LWIP_H__ */ diff --git a/include/net6.h b/include/net6.h index 1ed989e584a..2ceeaba0639 100644 --- a/include/net6.h +++ b/include/net6.h @@ -90,6 +90,16 @@ struct udp_hdr { 0x00, 0x00, 0x00, 0x00, \ 0x00, 0x00, 0x00, 0x00, \ 0x00, 0x00, 0x00, 0x02 } } } +/* + * With IPv6, the broadcast MAC address is not used. Instead, it should use + * the multicast address (see RFC RFC2464 section 7) + */ +#define IPV6_ALL_NODE_ETH_ADDR(_ip6_addr) {0x33, \ + 0x33, \ + _ip6_addr.in6_u.u6_addr8[12], \ + _ip6_addr.in6_u.u6_addr8[13], \ + _ip6_addr.in6_u.u6_addr8[14], \ + _ip6_addr.in6_u.u6_addr8[15]} #define IPV6_LINK_LOCAL_PREFIX 0xfe80 #define IPV6_LINK_LOCAL_MASK 0xffb0 /* The first 10-bit of address mask. */ diff --git a/include/power-domain.h b/include/power-domain.h index 18525073e5e..7fd2c5e365b 100644 --- a/include/power-domain.h +++ b/include/power-domain.h @@ -66,6 +66,15 @@ struct power_domain { }; /** + * struct power_domain_plat - Per device accessible structure + * @subdomains: Number of subdomains covered by this device, required + * for refcounting + */ +struct power_domain_plat { + int subdomains; +}; + +/** * power_domain_get - Get/request the power domain for a device. * * This looks up and requests a power domain. Each device is assumed to have @@ -147,38 +156,82 @@ static inline int power_domain_free(struct power_domain *power_domain) #endif /** - * power_domain_on - Enable power to a power domain. + * power_domain_on_lowlevel - Enable power to a power domain (with refcounting) * * @power_domain: A power domain struct that was previously successfully * requested by power_domain_get(). - * Return: 0 if OK, or a negative error code. + * Return: 0 if the transition has been performed correctly, + * -EALREADY if the domain is already on, + * a negative error code otherwise. */ #if CONFIG_IS_ENABLED(POWER_DOMAIN) -int power_domain_on(struct power_domain *power_domain); +int power_domain_on_lowlevel(struct power_domain *power_domain); #else -static inline int power_domain_on(struct power_domain *power_domain) +static inline int power_domain_on_lowlevel(struct power_domain *power_domain) { return -ENOSYS; } #endif /** - * power_domain_off - Disable power to a power domain. + * power_domain_on - Enable power to a power domain (ignores the actual state + * of the power domain) * * @power_domain: A power domain struct that was previously successfully * requested by power_domain_get(). - * Return: 0 if OK, or a negative error code. + * Return: a negative error code upon error during the transition, 0 otherwise. + */ +static inline int power_domain_on(struct power_domain *power_domain) +{ + int ret; + + ret = power_domain_on_lowlevel(power_domain); + if (ret == -EALREADY) + ret = 0; + + return ret; +} + +/** + * power_domain_off_lowlevel - Disable power to a power domain (with refcounting) + * + * @power_domain: A power domain struct that was previously successfully + * requested by power_domain_get(). + * Return: 0 if the transition has been performed correctly, + * -EALREADY if the domain is already off, + * -EBUSY if another device is keeping the domain on (but the refcounter + * is decremented), + * a negative error code otherwise. */ #if CONFIG_IS_ENABLED(POWER_DOMAIN) -int power_domain_off(struct power_domain *power_domain); +int power_domain_off_lowlevel(struct power_domain *power_domain); #else -static inline int power_domain_off(struct power_domain *power_domain) +static inline int power_domain_off_lowlevel(struct power_domain *power_domain) { return -ENOSYS; } #endif /** + * power_domain_off - Disable power to a power domain (ignores the actual state + * of the power domain) + * + * @power_domain: A power domain struct that was previously successfully + * requested by power_domain_get(). + * Return: a negative error code upon error during the transition, 0 otherwise. + */ +static inline int power_domain_off(struct power_domain *power_domain) +{ + int ret; + + ret = power_domain_off_lowlevel(power_domain); + if (ret == -EALREADY || ret == -EBUSY) + ret = 0; + + return ret; +} + +/** * dev_power_domain_on - Enable power domains for a device . * * @dev: The client device. diff --git a/include/power/cpcap.h b/include/power/cpcap.h new file mode 100644 index 00000000000..bb0e28cec55 --- /dev/null +++ b/include/power/cpcap.h @@ -0,0 +1,373 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +#ifndef _CPCAP_H_ +#define _CPCAP_H_ + +#define CPCAP_VENDOR_ST 0 +#define CPCAP_VENDOR_TI 1 + +#define CPCAP_REVISION_MAJOR(r) (((r) >> 4) + 1) +#define CPCAP_REVISION_MINOR(r) ((r) & 0xf) + +#define CPCAP_REVISION_1_0 0x08 +#define CPCAP_REVISION_1_1 0x09 +#define CPCAP_REVISION_2_0 0x10 +#define CPCAP_REVISION_2_1 0x11 +#define CPCAP_REVISION_3_1 0x19 + +/* CPCAP registers */ +#define CPCAP_REG_INT1 0x0000 /* Interrupt 1 */ +#define CPCAP_REG_INT2 0x0004 /* Interrupt 2 */ +#define CPCAP_REG_INT3 0x0008 /* Interrupt 3 */ +#define CPCAP_REG_INT4 0x000c /* Interrupt 4 */ +#define CPCAP_REG_INTM1 0x0010 /* Interrupt Mask 1 */ +#define CPCAP_REG_INTM2 0x0014 /* Interrupt Mask 2 */ +#define CPCAP_REG_INTM3 0x0018 /* Interrupt Mask 3 */ +#define CPCAP_REG_INTM4 0x001c /* Interrupt Mask 4 */ +#define CPCAP_REG_INTS1 0x0020 /* Interrupt Sense 1 */ +#define CPCAP_REG_INTS2 0x0024 /* Interrupt Sense 2 */ +#define CPCAP_REG_INTS3 0x0028 /* Interrupt Sense 3 */ +#define CPCAP_REG_INTS4 0x002c /* Interrupt Sense 4 */ +#define CPCAP_REG_ASSIGN1 0x0030 /* Resource Assignment 1 */ +#define CPCAP_REG_ASSIGN2 0x0034 /* Resource Assignment 2 */ +#define CPCAP_REG_ASSIGN3 0x0038 /* Resource Assignment 3 */ +#define CPCAP_REG_ASSIGN4 0x003c /* Resource Assignment 4 */ +#define CPCAP_REG_ASSIGN5 0x0040 /* Resource Assignment 5 */ +#define CPCAP_REG_ASSIGN6 0x0044 /* Resource Assignment 6 */ +#define CPCAP_REG_VERSC1 0x0048 /* Version Control 1 */ +#define CPCAP_REG_VERSC2 0x004c /* Version Control 2 */ + +#define CPCAP_REG_MI1 0x0200 /* Macro Interrupt 1 */ +#define CPCAP_REG_MIM1 0x0204 /* Macro Interrupt Mask 1 */ +#define CPCAP_REG_MI2 0x0208 /* Macro Interrupt 2 */ +#define CPCAP_REG_MIM2 0x020c /* Macro Interrupt Mask 2 */ +#define CPCAP_REG_UCC1 0x0210 /* UC Control 1 */ +#define CPCAP_REG_UCC2 0x0214 /* UC Control 2 */ + +#define CPCAP_REG_PC1 0x021c /* Power Cut 1 */ +#define CPCAP_REG_PC2 0x0220 /* Power Cut 2 */ +#define CPCAP_REG_BPEOL 0x0224 /* BP and EOL */ +#define CPCAP_REG_PGC 0x0228 /* Power Gate and Control */ +#define CPCAP_REG_MT1 0x022c /* Memory Transfer 1 */ +#define CPCAP_REG_MT2 0x0230 /* Memory Transfer 2 */ +#define CPCAP_REG_MT3 0x0234 /* Memory Transfer 3 */ +#define CPCAP_REG_PF 0x0238 /* Print Format */ + +#define CPCAP_REG_SCC 0x0400 /* System Clock Control */ +#define CPCAP_REG_SW1 0x0404 /* Stop Watch 1 */ +#define CPCAP_REG_SW2 0x0408 /* Stop Watch 2 */ +#define CPCAP_REG_UCTM 0x040c /* UC Turbo Mode */ +#define CPCAP_REG_TOD1 0x0410 /* Time of Day 1 */ +#define CPCAP_REG_TOD2 0x0414 /* Time of Day 2 */ +#define CPCAP_REG_TODA1 0x0418 /* Time of Day Alarm 1 */ +#define CPCAP_REG_TODA2 0x041c /* Time of Day Alarm 2 */ +#define CPCAP_REG_DAY 0x0420 /* Day */ +#define CPCAP_REG_DAYA 0x0424 /* Day Alarm */ +#define CPCAP_REG_VAL1 0x0428 /* Validity 1 */ +#define CPCAP_REG_VAL2 0x042c /* Validity 2 */ + +#define CPCAP_REG_SDVSPLL 0x0600 /* Switcher DVS and PLL */ +#define CPCAP_REG_SI2CC1 0x0604 /* Switcher I2C Control 1 */ +#define CPCAP_REG_Si2CC2 0x0608 /* Switcher I2C Control 2 */ +#define CPCAP_REG_S1C1 0x060c /* Switcher 1 Control 1 */ +#define CPCAP_REG_S1C2 0x0610 /* Switcher 1 Control 2 */ +#define CPCAP_REG_S2C1 0x0614 /* Switcher 2 Control 1 */ +#define CPCAP_REG_S2C2 0x0618 /* Switcher 2 Control 2 */ +#define CPCAP_REG_S3C 0x061c /* Switcher 3 Control */ +#define CPCAP_REG_S4C1 0x0620 /* Switcher 4 Control 1 */ +#define CPCAP_REG_S4C2 0x0624 /* Switcher 4 Control 2 */ +#define CPCAP_REG_S5C 0x0628 /* Switcher 5 Control */ +#define CPCAP_REG_S6C 0x062c /* Switcher 6 Control */ +#define CPCAP_REG_VCAMC 0x0630 /* VCAM Control */ +#define CPCAP_REG_VCSIC 0x0634 /* VCSI Control */ +#define CPCAP_REG_VDACC 0x0638 /* VDAC Control */ +#define CPCAP_REG_VDIGC 0x063c /* VDIG Control */ +#define CPCAP_REG_VFUSEC 0x0640 /* VFUSE Control */ +#define CPCAP_REG_VHVIOC 0x0644 /* VHVIO Control */ +#define CPCAP_REG_VSDIOC 0x0648 /* VSDIO Control */ +#define CPCAP_REG_VPLLC 0x064c /* VPLL Control */ +#define CPCAP_REG_VRF1C 0x0650 /* VRF1 Control */ +#define CPCAP_REG_VRF2C 0x0654 /* VRF2 Control */ +#define CPCAP_REG_VRFREFC 0x0658 /* VRFREF Control */ +#define CPCAP_REG_VWLAN1C 0x065c /* VWLAN1 Control */ +#define CPCAP_REG_VWLAN2C 0x0660 /* VWLAN2 Control */ +#define CPCAP_REG_VSIMC 0x0664 /* VSIM Control */ +#define CPCAP_REG_VVIBC 0x0668 /* VVIB Control */ +#define CPCAP_REG_VUSBC 0x066c /* VUSB Control */ +#define CPCAP_REG_VUSBINT1C 0x0670 /* VUSBINT1 Control */ +#define CPCAP_REG_VUSBINT2C 0x0674 /* VUSBINT2 Control */ +#define CPCAP_REG_URT 0x0678 /* Useroff Regulator Trigger */ +#define CPCAP_REG_URM1 0x067c /* Useroff Regulator Mask 1 */ +#define CPCAP_REG_URM2 0x0680 /* Useroff Regulator Mask 2 */ + +#define CPCAP_REG_VAUDIOC 0x0800 /* VAUDIO Control */ +#define CPCAP_REG_CC 0x0804 /* Codec Control */ +#define CPCAP_REG_CDI 0x0808 /* Codec Digital Interface */ +#define CPCAP_REG_SDAC 0x080c /* Stereo DAC */ +#define CPCAP_REG_SDACDI 0x0810 /* Stereo DAC Digital Interface */ +#define CPCAP_REG_TXI 0x0814 /* TX Inputs */ +#define CPCAP_REG_TXMP 0x0818 /* TX MIC PGA's */ +#define CPCAP_REG_RXOA 0x081c /* RX Output Amplifiers */ +#define CPCAP_REG_RXVC 0x0820 /* RX Volume Control */ +#define CPCAP_REG_RXCOA 0x0824 /* RX Codec to Output Amps */ +#define CPCAP_REG_RXSDOA 0x0828 /* RX Stereo DAC to Output Amps */ +#define CPCAP_REG_RXEPOA 0x082c /* RX External PGA to Output Amps */ +#define CPCAP_REG_RXLL 0x0830 /* RX Low Latency */ +#define CPCAP_REG_A2LA 0x0834 /* A2 Loudspeaker Amplifier */ +#define CPCAP_REG_MIPIS1 0x0838 /* MIPI Slimbus 1 */ +#define CPCAP_REG_MIPIS2 0x083c /* MIPI Slimbus 2 */ +#define CPCAP_REG_MIPIS3 0x0840 /* MIPI Slimbus 3. */ +#define CPCAP_REG_LVAB 0x0844 /* LMR Volume and A4 Balanced. */ + +#define CPCAP_REG_CCC1 0x0a00 /* Coulomb Counter Control 1 */ +#define CPCAP_REG_CRM 0x0a04 /* Charger and Reverse Mode */ +#define CPCAP_REG_CCCC2 0x0a08 /* Coincell and Coulomb Ctr Ctrl 2 */ +#define CPCAP_REG_CCS1 0x0a0c /* Coulomb Counter Sample 1 */ +#define CPCAP_REG_CCS2 0x0a10 /* Coulomb Counter Sample 2 */ +#define CPCAP_REG_CCA1 0x0a14 /* Coulomb Counter Accumulator 1 */ +#define CPCAP_REG_CCA2 0x0a18 /* Coulomb Counter Accumulator 2 */ +#define CPCAP_REG_CCM 0x0a1c /* Coulomb Counter Mode */ +#define CPCAP_REG_CCO 0x0a20 /* Coulomb Counter Offset */ +#define CPCAP_REG_CCI 0x0a24 /* Coulomb Counter Integrator */ + +#define CPCAP_REG_ADCC1 0x0c00 /* A/D Converter Configuration 1 */ +#define CPCAP_REG_ADCC2 0x0c04 /* A/D Converter Configuration 2 */ +#define CPCAP_REG_ADCD0 0x0c08 /* A/D Converter Data 0 */ +#define CPCAP_REG_ADCD1 0x0c0c /* A/D Converter Data 1 */ +#define CPCAP_REG_ADCD2 0x0c10 /* A/D Converter Data 2 */ +#define CPCAP_REG_ADCD3 0x0c14 /* A/D Converter Data 3 */ +#define CPCAP_REG_ADCD4 0x0c18 /* A/D Converter Data 4 */ +#define CPCAP_REG_ADCD5 0x0c1c /* A/D Converter Data 5 */ +#define CPCAP_REG_ADCD6 0x0c20 /* A/D Converter Data 6 */ +#define CPCAP_REG_ADCD7 0x0c24 /* A/D Converter Data 7 */ +#define CPCAP_REG_ADCAL1 0x0c28 /* A/D Converter Calibration 1 */ +#define CPCAP_REG_ADCAL2 0x0c2c /* A/D Converter Calibration 2 */ + +#define CPCAP_REG_USBC1 0x0e00 /* USB Control 1 */ +#define CPCAP_REG_USBC2 0x0e04 /* USB Control 2 */ +#define CPCAP_REG_USBC3 0x0e08 /* USB Control 3 */ +#define CPCAP_REG_UVIDL 0x0e0c /* ULPI Vendor ID Low */ +#define CPCAP_REG_UVIDH 0x0e10 /* ULPI Vendor ID High */ +#define CPCAP_REG_UPIDL 0x0e14 /* ULPI Product ID Low */ +#define CPCAP_REG_UPIDH 0x0e18 /* ULPI Product ID High */ +#define CPCAP_REG_UFC1 0x0e1c /* ULPI Function Control 1 */ +#define CPCAP_REG_UFC2 0x0e20 /* ULPI Function Control 2 */ +#define CPCAP_REG_UFC3 0x0e24 /* ULPI Function Control 3 */ +#define CPCAP_REG_UIC1 0x0e28 /* ULPI Interface Control 1 */ +#define CPCAP_REG_UIC2 0x0e2c /* ULPI Interface Control 2 */ +#define CPCAP_REG_UIC3 0x0e30 /* ULPI Interface Control 3 */ +#define CPCAP_REG_USBOTG1 0x0e34 /* USB OTG Control 1 */ +#define CPCAP_REG_USBOTG2 0x0e38 /* USB OTG Control 2 */ +#define CPCAP_REG_USBOTG3 0x0e3c /* USB OTG Control 3 */ +#define CPCAP_REG_UIER1 0x0e40 /* USB Interrupt Enable Rising 1 */ +#define CPCAP_REG_UIER2 0x0e44 /* USB Interrupt Enable Rising 2 */ +#define CPCAP_REG_UIER3 0x0e48 /* USB Interrupt Enable Rising 3 */ +#define CPCAP_REG_UIEF1 0x0e4c /* USB Interrupt Enable Falling 1 */ +#define CPCAP_REG_UIEF2 0x0e50 /* USB Interrupt Enable Falling 1 */ +#define CPCAP_REG_UIEF3 0x0e54 /* USB Interrupt Enable Falling 1 */ +#define CPCAP_REG_UIS 0x0e58 /* USB Interrupt Status */ +#define CPCAP_REG_UIL 0x0e5c /* USB Interrupt Latch */ +#define CPCAP_REG_USBD 0x0e60 /* USB Debug */ +#define CPCAP_REG_SCR1 0x0e64 /* Scratch 1 */ +#define CPCAP_REG_SCR2 0x0e68 /* Scratch 2 */ +#define CPCAP_REG_SCR3 0x0e6c /* Scratch 3 */ + +#define CPCAP_REG_VMC 0x0eac /* Video Mux Control */ +#define CPCAP_REG_OWDC 0x0eb0 /* One Wire Device Control */ +#define CPCAP_REG_GPIO0 0x0eb4 /* GPIO 0 Control */ + +#define CPCAP_REG_GPIO1 0x0ebc /* GPIO 1 Control */ + +#define CPCAP_REG_GPIO2 0x0ec4 /* GPIO 2 Control */ + +#define CPCAP_REG_GPIO3 0x0ecc /* GPIO 3 Control */ + +#define CPCAP_REG_GPIO4 0x0ed4 /* GPIO 4 Control */ + +#define CPCAP_REG_GPIO5 0x0edc /* GPIO 5 Control */ + +#define CPCAP_REG_GPIO6 0x0ee4 /* GPIO 6 Control */ + +#define CPCAP_REG_MDLC 0x1000 /* Main Display Lighting Control */ +#define CPCAP_REG_KLC 0x1004 /* Keypad Lighting Control */ +#define CPCAP_REG_ADLC 0x1008 /* Aux Display Lighting Control */ +#define CPCAP_REG_REDC 0x100c /* Red Triode Control */ +#define CPCAP_REG_GREENC 0x1010 /* Green Triode Control */ +#define CPCAP_REG_BLUEC 0x1014 /* Blue Triode Control */ +#define CPCAP_REG_CFC 0x1018 /* Camera Flash Control */ +#define CPCAP_REG_ABC 0x101c /* Adaptive Boost Control */ +#define CPCAP_REG_BLEDC 0x1020 /* Bluetooth LED Control */ +#define CPCAP_REG_CLEDC 0x1024 /* Camera Privacy LED Control */ + +#define CPCAP_REG_OW1C 0x1200 /* One Wire 1 Command */ +#define CPCAP_REG_OW1D 0x1204 /* One Wire 1 Data */ +#define CPCAP_REG_OW1I 0x1208 /* One Wire 1 Interrupt */ +#define CPCAP_REG_OW1IE 0x120c /* One Wire 1 Interrupt Enable */ + +#define CPCAP_REG_OW1 0x1214 /* One Wire 1 Control */ + +#define CPCAP_REG_OW2C 0x1220 /* One Wire 2 Command */ +#define CPCAP_REG_OW2D 0x1224 /* One Wire 2 Data */ +#define CPCAP_REG_OW2I 0x1228 /* One Wire 2 Interrupt */ +#define CPCAP_REG_OW2IE 0x122c /* One Wire 2 Interrupt Enable */ + +#define CPCAP_REG_OW2 0x1234 /* One Wire 2 Control */ + +#define CPCAP_REG_OW3C 0x1240 /* One Wire 3 Command */ +#define CPCAP_REG_OW3D 0x1244 /* One Wire 3 Data */ +#define CPCAP_REG_OW3I 0x1248 /* One Wire 3 Interrupt */ +#define CPCAP_REG_OW3IE 0x124c /* One Wire 3 Interrupt Enable */ + +#define CPCAP_REG_OW3 0x1254 /* One Wire 3 Control */ +#define CPCAP_REG_GCAIC 0x1258 /* GCAI Clock Control */ +#define CPCAP_REG_GCAIM 0x125c /* GCAI GPIO Mode */ +#define CPCAP_REG_LGDIR 0x1260 /* LMR GCAI GPIO Direction */ +#define CPCAP_REG_LGPU 0x1264 /* LMR GCAI GPIO Pull-up */ +#define CPCAP_REG_LGPIN 0x1268 /* LMR GCAI GPIO Pin */ +#define CPCAP_REG_LGMASK 0x126c /* LMR GCAI GPIO Mask */ +#define CPCAP_REG_LDEB 0x1270 /* LMR Debounce Settings */ +#define CPCAP_REG_LGDET 0x1274 /* LMR GCAI Detach Detect */ +#define CPCAP_REG_LMISC 0x1278 /* LMR Misc Bits */ +#define CPCAP_REG_LMACE 0x127c /* LMR Mace IC Support */ + +#define CPCAP_REG_TEST 0x7c00 /* Test */ + +#define CPCAP_REG_ST_TEST1 0x7d08 /* ST Test1 */ + +#define CPCAP_REG_ST_TEST2 0x7d18 /* ST Test2 */ + +/* Drivers name */ +#define CPCAP_LDO_DRIVER "cpcap_ldo" +#define CPCAP_SW_DRIVER "cpcap_sw" + +enum cpcap_regulator_id { + CPCAP_SW1, + CPCAP_SW2, + CPCAP_SW3, + CPCAP_SW4, + CPCAP_SW5, + CPCAP_SW6, + CPCAP_VCAM, + CPCAP_VCSI, + CPCAP_VDAC, + CPCAP_VDIG, + CPCAP_VFUSE, + CPCAP_VHVIO, + CPCAP_VSDIO, + CPCAP_VPLL, + CPCAP_VRF1, + CPCAP_VRF2, + CPCAP_VRFREF, + CPCAP_VWLAN1, + CPCAP_VWLAN2, + CPCAP_VSIM, + CPCAP_VSIMCARD, + CPCAP_VVIB, + CPCAP_VUSB, + CPCAP_VAUDIO, + CPCAP_REGULATORS_COUNT, +}; + +static const char * const cpcap_regulator_to_name[] = { + /* BUCK */ + [CPCAP_SW1] = "sw1", + [CPCAP_SW2] = "sw2", + [CPCAP_SW3] = "sw3", + [CPCAP_SW4] = "sw4", + [CPCAP_SW5] = "sw5", + [CPCAP_SW6] = "sw6", + /* LDO */ + [CPCAP_VCAM] = "vcam", + [CPCAP_VCSI] = "vcsi", + [CPCAP_VDAC] = "vdac", + [CPCAP_VDIG] = "vdig", + [CPCAP_VFUSE] = "vfuse", + [CPCAP_VHVIO] = "vhvio", + [CPCAP_VSDIO] = "vsdio", + [CPCAP_VPLL] = "vpll", + [CPCAP_VRF1] = "vrf1", + [CPCAP_VRF2] = "vrf2", + [CPCAP_VRFREF] = "vrfref", + [CPCAP_VWLAN1] = "vwlan1", + [CPCAP_VWLAN2] = "vwlan2", + [CPCAP_VSIM] = "vsim", + [CPCAP_VSIMCARD] = "vsimcard", + [CPCAP_VVIB] = "vvib", + [CPCAP_VUSB] = "vusb", + [CPCAP_VAUDIO] = "vaudio", +}; + +static const u32 unknown_val_tbl[] = { 0, }; +static const u32 sw1_val_tbl[] = { 750000, 762500, 775000, 787500, 800000, + 812500, 825000, 837500, 850000, 862500, + 875000, 887500, 900000, 912500, 925000, + 937500, 950000, 962500, 975000, 987500, + 1000000, 1012500, 1025000, 1037500, + 1050000, 1062500, 1075000, 1087500, + 1100000, 1112500, 1125000, 1137500, + 1150000, 1162500, 1175000, 1187500, + 1200000, 1212500, 1225000, 1237500, + 1250000, 1262500, 1275000, 1287500, + 1300000, 1312500, 1325000, 1337500, + 1350000, 1362500, 1375000, 1387500, + 1400000, 1412500, 1425000, 1437500, + 1450000, 1462500, 1475000 }; +static const u32 sw2_sw4_val_tbl[] = { 900000, 912500, 925000, 937500, 950000, + 962500, 975000, 987500, 1000000, 1012500, + 1025000, 1037500, 1050000, 1062500, + 1075000, 1087500, 1100000, 1112500, + 1125000, 1137500, 1150000, 1162500, + 1175000, 1187500, 1200000, 1212500, + 1225000, 1237500, 1250000, 1262500, + 1275000, 1287500, 1300000, 1312500, + 1325000, 1337500, 1350000, 1362500, + 1375000, 1387500, 1400000, 1412500, + 1425000, 1437500, 1450000, 1462500, + 1475000 }; +static const u32 sw3_val_tbl[] = { 1350000, 1800000, 1850000, 1875000 }; +static const u32 sw5_val_tbl[] = { 0, 5050000 }; +static const u32 vcam_val_tbl[] = { 2600000, 2700000, 2800000, 2900000 }; +static const u32 vcsi_val_tbl[] = { 1200000, 1800000 }; +static const u32 vdac_val_tbl[] = { 1200000, 1500000, 1800000, 2500000 }; +static const u32 vdig_val_tbl[] = { 1200000, 1350000, 1500000, 1875000 }; +static const u32 vfuse_val_tbl[] = { 1500000, 1600000, 1700000, 1800000, 1900000, + 2000000, 2100000, 2200000, 2300000, 2400000, + 2500000, 2600000, 2700000, 3150000 }; +static const u32 vhvio_val_tbl[] = { 2775000 }; +static const u32 vsdio_val_tbl[] = { 1500000, 1600000, 1800000, 2600000, + 2700000, 2800000, 2900000, 3000000 }; +static const u32 vpll_val_tbl[] = { 1200000, 1300000, 1400000, 1800000 }; +static const u32 vrf1_val_tbl[] = { 2775000, 2500000 }; /* Yes, this is correct */ +static const u32 vrf2_val_tbl[] = { 0, 2775000 }; +static const u32 vrfref_val_tbl[] = { 2500000, 2775000 }; +static const u32 vwlan1_val_tbl[] = { 1800000, 1900000 }; +static const u32 vwlan2_val_tbl[] = { 2775000, 3000000, 3300000, 3300000 }; +static const u32 vsim_val_tbl[] = { 1800000, 2900000 }; +static const u32 vsimcard_val_tbl[] = { 1800000, 2900000 }; +static const u32 vvib_val_tbl[] = { 1300000, 1800000, 2000000, 3000000 }; +static const u32 vusb_val_tbl[] = { 0, 3300000 }; +static const u32 vaudio_val_tbl[] = { 0, 2775000 }; + +struct cpcap_regulator_data { + u16 reg; + u16 assignment_reg; + u16 assignment_mask; + u16 mode_mask; + u16 volt_mask; + u8 volt_shft; + u16 mode_val; + u16 off_mode_val; + u32 val_tbl_sz; + const u32 *val_tbl; + u32 mode_cntr; + u32 volt_trans_time; /* in micro seconds */ + u32 turn_on_time; /* in micro seconds */ + + /* + * Bit difference between lowest value in val_tbl and start of voltage + * table setting in cpcap. Use this for switchers that have many too + * many voltages to list in val_tbl. + */ + u32 bit_offset_from_cpcap_lowest_voltage; +}; + +#endif /* _CPCAP_H_ */ diff --git a/include/regmap.h b/include/regmap.h index 22b043408ac..8c6f7c1c9b1 100644 --- a/include/regmap.h +++ b/include/regmap.h @@ -362,6 +362,34 @@ int regmap_raw_read_range(struct regmap *map, uint range_num, uint offset, int regmap_update_bits(struct regmap *map, uint offset, uint mask, uint val); /** + * regmap_set_bits() - Set bits to a regmap + * + * @map: Regmap to write bits to + * @offset: Offset in the regmap to write to + * @bits: Bits to set to the regmap at the specified offset + * + * Return: 0 if OK, -ve on error + */ +static inline int regmap_set_bits(struct regmap *map, uint offset, uint bits) +{ + return regmap_update_bits(map, offset, bits, bits); +} + +/** + * regmap_clear_bits() - Clear bits to a regmap + * + * @map: Regmap to write bits to + * @offset: Offset in the regmap to write to + * @bits: Bits to clear to the regmap at the specified offset + * + * Return: 0 if OK, -ve on error + */ +static inline int regmap_clear_bits(struct regmap *map, uint offset, uint bits) +{ + return regmap_update_bits(map, offset, bits, 0); +} + +/** * regmap_init_mem() - Set up a new register map that uses memory access * * @node: Device node that uses this map diff --git a/include/scsi.h b/include/scsi.h index b18ae37b861..ab53b47b58f 100644 --- a/include/scsi.h +++ b/include/scsi.h @@ -9,6 +9,7 @@ #include <asm/cache.h> #include <bouncebuf.h> #include <linux/dma-direction.h> +#include <part.h> struct udevice; @@ -181,6 +182,7 @@ struct scsi_cmd { #define SCSI_WRT_VERIFY 0x2E /* Write and Verify (O) */ #define SCSI_WRITE_LONG 0x3F /* Write Long (O) */ #define SCSI_WRITE_SAME 0x41 /* Write Same (O) */ +#define SCSI_UNMAP 0x42 /* Write 10-Byte (MANDATORY) */ /** * enum scsi_cmd_phase - current phase of the SCSI protocol diff --git a/include/sdhci.h b/include/sdhci.h index 31a49ca6a2f..2372697b743 100644 --- a/include/sdhci.h +++ b/include/sdhci.h @@ -518,6 +518,7 @@ void sdhci_set_uhs_timing(struct sdhci_host *host); /* Export the operations to drivers */ int sdhci_probe(struct udevice *dev); int sdhci_set_clock(struct mmc *mmc, unsigned int clock); +void sdhci_set_voltage(struct sdhci_host *host); /** * sdhci_set_control_reg - Set control registers diff --git a/include/setjmp.h b/include/setjmp.h index 37d3a8af85d..32dd48803e9 100644 --- a/include/setjmp.h +++ b/include/setjmp.h @@ -3,12 +3,27 @@ #ifndef _SETJMP_H_ #define _SETJMP_H_ 1 +/** + * DOC: Overview + * + * The long jump API allows to perform nonlocal gotos, that is jump from one + * function to another typically further down in the stack, while properly + * restoring the stack's state (unwinding). The two functions needed to do this + * are setjmp() and longjmp(). + * + * In addition to these two standard POSIX.1-2001/C89 functions, a third one is + * present in U-Boot: initjmp(). It is an extension which allows to implement + * user-mode threads. + */ + #ifdef CONFIG_HAVE_SETJMP #include <asm/setjmp.h> #else struct jmp_buf_data { }; #endif +#include <linux/compiler_attributes.h> +#include <stddef.h> /** * typedef jmp_buf - information needed to restore a calling environment @@ -37,4 +52,21 @@ int setjmp(jmp_buf env); */ void longjmp(jmp_buf env, int val); +/** + * initjmp() - prepare for a long jump to a given function with a given stack + * + * This function sets up a jump buffer for later use with longjmp(). It allows + * to branch to a specific function with a specific stack. Please note that + * @func MUST NOT return. It shall typically restore the main stack and resume + * execution by doing a long jump to a jump buffer initialized by setjmp() + * before the long jump. initjmp() allows to implement multithreading. + * + * @env: jump buffer + * @func: function to be called on longjmp(), MUST NOT RETURN + * @stack_base: the stack to be used by @func (lower address) + * @stack_sz: the stack size in bytes + */ +int initjmp(jmp_buf env, void __noreturn (*func)(void), void *stack_base, + size_t stack_sz); + #endif /* _SETJMP_H_ */ diff --git a/include/spi.h b/include/spi.h index 6944773b596..2783200d663 100644 --- a/include/spi.h +++ b/include/spi.h @@ -11,6 +11,8 @@ #include <linux/bitops.h> +struct spinand_info; + /* SPI mode flags */ #define SPI_CPHA BIT(0) /* clock phase (1 = SPI_CLOCK_PHASE_SECOND) */ #define SPI_CPOL BIT(1) /* clock polarity (1 = SPI_POLARITY_HIGH) */ @@ -537,6 +539,16 @@ struct dm_spi_ops { */ int (*get_mmap)(struct udevice *dev, ulong *map_basep, uint *map_sizep, uint *offsetp); + + /** + * setup_for_spinand() - Setup the SPI for attached SPI NAND + * + * @dev: The SPI flash slave device + * @spinand_info: The SPI NAND info to configure for + * @return 0 if OK, -ve value on error + */ + int (*setup_for_spinand)(struct spi_slave *slave, + const struct spinand_info *spinand_info); }; struct dm_spi_emul_ops { diff --git a/include/sunxi_gpio.h b/include/sunxi_gpio.h index 122987c395e..12b54c8dda4 100644 --- a/include/sunxi_gpio.h +++ b/include/sunxi_gpio.h @@ -82,7 +82,6 @@ enum sunxi_gpio_number { SUNXI_GPIO_L_START = 352, SUNXI_GPIO_M_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_L), SUNXI_GPIO_N_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_M), - SUNXI_GPIO_AXP0_START = 1024, }; /* SUNXI GPIO number definitions */ @@ -99,8 +98,6 @@ enum sunxi_gpio_number { #define SUNXI_GPM(_nr) (SUNXI_GPIO_M_START + (_nr)) #define SUNXI_GPN(_nr) (SUNXI_GPIO_N_START + (_nr)) -#define SUNXI_GPAXP0(_nr) (SUNXI_GPIO_AXP0_START + (_nr)) - /* GPIO pin function config */ #define SUNXI_GPIO_INPUT 0 #define SUNXI_GPIO_OUTPUT 1 @@ -185,11 +182,6 @@ enum sunxi_gpio_number { #define SUNXI_GPIO_PULL_UP 1 #define SUNXI_GPIO_PULL_DOWN 2 -/* Virtual AXP0 GPIOs */ -#define SUNXI_GPIO_AXP0_PREFIX "AXP0-" -#define SUNXI_GPIO_AXP0_VBUS_ENABLE 5 -#define SUNXI_GPIO_AXP0_GPIO_COUNT 6 - struct sunxi_gpio_plat { void *regs; char bank_name[3]; diff --git a/include/u-boot/schedule.h b/include/u-boot/schedule.h index 4fd34c41229..4605971fdcb 100644 --- a/include/u-boot/schedule.h +++ b/include/u-boot/schedule.h @@ -3,6 +3,8 @@ #ifndef _U_BOOT_SCHEDULE_H #define _U_BOOT_SCHEDULE_H +#include <uthread.h> + #if CONFIG_IS_ENABLED(CYCLIC) /** * schedule() - Schedule all potentially waiting tasks @@ -17,6 +19,7 @@ void schedule(void); static inline void schedule(void) { + uthread_schedule(); } #endif diff --git a/include/uthread.h b/include/uthread.h new file mode 100644 index 00000000000..11a19aa9488 --- /dev/null +++ b/include/uthread.h @@ -0,0 +1,188 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2025 Linaro Limited + */ + +#include <linux/list.h> +#include <linux/types.h> +#include <setjmp.h> + +#ifndef _UTHREAD_H_ +#define _UTHREAD_H_ + +/** + * DOC: Overview + * + * The uthread framework is a basic task scheduler that allows to run functions + * "in parallel" on a single CPU core. The scheduling is cooperative, not + * preemptive -- meaning that context switches from one task to another task is + * voluntary, via a call to uthread_schedule(). This characteristic makes thread + * synchronization much easier, because a thread cannot be interrupted in the + * middle of a critical section (reading from or writing to shared state, for + * instance). + * + * CONFIG_UTHREAD in lib/Kconfig enables the uthread framework. When disabled, + * the uthread_create() and uthread_schedule() functions may still be used so + * that code differences between uthreads enabled and disabled can be reduced to + * a minimum. + */ + +/** + * struct uthread - a thread object + * + * @fn: thread entry point + * @arg: argument passed to the entry point when the thread is started + * @ctx: context to resume execution of this thread (via longjmp()) + * @stack: initial stack pointer for the thread + * @done: true once @fn has returned, false otherwise + * @grp_id: user-supplied identifier for this thread and possibly others. A + * thread can belong to zero or one group (not more), and a group may contain + * any number of threads. + * @list: link in the global scheduler list + */ +struct uthread { + void (*fn)(void *arg); + void *arg; + jmp_buf ctx; + void *stack; + bool done; + unsigned int grp_id; + struct list_head list; +}; + +/** + * enum uthread_mutex_state - internal state of a struct uthread_mutex + * + * @UTHREAD_MUTEX_UNLOCKED: mutex has no owner + * @UTHREAD_MUTEX_LOCKED: mutex has one owner + */ +enum uthread_mutex_state { + UTHREAD_MUTEX_UNLOCKED = 0, + UTHREAD_MUTEX_LOCKED = 1 +}; + +/** + * struct uthread_mutex - a mutex object + * + * @state: the internal state of the mutex + */ +struct uthread_mutex { + enum uthread_mutex_state state; +}; + +#define UTHREAD_MUTEX_INITIALIZER { .state = UTHREAD_MUTEX_UNLOCKED } + +#ifdef CONFIG_UTHREAD + +/** + * uthread_create() - Create a uthread object and make it ready for execution + * + * Threads are automatically deleted when they return from their entry point. + * + * @uthr: a pointer to a user-allocated uthread structure to store information + * about the new thread, or NULL to let the framework allocate and manage its + * own structure. + * @fn: the thread's entry point + * @arg: argument passed to the thread's entry point + * @stack_sz: stack size for the new thread (in bytes). The stack is allocated + * on the heap. + * @grp_id: an optional thread group ID that the new thread should belong to + * (zero for no group) + */ +int uthread_create(struct uthread *uthr, void (*fn)(void *), void *arg, + size_t stack_sz, unsigned int grp_id); +/** + * uthread_schedule() - yield the CPU to the next runnable thread + * + * This function is called either by the main thread or any secondary thread + * (that is, any thread created via uthread_create()) to switch execution to + * the next runnable thread. + * + * Return: true if a thread was scheduled, false if no runnable thread was found + */ +bool uthread_schedule(void); +/** + * uthread_grp_new_id() - return a new ID for a thread group + * + * Return: the new thread group ID + */ +unsigned int uthread_grp_new_id(void); +/** + * uthread_grp_done() - test if all threads in a group are done + * + * @grp_id: the ID of the thread group that should be considered + * Return: false if the group contains at least one runnable thread (i.e., one + * thread which entry point has not returned yet), true otherwise + */ +bool uthread_grp_done(unsigned int grp_id); + +/** + * uthread_mutex_lock() - lock a mutex + * + * If the cwmutexlock is available (i.e., not owned by any other thread), then + * it is locked for use by the current thread. Otherwise the current thread + * blocks: it enters a wait loop by scheduling other threads until the mutex + * becomes unlocked. + * + * @mutex: pointer to the mutex to lock + * Return: 0 on success, in which case the lock is owned by the calling thread. + * != 0 otherwise (the lock is not owned by the calling thread). + */ +int uthread_mutex_lock(struct uthread_mutex *mutex); + +/** + * uthread_mutex_trylock() - lock a mutex if not currently locked + * + * Similar to uthread_mutex_lock() except return immediately if the mutex is + * locked already. + * + * @mutex: pointer to the mutex to lock + * Return: 0 on success, in which case the lock is owned by the calling thread. + * EBUSY if the mutex is already locked by another thread. Any other non-zero + * value on error. + */ +int uthread_mutex_trylock(struct uthread_mutex *mutex); + +/** + * uthread_mutex_unlock() - unlock a mutex + * + * The mutex is assumed to be owned by the calling thread on entry. On exit, it + * is unlocked. + * + * @mutex: pointer to the mutex to unlock + * Return: 0 on success, != 0 on error + */ +int uthread_mutex_unlock(struct uthread_mutex *mutex); + +#else + +static inline int uthread_create(struct uthread *uthr, void (*fn)(void *), + void *arg, size_t stack_sz, + unsigned int grp_id) +{ + fn(arg); + return 0; +} + +static inline bool uthread_schedule(void) +{ + return false; +} + +static inline unsigned int uthread_grp_new_id(void) +{ + return 0; +} + +static inline bool uthread_grp_done(unsigned int grp_id) +{ + return true; +} + +/* These are macros for convenience on the caller side */ +#define uthread_mutex_lock(_mutex) ({ 0; }) +#define uthread_mutex_trylock(_mutex) ({ 0 }) +#define uthread_mutex_unlock(_mutex) ({ 0; }) + +#endif /* CONFIG_UTHREAD */ +#endif /* _UTHREAD_H_ */ diff --git a/include/video.h b/include/video.h index a1f7fd7e839..2fe2f73a865 100644 --- a/include/video.h +++ b/include/video.h @@ -85,6 +85,11 @@ enum video_format { * @fb_size: Frame buffer size * @copy_fb: Copy of the frame buffer to keep up to date; see struct * video_uc_plat + * @damage: A bounding box of framebuffer regions updated since last sync + * @damage.xstart: X start position in pixels from the left + * @damage.ystart: Y start position in pixels from the top + * @damage.xend: X end position in pixels from the left + * @damage.xend: Y end position in pixels from the top * @line_length: Length of each frame buffer line, in bytes. This can be * set by the driver, but if not, the uclass will set it after * probing @@ -113,6 +118,12 @@ struct video_priv { void *fb; int fb_size; void *copy_fb; + struct { + int xstart; + int ystart; + int xend; + int yend; + } damage; int line_length; u32 colour_fg; u32 colour_bg; @@ -259,8 +270,9 @@ int video_fill_part(struct udevice *dev, int xstart, int ystart, int xend, * @return: 0 on success, error code otherwise * * Some frame buffers are cached or have a secondary frame buffer. This - * function syncs these up so that the current contents of the U-Boot frame - * buffer are displayed to the user. + * function syncs the damaged parts of them up so that the current contents + * of the U-Boot frame buffer are displayed to the user. It clears the damage + * buffer. */ int video_sync(struct udevice *vid, bool force); @@ -343,42 +355,29 @@ void video_set_default_colors(struct udevice *dev, bool invert); */ int video_default_font_height(struct udevice *dev); -#ifdef CONFIG_VIDEO_COPY +#ifdef CONFIG_VIDEO_DAMAGE /** - * vidconsole_sync_copy() - Sync back to the copy framebuffer + * video_damage() - Notify the video subsystem about screen updates. * - * This ensures that the copy framebuffer has the same data as the framebuffer - * for a particular region. It should be called after the framebuffer is updated - * - * @from and @to can be in either order. The region between them is synced. - * - * @dev: Vidconsole device being updated - * @from: Start/end address within the framebuffer (->fb) - * @to: Other address within the frame buffer - * Return: 0 if OK, -EFAULT if the start address is before the start of the - * frame buffer start - */ -int video_sync_copy(struct udevice *dev, void *from, void *to); - -/** - * video_sync_copy_all() - Sync the entire framebuffer to the copy + * @vid: Device to sync + * @x: Upper left X coordinate of the damaged rectangle + * @y: Upper left Y coordinate of the damaged rectangle + * @width: Width of the damaged rectangle + * @height: Height of the damaged rectangle * - * @dev: Vidconsole device being updated - * Return: 0 (always) + * Some frame buffers are cached or have a secondary frame buffer. This + * function notifies the video subsystem about rectangles that were updated + * within the frame buffer. They may only get written to the screen on the + * next call to video_sync(). */ -int video_sync_copy_all(struct udevice *dev); +void video_damage(struct udevice *vid, int x, int y, int width, int height); #else -static inline int video_sync_copy(struct udevice *dev, void *from, void *to) -{ - return 0; -} - -static inline int video_sync_copy_all(struct udevice *dev) +static inline void video_damage(struct udevice *vid, int x, int y, int width, + int height) { - return 0; + return; } - -#endif +#endif /* CONFIG_VIDEO_DAMAGE */ /** * video_is_active() - Test if one video device it active diff --git a/include/video_console.h b/include/video_console.h index 723d2315606..13197fa4518 100644 --- a/include/video_console.h +++ b/include/video_console.h @@ -537,56 +537,4 @@ void vidconsole_list_fonts(struct udevice *dev); */ int vidconsole_get_font_size(struct udevice *dev, const char **name, uint *sizep); -#ifdef CONFIG_VIDEO_COPY -/** - * vidconsole_sync_copy() - Sync back to the copy framebuffer - * - * This ensures that the copy framebuffer has the same data as the framebuffer - * for a particular region. It should be called after the framebuffer is updated - * - * @from and @to can be in either order. The region between them is synced. - * - * @dev: Vidconsole device being updated - * @from: Start/end address within the framebuffer (->fb) - * @to: Other address within the frame buffer - * Return: 0 if OK, -EFAULT if the start address is before the start of the - * frame buffer start - */ -int vidconsole_sync_copy(struct udevice *dev, void *from, void *to); - -/** - * vidconsole_memmove() - Perform a memmove() within the frame buffer - * - * This handles a memmove(), e.g. for scrolling. It also updates the copy - * framebuffer. - * - * @dev: Vidconsole device being updated - * @dst: Destination address within the framebuffer (->fb) - * @src: Source address within the framebuffer (->fb) - * @size: Number of bytes to transfer - * Return: 0 if OK, -EFAULT if the start address is before the start of the - * frame buffer start - */ -int vidconsole_memmove(struct udevice *dev, void *dst, const void *src, - int size); -#else - -#include <string.h> - -static inline int vidconsole_sync_copy(struct udevice *dev, void *from, - void *to) -{ - return 0; -} - -static inline int vidconsole_memmove(struct udevice *dev, void *dst, - const void *src, int size) -{ - memmove(dst, src, size); - - return 0; -} - -#endif - #endif diff --git a/include/xilinx.h b/include/xilinx.h index e4e29797988..c54d6dc1453 100644 --- a/include/xilinx.h +++ b/include/xilinx.h @@ -34,6 +34,8 @@ typedef enum { /* typedef xilinx_family */ xilinx_zynq, /* Zynq Family */ xilinx_zynqmp, /* ZynqMP Family */ xilinx_versal, /* Versal Family */ + xilinx_versal_net, /* Versal NET Family */ + xilinx_versal2, /* Versal Gen 2 Family */ max_xilinx_type /* insert all new types before this */ } xilinx_family; /* end, typedef xilinx_family */ diff --git a/include/zynqmp_firmware.h b/include/zynqmp_firmware.h index 73198a6a6ea..dc06abc52fc 100644 --- a/include/zynqmp_firmware.h +++ b/include/zynqmp_firmware.h @@ -457,6 +457,12 @@ int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id); int zynqmp_mmio_read(const u32 address, u32 *value); int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value); int zynqmp_pm_feature(const u32 api_id); +u32 zynqmp_pm_get_bootmode_reg(void); +int zynqmp_pm_ufs_get_txrx_cfgrdy(u32 *value); +int zynqmp_pm_ufs_sram_csr_read(u32 *value); +int zynqmp_pm_ufs_sram_csr_write(u32 *value); +int zynqmp_pm_ufs_cal_reg(u32 *value); +u32 zynqmp_pm_get_pmc_multi_boot_reg(void); /* Type of Config Object */ #define PM_CONFIG_OBJECT_TYPE_BASE 0x1U @@ -500,4 +506,10 @@ struct zynqmp_ipi_msg { u32 *buf; }; +#define CRP_BOOT_MODE_REG_NODE 0x30000001 +#define CRP_BOOT_MODE_REG_OFFSET 0x200 + +#define PM_REG_PMC_GLOBAL_NODE 0x30000004 +#define PMC_MULTI_BOOT_MODE_REG_OFFSET 0x4 + #endif /* _ZYNQMP_FIRMWARE_H_ */ |