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-rw-r--r--include/configs/mt7621.h43
-rw-r--r--include/configs/stm32mp13_st_common.h5
-rw-r--r--include/configs/stm32mp15_st_common.h3
-rw-r--r--include/dt-bindings/clock/mt7621-clk.h46
-rw-r--r--include/dt-bindings/clock/stm32fx-clock.h4
-rw-r--r--include/dt-bindings/clock/stm32mp1-clks.h23
-rw-r--r--include/dt-bindings/pinctrl/stm32-pinfunc.h1
-rw-r--r--include/dt-bindings/reset/mt7621-reset.h38
-rw-r--r--include/dt-bindings/reset/stm32mp1-resets.h14
-rw-r--r--include/efi_loader.h3
10 files changed, 177 insertions, 3 deletions
diff --git a/include/configs/mt7621.h b/include/configs/mt7621.h
new file mode 100644
index 00000000000..1f689970803
--- /dev/null
+++ b/include/configs/mt7621.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2022 MediaTek Inc. All rights reserved.
+ *
+ * Author: Weijie Gao <weijie.gao@mediatek.com>
+ */
+
+#ifndef __CONFIG_MT7621_H
+#define __CONFIG_MT7621_H
+
+#define CONFIG_SYS_MIPS_TIMER_FREQ 440000000
+
+#define CONFIG_SYS_SDRAM_BASE 0x80000000
+
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_MAX_MEM_MAPPED 0x1c000000
+
+#define CONFIG_SYS_INIT_SP_OFFSET 0x800000
+
+#define CONFIG_SYS_NONCACHED_MEMORY 0x100000
+
+/* MMC */
+#define MMC_SUPPORTS_TUNING
+
+/* NAND */
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+
+/* Serial SPL */
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL)
+#define CONFIG_SYS_NS16550_MEM32
+#define CONFIG_SYS_NS16550_CLK 50000000
+#define CONFIG_SYS_NS16550_REG_SIZE -4
+#define CONFIG_SYS_NS16550_COM1 0xbe000c00
+#endif
+
+/* Serial common */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
+ 230400, 460800, 921600 }
+
+/* Dummy value */
+#define CONFIG_SYS_UBOOT_BASE 0
+
+#endif /* __CONFIG_MT7621_H */
diff --git a/include/configs/stm32mp13_st_common.h b/include/configs/stm32mp13_st_common.h
index ec64b12f7ab..c51022b40d2 100644
--- a/include/configs/stm32mp13_st_common.h
+++ b/include/configs/stm32mp13_st_common.h
@@ -14,4 +14,9 @@
#include <configs/stm32mp13_common.h>
+/* uart with on-board st-link */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
+ 230400, 460800, 921600, \
+ 1000000, 2000000, 4000000}
+
#endif
diff --git a/include/configs/stm32mp15_st_common.h b/include/configs/stm32mp15_st_common.h
index 37b216e6e9f..6bdc286cfca 100644
--- a/include/configs/stm32mp15_st_common.h
+++ b/include/configs/stm32mp15_st_common.h
@@ -48,7 +48,8 @@
ST_STM32MP1_BOOTCMD \
STM32MP_PARTS_DEFAULT \
BOOTENV \
- STM32MP_EXTRA
+ STM32MP_EXTRA \
+ STM32MP_BOARD_EXTRA_ENV
#endif
#endif
diff --git a/include/dt-bindings/clock/mt7621-clk.h b/include/dt-bindings/clock/mt7621-clk.h
new file mode 100644
index 00000000000..978c67951ba
--- /dev/null
+++ b/include/dt-bindings/clock/mt7621-clk.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2022 MediaTek Inc. All rights reserved.
+ *
+ * Author: Weijie Gao <weijie.gao@mediatek.com>
+ */
+
+#ifndef _DT_BINDINGS_MT7621_CLK_H_
+#define _DT_BINDINGS_MT7621_CLK_H_
+
+#define MT7621_CLK_XTAL 0
+#define MT7621_CLK_CPU 1
+#define MT7621_CLK_BUS 2
+#define MT7621_CLK_50M 3
+#define MT7621_CLK_125M 4
+#define MT7621_CLK_150M 5
+#define MT7621_CLK_250M 6
+#define MT7621_CLK_270M 7
+
+#define MT7621_CLK_HSDMA 8
+#define MT7621_CLK_FE 9
+#define MT7621_CLK_SP_DIVTX 10
+#define MT7621_CLK_TIMER 11
+#define MT7621_CLK_PCM 12
+#define MT7621_CLK_PIO 13
+#define MT7621_CLK_GDMA 14
+#define MT7621_CLK_NAND 15
+#define MT7621_CLK_I2C 16
+#define MT7621_CLK_I2S 17
+#define MT7621_CLK_SPI 18
+#define MT7621_CLK_UART1 19
+#define MT7621_CLK_UART2 20
+#define MT7621_CLK_UART3 21
+#define MT7621_CLK_ETH 22
+#define MT7621_CLK_PCIE0 23
+#define MT7621_CLK_PCIE1 24
+#define MT7621_CLK_PCIE2 25
+#define MT7621_CLK_CRYPTO 26
+#define MT7621_CLK_SHXC 27
+
+#define MT7621_CLK_MAX 28
+
+/* for u-boot only */
+#define MT7621_CLK_DDR 29
+
+#endif /* _DT_BINDINGS_MT7621_CLK_H_ */
diff --git a/include/dt-bindings/clock/stm32fx-clock.h b/include/dt-bindings/clock/stm32fx-clock.h
index 1cc89c54857..e5dad050d51 100644
--- a/include/dt-bindings/clock/stm32fx-clock.h
+++ b/include/dt-bindings/clock/stm32fx-clock.h
@@ -7,10 +7,10 @@
*/
/*
- * List of clocks wich are not derived from system clock (SYSCLOCK)
+ * List of clocks which are not derived from system clock (SYSCLOCK)
*
* The index of these clocks is the secondary index of DT bindings
- * (see Documentatoin/devicetree/bindings/clock/st,stm32-rcc.txt)
+ * (see Documentation/devicetree/bindings/clock/st,stm32-rcc.txt)
*
* e.g:
<assigned-clocks = <&rcc 1 CLK_LSE>;
diff --git a/include/dt-bindings/clock/stm32mp1-clks.h b/include/dt-bindings/clock/stm32mp1-clks.h
index 4cdaf135829..25e8cfd4345 100644
--- a/include/dt-bindings/clock/stm32mp1-clks.h
+++ b/include/dt-bindings/clock/stm32mp1-clks.h
@@ -248,4 +248,27 @@
#define STM32MP1_LAST_CLK 232
+/* SCMI clock identifiers */
+#define CK_SCMI_HSE 0
+#define CK_SCMI_HSI 1
+#define CK_SCMI_CSI 2
+#define CK_SCMI_LSE 3
+#define CK_SCMI_LSI 4
+#define CK_SCMI_PLL2_Q 5
+#define CK_SCMI_PLL2_R 6
+#define CK_SCMI_MPU 7
+#define CK_SCMI_AXI 8
+#define CK_SCMI_BSEC 9
+#define CK_SCMI_CRYP1 10
+#define CK_SCMI_GPIOZ 11
+#define CK_SCMI_HASH1 12
+#define CK_SCMI_I2C4 13
+#define CK_SCMI_I2C6 14
+#define CK_SCMI_IWDG1 15
+#define CK_SCMI_RNG1 16
+#define CK_SCMI_RTC 17
+#define CK_SCMI_RTCAPB 18
+#define CK_SCMI_SPI6 19
+#define CK_SCMI_USART1 20
+
#endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */
diff --git a/include/dt-bindings/pinctrl/stm32-pinfunc.h b/include/dt-bindings/pinctrl/stm32-pinfunc.h
index e6e07807894..e6fb8ada3f4 100644
--- a/include/dt-bindings/pinctrl/stm32-pinfunc.h
+++ b/include/dt-bindings/pinctrl/stm32-pinfunc.h
@@ -39,3 +39,4 @@
#define STM32MP_PKG_AD 0x8
#endif /* _DT_BINDINGS_STM32_PINFUNC_H */
+
diff --git a/include/dt-bindings/reset/mt7621-reset.h b/include/dt-bindings/reset/mt7621-reset.h
new file mode 100644
index 00000000000..8e4341f0407
--- /dev/null
+++ b/include/dt-bindings/reset/mt7621-reset.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2022 MediaTek Inc. All rights reserved.
+ *
+ * Author: Weijie Gao <weijie.gao@mediatek.com>
+ */
+
+#ifndef _DT_BINDINGS_MT7621_RESET_H_
+#define _DT_BINDINGS_MT7621_RESET_H_
+
+#define RST_PPE 31
+#define RST_SDXC 30
+#define RST_CRYPTO 29
+#define RST_AUX_STCK 28
+#define RST_PCIE2 26
+#define RST_PCIE1 25
+#define RST_PCIE0 24
+#define RST_GMAC 23
+#define RST_UART3 21
+#define RST_UART2 20
+#define RST_UART1 19
+#define RST_SPI 18
+#define RST_I2S 17
+#define RST_I2C 16
+#define RST_NFI 15
+#define RST_GDMA 14
+#define RST_PIO 13
+#define RST_PCM 11
+#define RST_MC 10
+#define RST_INTC 9
+#define RST_TIMER 8
+#define RST_SPDIFTX 7
+#define RST_FE 6
+#define RST_HSDMA 5
+#define RST_MCM 2
+#define RST_SYS 0
+
+#endif /* _DT_BINDINGS_MT7621_RESET_H_ */
diff --git a/include/dt-bindings/reset/stm32mp1-resets.h b/include/dt-bindings/reset/stm32mp1-resets.h
index 702da37a2e8..4ffa7c3612e 100644
--- a/include/dt-bindings/reset/stm32mp1-resets.h
+++ b/include/dt-bindings/reset/stm32mp1-resets.h
@@ -106,4 +106,18 @@
#define GPIOJ_R 19785
#define GPIOK_R 19786
+/* SCMI reset domain identifiers */
+#define RST_SCMI_SPI6 0
+#define RST_SCMI_I2C4 1
+#define RST_SCMI_I2C6 2
+#define RST_SCMI_USART1 3
+#define RST_SCMI_STGEN 4
+#define RST_SCMI_GPIOZ 5
+#define RST_SCMI_CRYP1 6
+#define RST_SCMI_HASH1 7
+#define RST_SCMI_RNG1 8
+#define RST_SCMI_MDMA 9
+#define RST_SCMI_MCU 10
+#define RST_SCMI_MCU_HOLD_BOOT 11
+
#endif /* _DT_BINDINGS_STM32MP1_RESET_H_ */
diff --git a/include/efi_loader.h b/include/efi_loader.h
index 5b41985244e..3a63a1f75fd 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -802,6 +802,9 @@ ssize_t efi_dp_check_length(const struct efi_device_path *dp,
(((_dp)->type == DEVICE_PATH_TYPE_##_type) && \
((_dp)->sub_type == DEVICE_PATH_SUB_TYPE_##_subtype))
+/* template END node: */
+extern const struct efi_device_path END;
+
/* Indicate supported runtime services */
efi_status_t efi_init_runtime_supported(void);
generated by cgit v1.2.3 (git 2.0.4) at 2025-10-13 15:04:09 +0000