diff options
Diffstat (limited to 'include')
95 files changed, 1471 insertions, 2284 deletions
diff --git a/include/asm-generic/sections.h b/include/asm-generic/sections.h index b6bca53db10..024b1adde27 100644 --- a/include/asm-generic/sections.h +++ b/include/asm-generic/sections.h @@ -23,6 +23,7 @@ extern char __kprobes_text_start[], __kprobes_text_end[]; extern char __entry_text_start[], __entry_text_end[]; extern char __initdata_begin[], __initdata_end[]; extern char __start_rodata[], __end_rodata[]; +extern char __start_data[], __end_data[]; extern char __efi_helloworld_begin[]; extern char __efi_helloworld_end[]; extern char __efi_var_file_begin[]; @@ -63,10 +64,14 @@ static inline int arch_is_kernel_data(unsigned long addr) /* Start of U-Boot text region */ extern char __text_start[]; +extern char __text_end[]; /* This marks the text region which must be relocated */ extern char __image_copy_start[], __image_copy_end[]; +/* This marks the rcode region used for SPL relocation */ +extern char _rcode_start[], _rcode_end[]; + extern char __bss_end[]; extern char __rel_dyn_start[], __rel_dyn_end[]; extern char _image_binary_end[]; @@ -77,4 +82,17 @@ extern char _image_binary_end[]; */ extern void _start(void); +#ifndef USE_HOSTCC +#if CONFIG_IS_ENABLED(RELOC_LOADER) +#define __rcode __section(".text.rcode") +#define __rdata __section(".text.rdata") +#else +#define __rcode +#define __rdata +#endif +#else +#define __rcode +#define __rdata +#endif + #endif /* _ASM_GENERIC_SECTIONS_H_ */ diff --git a/include/bloblist.h b/include/bloblist.h index 414fb9b6e40..f32faf78560 100644 --- a/include/bloblist.h +++ b/include/bloblist.h @@ -250,6 +250,24 @@ static inline void *bloblist_check_magic(ulong addr) return ptr; } +#if CONFIG_IS_ENABLED(BLOBLIST) +/** + * bloblist_get_blob() - Find a blob and get the size of it + * + * Searches the bloblist and returns the blob with the matching tag + * + * @tag: Tag to search for (enum bloblist_tag_t) + * @sizep: Size of the blob found + * Return: pointer to bloblist if found, or NULL if not found + */ +void *bloblist_get_blob(uint tag, int *sizep); +#else +static inline void *bloblist_get_blob(uint tag, int *sizep) +{ + return NULL; +} +#endif + /** * bloblist_find() - Find a blob * diff --git a/include/cadence-nand.h b/include/cadence-nand.h new file mode 100644 index 00000000000..27ed217b1ed --- /dev/null +++ b/include/cadence-nand.h @@ -0,0 +1,529 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Cadence NAND flash controller driver + * + * Copyright (C) 2019 Cadence + * + * Author: Piotr Sroka <piotrs@cadence.com> + * + */ + +#ifndef _CADENCE_NAND_H_ +#define _CADENCE_NAND_H_ +#include <clk.h> +#include <reset.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/rawnand.h> + +/* + * HPNFC can work in 3 modes: + * - PIO - can work in master or slave DMA + * - CDMA - needs Master DMA for accessing command descriptors. + * - Generic mode - can use only slave DMA. + * CDMA and PIO modes can be used to execute only base commands. + * CDMA and PIO modes can be used to execute only base commands. + * Generic mode can be used to execute any command + * on NAND flash memory. Driver uses CDMA mode for + * block erasing, page reading, page programing. + * Generic mode is used for executing rest of commands. + */ + +#define DMA_DATA_SIZE_ALIGN 8 + +/* Register definition. */ +/* + * Command register 0. + * Writing data to this register will initiate a new transaction + * of the NF controller. + */ +#define CMD_REG0 0x0000 +/* Command type field mask. */ +#define CMD_REG0_CT GENMASK(31, 30) +/* Command type CDMA. */ +#define CMD_REG0_CT_CDMA 0uL +/* Command type generic. */ +#define CMD_REG0_CT_GEN 3uL +/* Command thread number field mask. */ +#define CMD_REG0_TN GENMASK(27, 24) + +/* Command register 2. */ +#define CMD_REG2 0x0008 +/* Command register 3. */ +#define CMD_REG3 0x000C +/* Pointer register to select which thread status will be selected. */ +#define CMD_STATUS_PTR 0x0010 +/* Command status register for selected thread. */ +#define CMD_STATUS 0x0014 + +/* Interrupt status register. */ +#define INTR_STATUS 0x0110 +#define INTR_STATUS_SDMA_ERR BIT(22) +#define INTR_STATUS_SDMA_TRIGG BIT(21) +#define INTR_STATUS_UNSUPP_CMD BIT(19) +#define INTR_STATUS_DDMA_TERR BIT(18) +#define INTR_STATUS_CDMA_TERR BIT(17) +#define INTR_STATUS_CDMA_IDL BIT(16) + +/* Interrupt enable register. */ +#define INTR_ENABLE 0x0114 +#define INTR_ENABLE_INTR_EN BIT(31) + +/* Controller internal state. */ +#define CTRL_STATUS 0x0118 +#define CTRL_STATUS_INIT_COMP BIT(9) +#define CTRL_STATUS_CTRL_BUSY BIT(8) + +/* Command Engine threads state. */ +#define TRD_STATUS 0x0120 + +/* Command Engine interrupt thread error status. */ +#define TRD_ERR_INT_STATUS 0x0128 +/* Command Engine interrupt thread error enable. */ +#define TRD_ERR_INT_STATUS_EN 0x0130 +/* Command Engine interrupt thread complete status. */ +#define TRD_COMP_INT_STATUS 0x0138 + +/* + * Transfer config 0 register. + * Configures data transfer parameters. + */ +#define TRAN_CFG_0 0x0400 +/* Offset value from the beginning of the page. */ +#define TRAN_CFG_0_OFFSET GENMASK(31, 16) +/* Numbers of sectors to transfer within singlNF device's page. */ +#define TRAN_CFG_0_SEC_CNT GENMASK(7, 0) + +/* + * Transfer config 1 register. + * Configures data transfer parameters. + */ +#define TRAN_CFG_1 0x0404 +/* Size of last data sector. */ +#define TRAN_CFG_1_LAST_SEC_SIZE GENMASK(31, 16) +/* Size of not-last data sector. */ +#define TRAN_CFG_1_SECTOR_SIZE GENMASK(15, 0) + +/* ECC engine configuration register 0. */ +#define ECC_CONFIG_0 0x0428 +/* Correction strength. */ +#define ECC_CONFIG_0_CORR_STR GENMASK(10, 8) +/* Enable erased pages detection mechanism. */ +#define ECC_CONFIG_0_ERASE_DET_EN BIT(1) +/* Enable controller ECC check bits generation and correction. */ +#define ECC_CONFIG_0_ECC_EN BIT(0) + +/* ECC engine configuration register 1. */ +#define ECC_CONFIG_1 0x042C + +/* Multiplane settings register. */ +#define MULTIPLANE_CFG 0x0434 +/* Cache operation settings. */ +#define CACHE_CFG 0x0438 + +/* Transferred data block size for the slave DMA module. */ +#define SDMA_SIZE 0x0440 + +/* Thread number associated with transferred data block + * for the slave DMA module. + */ +#define SDMA_TRD_NUM 0x0444 +/* Thread number mask. */ +#define SDMA_TRD_NUM_SDMA_TRD GENMASK(2, 0) + +#define CONTROL_DATA_CTRL 0x0494 +/* Thread number mask. */ +#define CONTROL_DATA_CTRL_SIZE GENMASK(15, 0) + +#define CTRL_VERSION 0x800 +#define CTRL_VERSION_REV GENMASK(7, 0) + +/* Available hardware features of the controller. */ +#define CTRL_FEATURES 0x804 +/* Support for NV-DDR2/3 work mode. */ +#define CTRL_FEATURES_NVDDR_2_3 BIT(28) +/* Support for NV-DDR work mode. */ +#define CTRL_FEATURES_NVDDR BIT(27) +/* Support for asynchronous work mode. */ +#define CTRL_FEATURES_ASYNC BIT(26) +/* Support for asynchronous work mode. */ +#define CTRL_FEATURES_N_BANKS GENMASK(25, 24) +/* Slave and Master DMA data width. */ +#define CTRL_FEATURES_DMA_DWITH64 BIT(21) +/* Availability of Control Data feature.*/ +#define CTRL_FEATURES_CONTROL_DATA BIT(10) + +/* BCH Engine identification register 0 - correction strengths. */ +#define BCH_CFG_0 0x838 +#define BCH_CFG_0_CORR_CAP_0 GENMASK(7, 0) +#define BCH_CFG_0_CORR_CAP_1 GENMASK(15, 8) +#define BCH_CFG_0_CORR_CAP_2 GENMASK(23, 16) +#define BCH_CFG_0_CORR_CAP_3 GENMASK(31, 24) + +/* BCH Engine identification register 1 - correction strengths. */ +#define BCH_CFG_1 0x83C +#define BCH_CFG_1_CORR_CAP_4 GENMASK(7, 0) +#define BCH_CFG_1_CORR_CAP_5 GENMASK(15, 8) +#define BCH_CFG_1_CORR_CAP_6 GENMASK(23, 16) +#define BCH_CFG_1_CORR_CAP_7 GENMASK(31, 24) + +/* BCH Engine identification register 2 - sector sizes. */ +#define BCH_CFG_2 0x840 +#define BCH_CFG_2_SECT_0 GENMASK(15, 0) +#define BCH_CFG_2_SECT_1 GENMASK(31, 16) + +/* BCH Engine identification register 3. */ +#define BCH_CFG_3 0x844 +#define BCH_CFG_3_METADATA_SIZE GENMASK(23, 16) + +/* Ready/Busy# line status. */ +#define RBN_SETINGS 0x1004 + +/* Common settings. */ +#define COMMON_SET 0x1008 +/* 16 bit device connected to the NAND Flash interface. */ +#define COMMON_SET_DEVICE_16BIT BIT(8) + +/* Skip_bytes registers. */ +#define SKIP_BYTES_CONF 0x100C +#define SKIP_BYTES_MARKER_VALUE GENMASK(31, 16) +#define SKIP_BYTES_NUM_OF_BYTES GENMASK(7, 0) + +#define SKIP_BYTES_OFFSET 0x1010 +#define SKIP_BYTES_OFFSET_VALUE GENMASK(23, 0) + +/* Timings configuration. */ +#define ASYNC_TOGGLE_TIMINGS 0x101c +#define ASYNC_TOGGLE_TIMINGS_TRH GENMASK(28, 24) +#define ASYNC_TOGGLE_TIMINGS_TRP GENMASK(20, 16) +#define ASYNC_TOGGLE_TIMINGS_TWH GENMASK(12, 8) +#define ASYNC_TOGGLE_TIMINGS_TWP GENMASK(4, 0) + +#define TIMINGS0 0x1024 +#define TIMINGS0_TADL GENMASK(31, 24) +#define TIMINGS0_TCCS GENMASK(23, 16) +#define TIMINGS0_TWHR GENMASK(15, 8) +#define TIMINGS0_TRHW GENMASK(7, 0) + +#define TIMINGS1 0x1028 +#define TIMINGS1_TRHZ GENMASK(31, 24) +#define TIMINGS1_TWB GENMASK(23, 16) +#define TIMINGS1_TVDLY GENMASK(7, 0) + +#define TIMINGS2 0x102c +#define TIMINGS2_TFEAT GENMASK(25, 16) +#define TIMINGS2_CS_HOLD_TIME GENMASK(13, 8) +#define TIMINGS2_CS_SETUP_TIME GENMASK(5, 0) + +/* Configuration of the resynchronization of slave DLL of PHY. */ +#define DLL_PHY_CTRL 0x1034 +#define DLL_PHY_CTRL_DLL_RST_N BIT(24) +#define DLL_PHY_CTRL_EXTENDED_WR_MODE BIT(17) +#define DLL_PHY_CTRL_EXTENDED_RD_MODE BIT(16) +#define DLL_PHY_CTRL_RS_HIGH_WAIT_CNT GENMASK(11, 8) +#define DLL_PHY_CTRL_RS_IDLE_CNT GENMASK(7, 0) + +/* TODO: - Identify better way to handle PHY address */ +#define PHY_OFFSET 0x10000 + +/* Register controlling DQ related timing. */ +#define PHY_DQ_TIMING PHY_OFFSET + 0x2000 +/* Register controlling DSQ related timing. */ +#define PHY_DQS_TIMING PHY_OFFSET + 0x2004 +#define PHY_DQS_TIMING_DQS_SEL_OE_END GENMASK(3, 0) +#define PHY_DQS_TIMING_PHONY_DQS_SEL BIT(16) +#define PHY_DQS_TIMING_USE_PHONY_DQS BIT(20) + +/* Register controlling the gate and loopback control related timing. */ +#define PHY_GATE_LPBK_CTRL PHY_OFFSET + 0x2008 +#define PHY_GATE_LPBK_CTRL_RDS GENMASK(24, 19) + +/* Register holds the control for the master DLL logic. */ +#define PHY_DLL_MASTER_CTRL PHY_OFFSET + 0x200C +#define PHY_DLL_MASTER_CTRL_BYPASS_MODE BIT(23) + +/* Register holds the control for the slave DLL logic. */ +#define PHY_DLL_SLAVE_CTRL PHY_OFFSET + 0x2010 + +/* This register handles the global control settings for the PHY. */ +#define PHY_CTRL PHY_OFFSET + 0x2080 +#define PHY_CTRL_SDR_DQS BIT(14) +#define PHY_CTRL_PHONY_DQS GENMASK(9, 4) + +/* + * This register handles the global control settings + * for the termination selects for reads. + */ +#define PHY_TSEL PHY_OFFSET + 0x2084 + +/* Generic command layout. */ +#define GCMD_LAY_CS GENMASK_ULL(11, 8) +/* + * This bit informs the minicotroller if it has to wait for tWB + * after sending the last CMD/ADDR/DATA in the sequence. + */ +#define GCMD_LAY_TWB BIT_ULL(6) +/* Type of generic instruction. */ +#define GCMD_LAY_INSTR GENMASK_ULL(5, 0) + +/* Generic CMD sequence type. */ +#define GCMD_LAY_INSTR_CMD 0 +/* Generic ADDR sequence type. */ +#define GCMD_LAY_INSTR_ADDR 1 +/* Generic data transfer sequence type. */ +#define GCMD_LAY_INSTR_DATA 2 + +/* Input part of generic command type of input is command. */ +#define GCMD_LAY_INPUT_CMD GENMASK_ULL(23, 16) + +/* Generic command address sequence - address fields. */ +#define GCMD_LAY_INPUT_ADDR GENMASK_ULL(63, 16) +/* Generic command address sequence - address size. */ +#define GCMD_LAY_INPUT_ADDR_SIZE GENMASK_ULL(13, 11) + +/* Transfer direction field of generic command data sequence. */ +#define GCMD_DIR BIT_ULL(11) +/* Read transfer direction of generic command data sequence. */ +#define GCMD_DIR_READ 0 +/* Write transfer direction of generic command data sequence. */ +#define GCMD_DIR_WRITE 1 + +/* ECC enabled flag of generic command data sequence - ECC enabled. */ +#define GCMD_ECC_EN BIT_ULL(12) +/* Generic command data sequence - sector size. */ +#define GCMD_SECT_SIZE GENMASK_ULL(31, 16) +/* Generic command data sequence - sector count. */ +#define GCMD_SECT_CNT GENMASK_ULL(39, 32) +/* Generic command data sequence - last sector size. */ +#define GCMD_LAST_SIZE GENMASK_ULL(55, 40) + +/* CDMA descriptor fields. */ +/* Erase command type of CDMA descriptor. */ +#define CDMA_CT_ERASE 0x1000 +/* Program page command type of CDMA descriptor. */ +#define CDMA_CT_WR 0x2100 +/* Read page command type of CDMA descriptor. */ +#define CDMA_CT_RD 0x2200 + +/* Flash pointer memory shift. */ +#define CDMA_CFPTR_MEM_SHIFT 24 +/* Flash pointer memory mask. */ +#define CDMA_CFPTR_MEM GENMASK(26, 24) + +/* + * Command DMA descriptor flags. If set causes issue interrupt after + * the completion of descriptor processing. + */ +#define CDMA_CF_INT BIT(8) +/* + * Command DMA descriptor flags - the next descriptor + * address field is valid and descriptor processing should continue. + */ +#define CDMA_CF_CONT BIT(9) +/* DMA master flag of command DMA descriptor. */ +#define CDMA_CF_DMA_MASTER BIT(10) + +/* Operation complete status of command descriptor. */ +#define CDMA_CS_COMP BIT(15) +/* Operation complete status of command descriptor. */ +/* Command descriptor status - operation fail. */ +#define CDMA_CS_FAIL BIT(14) +/* Command descriptor status - page erased. */ +#define CDMA_CS_ERP BIT(11) +/* Command descriptor status - timeout occurred. */ +#define CDMA_CS_TOUT BIT(10) +/* + * Maximum amount of correction applied to one ECC sector. + * It is part of command descriptor status. + */ +#define CDMA_CS_MAXERR GENMASK(9, 2) +/* Command descriptor status - uncorrectable ECC error. */ +#define CDMA_CS_UNCE BIT(1) +/* Command descriptor status - descriptor error. */ +#define CDMA_CS_ERR BIT(0) + +/* Status of operation - OK. */ +#define STAT_OK 0 +/* Status of operation - FAIL. */ +#define STAT_FAIL 2 +/* Status of operation - uncorrectable ECC error. */ +#define STAT_ECC_UNCORR 3 +/* Status of operation - page erased. */ +#define STAT_ERASED 5 +/* Status of operation - correctable ECC error. */ +#define STAT_ECC_CORR 6 +/* Status of operation - unsuspected state. */ +#define STAT_UNKNOWN 7 +/* Status of operation - operation is not completed yet. */ +#define STAT_BUSY 0xFF + +#define BCH_MAX_NUM_CORR_CAPS 8 +#define BCH_MAX_NUM_SECTOR_SIZES 2 + +#define ONE_CYCLE 1 +#define TIMEOUT_US 1000000 + +struct cadence_nand_timings { + u32 async_toggle_timings; + u32 timings0; + u32 timings1; + u32 timings2; + u32 dll_phy_ctrl; + u32 phy_ctrl; + u32 phy_dqs_timing; + u32 phy_gate_lpbk_ctrl; +}; + +/* Command DMA descriptor. */ +struct cadence_nand_cdma_desc { + /* Next descriptor address. */ + u64 next_pointer; + + /* Flash address is a 32-bit address comprising of BANK and ROW ADDR. */ + u32 flash_pointer; + /*field appears in HPNFC version 13*/ + u16 bank; + u16 rsvd0; + + /* Operation the controller needs to perform. */ + u16 command_type; + u16 rsvd1; + /* Flags for operation of this command. */ + u16 command_flags; + u16 rsvd2; + + /* System/host memory address required for data DMA commands. */ + u64 memory_pointer; + + /* Status of operation. */ + u32 status; + u32 rsvd3; + + /* Address pointer to sync buffer location. */ + u64 sync_flag_pointer; + + /* Controls the buffer sync mechanism. */ + u32 sync_arguments; + u32 rsvd4; + + /* Control data pointer. */ + u64 ctrl_data_ptr; +}; + +/* Interrupt status. */ +struct cadence_nand_irq_status { + /* Thread operation complete status. */ + u32 trd_status; + /* Thread operation error. */ + u32 trd_error; + /* Controller status. */ + u32 status; +}; + +/* Cadence NAND flash controller capabilities get from driver data. */ +struct cadence_nand_dt_devdata { + /* Skew value of the output signals of the NAND Flash interface. */ + u32 if_skew; + /* It informs if slave DMA interface is connected to DMA engine. */ + unsigned int has_dma:1; +}; + +/* Cadence NAND flash controller capabilities read from registers. */ +struct cdns_nand_caps { + /* Maximum number of banks supported by hardware. */ + u8 max_banks; + /* Slave and Master DMA data width in bytes (4 or 8). */ + u8 data_dma_width; + /* Control Data feature supported. */ + bool data_control_supp; + /* Is PHY type DLL. */ + bool is_phy_type_dll; +}; + +struct cadence_nand_info { + struct nand_hw_control controller; + struct udevice *dev; + struct reset_ctl softphy_reset; + struct reset_ctl nand_reset; + struct cadence_nand_cdma_desc *cdma_desc; + /* IP capability. */ + const struct cadence_nand_dt_devdata *caps1; + struct cdns_nand_caps caps2; + u8 ctrl_rev; + dma_addr_t dma_cdma_desc; + /* command interface buffers */ + u8 *buf; + u32 buf_size; + u8 *stat; + u8 cmd; + u32 buf_index; + + u8 curr_corr_str_idx; + + /* Register interface. */ + void __iomem *reg; + + struct { + void __iomem *virt; + dma_addr_t dma; + } io; + + int irq; + /* Interrupts that have happened. */ + struct cadence_nand_irq_status irq_status; + /* Interrupts we are waiting for. */ + struct cadence_nand_irq_status irq_mask; + + int ecc_strengths[BCH_MAX_NUM_CORR_CAPS]; + struct nand_ecc_step_info ecc_stepinfos[BCH_MAX_NUM_SECTOR_SIZES]; + struct nand_ecc_caps ecc_caps; + + int curr_trans_type; + + struct clk clk; + u32 nf_clk_rate; + /* + * Estimated Board delay. The value includes the total + * round trip delay for the signals and is used for deciding on values + * associated with data read capture. + */ + u32 board_delay; + + struct nand_chip *selected_chip; + + unsigned long assigned_cs; + struct list_head chips; + u8 bch_metadata_size; +}; + +struct cdns_nand_chip { + struct cadence_nand_timings timings; + struct nand_chip chip; + u8 nsels; + struct list_head node; + + /* + * part of oob area of NAND flash memory page. + * This part is available for user to read or write. + */ + u32 avail_oob_size; + + /* Sector size. There are few sectors per mtd->writesize */ + u32 sector_size; + u32 sector_count; + + /* Offset of BBM. */ + u8 bbm_offs; + /* Number of bytes reserved for BBM. */ + u8 bbm_len; + /* ECC strength index. */ + u8 corr_str_idx; + + u8 cs[]; +}; + +struct ecc_info { + int (*calc_ecc_bytes)(int step_size, int strength); + int max_step_size; +}; + +#endif /*_CADENCE_NAND_H_*/ diff --git a/include/configs/am335x_guardian.h b/include/configs/am335x_guardian.h index 96efd38594a..385dec2ff4f 100644 --- a/include/configs/am335x_guardian.h +++ b/include/configs/am335x_guardian.h @@ -63,11 +63,6 @@ "fi; " \ "setenv extrabootargs $extrabootargs \"swi_attached\"; " \ "fi;" \ - "run bootcmd_ubifs0;\0" \ - "altbootcmd=" \ - "setenv boot_syslinux_conf \"extlinux/extlinux-rollback.conf\"; " \ - "run distro_bootcmd; " \ - "setenv boot_syslinux_conf \"extlinux/extlinux.conf\"; " \ "run bootcmd_ubifs0;\0" #endif /* ! CONFIG_XPL_BUILD */ diff --git a/include/configs/beagley_ai.h b/include/configs/beagley_ai.h new file mode 100644 index 00000000000..a7072a094c5 --- /dev/null +++ b/include/configs/beagley_ai.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration header file for BeagleY-AI + * + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef __CONFIG_BEAGLEY_AI_H +#define __CONFIG_BEAGLEY_AI_H + +/* Now for the remaining common defines */ +#include <configs/ti_armv7_common.h> + +#endif /* __CONFIG_BEAGLEY_AI_H */ diff --git a/include/configs/bk4r1.h b/include/configs/bk4r1.h index 5df8d03c706..6d24c5decd5 100644 --- a/include/configs/bk4r1.h +++ b/include/configs/bk4r1.h @@ -16,8 +16,6 @@ #define BK4_EXTRA_ENV_SETTINGS \ "bootlimit=3\0" \ "eraseuserdata=false\0" \ - "altbootcmd=led 5 on; " \ - "boot\0" \ "set_gpio103=mw 0x400ff0c4 0x0080; mw 0x4004819C 0x000011bf\0" \ "set_gpio102=mw 0x400ff0c4 0x40; mw 0x40048198 0x000011bf\0" \ "set_gpio96=mw 0x40048180 0x282; mw 0x400ff0c4 0x1\0"\ diff --git a/include/configs/brppt2.h b/include/configs/brppt2.h index d01f0d37316..93559a171ae 100644 --- a/include/configs/brppt2.h +++ b/include/configs/brppt2.h @@ -64,7 +64,6 @@ BUR_COMMON_ENV \ " do echo \"### booting ${target} ###\"; run b_${target};" \ " if test ${b_break} = 1; then; exit; fi; done\0" \ "loaddev=mmc 0\0" \ -"altbootcmd=setenv b_mode 0; run b_default;\0" \ "bootlimit=1\0" \ "net2nor=sf probe && dhcp &&" \ " tftp ${loadaddr} SPL && sf erase 0 +${filesize} &&" \ diff --git a/include/configs/display5.h b/include/configs/display5.h index 51fa2b03a2e..98b1e5af2c0 100644 --- a/include/configs/display5.h +++ b/include/configs/display5.h @@ -170,7 +170,6 @@ "display=tianma-tm070-800x480\0" \ "board=display5\0" \ "mmcdev=0\0" \ - "altbootcmd=run recovery\0" \ "bootdelay=1\0" \ "baudrate=115200\0" \ "ethact=FEC\0" \ diff --git a/include/configs/ge_b1x5v2.h b/include/configs/ge_b1x5v2.h index f3d85c9c11e..5e3f67124c0 100644 --- a/include/configs/ge_b1x5v2.h +++ b/include/configs/ge_b1x5v2.h @@ -82,14 +82,6 @@ "doboot=" \ "echo Booting from mmc:${mmcdev}:${mmcpart} ...; " \ "run helix;\0" \ - "altbootcmd=" \ - "setenv mmcpart 1; run hasfirstboot || setenv mmcpart 2; " \ - "run hasfirstboot || setenv mmcpart 0; " \ - "if test ${mmcpart} != 0; then " \ - "setenv bootcause REVERT; " \ - "run swappartitions loadimage doboot; " \ - "fi; " \ - "run failbootcmd\0" \ "tryboot=" \ "setenv mmcpart 1; run hasfirstboot || setenv mmcpart 2; " \ "run loadimage || run swappartitions && run loadimage || " \ diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index 07b36706e56..c8ef048bd43 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -67,14 +67,6 @@ "Try again, or contact GE Service for support.\"; " \ "bootcount reset; " \ "while true; do sleep 1; done; \0" \ - "altbootcmd=" \ - "run doquiet; " \ - "setenv partnum 1; run hasfirstboot || setenv partnum 2; " \ - "run hasfirstboot || setenv partnum 0; " \ - "if test ${partnum} != 0; then " \ - "run swappartitions loadimage doboot; " \ - "fi; " \ - "run failbootcmd\0" \ "loadimage=" \ "ext2load ${dev} ${devnum}:${partnum} ${loadaddr} ${image}\0" \ "doboot=" \ diff --git a/include/configs/imx6-engicam.h b/include/configs/imx6-engicam.h index 786b70fe064..3d5701c636c 100644 --- a/include/configs/imx6-engicam.h +++ b/include/configs/imx6-engicam.h @@ -47,7 +47,6 @@ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ "loadfit=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${fit_image}\0" \ - "altbootcmd=run recoveryboot\0"\ "fitboot=echo Booting FIT image from mmc ...; " \ "run mmcargs; " \ "bootm ${loadaddr}\0" \ diff --git a/include/configs/imx6q-bosch-acc.h b/include/configs/imx6q-bosch-acc.h index 64ddbf711d3..84da8250684 100644 --- a/include/configs/imx6q-bosch-acc.h +++ b/include/configs/imx6q-bosch-acc.h @@ -42,8 +42,7 @@ "env_persisted=0\0" \ "env_persist=if test ${env_persisted} != 1; " \ "then env set env_persisted 1; run save_env; fi;\0" \ - "save_env=env save; env save\0" \ - "altbootcmd=run handle_ustate; run switch_bootset; run save_env; run bootcmd\0" + "save_env=env save; env save\0" #define CFG_ENV_FLAGS_LIST_STATIC \ "bootset:bw," \ diff --git a/include/configs/imx8mm-mx8menlo.h b/include/configs/imx8mm-mx8menlo.h index 7058d632d67..626ccae7205 100644 --- a/include/configs/imx8mm-mx8menlo.h +++ b/include/configs/imx8mm-mx8menlo.h @@ -18,14 +18,6 @@ "devtype=mmc\0" \ "devnum=1\0" \ "distro_bootpart=1\0" \ - "altbootcmd=" \ - "mmc partconf 0 mmcpart ; " \ - "if test ${mmcpart} -eq 1 ; then " \ - "mmc partconf 0 1 2 0 ; " \ - "else " \ - "mmc partconf 0 1 1 0 ; " \ - "fi ; " \ - "boot\0" \ "boot_file=fitImage\0" \ "console=ttymxc0\0" \ "fdt_addr=0x43000000\0" \ diff --git a/include/configs/imx8mm_data_modul_edm_sbc.h b/include/configs/imx8mm_data_modul_edm_sbc.h index 57ecb5e2190..5ce4219912f 100644 --- a/include/configs/imx8mm_data_modul_edm_sbc.h +++ b/include/configs/imx8mm_data_modul_edm_sbc.h @@ -34,7 +34,6 @@ #define CFG_SYS_FSL_ESDHC_ADDR 0 #define CFG_EXTRA_ENV_SETTINGS \ - "altbootcmd=run bootcmd\0" \ "bootlimit=3\0" \ "devtype=mmc\0" \ "devpart=1\0" \ diff --git a/include/configs/imx8mp_data_modul_edm_sbc.h b/include/configs/imx8mp_data_modul_edm_sbc.h index de5bdd30e18..58a03b35ac4 100644 --- a/include/configs/imx8mp_data_modul_edm_sbc.h +++ b/include/configs/imx8mp_data_modul_edm_sbc.h @@ -24,7 +24,6 @@ #define FEC_QUIRK_ENET_MAC #define CFG_EXTRA_ENV_SETTINGS \ - "altbootcmd=run bootcmd\0" \ "bootlimit=3\0" \ "devtype=mmc\0" \ "devpart=1\0" \ diff --git a/include/configs/imx8mp_dhcom_pdk2.h b/include/configs/imx8mp_dhcom_pdk2.h index c848fce8bda..f3e239d780f 100644 --- a/include/configs/imx8mp_dhcom_pdk2.h +++ b/include/configs/imx8mp_dhcom_pdk2.h @@ -28,7 +28,6 @@ #define CFG_SYS_FSL_ESDHC_ADDR 0 #define CFG_EXTRA_ENV_SETTINGS \ - "altbootcmd=run bootcmd ; reset\0" \ "bootlimit=3\0" \ "dfu_alt_info=" \ /* RAM block at DRAM offset 256..768 MiB */ \ diff --git a/include/configs/imxrt1020-evk.h b/include/configs/imxrt1020-evk.h index cd6af93454b..aec12082b95 100644 --- a/include/configs/imxrt1020-evk.h +++ b/include/configs/imxrt1020-evk.h @@ -9,8 +9,6 @@ #include <asm/arch/imx-regs.h> -#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 1 - #define PHYS_SDRAM 0x80000000 #define PHYS_SDRAM_SIZE (32 * 1024 * 1024) diff --git a/include/configs/imxrt1050-evk.h b/include/configs/imxrt1050-evk.h index c520c2fc203..5b8d6a7ac05 100644 --- a/include/configs/imxrt1050-evk.h +++ b/include/configs/imxrt1050-evk.h @@ -9,8 +9,6 @@ #include <asm/arch/imx-regs.h> -#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 1 - #define PHYS_SDRAM 0x80000000 #define PHYS_SDRAM_SIZE (32 * 1024 * 1024) diff --git a/include/configs/imxrt1170-evk.h b/include/configs/imxrt1170-evk.h index 1ccaa15bc11..f821212765c 100644 --- a/include/configs/imxrt1170-evk.h +++ b/include/configs/imxrt1170-evk.h @@ -10,8 +10,6 @@ #include <asm/arch/imx-regs.h> -#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 1 - /* * Configuration of the external SDRAM memory */ diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index 1ea4fa59fd5..a6aafb51854 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -93,13 +93,6 @@ "splashfile=boot/usplash.bmp.gz\0" \ "splashimage=0x88000000\0" \ "splashpos=m,m\0" \ - "altbootcmd=" \ - "if test ${mmcpart} -eq 1 ; then " \ - "setenv mmcpart 2 ; " \ - "else " \ - "setenv mmcpart 1 ; " \ - "fi ; " \ - "boot\0" \ "stdout=serial,vidconsole\0" \ "stderr=serial,vidconsole\0" \ "addcons=" \ diff --git a/include/configs/microchip_mpfs_icicle.h b/include/configs/microchip_mpfs_icicle.h index 5ced45b88b2..0077f6a5f95 100644 --- a/include/configs/microchip_mpfs_icicle.h +++ b/include/configs/microchip_mpfs_icicle.h @@ -26,6 +26,7 @@ "scriptaddr=0x88100000\0" \ "pxefile_addr_r=0x88200000\0" \ "ramdisk_addr_r=0x88300000\0" \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ BOOTENV #endif /* __CONFIG_H */ diff --git a/include/configs/mocha.h b/include/configs/mocha.h new file mode 100644 index 00000000000..1c2eb906085 --- /dev/null +++ b/include/configs/mocha.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + * + * Copyright (c) 2024, Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "tegra124-common.h" + +/* High-level configuration options */ +#define CFG_TEGRA_BOARD_STRING "Xiaomi Mocha" + +/* Board-specific serial config */ +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE + +#ifdef CONFIG_TEGRA_SUPPORT_NON_SECURE + #define CFG_PRAM 0x38400 /* 225 MB */ +#endif + +#include "tegra-common-post.h" + +#endif /* __CONFIG_H */ diff --git a/include/configs/mt7987.h b/include/configs/mt7987.h new file mode 100644 index 00000000000..18ed3c7a55b --- /dev/null +++ b/include/configs/mt7987.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Configuration for MediaTek MT7987 SoC + * + * Copyright (C) 2025 MediaTek Inc. + * Author: Sam Shih <sam.shih@mediatek.com> + */ + +#ifndef __MT7987_H +#define __MT7987_H + +#define CFG_MAX_MEM_MAPPED 0xC0000000 + +#endif diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h index 6d1f669de50..3707de254e1 100644 --- a/include/configs/mx53ppd.h +++ b/include/configs/mx53ppd.h @@ -59,14 +59,6 @@ "Try again, or contact GE Service for support.\"; " \ "bootcount reset; " \ "while true; do sleep 1; done; \0" \ - "altbootcmd=" \ - "run doquiet; " \ - "setenv partnum 1; run hasfirstboot || setenv partnum 2; " \ - "run hasfirstboot || setenv partnum 0; " \ - "if test ${partnum} != 0; then " \ - "run swappartitions loadimage doboot; " \ - "fi; " \ - "run failbootcmd\0" \ "loadimage=" \ "ext2load ${dev} ${devnum}:${partnum} ${loadaddr} ${image}\0" \ "doboot=" \ diff --git a/include/configs/openrd.h b/include/configs/openrd.h index 1e6b16b4e70..f91e62a2e47 100644 --- a/include/configs/openrd.h +++ b/include/configs/openrd.h @@ -15,22 +15,4 @@ #include "mv-common.h" -/* - * Environment variables configurations - */ -/* - * max 4k env size is enough, but in case of nand - * it has to be rounded to sector size - */ - -/* - * Default environment variables - */ - -#define CFG_EXTRA_ENV_SETTINGS "x_bootargs=console=ttyS0,115200 " \ - CONFIG_MTDPARTS_DEFAULT " rw ubi.mtd=2,2048\0" \ - "x_bootcmd_kernel=nand read 0x6400000 0x100000 0x300000\0" \ - "x_bootcmd_usb=usb start\0" \ - "x_bootargs_root=root=ubi0:rootfs rootfstype=ubifs\0" - #endif /* _CONFIG_OPENRD_BASE_H */ diff --git a/include/configs/phycore_am62ax.h b/include/configs/phycore_am62ax.h index 661ba8f73ca..4f612d2c2ce 100644 --- a/include/configs/phycore_am62ax.h +++ b/include/configs/phycore_am62ax.h @@ -12,4 +12,8 @@ /* DDR Configuration */ #define CFG_SYS_SDRAM_BASE 0x80000000 +#define PHYCORE_AM6XX_FW_NAME_TIBOOT3 u"PHYCORE_AM62AX_TIBOOT3" +#define PHYCORE_AM6XX_FW_NAME_SPL u"PHYCORE_AM62AX_SPL" +#define PHYCORE_AM6XX_FW_NAME_UBOOT u"PHYCORE_AM62AX_UBOOT" + #endif /* __PHYCORE_AM62AX_H */ diff --git a/include/configs/picasso.h b/include/configs/picasso.h new file mode 100644 index 00000000000..a58c7e5f353 --- /dev/null +++ b/include/configs/picasso.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation <www.nvidia.com> + * + * (C) Copyright 2024 + * Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "tegra20-common.h" + +/* High-level configuration options */ +#define CFG_TEGRA_BOARD_STRING "Acer Iconia Tab A500" + +/* Board-specific serial config */ +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE + +#include "tegra-common-post.h" + +#endif /* __CONFIG_H */ diff --git a/include/configs/pxa1908.h b/include/configs/pxa1908.h new file mode 100644 index 00000000000..b0d6cdfeb76 --- /dev/null +++ b/include/configs/pxa1908.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2024 + * Duje Mihanović <duje.mihanovic@skole.hr> + */ + +#ifndef __PXA1908_H +#define __PXA1908_H + +#define CFG_SYS_SDRAM_BASE 0x1000000 +#define CFG_SYS_INIT_RAM_ADDR 0x10000000 +#define CFG_SYS_INIT_RAM_SIZE 0x4000 +#define CFG_SYS_NS16550_IER 0x40 +#define CFG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 } +#define CFG_EXTRA_ENV_SETTINGS \ + "bootcmd=bootm $prevbl_initrd_start_addr\0" + +#endif diff --git a/include/configs/s4sk.h b/include/configs/s4sk.h new file mode 100644 index 00000000000..a1707359a39 --- /dev/null +++ b/include/configs/s4sk.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * This file is S4SK board configuration. + * + * Copyright (C) 2024-2025 Renesas Electronics Corp. + */ + +#ifndef __S4SK_H +#define __S4SK_H + +#include "rcar-gen4-common.h" + +#endif /* __S4SK_H */ diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index 2372485c84e..db2ac7f83bb 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -6,7 +6,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CFG_MALLOC_F_ADDR 0x0010000 +#define CFG_MALLOC_F_ADDR 0x000f4000 /* Size of our emulated memory */ #define SB_CONCAT(x, y) x ## y diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index 74b7fe85800..a918dc1350c 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -128,7 +128,6 @@ "verify=no \0" \ "project_dir=targetdir\0" \ "upgrade_available=0\0" \ - "altbootcmd=run bootcmd\0" \ "partitionset_active=A\0" \ "loadaddr=0x82000000\0" \ "kloadaddr=0x81000000\0" \ diff --git a/include/configs/siemens-env-common.h b/include/configs/siemens-env-common.h index 36fa5d936f7..c028823e1eb 100644 --- a/include/configs/siemens-env-common.h +++ b/include/configs/siemens-env-common.h @@ -183,7 +183,6 @@ "rootfs_name=/dev/mmcblk0\0" \ "upgrade_available=0\0" \ "bootlimit=3\0" \ - "altbootcmd=run bootcmd\0" \ "optargs=\0" \ /**********************************************************************/ diff --git a/include/configs/snapper9g45.h b/include/configs/snapper9g45.h index df8ed451a43..8ea708d0e92 100644 --- a/include/configs/snapper9g45.h +++ b/include/configs/snapper9g45.h @@ -58,8 +58,7 @@ "boot_tftp=setenv bootargs $bootargs_def ip=any nfsroot=$nfsroot; setenv autoload y && bootp && bootm\0" \ "boot_usb=setenv bootargs $bootargs_def; usb start && usb storage && fatload usb 0:1 $loadaddr dds-xm200.bin && bootm\0" \ "boot_mmc=setenv bootargs $bootargs_def; mmc rescan && fatload mmc 0:1 $loadaddr dds-xm200.bin && bootm\0" \ - "bootcmd=run boot_mmc ; run boot_usb ; run boot_working ; run boot_safe\0" \ - "altbootcmd=run boot_mmc ; run boot_usb ; run boot_safe ; run boot_working\0" + "bootcmd=run boot_mmc ; run boot_usb ; run boot_working ; run boot_safe\0" /* Console settings */ diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index b7ee1dbf201..5ed17671f79 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 * * Copyright (C) 2017-2024 Intel Corporation <www.intel.com> + * Copyright (C) 2025 Altera Corporation <www.altera.com> * */ @@ -56,6 +57,11 @@ #define BOOTENV_DEV_QSPI(devtypeu, devtypel, instance) \ "bootcmd_qspi=ubi detach; sf probe && " \ + "setenv mtdids 'nor0=nor0,nand0=nand.0' && " \ + "setenv mtdparts 'mtdparts=nor0:66m(u-boot),190m(root); " \ + "nand.0:2m(nand_uboot),500m(nand_root)' && " \ + "env select UBI; saveenv && " \ + "ubi part root && " \ "if ubi part root && ubi readvol ${scriptaddr} script; " \ "then echo QSPI: Running script from UBIFS; " \ "elif sf read ${scriptaddr} ${qspiscriptaddr} ${scriptsize}; " \ diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index 26b6c1cd188..39102f15eb9 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -239,20 +239,47 @@ "if test $fdtfile = undefined; then " \ "echo WARNING: Could not determine device tree to use; fi; \0" +#define GET_OVERLAY_MMC_TI_ARGS \ + "get_overlay_mmc=" \ + "fdt address ${fdtaddr};" \ + "fdt resize 0x100000;" \ + "for overlay in $name_overlays;" \ + "do;" \ + "load mmc ${bootpart} ${dtboaddr} ${bootdir}/dtb/${overlay} &&" \ + "fdt apply ${dtboaddr};" \ + "done;\0" \ + #define BOOT_TARGET_DEVICES(func) \ + func(TI_MMC, ti_mmc, na) \ func(MMC, mmc, 0) \ func(MMC, mmc, 1) \ func(PXE, pxe, na) \ func(DHCP, dhcp, na) +#define BOOTENV_DEV_TI_MMC(devtypeu, devtypel, instance) \ + "bootcmd_ti_mmc= run get_name_kern; run mmcboot\0" + +#define BOOTENV_DEV_NAME_TI_MMC(devtyeu, devtypel, instance) \ + "ti_mmc " + #include <config_distro_bootcmd.h> #define CFG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ DEFAULT_MMC_TI_ARGS \ + "bootpart=0:2\0" \ + "bootdir=/boot\0" \ + "get_name_kern=" \ + "if test $boot_fit -eq 1; then " \ + "setenv bootfile fitImage; " \ + "else " \ + "setenv bootfile zImage; " \ + "fi\0" \ DEFAULT_FIT_TI_ARGS \ + "get_fit_config=setenv name_fit_config ${fdtfile}\0" \ DEFAULT_COMMON_BOOT_TI_ARGS \ DEFAULT_FDT_TI_ARGS \ + GET_OVERLAY_MMC_TI_ARGS \ DFUARGS \ NETARGS \ NANDARGS \ diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index bb0db7c5ca3..13941ba3589 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -179,6 +179,7 @@ #ifndef CFG_EXTRA_ENV_SETTINGS #define CFG_EXTRA_ENV_SETTINGS \ ENV_MEM_LAYOUT_SETTINGS \ + "usb_pgood_delay=1000\0" \ BOOTENV #endif diff --git a/include/cpu_func.h b/include/cpu_func.h index 7e81c4364a7..70a41ead3f7 100644 --- a/include/cpu_func.h +++ b/include/cpu_func.h @@ -69,6 +69,23 @@ void flush_dcache_range(unsigned long start, unsigned long stop); void invalidate_dcache_range(unsigned long start, unsigned long stop); void invalidate_dcache_all(void); void invalidate_icache_all(void); + +enum pgprot_attrs { + MMU_ATTR_RO, + MMU_ATTR_RX, + MMU_ATTR_RW, +}; + +/** pgprot_set_attrs() - Set page table permissions + * + * @addr: Physical address start + * @size: size of memory to change + * @perm: New permissions + * + * Return: 0 on success, error otherwise. + **/ +int pgprot_set_attrs(phys_addr_t addr, size_t size, enum pgprot_attrs perm); + /** * noncached_init() - Initialize non-cached memory region * diff --git a/include/crypto/mscode.h b/include/crypto/mscode.h index 678e69001b9..55501c22acb 100644 --- a/include/crypto/mscode.h +++ b/include/crypto/mscode.h @@ -10,6 +10,7 @@ #include <crypto/hash_info.h> #endif #if CONFIG_IS_ENABLED(MBEDTLS_LIB_X509) +#include "mbedtls_options.h" #include <mbedtls/asn1.h> #include <mbedtls/oid.h> #endif diff --git a/include/crypto/pkcs7_parser.h b/include/crypto/pkcs7_parser.h index 469c2711fa6..fd1e48da09e 100644 --- a/include/crypto/pkcs7_parser.h +++ b/include/crypto/pkcs7_parser.h @@ -12,6 +12,7 @@ #include <crypto/pkcs7.h> #include <crypto/x509_parser.h> #if CONFIG_IS_ENABLED(MBEDTLS_LIB_X509) +#include "mbedtls_options.h" #include <mbedtls/pkcs7.h> #include <library/x509_internal.h> #include <mbedtls/asn1.h> diff --git a/include/dm/ofnode_graph.h b/include/dm/ofnode_graph.h new file mode 100644 index 00000000000..908c990a3f3 --- /dev/null +++ b/include/dm/ofnode_graph.h @@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2025 Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#ifndef _DM_OFNODE_GRAPH_H +#define _DM_OFNODE_GRAPH_H + +#include <dm/of.h> + +/** + * ofnode_graph_get_endpoint_count() - get the number of endpoints in a device ofnode + * @parent: ofnode to the device containing ports and endpoints + * + * Return: count of endpoint of this device ofnode + */ +unsigned int ofnode_graph_get_endpoint_count(ofnode parent); + +/** + * ofnode_graph_get_port_count() - get the number of port in a device or ports ofnode + * @parent: ofnode to the device or ports node + * + * Return: count of port of this device or ports node + */ +unsigned int ofnode_graph_get_port_count(ofnode parent); + +/** + * ofnode_graph_get_port_by_id() - get the port matching a given id + * @parent: parent ofnode + * @id: id of the port + * + * Return: ofnode in given port. + */ +ofnode ofnode_graph_get_port_by_id(ofnode parent, u32 id); + +/** + * ofnode_graph_get_endpoint_by_regs() - get the endpoint matching a given id + * @parent: parent ofnode + * @reg_id: id of the port + * @id: id for the endpoint + * + * Return: ofnode in given endpoint or NULL if not found. + * reg and port_reg are ignored when they are -1. + */ +ofnode ofnode_graph_get_endpoint_by_regs(ofnode parent, u32 reg_id, u32 id); + +/** + * ofnode_graph_get_remote_endpoint() - get remote endpoint node + * @endoint: ofnode of a local endpoint + * + * Return: Remote endpoint ofnode linked with local endpoint. + */ +ofnode ofnode_graph_get_remote_endpoint(ofnode endpoint); + +/** + * ofnode_graph_get_port_parent() - get port's parent node + * @endpoint: ofnode of a local endpoint + * + * Return: device ofnode associated with endpoint + */ +ofnode ofnode_graph_get_port_parent(ofnode endpoint); + +/** + * ofnode_graph_get_remote_port_parent() - get remote port's parent ofnode + * @endoint: ofnode of a local endpoint + * + * Return: device ofnode associated with endpoint linked to local endpoint. + */ +ofnode ofnode_graph_get_remote_port_parent(ofnode endpoint); + +/** + * ofnode_graph_get_remote_port() - get remote port ofnode + * @endoint: ofnode of a local endpoint + * + * Return: port ofnode associated with remote endpoint node linked + * to local endpoint. + */ +ofnode ofnode_graph_get_remote_port(ofnode endpoint); + +/** + * ofnode_graph_get_remote_node() - get remote parent ofnode for given port/endpoint + * @parent: parent ofnode containing graph port/endpoint + * @port: identifier (value of reg property) of the parent port ofnode + * @endpoint: identifier (value of reg property) of the endpoint ofnode + * + * Return: device ofnode associated with endpoint linked to local endpoint. + */ +ofnode ofnode_graph_get_remote_node(ofnode parent, u32 port, u32 endpoint); + +#endif diff --git a/include/dt-bindings/clock/mediatek,mt7987-clk.h b/include/dt-bindings/clock/mediatek,mt7987-clk.h new file mode 100644 index 00000000000..c7472ef9ebb --- /dev/null +++ b/include/dt-bindings/clock/mediatek,mt7987-clk.h @@ -0,0 +1,206 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024 MediaTek Inc. + * Author: Lu Tang <Lu.Tang@mediatek.com> + * Author: Sam Shih <sam.shih@mediatek.com> + */ + +#ifndef _DT_BINDINGS_CLK_MT7987_H +#define _DT_BINDINGS_CLK_MT7987_H + +/* INFRACFG */ + +#define CLK_INFRA_MUX_UART0_SEL 0 +#define CLK_INFRA_MUX_UART1_SEL 1 +#define CLK_INFRA_MUX_UART2_SEL 2 +#define CLK_INFRA_MUX_SPI0_SEL 3 +#define CLK_INFRA_MUX_SPI1_SEL 4 +#define CLK_INFRA_MUX_SPI2_BCK_SEL 5 +#define CLK_INFRA_PWM_BCK_SEL 6 +#define CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 7 +#define CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 8 +#define CLK_INFRA_66M_GPT_BCK 9 +#define CLK_INFRA_66M_PWM_HCK 10 +#define CLK_INFRA_66M_PWM_BCK 11 +#define CLK_INFRA_133M_CQDMA_BCK 12 +#define CLK_INFRA_66M_AUD_SLV_BCK 13 +#define CLK_INFRA_AUD_26M 14 +#define CLK_INFRA_AUD_L 15 +#define CLK_INFRA_AUD_AUD 16 +#define CLK_INFRA_AUD_EG2 17 +#define CLK_INFRA_DRAMC_F26M 18 +#define CLK_INFRA_133M_DBG_ACKM 19 +#define CLK_INFRA_66M_AP_DMA_BCK 20 +#define CLK_INFRA_MSDC200_SRC 21 +#define CLK_INFRA_66M_SEJ_BCK 22 +#define CLK_INFRA_PRE_CK_SEJ_F13M 23 +#define CLK_INFRA_66M_TRNG 24 +#define CLK_INFRA_26M_THERM_SYSTEM 25 +#define CLK_INFRA_I2C_BCK 26 +#define CLK_INFRA_66M_UART0_PCK 27 +#define CLK_INFRA_66M_UART1_PCK 28 +#define CLK_INFRA_66M_UART2_PCK 29 +#define CLK_INFRA_52M_UART0_CK 30 +#define CLK_INFRA_52M_UART1_CK 31 +#define CLK_INFRA_52M_UART2_CK 32 +#define CLK_INFRA_NFI 33 +#define CLK_INFRA_66M_NFI_HCK 34 +#define CLK_INFRA_104M_SPI0 35 +#define CLK_INFRA_104M_SPI1 36 +#define CLK_INFRA_104M_SPI2_BCK 37 +#define CLK_INFRA_66M_SPI0_HCK 38 +#define CLK_INFRA_66M_SPI1_HCK 39 +#define CLK_INFRA_66M_SPI2_HCK 40 +#define CLK_INFRA_66M_FLASHIF_AXI 41 +#define CLK_INFRA_RTC 42 +#define CLK_INFRA_26M_ADC_BCK 43 +#define CLK_INFRA_RC_ADC 44 +#define CLK_INFRA_MSDC400 45 +#define CLK_INFRA_MSDC2_HCK 46 +#define CLK_INFRA_133M_MSDC_0_HCK 47 +#define CLK_INFRA_66M_MSDC_0_HCK 48 +#define CLK_INFRA_133M_CPUM_BCK 49 +#define CLK_INFRA_BIST2FPC 50 +#define CLK_INFRA_I2C_X16W_MCK_CK_P1 51 +#define CLK_INFRA_I2C_X16W_PCK_CK_P1 52 +#define CLK_INFRA_133M_USB_HCK 53 +#define CLK_INFRA_133M_USB_HCK_CK_P1 54 +#define CLK_INFRA_66M_USB_HCK 55 +#define CLK_INFRA_66M_USB_HCK_CK_P1 56 +#define CLK_INFRA_USB_SYS_CK_P1 57 +#define CLK_INFRA_USB_CK_P1 58 +#define CLK_INFRA_USB_FRMCNT_CK_P1 59 +#define CLK_INFRA_USB_PIPE_CK_P1 60 +#define CLK_INFRA_USB_UTMI_CK_P1 61 +#define CLK_INFRA_USB_XHCI_CK_P1 62 +#define CLK_INFRA_PCIE_GFMUX_TL_P0 63 +#define CLK_INFRA_PCIE_GFMUX_TL_P1 64 +#define CLK_INFRA_PCIE_PIPE_P0 65 +#define CLK_INFRA_PCIE_PIPE_P1 66 +#define CLK_INFRA_133M_PCIE_CK_P0 67 +#define CLK_INFRA_133M_PCIE_CK_P1 68 +#define CLK_INFRA_PCIE_PERI_26M_CK_P0 69 +#define CLK_INFRA_PCIE_PERI_26M_CK_P1 70 +#define CLK_INFRA_NR_CLK 71 + +/* TOPCKGEN */ + +#define CLK_TOP_CB_M_D2 0 +#define CLK_TOP_CB_M_D3 1 +#define CLK_TOP_M_D3_D2 2 +#define CLK_TOP_CB_M_D4 3 +#define CLK_TOP_CB_M_D8 4 +#define CLK_TOP_M_D8_D2 5 +#define CLK_TOP_CB_APLL2_D4 6 +#define CLK_TOP_CB_NET1_D3 7 +#define CLK_TOP_CB_NET1_D4 8 +#define CLK_TOP_CB_NET1_D5 9 +#define CLK_TOP_NET1_D5_D2 10 +#define CLK_TOP_NET1_D5_D4 11 +#define CLK_TOP_CB_NET1_D7 12 +#define CLK_TOP_NET1_D7_D2 13 +#define CLK_TOP_NET1_D7_D4 14 +#define CLK_TOP_NET1_D8_D2 15 +#define CLK_TOP_NET1_D8_D4 16 +#define CLK_TOP_NET1_D8_D8 17 +#define CLK_TOP_NET1_D8_D16 18 +#define CLK_TOP_CB_NET2_D2 19 +#define CLK_TOP_CB_NET2_D4 20 +#define CLK_TOP_NET2_D4_D4 21 +#define CLK_TOP_NET2_D4_D8 22 +#define CLK_TOP_CB_NET2_D6 23 +#define CLK_TOP_NET2_D7_D2 24 +#define CLK_TOP_CB_NET2_D8 25 +#define CLK_TOP_MSDC_D2 26 +#define CLK_TOP_CB_CKSQ_40M 27 +#define CLK_TOP_CKSQ_40M_D2 28 +#define CLK_TOP_CB_RTC_32K 29 +#define CLK_TOP_CB_RTC_32P7K 30 +#define CLK_TOP_NETSYS_SEL 31 +#define CLK_TOP_NETSYS_500M_SEL 32 +#define CLK_TOP_NETSYS_2X_SEL 33 +#define CLK_TOP_ETH_GMII_SEL 34 +#define CLK_TOP_EIP_SEL 35 +#define CLK_TOP_AXI_INFRA_SEL 36 +#define CLK_TOP_UART_SEL 37 +#define CLK_TOP_EMMC_250M_SEL 38 +#define CLK_TOP_EMMC_400M_SEL 39 +#define CLK_TOP_SPI_SEL 40 +#define CLK_TOP_SPIM_MST_SEL 41 +#define CLK_TOP_NFI_SEL 42 +#define CLK_TOP_PWM_SEL 43 +#define CLK_TOP_I2C_SEL 44 +#define CLK_TOP_PCIE_MBIST_250M_SEL 45 +#define CLK_TOP_PEXTP_TL_SEL 46 +#define CLK_TOP_PEXTP_TL_P1_SEL 47 +#define CLK_TOP_USB_SYS_P1_SEL 48 +#define CLK_TOP_USB_XHCI_P1_SEL 49 +#define CLK_TOP_AUD_SEL 50 +#define CLK_TOP_A1SYS_SEL 51 +#define CLK_TOP_AUD_L_SEL 52 +#define CLK_TOP_A_TUNER_SEL 53 +#define CLK_TOP_USB_PHY_SEL 54 +#define CLK_TOP_SGM_0_SEL 55 +#define CLK_TOP_SGM_SBUS_0_SEL 56 +#define CLK_TOP_SGM_1_SEL 57 +#define CLK_TOP_SGM_SBUS_1_SEL 58 +#define CLK_TOP_SYSAXI_SEL 59 +#define CLK_TOP_SYSAPB_SEL 60 +#define CLK_TOP_ETH_REFCK_50M_SEL 61 +#define CLK_TOP_ETH_SYS_200M_SEL 62 +#define CLK_TOP_ETH_SYS_SEL 63 +#define CLK_TOP_ETH_XGMII_SEL 64 +#define CLK_TOP_DRAMC_SEL 65 +#define CLK_TOP_DRAMC_MD32_SEL 66 +#define CLK_TOP_INFRA_F26M_SEL 67 +#define CLK_TOP_PEXTP_P0_SEL 68 +#define CLK_TOP_PEXTP_P1_SEL 69 +#define CLK_TOP_DA_XTP_GLB_P0_SEL 70 +#define CLK_TOP_DA_XTP_GLB_P1_SEL 71 +#define CLK_TOP_CKM_SEL 72 +#define CLK_TOP_DA_CKM_XTAL_SEL 73 +#define CLK_TOP_PEXTP_SEL 74 +#define CLK_TOP_ETH_MII_SEL 75 +#define CLK_TOP_EMMC_200M_SEL 76 +#define CLK_TOP_AUD_I2S_M 77 +#define CLK_TOP_NR_CLK 78 + +/* APMIXEDSYS */ + +#define CLK_APMIXED_MPLL 0 +#define CLK_APMIXED_APLL2 1 +#define CLK_APMIXED_NET1PLL 2 +#define CLK_APMIXED_NET2PLL 3 +#define CLK_APMIXED_WEDMCUPLL 4 +#define CLK_APMIXED_SGMPLL 5 +#define CLK_APMIXED_ARM_LL 6 +#define CLK_APMIXED_MSDCPLL 7 +#define CLK_APMIXED_NR_CLK 8 + +/* MCUSYS */ + +#define CLK_MCU_BUS_DIV_SEL 0 +#define CLK_MCU_NR_CLK 1 + +/* SGMIISYS_0 */ + +#define CLK_SGM0_TX_EN 0 +#define CLK_SGM0_RX_EN 1 +#define CLK_SGMII0_NR_CLK 2 + +/* SGMIISYS_1 */ + +#define CLK_SGM1_TX_EN 0 +#define CLK_SGM1_RX_EN 1 +#define CLK_SGMII1_NR_CLK 2 + +/* ETHDMA */ + +#define CLK_ETHDMA_FE_EN 0 +#define CLK_ETHDMA_GP2_EN 1 +#define CLK_ETHDMA_GP1_EN 2 +#define CLK_ETHDMA_GP3_EN 3 +#define CLK_ETHDMA_NR_CLK 4 + +#endif /* _DT_BINDINGS_CLK_MT7987_H */ + diff --git a/include/dt-bindings/clock/rk3036-cru.h b/include/dt-bindings/clock/rk3036-cru.h deleted file mode 100644 index 2c0552d1a93..00000000000 --- a/include/dt-bindings/clock/rk3036-cru.h +++ /dev/null @@ -1,185 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2014 MundoReader S.L. - * Author: Heiko Stuebner <heiko@sntech.de> - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H -#define _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H - -/* core clocks */ -#define PLL_APLL 1 -#define PLL_DPLL 2 -#define PLL_GPLL 3 -#define ARMCLK 4 - -/* sclk gates (special clocks) */ -#define SCLK_GPU 64 -#define SCLK_SPI 65 -#define SCLK_SDMMC 68 -#define SCLK_SDIO 69 -#define SCLK_EMMC 71 -#define SCLK_NANDC 76 -#define SCLK_UART0 77 -#define SCLK_UART1 78 -#define SCLK_UART2 79 -#define SCLK_I2S 82 -#define SCLK_SPDIF 83 -#define SCLK_TIMER0 85 -#define SCLK_TIMER1 86 -#define SCLK_TIMER2 87 -#define SCLK_TIMER3 88 -#define SCLK_OTGPHY0 93 -#define SCLK_LCDC 100 -#define SCLK_HDMI 109 -#define SCLK_HEVC 111 -#define SCLK_I2S_OUT 113 -#define SCLK_SDMMC_DRV 114 -#define SCLK_SDIO_DRV 115 -#define SCLK_EMMC_DRV 117 -#define SCLK_SDMMC_SAMPLE 118 -#define SCLK_SDIO_SAMPLE 119 -#define SCLK_EMMC_SAMPLE 121 -#define SCLK_PVTM_CORE 123 -#define SCLK_PVTM_GPU 124 -#define SCLK_PVTM_VIDEO 125 -#define SCLK_MAC 151 -#define SCLK_MACREF 152 -#define SCLK_SFC 160 - -#define DCLK_LCDC 190 - -/* aclk gates */ -#define ACLK_DMAC2 194 -#define ACLK_LCDC 197 -#define ACLK_VIO 203 -#define ACLK_VCODEC 208 -#define ACLK_CPU 209 -#define ACLK_PERI 210 - -/* pclk gates */ -#define PCLK_GPIO0 320 -#define PCLK_GPIO1 321 -#define PCLK_GPIO2 322 -#define PCLK_GRF 329 -#define PCLK_I2C0 332 -#define PCLK_I2C1 333 -#define PCLK_I2C2 334 -#define PCLK_SPI 338 -#define PCLK_UART0 341 -#define PCLK_UART1 342 -#define PCLK_UART2 343 -#define PCLK_PWM 350 -#define PCLK_TIMER 353 -#define PCLK_HDMI 360 -#define PCLK_CPU 362 -#define PCLK_PERI 363 -#define PCLK_DDRUPCTL 364 -#define PCLK_WDT 368 - -/* hclk gates */ -#define HCLK_OTG0 449 -#define HCLK_OTG1 450 -#define HCLK_NANDC 453 -#define HCLK_SDMMC 456 -#define HCLK_SDIO 457 -#define HCLK_EMMC 459 -#define HCLK_I2S 462 -#define HCLK_LCDC 465 -#define HCLK_ROM 467 -#define HCLK_VIO_BUS 472 -#define HCLK_VCODEC 476 -#define HCLK_CPU 477 -#define HCLK_PERI 478 - -#define CLK_NR_CLKS (HCLK_PERI + 1) - -/* soft-reset indices */ -#define SRST_CORE0 0 -#define SRST_CORE1 1 -#define SRST_CORE0_DBG 4 -#define SRST_CORE1_DBG 5 -#define SRST_CORE0_POR 8 -#define SRST_CORE1_POR 9 -#define SRST_L2C 12 -#define SRST_TOPDBG 13 -#define SRST_STRC_SYS_A 14 -#define SRST_PD_CORE_NIU 15 - -#define SRST_TIMER2 16 -#define SRST_CPUSYS_H 17 -#define SRST_AHB2APB_H 19 -#define SRST_TIMER3 20 -#define SRST_INTMEM 21 -#define SRST_ROM 22 -#define SRST_PERI_NIU 23 -#define SRST_I2S 24 -#define SRST_DDR_PLL 25 -#define SRST_GPU_DLL 26 -#define SRST_TIMER0 27 -#define SRST_TIMER1 28 -#define SRST_CORE_DLL 29 -#define SRST_EFUSE_P 30 -#define SRST_ACODEC_P 31 - -#define SRST_GPIO0 32 -#define SRST_GPIO1 33 -#define SRST_GPIO2 34 -#define SRST_UART0 39 -#define SRST_UART1 40 -#define SRST_UART2 41 -#define SRST_I2C0 43 -#define SRST_I2C1 44 -#define SRST_I2C2 45 -#define SRST_SFC 47 - -#define SRST_PWM0 48 -#define SRST_DAP 51 -#define SRST_DAP_SYS 52 -#define SRST_GRF 55 -#define SRST_PERIPHSYS_A 57 -#define SRST_PERIPHSYS_H 58 -#define SRST_PERIPHSYS_P 59 -#define SRST_CPU_PERI 61 -#define SRST_EMEM_PERI 62 -#define SRST_USB_PERI 63 - -#define SRST_DMA2 64 -#define SRST_MAC 66 -#define SRST_NANDC 68 -#define SRST_USBOTG0 69 -#define SRST_OTGC0 71 -#define SRST_USBOTG1 72 -#define SRST_OTGC1 74 -#define SRST_DDRMSCH 79 - -#define SRST_MMC0 81 -#define SRST_SDIO 82 -#define SRST_EMMC 83 -#define SRST_SPI0 84 -#define SRST_WDT 86 -#define SRST_DDRPHY 88 -#define SRST_DDRPHY_P 89 -#define SRST_DDRCTRL 90 -#define SRST_DDRCTRL_P 91 - -#define SRST_HDMI_P 96 -#define SRST_VIO_BUS_H 99 -#define SRST_UTMI0 103 -#define SRST_UTMI1 104 -#define SRST_USBPOR 105 - -#define SRST_VCODEC_A 112 -#define SRST_VCODEC_H 113 -#define SRST_VIO1_A 114 -#define SRST_HEVC 115 -#define SRST_VCODEC_NIU_A 116 -#define SRST_LCDC1_A 117 -#define SRST_LCDC1_H 118 -#define SRST_LCDC1_D 119 -#define SRST_GPU 120 -#define SRST_GPU_NIU_A 122 - -#define SRST_DBG_P 131 - -#endif diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h deleted file mode 100644 index 453f66718c6..00000000000 --- a/include/dt-bindings/clock/rk3288-cru.h +++ /dev/null @@ -1,381 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (c) 2014 MundoReader S.L. - * Author: Heiko Stuebner <heiko@sntech.de> - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3288_H -#define _DT_BINDINGS_CLK_ROCKCHIP_RK3288_H - -/* core clocks */ -#define PLL_APLL 1 -#define PLL_DPLL 2 -#define PLL_CPLL 3 -#define PLL_GPLL 4 -#define PLL_NPLL 5 -#define ARMCLK 6 - -/* sclk gates (special clocks) */ -#define SCLK_GPU 64 -#define SCLK_SPI0 65 -#define SCLK_SPI1 66 -#define SCLK_SPI2 67 -#define SCLK_SDMMC 68 -#define SCLK_SDIO0 69 -#define SCLK_SDIO1 70 -#define SCLK_EMMC 71 -#define SCLK_TSADC 72 -#define SCLK_SARADC 73 -#define SCLK_PS2C 74 -#define SCLK_NANDC0 75 -#define SCLK_NANDC1 76 -#define SCLK_UART0 77 -#define SCLK_UART1 78 -#define SCLK_UART2 79 -#define SCLK_UART3 80 -#define SCLK_UART4 81 -#define SCLK_I2S0 82 -#define SCLK_SPDIF 83 -#define SCLK_SPDIF8CH 84 -#define SCLK_TIMER0 85 -#define SCLK_TIMER1 86 -#define SCLK_TIMER2 87 -#define SCLK_TIMER3 88 -#define SCLK_TIMER4 89 -#define SCLK_TIMER5 90 -#define SCLK_TIMER6 91 -#define SCLK_HSADC 92 -#define SCLK_OTGPHY0 93 -#define SCLK_OTGPHY1 94 -#define SCLK_OTGPHY2 95 -#define SCLK_OTG_ADP 96 -#define SCLK_HSICPHY480M 97 -#define SCLK_HSICPHY12M 98 -#define SCLK_MACREF 99 -#define SCLK_LCDC_PWM0 100 -#define SCLK_LCDC_PWM1 101 -#define SCLK_MAC_RX 102 -#define SCLK_MAC_TX 103 -#define SCLK_EDP_24M 104 -#define SCLK_EDP 105 -#define SCLK_RGA 106 -#define SCLK_ISP 107 -#define SCLK_ISP_JPE 108 -#define SCLK_HDMI_HDCP 109 -#define SCLK_HDMI_CEC 110 -#define SCLK_HEVC_CABAC 111 -#define SCLK_HEVC_CORE 112 -#define SCLK_I2S0_OUT 113 -#define SCLK_SDMMC_DRV 114 -#define SCLK_SDIO0_DRV 115 -#define SCLK_SDIO1_DRV 116 -#define SCLK_EMMC_DRV 117 -#define SCLK_SDMMC_SAMPLE 118 -#define SCLK_SDIO0_SAMPLE 119 -#define SCLK_SDIO1_SAMPLE 120 -#define SCLK_EMMC_SAMPLE 121 -#define SCLK_USBPHY480M_SRC 122 -#define SCLK_PVTM_CORE 123 -#define SCLK_PVTM_GPU 124 -#define SCLK_CRYPTO 125 -#define SCLK_MIPIDSI_24M 126 -#define SCLK_VIP_OUT 127 - -#define SCLK_MAC_PLL 150 -#define SCLK_MAC 151 -#define SCLK_MACREF_OUT 152 - -#define DCLK_VOP0 190 -#define DCLK_VOP1 191 - -/* aclk gates */ -#define ACLK_GPU 192 -#define ACLK_DMAC1 193 -#define ACLK_DMAC2 194 -#define ACLK_MMU 195 -#define ACLK_GMAC 196 -#define ACLK_VOP0 197 -#define ACLK_VOP1 198 -#define ACLK_CRYPTO 199 -#define ACLK_RGA 200 -#define ACLK_RGA_NIU 201 -#define ACLK_IEP 202 -#define ACLK_VIO0_NIU 203 -#define ACLK_VIP 204 -#define ACLK_ISP 205 -#define ACLK_VIO1_NIU 206 -#define ACLK_HEVC 207 -#define ACLK_VCODEC 208 -#define ACLK_CPU 209 -#define ACLK_PERI 210 - -/* pclk gates */ -#define PCLK_GPIO0 320 -#define PCLK_GPIO1 321 -#define PCLK_GPIO2 322 -#define PCLK_GPIO3 323 -#define PCLK_GPIO4 324 -#define PCLK_GPIO5 325 -#define PCLK_GPIO6 326 -#define PCLK_GPIO7 327 -#define PCLK_GPIO8 328 -#define PCLK_GRF 329 -#define PCLK_SGRF 330 -#define PCLK_PMU 331 -#define PCLK_I2C0 332 -#define PCLK_I2C1 333 -#define PCLK_I2C2 334 -#define PCLK_I2C3 335 -#define PCLK_I2C4 336 -#define PCLK_I2C5 337 -#define PCLK_SPI0 338 -#define PCLK_SPI1 339 -#define PCLK_SPI2 340 -#define PCLK_UART0 341 -#define PCLK_UART1 342 -#define PCLK_UART2 343 -#define PCLK_UART3 344 -#define PCLK_UART4 345 -#define PCLK_TSADC 346 -#define PCLK_SARADC 347 -#define PCLK_SIM 348 -#define PCLK_GMAC 349 -#define PCLK_PWM 350 -#define PCLK_RKPWM 351 -#define PCLK_PS2C 352 -#define PCLK_TIMER 353 -#define PCLK_TZPC 354 -#define PCLK_EDP_CTRL 355 -#define PCLK_MIPI_DSI0 356 -#define PCLK_MIPI_DSI1 357 -#define PCLK_MIPI_CSI 358 -#define PCLK_LVDS_PHY 359 -#define PCLK_HDMI_CTRL 360 -#define PCLK_VIO2_H2P 361 -#define PCLK_CPU 362 -#define PCLK_PERI 363 -#define PCLK_DDRUPCTL0 364 -#define PCLK_PUBL0 365 -#define PCLK_DDRUPCTL1 366 -#define PCLK_PUBL1 367 -#define PCLK_WDT 368 -#define PCLK_EFUSE256 369 -#define PCLK_EFUSE1024 370 -#define PCLK_ISP_IN 371 - -/* hclk gates */ -#define HCLK_GPS 448 -#define HCLK_OTG0 449 -#define HCLK_USBHOST0 450 -#define HCLK_USBHOST1 451 -#define HCLK_HSIC 452 -#define HCLK_NANDC0 453 -#define HCLK_NANDC1 454 -#define HCLK_TSP 455 -#define HCLK_SDMMC 456 -#define HCLK_SDIO0 457 -#define HCLK_SDIO1 458 -#define HCLK_EMMC 459 -#define HCLK_HSADC 460 -#define HCLK_CRYPTO 461 -#define HCLK_I2S0 462 -#define HCLK_SPDIF 463 -#define HCLK_SPDIF8CH 464 -#define HCLK_VOP0 465 -#define HCLK_VOP1 466 -#define HCLK_ROM 467 -#define HCLK_IEP 468 -#define HCLK_ISP 469 -#define HCLK_RGA 470 -#define HCLK_VIO_AHB_ARBI 471 -#define HCLK_VIO_NIU 472 -#define HCLK_VIP 473 -#define HCLK_VIO2_H2P 474 -#define HCLK_HEVC 475 -#define HCLK_VCODEC 476 -#define HCLK_CPU 477 -#define HCLK_PERI 478 - -#define CLK_NR_CLKS (HCLK_PERI + 1) - -/* soft-reset indices */ -#define SRST_CORE0 0 -#define SRST_CORE1 1 -#define SRST_CORE2 2 -#define SRST_CORE3 3 -#define SRST_CORE0_PO 4 -#define SRST_CORE1_PO 5 -#define SRST_CORE2_PO 6 -#define SRST_CORE3_PO 7 -#define SRST_PDCORE_STRSYS 8 -#define SRST_PDBUS_STRSYS 9 -#define SRST_L2C 10 -#define SRST_TOPDBG 11 -#define SRST_CORE0_DBG 12 -#define SRST_CORE1_DBG 13 -#define SRST_CORE2_DBG 14 -#define SRST_CORE3_DBG 15 - -#define SRST_PDBUG_AHB_ARBITOR 16 -#define SRST_EFUSE256 17 -#define SRST_DMAC1 18 -#define SRST_INTMEM 19 -#define SRST_ROM 20 -#define SRST_SPDIF8CH 21 -#define SRST_TIMER 22 -#define SRST_I2S0 23 -#define SRST_SPDIF 24 -#define SRST_TIMER0 25 -#define SRST_TIMER1 26 -#define SRST_TIMER2 27 -#define SRST_TIMER3 28 -#define SRST_TIMER4 29 -#define SRST_TIMER5 30 -#define SRST_EFUSE 31 - -#define SRST_GPIO0 32 -#define SRST_GPIO1 33 -#define SRST_GPIO2 34 -#define SRST_GPIO3 35 -#define SRST_GPIO4 36 -#define SRST_GPIO5 37 -#define SRST_GPIO6 38 -#define SRST_GPIO7 39 -#define SRST_GPIO8 40 -#define SRST_I2C0 42 -#define SRST_I2C1 43 -#define SRST_I2C2 44 -#define SRST_I2C3 45 -#define SRST_I2C4 46 -#define SRST_I2C5 47 - -#define SRST_DWPWM 48 -#define SRST_MMC_PERI 49 -#define SRST_PERIPH_MMU 50 -#define SRST_DAP 51 -#define SRST_DAP_SYS 52 -#define SRST_TPIU 53 -#define SRST_PMU_APB 54 -#define SRST_GRF 55 -#define SRST_PMU 56 -#define SRST_PERIPH_AXI 57 -#define SRST_PERIPH_AHB 58 -#define SRST_PERIPH_APB 59 -#define SRST_PERIPH_NIU 60 -#define SRST_PDPERI_AHB_ARBI 61 -#define SRST_EMEM 62 -#define SRST_USB_PERI 63 - -#define SRST_DMAC2 64 -#define SRST_MAC 66 -#define SRST_GPS 67 -#define SRST_RKPWM 69 -#define SRST_CCP 71 -#define SRST_USBHOST0 72 -#define SRST_HSIC 73 -#define SRST_HSIC_AUX 74 -#define SRST_HSIC_PHY 75 -#define SRST_HSADC 76 -#define SRST_NANDC0 77 -#define SRST_NANDC1 78 - -#define SRST_TZPC 80 -#define SRST_SPI0 83 -#define SRST_SPI1 84 -#define SRST_SPI2 85 -#define SRST_SARADC 87 -#define SRST_PDALIVE_NIU 88 -#define SRST_PDPMU_INTMEM 89 -#define SRST_PDPMU_NIU 90 -#define SRST_SGRF 91 - -#define SRST_VIO_ARBI 96 -#define SRST_RGA_NIU 97 -#define SRST_VIO0_NIU_AXI 98 -#define SRST_VIO_NIU_AHB 99 -#define SRST_LCDC0_AXI 100 -#define SRST_LCDC0_AHB 101 -#define SRST_LCDC0_DCLK 102 -#define SRST_VIO1_NIU_AXI 103 -#define SRST_VIP 104 -#define SRST_RGA_CORE 105 -#define SRST_IEP_AXI 106 -#define SRST_IEP_AHB 107 -#define SRST_RGA_AXI 108 -#define SRST_RGA_AHB 109 -#define SRST_ISP 110 -#define SRST_EDP 111 - -#define SRST_VCODEC_AXI 112 -#define SRST_VCODEC_AHB 113 -#define SRST_VIO_H2P 114 -#define SRST_MIPIDSI0 115 -#define SRST_MIPIDSI1 116 -#define SRST_MIPICSI 117 -#define SRST_LVDS_PHY 118 -#define SRST_LVDS_CON 119 -#define SRST_GPU 120 -#define SRST_HDMI 121 -#define SRST_CORE_PVTM 124 -#define SRST_GPU_PVTM 125 - -#define SRST_MMC0 128 -#define SRST_SDIO0 129 -#define SRST_SDIO1 130 -#define SRST_EMMC 131 -#define SRST_USBOTG_AHB 132 -#define SRST_USBOTG_PHY 133 -#define SRST_USBOTG_CON 134 -#define SRST_USBHOST0_AHB 135 -#define SRST_USBHOST0_PHY 136 -#define SRST_USBHOST0_CON 137 -#define SRST_USBHOST1_AHB 138 -#define SRST_USBHOST1_PHY 139 -#define SRST_USBHOST1_CON 140 -#define SRST_USB_ADP 141 -#define SRST_ACC_EFUSE 142 - -#define SRST_CORESIGHT 144 -#define SRST_PD_CORE_AHB_NOC 145 -#define SRST_PD_CORE_APB_NOC 146 -#define SRST_PD_CORE_MP_AXI 147 -#define SRST_GIC 148 -#define SRST_LCDC_PWM0 149 -#define SRST_LCDC_PWM1 150 -#define SRST_VIO0_H2P_BRG 151 -#define SRST_VIO1_H2P_BRG 152 -#define SRST_RGA_H2P_BRG 153 -#define SRST_HEVC 154 -#define SRST_TSADC 159 - -#define SRST_DDRPHY0 160 -#define SRST_DDRPHY0_APB 161 -#define SRST_DDRCTRL0 162 -#define SRST_DDRCTRL0_APB 163 -#define SRST_DDRPHY0_CTRL 164 -#define SRST_DDRPHY1 165 -#define SRST_DDRPHY1_APB 166 -#define SRST_DDRCTRL1 167 -#define SRST_DDRCTRL1_APB 168 -#define SRST_DDRPHY1_CTRL 169 -#define SRST_DDRMSCH0 170 -#define SRST_DDRMSCH1 171 -#define SRST_CRYPTO 174 -#define SRST_C2C_HOST 175 - -#define SRST_LCDC1_AXI 176 -#define SRST_LCDC1_AHB 177 -#define SRST_LCDC1_DCLK 178 -#define SRST_UART0 179 -#define SRST_UART1 180 -#define SRST_UART2 181 -#define SRST_UART3 182 -#define SRST_UART4 183 -#define SRST_SIMC 186 -#define SRST_PS2C 187 -#define SRST_TSP 188 -#define SRST_TSP_CLKIN0 189 -#define SRST_TSP_CLKIN1 190 -#define SRST_TSP_27M 191 - -#endif diff --git a/include/dt-bindings/clock/stm32fx-clock.h b/include/dt-bindings/clock/stm32fx-clock.h deleted file mode 100644 index e5dad050d51..00000000000 --- a/include/dt-bindings/clock/stm32fx-clock.h +++ /dev/null @@ -1,63 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * stm32fx-clock.h - * - * Copyright (C) 2016 STMicroelectronics - * Author: Gabriel Fernandez for STMicroelectronics. - */ - -/* - * List of clocks which are not derived from system clock (SYSCLOCK) - * - * The index of these clocks is the secondary index of DT bindings - * (see Documentation/devicetree/bindings/clock/st,stm32-rcc.txt) - * - * e.g: - <assigned-clocks = <&rcc 1 CLK_LSE>; -*/ - -#ifndef _DT_BINDINGS_CLK_STMFX_H -#define _DT_BINDINGS_CLK_STMFX_H - -#define SYSTICK 0 -#define FCLK 1 -#define CLK_LSI 2 -#define CLK_LSE 3 -#define CLK_HSE_RTC 4 -#define CLK_RTC 5 -#define PLL_VCO_I2S 6 -#define PLL_VCO_SAI 7 -#define CLK_LCD 8 -#define CLK_I2S 9 -#define CLK_SAI1 10 -#define CLK_SAI2 11 -#define CLK_I2SQ_PDIV 12 -#define CLK_SAIQ_PDIV 13 -#define CLK_HSI 14 -#define CLK_SYSCLK 15 -#define CLK_F469_DSI 16 - -#define END_PRIMARY_CLK 17 - -#define CLK_HDMI_CEC 16 -#define CLK_SPDIF 17 -#define CLK_USART1 18 -#define CLK_USART2 19 -#define CLK_USART3 20 -#define CLK_UART4 21 -#define CLK_UART5 22 -#define CLK_USART6 23 -#define CLK_UART7 24 -#define CLK_UART8 25 -#define CLK_I2C1 26 -#define CLK_I2C2 27 -#define CLK_I2C3 28 -#define CLK_I2C4 29 -#define CLK_LPTIMER 30 -#define CLK_PLL_SRC 31 -#define CLK_DFSDM1 32 -#define CLK_ADFSDM1 33 -#define CLK_F769_DSI 34 -#define END_PRIMARY_CLK_F7 35 - -#endif diff --git a/include/dt-bindings/clock/stm32h7-clks.h b/include/dt-bindings/clock/stm32h7-clks.h deleted file mode 100644 index 4d87e7ebc39..00000000000 --- a/include/dt-bindings/clock/stm32h7-clks.h +++ /dev/null @@ -1,167 +0,0 @@ -/* SYS, CORE AND BUS CLOCKS */ -#define SYS_D1CPRE 0 -#define HCLK 1 -#define PCLK1 2 -#define PCLK2 3 -#define PCLK3 4 -#define PCLK4 5 -#define HSI_DIV 6 -#define HSE_1M 7 -#define I2S_CKIN 8 -#define CK_DSI_PHY 9 -#define HSE_CK 10 -#define LSE_CK 11 -#define CSI_KER_DIV122 12 -#define RTC_CK 13 -#define CPU_SYSTICK 14 - -/* OSCILLATOR BANK */ -#define OSC_BANK 18 -#define HSI_CK 18 -#define HSI_KER_CK 19 -#define CSI_CK 20 -#define CSI_KER_CK 21 -#define RC48_CK 22 -#define LSI_CK 23 - -/* MCLOCK BANK */ -#define MCLK_BANK 28 -#define PER_CK 28 -#define PLLSRC 29 -#define SYS_CK 30 -#define TRACEIN_CK 31 - -/* ODF BANK */ -#define ODF_BANK 32 -#define PLL1_P 32 -#define PLL1_Q 33 -#define PLL1_R 34 -#define PLL2_P 35 -#define PLL2_Q 36 -#define PLL2_R 37 -#define PLL3_P 38 -#define PLL3_Q 39 -#define PLL3_R 40 - -/* MCO BANK */ -#define MCO_BANK 41 -#define MCO1 41 -#define MCO2 42 - -/* PERIF BANK */ -#define PERIF_BANK 50 -#define D1SRAM1_CK 50 -#define ITCM_CK 51 -#define DTCM2_CK 52 -#define DTCM1_CK 53 -#define FLITF_CK 54 -#define JPGDEC_CK 55 -#define DMA2D_CK 56 -#define MDMA_CK 57 -#define USB2ULPI_CK 58 -#define USB1ULPI_CK 59 -#define ETH1RX_CK 60 -#define ETH1TX_CK 61 -#define ETH1MAC_CK 62 -#define ART_CK 63 -#define DMA2_CK 64 -#define DMA1_CK 65 -#define D2SRAM3_CK 66 -#define D2SRAM2_CK 67 -#define D2SRAM1_CK 68 -#define HASH_CK 69 -#define CRYPT_CK 70 -#define CAMITF_CK 71 -#define BKPRAM_CK 72 -#define HSEM_CK 73 -#define BDMA_CK 74 -#define CRC_CK 75 -#define GPIOK_CK 76 -#define GPIOJ_CK 77 -#define GPIOI_CK 78 -#define GPIOH_CK 79 -#define GPIOG_CK 80 -#define GPIOF_CK 81 -#define GPIOE_CK 82 -#define GPIOD_CK 83 -#define GPIOC_CK 84 -#define GPIOB_CK 85 -#define GPIOA_CK 86 -#define WWDG1_CK 87 -#define DAC12_CK 88 -#define WWDG2_CK 89 -#define TIM14_CK 90 -#define TIM13_CK 91 -#define TIM12_CK 92 -#define TIM7_CK 93 -#define TIM6_CK 94 -#define TIM5_CK 95 -#define TIM4_CK 96 -#define TIM3_CK 97 -#define TIM2_CK 98 -#define MDIOS_CK 99 -#define OPAMP_CK 100 -#define CRS_CK 101 -#define TIM17_CK 102 -#define TIM16_CK 103 -#define TIM15_CK 104 -#define TIM8_CK 105 -#define TIM1_CK 106 -#define TMPSENS_CK 107 -#define RTCAPB_CK 108 -#define VREF_CK 109 -#define COMP12_CK 110 -#define SYSCFG_CK 111 -/* must be equal to last peripheral clock index */ -#define LAST_PERIF_BANK SYSCFG_CK - -/* KERNEL BANK */ -#define KERN_BANK 120 -#define SDMMC1_CK 120 -#define QUADSPI_CK 121 -#define FMC_CK 122 -#define USB2OTG_CK 123 -#define USB1OTG_CK 124 -#define ADC12_CK 125 -#define SDMMC2_CK 126 -#define RNG_CK 127 -#define ADC3_CK 128 -#define DSI_CK 129 -#define LTDC_CK 130 -#define USART8_CK 131 -#define USART7_CK 132 -#define HDMICEC_CK 133 -#define I2C3_CK 134 -#define I2C2_CK 135 -#define I2C1_CK 136 -#define UART5_CK 137 -#define UART4_CK 138 -#define USART3_CK 139 -#define USART2_CK 140 -#define SPDIFRX_CK 141 -#define SPI3_CK 142 -#define SPI2_CK 143 -#define LPTIM1_CK 144 -#define FDCAN_CK 145 -#define SWP_CK 146 -#define HRTIM_CK 147 -#define DFSDM1_CK 148 -#define SAI3_CK 149 -#define SAI2_CK 150 -#define SAI1_CK 151 -#define SPI5_CK 152 -#define SPI4_CK 153 -#define SPI1_CK 154 -#define USART6_CK 155 -#define USART1_CK 156 -#define SAI4B_CK 157 -#define SAI4A_CK 158 -#define LPTIM5_CK 159 -#define LPTIM4_CK 160 -#define LPTIM3_CK 161 -#define LPTIM2_CK 162 -#define I2C4_CK 163 -#define SPI6_CK 164 -#define LPUART1_CK 165 - -#define STM32H7_MAX_CLKS 166 diff --git a/include/dt-bindings/clock/stm32mp1-clks.h b/include/dt-bindings/clock/stm32mp1-clks.h deleted file mode 100644 index 0a5324bcdbd..00000000000 --- a/include/dt-bindings/clock/stm32mp1-clks.h +++ /dev/null @@ -1,274 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ -/* - * Copyright (C) STMicroelectronics 2018 - All Rights Reserved - * Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics. - */ - -#ifndef _DT_BINDINGS_STM32MP1_CLKS_H_ -#define _DT_BINDINGS_STM32MP1_CLKS_H_ - -/* OSCILLATOR clocks */ -#define CK_HSE 0 -#define CK_CSI 1 -#define CK_LSI 2 -#define CK_LSE 3 -#define CK_HSI 4 -#define CK_HSE_DIV2 5 - -/* Bus clocks */ -#define TIM2 6 -#define TIM3 7 -#define TIM4 8 -#define TIM5 9 -#define TIM6 10 -#define TIM7 11 -#define TIM12 12 -#define TIM13 13 -#define TIM14 14 -#define LPTIM1 15 -#define SPI2 16 -#define SPI3 17 -#define USART2 18 -#define USART3 19 -#define UART4 20 -#define UART5 21 -#define UART7 22 -#define UART8 23 -#define I2C1 24 -#define I2C2 25 -#define I2C3 26 -#define I2C5 27 -#define SPDIF 28 -#define CEC 29 -#define DAC12 30 -#define MDIO 31 -#define TIM1 32 -#define TIM8 33 -#define TIM15 34 -#define TIM16 35 -#define TIM17 36 -#define SPI1 37 -#define SPI4 38 -#define SPI5 39 -#define USART6 40 -#define SAI1 41 -#define SAI2 42 -#define SAI3 43 -#define DFSDM 44 -#define FDCAN 45 -#define LPTIM2 46 -#define LPTIM3 47 -#define LPTIM4 48 -#define LPTIM5 49 -#define SAI4 50 -#define SYSCFG 51 -#define VREF 52 -#define TMPSENS 53 -#define PMBCTRL 54 -#define HDP 55 -#define LTDC 56 -#define DSI 57 -#define IWDG2 58 -#define USBPHY 59 -#define STGENRO 60 -#define SPI6 61 -#define I2C4 62 -#define I2C6 63 -#define USART1 64 -#define RTCAPB 65 -#define TZC1 66 -#define TZPC 67 -#define IWDG1 68 -#define BSEC 69 -#define STGEN 70 -#define DMA1 71 -#define DMA2 72 -#define DMAMUX 73 -#define ADC12 74 -#define USBO 75 -#define SDMMC3 76 -#define DCMI 77 -#define CRYP2 78 -#define HASH2 79 -#define RNG2 80 -#define CRC2 81 -#define HSEM 82 -#define IPCC 83 -#define GPIOA 84 -#define GPIOB 85 -#define GPIOC 86 -#define GPIOD 87 -#define GPIOE 88 -#define GPIOF 89 -#define GPIOG 90 -#define GPIOH 91 -#define GPIOI 92 -#define GPIOJ 93 -#define GPIOK 94 -#define GPIOZ 95 -#define CRYP1 96 -#define HASH1 97 -#define RNG1 98 -#define BKPSRAM 99 -#define MDMA 100 -#define GPU 101 -#define ETHCK 102 -#define ETHTX 103 -#define ETHRX 104 -#define ETHMAC 105 -#define FMC 106 -#define QSPI 107 -#define SDMMC1 108 -#define SDMMC2 109 -#define CRC1 110 -#define USBH 111 -#define ETHSTP 112 -#define TZC2 113 - -/* Kernel clocks */ -#define SDMMC1_K 118 -#define SDMMC2_K 119 -#define SDMMC3_K 120 -#define FMC_K 121 -#define QSPI_K 122 -#define ETHCK_K 123 -#define RNG1_K 124 -#define RNG2_K 125 -#define GPU_K 126 -#define USBPHY_K 127 -#define STGEN_K 128 -#define SPDIF_K 129 -#define SPI1_K 130 -#define SPI2_K 131 -#define SPI3_K 132 -#define SPI4_K 133 -#define SPI5_K 134 -#define SPI6_K 135 -#define CEC_K 136 -#define I2C1_K 137 -#define I2C2_K 138 -#define I2C3_K 139 -#define I2C4_K 140 -#define I2C5_K 141 -#define I2C6_K 142 -#define LPTIM1_K 143 -#define LPTIM2_K 144 -#define LPTIM3_K 145 -#define LPTIM4_K 146 -#define LPTIM5_K 147 -#define USART1_K 148 -#define USART2_K 149 -#define USART3_K 150 -#define UART4_K 151 -#define UART5_K 152 -#define USART6_K 153 -#define UART7_K 154 -#define UART8_K 155 -#define DFSDM_K 156 -#define FDCAN_K 157 -#define SAI1_K 158 -#define SAI2_K 159 -#define SAI3_K 160 -#define SAI4_K 161 -#define ADC12_K 162 -#define DSI_K 163 -#define DSI_PX 164 -#define ADFSDM_K 165 -#define USBO_K 166 -#define LTDC_PX 167 -#define DAC12_K 168 -#define ETHPTP_K 169 - -/* PLL */ -#define PLL1 176 -#define PLL2 177 -#define PLL3 178 -#define PLL4 179 - -/* ODF */ -#define PLL1_P 180 -#define PLL1_Q 181 -#define PLL1_R 182 -#define PLL2_P 183 -#define PLL2_Q 184 -#define PLL2_R 185 -#define PLL3_P 186 -#define PLL3_Q 187 -#define PLL3_R 188 -#define PLL4_P 189 -#define PLL4_Q 190 -#define PLL4_R 191 - -/* AUX */ -#define RTC 192 - -/* MCLK */ -#define CK_PER 193 -#define CK_MPU 194 -#define CK_AXI 195 -#define CK_MCU 196 - -/* Time base */ -#define TIM2_K 197 -#define TIM3_K 198 -#define TIM4_K 199 -#define TIM5_K 200 -#define TIM6_K 201 -#define TIM7_K 202 -#define TIM12_K 203 -#define TIM13_K 204 -#define TIM14_K 205 -#define TIM1_K 206 -#define TIM8_K 207 -#define TIM15_K 208 -#define TIM16_K 209 -#define TIM17_K 210 - -/* MCO clocks */ -#define CK_MCO1 211 -#define CK_MCO2 212 - -/* TRACE & DEBUG clocks */ -#define CK_DBG 214 -#define CK_TRACE 215 - -/* DDR */ -#define DDRC1 220 -#define DDRC1LP 221 -#define DDRC2 222 -#define DDRC2LP 223 -#define DDRPHYC 224 -#define DDRPHYCLP 225 -#define DDRCAPB 226 -#define DDRCAPBLP 227 -#define AXIDCG 228 -#define DDRPHYCAPB 229 -#define DDRPHYCAPBLP 230 -#define DDRPERFM 231 - -#define STM32MP1_LAST_CLK 232 - -/* SCMI clock identifiers */ -#define CK_SCMI_HSE 0 -#define CK_SCMI_HSI 1 -#define CK_SCMI_CSI 2 -#define CK_SCMI_LSE 3 -#define CK_SCMI_LSI 4 -#define CK_SCMI_PLL2_Q 5 -#define CK_SCMI_PLL2_R 6 -#define CK_SCMI_MPU 7 -#define CK_SCMI_AXI 8 -#define CK_SCMI_BSEC 9 -#define CK_SCMI_CRYP1 10 -#define CK_SCMI_GPIOZ 11 -#define CK_SCMI_HASH1 12 -#define CK_SCMI_I2C4 13 -#define CK_SCMI_I2C6 14 -#define CK_SCMI_IWDG1 15 -#define CK_SCMI_RNG1 16 -#define CK_SCMI_RTC 17 -#define CK_SCMI_RTCAPB 18 -#define CK_SCMI_SPI6 19 -#define CK_SCMI_USART1 20 - -#endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */ diff --git a/include/dt-bindings/clock/stm32mp13-clks.h b/include/dt-bindings/clock/stm32mp13-clks.h deleted file mode 100644 index 0bd7b54c65f..00000000000 --- a/include/dt-bindings/clock/stm32mp13-clks.h +++ /dev/null @@ -1,229 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */ -/* - * Copyright (C) STMicroelectronics 2020 - All Rights Reserved - * Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics. - */ - -#ifndef _DT_BINDINGS_STM32MP13_CLKS_H_ -#define _DT_BINDINGS_STM32MP13_CLKS_H_ - -/* OSCILLATOR clocks */ -#define CK_HSE 0 -#define CK_CSI 1 -#define CK_LSI 2 -#define CK_LSE 3 -#define CK_HSI 4 -#define CK_HSE_DIV2 5 - -/* PLL */ -#define PLL1 6 -#define PLL2 7 -#define PLL3 8 -#define PLL4 9 - -/* ODF */ -#define PLL1_P 10 -#define PLL1_Q 11 -#define PLL1_R 12 -#define PLL2_P 13 -#define PLL2_Q 14 -#define PLL2_R 15 -#define PLL3_P 16 -#define PLL3_Q 17 -#define PLL3_R 18 -#define PLL4_P 19 -#define PLL4_Q 20 -#define PLL4_R 21 - -#define PCLK1 22 -#define PCLK2 23 -#define PCLK3 24 -#define PCLK4 25 -#define PCLK5 26 -#define PCLK6 27 - -/* SYSTEM CLOCK */ -#define CK_PER 28 -#define CK_MPU 29 -#define CK_AXI 30 -#define CK_MLAHB 31 - -/* BASE TIMER */ -#define CK_TIMG1 32 -#define CK_TIMG2 33 -#define CK_TIMG3 34 - -/* AUX */ -#define RTC 35 - -/* TRACE & DEBUG clocks */ -#define CK_DBG 36 -#define CK_TRACE 37 - -/* MCO clocks */ -#define CK_MCO1 38 -#define CK_MCO2 39 - -/* IP clocks */ -#define SYSCFG 40 -#define VREF 41 -#define DTS 42 -#define PMBCTRL 43 -#define HDP 44 -#define IWDG2 45 -#define STGENRO 46 -#define USART1 47 -#define RTCAPB 48 -#define TZC 49 -#define TZPC 50 -#define IWDG1 51 -#define BSEC 52 -#define DMA1 53 -#define DMA2 54 -#define DMAMUX1 55 -#define DMAMUX2 56 -#define GPIOA 57 -#define GPIOB 58 -#define GPIOC 59 -#define GPIOD 60 -#define GPIOE 61 -#define GPIOF 62 -#define GPIOG 63 -#define GPIOH 64 -#define GPIOI 65 -#define CRYP1 66 -#define HASH1 67 -#define BKPSRAM 68 -#define MDMA 69 -#define CRC1 70 -#define USBH 71 -#define DMA3 72 -#define TSC 73 -#define PKA 74 -#define AXIMC 75 -#define MCE 76 -#define ETH1TX 77 -#define ETH2TX 78 -#define ETH1RX 79 -#define ETH2RX 80 -#define ETH1MAC 81 -#define ETH2MAC 82 -#define ETH1STP 83 -#define ETH2STP 84 - -/* IP clocks with parents */ -#define SDMMC1_K 85 -#define SDMMC2_K 86 -#define ADC1_K 87 -#define ADC2_K 88 -#define FMC_K 89 -#define QSPI_K 90 -#define RNG1_K 91 -#define USBPHY_K 92 -#define STGEN_K 93 -#define SPDIF_K 94 -#define SPI1_K 95 -#define SPI2_K 96 -#define SPI3_K 97 -#define SPI4_K 98 -#define SPI5_K 99 -#define I2C1_K 100 -#define I2C2_K 101 -#define I2C3_K 102 -#define I2C4_K 103 -#define I2C5_K 104 -#define TIM2_K 105 -#define TIM3_K 106 -#define TIM4_K 107 -#define TIM5_K 108 -#define TIM6_K 109 -#define TIM7_K 110 -#define TIM12_K 111 -#define TIM13_K 112 -#define TIM14_K 113 -#define TIM1_K 114 -#define TIM8_K 115 -#define TIM15_K 116 -#define TIM16_K 117 -#define TIM17_K 118 -#define LPTIM1_K 119 -#define LPTIM2_K 120 -#define LPTIM3_K 121 -#define LPTIM4_K 122 -#define LPTIM5_K 123 -#define USART1_K 124 -#define USART2_K 125 -#define USART3_K 126 -#define UART4_K 127 -#define UART5_K 128 -#define USART6_K 129 -#define UART7_K 130 -#define UART8_K 131 -#define DFSDM_K 132 -#define FDCAN_K 133 -#define SAI1_K 134 -#define SAI2_K 135 -#define ADFSDM_K 136 -#define USBO_K 137 -#define LTDC_PX 138 -#define ETH1CK_K 139 -#define ETH1PTP_K 140 -#define ETH2CK_K 141 -#define ETH2PTP_K 142 -#define DCMIPP_K 143 -#define SAES_K 144 -#define DTS_K 145 - -/* DDR */ -#define DDRC1 146 -#define DDRC1LP 147 -#define DDRC2 148 -#define DDRC2LP 149 -#define DDRPHYC 150 -#define DDRPHYCLP 151 -#define DDRCAPB 152 -#define DDRCAPBLP 153 -#define AXIDCG 154 -#define DDRPHYCAPB 155 -#define DDRPHYCAPBLP 156 -#define DDRPERFM 157 - -#define ADC1 158 -#define ADC2 159 -#define SAI1 160 -#define SAI2 161 - -#define STM32MP1_LAST_CLK 162 - -/* SCMI clock identifiers */ -#define CK_SCMI_HSE 0 -#define CK_SCMI_HSI 1 -#define CK_SCMI_CSI 2 -#define CK_SCMI_LSE 3 -#define CK_SCMI_LSI 4 -#define CK_SCMI_HSE_DIV2 5 -#define CK_SCMI_PLL2_Q 6 -#define CK_SCMI_PLL2_R 7 -#define CK_SCMI_PLL3_P 8 -#define CK_SCMI_PLL3_Q 9 -#define CK_SCMI_PLL3_R 10 -#define CK_SCMI_PLL4_P 11 -#define CK_SCMI_PLL4_Q 12 -#define CK_SCMI_PLL4_R 13 -#define CK_SCMI_MPU 14 -#define CK_SCMI_AXI 15 -#define CK_SCMI_MLAHB 16 -#define CK_SCMI_CKPER 17 -#define CK_SCMI_PCLK1 18 -#define CK_SCMI_PCLK2 19 -#define CK_SCMI_PCLK3 20 -#define CK_SCMI_PCLK4 21 -#define CK_SCMI_PCLK5 22 -#define CK_SCMI_PCLK6 23 -#define CK_SCMI_CKTIMG1 24 -#define CK_SCMI_CKTIMG2 25 -#define CK_SCMI_CKTIMG3 26 -#define CK_SCMI_RTC 27 -#define CK_SCMI_RTCAPB 28 - -#endif /* _DT_BINDINGS_STM32MP13_CLKS_H_ */ diff --git a/include/dt-bindings/mfd/stm32f4-rcc.h b/include/dt-bindings/mfd/stm32f4-rcc.h deleted file mode 100644 index 36448a5619a..00000000000 --- a/include/dt-bindings/mfd/stm32f4-rcc.h +++ /dev/null @@ -1,108 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for the STM32F4 RCC IP - */ - -#ifndef _DT_BINDINGS_MFD_STM32F4_RCC_H -#define _DT_BINDINGS_MFD_STM32F4_RCC_H - -/* AHB1 */ -#define STM32F4_RCC_AHB1_GPIOA 0 -#define STM32F4_RCC_AHB1_GPIOB 1 -#define STM32F4_RCC_AHB1_GPIOC 2 -#define STM32F4_RCC_AHB1_GPIOD 3 -#define STM32F4_RCC_AHB1_GPIOE 4 -#define STM32F4_RCC_AHB1_GPIOF 5 -#define STM32F4_RCC_AHB1_GPIOG 6 -#define STM32F4_RCC_AHB1_GPIOH 7 -#define STM32F4_RCC_AHB1_GPIOI 8 -#define STM32F4_RCC_AHB1_GPIOJ 9 -#define STM32F4_RCC_AHB1_GPIOK 10 -#define STM32F4_RCC_AHB1_CRC 12 -#define STM32F4_RCC_AHB1_BKPSRAM 18 -#define STM32F4_RCC_AHB1_CCMDATARAM 20 -#define STM32F4_RCC_AHB1_DMA1 21 -#define STM32F4_RCC_AHB1_DMA2 22 -#define STM32F4_RCC_AHB1_DMA2D 23 -#define STM32F4_RCC_AHB1_ETHMAC 25 -#define STM32F4_RCC_AHB1_ETHMACTX 26 -#define STM32F4_RCC_AHB1_ETHMACRX 27 -#define STM32F4_RCC_AHB1_ETHMACPTP 28 -#define STM32F4_RCC_AHB1_OTGHS 29 -#define STM32F4_RCC_AHB1_OTGHSULPI 30 - -#define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) -#define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) - -/* AHB2 */ -#define STM32F4_RCC_AHB2_DCMI 0 -#define STM32F4_RCC_AHB2_CRYP 4 -#define STM32F4_RCC_AHB2_HASH 5 -#define STM32F4_RCC_AHB2_RNG 6 -#define STM32F4_RCC_AHB2_OTGFS 7 - -#define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) -#define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) - -/* AHB3 */ -#define STM32F4_RCC_AHB3_FMC 0 -#define STM32F4_RCC_AHB3_QSPI 1 - -#define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) -#define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) - -/* APB1 */ -#define STM32F4_RCC_APB1_TIM2 0 -#define STM32F4_RCC_APB1_TIM3 1 -#define STM32F4_RCC_APB1_TIM4 2 -#define STM32F4_RCC_APB1_TIM5 3 -#define STM32F4_RCC_APB1_TIM6 4 -#define STM32F4_RCC_APB1_TIM7 5 -#define STM32F4_RCC_APB1_TIM12 6 -#define STM32F4_RCC_APB1_TIM13 7 -#define STM32F4_RCC_APB1_TIM14 8 -#define STM32F4_RCC_APB1_WWDG 11 -#define STM32F4_RCC_APB1_SPI2 14 -#define STM32F4_RCC_APB1_SPI3 15 -#define STM32F4_RCC_APB1_UART2 17 -#define STM32F4_RCC_APB1_UART3 18 -#define STM32F4_RCC_APB1_UART4 19 -#define STM32F4_RCC_APB1_UART5 20 -#define STM32F4_RCC_APB1_I2C1 21 -#define STM32F4_RCC_APB1_I2C2 22 -#define STM32F4_RCC_APB1_I2C3 23 -#define STM32F4_RCC_APB1_CAN1 25 -#define STM32F4_RCC_APB1_CAN2 26 -#define STM32F4_RCC_APB1_PWR 28 -#define STM32F4_RCC_APB1_DAC 29 -#define STM32F4_RCC_APB1_UART7 30 -#define STM32F4_RCC_APB1_UART8 31 - -#define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) -#define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80) - -/* APB2 */ -#define STM32F4_RCC_APB2_TIM1 0 -#define STM32F4_RCC_APB2_TIM8 1 -#define STM32F4_RCC_APB2_USART1 4 -#define STM32F4_RCC_APB2_USART6 5 -#define STM32F4_RCC_APB2_ADC1 8 -#define STM32F4_RCC_APB2_ADC2 9 -#define STM32F4_RCC_APB2_ADC3 10 -#define STM32F4_RCC_APB2_SDIO 11 -#define STM32F4_RCC_APB2_SPI1 12 -#define STM32F4_RCC_APB2_SPI4 13 -#define STM32F4_RCC_APB2_SYSCFG 14 -#define STM32F4_RCC_APB2_TIM9 16 -#define STM32F4_RCC_APB2_TIM10 17 -#define STM32F4_RCC_APB2_TIM11 18 -#define STM32F4_RCC_APB2_SPI5 20 -#define STM32F4_RCC_APB2_SPI6 21 -#define STM32F4_RCC_APB2_SAI1 22 -#define STM32F4_RCC_APB2_LTDC 26 -#define STM32F4_RCC_APB2_DSI 27 - -#define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) -#define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0) - -#endif /* _DT_BINDINGS_MFD_STM32F4_RCC_H */ diff --git a/include/dt-bindings/mfd/stm32f7-rcc.h b/include/dt-bindings/mfd/stm32f7-rcc.h deleted file mode 100644 index 1aa267e76a5..00000000000 --- a/include/dt-bindings/mfd/stm32f7-rcc.h +++ /dev/null @@ -1,115 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for the STM32F7 RCC IP - */ - -#ifndef _DT_BINDINGS_MFD_STM32F7_RCC_H -#define _DT_BINDINGS_MFD_STM32F7_RCC_H - -/* AHB1 */ -#define STM32F7_RCC_AHB1_GPIOA 0 -#define STM32F7_RCC_AHB1_GPIOB 1 -#define STM32F7_RCC_AHB1_GPIOC 2 -#define STM32F7_RCC_AHB1_GPIOD 3 -#define STM32F7_RCC_AHB1_GPIOE 4 -#define STM32F7_RCC_AHB1_GPIOF 5 -#define STM32F7_RCC_AHB1_GPIOG 6 -#define STM32F7_RCC_AHB1_GPIOH 7 -#define STM32F7_RCC_AHB1_GPIOI 8 -#define STM32F7_RCC_AHB1_GPIOJ 9 -#define STM32F7_RCC_AHB1_GPIOK 10 -#define STM32F7_RCC_AHB1_CRC 12 -#define STM32F7_RCC_AHB1_BKPSRAM 18 -#define STM32F7_RCC_AHB1_DTCMRAM 20 -#define STM32F7_RCC_AHB1_DMA1 21 -#define STM32F7_RCC_AHB1_DMA2 22 -#define STM32F7_RCC_AHB1_DMA2D 23 -#define STM32F7_RCC_AHB1_ETHMAC 25 -#define STM32F7_RCC_AHB1_ETHMACTX 26 -#define STM32F7_RCC_AHB1_ETHMACRX 27 -#define STM32FF_RCC_AHB1_ETHMACPTP 28 -#define STM32F7_RCC_AHB1_OTGHS 29 -#define STM32F7_RCC_AHB1_OTGHSULPI 30 - -#define STM32F7_AHB1_RESET(bit) (STM32F7_RCC_AHB1_##bit + (0x10 * 8)) -#define STM32F7_AHB1_CLOCK(bit) (STM32F7_RCC_AHB1_##bit) - -/* AHB2 */ -#define STM32F7_RCC_AHB2_DCMI 0 -#define STM32F7_RCC_AHB2_CRYP 4 -#define STM32F7_RCC_AHB2_HASH 5 -#define STM32F7_RCC_AHB2_RNG 6 -#define STM32F7_RCC_AHB2_OTGFS 7 - -#define STM32F7_AHB2_RESET(bit) (STM32F7_RCC_AHB2_##bit + (0x14 * 8)) -#define STM32F7_AHB2_CLOCK(bit) (STM32F7_RCC_AHB2_##bit + 0x20) - -/* AHB3 */ -#define STM32F7_RCC_AHB3_FMC 0 -#define STM32F7_RCC_AHB3_QSPI 1 - -#define STM32F7_AHB3_RESET(bit) (STM32F7_RCC_AHB3_##bit + (0x18 * 8)) -#define STM32F7_AHB3_CLOCK(bit) (STM32F7_RCC_AHB3_##bit + 0x40) - -/* APB1 */ -#define STM32F7_RCC_APB1_TIM2 0 -#define STM32F7_RCC_APB1_TIM3 1 -#define STM32F7_RCC_APB1_TIM4 2 -#define STM32F7_RCC_APB1_TIM5 3 -#define STM32F7_RCC_APB1_TIM6 4 -#define STM32F7_RCC_APB1_TIM7 5 -#define STM32F7_RCC_APB1_TIM12 6 -#define STM32F7_RCC_APB1_TIM13 7 -#define STM32F7_RCC_APB1_TIM14 8 -#define STM32F7_RCC_APB1_LPTIM1 9 -#define STM32F7_RCC_APB1_WWDG 11 -#define STM32F7_RCC_APB1_CAN3 13 -#define STM32F7_RCC_APB1_SPI2 14 -#define STM32F7_RCC_APB1_SPI3 15 -#define STM32F7_RCC_APB1_SPDIFRX 16 -#define STM32F7_RCC_APB1_UART2 17 -#define STM32F7_RCC_APB1_UART3 18 -#define STM32F7_RCC_APB1_UART4 19 -#define STM32F7_RCC_APB1_UART5 20 -#define STM32F7_RCC_APB1_I2C1 21 -#define STM32F7_RCC_APB1_I2C2 22 -#define STM32F7_RCC_APB1_I2C3 23 -#define STM32F7_RCC_APB1_I2C4 24 -#define STM32F7_RCC_APB1_CAN1 25 -#define STM32F7_RCC_APB1_CAN2 26 -#define STM32F7_RCC_APB1_CEC 27 -#define STM32F7_RCC_APB1_PWR 28 -#define STM32F7_RCC_APB1_DAC 29 -#define STM32F7_RCC_APB1_UART7 30 -#define STM32F7_RCC_APB1_UART8 31 - -#define STM32F7_APB1_RESET(bit) (STM32F7_RCC_APB1_##bit + (0x20 * 8)) -#define STM32F7_APB1_CLOCK(bit) (STM32F7_RCC_APB1_##bit + 0x80) - -/* APB2 */ -#define STM32F7_RCC_APB2_TIM1 0 -#define STM32F7_RCC_APB2_TIM8 1 -#define STM32F7_RCC_APB2_USART1 4 -#define STM32F7_RCC_APB2_USART6 5 -#define STM32F7_RCC_APB2_SDMMC2 7 -#define STM32F7_RCC_APB2_ADC1 8 -#define STM32F7_RCC_APB2_ADC2 9 -#define STM32F7_RCC_APB2_ADC3 10 -#define STM32F7_RCC_APB2_SDMMC1 11 -#define STM32F7_RCC_APB2_SPI1 12 -#define STM32F7_RCC_APB2_SPI4 13 -#define STM32F7_RCC_APB2_SYSCFG 14 -#define STM32F7_RCC_APB2_TIM9 16 -#define STM32F7_RCC_APB2_TIM10 17 -#define STM32F7_RCC_APB2_TIM11 18 -#define STM32F7_RCC_APB2_SPI5 20 -#define STM32F7_RCC_APB2_SPI6 21 -#define STM32F7_RCC_APB2_SAI1 22 -#define STM32F7_RCC_APB2_SAI2 23 -#define STM32F7_RCC_APB2_LTDC 26 -#define STM32F7_RCC_APB2_DSI 27 - -#define STM32F7_APB2_RESET(bit) (STM32F7_RCC_APB2_##bit + (0x24 * 8)) -#define STM32F7_APB2_CLOCK(bit) (STM32F7_RCC_APB2_##bit + 0xA0) - -#endif /* _DT_BINDINGS_MFD_STM32F7_RCC_H */ diff --git a/include/dt-bindings/mfd/stm32h7-rcc.h b/include/dt-bindings/mfd/stm32h7-rcc.h deleted file mode 100644 index 06e8476bf08..00000000000 --- a/include/dt-bindings/mfd/stm32h7-rcc.h +++ /dev/null @@ -1,138 +0,0 @@ -/* - * This header provides constants for the STM32H7 RCC IP - */ - -#ifndef _DT_BINDINGS_MFD_STM32H7_RCC_H -#define _DT_BINDINGS_MFD_STM32H7_RCC_H - -/* AHB3 */ -#define STM32H7_RCC_AHB3_MDMA 0 -#define STM32H7_RCC_AHB3_DMA2D 4 -#define STM32H7_RCC_AHB3_JPGDEC 5 -#define STM32H7_RCC_AHB3_FMC 12 -#define STM32H7_RCC_AHB3_QUADSPI 14 -#define STM32H7_RCC_AHB3_SDMMC1 16 -#define STM32H7_RCC_AHB3_CPU 31 -#define STM32H7_RCC_AHB3_CPU1 31 - -#define STM32H7_AHB3_RESET(bit) (STM32H7_RCC_AHB3_##bit + (0x7C * 8)) - -/* AHB1 */ -#define STM32H7_RCC_AHB1_DMA1 0 -#define STM32H7_RCC_AHB1_DMA2 1 -#define STM32H7_RCC_AHB1_ADC12 5 -#define STM32H7_RCC_AHB1_ART 14 -#define STM32H7_RCC_AHB1_ETH1MAC 15 -#define STM32H7_RCC_AHB1_USB1OTG 25 -#define STM32H7_RCC_AHB1_USB2OTG 27 -#define STM32H7_RCC_AHB1_CPU2 31 - -#define STM32H7_AHB1_RESET(bit) (STM32H7_RCC_AHB1_##bit + (0x80 * 8)) - -/* AHB2 */ -#define STM32H7_RCC_AHB2_CAMITF 0 -#define STM32H7_RCC_AHB2_CRYPT 4 -#define STM32H7_RCC_AHB2_HASH 5 -#define STM32H7_RCC_AHB2_RNG 6 -#define STM32H7_RCC_AHB2_SDMMC2 9 - -#define STM32H7_AHB2_RESET(bit) (STM32H7_RCC_AHB2_##bit + (0x84 * 8)) - -/* AHB4 */ -#define STM32H7_RCC_AHB4_GPIOA 0 -#define STM32H7_RCC_AHB4_GPIOB 1 -#define STM32H7_RCC_AHB4_GPIOC 2 -#define STM32H7_RCC_AHB4_GPIOD 3 -#define STM32H7_RCC_AHB4_GPIOE 4 -#define STM32H7_RCC_AHB4_GPIOF 5 -#define STM32H7_RCC_AHB4_GPIOG 6 -#define STM32H7_RCC_AHB4_GPIOH 7 -#define STM32H7_RCC_AHB4_GPIOI 8 -#define STM32H7_RCC_AHB4_GPIOJ 9 -#define STM32H7_RCC_AHB4_GPIOK 10 -#define STM32H7_RCC_AHB4_CRC 19 -#define STM32H7_RCC_AHB4_BDMA 21 -#define STM32H7_RCC_AHB4_ADC3 24 -#define STM32H7_RCC_AHB4_HSEM 25 - -#define STM32H7_AHB4_RESET(bit) (STM32H7_RCC_AHB4_##bit + (0x88 * 8)) - -/* APB3 */ -#define STM32H7_RCC_APB3_LTDC 3 -#define STM32H7_RCC_APB3_DSI 4 - -#define STM32H7_APB3_RESET(bit) (STM32H7_RCC_APB3_##bit + (0x8C * 8)) - -/* APB1L */ -#define STM32H7_RCC_APB1L_TIM2 0 -#define STM32H7_RCC_APB1L_TIM3 1 -#define STM32H7_RCC_APB1L_TIM4 2 -#define STM32H7_RCC_APB1L_TIM5 3 -#define STM32H7_RCC_APB1L_TIM6 4 -#define STM32H7_RCC_APB1L_TIM7 5 -#define STM32H7_RCC_APB1L_TIM12 6 -#define STM32H7_RCC_APB1L_TIM13 7 -#define STM32H7_RCC_APB1L_TIM14 8 -#define STM32H7_RCC_APB1L_LPTIM1 9 -#define STM32H7_RCC_APB1L_SPI2 14 -#define STM32H7_RCC_APB1L_SPI3 15 -#define STM32H7_RCC_APB1L_SPDIF_RX 16 -#define STM32H7_RCC_APB1L_USART2 17 -#define STM32H7_RCC_APB1L_USART3 18 -#define STM32H7_RCC_APB1L_UART4 19 -#define STM32H7_RCC_APB1L_UART5 20 -#define STM32H7_RCC_APB1L_I2C1 21 -#define STM32H7_RCC_APB1L_I2C2 22 -#define STM32H7_RCC_APB1L_I2C3 23 -#define STM32H7_RCC_APB1L_HDMICEC 27 -#define STM32H7_RCC_APB1L_DAC12 29 -#define STM32H7_RCC_APB1L_USART7 30 -#define STM32H7_RCC_APB1L_USART8 31 - -#define STM32H7_APB1L_RESET(bit) (STM32H7_RCC_APB1L_##bit + (0x90 * 8)) - -/* APB1H */ -#define STM32H7_RCC_APB1H_CRS 1 -#define STM32H7_RCC_APB1H_SWP 2 -#define STM32H7_RCC_APB1H_OPAMP 4 -#define STM32H7_RCC_APB1H_MDIOS 5 -#define STM32H7_RCC_APB1H_FDCAN 8 - -#define STM32H7_APB1H_RESET(bit) (STM32H7_RCC_APB1H_##bit + (0x94 * 8)) - -/* APB2 */ -#define STM32H7_RCC_APB2_TIM1 0 -#define STM32H7_RCC_APB2_TIM8 1 -#define STM32H7_RCC_APB2_USART1 4 -#define STM32H7_RCC_APB2_USART6 5 -#define STM32H7_RCC_APB2_SPI1 12 -#define STM32H7_RCC_APB2_SPI4 13 -#define STM32H7_RCC_APB2_TIM15 16 -#define STM32H7_RCC_APB2_TIM16 17 -#define STM32H7_RCC_APB2_TIM17 18 -#define STM32H7_RCC_APB2_SPI5 20 -#define STM32H7_RCC_APB2_SAI1 22 -#define STM32H7_RCC_APB2_SAI2 23 -#define STM32H7_RCC_APB2_SAI3 24 -#define STM32H7_RCC_APB2_DFSDM1 28 -#define STM32H7_RCC_APB2_HRTIM 29 - -#define STM32H7_APB2_RESET(bit) (STM32H7_RCC_APB2_##bit + (0x98 * 8)) - -/* APB4 */ -#define STM32H7_RCC_APB4_SYSCFG 1 -#define STM32H7_RCC_APB4_LPUART1 3 -#define STM32H7_RCC_APB4_SPI6 5 -#define STM32H7_RCC_APB4_I2C4 7 -#define STM32H7_RCC_APB4_LPTIM2 9 -#define STM32H7_RCC_APB4_LPTIM3 10 -#define STM32H7_RCC_APB4_LPTIM4 11 -#define STM32H7_RCC_APB4_LPTIM5 12 -#define STM32H7_RCC_APB4_COMP12 14 -#define STM32H7_RCC_APB4_VREF 15 -#define STM32H7_RCC_APB4_SAI4 21 -#define STM32H7_RCC_APB4_TMPSENS 26 - -#define STM32H7_APB4_RESET(bit) (STM32H7_RCC_APB4_##bit + (0x9C * 8)) - -#endif /* _DT_BINDINGS_MFD_STM32H7_RCC_H */ diff --git a/include/dt-bindings/pinctrl/adi-adsp.h b/include/dt-bindings/pinctrl/adi-adsp.h new file mode 100644 index 00000000000..7dc8a1ef5c4 --- /dev/null +++ b/include/dt-bindings/pinctrl/adi-adsp.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * (C) Copyright 2022 - Analog Devices, Inc. + * + * Written and/or maintained by Timesys Corporation + * + * Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com> + * Contact: Greg Malysa <greg.malysa@timesys.com> + * + */ + +#ifndef DT_BINDINGS_PINCTRL_ADI_ADSP +#define DT_BINDINGS_PINCTRL_ADI_ADSP + +#define ADI_ADSP_PIN(port, pin) (16 * ((port) - 'A') + (pin)) +#define ADI_ADSP_PINFUNC_ALT0 0 +#define ADI_ADSP_PINFUNC_ALT1 1 +#define ADI_ADSP_PINFUNC_ALT2 2 +#define ADI_ADSP_PINFUNC_ALT3 3 + +#endif diff --git a/include/dt-bindings/pinctrl/stm32-pinfunc.h b/include/dt-bindings/pinctrl/stm32-pinfunc.h deleted file mode 100644 index 28ad0235086..00000000000 --- a/include/dt-bindings/pinctrl/stm32-pinfunc.h +++ /dev/null @@ -1,45 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ -/* - * Copyright (C) STMicroelectronics 2017 - All Rights Reserved - * Author: Torgue Alexandre <alexandre.torgue@st.com> for STMicroelectronics. - */ - -#ifndef _DT_BINDINGS_STM32_PINFUNC_H -#define _DT_BINDINGS_STM32_PINFUNC_H - -/* define PIN modes */ -#define GPIO 0x0 -#define AF0 0x1 -#define AF1 0x2 -#define AF2 0x3 -#define AF3 0x4 -#define AF4 0x5 -#define AF5 0x6 -#define AF6 0x7 -#define AF7 0x8 -#define AF8 0x9 -#define AF9 0xa -#define AF10 0xb -#define AF11 0xc -#define AF12 0xd -#define AF13 0xe -#define AF14 0xf -#define AF15 0x10 -#define ANALOG 0x11 - -/* define Pins number*/ -#define PIN_NO(port, line) (((port) - 'A') * 0x10 + (line)) - -#define STM32_PINMUX(port, line, mode) (((PIN_NO(port, line)) << 8) | (mode)) - -/* package information */ -#define STM32MP_PKG_AA 0x1 -#define STM32MP_PKG_AB 0x2 -#define STM32MP_PKG_AC 0x4 -#define STM32MP_PKG_AD 0x8 -#define STM32MP_PKG_AI 0x100 -#define STM32MP_PKG_AK 0x400 -#define STM32MP_PKG_AL 0x800 - -#endif /* _DT_BINDINGS_STM32_PINFUNC_H */ - diff --git a/include/dt-bindings/regulator/st,stm32mp13-regulator.h b/include/dt-bindings/regulator/st,stm32mp13-regulator.h deleted file mode 100644 index b3a974dfc58..00000000000 --- a/include/dt-bindings/regulator/st,stm32mp13-regulator.h +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */ -/* - * Copyright (C) 2022, STMicroelectronics - All Rights Reserved - */ - -#ifndef __DT_BINDINGS_REGULATOR_ST_STM32MP13_REGULATOR_H -#define __DT_BINDINGS_REGULATOR_ST_STM32MP13_REGULATOR_H - -/* SCMI voltage domains identifiers */ - -/* SOC Internal regulators */ -#define VOLTD_SCMI_REG11 0 -#define VOLTD_SCMI_REG18 1 -#define VOLTD_SCMI_USB33 2 -#define VOLTD_SCMI_SDMMC1_IO 3 -#define VOLTD_SCMI_SDMMC2_IO 4 -#define VOLTD_SCMI_VREFBUF 5 - -/* STPMIC1 regulators */ -#define VOLTD_SCMI_STPMIC1_BUCK1 6 -#define VOLTD_SCMI_STPMIC1_BUCK2 7 -#define VOLTD_SCMI_STPMIC1_BUCK3 8 -#define VOLTD_SCMI_STPMIC1_BUCK4 9 -#define VOLTD_SCMI_STPMIC1_LDO1 10 -#define VOLTD_SCMI_STPMIC1_LDO2 11 -#define VOLTD_SCMI_STPMIC1_LDO3 12 -#define VOLTD_SCMI_STPMIC1_LDO4 13 -#define VOLTD_SCMI_STPMIC1_LDO5 14 -#define VOLTD_SCMI_STPMIC1_LDO6 15 -#define VOLTD_SCMI_STPMIC1_VREFDDR 16 -#define VOLTD_SCMI_STPMIC1_BOOST 17 -#define VOLTD_SCMI_STPMIC1_PWR_SW1 18 -#define VOLTD_SCMI_STPMIC1_PWR_SW2 19 - -/* External regulators */ -#define VOLTD_SCMI_REGU0 20 -#define VOLTD_SCMI_REGU1 21 -#define VOLTD_SCMI_REGU2 22 -#define VOLTD_SCMI_REGU3 23 -#define VOLTD_SCMI_REGU4 24 - -#endif /*__DT_BINDINGS_REGULATOR_ST_STM32MP13_REGULATOR_H */ diff --git a/include/dt-bindings/reset/stm32mp1-resets.h b/include/dt-bindings/reset/stm32mp1-resets.h deleted file mode 100644 index 9071f139649..00000000000 --- a/include/dt-bindings/reset/stm32mp1-resets.h +++ /dev/null @@ -1,123 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ -/* - * Copyright (C) STMicroelectronics 2018 - All Rights Reserved - * Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics. - */ - -#ifndef _DT_BINDINGS_STM32MP1_RESET_H_ -#define _DT_BINDINGS_STM32MP1_RESET_H_ - -#define MCU_HOLD_BOOT_R 2144 -#define LTDC_R 3072 -#define DSI_R 3076 -#define DDRPERFM_R 3080 -#define USBPHY_R 3088 -#define SPI6_R 3136 -#define I2C4_R 3138 -#define I2C6_R 3139 -#define USART1_R 3140 -#define STGEN_R 3156 -#define GPIOZ_R 3200 -#define CRYP1_R 3204 -#define HASH1_R 3205 -#define RNG1_R 3206 -#define AXIM_R 3216 -#define GPU_R 3269 -#define ETHMAC_R 3274 -#define FMC_R 3276 -#define QSPI_R 3278 -#define SDMMC1_R 3280 -#define SDMMC2_R 3281 -#define CRC1_R 3284 -#define USBH_R 3288 -#define MDMA_R 3328 -#define MCU_R 8225 -#define TIM2_R 19456 -#define TIM3_R 19457 -#define TIM4_R 19458 -#define TIM5_R 19459 -#define TIM6_R 19460 -#define TIM7_R 19461 -#define TIM12_R 16462 -#define TIM13_R 16463 -#define TIM14_R 16464 -#define LPTIM1_R 19465 -#define SPI2_R 19467 -#define SPI3_R 19468 -#define USART2_R 19470 -#define USART3_R 19471 -#define UART4_R 19472 -#define UART5_R 19473 -#define UART7_R 19474 -#define UART8_R 19475 -#define I2C1_R 19477 -#define I2C2_R 19478 -#define I2C3_R 19479 -#define I2C5_R 19480 -#define SPDIF_R 19482 -#define CEC_R 19483 -#define DAC12_R 19485 -#define MDIO_R 19847 -#define TIM1_R 19520 -#define TIM8_R 19521 -#define TIM15_R 19522 -#define TIM16_R 19523 -#define TIM17_R 19524 -#define SPI1_R 19528 -#define SPI4_R 19529 -#define SPI5_R 19530 -#define USART6_R 19533 -#define SAI1_R 19536 -#define SAI2_R 19537 -#define SAI3_R 19538 -#define DFSDM_R 19540 -#define FDCAN_R 19544 -#define LPTIM2_R 19584 -#define LPTIM3_R 19585 -#define LPTIM4_R 19586 -#define LPTIM5_R 19587 -#define SAI4_R 19592 -#define SYSCFG_R 19595 -#define VREF_R 19597 -#define TMPSENS_R 19600 -#define PMBCTRL_R 19601 -#define DMA1_R 19648 -#define DMA2_R 19649 -#define DMAMUX_R 19650 -#define ADC12_R 19653 -#define USBO_R 19656 -#define SDMMC3_R 19664 -#define CAMITF_R 19712 -#define CRYP2_R 19716 -#define HASH2_R 19717 -#define RNG2_R 19718 -#define CRC2_R 19719 -#define HSEM_R 19723 -#define MBOX_R 19724 -#define GPIOA_R 19776 -#define GPIOB_R 19777 -#define GPIOC_R 19778 -#define GPIOD_R 19779 -#define GPIOE_R 19780 -#define GPIOF_R 19781 -#define GPIOG_R 19782 -#define GPIOH_R 19783 -#define GPIOI_R 19784 -#define GPIOJ_R 19785 -#define GPIOK_R 19786 - -/* SCMI reset domain identifiers */ -#define RST_SCMI_SPI6 0 -#define RST_SCMI_I2C4 1 -#define RST_SCMI_I2C6 2 -#define RST_SCMI_USART1 3 -#define RST_SCMI_STGEN 4 -#define RST_SCMI_GPIOZ 5 -#define RST_SCMI_CRYP1 6 -#define RST_SCMI_HASH1 7 -#define RST_SCMI_RNG1 8 -#define RST_SCMI_MDMA 9 -#define RST_SCMI_MCU 10 -#define RST_SCMI_MCU_HOLD_BOOT 11 - -#endif /* _DT_BINDINGS_STM32MP1_RESET_H_ */ diff --git a/include/dt-bindings/reset/stm32mp13-resets.h b/include/dt-bindings/reset/stm32mp13-resets.h deleted file mode 100644 index ecb37c7ddde..00000000000 --- a/include/dt-bindings/reset/stm32mp13-resets.h +++ /dev/null @@ -1,100 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */ -/* - * Copyright (C) STMicroelectronics 2018 - All Rights Reserved - * Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics. - */ - -#ifndef _DT_BINDINGS_STM32MP13_RESET_H_ -#define _DT_BINDINGS_STM32MP13_RESET_H_ - -#define TIM2_R 13568 -#define TIM3_R 13569 -#define TIM4_R 13570 -#define TIM5_R 13571 -#define TIM6_R 13572 -#define TIM7_R 13573 -#define LPTIM1_R 13577 -#define SPI2_R 13579 -#define SPI3_R 13580 -#define USART3_R 13583 -#define UART4_R 13584 -#define UART5_R 13585 -#define UART7_R 13586 -#define UART8_R 13587 -#define I2C1_R 13589 -#define I2C2_R 13590 -#define SPDIF_R 13594 -#define TIM1_R 13632 -#define TIM8_R 13633 -#define SPI1_R 13640 -#define USART6_R 13645 -#define SAI1_R 13648 -#define SAI2_R 13649 -#define DFSDM_R 13652 -#define FDCAN_R 13656 -#define LPTIM2_R 13696 -#define LPTIM3_R 13697 -#define LPTIM4_R 13698 -#define LPTIM5_R 13699 -#define SYSCFG_R 13707 -#define VREF_R 13709 -#define DTS_R 13712 -#define PMBCTRL_R 13713 -#define LTDC_R 13760 -#define DCMIPP_R 13761 -#define DDRPERFM_R 13768 -#define USBPHY_R 13776 -#define STGEN_R 13844 -#define USART1_R 13888 -#define USART2_R 13889 -#define SPI4_R 13890 -#define SPI5_R 13891 -#define I2C3_R 13892 -#define I2C4_R 13893 -#define I2C5_R 13894 -#define TIM12_R 13895 -#define TIM13_R 13896 -#define TIM14_R 13897 -#define TIM15_R 13898 -#define TIM16_R 13899 -#define TIM17_R 13900 -#define DMA1_R 13952 -#define DMA2_R 13953 -#define DMAMUX1_R 13954 -#define DMA3_R 13955 -#define DMAMUX2_R 13956 -#define ADC1_R 13957 -#define ADC2_R 13958 -#define USBO_R 13960 -#define GPIOA_R 14080 -#define GPIOB_R 14081 -#define GPIOC_R 14082 -#define GPIOD_R 14083 -#define GPIOE_R 14084 -#define GPIOF_R 14085 -#define GPIOG_R 14086 -#define GPIOH_R 14087 -#define GPIOI_R 14088 -#define TSC_R 14095 -#define PKA_R 14146 -#define SAES_R 14147 -#define CRYP1_R 14148 -#define HASH1_R 14149 -#define RNG1_R 14150 -#define AXIMC_R 14160 -#define MDMA_R 14208 -#define MCE_R 14209 -#define ETH1MAC_R 14218 -#define FMC_R 14220 -#define QSPI_R 14222 -#define SDMMC1_R 14224 -#define SDMMC2_R 14225 -#define CRC1_R 14228 -#define USBH_R 14232 -#define ETH2MAC_R 14238 - -/* SCMI reset domain identifiers */ -#define RST_SCMI_LTDC 0 -#define RST_SCMI_MDMA 1 - -#endif /* _DT_BINDINGS_STM32MP13_RESET_H_ */ diff --git a/include/dwc3-sti-glue.h b/include/dwc3-sti-glue.h deleted file mode 100644 index 546ffbaf7b4..00000000000 --- a/include/dwc3-sti-glue.h +++ /dev/null @@ -1,41 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics. - */ - -#ifndef __DWC3_STI_UBOOT_H_ -#define __DWC3_STI_UBOOT_H_ - -/* glue registers */ -#include <linux/bitops.h> -#define CLKRST_CTRL 0x00 -#define AUX_CLK_EN BIT(0) -#define SW_PIPEW_RESET_N BIT(4) -#define EXT_CFG_RESET_N BIT(8) - -#define XHCI_REVISION BIT(12) - -#define USB2_VBUS_MNGMNT_SEL1 0x2C -#define USB2_VBUS_UTMIOTG 0x1 - -#define SEL_OVERRIDE_VBUSVALID(n) ((n) << 0) -#define SEL_OVERRIDE_POWERPRESENT(n) ((n) << 4) -#define SEL_OVERRIDE_BVALID(n) ((n) << 8) - -/* Static DRD configuration */ -#define USB3_CONTROL_MASK 0xf77 - -#define USB3_DEVICE_NOT_HOST BIT(0) -#define USB3_FORCE_VBUSVALID BIT(1) -#define USB3_DELAY_VBUSVALID BIT(2) -#define USB3_SEL_FORCE_OPMODE BIT(4) -#define USB3_FORCE_OPMODE(n) ((n) << 5) -#define USB3_SEL_FORCE_DPPULLDOWN2 BIT(8) -#define USB3_FORCE_DPPULLDOWN2 BIT(9) -#define USB3_SEL_FORCE_DMPULLDOWN2 BIT(10) -#define USB3_FORCE_DMPULLDOWN2 BIT(11) - -int sti_dwc3_init(enum usb_dr_mode mode); - -#endif /* __DWC3_STI_UBOOT_H_ */ diff --git a/include/efi_loader.h b/include/efi_loader.h index dcae6a731a0..e9c10819ba2 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -15,13 +15,13 @@ #include <efi_api.h> #include <image.h> #include <pe.h> +#include <setjmp.h> #include <linux/list.h> #include <linux/sizes.h> #include <linux/oid_registry.h> struct blk_desc; struct bootflow; -struct jmp_buf_data; #if CONFIG_IS_ENABLED(EFI_LOADER) @@ -129,17 +129,22 @@ static inline void efi_set_bootdev(const char *dev, const char *devnr, #if CONFIG_IS_ENABLED(NETDEVICES) && CONFIG_IS_ENABLED(EFI_LOADER) /* Call this to update the current device path of the efi net device */ -efi_status_t efi_net_set_dp(const char *dev, const char *server); +efi_status_t efi_net_new_dp(const char *dev, const char *server, struct udevice *udev); /* Call this to get the current device path of the efi net device */ -void efi_net_get_dp(struct efi_device_path **dp); +void efi_net_dp_from_dev(struct efi_device_path **dp, struct udevice *udev, bool cache_only); void efi_net_get_addr(struct efi_ipv4_address *ip, struct efi_ipv4_address *mask, - struct efi_ipv4_address *gw); + struct efi_ipv4_address *gw, + struct udevice *dev); void efi_net_set_addr(struct efi_ipv4_address *ip, struct efi_ipv4_address *mask, - struct efi_ipv4_address *gw); + struct efi_ipv4_address *gw, + struct udevice *dev); +#if IS_ENABLED(CONFIG_EFI_HTTP_PROTOCOL) efi_status_t efi_net_do_request(u8 *url, enum efi_http_method method, void **buffer, - u32 *status_code, ulong *file_size, char *headers_buffer); + u32 *status_code, ulong *file_size, char *headers_buffer, + struct efi_service_binding_protocol *parent); +#endif #define MAX_HTTP_HEADERS_SIZE SZ_64K #define MAX_HTTP_HEADERS 100 #define MAX_HTTP_HEADER_NAME 128 @@ -151,13 +156,16 @@ struct http_header { void efi_net_parse_headers(ulong *num_headers, struct http_header *headers); #else -static inline void efi_net_get_dp(struct efi_device_path **dp) { } +static inline void efi_net_dp_from_dev(struct efi_device_path **dp, + struct udevice *udev, bool cache_only) { } static inline void efi_net_get_addr(struct efi_ipv4_address *ip, struct efi_ipv4_address *mask, - struct efi_ipv4_address *gw) { } + struct efi_ipv4_address *gw, + struct udevice *dev) { } static inline void efi_net_set_addr(struct efi_ipv4_address *ip, struct efi_ipv4_address *mask, - struct efi_ipv4_address *gw) { } + struct efi_ipv4_address *gw, + struct udevice *dev) { } #endif /* Maximum number of configuration tables */ @@ -321,6 +329,8 @@ extern const efi_guid_t efi_guid_host_dev; #endif /* GUID of the EFI_BLOCK_IO_PROTOCOL */ extern const efi_guid_t efi_block_io_guid; +/* GUID of the EFI_SIMPLE_NETWORK_PROTOCOL */ +extern const efi_guid_t efi_net_guid; extern const efi_guid_t efi_global_variable_guid; extern const efi_guid_t efi_guid_console_control; extern const efi_guid_t efi_guid_device_path; @@ -485,7 +495,7 @@ struct efi_loaded_image_obj { efi_status_t *exit_status; efi_uintn_t *exit_data_size; u16 **exit_data; - struct jmp_buf_data *exit_jmp; + jmp_buf *exit_jmp; EFIAPI efi_status_t (*entry)(efi_handle_t image_handle, struct efi_system_table *st); u16 image_type; @@ -647,7 +657,8 @@ int efi_disk_create_partitions(efi_handle_t parent, struct blk_desc *desc, /* Called by bootefi to make GOP (graphical) interface available */ efi_status_t efi_gop_register(void); /* Called by bootefi to make the network interface available */ -efi_status_t efi_net_register(void); +efi_status_t efi_net_register(struct udevice *dev); +efi_status_t efi_net_do_start(struct udevice *dev); /* Called by efi_net_register to make the ip4 config2 protocol available */ efi_status_t efi_ipconfig_register(const efi_handle_t handle, struct efi_ip4_config2_protocol *ip4config); @@ -733,6 +744,10 @@ efi_status_t efi_search_protocol(const efi_handle_t handle, efi_status_t efi_add_protocol(const efi_handle_t handle, const efi_guid_t *protocol, void *protocol_interface); +/* Uninstall new protocol on a handle */ +efi_status_t efi_uninstall_protocol + (efi_handle_t handle, const efi_guid_t *protocol, + void *protocol_interface, bool preserve); /* Reinstall a protocol on a handle */ efi_status_t EFIAPI efi_reinstall_protocol_interface( efi_handle_t handle, @@ -748,6 +763,15 @@ efi_status_t EFIAPI efi_install_multiple_protocol_interfaces(efi_handle_t *handle, ...); efi_status_t EFIAPI efi_uninstall_multiple_protocol_interfaces(efi_handle_t handle, ...); +/* Connect and disconnect controller */ +efi_status_t EFIAPI efi_connect_controller(efi_handle_t controller_handle, + efi_handle_t *driver_image_handle, + struct efi_device_path *remain_device_path, + bool recursive); +efi_status_t EFIAPI efi_disconnect_controller( + efi_handle_t controller_handle, + efi_handle_t driver_image_handle, + efi_handle_t child_handle); /* Get handles that support a given protocol */ efi_status_t EFIAPI efi_locate_handle_buffer( enum efi_locate_search_type search_type, @@ -768,6 +792,8 @@ efi_status_t efi_create_event(uint32_t type, efi_uintn_t notify_tpl, void *context), void *notify_context, const efi_guid_t *group, struct efi_event **event); +/* Call this to close an event */ +efi_status_t EFIAPI efi_close_event(struct efi_event *event); /* Call this to set a timer */ efi_status_t efi_set_timer(struct efi_event *event, enum efi_timer_delay type, uint64_t trigger_time); @@ -852,21 +878,6 @@ efi_status_t efi_get_memory_map(efi_uintn_t *memory_map_size, /* Adds a range into the EFI memory map */ efi_status_t efi_add_memory_map(u64 start, u64 size, int memory_type); -/** - * efi_add_memory_map_pg() - add pages to the memory map - * - * @start: start address, must be a multiple of - * EFI_PAGE_SIZE - * @pages: number of pages to add - * @memory_type: type of memory added - * @overlap_conventional: region may only overlap free(conventional) - * memory - * Return: status code - */ -efi_status_t efi_add_memory_map_pg(u64 start, u64 pages, - int memory_type, - bool overlap_conventional); - /* Called by board init to initialize the EFI drivers */ efi_status_t efi_driver_init(void); /* Called when a block device is added */ @@ -922,8 +933,8 @@ struct efi_device_path *efi_dp_from_part(struct blk_desc *desc, int part); struct efi_device_path *efi_dp_part_node(struct blk_desc *desc, int part); struct efi_device_path *efi_dp_from_file(const struct efi_device_path *dp, const char *path); -struct efi_device_path *efi_dp_from_eth(void); -struct efi_device_path *efi_dp_from_http(const char *server); +struct efi_device_path *efi_dp_from_eth(struct udevice *dev); +struct efi_device_path *efi_dp_from_http(const char *server, struct udevice *dev); struct efi_device_path *efi_dp_from_mem(uint32_t mem_type, uint64_t start_address, size_t size); @@ -1264,6 +1275,21 @@ efi_status_t efi_disk_get_device_name(const efi_handle_t handle, char *buf, int void efi_add_known_memory(void); /** + * efi_map_update_notify() - notify EFI of memory map changes + * + * @addr: start of memory area + * @size: size of memory area + * @op: type of change + * Return: 0 if change could be processed + */ +#ifdef CONFIG_EFI_LOADER +int efi_map_update_notify(phys_addr_t addr, phys_size_t size, + enum lmb_map_op op); +#else +#define efi_map_update_notify(addr, size, op) (0) +#endif + +/** * efi_load_option_dp_join() - join device-paths for load option * * @dp: in: binary device-path, out: joined device-path diff --git a/include/efi_tcg2.h b/include/efi_tcg2.h index 8dfb1bc9527..7ed88809913 100644 --- a/include/efi_tcg2.h +++ b/include/efi_tcg2.h @@ -28,8 +28,6 @@ #define EFI_TCG2_MAX_PCR_INDEX 23 #define EFI_TCG2_FINAL_EVENTS_TABLE_VERSION 1 -#define TPM2_EVENT_LOG_SIZE CONFIG_EFI_TCG2_PROTOCOL_EVENTLOG_SIZE - typedef u32 efi_tcg_event_log_bitmap; typedef u32 efi_tcg_event_log_format; typedef u32 efi_tcg_event_algorithm_bitmap; diff --git a/include/env/pg-wcom/common.env b/include/env/pg-wcom/common.env index 4b660cebd67..5f2ba1c4090 100644 --- a/include/env/pg-wcom/common.env +++ b/include/env/pg-wcom/common.env @@ -22,7 +22,6 @@ add_default=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${ WCOM_UBI_LINUX_MTD addpanic=setenv bootargs ${bootargs} panic=1 panic_on_oops=1 -altbootcmd=run bootcmd backup_bank=0 boot=bootm ${load_addr_r} - ${fdt_addr_r} diff --git a/include/env/phytec/k3_dfu.env b/include/env/phytec/k3_dfu.env new file mode 100644 index 00000000000..0cba87da99d --- /dev/null +++ b/include/env/phytec/k3_dfu.env @@ -0,0 +1,3 @@ +dfu_alt_info_ram= + tispl.bin ram 0x80080000 0x200000; + u-boot.img ram 0x81000000 0x400000 diff --git a/include/env/phytec/k3_mmc.env b/include/env/phytec/k3_mmc.env index ad8d3a8b764..3f67e312f65 100644 --- a/include/env/phytec/k3_mmc.env +++ b/include/env/phytec/k3_mmc.env @@ -11,6 +11,7 @@ mmcargs=setenv bootargs console=${console} earlycon=${earlycon} root=/dev/mmcblk${mmcdev}p${mmcroot} ${raucargs} rootwait rw + ${optargs} mmcloadimage=load mmc ${mmcdev}:${mmcpart} ${kernel_addr_r} Image mmcloadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile} mmcboot=if test ${doraucboot} = 1; then run raucinit; fi; diff --git a/include/env/phytec/k3_net.env b/include/env/phytec/k3_net.env index 377e406688d..8ad1cb7b0c2 100644 --- a/include/env/phytec/k3_net.env +++ b/include/env/phytec/k3_net.env @@ -9,7 +9,7 @@ #include <env/phytec/overlays.env> netargs=setenv bootargs console=${console} root=/dev/nfs ip=dhcp rw - nfsroot=${serverip}:${nfsroot},vers=4,tcp + nfsroot=${serverip}:${nfsroot},vers=4,tcp ${optargs} netloadimage=${net_fetch_cmd} ${kernel_addr_r} ${serverip}:/Image netloadfdt=${net_fetch_cmd} ${fdt_addr_r} ${serverip}:/${fdtfile} netboot=run netargs; diff --git a/include/env/phytec/k3_spi.env b/include/env/phytec/k3_spi.env index 97d3a157058..8e9cfce3b4c 100644 --- a/include/env/phytec/k3_spi.env +++ b/include/env/phytec/k3_spi.env @@ -6,7 +6,7 @@ /* Logic for TI K3 based SoCs to boot from an OSPI/QSPI NOR flash. */ -spiargs=setenv bootargs console=${console} earlycon=${earlycon} +spiargs=setenv bootargs console=${console} earlycon=${earlycon} ${optargs} spiloadimage=sf read ${kernel_addr_r} ${spi_image_addr} ${size_kern} spiloadfdt=sf read ${fdt_addr_r} ${spi_fdt_addr} ${size_fdt} spiloadramdisk=sf read ${ramdisk_addr_r} ${spi_ramdisk_addr} ${size_fs} diff --git a/include/env/ti/mmc.h b/include/env/ti/mmc.h index d07189baaf4..dbb0e3559ea 100644 --- a/include/env/ti/mmc.h +++ b/include/env/ti/mmc.h @@ -44,6 +44,7 @@ "mmcloados=" \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if run loadfdt; then " \ + "run get_overlay_mmc;" \ "bootz ${loadaddr} - ${fdtaddr}; " \ "else " \ "if test ${boot_fdt} = try; then " \ diff --git a/include/env_default.h b/include/env_default.h index aa3dd40f3fa..60c39f9853f 100644 --- a/include/env_default.h +++ b/include/env_default.h @@ -115,6 +115,9 @@ const char default_environment[] = { #if defined(CONFIG_BOOTCOUNT_BOOTLIMIT) && (CONFIG_BOOTCOUNT_BOOTLIMIT > 0) "bootlimit=" __stringify(CONFIG_BOOTCOUNT_BOOTLIMIT)"\0" #endif +#ifdef CONFIG_BOOTCOUNT_ALTBOOTCMD + "altbootcmd=" CONFIG_BOOTCOUNT_ALTBOOTCMD "\0" +#endif #ifdef CONFIG_MTDIDS_DEFAULT "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" #endif diff --git a/include/fat.h b/include/fat.h index 3dce99a23cf..ca97880de12 100644 --- a/include/fat.h +++ b/include/fat.h @@ -206,6 +206,7 @@ int fat_opendir(const char *filename, struct fs_dir_stream **dirsp); int fat_readdir(struct fs_dir_stream *dirs, struct fs_dirent **dentp); void fat_closedir(struct fs_dir_stream *dirs); int fat_unlink(const char *filename); +int fat_rename(const char *old_path, const char *new_path); int fat_mkdir(const char *dirname); void fat_close(void); void *fat_next_cluster(fat_itr *itr, unsigned int *nbytes); diff --git a/include/fpga.h b/include/fpga.h index 44f2755a3f1..4cc44164b2f 100644 --- a/include/fpga.h +++ b/include/fpga.h @@ -58,7 +58,7 @@ typedef enum { void fpga_init(void); int fpga_add(fpga_type devtype, void *desc); int fpga_count(void); -const fpga_desc *const fpga_get_desc(int devnum); +const fpga_desc *fpga_get_desc(int devnum); int fpga_is_partial_data(int devnum, size_t img_len); #if CONFIG_IS_ENABLED(FPGA) int fpga_load(int devnum, const void *buf, size_t bsize, @@ -78,8 +78,8 @@ int fpga_loadbitstream(int devnum, char *fpgadata, size_t size, bitstream_type bstype); int fpga_dump(int devnum, const void *buf, size_t bsize); int fpga_info(int devnum); -const fpga_desc *const fpga_validate(int devnum, const void *buf, - size_t bsize, char *fn); +const fpga_desc *fpga_validate(int devnum, const void *buf, + size_t bsize, char *fn); int fpga_compatible2flag(int devnum, const char *compatible); #endif /* _FPGA_H_ */ diff --git a/include/fs.h b/include/fs.h index 2474880385d..54449faf2e5 100644 --- a/include/fs.h +++ b/include/fs.h @@ -86,7 +86,7 @@ int fs_set_blk_dev_with_part(struct blk_desc *desc, int part); * * Many file functions implicitly call fs_close(), e.g. fs_closedir(), * fs_exist(), fs_ln(), fs_ls(), fs_mkdir(), fs_read(), fs_size(), fs_write(), - * fs_unlink(). + * fs_unlink(), fs_rename(). */ void fs_close(void); @@ -270,6 +270,18 @@ int fs_unlink(const char *filename); */ int fs_mkdir(const char *filename); +/** + * fs_rename - rename/move a file or directory + * + * @old_path: existing path of the file/directory to rename + * @new_path: new path of the file/directory. If this points to an existing + * file or empty directory, the existing file/directory will be unlinked. + * If this points to a non-empty directory, the rename will fail. + * + * Return: 0 on success, -1 on error conditions + */ +int fs_rename(const char *old_path, const char *new_path); + /* * Common implementation for various filesystem commands, optionally limited * to a specific filesystem type via the fstype parameter. @@ -290,6 +302,8 @@ int do_mkdir(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[], int fstype); int do_ln(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[], int fstype); +int do_mv(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[], + int fstype); /* * Determine the UUID of the specified filesystem and print it. Optionally it is diff --git a/include/image.h b/include/image.h index 8a9f779d3ff..c1db8383459 100644 --- a/include/image.h +++ b/include/image.h @@ -232,6 +232,7 @@ enum image_type_t { IH_TYPE_FDT_LEGACY, /* Binary Flat Device Tree Blob in a Legacy Image */ IH_TYPE_RENESAS_SPKG, /* Renesas SPKG image */ IH_TYPE_STARFIVE_SPL, /* StarFive SPL image */ + IH_TYPE_TFA_BL31, /* TFA BL31 image */ IH_TYPE_COUNT, /* Number of image types */ }; @@ -1687,6 +1688,24 @@ struct sig_header_s { */ int image_pre_load(ulong addr); +#if defined(USE_HOSTCC) +/** + * rsa_verify_openssl() - Verify a signature against some data with openssl API + * + * Verify a RSA PKCS1.5/PSS signature against an expected hash. + * + * @info: Specifies the key and algorithms + * @region: Pointer to the input data + * @region_count: Number of region + * @sig: Signature + * @sig_len: Number of bytes in the signature + * Return: 0 if verified, -ve on error + */ +int rsa_verify_openssl(struct image_sign_info *info, + const struct image_region region[], int region_count, + uint8_t *sig, uint sig_len); +#endif + /** * fit_image_verify_required_sigs() - Verify signatures marked as 'required' * diff --git a/include/interrupt.h b/include/interrupt.h index 46ef2e196d4..6ea28b54a56 100644 --- a/include/interrupt.h +++ b/include/interrupt.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include <asm/setjmp.h> +#include <setjmp.h> /** * struct resume_data - data for resume after interrupt diff --git a/include/led.h b/include/led.h index 64247cd3a70..2a7f38bf84b 100644 --- a/include/led.h +++ b/include/led.h @@ -53,6 +53,11 @@ struct udevice; +/* + * value imported from linux:include/linux/uapi/linux/uleds.h + */ +#define LED_MAX_NAME_SIZE 64 + enum led_state_t { LEDST_OFF = 0, LEDST_ON = 1, @@ -81,11 +86,14 @@ struct led_sw_blink { * * @label: LED label * @default_state: LED default state + * @name: LED name, derived from function, color or function-enumerator + * property. * @sw_blink: LED software blink struct */ struct led_uc_plat { const char *label; enum led_state_t default_state; + char name[LED_MAX_NAME_SIZE]; #ifdef CONFIG_LED_SW_BLINK struct led_sw_blink *sw_blink; #endif diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index 2d85b392465..3e80b134063 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -132,6 +132,17 @@ void nand_wait_ready(struct mtd_info *mtd); #define NAND_DATA_IFACE_CHECK_ONLY -1 /* + * There are different places where the manufacturer stores the factory bad + * block markers. + * + * Position within the block: Each of these pages needs to be checked for a + * bad block marking pattern. + */ +#define NAND_BBM_FIRSTPAGE BIT(24) +#define NAND_BBM_SECONDPAGE BIT(25) +#define NAND_BBM_LASTPAGE BIT(26) + +/* * Constants for ECC_MODES */ typedef enum { @@ -981,6 +992,7 @@ struct nand_chip { struct nand_bbt_descr *bbt_md; struct nand_bbt_descr *badblock_pattern; + int cur_cs; void *priv; diff --git a/include/linux/string.h b/include/linux/string.h index 27b2beb9ddb..d943fcce690 100644 --- a/include/linux/string.h +++ b/include/linux/string.h @@ -72,6 +72,9 @@ extern char * strrchr(const char *,int); #ifndef __HAVE_ARCH_STRSTR extern char * strstr(const char *,const char *); #endif +#ifndef __HAVE_ARCH_STRNSTR +extern char *strnstr(const char *, const char *, size_t); +#endif #ifndef __HAVE_ARCH_STRLEN extern __kernel_size_t strlen(const char *); #endif diff --git a/include/lmb.h b/include/lmb.h index d9d7435a431..09297a4f530 100644 --- a/include/lmb.h +++ b/include/lmb.h @@ -32,6 +32,18 @@ #define LMB_NONOTIFY BIT(2) /** + * enum lmb_map_op - memory map operation + */ +enum lmb_map_op { + /** @LMB_MAP_OP_RESERVE: reserve memory */ + LMB_MAP_OP_RESERVE = 1, + /** @LMB_MAP_OP_FREE: free memory */ + LMB_MAP_OP_FREE, + /** @LMB_MAP_OP_ADD: add memory */ + LMB_MAP_OP_ADD, +}; + +/** * struct lmb_region - Description of one region * @base: Base address of the region * @size: Size of the region diff --git a/include/mcheck.h b/include/mcheck.h index bd506ae6291..4b11751ebcc 100644 --- a/include/mcheck.h +++ b/include/mcheck.h @@ -1,18 +1,7 @@ -/* SPDX-License-Identifier: GPL-2.1+ */ +/* SPDX-License-Identifier: LGPL-2.1-or-later */ /* * Copyright (C) 1996-2024 Free Software Foundation, Inc. * This file is part of the GNU C Library. - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * <https://www.gnu.org/licenses/>. */ #ifndef _MCHECK_H #define _MCHECK_H 1 diff --git a/include/miiphy.h b/include/miiphy.h index 5abffd8fb6b..00d0b9b6a43 100644 --- a/include/miiphy.h +++ b/include/miiphy.h @@ -33,8 +33,6 @@ int miiphy_is_1000base_x(const char *devname, unsigned char addr); int miiphy_link(const char *devname, unsigned char addr); #endif -void miiphy_init(void); - int miiphy_set_current_dev(const char *devname); const char *miiphy_get_current_dev(void); struct mii_dev *mdio_get_current_dev(void); @@ -63,35 +61,19 @@ void mdio_list_devices(void); #define BB_MII_DEVNAME "bb_miiphy" -struct bb_miiphy_bus { - char name[16]; - int (*init)(struct bb_miiphy_bus *bus); - int (*mdio_active)(struct bb_miiphy_bus *bus); - int (*mdio_tristate)(struct bb_miiphy_bus *bus); - int (*set_mdio)(struct bb_miiphy_bus *bus, int v); - int (*get_mdio)(struct bb_miiphy_bus *bus, int *v); - int (*set_mdc)(struct bb_miiphy_bus *bus, int v); - int (*delay)(struct bb_miiphy_bus *bus); -#ifdef CONFIG_BITBANGMII_MULTI - void *priv; -#endif +struct bb_miiphy_bus_ops { + int (*mdio_active)(struct mii_dev *miidev); + int (*mdio_tristate)(struct mii_dev *miidev); + int (*set_mdio)(struct mii_dev *miidev, int v); + int (*get_mdio)(struct mii_dev *miidev, int *v); + int (*set_mdc)(struct mii_dev *miidev, int v); + int (*delay)(struct mii_dev *miidev); }; -extern struct bb_miiphy_bus bb_miiphy_buses[]; -extern int bb_miiphy_buses_num; - -/** - * bb_miiphy_init() - Initialize bit-banged MII bus driver - * - * It is called during the generic post-relocation init sequence. - * - * Return: 0 if OK - */ -int bb_miiphy_init(void); - -int bb_miiphy_read(struct mii_dev *miidev, int addr, int devad, int reg); -int bb_miiphy_write(struct mii_dev *miidev, int addr, int devad, int reg, - u16 value); +int bb_miiphy_read(struct mii_dev *miidev, const struct bb_miiphy_bus_ops *ops, + int addr, int devad, int reg); +int bb_miiphy_write(struct mii_dev *miidev, const struct bb_miiphy_bus_ops *ops, + int addr, int devad, int reg, u16 value); #endif /* phy seed setup */ diff --git a/include/net-common.h b/include/net-common.h index 29d31f37263..1d507b13b06 100644 --- a/include/net-common.h +++ b/include/net-common.h @@ -291,6 +291,7 @@ struct eth_ops { #define eth_get_ops(dev) ((struct eth_ops *)(dev)->driver->ops) struct udevice *eth_get_dev(void); /* get the current device */ +void eth_set_dev(struct udevice *dev); /* set a device */ unsigned char *eth_get_ethaddr(void); /* get the current device MAC */ int eth_rx(void); /* Check for received packets */ void eth_halt(void); /* stop SCC */ diff --git a/include/net-lwip.h b/include/net-lwip.h index 4d7f9387d1d..64e5c720560 100644 --- a/include/net-lwip.h +++ b/include/net-lwip.h @@ -10,6 +10,7 @@ enum proto_t { TFTPGET }; +void net_lwip_set_current(void); struct netif *net_lwip_new_netif(struct udevice *udev); struct netif *net_lwip_new_netif_noip(struct udevice *udev); void net_lwip_remove_netif(struct netif *netif); diff --git a/include/power/tps65941.h b/include/power/tps65941.h index cec85333f0b..a026ec56958 100644 --- a/include/power/tps65941.h +++ b/include/power/tps65941.h @@ -21,10 +21,11 @@ #define TPS65941_BUCK_VOLT_MAX 3340000 #define TPS65941_BUCK_MODE_MASK 0x1 -#define TPS65941_LDO_VOLT_MASK 0x3E +#define TPS65941_LDO_VOLT_MASK 0x7E #define TPS65941_LDO_VOLT_MAX_HEX 0x3A #define TPS65941_LDO_VOLT_MIN_HEX 0x4 #define TPS65941_LDO_VOLT_MAX 3300000 +#define TPS65941_LDO_VOLT_MIN 600000 #define TPS65941_LDO_MODE_MASK 0x1 #define TPS65941_LDO_BYPASS_EN 0x80 #define TP65941_BUCK_CONF_SLEW_MASK 0x7 diff --git a/include/serial.h b/include/serial.h index e5f6d984d28..0a707ca730d 100644 --- a/include/serial.h +++ b/include/serial.h @@ -48,26 +48,6 @@ extern int serial_assign(const char *name); extern void serial_reinit_all(void); int serial_initialize(void); -/* For usbtty */ -#ifdef CONFIG_USB_TTY - -struct stdio_dev; - -int usbtty_getc(struct stdio_dev *dev); -void usbtty_putc(struct stdio_dev *dev, const char c); -void usbtty_puts(struct stdio_dev *dev, const char *str); -int usbtty_tstc(struct stdio_dev *dev); - -#else - -/* stubs */ -#define usbtty_getc(dev) 0 -#define usbtty_putc(dev, a) -#define usbtty_puts(dev, a) -#define usbtty_tstc(dev) 0 - -#endif /* CONFIG_USB_TTY */ - struct udevice; enum serial_par { diff --git a/include/setjmp.h b/include/setjmp.h new file mode 100644 index 00000000000..37d3a8af85d --- /dev/null +++ b/include/setjmp.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef _SETJMP_H_ +#define _SETJMP_H_ 1 + +#ifdef CONFIG_HAVE_SETJMP +#include <asm/setjmp.h> +#else +struct jmp_buf_data { +}; +#endif + +/** + * typedef jmp_buf - information needed to restore a calling environment + */ +typedef struct jmp_buf_data jmp_buf[1]; + +/** + * setjmp() - prepare for a long jump + * + * Registers, the stack pointer, and the return address are saved in the + * jump bufffer. The function returns zero afterwards. When longjmp() is + * executed the function returns a second time with a non-zero value. + * + * @env: jump buffer used to store register values + * Return: 0 after setting up jump buffer, non-zero after longjmp() + */ +int setjmp(jmp_buf env); + +/** + * longjmp() - long jump + * + * Jump back to the address and the register state saved by setjmp(). + * + * @env: jump buffer + * @val: value to be returned by setjmp(), 0 is replaced by 1 + */ +void longjmp(jmp_buf env, int val); + +#endif /* _SETJMP_H_ */ diff --git a/include/spl.h b/include/spl.h index 7155e9c67aa..850c64d4b19 100644 --- a/include/spl.h +++ b/include/spl.h @@ -345,7 +345,7 @@ typedef ulong (*spl_load_reader)(struct spl_load_info *load, ulong sector, * @priv: Private data for the device * @bl_len: Block length for reading in bytes * @phase: Image phase to load - * @fit_loaded: true if the FIT has been loaded, except for external data + * @no_fdt_update: true to update the FDT with any loadables that are loaded */ struct spl_load_info { spl_load_reader read; @@ -355,7 +355,7 @@ struct spl_load_info { #endif #if CONFIG_IS_ENABLED(BOOTMETH_VBE) u8 phase; - u8 fit_loaded; + u8 fdt_update; #endif }; @@ -395,12 +395,20 @@ static inline enum image_phase_t xpl_get_phase(struct spl_load_info *info) #endif } -static inline bool xpl_get_fit_loaded(struct spl_load_info *info) +static inline void xpl_set_fdt_update(struct spl_load_info *info, + bool fdt_update) { #if CONFIG_IS_ENABLED(BOOTMETH_VBE) - return info->fit_loaded; + info->fdt_update = fdt_update; +#endif +} + +static inline enum image_phase_t xpl_get_fdt_update(struct spl_load_info *info) +{ +#if CONFIG_IS_ENABLED(BOOTMETH_VBE) + return info->fdt_update; #else - return false; + return true; #endif } @@ -415,6 +423,7 @@ static inline void spl_load_init(struct spl_load_info *load, load->priv = priv; spl_set_bl_len(load, bl_len); xpl_set_phase(load, IH_PHASE_NONE); + xpl_set_fdt_update(load, true); } /* diff --git a/include/spl_load.h b/include/spl_load.h index 935f7d336f2..525e0c9e86c 100644 --- a/include/spl_load.h +++ b/include/spl_load.h @@ -20,13 +20,15 @@ static inline int _spl_load(struct spl_image_info *spl_image, ulong base_offset, image_offset, overhead; int read, ret; + log_debug("\nloading hdr from %lx to %p\n", (ulong)offset, header); read = info->read(info, offset, ALIGN(sizeof(*header), spl_get_bl_len(info)), header); if (read < (int)sizeof(*header)) return -EIO; if (image_get_magic(header) == FDT_MAGIC) { - if (IS_ENABLED(CONFIG_SPL_LOAD_FIT_FULL)) { + log_debug("Found FIT\n"); + if (CONFIG_IS_ENABLED(LOAD_FIT_FULL)) { void *buf; /* @@ -48,9 +50,12 @@ static inline int _spl_load(struct spl_image_info *spl_image, return spl_parse_image_header(spl_image, bootdev, buf); } - if (IS_ENABLED(CONFIG_SPL_LOAD_FIT)) + if (CONFIG_IS_ENABLED(LOAD_FIT)) { + log_debug("Simple loading\n"); return spl_load_simple_fit(spl_image, info, offset, header); + } + log_debug("No FIT support\n"); } if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER) && diff --git a/include/stdio_dev.h b/include/stdio_dev.h index 4e3c4708f80..f7f9c10199e 100644 --- a/include/stdio_dev.h +++ b/include/stdio_dev.h @@ -101,7 +101,6 @@ struct stdio_dev *stdio_clone(struct stdio_dev *dev); int drv_lcd_init(void); int drv_video_init(void); int drv_keyboard_init(void); -int drv_usbtty_init(void); int drv_usbacm_init(void); int drv_nc_init(void); int drv_jtag_console_init(void); diff --git a/include/sysinfo.h b/include/sysinfo.h index ba2ac273e8e..e87cf969fcd 100644 --- a/include/sysinfo.h +++ b/include/sysinfo.h @@ -57,6 +57,7 @@ enum sysinfo_id { SYSID_SM_SYSTEM_WAKEUP, SYSID_SM_SYSTEM_SKU, SYSID_SM_SYSTEM_FAMILY, + SYSID_SM_SYSTEM_UUID, /* Baseboard (or Module) Information (Type 2) */ SYSID_SM_BASEBOARD_MANUFACTURER, @@ -151,6 +152,8 @@ enum sysinfo_id { /* For show_board_info() */ SYSID_BOARD_MODEL, SYSID_BOARD_MANUFACTURER, + SYSID_BOARD_MAC_ADDR, + SYSID_BOARD_RAM_SIZE_MB, SYSID_PRIOR_STAGE_VERSION, SYSID_PRIOR_STAGE_DATE, @@ -221,6 +224,30 @@ struct sysinfo_ops { int (*get_data)(struct udevice *dev, int id, void **data, size_t *size); /** + * get_item_count() - Get the item count of the specific data area that + * describes the hardware setup. + * @dev: The sysinfo instance to gather the data. + * @id: A unique identifier for the data area to be get. + * + * Return: non-negative item count if OK, -ve on error. + */ + int (*get_item_count)(struct udevice *dev, int id); + + /** + * get_data_by_index() - Get a data value by index from the platform. + * + * @dev: The sysinfo instance to gather the data. + * @id: A unique identifier for the data area to be get. + * @index: The item index, starting from 0. + * @data: Pointer to the address of the data area. + * @size: Pointer to the size of the data area. + * + * Return: 0 if OK, -ve on error. + */ + int (*get_data_by_index)(struct udevice *dev, int id, int index, + void **data, size_t *size); + + /** * get_fit_loadable - Get the name of an image to load from FIT * This function can be used to provide the image names based on runtime * detection. A classic use-case would when DTBOs are used to describe @@ -304,6 +331,32 @@ int sysinfo_get_str(struct udevice *dev, int id, size_t size, char *val); int sysinfo_get_data(struct udevice *dev, int id, void **data, size_t *size); /** + * sysinfo_get_item_count() - Get the item count of the specific data area that + * describes the hardware setup. + * @dev: The sysinfo instance to gather the data. + * @id: A unique identifier for the data area to be get. + * + * Return: non-negative item count if OK, -EPERM if called before + * sysinfo_detect(), else -ve on error. + */ +int sysinfo_get_item_count(struct udevice *dev, int id); + +/** + * sysinfo_get_data_by_index() - Get a data value by index from the platform. + * + * @dev: The sysinfo instance to gather the data. + * @id: A unique identifier for the data area to be get. + * @index: The item index, starting from 0. + * @data: Pointer to the address of the data area. + * @size: Pointer to the size of the data area. + * + * Return: 0 if OK, -EPERM if called before sysinfo_detect(), else -ve on + * error. + */ +int sysinfo_get_data_by_index(struct udevice *dev, int id, int index, + void **data, size_t *size); + +/** * sysinfo_get() - Return the sysinfo device for the sysinfo in question. * @devp: Pointer to structure to receive the sysinfo device. * @@ -364,6 +417,18 @@ static inline int sysinfo_get_data(struct udevice *dev, int id, void **data, return -ENOSYS; } +static inline int sysinfo_get_item_count(struct udevice *dev, int id) +{ + return -ENOSYS; +} + +static inline int sysinfo_get_data_by_index(struct udevice *dev, int id, + int index, void **data, + size_t *size) +{ + return -ENOSYS; +} + static inline int sysinfo_get(struct udevice **devp) { return -ENOSYS; diff --git a/include/test/fdt_overlay.h b/include/test/fdt_overlay.h new file mode 100644 index 00000000000..251ad0ec97a --- /dev/null +++ b/include/test/fdt_overlay.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2016 NextThing Co + * Copyright (c) 2016 Free Electrons + */ + +#ifndef __TEST_OVERLAY_H__ +#define __TEST_OVERLAY_H__ + +#include <test/test.h> + +/* Declare a new FDT-overlay test */ +#define FDT_OVERLAY_TEST(_name, _flags) UNIT_TEST(_name, _flags, fdt_overlay) + +/* Declare init for FDT-overlay test */ +#define FDT_OVERLAY_TEST_INIT(_name, _flags) \ + UNIT_TEST_INIT(_name, _flags, fdt_overlay) + +#endif /* __TEST_OVERLAY_H__ */ diff --git a/include/test/optee.h b/include/test/optee.h index f4255b39ee3..0a548a59e83 100644 --- a/include/test/optee.h +++ b/include/test/optee.h @@ -8,7 +8,9 @@ #include <test/test.h> -/* Declare a new environment test */ +/* Declare a new optee test */ #define OPTEE_TEST(_name, _flags) UNIT_TEST(_name, _flags, optee) +#define OPTEE_TEST_INIT(_name, _flags) UNIT_TEST_INIT(_name, _flags, optee) +#define OPTEE_TEST_UNINIT(_name, _flags) UNIT_TEST_UNINIT(_name, _flags, optee) #endif /* __TEST_OPTEE_H__ */ diff --git a/include/test/overlay.h b/include/test/overlay.h deleted file mode 100644 index 5dc98399ce7..00000000000 --- a/include/test/overlay.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2016 NextThing Co - * Copyright (c) 2016 Free Electrons - */ - -#ifndef __TEST_OVERLAY_H__ -#define __TEST_OVERLAY_H__ - -#include <test/test.h> - -/* Declare a new environment test */ -#define OVERLAY_TEST(_name, _flags) UNIT_TEST(_name, _flags, overlay) - -#endif /* __TEST_OVERLAY_H__ */ diff --git a/include/test/suites.h b/include/test/suites.h deleted file mode 100644 index 774dd893378..00000000000 --- a/include/test/suites.h +++ /dev/null @@ -1,43 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * (C) Copyright 2015 - * Joe Hershberger, National Instruments, joe.hershberger@ni.com - */ - -#ifndef __TEST_SUITES_H__ -#define __TEST_SUITES_H__ - -struct cmd_tbl; -struct unit_test; -struct unit_test_state; - -/* 'command' functions normally called do_xxx where xxx is the command name */ -typedef int (*ut_cmd_func)(struct unit_test_state *uts, struct cmd_tbl *cmd, - int flags, int argc, char *const argv[]); - -/** - * cmd_ut_category() - Run a category of unit tests - * - * @uts: Unit-test state, which must be ready for use, i.e. ut_init_state() - * has been called. The caller is responsible for calling - * ut_uninit_state() after this function returns - * @name: Category name - * @prefix: Prefix of test name - * @tests: List of tests to run - * @n_ents: Number of tests in @tests - * @argc: Argument count provided. Must be >= 1. If this is 1 then all - * tests are run, otherwise only the one named @argv[1] is run. - * @argv: Arguments: argv[1] is the test to run (if @argc >= 2) - * Return: 0 if OK, CMD_RET_FAILURE on failure - */ -int cmd_ut_category(struct unit_test_state *uts, const char *name, - const char *prefix, struct unit_test *tests, int n_ents, - int argc, char *const argv[]); - -int do_ut_bootstd(struct unit_test_state *uts, struct cmd_tbl *cmdtp, int flag, - int argc, char *const argv[]); -int do_ut_optee(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); -int do_ut_overlay(struct unit_test_state *uts, struct cmd_tbl *cmdtp, int flag, - int argc, char *const argv[]); - -#endif /* __TEST_SUITES_H__ */ diff --git a/include/test/test.h b/include/test/test.h index bac43c81d63..0f2b68a5dee 100644 --- a/include/test/test.h +++ b/include/test/test.h @@ -16,11 +16,15 @@ * @skip_count: Number of tests that were skipped * @test_count: Number of tests run. If a test is run muiltiple times, only one * is counted + * @start: Timer value when test started + * @duration_ms: Suite duration in milliseconds */ struct ut_stats { int fail_count; int skip_count; int test_count; + ulong start; + ulong duration_ms; }; /* @@ -29,6 +33,8 @@ struct ut_stats { * @cur: Statistics for the current run * @total: Statistics for all test runs * @run_count: Number of times ut_run_list() has been called + * @worst: Sute which had the first per-text run time + * @worst_ms: Time taken by that test * @start: Store the starting mallinfo when doing leak test * @of_live: true to use livetree if available, false to use flattree * @of_root: Record of the livetree root node (used for setting up tests) @@ -52,6 +58,8 @@ struct unit_test_state { struct ut_stats cur; struct ut_stats total; int run_count; + const struct suite *worst; + int worst_ms; struct mallinfo start; struct device_node *of_root; bool of_live; @@ -92,6 +100,8 @@ enum ut_flags { UTF_ETH_BOOTDEV = BIT(9), /* enable Ethernet bootdevs */ UTF_SF_BOOTDEV = BIT(10), /* enable SPI flash bootdevs */ UFT_BLOBLIST = BIT(11), /* test changes gd->bloblist */ + UTF_INIT = BIT(12), /* test inits a suite */ + UTF_UNINIT = BIT(13), /* test uninits a suite */ }; /** @@ -139,6 +149,24 @@ struct unit_test { .func = _name, \ } +/* init function for unit-test suite (the 'A' makes it first) */ +#define UNIT_TEST_INIT(_name, _flags, _suite) \ + ll_entry_declare(struct unit_test, A ## _name, ut_ ## _suite) = { \ + .file = __FILE__, \ + .name = #_name, \ + .flags = (_flags) | UTF_INIT, \ + .func = _name, \ + } + +/* uninit function for unit-test suite (the 'aaa' makes it last) */ +#define UNIT_TEST_UNINIT(_name, _flags, _suite) \ + ll_entry_declare(struct unit_test, zzz ## _name, ut_ ## _suite) = { \ + .file = __FILE__, \ + .name = #_name, \ + .flags = (_flags) | UTF_UNINIT, \ + .func = _name, \ + } + /* Get the start of a list of unit tests for a particular suite */ #define UNIT_TEST_SUITE_START(_suite) \ ll_entry_start(struct unit_test, ut_ ## _suite) diff --git a/include/time.h b/include/time.h index 3b2ba091247..f5b86bf70fe 100644 --- a/include/time.h +++ b/include/time.h @@ -28,7 +28,7 @@ uint64_t get_timer_us(uint64_t base); */ unsigned long get_timer_us_long(unsigned long base); -/* +/** * timer_test_add_offset() * * Allow tests to add to the time reported through lib/time.c functions @@ -36,6 +36,19 @@ unsigned long get_timer_us_long(unsigned long base); */ void timer_test_add_offset(unsigned long offset); +#ifdef CONFIG_SANDBOX +/** + * timer_test_get_offset() + * + * Get the total offset currently being added the time + * + * Return:: number of milliseconds the system time has been advanced + */ +ulong timer_test_get_offset(void); +#else +static inline ulong timer_test_get_offset(void) { return 0; } +#endif + /** * usec_to_tick() - convert microseconds to clock ticks * diff --git a/include/u-boot/sha1.h b/include/u-boot/sha1.h index dd66258bbe9..c2d62e9cf0f 100644 --- a/include/u-boot/sha1.h +++ b/include/u-boot/sha1.h @@ -18,17 +18,7 @@ #include <linux/types.h> #if CONFIG_IS_ENABLED(MBEDTLS_LIB_CRYPTO) -/* - * FIXME: - * MbedTLS define the members of "mbedtls_sha256_context" as private, - * but "state" needs to be access by arch/arm/cpu/armv8/sha1_ce_glue. - * MBEDTLS_ALLOW_PRIVATE_ACCESS needs to be enabled to allow the external - * access. - * Directly including <external/mbedtls/library/common.h> is not allowed, - * since this will include <malloc.h> and break the sandbox test. - */ -#define MBEDTLS_ALLOW_PRIVATE_ACCESS - +#include "mbedtls_options.h" #include <mbedtls/sha1.h> #endif diff --git a/include/u-boot/sha256.h b/include/u-boot/sha256.h index d7a3403270b..2d86508332e 100644 --- a/include/u-boot/sha256.h +++ b/include/u-boot/sha256.h @@ -7,17 +7,7 @@ #include <linux/types.h> #if CONFIG_IS_ENABLED(MBEDTLS_LIB_CRYPTO) -/* - * FIXME: - * MbedTLS define the members of "mbedtls_sha256_context" as private, - * but "state" needs to be access by arch/arm/cpu/armv8/sha256_ce_glue. - * MBEDTLS_ALLOW_PRIVATE_ACCESS needs to be enabled to allow the external - * access. - * Directly including <external/mbedtls/library/common.h> is not allowed, - * since this will include <malloc.h> and break the sandbox test. - */ -#define MBEDTLS_ALLOW_PRIVATE_ACCESS - +#include "mbedtls_options.h" #include <mbedtls/sha256.h> #endif diff --git a/include/vbe.h b/include/vbe.h index 56bff63362f..61bfa0e557d 100644 --- a/include/vbe.h +++ b/include/vbe.h @@ -10,6 +10,8 @@ #ifndef __VBE_H #define __VBE_H +#include <linux/types.h> + /** * enum vbe_phase_t - current phase of VBE * @@ -26,12 +28,31 @@ enum vbe_phase_t { }; /** + * enum vbe_pick_t - indicates which firmware is picked + * + * @VBEFT_A: Firmware A + * @VBEFT_B: Firmware B + * @VBEFT_RECOVERY: Recovery firmware + */ +enum vbe_pick_t { + VBEP_A, + VBEP_B, + VBEP_RECOVERY, +}; + +/** * struct vbe_handoff - information about VBE progress * + * @offset: Offset of the FIT to use for SPL onwards + * @size: Size of the area containing the FIT * @phases: Indicates which phases used the VBE bootmeth (1 << PHASE_...) + * @pick: Indicates which firmware pick was used (enum vbe_pick_t) */ struct vbe_handoff { + ulong offset; + ulong size; u8 phases; + u8 pick; }; /** diff --git a/include/video_bridge.h b/include/video_bridge.h index 3b429eac578..00e9804565c 100644 --- a/include/video_bridge.h +++ b/include/video_bridge.h @@ -54,6 +54,19 @@ struct video_bridge_ops { int (*set_backlight)(struct udevice *dev, int percent); /** + * get_display_timing() - Get display timings from bridge. + * + * @dev: Bridge device containing the linked display timings + * @tim: Place to put timings + * @return 0 if OK, -ve on error + * + * This call it totally optional and useful mainly for integrated + * bridges with fixed output device. + */ + int (*get_display_timing)(struct udevice *dev, + struct display_timing *timing); + + /** * read_edid() - Read information from EDID * * @dev: Device to read from @@ -67,6 +80,7 @@ struct video_bridge_ops { #define video_bridge_get_ops(dev) \ ((struct video_bridge_ops *)(dev)->driver->ops) +#if CONFIG_IS_ENABLED(VIDEO_BRIDGE) /** * video_bridge_attach() - attach a video bridge * @@ -99,6 +113,14 @@ int video_bridge_set_active(struct udevice *dev, bool active); int video_bridge_check_attached(struct udevice *dev); /** + * video_bridge_get_display_timing() - Get display timings from bridge. + * + * @dev: Bridge device containing the linked display timings + * Return: 0 if OK, -ve on error + */ +int video_bridge_get_display_timing(struct udevice *dev, + struct display_timing *timing); +/** * video_bridge_read_edid() - Read information from EDID * * @dev: Device to read from @@ -107,5 +129,37 @@ int video_bridge_check_attached(struct udevice *dev); * Return: number of bytes read, <=0 for error */ int video_bridge_read_edid(struct udevice *dev, u8 *buf, int buf_size); +#else +static inline int video_bridge_attach(struct udevice *dev) +{ + return -ENOSYS; +} + +static inline int video_bridge_set_backlight(struct udevice *dev, int percent) +{ + return -ENOSYS; +} + +static inline int video_bridge_set_active(struct udevice *dev, bool active) +{ + return -ENOSYS; +} + +static inline int video_bridge_check_attached(struct udevice *dev) +{ + return -ENOSYS; +} + +static inline int video_bridge_get_display_timing(struct udevice *dev, + struct display_timing *timing) +{ + return -ENOSYS; +} + +static inline int video_bridge_read_edid(struct udevice *dev, u8 *buf, int buf_size) +{ + return -ENOSYS; +} +#endif /* CONFIG_VIDEO_BRIDGE */ #endif |