diff options
Diffstat (limited to 'include')
121 files changed, 2570 insertions, 2168 deletions
diff --git a/include/alist.h b/include/alist.h new file mode 100644 index 00000000000..68d268f01af --- /dev/null +++ b/include/alist.h @@ -0,0 +1,239 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Handles a contiguous list of pointers which be allocated and freed + * + * Copyright 2023 Google LLC + * Written by Simon Glass <sjg@chromium.org> + */ + +#ifndef __ALIST_H +#define __ALIST_H + +#include <stdbool.h> +#include <linux/bitops.h> +#include <linux/types.h> + +/** + * struct alist - object list that can be allocated and freed + * + * Holds a list of objects, each of the same size. The object is typically a + * C struct. The array is alloced in memory can change in size. + * + * The list rememebers the size of the list, but has a separate count of how + * much space is allocated, This allows it increase in size in steps as more + * elements are added, which is more efficient that reallocating the list every + * time a single item is added + * + * Two types of access are provided: + * + * alist_get...(index) + * gets an existing element, if its index is less that size + * + * alist_ensure(index) + * address an existing element, or creates a new one if not present + * + * @data: object data of size `@obj_size * @alloc`. The list can grow as + * needed but never shrinks + * @obj_size: Size of each object in bytes + * @count: number of objects in array + * @alloc: allocated length of array, to which @count can grow + * @flags: flags for the alist (ALISTF_...) + */ +struct alist { + void *data; + u16 obj_size; + u16 count; + u16 alloc; + u16 flags; +}; + +/** + * enum alist_flags - Flags for the alist + * + * @ALIST_FAIL: true if any allocation has failed. Once this has happened, the + * alist is dead and cannot grow further + */ +enum alist_flags { + ALISTF_FAIL = BIT(0), +}; + +/** + * alist_has() - Check if an index is within the list range + * + * Checks if index is within the current alist count + * + * @lst: alist to check + * @index: Index to check + * Returns: true if value, else false + */ +static inline bool alist_has(struct alist *lst, uint index) +{ + return index < lst->count; +} + +/** + * alist_err() - Check if the alist is still valid + * + * @lst: List to check + * Return: false if OK, true if any previous allocation failed + */ +static inline bool alist_err(struct alist *lst) +{ + return lst->flags & ALISTF_FAIL; +} + +/** + * alist_full() - Check if the alist is full + * + * @lst: List to check + * Return: true if full, false otherwise + */ +static inline bool alist_full(struct alist *lst) +{ + return lst->count == lst->alloc; +} + +/** + * alist_get_ptr() - Get the value of a pointer + * + * @lst: alist to check + * @index: Index to read from + * Returns: pointer, if present, else NULL + */ +const void *alist_get_ptr(const struct alist *lst, uint index); + +/** + * alist_getd() - Get the value of a pointer directly, with no checking + * + * This must only be called on indexes for which alist_has() returns true + * + * @lst: alist to check + * @index: Index to read from + * Returns: pointer value (may be NULL) + */ +static inline const void *alist_getd(struct alist *lst, uint index) +{ + return lst->data + index * lst->obj_size; +} + +/** get an entry as a constant */ +#define alist_get(_lst, _index, _struct) \ + ((const _struct *)alist_get_ptr(_lst, _index)) + +/** get an entry which can be written to */ +#define alist_getw(_lst, _index, _struct) \ + ((_struct *)alist_get_ptr(_lst, _index)) + +/** + * alist_ensure_ptr() - Ensure an object exists at a given index + * + * This provides read/write access to an array element. If it does not exist, + * it is allocated, reading for the caller to store the object into + * + * Allocates a object at the given index if needed + * + * @lst: alist to check + * @index: Index to address + * Returns: pointer where struct can be read/written, or NULL if out of memory + */ +void *alist_ensure_ptr(struct alist *lst, uint index); + +/** + * alist_ensure() - Address a struct, the correct object type + * + * Use as: + * struct my_struct *ptr = alist_ensure(&lst, 4, struct my_struct); + */ +#define alist_ensure(_lst, _index, _struct) \ + ((_struct *)alist_ensure_ptr(_lst, _index)) + +/** + * alist_add_placeholder() - Add a new item to the end of the list + * + * @lst: alist to add to + * Return: Pointer to the newly added position. Note that this is not inited so + * the caller must copy the requested struct to the returned pointer + */ +void *alist_add_placeholder(struct alist *lst); + +/** + * alist_add_ptr() - Ad a new object to the list + * + * @lst: alist to add to + * @obj: Pointer to object to copy in + * Returns: pointer to where the object was copied, or NULL if out of memory + */ +void *alist_add_ptr(struct alist *lst, void *obj); + +/** + * alist_expand_by() - Expand a list by the given amount + * + * @lst: alist to expand + * @inc_by: Amount to expand by + * Return: true if OK, false if out of memory + */ +bool alist_expand_by(struct alist *lst, uint inc_by); + +/** + * alist_add() - Used to add an object type with the correct type + * + * Use as: + * struct my_struct obj; + * struct my_struct *ptr = alist_add(&lst, &obj); + */ +#define alist_add(_lst, _obj) \ + ((typeof(_obj) *)alist_add_ptr(_lst, &(_obj))) + +/** + * alist_init() - Set up a new object list + * + * Sets up a list of objects, initially empty + * + * @lst: alist to set up + * @obj_size: Size of each element in bytes + * @alloc_size: Number of items to allowed to start, before reallocation is + * needed (0 to start with no space) + * Return: true if OK, false if out of memory + */ +bool alist_init(struct alist *lst, uint obj_size, uint alloc_size); + +#define alist_init_struct(_lst, _struct) \ + alist_init(_lst, sizeof(_struct), 0) + +/** + * alist_uninit_move_ptr() - Return the allocated contents and uninit the alist + * + * This returns the alist data to the caller, so that the caller receives data + * that it can be sure will hang around. The caller is responsible for freeing + * the data. + * + * If the alist size is 0, this returns NULL + * + * The alist is uninited as part of this. + * + * The alist must be inited before this can be called. + * + * @alist: alist to uninit + * @countp: if non-NULL, returns the number of objects in the returned data + * (which is @alist->size) + * Return: data contents, allocated with malloc(), or NULL if the data could not + * be allocated, or the data size is 0 + */ +void *alist_uninit_move_ptr(struct alist *alist, size_t *countp); + +/** + * alist_uninit_move() - Typed version of alist_uninit_move_ptr() + */ +#define alist_uninit_move(_lst, _countp, _struct) \ + (_struct *)alist_uninit_move_ptr(_lst, _countp) + +/** + * alist_uninit() - Free any memory used by an alist + * + * The alist must be inited before this can be called. + * + * @alist: alist to uninit + */ +void alist_uninit(struct alist *alist); + +#endif /* __ALIST_H */ diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index 27aa75e7036..d6c15e2c406 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -20,6 +20,7 @@ */ #ifndef __ASSEMBLY__ +#include <board_f.h> #include <cyclic.h> #include <event_internal.h> #include <fdtdec.h> @@ -30,6 +31,7 @@ struct acpi_ctx; struct driver_rt; +struct upl; typedef struct global_data gd_t; @@ -42,38 +44,140 @@ struct global_data { */ struct bd_info *bd; /** + * @new_gd: pointer to relocated global data + */ + struct global_data *new_gd; + /** + * @fdt_blob: U-Boot's own device tree, NULL if none + */ + const void *fdt_blob; + /** + * @cur_serial_dev: current serial device + */ + struct udevice *cur_serial_dev; +#ifndef CONFIG_SPL_BUILD + /** + * @jt: jump table + * + * The jump table contains pointers to exported functions. A pointer to + * the jump table is passed to standalone applications. + */ + struct jt_funcs *jt; + /** + * @boardf: information only used before relocation + */ + struct board_f *boardf; +#endif + /** + * @ram_size: RAM size in bytes + */ + phys_size_t ram_size; + /** + * @ram_top: top address of RAM used by U-Boot + */ + phys_addr_t ram_top; + /** * @flags: global data flags * * See &enum gd_flags */ unsigned long flags; /** + * @cpu_clk: CPU clock rate in Hz + */ + unsigned long cpu_clk; +#if CONFIG_IS_ENABLED(ENV_SUPPORT) + /** + * @env_addr: address of environment structure + * + * @env_addr contains the address of the structure holding the + * environment variables. + */ + unsigned long env_addr; +#endif /* ENV_SUPPORT */ + /** + * @ram_base: base address of RAM used by U-Boot + */ + unsigned long ram_base; + /** + * @relocaddr: start address of U-Boot in RAM + * + * After relocation this field indicates the address to which U-Boot + * has been relocated. It can be displayed using the bdinfo command. + * Its value is needed to display the source code when debugging with + * GDB using the 'add-symbol-file u-boot <relocaddr>' command. + */ + unsigned long relocaddr; + /** + * @irq_sp: IRQ stack pointer + */ + unsigned long irq_sp; + /** + * @start_addr_sp: initial stack pointer address + */ + unsigned long start_addr_sp; + /** + * @reloc_off: relocation offset + */ + unsigned long reloc_off; + /** + * @bus_clk: platform clock rate in Hz + */ + unsigned int bus_clk; + /** + * @mem_clk: memory clock rate in Hz + */ + unsigned int mem_clk; + /** + * @mon_len: monitor length in bytes + */ + unsigned int mon_len; + /** * @baudrate: baud rate of the serial interface */ unsigned int baudrate; +#if CONFIG_IS_ENABLED(ENV_SUPPORT) /** - * @cpu_clk: CPU clock rate in Hz + * @env_has_init: bit mask indicating environment locations + * + * &enum env_location defines which bit relates to which location */ - unsigned long cpu_clk; + unsigned short env_has_init; /** - * @bus_clk: platform clock rate in Hz + * @env_valid: environment is valid + * + * See &enum env_valid */ - unsigned long bus_clk; + unsigned char env_valid; /** - * @pci_clk: PCI clock rate in Hz + * @env_load_prio: priority of the loaded environment */ - /* We cannot bracket this with CONFIG_PCI due to mpc5xxx */ - unsigned long pci_clk; + char env_load_prio; /** - * @mem_clk: memory clock rate in Hz + * @env_buf: buffer for env_get() before reloc */ - unsigned long mem_clk; -#if CONFIG_IS_ENABLED(VIDEO) + char env_buf[32]; +#endif /* ENV_SUPPORT */ /** - * @fb_base: base address of frame buffer memory + * @fdt_src: Source of FDT */ - unsigned long fb_base; -#endif + enum fdt_source_t fdt_src; + /** + * @arch: architecture-specific data + */ + struct arch_global_data arch; + /** + * @dmtag_list: List of DM tags + */ + struct list_head dmtag_list; + /** + * @timebase_h: high 32 bits of timer + */ + unsigned int timebase_h; + /** + * @timebase_l: low 32 bits of timer + */ + unsigned int timebase_l; #if defined(CONFIG_POST) /** * @post_log_word: active POST tests @@ -103,15 +207,6 @@ struct global_data { */ unsigned long board_type; #endif - /** - * @have_console: console is available - * - * A value of 1 indicates that serial_init() was called and a console - * is available. - * A value of 0 indicates that console input and output drivers shall - * not be called. - */ - unsigned long have_console; #if CONFIG_IS_ENABLED(PRE_CONSOLE_BUFFER) /** * @precon_buf_idx: pre-console buffer index @@ -125,71 +220,6 @@ struct global_data { */ long precon_buf_idx; #endif - /** - * @env_addr: address of environment structure - * - * @env_addr contains the address of the structure holding the - * environment variables. - */ - unsigned long env_addr; - /** - * @env_valid: environment is valid - * - * See &enum env_valid - */ - unsigned long env_valid; - /** - * @env_has_init: bit mask indicating environment locations - * - * &enum env_location defines which bit relates to which location - */ - unsigned long env_has_init; - /** - * @env_load_prio: priority of the loaded environment - */ - int env_load_prio; - /** - * @ram_base: base address of RAM used by U-Boot - */ - unsigned long ram_base; - /** - * @ram_top: top address of RAM used by U-Boot - */ - phys_addr_t ram_top; - /** - * @relocaddr: start address of U-Boot in RAM - * - * After relocation this field indicates the address to which U-Boot - * has been relocated. It can be displayed using the bdinfo command. - * Its value is needed to display the source code when debugging with - * GDB using the 'add-symbol-file u-boot <relocaddr>' command. - */ - unsigned long relocaddr; - /** - * @ram_size: RAM size in bytes - */ - phys_size_t ram_size; - /** - * @mon_len: monitor length in bytes - */ - unsigned long mon_len; - /** - * @irq_sp: IRQ stack pointer - */ - unsigned long irq_sp; - /** - * @start_addr_sp: initial stack pointer address - */ - unsigned long start_addr_sp; - /** - * @reloc_off: relocation offset - */ - unsigned long reloc_off; - /** - * @new_gd: pointer to relocated global data - */ - struct global_data *new_gd; - #ifdef CONFIG_DM /** * @dm_root: root instance for Driver Model @@ -234,46 +264,18 @@ struct global_data { */ struct udevice *timer; #endif - /** - * @fdt_blob: U-Boot's own device tree, NULL if none - */ - const void *fdt_blob; - /** - * @new_fdt: relocated device tree - */ - void *new_fdt; - /** - * @fdt_size: space reserved for relocated device space - */ - unsigned long fdt_size; - /** - * @fdt_src: Source of FDT - */ - enum fdt_source_t fdt_src; #if CONFIG_IS_ENABLED(OF_LIVE) /** * @of_root: root node of the live tree */ struct device_node *of_root; #endif - #if CONFIG_IS_ENABLED(MULTI_DTB_FIT) /** * @multi_dtb_fit: pointer to uncompressed multi-dtb FIT image */ const void *multi_dtb_fit; #endif - /** - * @jt: jump table - * - * The jump table contains pointers to exported functions. A pointer to - * the jump table is passed to standalone applications. - */ - struct jt_funcs *jt; - /** - * @env_buf: buffer for env_get() before reloc - */ - char env_buf[32]; #ifdef CONFIG_TRACE /** * @trace_buff: trace buffer @@ -289,18 +291,10 @@ struct global_data { */ int cur_i2c_bus; #endif - /** - * @timebase_h: high 32 bits of timer - */ - unsigned int timebase_h; - /** - * @timebase_l: low 32 bits of timer - */ - unsigned int timebase_l; +#if CONFIG_IS_ENABLED(CMD_BDINFO_EXTRA) /** * @malloc_start: start of malloc() region */ -#if CONFIG_IS_ENABLED(CMD_BDINFO_EXTRA) unsigned long malloc_start; #endif #if CONFIG_IS_ENABLED(SYS_MALLOC_F) @@ -309,43 +303,14 @@ struct global_data { */ unsigned long malloc_base; /** - * @malloc_limit: limit address of early malloc() + * @malloc_limit: maximum size of early malloc() */ - unsigned long malloc_limit; + unsigned int malloc_limit; /** - * @malloc_ptr: current address of early malloc() + * @malloc_ptr: currently used bytes of early malloc() */ - unsigned long malloc_ptr; + unsigned int malloc_ptr; #endif -#ifdef CONFIG_PCI - /** - * @hose: PCI hose for early use - */ - struct pci_controller *hose; - /** - * @pci_ram_top: top of region accessible to PCI - */ - phys_addr_t pci_ram_top; -#endif -#ifdef CONFIG_PCI_BOOTDELAY - /** - * @pcidelay_done: delay time before scanning of PIC hose expired - * - * If CONFIG_PCI_BOOTDELAY=y, pci_hose_scan() waits for the number of - * milliseconds defined by environment variable pcidelay before - * scanning. Once this delay has expired the flag @pcidelay_done - * is set to 1. - */ - int pcidelay_done; -#endif - /** - * @cur_serial_dev: current serial device - */ - struct udevice *cur_serial_dev; - /** - * @arch: architecture-specific data - */ - struct arch_global_data arch; #ifdef CONFIG_CONSOLE_RECORD /** * @console_out: output buffer for console recording @@ -376,13 +341,19 @@ struct global_data { * @bootstage: boot stage information */ struct bootstage_data *bootstage; - /** - * @new_bootstage: relocated boot stage information - */ - struct bootstage_data *new_bootstage; #endif #ifdef CONFIG_LOG /** + * @log_head: list of logging devices + */ + struct list_head log_head; + /** + * @log_fmt: bit mask for logging format + * + * The @log_fmt bit mask selects the fields to be shown in log messages. + * &enum log_fmt defines the bits of the bit mask. + */ + /** * @log_drop_count: number of dropped log messages * * This counter is incremented for each log message which can not @@ -396,60 +367,39 @@ struct global_data { * For logging devices without filters @default_log_level defines the * logging level, cf. &enum log_level_t. */ - int default_log_level; - /** - * @log_head: list of logging devices - */ - struct list_head log_head; - /** - * @log_fmt: bit mask for logging format - * - * The @log_fmt bit mask selects the fields to be shown in log messages. - * &enum log_fmt defines the bits of the bit mask. - */ - int log_fmt; - - /** - * @processing_msg: a log message is being processed - * - * This flag is used to suppress the creation of additional messages - * while another message is being processed. - */ - bool processing_msg; + char default_log_level; + char log_fmt; /** * @logc_prev: logging category of previous message * * This value is used as logging category for continuation messages. */ - int logc_prev; + unsigned char logc_prev; /** * @logl_prev: logging level of the previous message * * This value is used as logging level for continuation messages. */ - int logl_prev; + unsigned char logl_prev; /** * @log_cont: Previous log line did not finished wtih \n * * This allows for chained log messages on the same line */ bool log_cont; + /** + * @processing_msg: a log message is being processed + * + * This flag is used to suppress the creation of additional messages + * while another message is being processed. + */ + bool processing_msg; #endif #if CONFIG_IS_ENABLED(BLOBLIST) /** * @bloblist: blob list information */ struct bloblist_hdr *bloblist; - /** - * @new_bloblist: relocated blob list information - */ - struct bloblist_hdr *new_bloblist; -#endif -#if CONFIG_IS_ENABLED(HANDOFF) - /** - * @spl_handoff: SPL hand-off information - */ - struct spl_handoff *spl_handoff; #endif #if defined(CONFIG_TRANSLATION_OFFSET) /** @@ -487,10 +437,12 @@ struct global_data { */ struct hlist_head cyclic_list; #endif +#if CONFIG_IS_ENABLED(UPL) /** - * @dmtag_list: List of DM tags + * @upl: Universal Payload-handoff information */ - struct list_head dmtag_list; + struct upl *upl; +#endif }; #ifndef DO_DEPS_ONLY static_assert(sizeof(struct global_data) == GD_SIZE); @@ -578,18 +530,20 @@ static_assert(sizeof(struct global_data) == GD_SIZE); #define gd_set_malloc_start(val) #endif -#if CONFIG_IS_ENABLED(PCI) -#define gd_set_pci_ram_top(val) gd->pci_ram_top = val -#else -#define gd_set_pci_ram_top(val) -#endif - #if CONFIG_VAL(SYS_MALLOC_F_LEN) #define gd_malloc_ptr() gd->malloc_ptr #else #define gd_malloc_ptr() 0L #endif +#if CONFIG_IS_ENABLED(UPL) +#define gd_upl() gd->upl +#define gd_set_upl(_val) gd->upl = (_val) +#else +#define gd_upl() NULL +#define gd_set_upl(val) +#endif + /** * enum gd_flags - global data flags * @@ -701,6 +655,16 @@ enum gd_flags { * @GD_FLG_HUSH_MODERN_PARSER: Use hush 2021 parser. */ GD_FLG_HUSH_MODERN_PARSER = 0x2000000, + /** + * @GD_FLG_UPL: Read/write a Universal Payload (UPL) handoff + */ + GD_FLG_UPL = 0x4000000, + /** + * @GD_FLG_HAVE_CONSOLE: serial_init() was called and a console + * is available. When not set, indicates that console input and output + * drivers shall not be called. + */ + GD_FLG_HAVE_CONSOLE = 0x8000000, }; #endif /* __ASSEMBLY__ */ diff --git a/include/blk.h b/include/blk.h index 7c7cf7f2b10..1fc9a5b8471 100644 --- a/include/blk.h +++ b/include/blk.h @@ -650,7 +650,7 @@ struct blk_driver *blk_driver_lookup_type(int uclass_id); struct blk_desc *blk_get_devnum_by_uclass_id(enum uclass_id uclass_id, int devnum); /** - * blk_get_devnum_by_uclass_id() - Get a block device by type name, and number + * blk_get_devnum_by_uclass_idname() - Get block device by type name and number * * This looks up the block device type based on @uclass_idname, then calls * blk_get_devnum_by_uclass_id(). @@ -660,7 +660,7 @@ struct blk_desc *blk_get_devnum_by_uclass_id(enum uclass_id uclass_id, int devnu * Return: point to block device descriptor, or NULL if not found */ struct blk_desc *blk_get_devnum_by_uclass_idname(const char *uclass_idname, - int devnum); + int devnum); /** * blk_dselect_hwpart() - select a hardware partition diff --git a/include/board_f.h b/include/board_f.h new file mode 100644 index 00000000000..05aa51510c2 --- /dev/null +++ b/include/board_f.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2024 Google LLC + * Written by: Simon Glass <sjg@chromeium.org> + */ + +#ifndef __BOARD_F +#define __BOARD_F + +/** + * struct board_f: Information used only before relocation + * + * This struct is set up in board_init_f() and used to deal with relocation. It + * is not available after relocation. + */ +struct board_f { + /** + * @new_fdt: relocated device tree + */ + void *new_fdt; + /** + * @fdt_size: space reserved for relocated device space + */ + unsigned long fdt_size; + /** + * @new_bootstage: relocated boot stage information + */ + struct bootstage_data *new_bootstage; + /** + * @new_bloblist: relocated blob list information + */ + struct bloblist_hdr *new_bloblist; +}; + +#endif diff --git a/include/bootstage.h b/include/bootstage.h index f4e77b09d74..57792648c49 100644 --- a/include/bootstage.h +++ b/include/bootstage.h @@ -258,7 +258,7 @@ void show_boot_progress(int val); * relocation, since memory can be overwritten later. * Return: Always returns 0, to indicate success */ -int bootstage_relocate(void); +int bootstage_relocate(void *to); /** * Add a new bootstage record @@ -395,7 +395,7 @@ static inline ulong bootstage_add_record(enum bootstage_id id, * and won't even do that unless CONFIG_SHOW_BOOT_PROGRESS is defined */ -static inline int bootstage_relocate(void) +static inline int bootstage_relocate(void *to) { return 0; } diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h index 6fd43511ee4..e5df82c6830 100644 --- a/include/configs/apalis_imx6.h +++ b/include/configs/apalis_imx6.h @@ -23,11 +23,6 @@ /* Network */ -/* USB Configs */ -/* Host */ -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 - /* Framebuffer and LCD */ /* Command definition */ diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index 9d4a4bbdf43..8a66b1275df 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -411,10 +411,6 @@ /* DMA stuff, needed for GPMI/MXS NAND support */ -/* USB Configs */ -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 - /* UBI support */ #define CFG_ENV_FLAGS_LIST_STATIC "ethaddr:mw,serial#:sw,board_type:sw," \ diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index b9cc7ba974d..b75db7e7bac 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -35,11 +35,7 @@ #define CFG_SYS_SDRAM_SIZE 0x04000000 #define CFG_SYS_INIT_RAM_SIZE (16 * 1024) -#ifdef CONFIG_AT91SAM9XE -# define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM -#else -# define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 -#endif +#define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 /* NAND flash */ #ifdef CONFIG_CMD_NAND diff --git a/include/configs/brppt2.h b/include/configs/brppt2.h index 38c98c5e21c..d01f0d37316 100644 --- a/include/configs/brppt2.h +++ b/include/configs/brppt2.h @@ -78,7 +78,4 @@ BUR_COMMON_ENV \ #define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE -/* USB Configs */ -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) - #endif /* __CONFIG_BRPP2_IMX6_H */ diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h index 280ae1e9cca..8c363137b4f 100644 --- a/include/configs/cl-som-imx7.h +++ b/include/configs/cl-som-imx7.h @@ -95,8 +95,4 @@ #define CFG_SYS_FSL_USDHC_NUM 2 #endif -/* USB Configs */ -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 - #endif /* __CONFIG_H */ diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index 7d0f2b6dc13..f7fd4c517b4 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -134,10 +134,6 @@ /* Ethernet */ #define CFG_FEC_MXC_PHYADDR 0 -/* USB */ -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 - /* Boot */ #define CFG_SYS_BOOTMAPSZ (8 << 20) diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h index 8860ceec1a0..26b29bad6a1 100644 --- a/include/configs/colibri-imx6ull.h +++ b/include/configs/colibri-imx6ull.h @@ -117,11 +117,6 @@ #define CFG_SYS_NAND_BASE -1 #endif -/* USB Configs */ - -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 - /* USB Device Firmware Update support */ #define DFU_DEFAULT_POLL_TIMEOUT 300 diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h index 79e5b870b81..664b7c8ce0c 100644 --- a/include/configs/colibri_imx6.h +++ b/include/configs/colibri_imx6.h @@ -21,11 +21,6 @@ #define CFG_SYS_FSL_ESDHC_ADDR 0 #define CFG_SYS_FSL_USDHC_NUM 2 -/* USB Configs */ -/* Host */ -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 - /* Command definition */ #define BOOT_TARGET_DEVICES(func) \ diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index 33133a0b96e..c340dfb1189 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -159,9 +159,4 @@ #define CFG_SYS_NAND_BASE 0x40000000 #endif -/* USB Configs */ - -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 - #endif diff --git a/include/configs/dart_6ul.h b/include/configs/dart_6ul.h index c5781670864..2b329b4065c 100644 --- a/include/configs/dart_6ul.h +++ b/include/configs/dart_6ul.h @@ -46,10 +46,6 @@ #define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE -/* USB Configs */ -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 - #define ENV_MMC \ "mmcdev=" __stringify(MMC_ROOTFS_DEV) "\0" \ "mmcpart=" __stringify(MMC_ROOTFS_PART) "\0" \ diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h index 4b5ef4ad510..9b6f03f6856 100644 --- a/include/configs/dh_imx6.h +++ b/include/configs/dh_imx6.h @@ -30,10 +30,6 @@ /* UART */ #define CFG_MXC_UART_BASE UART1_BASE -/* USB Configs */ -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 - /* USB Gadget (DFU, UMS) */ #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) #define DFU_DEFAULT_POLL_TIMEOUT 300 diff --git a/include/configs/display5.h b/include/configs/display5.h index 2005a256d6e..51fa2b03a2e 100644 --- a/include/configs/display5.h +++ b/include/configs/display5.h @@ -287,5 +287,4 @@ /* The 0x120000 value corresponds to above SPI-NOR memory MAP */ #endif -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #endif /* __CONFIG_H */ diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h index 31c7e104f6b..61c0d755a8d 100644 --- a/include/configs/embestmx6boards.h +++ b/include/configs/embestmx6boards.h @@ -17,10 +17,6 @@ #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) -/* USB Configs */ -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 - /* MMC Configs */ #define CFG_SYS_FSL_ESDHC_ADDR 0 diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h deleted file mode 100644 index 807c6963192..00000000000 --- a/include/configs/ethernut5.h +++ /dev/null @@ -1,91 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 - * egnite GmbH <info@egnite.de> - * - * Configuation settings for Ethernut 5 with AT91SAM9XE. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <asm/hardware.h> - -/* The first stage boot loader expects u-boot running at this address. */ - -/* The first stage boot loader takes care of low level initialization. */ - -/* CPU information */ - -/* ARM asynchronous clock */ -#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ -#define CFG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ - -/* 32kB internal SRAM */ -#define CFG_SYS_INIT_RAM_ADDR 0x00300000 /*AT91SAM9XE_SRAM_BASE */ -#define CFG_SYS_INIT_RAM_SIZE (32 << 10) - -/* 128MB SDRAM in 1 bank */ -#define CFG_SYS_SDRAM_BASE 0x20000000 -#define CFG_SYS_SDRAM_SIZE (128 << 20) - -/* 512kB on-chip NOR flash */ -# define CFG_SYS_FLASH_BASE 0x00200000 /* AT91SAM9XE_FLASH_BASE */ - -/* bootstrap + u-boot + env + linux in dataflash on CS0 */ - -/* NAND flash */ -#ifdef CONFIG_CMD_NAND -#define CFG_SYS_NAND_BASE 0x40000000 -/* our ALE is AD21 */ -#define CFG_SYS_NAND_MASK_ALE (1 << 21) -/* our CLE is AD22 */ -#define CFG_SYS_NAND_MASK_CLE (1 << 22) -#define CFG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14) -#endif - -/* JFFS2 */ - -/* Ethernet */ -#define CFG_PHY_ID 0 - -/* MMC */ -#ifdef CONFIG_CMD_MMC -#define CFG_SYS_MMC_CD_PIN AT91_PIO_PORTC, 8 -#endif - -/* RTC */ -#if defined(CONFIG_CMD_DATE) || defined(CONFIG_CMD_SNTP) -#define CFG_SYS_I2C_RTC_ADDR 0x51 -#endif - -/* I2C */ -#define CFG_SYS_MAX_I2C_BUS 1 - -#define I2C_SOFT_DECLARATIONS - -#define GPIO_I2C_SCL AT91_PIO_PORTA, 24 -#define GPIO_I2C_SDA AT91_PIO_PORTA, 23 - -#define I2C_INIT { \ - at91_set_pio_periph(AT91_PIO_PORTA, 23, 0); \ - at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \ - at91_set_pio_periph(AT91_PIO_PORTA, 24, 0); \ - at91_set_pio_output(AT91_PIO_PORTA, 24, 0); \ - at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \ -} - -#define I2C_ACTIVE at91_set_pio_output(AT91_PIO_PORTA, 23, 0) -#define I2C_TRISTATE at91_set_pio_input(AT91_PIO_PORTA, 23, 0) -#define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit) -#define I2C_SDA(bit) at91_set_pio_value(AT91_PIO_PORTA, 23, bit) -#define I2C_DELAY udelay(100) -#define I2C_READ at91_get_pio_value(AT91_PIO_PORTA, 23) - -/* File systems */ - -/* Boot command */ - -/* Misc. u-boot settings */ - -#endif diff --git a/include/configs/ge_b1x5v2.h b/include/configs/ge_b1x5v2.h index 49b058cb10d..f3d85c9c11e 100644 --- a/include/configs/ge_b1x5v2.h +++ b/include/configs/ge_b1x5v2.h @@ -23,10 +23,6 @@ #define CONSOLE_DEVICE "ttymxc2" /* Base board debug connector */ #endif -/* USB */ -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 - /* Memory */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index ebc5d03d0d5..acfb5135dbe 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -6,55 +6,22 @@ #ifndef __CONFIG_H #define __CONFIG_H -/* SPL */ -/* Location in NAND to read U-Boot from */ - -/* Falcon Mode */ - -/* Falcon Mode - MMC support: args@1MB kernel@2MB */ - #include "mx6_common.h" /* Serial */ #define CFG_MXC_UART_BASE UART2_BASE -/* NAND */ - /* MMC Configs */ #define CFG_SYS_FSL_ESDHC_ADDR 0 -/* - * PCI express - */ - -/* - * PMIC - */ +/* PMIC */ #define CFG_POWER_PFUZE100_I2C_ADDR 0x08 #define CFG_POWER_LTC3676_I2C_ADDR 0x3c -/* Various command support */ - -/* USB Configs */ -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 - -/* Miscellaneous configurable options */ - -/* Memory configuration */ - /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE -/* - * MTD Command for mtdparts - */ - -/* Persistent Environment Config */ - -/* Environment */ - #endif /* __CONFIG_H */ diff --git a/include/configs/ibex_ast2700.h b/include/configs/ibex_ast2700.h new file mode 100644 index 00000000000..0f6850f7240 --- /dev/null +++ b/include/configs/ibex_ast2700.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) Aspeed Technology Inc. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE +#define CFG_SYS_SDRAM_BASE 0x80000000 + +#endif /* __CONFIG_H */ diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h index 66004a6eb2a..75997469cd9 100644 --- a/include/configs/imx6_logic.h +++ b/include/configs/imx6_logic.h @@ -114,12 +114,6 @@ #define CFG_SYS_NAND_BASE 0x40000000 #define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE -/* USB Configs */ -#ifdef CONFIG_CMD_USB -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 -#endif - /* Falcon Mode */ /* Falcon Mode - MMC support: args@1MB kernel@2MB */ diff --git a/include/configs/imx6dl-mamoj.h b/include/configs/imx6dl-mamoj.h index 6c61b3f4480..8abb58b0691 100644 --- a/include/configs/imx6dl-mamoj.h +++ b/include/configs/imx6dl-mamoj.h @@ -42,10 +42,6 @@ /* Ethernet */ #define CFG_FEC_MXC_PHYADDR 1 -/* USB */ -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 - /* Falcon */ /* MMC support: args@1MB kernel@2MB */ diff --git a/include/configs/imx6q-bosch-acc.h b/include/configs/imx6q-bosch-acc.h index 2c998cdcfc7..fab5063b73f 100644 --- a/include/configs/imx6q-bosch-acc.h +++ b/include/configs/imx6q-bosch-acc.h @@ -110,7 +110,5 @@ #endif #endif -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 #endif /* __IMX6Q_ACC_H */ diff --git a/include/configs/imx7-cm.h b/include/configs/imx7-cm.h index 131f18290b9..36c4c5b8b50 100644 --- a/include/configs/imx7-cm.h +++ b/include/configs/imx7-cm.h @@ -77,7 +77,4 @@ #define CFG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR #define CFG_SYS_FSL_USDHC_NUM 2 -/* USB Configs */ -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) - #endif /* __CONFIG_H */ diff --git a/include/configs/imx8mm-cl-iot-gate.h b/include/configs/imx8mm-cl-iot-gate.h index 6442e3d570f..146f7945719 100644 --- a/include/configs/imx8mm-cl-iot-gate.h +++ b/include/configs/imx8mm-cl-iot-gate.h @@ -137,7 +137,4 @@ #define CFG_FEC_MXC_PHYADDR -1 /* Auto search of PHY on MII */ -/* USB Configs */ -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) - #endif /*__IMX8MM_CL_IOT_GATE_H*/ diff --git a/include/configs/kontron-sl-mx6ul.h b/include/configs/kontron-sl-mx6ul.h index 1c92cd78767..015df01db4e 100644 --- a/include/configs/kontron-sl-mx6ul.h +++ b/include/configs/kontron-sl-mx6ul.h @@ -24,11 +24,6 @@ /* Board and environment settings */ #define CFG_MXC_UART_BASE UART4_BASE -#ifdef CONFIG_USB_EHCI_HCD -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 -#endif - /* Boot order for distro boot */ #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ diff --git a/include/configs/kontron-sl-mx8mm.h b/include/configs/kontron-sl-mx8mm.h index eee3d2ddb03..3a129c5cce7 100644 --- a/include/configs/kontron-sl-mx8mm.h +++ b/include/configs/kontron-sl-mx8mm.h @@ -24,11 +24,6 @@ /* Board and environment settings */ -#ifdef CONFIG_USB_EHCI_HCD -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 -#endif - /* GUID for capsule updatable firmware image */ #define KONTRON_SL_MX8MM_FIT_IMAGE_GUID \ EFI_GUID(0xd488e45a, 0x4929, 0x4b55, 0x8c, 0x14, \ diff --git a/include/configs/kp_imx53.h b/include/configs/kp_imx53.h index 6e383cbe75f..78c6c67ab99 100644 --- a/include/configs/kp_imx53.h +++ b/include/configs/kp_imx53.h @@ -11,7 +11,6 @@ #include <linux/sizes.h> /* USB Configs */ -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CFG_MXC_USB_FLAGS 0 /* Command definition */ diff --git a/include/configs/kp_imx6q_tpc.h b/include/configs/kp_imx6q_tpc.h index 1aa4b8ab598..c0cb3db23e7 100644 --- a/include/configs/kp_imx6q_tpc.h +++ b/include/configs/kp_imx6q_tpc.h @@ -16,12 +16,6 @@ /* FEC ethernet */ -/* USB Configs */ -#ifdef CONFIG_CMD_USB -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 -#endif - #define CFG_EXTRA_ENV_SETTINGS \ "console=ttymxc0,115200\0" \ "fdt_addr=0x18000000\0" \ diff --git a/include/configs/liteboard.h b/include/configs/liteboard.h index 5811059c8e2..fc6bc6b28ba 100644 --- a/include/configs/liteboard.h +++ b/include/configs/liteboard.h @@ -93,12 +93,6 @@ /* FLASH and environment organization */ -/* USB Configs */ -#ifdef CONFIG_CMD_USB -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 -#endif - #ifdef CONFIG_CMD_NET #define CFG_FEC_ENET_DEV 0 diff --git a/include/configs/ls1028aqds.h b/include/configs/ls1028aqds.h index 769ece901c1..ed93b51d808 100644 --- a/include/configs/ls1028aqds.h +++ b/include/configs/ls1028aqds.h @@ -47,7 +47,6 @@ #endif /* RTC */ -#define CFG_SYS_RTC_BUS_NUM 1 #define I2C_MUX_CH_RTC 0xB /* Store environment at top of flash */ diff --git a/include/configs/ls1028ardb.h b/include/configs/ls1028ardb.h index 0f591e3c4ab..d44ce45fd6b 100644 --- a/include/configs/ls1028ardb.h +++ b/include/configs/ls1028ardb.h @@ -10,8 +10,6 @@ #define COUNTER_FREQUENCY_REAL (get_board_sys_clk() / 4) -#define CFG_SYS_RTC_BUS_NUM 0 - /* Store environment at top of flash */ /* diff --git a/include/configs/ls1046afrwy.h b/include/configs/ls1046afrwy.h index 5e03a962d10..21804fc6654 100644 --- a/include/configs/ls1046afrwy.h +++ b/include/configs/ls1046afrwy.h @@ -66,7 +66,6 @@ /* RTC */ #define CFG_SYS_I2C_RTC_ADDR 0x51 /* Channel 0 I2C bus 0*/ -#define CFG_SYS_RTC_BUS_NUM 0 /* * Environment diff --git a/include/configs/lx2160aqds.h b/include/configs/lx2160aqds.h index 3a316e73308..5b397e23d89 100644 --- a/include/configs/lx2160aqds.h +++ b/include/configs/lx2160aqds.h @@ -8,9 +8,6 @@ #include "lx2160a_common.h" -/* RTC */ -#define CFG_SYS_RTC_BUS_NUM 0 - /* MAC/PHY configuration */ /* Initial environment variables */ diff --git a/include/configs/lx2160ardb.h b/include/configs/lx2160ardb.h index 6404b359111..e700a7b1135 100644 --- a/include/configs/lx2160ardb.h +++ b/include/configs/lx2160ardb.h @@ -8,9 +8,6 @@ #include "lx2160a_common.h" -/* RTC */ -#define CFG_SYS_RTC_BUS_NUM 4 - #if defined(CONFIG_FSL_MC_ENET) #define AQR113C_PHY_ADDR1 0x0 #define AQR113C_PHY_ADDR2 0x08 diff --git a/include/configs/lx2162aqds.h b/include/configs/lx2162aqds.h index 54d7cea4c59..2d0db47b334 100644 --- a/include/configs/lx2162aqds.h +++ b/include/configs/lx2162aqds.h @@ -10,9 +10,6 @@ /* USB */ -/* RTC */ -#define CFG_SYS_RTC_BUS_NUM 0 - /* Initial environment variables */ #define CFG_EXTRA_ENV_SETTINGS \ EXTRA_ENV_SETTINGS \ diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index 9cf46b2c362..1ea4fa59fd5 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -57,8 +57,6 @@ #define CFG_FEC_MXC_PHYADDR 0x0 #endif -#define CFG_SYS_RTC_BUS_NUM 1 /* I2C2 */ - /* * RTC */ @@ -70,8 +68,6 @@ * USB */ #ifdef CONFIG_CMD_USB -#define CFG_MXC_USB_PORT 1 -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CFG_MXC_USB_FLAGS 0 #endif diff --git a/include/configs/meerkat96.h b/include/configs/meerkat96.h index 6ffc1282411..8e248177b1c 100644 --- a/include/configs/meerkat96.h +++ b/include/configs/meerkat96.h @@ -23,7 +23,4 @@ /* Environment configs */ -/* USB configs */ -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) - #endif diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index dff54d04a67..6c8cb78274b 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -33,7 +33,6 @@ #define CFG_SYS_FSL_ESDHC_ADDR MMC_SDHC1_BASE_ADDR /* USB Configs */ -#define CFG_MXC_USB_PORT 1 #define CFG_MXC_USB_PORTSC PORT_PTS_ULPI #define CFG_MXC_USB_FLAGS MXC_EHCI_POWER_PINS_ENABLED diff --git a/include/configs/mx53cx9020.h b/include/configs/mx53cx9020.h index dccfdc3a15d..70aa140036f 100644 --- a/include/configs/mx53cx9020.h +++ b/include/configs/mx53cx9020.h @@ -22,8 +22,6 @@ /* bootz: zImage/initrd.img support */ /* USB Configs */ -#define CFG_MXC_USB_PORT 1 -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CFG_MXC_USB_FLAGS 0 /* Command definition */ diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index 7398804e6b5..14095b99f03 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -17,8 +17,6 @@ #define CFG_SYS_FSL_ESDHC_ADDR 0 /* USB Configs */ -#define CFG_MXC_USB_PORT 1 -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CFG_MXC_USB_FLAGS 0 /* PMIC Controller */ diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h index df65dbeea41..6d1f669de50 100644 --- a/include/configs/mx53ppd.h +++ b/include/configs/mx53ppd.h @@ -12,8 +12,6 @@ #include <asm/arch/imx-regs.h> /* USB Configs */ -#define CFG_MXC_USB_PORT 1 -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CFG_MXC_USB_FLAGS 0 /* Command definition */ diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h index f0d6405d301..068b9e4d25f 100644 --- a/include/configs/mx6cuboxi.h +++ b/include/configs/mx6cuboxi.h @@ -14,9 +14,6 @@ /* MMC Configs */ #define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR -/* USB */ -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) - /* Command definition */ #define CFG_MXC_UART_BASE UART1_BASE diff --git a/include/configs/mx6memcal.h b/include/configs/mx6memcal.h index f2edd13eb88..a966c8b2a44 100644 --- a/include/configs/mx6memcal.h +++ b/include/configs/mx6memcal.h @@ -31,6 +31,5 @@ #define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CFG_MXC_USB_PORTSC PORT_PTS_UTMI #endif /* __CONFIG_H */ diff --git a/include/configs/mx6sabreauto.h b/include/configs/mx6sabreauto.h index 91544c8a0e2..e491af3e927 100644 --- a/include/configs/mx6sabreauto.h +++ b/include/configs/mx6sabreauto.h @@ -11,10 +11,6 @@ #define CFG_MXC_UART_BASE UART4_BASE #define CONSOLE_DEV "ttymxc3" -/* USB Configs */ -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 - #define CFG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} } #include "mx6sabre_common.h" diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h index 844f10e4229..e34947c94d0 100644 --- a/include/configs/mx6sabresd.h +++ b/include/configs/mx6sabresd.h @@ -24,10 +24,4 @@ #define CFG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(3, 19) #endif -/* USB Configs */ -#ifdef CONFIG_CMD_USB -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 -#endif - #endif /* __MX6SABRESD_CONFIG_H */ diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index 39c8ef060c7..d4e66a39882 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -25,9 +25,9 @@ "fdt_addr=0x88000000\0" \ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ - "mmcdev=1\0" \ + "mmcdev=0\0" \ "mmcpart=1\0" \ - "finduuid=part uuid mmc 1:2 uuid\0" \ + "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ "root=PARTUUID=${uuid} rootwait rw\0" \ "loadbootscript=" \ @@ -88,12 +88,6 @@ /* Environment organization */ -/* USB Configs */ -#ifdef CONFIG_CMD_USB -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 -#endif - #define CFG_SYS_FSL_USDHC_NUM 3 #endif /* __CONFIG_H */ diff --git a/include/configs/mx6sllevk.h b/include/configs/mx6sllevk.h index 290996b51bc..0ba4054bbe4 100644 --- a/include/configs/mx6sllevk.h +++ b/include/configs/mx6sllevk.h @@ -92,10 +92,5 @@ #define CFG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR #define CFG_SYS_FSL_USDHC_NUM 3 -/* USB Configs */ -#ifdef CONFIG_CMD_USB -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#endif - #include <linux/stringify.h> #endif /* __CONFIG_H */ diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h index 1c14a6beb0a..36d82e81d5d 100644 --- a/include/configs/mx6sxsabreauto.h +++ b/include/configs/mx6sxsabreauto.h @@ -95,11 +95,6 @@ #define IMX_FEC_BASE ENET2_BASE_ADDR #define CFG_FEC_MXC_PHYADDR 0x0 -#ifdef CONFIG_CMD_USB -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 -#endif - #define CFG_SYS_FSL_USDHC_NUM 2 #endif /* __CONFIG_H */ diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index fe0ad34ef9c..844becbfd2c 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -117,11 +117,6 @@ #define CFG_FEC_MXC_PHYADDR 0x1 -#ifdef CONFIG_CMD_USB -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 -#endif - #ifdef CONFIG_CMD_PCI #define CFG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(2, 0) #define CFG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(2, 1) diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index 98b743b9364..3716dc75b96 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -114,12 +114,6 @@ /* environment organization */ -/* USB Configs */ -#ifdef CONFIG_CMD_USB -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 -#endif - #ifdef CONFIG_CMD_NET #define CFG_FEC_ENET_DEV 1 diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index 94bee75fdea..f5ab4720750 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -98,7 +98,4 @@ /* DMA stuff, needed for GPMI/MXS NAND support */ #endif -/* USB Configs */ -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) - #endif /* __CONFIG_H */ diff --git a/include/configs/mx7ulp_com.h b/include/configs/mx7ulp_com.h index a310c64e794..f8e3950fa32 100644 --- a/include/configs/mx7ulp_com.h +++ b/include/configs/mx7ulp_com.h @@ -51,5 +51,4 @@ #define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CFG_SYS_INIT_RAM_SIZE SZ_256K -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #endif /* __CONFIG_H */ diff --git a/include/configs/mys_6ulx.h b/include/configs/mys_6ulx.h index 2571098d06c..ddd46c8f945 100644 --- a/include/configs/mys_6ulx.h +++ b/include/configs/mys_6ulx.h @@ -29,10 +29,6 @@ /* NAND */ #define CFG_SYS_NAND_BASE 0x40000000 -/* USB Configs */ -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 - #define CFG_EXTRA_ENV_SETTINGS \ "console=ttymxc0,115200n8\0" \ "fdt_addr_r=0x82000000\0" \ diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index c03d11dcdae..23eefaffc72 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -18,10 +18,6 @@ #define IMX_FEC_BASE ENET_BASE_ADDR #define CFG_FEC_MXC_PHYADDR 6 -/* USB Configs */ -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 - #ifdef CONFIG_CMD_MMC #define DISTRO_BOOT_DEV_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1) #else diff --git a/include/configs/novena.h b/include/configs/novena.h index 39d3afd1c8e..059b8104e4b 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -51,12 +51,6 @@ /* UART */ #define CFG_MXC_UART_BASE UART2_BASE -/* USB Configs */ -#ifdef CONFIG_CMD_USB -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 -#endif - /* Extra U-Boot environment. */ #define CFG_EXTRA_ENV_SETTINGS \ "fdt_high=0xffffffff\0" \ diff --git a/include/configs/npi_imx6ull.h b/include/configs/npi_imx6ull.h index 5f933391cc0..1caa63f0227 100644 --- a/include/configs/npi_imx6ull.h +++ b/include/configs/npi_imx6ull.h @@ -28,10 +28,6 @@ /* NAND */ #define CFG_SYS_NAND_BASE 0x40000000 -/* USB Configs */ -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 - #ifdef CONFIG_CMD_NET #define CFG_FEC_MXC_PHYADDR 0x1 #endif diff --git a/include/configs/o4-imx6ull-nano.h b/include/configs/o4-imx6ull-nano.h index 9050da8738b..f5a4898f90e 100644 --- a/include/configs/o4-imx6ull-nano.h +++ b/include/configs/o4-imx6ull-nano.h @@ -11,10 +11,6 @@ #define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE -#if IS_ENABLED(CONFIG_CMD_USB) -# define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#endif /* CONFIG_CMD_USB */ - #define CFG_EXTRA_ENV_SETTINGS \ "mmcdev=0\0" \ "mmcpart=2\0" \ diff --git a/include/configs/opos6uldev.h b/include/configs/opos6uldev.h index 1edb1826c4e..fd945235af3 100644 --- a/include/configs/opos6uldev.h +++ b/include/configs/opos6uldev.h @@ -17,12 +17,6 @@ #define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE -/* USB */ -#ifdef CONFIG_USB_EHCI_MX6 -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 -#endif - /* LCD */ #define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR diff --git a/include/configs/pcl063.h b/include/configs/pcl063.h index 38dcee05359..0c96506b5fb 100644 --- a/include/configs/pcl063.h +++ b/include/configs/pcl063.h @@ -41,10 +41,6 @@ /* NAND */ #define CFG_SYS_NAND_BASE 0x40000000 -/* USB Configs */ -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 - #define CFG_EXTRA_ENV_SETTINGS \ "console=ttymxc0,115200n8\0" \ "fdt_addr_r=0x82000000\0" \ diff --git a/include/configs/pcl063_ull.h b/include/configs/pcl063_ull.h index d742201ce43..0f265adc5dc 100644 --- a/include/configs/pcl063_ull.h +++ b/include/configs/pcl063_ull.h @@ -43,10 +43,6 @@ /* NAND */ #define CFG_SYS_NAND_BASE 0x40000000 -/* USB Configs */ -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 - #define ENV_MMC \ "mmcdev=" __stringify(MMC_ROOTFS_DEV) "\0" \ "mmcpart=" __stringify(MMC_ROOTFS_PART) "\0" \ diff --git a/include/configs/phycore_imx8mm.h b/include/configs/phycore_imx8mm.h index dd7cfdba52d..0910ae2d870 100644 --- a/include/configs/phycore_imx8mm.h +++ b/include/configs/phycore_imx8mm.h @@ -29,6 +29,14 @@ "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ "mmcpart=1\0" \ "mmcroot=2\0" \ + "update_offset=0x42\0" \ + "update_filename=flash.bin\0" \ + "update_bootimg=" \ + "mmc dev ${mmcdev} ; " \ + "if dhcp ${loadaddr} ${update_filepath}/${update_filename} ; then " \ + "setexpr fw_sz ${filesize} / 0x200 ; " /* SD block size */ \ + "mmc write ${loadaddr} ${update_offset} ${fw_sz} ; " \ + "fi\0" \ "mmcautodetect=yes\0" \ "mmcargs=setenv bootargs console=${console} " \ "root=/dev/mmcblk${mmcdev}p${mmcroot} rootwait rw\0" \ diff --git a/include/configs/pico-imx6.h b/include/configs/pico-imx6.h index d806d7d9c57..500dd8c069a 100644 --- a/include/configs/pico-imx6.h +++ b/include/configs/pico-imx6.h @@ -15,10 +15,6 @@ /* MMC Configuration */ #define CFG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR -/* USB Configs */ -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 - #define DFU_DEFAULT_POLL_TIMEOUT 300 #define CFG_DFU_ENV_SETTINGS \ diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h index 8a22f0134b3..37f4c7d8a09 100644 --- a/include/configs/pico-imx6ul.h +++ b/include/configs/pico-imx6ul.h @@ -21,10 +21,6 @@ /* MMC Configs */ #define CFG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR -/* USB Configs */ -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 - #define DFU_DEFAULT_POLL_TIMEOUT 300 #define CFG_DFU_ENV_SETTINGS \ diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index e7a8cb20dff..89850d8e4a7 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -105,8 +105,4 @@ #define CFG_SYS_FSL_USDHC_NUM 2 -/* USB Configs */ -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 - #endif diff --git a/include/configs/sniper.h b/include/configs/sniper.h index 45a3102aeee..d0ae5e18605 100644 --- a/include/configs/sniper.h +++ b/include/configs/sniper.h @@ -35,20 +35,6 @@ #define CFG_SYS_SDRAM_BASE 0x80000000 /* - * I2C - */ - -#define CFG_I2C_MULTI_BUS - -/* - * Input - */ - -/* - * SPL - */ - -/* * Serial */ diff --git a/include/configs/somlabs_visionsom_6ull.h b/include/configs/somlabs_visionsom_6ull.h index 041a83b057d..c8fdb40d011 100644 --- a/include/configs/somlabs_visionsom_6ull.h +++ b/include/configs/somlabs_visionsom_6ull.h @@ -59,12 +59,6 @@ /* environment organization */ -/* USB Configs */ -#ifdef CONFIG_CMD_USB -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 -#endif - #ifdef CONFIG_CMD_NET #define CFG_FEC_MXC_PHYADDR 0x1 #endif diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h index 256331ae173..9ef774afd0f 100644 --- a/include/configs/tbs2910.h +++ b/include/configs/tbs2910.h @@ -25,11 +25,6 @@ #define CFG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12) #endif -/* USB */ -#ifdef CONFIG_CMD_USB -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#endif /* CONFIG_CMD_USB */ - #define CFG_EXTRA_ENV_SETTINGS \ BOOTENV \ "bootargs_mmc1=console=ttymxc0,115200 di0_primary console=tty1\0" \ diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index b4a06a75c53..fd4d170456a 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -26,12 +26,14 @@ #define TQMA6_SPI_FLASH_SECTOR_SIZE SZ_64K +#if !defined(CONFIG_DM_PMIC) +#define CFG_POWER_PFUZE100_I2C_ADDR 0x08 +#define TQMA6_PFUZE100_I2C_BUS 2 +#endif + /* MMC Configs */ #define CFG_SYS_FSL_ESDHC_ADDR 0 -/* USB Configs */ -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) - #if defined(CONFIG_TQMA6X_MMC_BOOT) #define TQMA6_UBOOT_OFFSET SZ_1K diff --git a/include/configs/tqma6_wru4.h b/include/configs/tqma6_wru4.h index e06fc7fe155..5e21463305a 100644 --- a/include/configs/tqma6_wru4.h +++ b/include/configs/tqma6_wru4.h @@ -16,7 +16,6 @@ /* Watchdog */ /* Config on-board RTC */ -#define CFG_SYS_RTC_BUS_NUM 2 #define CFG_SYS_I2C_RTC_ADDR 0x68 /* Turn off RTC square-wave output to save battery */ diff --git a/include/configs/usbarmory.h b/include/configs/usbarmory.h index 27e61f5b8f4..5bdd124be65 100644 --- a/include/configs/usbarmory.h +++ b/include/configs/usbarmory.h @@ -23,8 +23,6 @@ #define CFG_SYS_FSL_ESDHC_ADDR 0 /* USB */ -#define CFG_MXC_USB_PORT 1 -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CFG_MXC_USB_FLAGS 0 /* Linux boot */ diff --git a/include/configs/verdin-imx8mm.h b/include/configs/verdin-imx8mm.h index 12d2b682305..b018bbe29dd 100644 --- a/include/configs/verdin-imx8mm.h +++ b/include/configs/verdin-imx8mm.h @@ -63,7 +63,4 @@ #define PHYS_SDRAM_2 0x100000000 #define PHYS_SDRAM_2_SIZE (long)(SZ_1G) -/* USB Configs */ -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) - #endif /* __VERDIN_IMX8MM_H */ diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h index 30654191a26..2cf7bc70d8d 100644 --- a/include/configs/vining_2000.h +++ b/include/configs/vining_2000.h @@ -36,8 +36,6 @@ /* Network */ #define CFG_FEC_MXC_PHYADDR 0x0 -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 #ifdef CONFIG_CMD_PCI #define CFG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(4, 6) diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index 7b8c5cbe7a8..b5b342b3538 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -16,10 +16,6 @@ #define CFG_SYS_FSL_USDHC_NUM 2 #define CFG_SYS_FSL_ESDHC_ADDR 0 -/* USB Configs */ -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 - #define CFG_EXTRA_ENV_SETTINGS \ "console=ttymxc0\0" \ "splashpos=m,m\0" \ diff --git a/include/configs/warp7.h b/include/configs/warp7.h index 0da9250c3b7..a5278d1cb9b 100644 --- a/include/configs/warp7.h +++ b/include/configs/warp7.h @@ -92,7 +92,6 @@ #define CFG_SYS_FSL_USDHC_NUM 1 -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) /* USB Device Firmware Update support */ #define DFU_DEFAULT_POLL_TIMEOUT 300 diff --git a/include/configs/xpress.h b/include/configs/xpress.h index a2aa31008ec..8efebf77c3d 100644 --- a/include/configs/xpress.h +++ b/include/configs/xpress.h @@ -27,10 +27,6 @@ /* Environment is in stored in the eMMC boot partition */ -/* USB Configs */ -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 - #define CFG_FEC_ENET_DEV 0 #define CFG_FEC_MXC_PHYADDR 0x0 diff --git a/include/console.h b/include/console.h index 2617e160073..6b6d0f9de73 100644 --- a/include/console.h +++ b/include/console.h @@ -73,7 +73,7 @@ int console_record_reset_enable(void); * @str: Place to put string * @maxlen: Maximum length of @str including nul terminator * Return: length of string returned, or -ENOSPC if the console buffer was - * overflowed by the output + * overflowed by the output, or -ENOENT if there was nothing to read */ int console_record_readline(char *str, int maxlen); diff --git a/include/dm/test.h b/include/dm/test.h index 02737411a16..3cbf2c740d4 100644 --- a/include/dm/test.h +++ b/include/dm/test.h @@ -143,7 +143,7 @@ extern struct unit_test_state global_dm_test_state; /* Declare a new driver model test */ #define DM_TEST(_name, _flags) \ - UNIT_TEST(_name, UT_TESTF_DM | UT_TESTF_CONSOLE_REC | (_flags), dm_test) + UNIT_TEST(_name, UTF_DM | UTF_CONSOLE | (_flags), dm_test) /* * struct sandbox_sdl_plat - Platform data for the SDL video driver diff --git a/include/dt-bindings/clock/mt7622-clk.h b/include/dt-bindings/clock/mt7622-clk.h index 76fcaff0e42..cdbcaef76eb 100644 --- a/include/dt-bindings/clock/mt7622-clk.h +++ b/include/dt-bindings/clock/mt7622-clk.h @@ -117,46 +117,51 @@ #define CLK_TOP_I2S1_MCK_DIV_PD 104 #define CLK_TOP_I2S2_MCK_DIV_PD 105 #define CLK_TOP_I2S3_MCK_DIV_PD 106 +#define CLK_TOP_A1SYS_HP_DIV_PD 107 +#define CLK_TOP_A2SYS_HP_DIV_PD 108 /* INFRACFG */ -#define CLK_INFRA_DBGCLK_PD 0 -#define CLK_INFRA_TRNG 1 +#define CLK_INFRA_MUX1_SEL 0 +#define CLK_INFRA_DBGCLK_PD 1 #define CLK_INFRA_AUDIO_PD 2 #define CLK_INFRA_IRRX_PD 3 #define CLK_INFRA_APXGPT_PD 4 #define CLK_INFRA_PMIC_PD 5 +#define CLK_INFRA_TRNG 6 /* PERICFG */ -#define CLK_PERI_THERM_PD 0 -#define CLK_PERI_PWM1_PD 1 -#define CLK_PERI_PWM2_PD 2 -#define CLK_PERI_PWM3_PD 3 -#define CLK_PERI_PWM4_PD 4 -#define CLK_PERI_PWM5_PD 5 -#define CLK_PERI_PWM6_PD 6 -#define CLK_PERI_PWM7_PD 7 -#define CLK_PERI_PWM_PD 8 -#define CLK_PERI_AP_DMA_PD 9 -#define CLK_PERI_MSDC30_0_PD 10 -#define CLK_PERI_MSDC30_1_PD 11 -#define CLK_PERI_UART0_PD 12 -#define CLK_PERI_UART1_PD 13 -#define CLK_PERI_UART2_PD 14 -#define CLK_PERI_UART3_PD 15 -#define CLK_PERI_BTIF_PD 16 -#define CLK_PERI_I2C0_PD 17 -#define CLK_PERI_I2C1_PD 18 -#define CLK_PERI_I2C2_PD 19 -#define CLK_PERI_SPI1_PD 20 -#define CLK_PERI_AUXADC_PD 21 -#define CLK_PERI_SPI0_PD 22 -#define CLK_PERI_SNFI_PD 23 -#define CLK_PERI_NFI_PD 24 -#define CLK_PERI_NFIECC_PD 25 -#define CLK_PERI_FLASH_PD 26 -#define CLK_PERI_IRTX_PD 27 +#define CLK_PERIBUS_SEL 0 +#define CLK_PERI_THERM_PD 1 +#define CLK_PERI_PWM1_PD 2 +#define CLK_PERI_PWM2_PD 3 +#define CLK_PERI_PWM3_PD 4 +#define CLK_PERI_PWM4_PD 5 +#define CLK_PERI_PWM5_PD 6 +#define CLK_PERI_PWM6_PD 7 +#define CLK_PERI_PWM7_PD 8 +#define CLK_PERI_PWM_PD 9 +#define CLK_PERI_AP_DMA_PD 10 +#define CLK_PERI_MSDC30_0_PD 11 +#define CLK_PERI_MSDC30_1_PD 12 +#define CLK_PERI_UART0_PD 13 +#define CLK_PERI_UART1_PD 14 +#define CLK_PERI_UART2_PD 15 +#define CLK_PERI_UART3_PD 16 +#define CLK_PERI_UART4_PD 17 +#define CLK_PERI_BTIF_PD 18 +#define CLK_PERI_I2C0_PD 19 +#define CLK_PERI_I2C1_PD 20 +#define CLK_PERI_I2C2_PD 21 +#define CLK_PERI_SPI1_PD 22 +#define CLK_PERI_AUXADC_PD 23 +#define CLK_PERI_SPI0_PD 24 +#define CLK_PERI_SNFI_PD 25 +#define CLK_PERI_NFI_PD 26 +#define CLK_PERI_NFIECC_PD 27 +#define CLK_PERI_FLASH_PD 28 +#define CLK_PERI_IRTX_PD 29 /* APMIXEDSYS */ @@ -169,6 +174,7 @@ #define CLK_APMIXED_AUD2PLL 6 #define CLK_APMIXED_TRGPLL 7 #define CLK_APMIXED_SGMIPLL 8 +#define CLK_APMIXED_MAIN_CORE_EN 9 /* AUDIOSYS */ @@ -206,7 +212,7 @@ #define CLK_AUDIO_DLMCH 31 #define CLK_AUDIO_ARB1 32 #define CLK_AUDIO_AWB 33 -#define CLK_AUDIO_AWB3 34 +#define CLK_AUDIO_AWB2 34 #define CLK_AUDIO_DAI 35 #define CLK_AUDIO_MOD 36 #define CLK_AUDIO_ASRCI3 37 diff --git a/include/dt-bindings/clock/mt7623-clk.h b/include/dt-bindings/clock/mt7623-clk.h index 71ced1593af..0caeb65c3d2 100644 --- a/include/dt-bindings/clock/mt7623-clk.h +++ b/include/dt-bindings/clock/mt7623-clk.h @@ -7,407 +7,477 @@ #define _DT_BINDINGS_CLK_MT2701_H /* TOPCKGEN */ -#define CLK_TOP_FCLKS_OFF 0 - -#define CLK_TOP_DPI 0 -#define CLK_TOP_DMPLL 1 -#define CLK_TOP_VENCPLL 2 -#define CLK_TOP_HDMI_0_PIX340M 3 -#define CLK_TOP_HDMI_0_DEEP340M 4 -#define CLK_TOP_HDMI_0_PLL340M 5 -#define CLK_TOP_HADDS2_FB 6 -#define CLK_TOP_WBG_DIG_416M 7 -#define CLK_TOP_DSI0_LNTC_DSI 8 -#define CLK_TOP_HDMI_SCL_RX 9 -#define CLK_TOP_32K_EXTERNAL 10 -#define CLK_TOP_HDMITX_CLKDIG_CTS 11 -#define CLK_TOP_AUD_EXT1 12 -#define CLK_TOP_AUD_EXT2 13 -#define CLK_TOP_NFI1X_PAD 14 - -#define CLK_TOP_SYSPLL 15 -#define CLK_TOP_SYSPLL_D2 16 -#define CLK_TOP_SYSPLL_D3 17 -#define CLK_TOP_SYSPLL_D5 18 -#define CLK_TOP_SYSPLL_D7 19 -#define CLK_TOP_SYSPLL1_D2 20 -#define CLK_TOP_SYSPLL1_D4 21 -#define CLK_TOP_SYSPLL1_D8 22 -#define CLK_TOP_SYSPLL1_D16 23 -#define CLK_TOP_SYSPLL2_D2 24 -#define CLK_TOP_SYSPLL2_D4 25 -#define CLK_TOP_SYSPLL2_D8 26 -#define CLK_TOP_SYSPLL3_D2 27 -#define CLK_TOP_SYSPLL3_D4 28 -#define CLK_TOP_SYSPLL4_D2 29 -#define CLK_TOP_SYSPLL4_D4 30 -#define CLK_TOP_UNIVPLL 31 -#define CLK_TOP_UNIVPLL_D2 32 -#define CLK_TOP_UNIVPLL_D3 33 -#define CLK_TOP_UNIVPLL_D5 34 -#define CLK_TOP_UNIVPLL_D7 35 -#define CLK_TOP_UNIVPLL_D26 36 -#define CLK_TOP_UNIVPLL_D52 37 -#define CLK_TOP_UNIVPLL_D108 38 -#define CLK_TOP_USB_PHY48M 39 -#define CLK_TOP_UNIVPLL1_D2 40 -#define CLK_TOP_UNIVPLL1_D4 41 -#define CLK_TOP_UNIVPLL1_D8 42 -#define CLK_TOP_UNIVPLL2_D2 43 -#define CLK_TOP_UNIVPLL2_D4 44 -#define CLK_TOP_UNIVPLL2_D8 45 -#define CLK_TOP_UNIVPLL2_D16 46 -#define CLK_TOP_UNIVPLL2_D32 47 -#define CLK_TOP_UNIVPLL3_D2 48 -#define CLK_TOP_UNIVPLL3_D4 49 -#define CLK_TOP_UNIVPLL3_D8 50 -#define CLK_TOP_MSDCPLL 51 -#define CLK_TOP_MSDCPLL_D2 52 -#define CLK_TOP_MSDCPLL_D4 53 -#define CLK_TOP_MSDCPLL_D8 54 -#define CLK_TOP_MMPLL 55 -#define CLK_TOP_MMPLL_D2 56 -#define CLK_TOP_DMPLL_D2 57 -#define CLK_TOP_DMPLL_D4 58 -#define CLK_TOP_DMPLL_X2 59 -#define CLK_TOP_TVDPLL 60 -#define CLK_TOP_TVDPLL_D2 61 -#define CLK_TOP_TVDPLL_D4 62 -#define CLK_TOP_VDECPLL 63 -#define CLK_TOP_TVD2PLL 64 -#define CLK_TOP_TVD2PLL_D2 65 -#define CLK_TOP_MIPIPLL 66 -#define CLK_TOP_MIPIPLL_D2 67 -#define CLK_TOP_MIPIPLL_D4 68 -#define CLK_TOP_HDMIPLL 69 -#define CLK_TOP_HDMIPLL_D2 70 -#define CLK_TOP_HDMIPLL_D3 71 -#define CLK_TOP_ARMPLL_1P3G 72 -#define CLK_TOP_AUDPLL 73 -#define CLK_TOP_AUDPLL_D4 74 -#define CLK_TOP_AUDPLL_D8 75 -#define CLK_TOP_AUDPLL_D16 76 -#define CLK_TOP_AUDPLL_D24 77 -#define CLK_TOP_AUD1PLL_98M 78 -#define CLK_TOP_AUD2PLL_90M 79 -#define CLK_TOP_HADDS2PLL_98M 80 -#define CLK_TOP_HADDS2PLL_294M 81 -#define CLK_TOP_ETHPLL_500M 82 -#define CLK_TOP_CLK26M_D8 83 -#define CLK_TOP_32K_INTERNAL 84 -#define CLK_TOP_AXISEL_D4 85 -#define CLK_TOP_8BDAC 86 - -#define CLK_TOP_AXI_SEL 87 -#define CLK_TOP_MEM_SEL 88 -#define CLK_TOP_DDRPHYCFG_SEL 89 -#define CLK_TOP_MM_SEL 90 -#define CLK_TOP_PWM_SEL 91 -#define CLK_TOP_VDEC_SEL 92 -#define CLK_TOP_MFG_SEL 93 -#define CLK_TOP_CAMTG_SEL 94 -#define CLK_TOP_UART_SEL 95 -#define CLK_TOP_SPI0_SEL 96 -#define CLK_TOP_USB20_SEL 97 -#define CLK_TOP_MSDC30_0_SEL 98 -#define CLK_TOP_MSDC30_1_SEL 99 -#define CLK_TOP_MSDC30_2_SEL 100 -#define CLK_TOP_AUDIO_SEL 101 -#define CLK_TOP_AUDINTBUS_SEL 102 -#define CLK_TOP_PMICSPI_SEL 103 -#define CLK_TOP_SCP_SEL 104 -#define CLK_TOP_DPI0_SEL 105 -#define CLK_TOP_DPI1_SEL 106 -#define CLK_TOP_TVE_SEL 107 -#define CLK_TOP_HDMI_SEL 108 -#define CLK_TOP_APLL_SEL 109 -#define CLK_TOP_RTC_SEL 110 -#define CLK_TOP_NFI2X_SEL 111 -#define CLK_TOP_EMMC_HCLK_SEL 112 -#define CLK_TOP_FLASH_SEL 113 -#define CLK_TOP_DI_SEL 114 -#define CLK_TOP_NR_SEL 115 -#define CLK_TOP_OSD_SEL 116 -#define CLK_TOP_HDMIRX_BIST_SEL 117 -#define CLK_TOP_INTDIR_SEL 118 -#define CLK_TOP_ASM_I_SEL 119 -#define CLK_TOP_ASM_M_SEL 120 -#define CLK_TOP_ASM_H_SEL 121 -#define CLK_TOP_MS_CARD_SEL 122 -#define CLK_TOP_ETHIF_SEL 123 -#define CLK_TOP_HDMIRX26_24_SEL 124 -#define CLK_TOP_MSDC30_3_SEL 125 -#define CLK_TOP_CMSYS_SEL 126 -#define CLK_TOP_SPI1_SEL 127 -#define CLK_TOP_SPI2_SEL 128 -#define CLK_TOP_8BDAC_SEL 129 -#define CLK_TOP_AUD2DVD_SEL 130 -#define CLK_TOP_PADMCLK_SEL 131 -#define CLK_TOP_AUD_MUX1_SEL 132 -#define CLK_TOP_AUD_MUX2_SEL 133 -#define CLK_TOP_AUDPLL_MUX_SEL 134 -#define CLK_TOP_AUD_K1_SRC_SEL 135 -#define CLK_TOP_AUD_K2_SRC_SEL 136 -#define CLK_TOP_AUD_K3_SRC_SEL 137 -#define CLK_TOP_AUD_K4_SRC_SEL 138 -#define CLK_TOP_AUD_K5_SRC_SEL 139 -#define CLK_TOP_AUD_K6_SRC_SEL 140 - -#define CLK_TOP_AUD_EXTCK1_DIV 141 -#define CLK_TOP_AUD_EXTCK2_DIV 142 -#define CLK_TOP_AUD_MUX1_DIV 143 -#define CLK_TOP_AUD_MUX2_DIV 144 -#define CLK_TOP_AUD_K1_SRC_DIV 145 -#define CLK_TOP_AUD_K2_SRC_DIV 146 -#define CLK_TOP_AUD_K3_SRC_DIV 147 -#define CLK_TOP_AUD_K4_SRC_DIV 148 -#define CLK_TOP_AUD_K5_SRC_DIV 149 -#define CLK_TOP_AUD_K6_SRC_DIV 150 -#define CLK_TOP_AUD_48K_TIMING 151 -#define CLK_TOP_AUD_44K_TIMING 152 -#define CLK_TOP_AUD_I2S1_MCLK 153 -#define CLK_TOP_AUD_I2S2_MCLK 154 -#define CLK_TOP_AUD_I2S3_MCLK 155 -#define CLK_TOP_AUD_I2S4_MCLK 156 -#define CLK_TOP_AUD_I2S5_MCLK 157 -#define CLK_TOP_AUD_I2S6_MCLK 158 +#define CLK_TOP_SYSPLL 1 +#define CLK_TOP_SYSPLL_D2 2 +#define CLK_TOP_SYSPLL_D3 3 +#define CLK_TOP_SYSPLL_D5 4 +#define CLK_TOP_SYSPLL_D7 5 +#define CLK_TOP_SYSPLL1_D2 6 +#define CLK_TOP_SYSPLL1_D4 7 +#define CLK_TOP_SYSPLL1_D8 8 +#define CLK_TOP_SYSPLL1_D16 9 +#define CLK_TOP_SYSPLL2_D2 10 +#define CLK_TOP_SYSPLL2_D4 11 +#define CLK_TOP_SYSPLL2_D8 12 +#define CLK_TOP_SYSPLL3_D2 13 +#define CLK_TOP_SYSPLL3_D4 14 +#define CLK_TOP_SYSPLL4_D2 15 +#define CLK_TOP_SYSPLL4_D4 16 +#define CLK_TOP_UNIVPLL 17 +#define CLK_TOP_UNIVPLL_D2 18 +#define CLK_TOP_UNIVPLL_D3 19 +#define CLK_TOP_UNIVPLL_D5 20 +#define CLK_TOP_UNIVPLL_D7 21 +#define CLK_TOP_UNIVPLL_D26 22 +#define CLK_TOP_UNIVPLL_D52 23 +#define CLK_TOP_UNIVPLL_D108 24 +#define CLK_TOP_USB_PHY48M 25 +#define CLK_TOP_UNIVPLL1_D2 26 +#define CLK_TOP_UNIVPLL1_D4 27 +#define CLK_TOP_UNIVPLL1_D8 28 +#define CLK_TOP_UNIVPLL2_D2 29 +#define CLK_TOP_UNIVPLL2_D4 30 +#define CLK_TOP_UNIVPLL2_D8 31 +#define CLK_TOP_UNIVPLL2_D16 32 +#define CLK_TOP_UNIVPLL2_D32 33 +#define CLK_TOP_UNIVPLL3_D2 34 +#define CLK_TOP_UNIVPLL3_D4 35 +#define CLK_TOP_UNIVPLL3_D8 36 +#define CLK_TOP_MSDCPLL 37 +#define CLK_TOP_MSDCPLL_D2 38 +#define CLK_TOP_MSDCPLL_D4 39 +#define CLK_TOP_MSDCPLL_D8 40 +#define CLK_TOP_MMPLL 41 +#define CLK_TOP_MMPLL_D2 42 +#define CLK_TOP_DMPLL 43 +#define CLK_TOP_DMPLL_D2 44 +#define CLK_TOP_DMPLL_D4 45 +#define CLK_TOP_DMPLL_X2 46 +#define CLK_TOP_TVDPLL 47 +#define CLK_TOP_TVDPLL_D2 48 +#define CLK_TOP_TVDPLL_D4 49 +#define CLK_TOP_TVD2PLL 50 +#define CLK_TOP_TVD2PLL_D2 51 +#define CLK_TOP_HADDS2PLL_98M 52 +#define CLK_TOP_HADDS2PLL_294M 53 +#define CLK_TOP_HADDS2_FB 54 +#define CLK_TOP_MIPIPLL_D2 55 +#define CLK_TOP_MIPIPLL_D4 56 +#define CLK_TOP_HDMIPLL 57 +#define CLK_TOP_HDMIPLL_D2 58 +#define CLK_TOP_HDMIPLL_D3 59 +#define CLK_TOP_HDMI_SCL_RX 60 +#define CLK_TOP_HDMI_0_PIX340M 61 +#define CLK_TOP_HDMI_0_DEEP340M 62 +#define CLK_TOP_HDMI_0_PLL340M 63 +#define CLK_TOP_AUD1PLL_98M 64 +#define CLK_TOP_AUD2PLL_90M 65 +#define CLK_TOP_AUDPLL 66 +#define CLK_TOP_AUDPLL_D4 67 +#define CLK_TOP_AUDPLL_D8 68 +#define CLK_TOP_AUDPLL_D16 69 +#define CLK_TOP_AUDPLL_D24 70 +#define CLK_TOP_ETHPLL_500M 71 +#define CLK_TOP_VDECPLL 72 +#define CLK_TOP_VENCPLL 73 +#define CLK_TOP_MIPIPLL 74 +#define CLK_TOP_ARMPLL_1P3G 75 + +#define CLK_TOP_MM_SEL 76 +#define CLK_TOP_DDRPHYCFG_SEL 77 +#define CLK_TOP_MEM_SEL 78 +#define CLK_TOP_AXI_SEL 79 +#define CLK_TOP_CAMTG_SEL 80 +#define CLK_TOP_MFG_SEL 81 +#define CLK_TOP_VDEC_SEL 82 +#define CLK_TOP_PWM_SEL 83 +#define CLK_TOP_MSDC30_0_SEL 84 +#define CLK_TOP_USB20_SEL 85 +#define CLK_TOP_SPI0_SEL 86 +#define CLK_TOP_UART_SEL 87 +#define CLK_TOP_AUDINTBUS_SEL 88 +#define CLK_TOP_AUDIO_SEL 89 +#define CLK_TOP_MSDC30_2_SEL 90 +#define CLK_TOP_MSDC30_1_SEL 91 +#define CLK_TOP_DPI1_SEL 92 +#define CLK_TOP_DPI0_SEL 93 +#define CLK_TOP_SCP_SEL 94 +#define CLK_TOP_PMICSPI_SEL 95 +#define CLK_TOP_APLL_SEL 96 +#define CLK_TOP_HDMI_SEL 97 +#define CLK_TOP_TVE_SEL 98 +#define CLK_TOP_EMMC_HCLK_SEL 99 +#define CLK_TOP_NFI2X_SEL 100 +#define CLK_TOP_RTC_SEL 101 +#define CLK_TOP_OSD_SEL 102 +#define CLK_TOP_NR_SEL 103 +#define CLK_TOP_DI_SEL 104 +#define CLK_TOP_FLASH_SEL 105 +#define CLK_TOP_ASM_M_SEL 106 +#define CLK_TOP_ASM_I_SEL 107 +#define CLK_TOP_INTDIR_SEL 108 +#define CLK_TOP_HDMIRX_BIST_SEL 109 +#define CLK_TOP_ETHIF_SEL 110 +#define CLK_TOP_MS_CARD_SEL 111 +#define CLK_TOP_ASM_H_SEL 112 +#define CLK_TOP_SPI1_SEL 113 +#define CLK_TOP_CMSYS_SEL 114 +#define CLK_TOP_MSDC30_3_SEL 115 +#define CLK_TOP_HDMIRX26_24_SEL 116 +#define CLK_TOP_AUD2DVD_SEL 117 +#define CLK_TOP_8BDAC_SEL 118 +#define CLK_TOP_SPI2_SEL 119 +#define CLK_TOP_AUD_MUX1_SEL 120 +#define CLK_TOP_AUD_MUX2_SEL 121 +#define CLK_TOP_AUDPLL_MUX_SEL 122 +#define CLK_TOP_AUD_K1_SRC_SEL 123 +#define CLK_TOP_AUD_K2_SRC_SEL 124 +#define CLK_TOP_AUD_K3_SRC_SEL 125 +#define CLK_TOP_AUD_K4_SRC_SEL 126 +#define CLK_TOP_AUD_K5_SRC_SEL 127 +#define CLK_TOP_AUD_K6_SRC_SEL 128 +#define CLK_TOP_PADMCLK_SEL 129 +#define CLK_TOP_AUD_EXTCK1_DIV 130 +#define CLK_TOP_AUD_EXTCK2_DIV 131 +#define CLK_TOP_AUD_MUX1_DIV 132 +#define CLK_TOP_AUD_MUX2_DIV 133 +#define CLK_TOP_AUD_K1_SRC_DIV 134 +#define CLK_TOP_AUD_K2_SRC_DIV 135 +#define CLK_TOP_AUD_K3_SRC_DIV 136 +#define CLK_TOP_AUD_K4_SRC_DIV 137 +#define CLK_TOP_AUD_K5_SRC_DIV 138 +#define CLK_TOP_AUD_K6_SRC_DIV 139 +#define CLK_TOP_AUD_I2S1_MCLK 140 +#define CLK_TOP_AUD_I2S2_MCLK 141 +#define CLK_TOP_AUD_I2S3_MCLK 142 +#define CLK_TOP_AUD_I2S4_MCLK 143 +#define CLK_TOP_AUD_I2S5_MCLK 144 +#define CLK_TOP_AUD_I2S6_MCLK 145 +#define CLK_TOP_AUD_48K_TIMING 146 +#define CLK_TOP_AUD_44K_TIMING 147 + +#define CLK_TOP_32K_INTERNAL 148 +#define CLK_TOP_32K_EXTERNAL 149 +#define CLK_TOP_CLK26M_D8 150 +#define CLK_TOP_8BDAC 151 +#define CLK_TOP_WBG_DIG_416M 152 +#define CLK_TOP_DPI 153 +#define CLK_TOP_DSI0_LNTC_DSI 154 +#define CLK_TOP_AUD_EXT1 155 +#define CLK_TOP_AUD_EXT2 156 +#define CLK_TOP_NFI1X_PAD 157 +#define CLK_TOP_AXISEL_D4 158 #define CLK_TOP_NR 159 /* APMIXEDSYS */ -#define CLK_APMIXED_ARMPLL 0 -#define CLK_APMIXED_MAINPLL 1 -#define CLK_APMIXED_UNIVPLL 2 -#define CLK_APMIXED_MMPLL 3 -#define CLK_APMIXED_MSDCPLL 4 -#define CLK_APMIXED_TVDPLL 5 -#define CLK_APMIXED_AUD1PLL 6 -#define CLK_APMIXED_TRGPLL 7 -#define CLK_APMIXED_ETHPLL 8 -#define CLK_APMIXED_VDECPLL 9 -#define CLK_APMIXED_HADDS2PLL 10 -#define CLK_APMIXED_AUD2PLL 11 -#define CLK_APMIXED_TVD2PLL 12 -#define CLK_APMIXED_NR 13 + +#define CLK_APMIXED_ARMPLL 1 +#define CLK_APMIXED_MAINPLL 2 +#define CLK_APMIXED_UNIVPLL 3 +#define CLK_APMIXED_MMPLL 4 +#define CLK_APMIXED_MSDCPLL 5 +#define CLK_APMIXED_TVDPLL 6 +#define CLK_APMIXED_AUD1PLL 7 +#define CLK_APMIXED_TRGPLL 8 +#define CLK_APMIXED_ETHPLL 9 +#define CLK_APMIXED_VDECPLL 10 +#define CLK_APMIXED_HADDS2PLL 11 +#define CLK_APMIXED_AUD2PLL 12 +#define CLK_APMIXED_TVD2PLL 13 +#define CLK_APMIXED_HDMI_REF 14 +#define CLK_APMIXED_NR 15 + +/* DDRPHY */ + +#define CLK_DDRPHY_VENCPLL 1 +#define CLK_DDRPHY_NR 2 /* INFRACFG */ -#define CLK_INFRA_DBG 0 -#define CLK_INFRA_SMI 1 -#define CLK_INFRA_QAXI_CM4 2 -#define CLK_INFRA_AUD_SPLIN_B 3 -#define CLK_INFRA_AUDIO 4 -#define CLK_INFRA_EFUSE 5 -#define CLK_INFRA_L2C_SRAM 6 -#define CLK_INFRA_M4U 7 -#define CLK_INFRA_CONNMCU 8 -#define CLK_INFRA_TRNG 9 -#define CLK_INFRA_RAMBUFIF 10 -#define CLK_INFRA_CPUM 11 -#define CLK_INFRA_KP 12 -#define CLK_INFRA_CEC 13 -#define CLK_INFRA_IRRX 14 -#define CLK_INFRA_PMICSPI 15 -#define CLK_INFRA_PMICWRAP 16 -#define CLK_INFRA_DDCCI 17 -#define CLK_INFRA_CPUSEL 18 -#define CLK_INFRA_NR 19 + +#define CLK_INFRA_DBG 1 +#define CLK_INFRA_SMI 2 +#define CLK_INFRA_QAXI_CM4 3 +#define CLK_INFRA_AUD_SPLIN_B 4 +#define CLK_INFRA_AUDIO 5 +#define CLK_INFRA_EFUSE 6 +#define CLK_INFRA_L2C_SRAM 7 +#define CLK_INFRA_M4U 8 +#define CLK_INFRA_CONNMCU 9 +#define CLK_INFRA_TRNG 10 +#define CLK_INFRA_RAMBUFIF 11 +#define CLK_INFRA_CPUM 12 +#define CLK_INFRA_KP 13 +#define CLK_INFRA_CEC 14 +#define CLK_INFRA_IRRX 15 +#define CLK_INFRA_PMICSPI 16 +#define CLK_INFRA_PMICWRAP 17 +#define CLK_INFRA_DDCCI 18 +#define CLK_INFRA_CLK_13M 19 +#define CLK_INFRA_CPUSEL 20 +#define CLK_INFRA_NR 21 /* PERICFG */ -#define CLK_PERI_NFI 0 -#define CLK_PERI_THERM 1 -#define CLK_PERI_PWM1 2 -#define CLK_PERI_PWM2 3 -#define CLK_PERI_PWM3 4 -#define CLK_PERI_PWM4 5 -#define CLK_PERI_PWM5 6 -#define CLK_PERI_PWM6 7 -#define CLK_PERI_PWM7 8 -#define CLK_PERI_PWM 9 -#define CLK_PERI_USB0 10 -#define CLK_PERI_USB1 11 -#define CLK_PERI_AP_DMA 12 -#define CLK_PERI_MSDC30_0 13 -#define CLK_PERI_MSDC30_1 14 -#define CLK_PERI_MSDC30_2 15 -#define CLK_PERI_MSDC30_3 16 -#define CLK_PERI_MSDC50_3 17 -#define CLK_PERI_NLI 18 -#define CLK_PERI_UART0 19 -#define CLK_PERI_UART1 20 -#define CLK_PERI_UART2 21 -#define CLK_PERI_UART3 22 -#define CLK_PERI_BTIF 23 -#define CLK_PERI_I2C0 24 -#define CLK_PERI_I2C1 25 -#define CLK_PERI_I2C2 26 -#define CLK_PERI_I2C3 27 -#define CLK_PERI_AUXADC 28 -#define CLK_PERI_SPI0 39 -#define CLK_PERI_ETH 30 -#define CLK_PERI_USB0_MCU 31 - -#define CLK_PERI_USB1_MCU 32 -#define CLK_PERI_USB_SLV 33 -#define CLK_PERI_GCPU 34 -#define CLK_PERI_NFI_ECC 35 -#define CLK_PERI_NFI_PAD 36 -#define CLK_PERI_FLASH 37 -#define CLK_PERI_HOST89_INT 38 -#define CLK_PERI_HOST89_SPI 39 -#define CLK_PERI_HOST89_DVD 40 -#define CLK_PERI_SPI1 41 -#define CLK_PERI_SPI2 42 -#define CLK_PERI_FCI 43 -#define CLK_PERI_NR 44 + +#define CLK_PERI_NFI 1 +#define CLK_PERI_THERM 2 +#define CLK_PERI_PWM1 3 +#define CLK_PERI_PWM2 4 +#define CLK_PERI_PWM3 5 +#define CLK_PERI_PWM4 6 +#define CLK_PERI_PWM5 7 +#define CLK_PERI_PWM6 8 +#define CLK_PERI_PWM7 9 +#define CLK_PERI_PWM 10 +#define CLK_PERI_USB0 11 +#define CLK_PERI_USB1 12 +#define CLK_PERI_AP_DMA 13 +#define CLK_PERI_MSDC30_0 14 +#define CLK_PERI_MSDC30_1 15 +#define CLK_PERI_MSDC30_2 16 +#define CLK_PERI_MSDC30_3 17 +#define CLK_PERI_MSDC50_3 18 +#define CLK_PERI_NLI 19 +#define CLK_PERI_UART0 20 +#define CLK_PERI_UART1 21 +#define CLK_PERI_UART2 22 +#define CLK_PERI_UART3 23 +#define CLK_PERI_BTIF 24 +#define CLK_PERI_I2C0 25 +#define CLK_PERI_I2C1 26 +#define CLK_PERI_I2C2 27 +#define CLK_PERI_I2C3 28 +#define CLK_PERI_AUXADC 29 +#define CLK_PERI_SPI0 30 +#define CLK_PERI_ETH 31 +#define CLK_PERI_USB0_MCU 32 + +#define CLK_PERI_USB1_MCU 33 +#define CLK_PERI_USB_SLV 34 +#define CLK_PERI_GCPU 35 +#define CLK_PERI_NFI_ECC 36 +#define CLK_PERI_NFI_PAD 37 +#define CLK_PERI_FLASH 38 +#define CLK_PERI_HOST89_INT 39 +#define CLK_PERI_HOST89_SPI 40 +#define CLK_PERI_HOST89_DVD 41 +#define CLK_PERI_SPI1 42 +#define CLK_PERI_SPI2 43 +#define CLK_PERI_FCI 44 + +#define CLK_PERI_UART0_SEL 45 +#define CLK_PERI_UART1_SEL 46 +#define CLK_PERI_UART2_SEL 47 +#define CLK_PERI_UART3_SEL 48 +#define CLK_PERI_NR 49 /* AUDIO */ -#define CLK_AUD_AFE 0 -#define CLK_AUD_LRCK_DETECT 1 -#define CLK_AUD_I2S 2 -#define CLK_AUD_APLL_TUNER 3 -#define CLK_AUD_HDMI 4 -#define CLK_AUD_SPDF 5 -#define CLK_AUD_SPDF2 6 -#define CLK_AUD_APLL 7 -#define CLK_AUD_TML 8 -#define CLK_AUD_AHB_IDLE_EXT 9 -#define CLK_AUD_AHB_IDLE_INT 10 - -#define CLK_AUD_I2SIN1 11 -#define CLK_AUD_I2SIN2 12 -#define CLK_AUD_I2SIN3 13 -#define CLK_AUD_I2SIN4 14 -#define CLK_AUD_I2SIN5 15 -#define CLK_AUD_I2SIN6 16 -#define CLK_AUD_I2SO1 17 -#define CLK_AUD_I2SO2 18 -#define CLK_AUD_I2SO3 19 -#define CLK_AUD_I2SO4 20 -#define CLK_AUD_I2SO5 21 -#define CLK_AUD_I2SO6 22 -#define CLK_AUD_ASRCI1 23 -#define CLK_AUD_ASRCI2 24 -#define CLK_AUD_ASRCO1 25 -#define CLK_AUD_ASRCO2 26 -#define CLK_AUD_ASRC11 27 -#define CLK_AUD_ASRC12 28 -#define CLK_AUD_HDMIRX 29 -#define CLK_AUD_INTDIR 30 -#define CLK_AUD_A1SYS 31 -#define CLK_AUD_A2SYS 32 -#define CLK_AUD_AFE_CONN 33 -#define CLK_AUD_AFE_PCMIF 34 -#define CLK_AUD_AFE_MRGIF 35 - -#define CLK_AUD_MMIF_UL1 36 -#define CLK_AUD_MMIF_UL2 37 -#define CLK_AUD_MMIF_UL3 38 -#define CLK_AUD_MMIF_UL4 39 -#define CLK_AUD_MMIF_UL5 40 -#define CLK_AUD_MMIF_UL6 41 -#define CLK_AUD_MMIF_DL1 42 -#define CLK_AUD_MMIF_DL2 43 -#define CLK_AUD_MMIF_DL3 44 -#define CLK_AUD_MMIF_DL4 45 -#define CLK_AUD_MMIF_DL5 46 -#define CLK_AUD_MMIF_DL6 47 -#define CLK_AUD_MMIF_DLMCH 48 -#define CLK_AUD_MMIF_ARB1 49 -#define CLK_AUD_MMIF_AWB1 50 -#define CLK_AUD_MMIF_AWB2 51 -#define CLK_AUD_MMIF_DAI 52 - -#define CLK_AUD_DMIC1 53 -#define CLK_AUD_DMIC2 54 -#define CLK_AUD_ASRCI3 55 -#define CLK_AUD_ASRCI4 56 -#define CLK_AUD_ASRCI5 57 -#define CLK_AUD_ASRCI6 58 -#define CLK_AUD_ASRCO3 59 -#define CLK_AUD_ASRCO4 60 -#define CLK_AUD_ASRCO5 61 -#define CLK_AUD_ASRCO6 62 -#define CLK_AUD_MEM_ASRC1 63 -#define CLK_AUD_MEM_ASRC2 64 -#define CLK_AUD_MEM_ASRC3 65 -#define CLK_AUD_MEM_ASRC4 66 -#define CLK_AUD_MEM_ASRC5 67 -#define CLK_AUD_DSD_ENC 68 -#define CLK_AUD_ASRC_BRG 60 -#define CLK_AUD_NR 70 + +#define CLK_AUD_AFE 1 +#define CLK_AUD_LRCK_DETECT 2 +#define CLK_AUD_I2S 3 +#define CLK_AUD_APLL_TUNER 4 +#define CLK_AUD_HDMI 5 +#define CLK_AUD_SPDF 6 +#define CLK_AUD_SPDF2 7 +#define CLK_AUD_APLL 8 +#define CLK_AUD_TML 9 +#define CLK_AUD_AHB_IDLE_EXT 10 +#define CLK_AUD_AHB_IDLE_INT 11 + +#define CLK_AUD_I2SIN1 12 +#define CLK_AUD_I2SIN2 13 +#define CLK_AUD_I2SIN3 14 +#define CLK_AUD_I2SIN4 15 +#define CLK_AUD_I2SIN5 16 +#define CLK_AUD_I2SIN6 17 +#define CLK_AUD_I2SO1 18 +#define CLK_AUD_I2SO2 19 +#define CLK_AUD_I2SO3 20 +#define CLK_AUD_I2SO4 21 +#define CLK_AUD_I2SO5 22 +#define CLK_AUD_I2SO6 23 +#define CLK_AUD_ASRCI1 24 +#define CLK_AUD_ASRCI2 25 +#define CLK_AUD_ASRCO1 26 +#define CLK_AUD_ASRCO2 27 +#define CLK_AUD_ASRC11 28 +#define CLK_AUD_ASRC12 29 +#define CLK_AUD_HDMIRX 30 +#define CLK_AUD_INTDIR 31 +#define CLK_AUD_A1SYS 32 +#define CLK_AUD_A2SYS 33 +#define CLK_AUD_AFE_CONN 34 +#define CLK_AUD_AFE_PCMIF 35 +#define CLK_AUD_AFE_MRGIF 36 + +#define CLK_AUD_MMIF_UL1 37 +#define CLK_AUD_MMIF_UL2 38 +#define CLK_AUD_MMIF_UL3 39 +#define CLK_AUD_MMIF_UL4 40 +#define CLK_AUD_MMIF_UL5 41 +#define CLK_AUD_MMIF_UL6 42 +#define CLK_AUD_MMIF_DL1 43 +#define CLK_AUD_MMIF_DL2 44 +#define CLK_AUD_MMIF_DL3 45 +#define CLK_AUD_MMIF_DL4 46 +#define CLK_AUD_MMIF_DL5 47 +#define CLK_AUD_MMIF_DL6 48 +#define CLK_AUD_MMIF_DLMCH 49 +#define CLK_AUD_MMIF_ARB1 50 +#define CLK_AUD_MMIF_AWB1 51 +#define CLK_AUD_MMIF_AWB2 52 +#define CLK_AUD_MMIF_DAI 53 + +#define CLK_AUD_DMIC1 54 +#define CLK_AUD_DMIC2 55 +#define CLK_AUD_ASRCI3 56 +#define CLK_AUD_ASRCI4 57 +#define CLK_AUD_ASRCI5 58 +#define CLK_AUD_ASRCI6 59 +#define CLK_AUD_ASRCO3 60 +#define CLK_AUD_ASRCO4 61 +#define CLK_AUD_ASRCO5 62 +#define CLK_AUD_ASRCO6 63 +#define CLK_AUD_MEM_ASRC1 64 +#define CLK_AUD_MEM_ASRC2 65 +#define CLK_AUD_MEM_ASRC3 66 +#define CLK_AUD_MEM_ASRC4 67 +#define CLK_AUD_MEM_ASRC5 68 +#define CLK_AUD_DSD_ENC 69 +#define CLK_AUD_ASRC_BRG 70 +#define CLK_AUD_NR 71 /* MMSYS */ -#define CLK_MM_SMI_COMMON 0 -#define CLK_MM_SMI_LARB0 1 -#define CLK_MM_CMDQ 2 -#define CLK_MM_MUTEX 3 -#define CLK_MM_DISP_COLOR 4 -#define CLK_MM_DISP_BLS 5 -#define CLK_MM_DISP_WDMA 6 -#define CLK_MM_DISP_RDMA 7 -#define CLK_MM_DISP_OVL 8 -#define CLK_MM_MDP_TDSHP 9 -#define CLK_MM_MDP_WROT 10 -#define CLK_MM_MDP_WDMA 11 -#define CLK_MM_MDP_RSZ1 12 -#define CLK_MM_MDP_RSZ0 13 -#define CLK_MM_MDP_RDMA 14 -#define CLK_MM_MDP_BLS_26M 15 -#define CLK_MM_CAM_MDP 16 -#define CLK_MM_FAKE_ENG 17 -#define CLK_MM_MUTEX_32K 18 -#define CLK_MM_DISP_RDMA1 19 -#define CLK_MM_DISP_UFOE 20 - -#define CLK_MM_DSI_ENGINE 21 -#define CLK_MM_DSI_DIG 22 -#define CLK_MM_DPI_DIGL 23 -#define CLK_MM_DPI_ENGINE 24 -#define CLK_MM_DPI1_DIGL 25 -#define CLK_MM_DPI1_ENGINE 26 -#define CLK_MM_TVE_OUTPUT 27 -#define CLK_MM_TVE_INPUT 28 -#define CLK_MM_HDMI_PIXEL 29 -#define CLK_MM_HDMI_PLL 30 -#define CLK_MM_HDMI_AUDIO 31 -#define CLK_MM_HDMI_SPDIF 32 -#define CLK_MM_TVE_FMM 33 -#define CLK_MM_NR 34 + +#define CLK_MM_SMI_COMMON 1 +#define CLK_MM_SMI_LARB0 2 +#define CLK_MM_CMDQ 3 +#define CLK_MM_MUTEX 4 +#define CLK_MM_DISP_COLOR 5 +#define CLK_MM_DISP_BLS 6 +#define CLK_MM_DISP_WDMA 7 +#define CLK_MM_DISP_RDMA 8 +#define CLK_MM_DISP_OVL 9 +#define CLK_MM_MDP_TDSHP 10 +#define CLK_MM_MDP_WROT 11 +#define CLK_MM_MDP_WDMA 12 +#define CLK_MM_MDP_RSZ1 13 +#define CLK_MM_MDP_RSZ0 14 +#define CLK_MM_MDP_RDMA 15 +#define CLK_MM_MDP_BLS_26M 16 +#define CLK_MM_CAM_MDP 17 +#define CLK_MM_FAKE_ENG 18 +#define CLK_MM_MUTEX_32K 19 +#define CLK_MM_DISP_RDMA1 20 +#define CLK_MM_DISP_UFOE 21 + +#define CLK_MM_DSI_ENGINE 22 +#define CLK_MM_DSI_DIG 23 +#define CLK_MM_DPI_DIGL 24 +#define CLK_MM_DPI_ENGINE 25 +#define CLK_MM_DPI1_DIGL 26 +#define CLK_MM_DPI1_ENGINE 27 +#define CLK_MM_TVE_OUTPUT 28 +#define CLK_MM_TVE_INPUT 29 +#define CLK_MM_HDMI_PIXEL 30 +#define CLK_MM_HDMI_PLL 31 +#define CLK_MM_HDMI_AUDIO 32 +#define CLK_MM_HDMI_SPDIF 33 +#define CLK_MM_TVE_FMM 34 +#define CLK_MM_NR 35 /* IMGSYS */ -#define CLK_IMG_SMI_COMM 0 -#define CLK_IMG_RESZ 1 -#define CLK_IMG_JPGDEC_SMI 2 -#define CLK_IMG_JPGDEC 3 -#define CLK_IMG_VENC_LT 4 -#define CLK_IMG_VENC 5 -#define CLK_IMG_NR 6 + +#define CLK_IMG_SMI_COMM 1 +#define CLK_IMG_RESZ 2 +#define CLK_IMG_JPGDEC_SMI 3 +#define CLK_IMG_JPGDEC 4 +#define CLK_IMG_VENC_LT 5 +#define CLK_IMG_VENC 6 +#define CLK_IMG_NR 7 /* VDEC */ -#define CLK_VDEC_CKGEN 0 -#define CLK_VDEC_LARB 1 -#define CLK_VDEC_NR 2 + +#define CLK_VDEC_CKGEN 1 +#define CLK_VDEC_LARB 2 +#define CLK_VDEC_NR 3 /* HIFSYS */ -#define CLK_HIFSYS_USB0PHY 0 -#define CLK_HIFSYS_USB1PHY 1 -#define CLK_HIFSYS_PCIE0 2 -#define CLK_HIFSYS_PCIE1 3 -#define CLK_HIFSYS_PCIE2 4 -#define CLK_HIFSYS_NR 5 + +#define CLK_HIFSYS_USB0PHY 1 +#define CLK_HIFSYS_USB1PHY 2 +#define CLK_HIFSYS_PCIE0 3 +#define CLK_HIFSYS_PCIE1 4 +#define CLK_HIFSYS_PCIE2 5 +#define CLK_HIFSYS_NR 6 /* ETHSYS */ -#define CLK_ETHSYS_HSDMA 0 -#define CLK_ETHSYS_ESW 1 -#define CLK_ETHSYS_GP2 2 -#define CLK_ETHSYS_GP1 3 -#define CLK_ETHSYS_PCM 4 -#define CLK_ETHSYS_GDMA 5 -#define CLK_ETHSYS_I2S 6 -#define CLK_ETHSYS_CRYPTO 7 -#define CLK_ETHSYS_NR 8 +#define CLK_ETHSYS_HSDMA 1 +#define CLK_ETHSYS_ESW 2 +#define CLK_ETHSYS_GP2 3 +#define CLK_ETHSYS_GP1 4 +#define CLK_ETHSYS_PCM 5 +#define CLK_ETHSYS_GDMA 6 +#define CLK_ETHSYS_I2S 7 +#define CLK_ETHSYS_CRYPTO 8 +#define CLK_ETHSYS_NR 9 /* G3DSYS */ -#define CLK_G3DSYS_CORE 0 -#define CLK_G3DSYS_NR 1 +#define CLK_G3DSYS_CORE 1 +#define CLK_G3DSYS_NR 2 + +/* BDP */ + +#define CLK_BDP_BRG_BA 1 +#define CLK_BDP_BRG_DRAM 2 +#define CLK_BDP_LARB_DRAM 3 +#define CLK_BDP_WR_VDI_PXL 4 +#define CLK_BDP_WR_VDI_DRAM 5 +#define CLK_BDP_WR_B 6 +#define CLK_BDP_DGI_IN 7 +#define CLK_BDP_DGI_OUT 8 +#define CLK_BDP_FMT_MAST_27 9 +#define CLK_BDP_FMT_B 10 +#define CLK_BDP_OSD_B 11 +#define CLK_BDP_OSD_DRAM 12 +#define CLK_BDP_OSD_AGENT 13 +#define CLK_BDP_OSD_PXL 14 +#define CLK_BDP_RLE_B 15 +#define CLK_BDP_RLE_AGENT 16 +#define CLK_BDP_RLE_DRAM 17 +#define CLK_BDP_F27M 18 +#define CLK_BDP_F27M_VDOUT 19 +#define CLK_BDP_F27_74_74 20 +#define CLK_BDP_F2FS 21 +#define CLK_BDP_F2FS74_148 22 +#define CLK_BDP_FB 23 +#define CLK_BDP_VDO_DRAM 24 +#define CLK_BDP_VDO_2FS 25 +#define CLK_BDP_VDO_B 26 +#define CLK_BDP_WR_DI_PXL 27 +#define CLK_BDP_WR_DI_DRAM 28 +#define CLK_BDP_WR_DI_B 29 +#define CLK_BDP_NR_PXL 30 +#define CLK_BDP_NR_DRAM 31 +#define CLK_BDP_NR_B 32 + +#define CLK_BDP_RX_F 33 +#define CLK_BDP_RX_X 34 +#define CLK_BDP_RXPDT 35 +#define CLK_BDP_RX_CSCL_N 36 +#define CLK_BDP_RX_CSCL 37 +#define CLK_BDP_RX_DDCSCL_N 38 +#define CLK_BDP_RX_DDCSCL 39 +#define CLK_BDP_RX_VCO 40 +#define CLK_BDP_RX_DP 41 +#define CLK_BDP_RX_P 42 +#define CLK_BDP_RX_M 43 +#define CLK_BDP_RX_PLL 44 +#define CLK_BDP_BRG_RT_B 45 +#define CLK_BDP_BRG_RT_DRAM 46 +#define CLK_BDP_LARBRT_DRAM 47 +#define CLK_BDP_TMDS_SYN 48 +#define CLK_BDP_HDMI_MON 49 +#define CLK_BDP_NR 50 #endif /* _DT_BINDINGS_CLK_MT2701_H */ diff --git a/include/dt-bindings/clock/mt7981-clk.h b/include/dt-bindings/clock/mt7981-clk.h index e24c759e499..52325916015 100644 --- a/include/dt-bindings/clock/mt7981-clk.h +++ b/include/dt-bindings/clock/mt7981-clk.h @@ -8,260 +8,219 @@ #ifndef _DT_BINDINGS_CLK_MT7981_H #define _DT_BINDINGS_CLK_MT7981_H -/* INFRACFG */ - -#define CK_INFRA_CK_F26M 0 -#define CK_INFRA_UART 1 -#define CK_INFRA_ISPI0 2 -#define CK_INFRA_I2C 3 -#define CK_INFRA_ISPI1 4 -#define CK_INFRA_PWM 5 -#define CK_INFRA_66M_MCK 6 -#define CK_INFRA_CK_F32K 7 -#define CK_INFRA_PCIE_CK 8 -#define CK_INFRA_PWM_BCK 9 -#define CK_INFRA_PWM_CK1 10 -#define CK_INFRA_PWM_CK2 11 -#define CK_INFRA_133M_HCK 12 -#define CK_INFRA_66M_PHCK 13 -#define CK_INFRA_FAUD_L_CK 14 -#define CK_INFRA_FAUD_AUD_CK 15 -#define CK_INFRA_FAUD_EG2_CK 16 -#define CK_INFRA_I2CS_CK 17 -#define CK_INFRA_MUX_UART0 18 -#define CK_INFRA_MUX_UART1 19 -#define CK_INFRA_MUX_UART2 20 -#define CK_INFRA_NFI_CK 21 -#define CK_INFRA_SPINFI_CK 22 -#define CK_INFRA_MUX_SPI0 23 -#define CK_INFRA_MUX_SPI1 24 -#define CK_INFRA_MUX_SPI2 25 -#define CK_INFRA_RTC_32K 26 -#define CK_INFRA_FMSDC_CK 27 -#define CK_INFRA_FMSDC_HCK_CK 28 -#define CK_INFRA_PERI_133M 29 -#define CK_INFRA_133M_PHCK 30 -#define CK_INFRA_USB_SYS_CK 31 -#define CK_INFRA_USB_CK 32 -#define CK_INFRA_USB_XHCI_CK 33 -#define CK_INFRA_PCIE_GFMUX_TL_O_PRE 34 -#define CK_INFRA_F26M_CK0 35 -#define CK_INFRA_133M_MCK 36 -#define CLK_INFRA_NR_CLK 37 - /* TOPCKGEN */ -#define CK_TOP_CB_CKSQ_40M 0 -#define CK_TOP_CB_M_416M 1 -#define CK_TOP_CB_M_D2 2 -#define CK_TOP_CB_M_D3 3 -#define CK_TOP_M_D3_D2 4 -#define CK_TOP_CB_M_D4 5 -#define CK_TOP_CB_M_D8 6 -#define CK_TOP_M_D8_D2 7 -#define CK_TOP_CB_MM_720M 8 -#define CK_TOP_CB_MM_D2 9 -#define CK_TOP_CB_MM_D3 10 -#define CK_TOP_CB_MM_D3_D5 11 -#define CK_TOP_CB_MM_D4 12 -#define CK_TOP_CB_MM_D6 13 -#define CK_TOP_MM_D6_D2 14 -#define CK_TOP_CB_MM_D8 15 -#define CK_TOP_CB_APLL2_196M 16 -#define CK_TOP_APLL2_D2 17 -#define CK_TOP_APLL2_D4 18 -#define CK_TOP_NET1_2500M 19 -#define CK_TOP_CB_NET1_D4 20 -#define CK_TOP_CB_NET1_D5 21 -#define CK_TOP_NET1_D5_D2 22 -#define CK_TOP_NET1_D5_D4 23 -#define CK_TOP_CB_NET1_D8 24 -#define CK_TOP_NET1_D8_D2 25 -#define CK_TOP_NET1_D8_D4 26 -#define CK_TOP_CB_NET2_800M 27 -#define CK_TOP_CB_NET2_D2 28 -#define CK_TOP_CB_NET2_D4 29 -#define CK_TOP_NET2_D4_D2 30 -#define CK_TOP_NET2_D4_D4 31 -#define CK_TOP_CB_NET2_D6 32 -#define CK_TOP_CB_WEDMCU_208M 33 -#define CK_TOP_CB_SGM_325M 34 -#define CK_TOP_CKSQ_40M_D2 35 -#define CK_TOP_CB_RTC_32K 36 -#define CK_TOP_CB_RTC_32P7K 37 -#define CK_TOP_USB_TX250M 38 -#define CK_TOP_FAUD 39 -#define CK_TOP_NFI1X 40 -#define CK_TOP_USB_EQ_RX250M 41 -#define CK_TOP_USB_CDR_CK 42 -#define CK_TOP_USB_LN0_CK 43 -#define CK_TOP_SPINFI_BCK 44 -#define CK_TOP_SPI 45 -#define CK_TOP_SPIM_MST 46 -#define CK_TOP_UART_BCK 47 -#define CK_TOP_PWM_BCK 48 -#define CK_TOP_I2C_BCK 49 -#define CK_TOP_PEXTP_TL 50 -#define CK_TOP_EMMC_208M 51 -#define CK_TOP_EMMC_400M 52 -#define CK_TOP_DRAMC_REF 53 -#define CK_TOP_DRAMC_MD32 54 -#define CK_TOP_SYSAXI 55 -#define CK_TOP_SYSAPB 56 -#define CK_TOP_ARM_DB_MAIN 57 -#define CK_TOP_AP2CNN_HOST 58 -#define CK_TOP_NETSYS 59 -#define CK_TOP_NETSYS_500M 60 -#define CK_TOP_NETSYS_WED_MCU 61 -#define CK_TOP_NETSYS_2X 62 -#define CK_TOP_SGM_325M 63 -#define CK_TOP_SGM_REG 64 -#define CK_TOP_F26M 65 -#define CK_TOP_EIP97B 66 -#define CK_TOP_USB3_PHY 67 -#define CK_TOP_AUD 68 -#define CK_TOP_A1SYS 69 -#define CK_TOP_AUD_L 70 -#define CK_TOP_A_TUNER 71 -#define CK_TOP_U2U3_REF 72 -#define CK_TOP_U2U3_SYS 73 -#define CK_TOP_U2U3_XHCI 74 -#define CK_TOP_USB_FRMCNT 75 -#define CK_TOP_NFI1X_SEL 76 -#define CK_TOP_SPINFI_SEL 77 -#define CK_TOP_SPI_SEL 78 -#define CK_TOP_SPIM_MST_SEL 79 -#define CK_TOP_UART_SEL 80 -#define CK_TOP_PWM_SEL 81 -#define CK_TOP_I2C_SEL 82 -#define CK_TOP_PEXTP_TL_SEL 83 -#define CK_TOP_EMMC_208M_SEL 84 -#define CK_TOP_EMMC_400M_SEL 85 -#define CK_TOP_F26M_SEL 86 -#define CK_TOP_DRAMC_SEL 87 -#define CK_TOP_DRAMC_MD32_SEL 88 -#define CK_TOP_SYSAXI_SEL 89 -#define CK_TOP_SYSAPB_SEL 90 -#define CK_TOP_ARM_DB_MAIN_SEL 91 -#define CK_TOP_AP2CNN_HOST_SEL 92 -#define CK_TOP_NETSYS_SEL 93 -#define CK_TOP_NETSYS_500M_SEL 94 -#define CK_TOP_NETSYS_MCU_SEL 95 -#define CK_TOP_NETSYS_2X_SEL 96 -#define CK_TOP_SGM_325M_SEL 97 -#define CK_TOP_SGM_REG_SEL 98 -#define CK_TOP_EIP97B_SEL 99 -#define CK_TOP_USB3_PHY_SEL 100 -#define CK_TOP_AUD_SEL 101 -#define CK_TOP_A1SYS_SEL 102 -#define CK_TOP_AUD_L_SEL 103 -#define CK_TOP_A_TUNER_SEL 104 -#define CK_TOP_U2U3_SEL 105 -#define CK_TOP_U2U3_SYS_SEL 106 -#define CK_TOP_U2U3_XHCI_SEL 107 -#define CK_TOP_USB_FRMCNT_SEL 108 -#define CLK_TOP_NR_CLK 109 +#define CLK_TOP_CB_CKSQ_40M 0 +#define CLK_TOP_CB_M_416M 1 +#define CLK_TOP_CB_M_D2 2 +#define CLK_TOP_CB_M_D3 3 +#define CLK_TOP_M_D3_D2 4 +#define CLK_TOP_CB_M_D4 5 +#define CLK_TOP_CB_M_D8 6 +#define CLK_TOP_M_D8_D2 7 +#define CLK_TOP_CB_MM_720M 8 +#define CLK_TOP_CB_MM_D2 9 +#define CLK_TOP_CB_MM_D3 10 +#define CLK_TOP_CB_MM_D3_D5 11 +#define CLK_TOP_CB_MM_D4 12 +#define CLK_TOP_CB_MM_D6 13 +#define CLK_TOP_MM_D6_D2 14 +#define CLK_TOP_CB_MM_D8 15 +#define CLK_TOP_CB_APLL2_196M 16 +#define CLK_TOP_APLL2_D2 17 +#define CLK_TOP_APLL2_D4 18 +#define CLK_TOP_NET1_2500M 19 +#define CLK_TOP_CB_NET1_D4 20 +#define CLK_TOP_CB_NET1_D5 21 +#define CLK_TOP_NET1_D5_D2 22 +#define CLK_TOP_NET1_D5_D4 23 +#define CLK_TOP_CB_NET1_D8 24 +#define CLK_TOP_NET1_D8_D2 25 +#define CLK_TOP_NET1_D8_D4 26 +#define CLK_TOP_CB_NET2_800M 27 +#define CLK_TOP_CB_NET2_D2 28 +#define CLK_TOP_CB_NET2_D4 29 +#define CLK_TOP_NET2_D4_D2 30 +#define CLK_TOP_NET2_D4_D4 31 +#define CLK_TOP_CB_NET2_D6 32 +#define CLK_TOP_CB_WEDMCU_208M 33 +#define CLK_TOP_CB_SGM_325M 34 +#define CLK_TOP_CKSQ_40M_D2 35 +#define CLK_TOP_CB_RTC_32K 36 +#define CLK_TOP_CB_RTC_32P7K 37 +#define CLK_TOP_USB_TX250M 38 +#define CLK_TOP_FAUD 39 +#define CLK_TOP_NFI1X 40 +#define CLK_TOP_USB_EQ_RX250M 41 +#define CLK_TOP_USB_CDR_CK 42 +#define CLK_TOP_USB_LN0_CK 43 +#define CLK_TOP_SPINFI_BCK 44 +#define CLK_TOP_SPI 45 +#define CLK_TOP_SPIM_MST 46 +#define CLK_TOP_UART_BCK 47 +#define CLK_TOP_PWM_BCK 48 +#define CLK_TOP_I2C_BCK 49 +#define CLK_TOP_PEXTP_TL 50 +#define CLK_TOP_EMMC_208M 51 +#define CLK_TOP_EMMC_400M 52 +#define CLK_TOP_DRAMC_REF 53 +#define CLK_TOP_DRAMC_MD32 54 +#define CLK_TOP_SYSAXI 55 +#define CLK_TOP_SYSAPB 56 +#define CLK_TOP_ARM_DB_MAIN 57 +#define CLK_TOP_AP2CNN_HOST 58 +#define CLK_TOP_NETSYS 59 +#define CLK_TOP_NETSYS_500M 60 +#define CLK_TOP_NETSYS_WED_MCU 61 +#define CLK_TOP_NETSYS_2X 62 +#define CLK_TOP_SGM_325M 63 +#define CLK_TOP_SGM_REG 64 +#define CLK_TOP_F26M 65 +#define CLK_TOP_EIP97B 66 +#define CLK_TOP_USB3_PHY 67 +#define CLK_TOP_AUD 68 +#define CLK_TOP_A1SYS 69 +#define CLK_TOP_AUD_L 70 +#define CLK_TOP_A_TUNER 71 +#define CLK_TOP_U2U3_REF 72 +#define CLK_TOP_U2U3_SYS 73 +#define CLK_TOP_U2U3_XHCI 74 +#define CLK_TOP_USB_FRMCNT 75 +#define CLK_TOP_NFI1X_SEL 76 +#define CLK_TOP_SPINFI_SEL 77 +#define CLK_TOP_SPI_SEL 78 +#define CLK_TOP_SPIM_MST_SEL 79 +#define CLK_TOP_UART_SEL 80 +#define CLK_TOP_PWM_SEL 81 +#define CLK_TOP_I2C_SEL 82 +#define CLK_TOP_PEXTP_TL_SEL 83 +#define CLK_TOP_EMMC_208M_SEL 84 +#define CLK_TOP_EMMC_400M_SEL 85 +#define CLK_TOP_F26M_SEL 86 +#define CLK_TOP_DRAMC_SEL 87 +#define CLK_TOP_DRAMC_MD32_SEL 88 +#define CLK_TOP_SYSAXI_SEL 89 +#define CLK_TOP_SYSAPB_SEL 90 +#define CLK_TOP_ARM_DB_MAIN_SEL 91 +#define CLK_TOP_AP2CNN_HOST_SEL 92 +#define CLK_TOP_NETSYS_SEL 93 +#define CLK_TOP_NETSYS_500M_SEL 94 +#define CLK_TOP_NETSYS_MCU_SEL 95 +#define CLK_TOP_NETSYS_2X_SEL 96 +#define CLK_TOP_SGM_325M_SEL 97 +#define CLK_TOP_SGM_REG_SEL 98 +#define CLK_TOP_EIP97B_SEL 99 +#define CLK_TOP_USB3_PHY_SEL 100 +#define CLK_TOP_AUD_SEL 101 +#define CLK_TOP_A1SYS_SEL 102 +#define CLK_TOP_AUD_L_SEL 103 +#define CLK_TOP_A_TUNER_SEL 104 +#define CLK_TOP_U2U3_SEL 105 +#define CLK_TOP_U2U3_SYS_SEL 106 +#define CLK_TOP_U2U3_XHCI_SEL 107 +#define CLK_TOP_USB_FRMCNT_SEL 108 +#define CLK_TOP_AUD_I2S_M 109 +#define CLK_TOP_NR_CLK 110 -/* - * INFRACFG_AO - * clock muxes need to be append to infracfg domain, and clock gates - * need to be keep in infracgh_ao domain - */ -#define INFRACFG_AO_OFFSET 10 +/* INFRACFG */ -#define CK_INFRA_UART0_SEL (0 + CLK_INFRA_NR_CLK) -#define CK_INFRA_UART1_SEL (1 + CLK_INFRA_NR_CLK) -#define CK_INFRA_UART2_SEL (2 + CLK_INFRA_NR_CLK) -#define CK_INFRA_SPI0_SEL (3 + CLK_INFRA_NR_CLK) -#define CK_INFRA_SPI1_SEL (4 + CLK_INFRA_NR_CLK) -#define CK_INFRA_SPI2_SEL (5 + CLK_INFRA_NR_CLK) -#define CK_INFRA_PWM1_SEL (6 + CLK_INFRA_NR_CLK) -#define CK_INFRA_PWM2_SEL (7 + CLK_INFRA_NR_CLK) -#define CK_INFRA_PWM_BSEL (8 + CLK_INFRA_NR_CLK) -#define CK_INFRA_PCIE_SEL (9 + CLK_INFRA_NR_CLK) -#define CK_INFRA_GPT_STA (10 - INFRACFG_AO_OFFSET) -#define CK_INFRA_PWM_HCK (11 - INFRACFG_AO_OFFSET) -#define CK_INFRA_PWM_STA (12 - INFRACFG_AO_OFFSET) -#define CK_INFRA_PWM1_CK (13 - INFRACFG_AO_OFFSET) -#define CK_INFRA_PWM2_CK (14 - INFRACFG_AO_OFFSET) -#define CK_INFRA_CQ_DMA_CK (15 - INFRACFG_AO_OFFSET) -#define CK_INFRA_AUD_BUS_CK (16 - INFRACFG_AO_OFFSET) -#define CK_INFRA_AUD_26M_CK (17 - INFRACFG_AO_OFFSET) -#define CK_INFRA_AUD_L_CK (18 - INFRACFG_AO_OFFSET) -#define CK_INFRA_AUD_AUD_CK (19 - INFRACFG_AO_OFFSET) -#define CK_INFRA_AUD_EG2_CK (20 - INFRACFG_AO_OFFSET) -#define CK_INFRA_DRAMC_26M_CK (21 - INFRACFG_AO_OFFSET) -#define CK_INFRA_DBG_CK (22 - INFRACFG_AO_OFFSET) -#define CK_INFRA_AP_DMA_CK (23 - INFRACFG_AO_OFFSET) -#define CK_INFRA_SEJ_CK (24 - INFRACFG_AO_OFFSET) -#define CK_INFRA_SEJ_13M_CK (25 - INFRACFG_AO_OFFSET) -#define CK_INFRA_THERM_CK (26 - INFRACFG_AO_OFFSET) -#define CK_INFRA_I2CO_CK (27 - INFRACFG_AO_OFFSET) -#define CK_INFRA_UART0_CK (28 - INFRACFG_AO_OFFSET) -#define CK_INFRA_UART1_CK (29 - INFRACFG_AO_OFFSET) -#define CK_INFRA_UART2_CK (30 - INFRACFG_AO_OFFSET) -#define CK_INFRA_SPI2_CK (31 - INFRACFG_AO_OFFSET) -#define CK_INFRA_SPI2_HCK_CK (32 - INFRACFG_AO_OFFSET) -#define CK_INFRA_NFI1_CK (33 - INFRACFG_AO_OFFSET) -#define CK_INFRA_SPINFI1_CK (34 - INFRACFG_AO_OFFSET) -#define CK_INFRA_NFI_HCK_CK (35 - INFRACFG_AO_OFFSET) -#define CK_INFRA_SPI0_CK (36 - INFRACFG_AO_OFFSET) -#define CK_INFRA_SPI1_CK (37 - INFRACFG_AO_OFFSET) -#define CK_INFRA_SPI0_HCK_CK (38 - INFRACFG_AO_OFFSET) -#define CK_INFRA_SPI1_HCK_CK (39 - INFRACFG_AO_OFFSET) -#define CK_INFRA_FRTC_CK (40 - INFRACFG_AO_OFFSET) -#define CK_INFRA_MSDC_CK (41 - INFRACFG_AO_OFFSET) -#define CK_INFRA_MSDC_HCK_CK (42 - INFRACFG_AO_OFFSET) -#define CK_INFRA_MSDC_133M_CK (43 - INFRACFG_AO_OFFSET) -#define CK_INFRA_MSDC_66M_CK (44 - INFRACFG_AO_OFFSET) -#define CK_INFRA_ADC_26M_CK (45 - INFRACFG_AO_OFFSET) -#define CK_INFRA_ADC_FRC_CK (46 - INFRACFG_AO_OFFSET) -#define CK_INFRA_FBIST2FPC_CK (47 - INFRACFG_AO_OFFSET) -#define CK_INFRA_I2C_MCK_CK (48 - INFRACFG_AO_OFFSET) -#define CK_INFRA_I2C_PCK_CK (49 - INFRACFG_AO_OFFSET) -#define CK_INFRA_IUSB_133_CK (50 - INFRACFG_AO_OFFSET) -#define CK_INFRA_IUSB_66M_CK (51 - INFRACFG_AO_OFFSET) -#define CK_INFRA_IUSB_SYS_CK (52 - INFRACFG_AO_OFFSET) -#define CK_INFRA_IUSB_CK (53 - INFRACFG_AO_OFFSET) -#define CK_INFRA_IPCIE_CK (54 - INFRACFG_AO_OFFSET) -#define CK_INFRA_IPCIER_CK (55 - INFRACFG_AO_OFFSET) -#define CK_INFRA_IPCIEB_CK (56 - INFRACFG_AO_OFFSET) -#define CLK_INFRA_AO_NR_CLK (57 - INFRACFG_AO_OFFSET) +#define CLK_INFRA_66M_MCK 0 +#define CLK_INFRA_UART0_SEL 1 +#define CLK_INFRA_UART1_SEL 2 +#define CLK_INFRA_UART2_SEL 3 +#define CLK_INFRA_SPI0_SEL 4 +#define CLK_INFRA_SPI1_SEL 5 +#define CLK_INFRA_SPI2_SEL 6 +#define CLK_INFRA_PWM1_SEL 7 +#define CLK_INFRA_PWM2_SEL 8 +#define CLK_INFRA_PWM3_SEL 9 +#define CLK_INFRA_PWM_BSEL 10 +#define CLK_INFRA_PCIE_SEL 11 +#define CLK_INFRA_GPT_STA 12 +#define CLK_INFRA_PWM_HCK 13 +#define CLK_INFRA_PWM_STA 14 +#define CLK_INFRA_PWM1_CK 15 +#define CLK_INFRA_PWM2_CK 16 +#define CLK_INFRA_PWM3_CK 17 +#define CLK_INFRA_CQ_DMA_CK 18 +#define CLK_INFRA_AUD_BUS_CK 19 +#define CLK_INFRA_AUD_26M_CK 20 +#define CLK_INFRA_AUD_L_CK 21 +#define CLK_INFRA_AUD_AUD_CK 22 +#define CLK_INFRA_AUD_EG2_CK 23 +#define CLK_INFRA_DRAMC_26M_CK 24 +#define CLK_INFRA_DBG_CK 25 +#define CLK_INFRA_AP_DMA_CK 26 +#define CLK_INFRA_SEJ_CK 27 +#define CLK_INFRA_SEJ_13M_CK 28 +#define CLK_INFRA_THERM_CK 29 +#define CLK_INFRA_I2C0_CK 30 +#define CLK_INFRA_UART0_CK 31 +#define CLK_INFRA_UART1_CK 32 +#define CLK_INFRA_UART2_CK 33 +#define CLK_INFRA_SPI2_CK 34 +#define CLK_INFRA_SPI2_HCK_CK 35 +#define CLK_INFRA_NFI1_CK 36 +#define CLK_INFRA_SPINFI1_CK 37 +#define CLK_INFRA_NFI_HCK_CK 38 +#define CLK_INFRA_SPI0_CK 39 +#define CLK_INFRA_SPI1_CK 40 +#define CLK_INFRA_SPI0_HCK_CK 41 +#define CLK_INFRA_SPI1_HCK_CK 42 +#define CLK_INFRA_FRTC_CK 43 +#define CLK_INFRA_MSDC_CK 44 +#define CLK_INFRA_MSDC_HCK_CK 45 +#define CLK_INFRA_MSDC_133M_CK 46 +#define CLK_INFRA_MSDC_66M_CK 47 +#define CLK_INFRA_ADC_26M_CK 48 +#define CLK_INFRA_ADC_FRC_CK 49 +#define CLK_INFRA_FBIST2FPC_CK 50 +#define CLK_INFRA_I2C_MCK_CK 51 +#define CLK_INFRA_I2C_PCK_CK 52 +#define CLK_INFRA_IUSB_133_CK 53 +#define CLK_INFRA_IUSB_66M_CK 54 +#define CLK_INFRA_IUSB_SYS_CK 55 +#define CLK_INFRA_IUSB_CK 56 +#define CLK_INFRA_IPCIE_CK 57 +#define CLK_INFRA_IPCIE_PIPE_CK 58 +#define CLK_INFRA_IPCIER_CK 59 +#define CLK_INFRA_IPCIEB_CK 60 +#define CLK_INFRA_NR_CLK 61 /* APMIXEDSYS */ -#define CK_APMIXED_ARMPLL 0 -#define CK_APMIXED_NET2PLL 1 -#define CK_APMIXED_MMPLL 2 -#define CK_APMIXED_SGMPLL 3 -#define CK_APMIXED_WEDMCUPLL 4 -#define CK_APMIXED_NET1PLL 5 -#define CK_APMIXED_MPLL 6 -#define CK_APMIXED_APLL2 7 +#define CLK_APMIXED_ARMPLL 0 +#define CLK_APMIXED_NET2PLL 1 +#define CLK_APMIXED_MMPLL 2 +#define CLK_APMIXED_SGMPLL 3 +#define CLK_APMIXED_WEDMCUPLL 4 +#define CLK_APMIXED_NET1PLL 5 +#define CLK_APMIXED_MPLL 6 +#define CLK_APMIXED_APLL2 7 #define CLK_APMIXED_NR_CLK 8 /* SGMIISYS_0 */ -#define CK_SGM0_TX_EN 0 -#define CK_SGM0_RX_EN 1 -#define CK_SGM0_CK0_EN 2 -#define CK_SGM0_CDR_CK0_EN 3 +#define CLK_SGM0_TX_EN 0 +#define CLK_SGM0_RX_EN 1 +#define CLK_SGM0_CK0_EN 2 +#define CLK_SGM0_CDR_CK0_EN 3 #define CLK_SGMII0_NR_CLK 4 /* SGMIISYS_1 */ -#define CK_SGM1_TX_EN 0 -#define CK_SGM1_RX_EN 1 -#define CK_SGM1_CK1_EN 2 -#define CK_SGM1_CDR_CK1_EN 3 +#define CLK_SGM1_TX_EN 0 +#define CLK_SGM1_RX_EN 1 +#define CLK_SGM1_CK1_EN 2 +#define CLK_SGM1_CDR_CK1_EN 3 #define CLK_SGMII1_NR_CLK 4 /* ETHSYS */ -#define CK_ETH_FE_EN 0 -#define CK_ETH_GP2_EN 1 -#define CK_ETH_GP1_EN 2 -#define CK_ETH_WOCPU0_EN 3 +#define CLK_ETH_FE_EN 0 +#define CLK_ETH_GP2_EN 1 +#define CLK_ETH_GP1_EN 2 +#define CLK_ETH_WOCPU0_EN 3 #define CLK_ETH_NR_CLK 4 #endif /* _DT_BINDINGS_CLK_MT7981_H */ diff --git a/include/dt-bindings/clock/mt7986-clk.h b/include/dt-bindings/clock/mt7986-clk.h index 820f8631831..5da260386fd 100644 --- a/include/dt-bindings/clock/mt7986-clk.h +++ b/include/dt-bindings/clock/mt7986-clk.h @@ -8,240 +8,169 @@ #ifndef _DT_BINDINGS_CLK_MT7986_H #define _DT_BINDINGS_CLK_MT7986_H -/* INFRACFG */ - -#define CK_INFRA_CK_F26M 0 -#define CK_INFRA_UART 1 -#define CK_INFRA_ISPI0 2 -#define CK_INFRA_I2C 3 -#define CK_INFRA_ISPI1 4 -#define CK_INFRA_PWM 5 -#define CK_INFRA_66M_MCK 6 -#define CK_INFRA_CK_F32K 7 -#define CK_INFRA_PCIE_CK 8 -#define CK_INFRA_PWM_BCK 9 -#define CK_INFRA_PWM_CK1 10 -#define CK_INFRA_PWM_CK2 11 -#define CK_INFRA_133M_HCK 12 -#define CK_INFRA_EIP_CK 13 -#define CK_INFRA_66M_PHCK 14 -#define CK_INFRA_FAUD_L_CK 15 -#define CK_INFRA_FAUD_AUD_CK 17 -#define CK_INFRA_FAUD_EG2_CK 17 -#define CK_INFRA_I2CS_CK 18 -#define CK_INFRA_MUX_UART0 19 -#define CK_INFRA_MUX_UART1 20 -#define CK_INFRA_MUX_UART2 21 -#define CK_INFRA_NFI_CK 22 -#define CK_INFRA_SPINFI_CK 23 -#define CK_INFRA_MUX_SPI0 24 -#define CK_INFRA_MUX_SPI1 25 -#define CK_INFRA_RTC_32K 26 -#define CK_INFRA_FMSDC_CK 27 -#define CK_INFRA_FMSDC_HCK_CK 28 -#define CK_INFRA_PERI_133M 29 -#define CK_INFRA_133M_PHCK 30 -#define CK_INFRA_USB_SYS_CK 31 -#define CK_INFRA_USB_CK 32 -#define CK_INFRA_USB_XHCI_CK 33 -#define CK_INFRA_PCIE_GFMUX_TL_O_PRE 34 -#define CK_INFRA_F26M_CK0 35 -#define CK_INFRA_HD_133M 36 -#define CLK_INFRA_NR_CLK 37 - /* TOPCKGEN */ -#define CK_TOP_CB_CKSQ_40M 0 -#define CK_TOP_CB_M_416M 1 -#define CK_TOP_CB_M_D2 2 -#define CK_TOP_CB_M_D4 3 -#define CK_TOP_CB_M_D8 4 -#define CK_TOP_M_D8_D2 5 -#define CK_TOP_M_D3_D2 6 -#define CK_TOP_CB_MM_D2 7 -#define CK_TOP_CB_MM_D4 8 -#define CK_TOP_CB_MM_D8 9 -#define CK_TOP_MM_D8_D2 10 -#define CK_TOP_MM_D3_D8 11 -#define CK_TOP_CB_U2_PHYD_CK 12 -#define CK_TOP_CB_APLL2_196M 13 -#define CK_TOP_APLL2_D4 14 -#define CK_TOP_CB_NET1_D4 15 -#define CK_TOP_CB_NET1_D5 16 -#define CK_TOP_NET1_D5_D2 17 -#define CK_TOP_NET1_D5_D4 18 -#define CK_TOP_NET1_D8_D2 19 -#define CK_TOP_NET1_D8_D4 20 -#define CK_TOP_CB_NET2_800M 21 -#define CK_TOP_CB_NET2_D4 22 -#define CK_TOP_NET2_D4_D2 23 -#define CK_TOP_NET2_D3_D2 24 -#define CK_TOP_CB_WEDMCU_760M 25 -#define CK_TOP_WEDMCU_D5_D2 26 -#define CK_TOP_CB_SGM_325M 27 -#define CK_TOP_CB_CKSQ_40M_D2 28 -#define CK_TOP_CB_RTC_32K 29 -#define CK_TOP_CB_RTC_32P7K 30 -#define CK_TOP_NFI1X 31 -#define CK_TOP_USB_EQ_RX250M 32 -#define CK_TOP_USB_TX250M 33 -#define CK_TOP_USB_LN0_CK 34 -#define CK_TOP_USB_CDR_CK 35 -#define CK_TOP_SPINFI_BCK 36 -#define CK_TOP_I2C_BCK 37 -#define CK_TOP_PEXTP_TL 38 -#define CK_TOP_EMMC_250M 39 -#define CK_TOP_EMMC_416M 40 -#define CK_TOP_F_26M_ADC_CK 41 -#define CK_TOP_SYSAXI 42 -#define CK_TOP_NETSYS_WED_MCU 43 -#define CK_TOP_NETSYS_2X 44 -#define CK_TOP_SGM_325M 45 -#define CK_TOP_A1SYS 46 -#define CK_TOP_EIP_B 47 -#define CK_TOP_F26M 48 -#define CK_TOP_AUD_L 49 -#define CK_TOP_A_TUNER 50 -#define CK_TOP_U2U3_REF 51 -#define CK_TOP_U2U3_SYS 52 -#define CK_TOP_U2U3_XHCI 53 -#define CK_TOP_AP2CNN_HOST 54 -#define CK_TOP_NFI1X_SEL 55 -#define CK_TOP_SPINFI_SEL 56 -#define CK_TOP_SPI_SEL 57 -#define CK_TOP_SPIM_MST_SEL 58 -#define CK_TOP_UART_SEL 59 -#define CK_TOP_PWM_SEL 60 -#define CK_TOP_I2C_SEL 61 -#define CK_TOP_PEXTP_TL_SEL 62 -#define CK_TOP_EMMC_250M_SEL 63 -#define CK_TOP_EMMC_416M_SEL 64 -#define CK_TOP_F_26M_ADC_SEL 65 -#define CK_TOP_DRAMC_SEL 66 -#define CK_TOP_DRAMC_MD32_SEL 67 -#define CK_TOP_SYSAXI_SEL 68 -#define CK_TOP_SYSAPB_SEL 69 -#define CK_TOP_ARM_DB_MAIN_SEL 70 -#define CK_TOP_ARM_DB_JTSEL 71 -#define CK_TOP_NETSYS_SEL 72 -#define CK_TOP_NETSYS_500M_SEL 73 -#define CK_TOP_NETSYS_MCU_SEL 74 -#define CK_TOP_NETSYS_2X_SEL 75 -#define CK_TOP_SGM_325M_SEL 76 -#define CK_TOP_SGM_REG_SEL 77 -#define CK_TOP_A1SYS_SEL 78 -#define CK_TOP_CONN_MCUSYS_SEL 79 -#define CK_TOP_EIP_B_SEL 80 -#define CK_TOP_PCIE_PHY_SEL 81 -#define CK_TOP_USB3_PHY_SEL 82 -#define CK_TOP_F26M_SEL 83 -#define CK_TOP_AUD_L_SEL 84 -#define CK_TOP_A_TUNER_SEL 85 -#define CK_TOP_U2U3_SEL 86 -#define CK_TOP_U2U3_SYS_SEL 87 -#define CK_TOP_U2U3_XHCI_SEL 88 -#define CK_TOP_DA_U2_REFSEL 89 -#define CK_TOP_DA_U2_CK_1P_SEL 90 -#define CK_TOP_AP2CNN_HOST_SEL 91 -#define CLK_TOP_NR_CLK 92 +#define CLK_TOP_XTAL 0 +#define CLK_TOP_XTAL_D2 1 +#define CLK_TOP_RTC_32K 2 +#define CLK_TOP_RTC_32P7K 3 +/* #define CLK_TOP_A_TUNER 4 */ +#define CLK_TOP_MPLL_D2 4 +#define CLK_TOP_MPLL_D4 5 +#define CLK_TOP_MPLL_D8 6 +#define CLK_TOP_MPLL_D8_D2 7 +#define CLK_TOP_MPLL_D3_D2 8 +#define CLK_TOP_MMPLL_D2 9 +#define CLK_TOP_MMPLL_D4 10 +#define CLK_TOP_MMPLL_D8 11 +#define CLK_TOP_MMPLL_D8_D2 12 +#define CLK_TOP_MMPLL_D3_D8 13 +#define CLK_TOP_MMPLL_U2PHYD 14 +#define CLK_TOP_APLL2_D4 15 +#define CLK_TOP_NET1PLL_D4 16 +#define CLK_TOP_NET1PLL_D5 17 +#define CLK_TOP_NET1PLL_D5_D2 18 +#define CLK_TOP_NET1PLL_D5_D4 19 +#define CLK_TOP_NET1PLL_D8_D2 20 +#define CLK_TOP_NET1PLL_D8_D4 21 +#define CLK_TOP_NET2PLL_D4 22 +#define CLK_TOP_NET2PLL_D4_D2 23 +#define CLK_TOP_NET2PLL_D3_D2 24 +#define CLK_TOP_WEDMCUPLL_D5_D2 25 +#define CLK_TOP_NFI1X_SEL 26 +#define CLK_TOP_SPINFI_SEL 27 +#define CLK_TOP_SPI_SEL 28 +#define CLK_TOP_SPIM_MST_SEL 29 +#define CLK_TOP_UART_SEL 30 +#define CLK_TOP_PWM_SEL 31 +#define CLK_TOP_I2C_SEL 32 +#define CLK_TOP_PEXTP_TL_SEL 33 +#define CLK_TOP_EMMC_250M_SEL 34 +#define CLK_TOP_EMMC_416M_SEL 35 +#define CLK_TOP_F_26M_ADC_SEL 36 +#define CLK_TOP_DRAMC_SEL 37 +#define CLK_TOP_DRAMC_MD32_SEL 38 +#define CLK_TOP_SYSAXI_SEL 39 +#define CLK_TOP_SYSAPB_SEL 40 +#define CLK_TOP_ARM_DB_MAIN_SEL 41 +#define CLK_TOP_ARM_DB_JTSEL 42 +#define CLK_TOP_NETSYS_SEL 43 +#define CLK_TOP_NETSYS_500M_SEL 44 +#define CLK_TOP_NETSYS_MCU_SEL 45 +#define CLK_TOP_NETSYS_2X_SEL 46 +#define CLK_TOP_SGM_325M_SEL 47 +#define CLK_TOP_SGM_REG_SEL 48 +#define CLK_TOP_A1SYS_SEL 49 +#define CLK_TOP_CONN_MCUSYS_SEL 50 +#define CLK_TOP_EIP_B_SEL 51 +#define CLK_TOP_PCIE_PHY_SEL 52 +#define CLK_TOP_USB3_PHY_SEL 53 +#define CLK_TOP_F26M_SEL 54 +#define CLK_TOP_AUD_L_SEL 55 +#define CLK_TOP_A_TUNER_SEL 56 +#define CLK_TOP_U2U3_SEL 57 +#define CLK_TOP_U2U3_SYS_SEL 58 +#define CLK_TOP_U2U3_XHCI_SEL 59 +#define CLK_TOP_DA_U2_REFSEL 60 +#define CLK_TOP_DA_U2_CK_1P_SEL 61 +#define CLK_TOP_AP2CNN_HOST_SEL 62 +#define CLK_TOP_NR_CLK 63 -/* - * INFRACFG_AO - * clock muxes need to be append to infracfg domain, and clock gates - * need to be keep in infracgh_ao domain - */ +/* INFRACFG */ -#define CK_INFRA_UART0_SEL (0 + CLK_INFRA_NR_CLK) -#define CK_INFRA_UART1_SEL (1 + CLK_INFRA_NR_CLK) -#define CK_INFRA_UART2_SEL (2 + CLK_INFRA_NR_CLK) -#define CK_INFRA_SPI0_SEL (3 + CLK_INFRA_NR_CLK) -#define CK_INFRA_SPI1_SEL (4 + CLK_INFRA_NR_CLK) -#define CK_INFRA_PWM1_SEL (5 + CLK_INFRA_NR_CLK) -#define CK_INFRA_PWM2_SEL (6 + CLK_INFRA_NR_CLK) -#define CK_INFRA_PWM_BSEL (7 + CLK_INFRA_NR_CLK) -#define CK_INFRA_PCIE_SEL (8 + CLK_INFRA_NR_CLK) -#define CK_INFRA_GPT_STA 0 -#define CK_INFRA_PWM_HCK 1 -#define CK_INFRA_PWM_STA 2 -#define CK_INFRA_PWM1_CK 3 -#define CK_INFRA_PWM2_CK 4 -#define CK_INFRA_CQ_DMA_CK 5 -#define CK_INFRA_EIP97_CK 6 -#define CK_INFRA_AUD_BUS_CK 7 -#define CK_INFRA_AUD_26M_CK 8 -#define CK_INFRA_AUD_L_CK 9 -#define CK_INFRA_AUD_AUD_CK 10 -#define CK_INFRA_AUD_EG2_CK 11 -#define CK_INFRA_DRAMC_26M_CK 12 -#define CK_INFRA_DBG_CK 13 -#define CK_INFRA_AP_DMA_CK 14 -#define CK_INFRA_SEJ_CK 15 -#define CK_INFRA_SEJ_13M_CK 16 -#define CK_INFRA_THERM_CK 17 -#define CK_INFRA_I2CO_CK 18 -#define CK_INFRA_TRNG_CK 19 -#define CK_INFRA_UART0_CK 20 -#define CK_INFRA_UART1_CK 21 -#define CK_INFRA_UART2_CK 22 -#define CK_INFRA_NFI1_CK 23 -#define CK_INFRA_SPINFI1_CK 24 -#define CK_INFRA_NFI_HCK_CK 25 -#define CK_INFRA_SPI0_CK 26 -#define CK_INFRA_SPI1_CK 27 -#define CK_INFRA_SPI0_HCK_CK 28 -#define CK_INFRA_SPI1_HCK_CK 29 -#define CK_INFRA_FRTC_CK 30 -#define CK_INFRA_MSDC_CK 31 -#define CK_INFRA_MSDC_HCK_CK 32 -#define CK_INFRA_MSDC_133M_CK 33 -#define CK_INFRA_MSDC_66M_CK 34 -#define CK_INFRA_ADC_26M_CK 35 -#define CK_INFRA_ADC_FRC_CK 36 -#define CK_INFRA_FBIST2FPC_CK 37 -#define CK_INFRA_IUSB_133_CK 38 -#define CK_INFRA_IUSB_66M_CK 39 -#define CK_INFRA_IUSB_SYS_CK 40 -#define CK_INFRA_IUSB_CK 41 -#define CK_INFRA_IPCIE_CK 42 -#define CK_INFRA_IPCIER_CK 43 -#define CK_INFRA_IPCIEB_CK 44 -#define CLK_INFRA_AO_NR_CLK 45 +#define CLK_INFRA_SYSAXI_D2 0 +#define CLK_INFRA_UART0_SEL 1 +#define CLK_INFRA_UART1_SEL 2 +#define CLK_INFRA_UART2_SEL 3 +#define CLK_INFRA_SPI0_SEL 4 +#define CLK_INFRA_SPI1_SEL 5 +#define CLK_INFRA_PWM1_SEL 6 +#define CLK_INFRA_PWM2_SEL 7 +#define CLK_INFRA_PWM_BSEL 8 +#define CLK_INFRA_PCIE_SEL 9 +#define CLK_INFRA_GPT_STA 10 +#define CLK_INFRA_PWM_HCK 11 +#define CLK_INFRA_PWM_STA 12 +#define CLK_INFRA_PWM1_CK 13 +#define CLK_INFRA_PWM2_CK 14 +#define CLK_INFRA_CQ_DMA_CK 15 +#define CLK_INFRA_EIP97_CK 16 +#define CLK_INFRA_AUD_BUS_CK 17 +#define CLK_INFRA_AUD_26M_CK 18 +#define CLK_INFRA_AUD_L_CK 19 +#define CLK_INFRA_AUD_AUD_CK 20 +#define CLK_INFRA_AUD_EG2_CK 21 +#define CLK_INFRA_DRAMC_26M_CK 22 +#define CLK_INFRA_DBG_CK 23 +#define CLK_INFRA_AP_DMA_CK 24 +#define CLK_INFRA_SEJ_CK 25 +#define CLK_INFRA_SEJ_13M_CK 26 +#define CLK_INFRA_THERM_CK 27 +#define CLK_INFRA_I2C0_CK 28 +#define CLK_INFRA_UART0_CK 29 +#define CLK_INFRA_UART1_CK 30 +#define CLK_INFRA_UART2_CK 31 +#define CLK_INFRA_NFI1_CK 32 +#define CLK_INFRA_SPINFI1_CK 33 +#define CLK_INFRA_NFI_HCK_CK 34 +#define CLK_INFRA_SPI0_CK 35 +#define CLK_INFRA_SPI1_CK 36 +#define CLK_INFRA_SPI0_HCK_CK 37 +#define CLK_INFRA_SPI1_HCK_CK 38 +#define CLK_INFRA_FRTC_CK 39 +#define CLK_INFRA_MSDC_CK 40 +#define CLK_INFRA_MSDC_HCK_CK 41 +#define CLK_INFRA_MSDC_133M_CK 42 +#define CLK_INFRA_MSDC_66M_CK 43 +#define CLK_INFRA_ADC_26M_CK 44 +#define CLK_INFRA_ADC_FRC_CK 45 +#define CLK_INFRA_FBIST2FPC_CK 46 +#define CLK_INFRA_IUSB_133_CK 47 +#define CLK_INFRA_IUSB_66M_CK 48 +#define CLK_INFRA_IUSB_SYS_CK 49 +#define CLK_INFRA_IUSB_CK 50 +#define CLK_INFRA_IPCIE_CK 51 +#define CLK_INFRA_IPCIE_PIPE_CK 52 +#define CLK_INFRA_IPCIER_CK 53 +#define CLK_INFRA_IPCIEB_CK 54 +#define CLK_INFRA_TRNG_CK 55 +#define CLK_INFRA_AO_NR_CLK 46 /* APMIXEDSYS */ -#define CK_APMIXED_ARMPLL 0 -#define CK_APMIXED_NET2PLL 1 -#define CK_APMIXED_MMPLL 2 -#define CK_APMIXED_SGMPLL 3 -#define CK_APMIXED_WEDMCUPLL 4 -#define CK_APMIXED_NET1PLL 5 -#define CK_APMIXED_MPLL 6 -#define CK_APMIXED_APLL2 7 +#define CLK_APMIXED_ARMPLL 0 +#define CLK_APMIXED_NET2PLL 1 +#define CLK_APMIXED_MMPLL 2 +#define CLK_APMIXED_SGMPLL 3 +#define CLK_APMIXED_WEDMCUPLL 4 +#define CLK_APMIXED_NET1PLL 5 +#define CLK_APMIXED_MPLL 6 +#define CLK_APMIXED_APLL2 7 #define CLK_APMIXED_NR_CLK 8 /* SGMIISYS_0 */ -#define CK_SGM0_TX_EN 0 -#define CK_SGM0_RX_EN 1 -#define CK_SGM0_CK0_EN 2 -#define CK_SGM0_CDR_CK0_EN 3 +#define CLK_SGM0_TX_EN 0 +#define CLK_SGM0_RX_EN 1 +#define CLK_SGM0_CK0_EN 2 +#define CLK_SGM0_CDR_CK0_EN 3 #define CLK_SGMII0_NR_CLK 4 /* SGMIISYS_1 */ -#define CK_SGM1_TX_EN 0 -#define CK_SGM1_RX_EN 1 -#define CK_SGM1_CK1_EN 2 -#define CK_SGM1_CDR_CK1_EN 3 +#define CLK_SGM1_TX_EN 0 +#define CLK_SGM1_RX_EN 1 +#define CLK_SGM1_CK1_EN 2 +#define CLK_SGM1_CDR_CK1_EN 3 #define CLK_SGMII1_NR_CLK 4 /* ETHSYS */ -#define CK_ETH_FE_EN 0 -#define CK_ETH_GP2_EN 1 -#define CK_ETH_GP1_EN 2 -#define CK_ETH_WOCPU1_EN 3 -#define CK_ETH_WOCPU0_EN 4 +#define CLK_ETH_FE_EN 0 +#define CLK_ETH_GP2_EN 1 +#define CLK_ETH_GP1_EN 2 +#define CLK_ETH_WOCPU1_EN 3 +#define CLK_ETH_WOCPU0_EN 4 #define CLK_ETH_NR_CLK 5 #endif diff --git a/include/dt-bindings/clock/mt7988-clk.h b/include/dt-bindings/clock/mt7988-clk.h index 5c21bf63119..e6e6978809d 100644 --- a/include/dt-bindings/clock/mt7988-clk.h +++ b/include/dt-bindings/clock/mt7988-clk.h @@ -8,342 +8,257 @@ #ifndef _DT_BINDINGS_CLK_MT7988_H #define _DT_BINDINGS_CLK_MT7988_H -/* INFRACFG */ -/* mtk_fixed_factor */ -#define CK_INFRA_CK_F26M 0 -#define CK_INFRA_PWM_O 1 -#define CK_INFRA_PCIE_OCC_P0 2 -#define CK_INFRA_PCIE_OCC_P1 3 -#define CK_INFRA_PCIE_OCC_P2 4 -#define CK_INFRA_PCIE_OCC_P3 5 -#define CK_INFRA_133M_HCK 6 -#define CK_INFRA_133M_PHCK 7 -#define CK_INFRA_66M_PHCK 8 -#define CK_INFRA_FAUD_L_O 9 -#define CK_INFRA_FAUD_AUD_O 10 -#define CK_INFRA_FAUD_EG2_O 11 -#define CK_INFRA_I2C_O 12 -#define CK_INFRA_UART_O0 13 -#define CK_INFRA_UART_O1 14 -#define CK_INFRA_UART_O2 15 -#define CK_INFRA_NFI_O 16 -#define CK_INFRA_SPINFI_O 17 -#define CK_INFRA_SPI0_O 18 -#define CK_INFRA_SPI1_O 19 -#define CK_INFRA_LB_MUX_FRTC 20 -#define CK_INFRA_FRTC 21 -#define CK_INFRA_FMSDC400_O 22 -#define CK_INFRA_FMSDC2_HCK_OCC 23 -#define CK_INFRA_PERI_133M 24 -#define CK_INFRA_USB_O 25 -#define CK_INFRA_USB_O_P1 26 -#define CK_INFRA_USB_FRMCNT_O 27 -#define CK_INFRA_USB_FRMCNT_O_P1 28 -#define CK_INFRA_USB_XHCI_O 29 -#define CK_INFRA_USB_XHCI_O_P1 30 -#define CK_INFRA_USB_PIPE_O 31 -#define CK_INFRA_USB_PIPE_O_P1 32 -#define CK_INFRA_USB_UTMI_O 33 -#define CK_INFRA_USB_UTMI_O_P1 34 -#define CK_INFRA_PCIE_PIPE_OCC_P0 35 -#define CK_INFRA_PCIE_PIPE_OCC_P1 36 -#define CK_INFRA_PCIE_PIPE_OCC_P2 37 -#define CK_INFRA_PCIE_PIPE_OCC_P3 38 -#define CK_INFRA_F26M_O0 39 -#define CK_INFRA_F26M_O1 40 -#define CK_INFRA_133M_MCK 41 -#define CK_INFRA_66M_MCK 42 -#define CK_INFRA_PERI_66M_O 43 -#define CK_INFRA_USB_SYS_O 44 -#define CK_INFRA_USB_SYS_O_P1 45 - /* INFRACFG_AO */ -#define GATE_OFFSET 65 /* mtk_mux */ -#define CK_INFRA_MUX_UART0_SEL 46 /* Linux CLK ID (0) */ -#define CK_INFRA_MUX_UART1_SEL 47 /* Linux CLK ID (1) */ -#define CK_INFRA_MUX_UART2_SEL 48 /* Linux CLK ID (2) */ -#define CK_INFRA_MUX_SPI0_SEL 49 /* Linux CLK ID (3) */ -#define CK_INFRA_MUX_SPI1_SEL 50 /* Linux CLK ID (4) */ -#define CK_INFRA_MUX_SPI2_SEL 51 /* Linux CLK ID (5) */ -#define CK_INFRA_PWM_SEL 52 /* Linux CLK ID (6) */ -#define CK_INFRA_PWM_CK1_SEL 53 /* Linux CLK ID (7) */ -#define CK_INFRA_PWM_CK2_SEL 54 /* Linux CLK ID (8) */ -#define CK_INFRA_PWM_CK3_SEL 55 /* Linux CLK ID (9) */ -#define CK_INFRA_PWM_CK4_SEL 56 /* Linux CLK ID (10) */ -#define CK_INFRA_PWM_CK5_SEL 57 /* Linux CLK ID (11) */ -#define CK_INFRA_PWM_CK6_SEL 58 /* Linux CLK ID (12) */ -#define CK_INFRA_PWM_CK7_SEL 59 /* Linux CLK ID (13) */ -#define CK_INFRA_PWM_CK8_SEL 60 /* Linux CLK ID (14) */ -#define CK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 61 /* Linux CLK ID (15) */ -#define CK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 62 /* Linux CLK ID (16) */ -#define CK_INFRA_PCIE_GFMUX_TL_O_P2_SEL 63 /* Linux CLK ID (17) */ -#define CK_INFRA_PCIE_GFMUX_TL_O_P3_SEL 64 /* Linux CLK ID (18) */ +#define CLK_INFRA_MUX_UART0_SEL 0 +#define CLK_INFRA_MUX_UART1_SEL 1 +#define CLK_INFRA_MUX_UART2_SEL 2 +#define CLK_INFRA_MUX_SPI0_SEL 3 +#define CLK_INFRA_MUX_SPI1_SEL 4 +#define CLK_INFRA_MUX_SPI2_SEL 5 +#define CLK_INFRA_PWM_SEL 6 +#define CLK_INFRA_PWM_CK1_SEL 7 +#define CLK_INFRA_PWM_CK2_SEL 8 +#define CLK_INFRA_PWM_CK3_SEL 9 +#define CLK_INFRA_PWM_CK4_SEL 10 +#define CLK_INFRA_PWM_CK5_SEL 11 +#define CLK_INFRA_PWM_CK6_SEL 12 +#define CLK_INFRA_PWM_CK7_SEL 13 +#define CLK_INFRA_PWM_CK8_SEL 14 +#define CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 15 +#define CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 16 +#define CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL 17 +#define CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL 18 + +/* INFRACFG */ /* mtk_gate */ -#define CK_INFRA_66M_GPT_BCK (65 - GATE_OFFSET) /* Linux CLK ID (19) */ -#define CK_INFRA_66M_PWM_HCK (66 - GATE_OFFSET) /* Linux CLK ID (20) */ -#define CK_INFRA_66M_PWM_BCK (67 - GATE_OFFSET) /* Linux CLK ID (21) */ -#define CK_INFRA_66M_PWM_CK1 (68 - GATE_OFFSET) /* Linux CLK ID (22) */ -#define CK_INFRA_66M_PWM_CK2 (69 - GATE_OFFSET) /* Linux CLK ID (23) */ -#define CK_INFRA_66M_PWM_CK3 (70 - GATE_OFFSET) /* Linux CLK ID (24) */ -#define CK_INFRA_66M_PWM_CK4 (71 - GATE_OFFSET) /* Linux CLK ID (25) */ -#define CK_INFRA_66M_PWM_CK5 (72 - GATE_OFFSET) /* Linux CLK ID (26) */ -#define CK_INFRA_66M_PWM_CK6 (73 - GATE_OFFSET) /* Linux CLK ID (27) */ -#define CK_INFRA_66M_PWM_CK7 (74 - GATE_OFFSET) /* Linux CLK ID (28) */ -#define CK_INFRA_66M_PWM_CK8 (75 - GATE_OFFSET) /* Linux CLK ID (29) */ -#define CK_INFRA_133M_CQDMA_BCK (76 - GATE_OFFSET) /* Linux CLK ID (30) */ -#define CK_INFRA_66M_AUD_SLV_BCK (77 - GATE_OFFSET) /* Linux CLK ID (31) */ -#define CK_INFRA_AUD_26M (78 - GATE_OFFSET) /* Linux CLK ID (32) */ -#define CK_INFRA_AUD_L (79 - GATE_OFFSET) /* Linux CLK ID (33) */ -#define CK_INFRA_AUD_AUD (80 - GATE_OFFSET) /* Linux CLK ID (34) */ -#define CK_INFRA_AUD_EG2 (81 - GATE_OFFSET) /* Linux CLK ID (35) */ -#define CK_INFRA_DRAMC_F26M (82 - GATE_OFFSET) /* Linux CLK ID (36) */ -#define CK_INFRA_133M_DBG_ACKM (83 - GATE_OFFSET) /* Linux CLK ID (37) */ -#define CK_INFRA_66M_AP_DMA_BCK (84 - GATE_OFFSET) /* Linux CLK ID (38) */ -#define CK_INFRA_66M_SEJ_BCK (85 - GATE_OFFSET) /* Linux CLK ID (39) */ -#define CK_INFRA_PRE_CK_SEJ_F13M (86 - GATE_OFFSET) /* Linux CLK ID (40) */ -#define CK_INFRA_66M_TRNG (87 - GATE_OFFSET) /* Linux CLK ID (41) */ -#define CK_INFRA_26M_THERM_SYSTEM (88 - GATE_OFFSET) /* Linux CLK ID (42) */ -#define CK_INFRA_I2C_BCK (89 - GATE_OFFSET) /* Linux CLK ID (43) */ -#define CK_INFRA_66M_UART0_PCK (90 - GATE_OFFSET) /* Linux CLK ID (44) */ -#define CK_INFRA_66M_UART1_PCK (91 - GATE_OFFSET) /* Linux CLK ID (45) */ -#define CK_INFRA_66M_UART2_PCK (92 - GATE_OFFSET) /* Linux CLK ID (46) */ -#define CK_INFRA_52M_UART0_CK (93 - GATE_OFFSET) /* Linux CLK ID (47) */ -#define CK_INFRA_52M_UART1_CK (94 - GATE_OFFSET) /* Linux CLK ID (48) */ -#define CK_INFRA_52M_UART2_CK (95 - GATE_OFFSET) /* Linux CLK ID (49) */ -#define CK_INFRA_NFI (96 - GATE_OFFSET) /* Linux CLK ID (50) */ -#define CK_INFRA_SPINFI (97 - GATE_OFFSET) /* Linux CLK ID (51) */ -#define CK_INFRA_66M_NFI_HCK (98 - GATE_OFFSET) /* Linux CLK ID (52) */ -#define CK_INFRA_104M_SPI0 (99 - GATE_OFFSET) /* Linux CLK ID (53) */ -#define CK_INFRA_104M_SPI1 (100 - GATE_OFFSET) /* Linux CLK ID (54) */ -#define CK_INFRA_104M_SPI2_BCK (101 - GATE_OFFSET) /* Linux CLK ID (55) */ -#define CK_INFRA_66M_SPI0_HCK (102 - GATE_OFFSET) /* Linux CLK ID (56) */ -#define CK_INFRA_66M_SPI1_HCK (103 - GATE_OFFSET) /* Linux CLK ID (57) */ -#define CK_INFRA_66M_SPI2_HCK (104 - GATE_OFFSET) /* Linux CLK ID (58) */ -#define CK_INFRA_66M_FLASHIF_AXI (105 - GATE_OFFSET) /* Linux CLK ID (59) */ -#define CK_INFRA_RTC (106 - GATE_OFFSET) /* Linux CLK ID (60) */ -#define CK_INFRA_26M_ADC_BCK (107 - GATE_OFFSET) /* Linux CLK ID (61) */ -#define CK_INFRA_RC_ADC (108 - GATE_OFFSET) /* Linux CLK ID (62) */ -#define CK_INFRA_MSDC400 (109 - GATE_OFFSET) /* Linux CLK ID (63) */ -#define CK_INFRA_MSDC2_HCK (110 - GATE_OFFSET) /* Linux CLK ID (64) */ -#define CK_INFRA_133M_MSDC_0_HCK (111 - GATE_OFFSET) /* Linux CLK ID (65) */ -#define CK_INFRA_66M_MSDC_0_HCK (112 - GATE_OFFSET) /* Linux CLK ID (66) */ -#define CK_INFRA_133M_CPUM_BCK (113 - GATE_OFFSET) /* Linux CLK ID (67) */ -#define CK_INFRA_BIST2FPC (114 - GATE_OFFSET) /* Linux CLK ID (68) */ -#define CK_INFRA_I2C_X16W_MCK_CK_P1 (115 - GATE_OFFSET) /* Linux CLK ID (69) */ -#define CK_INFRA_I2C_X16W_PCK_CK_P1 (116 - GATE_OFFSET) /* Linux CLK ID (70) */ -#define CK_INFRA_133M_USB_HCK (117 - GATE_OFFSET) /* Linux CLK ID (71) */ -#define CK_INFRA_133M_USB_HCK_CK_P1 (118 - GATE_OFFSET) /* Linux CLK ID (72) */ -#define CK_INFRA_66M_USB_HCK (119 - GATE_OFFSET) /* Linux CLK ID (73) */ -#define CK_INFRA_66M_USB_HCK_CK_P1 (120 - GATE_OFFSET) /* Linux CLK ID (74) */ -#define CK_INFRA_USB_SYS (121 - GATE_OFFSET) /* Linux CLK ID (75) */ -#define CK_INFRA_USB_SYS_CK_P1 (122 - GATE_OFFSET) /* Linux CLK ID (76) */ -#define CK_INFRA_USB_REF (123 - GATE_OFFSET) /* Linux CLK ID (77) */ -#define CK_INFRA_USB_CK_P1 (124 - GATE_OFFSET) /* Linux CLK ID (78) */ -#define CK_INFRA_USB_FRMCNT (125 - GATE_OFFSET) /* Linux CLK ID (79) */ -#define CK_INFRA_USB_FRMCNT_CK_P1 (126 - GATE_OFFSET) /* Linux CLK ID (80) */ -#define CK_INFRA_USB_PIPE (127 - GATE_OFFSET) /* Linux CLK ID (81) */ -#define CK_INFRA_USB_PIPE_CK_P1 (128 - GATE_OFFSET) /* Linux CLK ID (82) */ -#define CK_INFRA_USB_UTMI (129 - GATE_OFFSET) /* Linux CLK ID (83) */ -#define CK_INFRA_USB_UTMI_CK_P1 (130 - GATE_OFFSET) /* Linux CLK ID (84) */ -#define CK_INFRA_USB_XHCI (131 - GATE_OFFSET) /* Linux CLK ID (85) */ -#define CK_INFRA_USB_XHCI_CK_P1 (132 - GATE_OFFSET) /* Linux CLK ID (86) */ -#define CK_INFRA_PCIE_GFMUX_TL_P0 (133 - GATE_OFFSET) /* Linux CLK ID (87) */ -#define CK_INFRA_PCIE_GFMUX_TL_P1 (134 - GATE_OFFSET) /* Linux CLK ID (88) */ -#define CK_INFRA_PCIE_GFMUX_TL_P2 (135 - GATE_OFFSET) /* Linux CLK ID (89) */ -#define CK_INFRA_PCIE_GFMUX_TL_P3 (136 - GATE_OFFSET) /* Linux CLK ID (90) */ -#define CK_INFRA_PCIE_PIPE_P0 (137 - GATE_OFFSET) /* Linux CLK ID (91) */ -#define CK_INFRA_PCIE_PIPE_P1 (138 - GATE_OFFSET) /* Linux CLK ID (92) */ -#define CK_INFRA_PCIE_PIPE_P2 (139 - GATE_OFFSET) /* Linux CLK ID (93) */ -#define CK_INFRA_PCIE_PIPE_P3 (140 - GATE_OFFSET) /* Linux CLK ID (94) */ -#define CK_INFRA_133M_PCIE_CK_P0 (141 - GATE_OFFSET) /* Linux CLK ID (95) */ -#define CK_INFRA_133M_PCIE_CK_P1 (142 - GATE_OFFSET) /* Linux CLK ID (96) */ -#define CK_INFRA_133M_PCIE_CK_P2 (143 - GATE_OFFSET) /* Linux CLK ID (97) */ -#define CK_INFRA_133M_PCIE_CK_P3 (144 - GATE_OFFSET) /* Linux CLK ID (98) */ -#define CK_INFRA_PCIE_PERI_26M_CK_P0 (145 - GATE_OFFSET) /* Linux CLK ID (99) */ -#define CK_INFRA_PCIE_PERI_26M_CK_P1 \ - (146 - GATE_OFFSET) /* Linux CLK ID (100) */ -#define CK_INFRA_PCIE_PERI_26M_CK_P2 \ - (147 - GATE_OFFSET) /* Linux CLK ID (101) */ -#define CK_INFRA_PCIE_PERI_26M_CK_P3 \ - (148 - GATE_OFFSET) /* Linux CLK ID (102) */ +#define CLK_INFRA_PCIE_PERI_26M_CK_P0 19 +#define CLK_INFRA_PCIE_PERI_26M_CK_P1 20 +#define CLK_INFRA_PCIE_PERI_26M_CK_P2 21 +#define CLK_INFRA_PCIE_PERI_26M_CK_P3 22 +#define CLK_INFRA_66M_GPT_BCK 23 +#define CLK_INFRA_66M_PWM_HCK 24 +#define CLK_INFRA_66M_PWM_BCK 25 +#define CLK_INFRA_66M_PWM_CK1 26 +#define CLK_INFRA_66M_PWM_CK2 27 +#define CLK_INFRA_66M_PWM_CK3 28 +#define CLK_INFRA_66M_PWM_CK4 29 +#define CLK_INFRA_66M_PWM_CK5 30 +#define CLK_INFRA_66M_PWM_CK6 31 +#define CLK_INFRA_66M_PWM_CK7 32 +#define CLK_INFRA_66M_PWM_CK8 33 +#define CLK_INFRA_133M_CQDMA_BCK 34 +#define CLK_INFRA_66M_AUD_SLV_BCK 35 +#define CLK_INFRA_AUD_26M 36 +#define CLK_INFRA_AUD_L 37 +#define CLK_INFRA_AUD_AUD 38 +#define CLK_INFRA_AUD_EG2 39 +#define CLK_INFRA_DRAMC_F26M 40 +#define CLK_INFRA_133M_DBG_ACKM 41 +#define CLK_INFRA_66M_AP_DMA_BCK 42 +#define CLK_INFRA_66M_SEJ_BCK 43 +#define CLK_INFRA_PRE_CK_SEJ_F13M 44 +/* #define CLK_INFRA_66M_TRNG 44 */ +#define CLK_INFRA_26M_THERM_SYSTEM 45 +#define CLK_INFRA_I2C_BCK 46 +/* #define CLK_INFRA_66M_UART0_PCK 46 */ +/* #define CLK_INFRA_66M_UART1_PCK 47 */ +/* #define CLK_INFRA_66M_UART2_PCK 48 */ +#define CLK_INFRA_52M_UART0_CK 47 +#define CLK_INFRA_52M_UART1_CK 48 +#define CLK_INFRA_52M_UART2_CK 49 +#define CLK_INFRA_NFI 50 +#define CLK_INFRA_SPINFI 51 +#define CLK_INFRA_66M_NFI_HCK 52 +#define CLK_INFRA_104M_SPI0 53 +#define CLK_INFRA_104M_SPI1 54 +#define CLK_INFRA_104M_SPI2_BCK 55 +#define CLK_INFRA_66M_SPI0_HCK 56 +#define CLK_INFRA_66M_SPI1_HCK 57 +#define CLK_INFRA_66M_SPI2_HCK 58 +#define CLK_INFRA_66M_FLASHIF_AXI 59 +#define CLK_INFRA_RTC 60 +#define CLK_INFRA_26M_ADC_BCK 61 +#define CLK_INFRA_RC_ADC 62 +#define CLK_INFRA_MSDC400 63 +#define CLK_INFRA_MSDC2_HCK 64 +#define CLK_INFRA_133M_MSDC_0_HCK 65 +#define CLK_INFRA_66M_MSDC_0_HCK 66 +#define CLK_INFRA_133M_CPUM_BCK 67 +#define CLK_INFRA_BIST2FPC 68 +#define CLK_INFRA_I2C_X16W_MCK_CK_P1 69 +#define CLK_INFRA_I2C_X16W_PCK_CK_P1 70 +#define CLK_INFRA_133M_USB_HCK 71 +#define CLK_INFRA_133M_USB_HCK_CK_P1 72 +#define CLK_INFRA_66M_USB_HCK 73 +#define CLK_INFRA_66M_USB_HCK_CK_P1 74 +#define CLK_INFRA_USB_SYS 75 +#define CLK_INFRA_USB_SYS_CK_P1 76 +#define CLK_INFRA_USB_REF 77 +#define CLK_INFRA_USB_CK_P1 78 +#define CLK_INFRA_USB_FRMCNT 79 +#define CLK_INFRA_USB_FRMCNT_CK_P1 80 +#define CLK_INFRA_USB_PIPE 81 +#define CLK_INFRA_USB_PIPE_CK_P1 82 +#define CLK_INFRA_USB_UTMI 83 +#define CLK_INFRA_USB_UTMI_CK_P1 84 +#define CLK_INFRA_USB_XHCI 85 +#define CLK_INFRA_USB_XHCI_CK_P1 86 +#define CLK_INFRA_PCIE_GFMUX_TL_P0 87 +#define CLK_INFRA_PCIE_GFMUX_TL_P1 88 +#define CLK_INFRA_PCIE_GFMUX_TL_P2 89 +#define CLK_INFRA_PCIE_GFMUX_TL_P3 90 +#define CLK_INFRA_PCIE_PIPE_P0 91 +#define CLK_INFRA_PCIE_PIPE_P1 92 +#define CLK_INFRA_PCIE_PIPE_P2 93 +#define CLK_INFRA_PCIE_PIPE_P3 94 +#define CLK_INFRA_133M_PCIE_CK_P0 95 +#define CLK_INFRA_133M_PCIE_CK_P1 96 +#define CLK_INFRA_133M_PCIE_CK_P2 97 +#define CLK_INFRA_133M_PCIE_CK_P3 98 /* TOPCKGEN */ +/* mtk_fixed_clk */ +#define CLK_TOP_XTAL 0 /* mtk_fixed_factor */ -#define CK_TOP_CB_CKSQ_40M 0 /* Linux CLK ID (74) */ -#define CK_TOP_CB_M_416M 1 /* Linux CLK ID (75) */ -#define CK_TOP_CB_M_D2 2 /* Linux CLK ID (76) */ -#define CK_TOP_M_D3_D2 3 /* Linux CLK ID (77) */ -#define CK_TOP_CB_M_D4 4 /* Linux CLK ID (78) */ -#define CK_TOP_CB_M_D8 5 /* Linux CLK ID (79) */ -#define CK_TOP_M_D8_D2 6 /* Linux CLK ID (80) */ -#define CK_TOP_CB_MM_720M 7 /* Linux CLK ID (81) */ -#define CK_TOP_CB_MM_D2 8 /* Linux CLK ID (82) */ -#define CK_TOP_CB_MM_D3_D5 9 /* Linux CLK ID (83) */ -#define CK_TOP_CB_MM_D4 10 /* Linux CLK ID (84) */ -#define CK_TOP_MM_D6_D2 11 /* Linux CLK ID (85) */ -#define CK_TOP_CB_MM_D8 12 /* Linux CLK ID (86) */ -#define CK_TOP_CB_APLL2_196M 13 /* Linux CLK ID (87) */ -#define CK_TOP_CB_APLL2_D4 14 /* Linux CLK ID (88) */ -#define CK_TOP_CB_NET1_D4 15 /* Linux CLK ID (89) */ -#define CK_TOP_CB_NET1_D5 16 /* Linux CLK ID (90) */ -#define CK_TOP_NET1_D5_D2 17 /* Linux CLK ID (91) */ -#define CK_TOP_NET1_D5_D4 18 /* Linux CLK ID (92) */ -#define CK_TOP_CB_NET1_D8 19 /* Linux CLK ID (93) */ -#define CK_TOP_NET1_D8_D2 20 /* Linux CLK ID (94) */ -#define CK_TOP_NET1_D8_D4 21 /* Linux CLK ID (95) */ -#define CK_TOP_NET1_D8_D8 22 /* Linux CLK ID (96) */ -#define CK_TOP_NET1_D8_D16 23 /* Linux CLK ID (97) */ -#define CK_TOP_CB_NET2_800M 24 /* Linux CLK ID (98) */ -#define CK_TOP_CB_NET2_D2 25 /* Linux CLK ID (99) */ -#define CK_TOP_CB_NET2_D4 26 /* Linux CLK ID (100) */ -#define CK_TOP_NET2_D4_D4 27 /* Linux CLK ID (101) */ -#define CK_TOP_NET2_D4_D8 28 /* Linux CLK ID (102) */ -#define CK_TOP_CB_NET2_D6 29 /* Linux CLK ID (103) */ -#define CK_TOP_CB_NET2_D8 30 /* Linux CLK ID (104) */ -#define CK_TOP_CB_WEDMCU_208M 31 /* Linux CLK ID (105) */ -#define CK_TOP_CB_SGM_325M 32 /* Linux CLK ID (106) */ -#define CK_TOP_CB_NETSYS_850M 33 /* Linux CLK ID (107) */ -#define CK_TOP_CB_MSDC_400M 34 /* Linux CLK ID (108) */ -#define CK_TOP_CKSQ_40M_D2 35 /* Linux CLK ID (109) */ -#define CK_TOP_CB_RTC_32K 36 /* Linux CLK ID (110) */ -#define CK_TOP_CB_RTC_32P7K 37 /* Linux CLK ID (111) */ -#define CK_TOP_INFRA_F32K 38 /* Linux CLK ID (112) */ -#define CK_TOP_CKSQ_SRC 39 /* Linux CLK ID (113) */ -#define CK_TOP_NETSYS_2X 40 /* Linux CLK ID (114) */ -#define CK_TOP_NETSYS_GSW 41 /* Linux CLK ID (115) */ -#define CK_TOP_NETSYS_WED_MCU 42 /* Linux CLK ID (116) */ -#define CK_TOP_EIP197 43 /* Linux CLK ID (117) */ -#define CK_TOP_EMMC_250M 44 /* Linux CLK ID (118) */ -#define CK_TOP_EMMC_400M 45 /* Linux CLK ID (119) */ -#define CK_TOP_SPI 46 /* Linux CLK ID (120) */ -#define CK_TOP_SPIM_MST 47 /* Linux CLK ID (121) */ -#define CK_TOP_NFI1X 48 /* Linux CLK ID (122) */ -#define CK_TOP_SPINFI_BCK 49 /* Linux CLK ID (123) */ -#define CK_TOP_I2C_BCK 50 /* Linux CLK ID (124) */ -#define CK_TOP_USB_SYS 51 /* Linux CLK ID (125) */ -#define CK_TOP_USB_SYS_P1 52 /* Linux CLK ID (126) */ -#define CK_TOP_USB_XHCI 53 /* Linux CLK ID (127) */ -#define CK_TOP_USB_XHCI_P1 54 /* Linux CLK ID (128) */ -#define CK_TOP_USB_FRMCNT 55 /* Linux CLK ID (129) */ -#define CK_TOP_USB_FRMCNT_P1 56 /* Linux CLK ID (130) */ -#define CK_TOP_AUD 57 /* Linux CLK ID (131) */ -#define CK_TOP_A1SYS 58 /* Linux CLK ID (132) */ -#define CK_TOP_AUD_L 59 /* Linux CLK ID (133) */ -#define CK_TOP_A_TUNER 60 /* Linux CLK ID (134) */ -#define CK_TOP_SYSAXI 61 /* Linux CLK ID (135) */ -#define CK_TOP_INFRA_F26M 62 /* Linux CLK ID (136) */ -#define CK_TOP_USB_REF 63 /* Linux CLK ID (137) */ -#define CK_TOP_USB_CK_P1 64 /* Linux CLK ID (138) */ +#define CLK_TOP_XTAL_D2 1 +#define CLK_TOP_RTC_32K 2 +#define CLK_TOP_RTC_32P7K 3 +#define CLK_TOP_MPLL_D2 4 +#define CLK_TOP_MPLL_D3_D2 5 +#define CLK_TOP_MPLL_D4 6 +#define CLK_TOP_MPLL_D8 7 +#define CLK_TOP_MPLL_D8_D2 8 +#define CLK_TOP_MMPLL_D2 9 +#define CLK_TOP_MMPLL_D3_D5 10 +#define CLK_TOP_MMPLL_D4 11 +#define CLK_TOP_MMPLL_D6_D2 12 +#define CLK_TOP_MMPLL_D8 13 +#define CLK_TOP_APLL2_D4 14 +#define CLK_TOP_NET1PLL_D4 15 +#define CLK_TOP_NET1PLL_D5 16 +#define CLK_TOP_NET1PLL_D5_D2 17 +#define CLK_TOP_NET1PLL_D5_D4 18 +#define CLK_TOP_NET1PLL_D8 19 +#define CLK_TOP_NET1PLL_D8_D2 20 +#define CLK_TOP_NET1PLL_D8_D4 21 +#define CLK_TOP_NET1PLL_D8_D8 22 +#define CLK_TOP_NET1PLL_D8_D16 23 +#define CLK_TOP_NET2PLL_D2 24 +#define CLK_TOP_NET2PLL_D4 25 +#define CLK_TOP_NET2PLL_D4_D4 26 +#define CLK_TOP_NET2PLL_D4_D8 27 +#define CLK_TOP_NET2PLL_D6 28 +#define CLK_TOP_NET2PLL_D8 29 /* mtk_mux */ -#define CK_TOP_NETSYS_SEL 65 /* Linux CLK ID (0) */ -#define CK_TOP_NETSYS_500M_SEL 66 /* Linux CLK ID (1) */ -#define CK_TOP_NETSYS_2X_SEL 67 /* Linux CLK ID (2) */ -#define CK_TOP_NETSYS_GSW_SEL 68 /* Linux CLK ID (3) */ -#define CK_TOP_ETH_GMII_SEL 69 /* Linux CLK ID (4) */ -#define CK_TOP_NETSYS_MCU_SEL 70 /* Linux CLK ID (5) */ -#define CK_TOP_NETSYS_PAO_2X_SEL 71 /* Linux CLK ID (6) */ -#define CK_TOP_EIP197_SEL 72 /* Linux CLK ID (7) */ -#define CK_TOP_AXI_INFRA_SEL 73 /* Linux CLK ID (8) */ -#define CK_TOP_UART_SEL 74 /* Linux CLK ID (9) */ -#define CK_TOP_EMMC_250M_SEL 75 /* Linux CLK ID (10) */ -#define CK_TOP_EMMC_400M_SEL 76 /* Linux CLK ID (11) */ -#define CK_TOP_SPI_SEL 77 /* Linux CLK ID (12) */ -#define CK_TOP_SPIM_MST_SEL 78 /* Linux CLK ID (13) */ -#define CK_TOP_NFI1X_SEL 79 /* Linux CLK ID (14) */ -#define CK_TOP_SPINFI_SEL 80 /* Linux CLK ID (15) */ -#define CK_TOP_PWM_SEL 81 /* Linux CLK ID (16) */ -#define CK_TOP_I2C_SEL 82 /* Linux CLK ID (17) */ -#define CK_TOP_PCIE_MBIST_250M_SEL 83 /* Linux CLK ID (18) */ -#define CK_TOP_PEXTP_TL_SEL 84 /* Linux CLK ID (19) */ -#define CK_TOP_PEXTP_TL_P1_SEL 85 /* Linux CLK ID (20) */ -#define CK_TOP_PEXTP_TL_P2_SEL 86 /* Linux CLK ID (21) */ -#define CK_TOP_PEXTP_TL_P3_SEL 87 /* Linux CLK ID (22) */ -#define CK_TOP_USB_SYS_SEL 88 /* Linux CLK ID (23) */ -#define CK_TOP_USB_SYS_P1_SEL 89 /* Linux CLK ID (24) */ -#define CK_TOP_USB_XHCI_SEL 90 /* Linux CLK ID (25) */ -#define CK_TOP_USB_XHCI_P1_SEL 91 /* Linux CLK ID (26) */ -#define CK_TOP_USB_FRMCNT_SEL 92 /* Linux CLK ID (27) */ -#define CK_TOP_USB_FRMCNT_P1_SEL 93 /* Linux CLK ID (28) */ -#define CK_TOP_AUD_SEL 94 /* Linux CLK ID (29) */ -#define CK_TOP_A1SYS_SEL 95 /* Linux CLK ID (30) */ -#define CK_TOP_AUD_L_SEL 96 /* Linux CLK ID (31) */ -#define CK_TOP_A_TUNER_SEL 97 /* Linux CLK ID (32) */ -#define CK_TOP_SSPXTP_SEL 98 /* Linux CLK ID (33) */ -#define CK_TOP_USB_PHY_SEL 99 /* Linux CLK ID (34) */ -#define CK_TOP_USXGMII_SBUS_0_SEL 100 /* Linux CLK ID (35) */ -#define CK_TOP_USXGMII_SBUS_1_SEL 101 /* Linux CLK ID (36) */ -#define CK_TOP_SGM_0_SEL 102 /* Linux CLK ID (37) */ -#define CK_TOP_SGM_SBUS_0_SEL 103 /* Linux CLK ID (38) */ -#define CK_TOP_SGM_1_SEL 104 /* Linux CLK ID (39) */ -#define CK_TOP_SGM_SBUS_1_SEL 105 /* Linux CLK ID (40) */ -#define CK_TOP_XFI_PHY_0_XTAL_SEL 106 /* Linux CLK ID (41) */ -#define CK_TOP_XFI_PHY_1_XTAL_SEL 107 /* Linux CLK ID (42) */ -#define CK_TOP_SYSAXI_SEL 108 /* Linux CLK ID (43) */ -#define CK_TOP_SYSAPB_SEL 109 /* Linux CLK ID (44) */ -#define CK_TOP_ETH_REFCK_50M_SEL 110 /* Linux CLK ID (45) */ -#define CK_TOP_ETH_SYS_200M_SEL 111 /* Linux CLK ID (46) */ -#define CK_TOP_ETH_SYS_SEL 112 /* Linux CLK ID (47) */ -#define CK_TOP_ETH_XGMII_SEL 113 /* Linux CLK ID (48) */ -#define CK_TOP_BUS_TOPS_SEL 114 /* Linux CLK ID (49) */ -#define CK_TOP_NPU_TOPS_SEL 115 /* Linux CLK ID (50) */ -#define CK_TOP_DRAMC_SEL 116 /* Linux CLK ID (51) */ -#define CK_TOP_DRAMC_MD32_SEL 117 /* Linux CLK ID (52) */ -#define CK_TOP_INFRA_F26M_SEL 118 /* Linux CLK ID (53) */ -#define CK_TOP_PEXTP_P0_SEL 119 /* Linux CLK ID (54) */ -#define CK_TOP_PEXTP_P1_SEL 120 /* Linux CLK ID (55) */ -#define CK_TOP_PEXTP_P2_SEL 121 /* Linux CLK ID (56) */ -#define CK_TOP_PEXTP_P3_SEL 122 /* Linux CLK ID (57) */ -#define CK_TOP_DA_XTP_GLB_P0_SEL 123 /* Linux CLK ID (58) */ -#define CK_TOP_DA_XTP_GLB_P1_SEL 124 /* Linux CLK ID (59) */ -#define CK_TOP_DA_XTP_GLB_P2_SEL 125 /* Linux CLK ID (60) */ -#define CK_TOP_DA_XTP_GLB_P3_SEL 126 /* Linux CLK ID (61) */ -#define CK_TOP_CKM_SEL 127 /* Linux CLK ID (62) */ -#define CK_TOP_DA_SELM_XTAL_SEL 128 /* Linux CLK ID (63) */ -#define CK_TOP_PEXTP_SEL 129 /* Linux CLK ID (64) */ -#define CK_TOP_TOPS_P2_26M_SEL 130 /* Linux CLK ID (65) */ -#define CK_TOP_MCUSYS_BACKUP_625M_SEL 131 /* Linux CLK ID (66) */ -#define CK_TOP_NETSYS_SYNC_250M_SEL 132 /* Linux CLK ID (67) */ -#define CK_TOP_MACSEC_SEL 133 /* Linux CLK ID (68) */ -#define CK_TOP_NETSYS_TOPS_400M_SEL 134 /* Linux CLK ID (69) */ -#define CK_TOP_NETSYS_PPEFB_250M_SEL 135 /* Linux CLK ID (70) */ -#define CK_TOP_NETSYS_WARP_SEL 136 /* Linux CLK ID (71) */ -#define CK_TOP_ETH_MII_SEL 137 /* Linux CLK ID (72) */ -#define CK_TOP_CK_NPU_SEL_CM_TOPS_SEL 138 /* Linux CLK ID (73) */ +#define CLK_TOP_NETSYS_SEL 30 +#define CLK_TOP_NETSYS_500M_SEL 31 +#define CLK_TOP_NETSYS_2X_SEL 32 +#define CLK_TOP_NETSYS_GSW_SEL 33 +#define CLK_TOP_ETH_GMII_SEL 34 +#define CLK_TOP_NETSYS_MCU_SEL 35 +#define CLK_TOP_NETSYS_PAO_2X_SEL 36 +#define CLK_TOP_EIP197_SEL 37 +#define CLK_TOP_AXI_INFRA_SEL 38 +#define CLK_TOP_UART_SEL 39 +#define CLK_TOP_EMMC_250M_SEL 40 +#define CLK_TOP_EMMC_400M_SEL 41 +#define CLK_TOP_SPI_SEL 42 +#define CLK_TOP_SPIM_MST_SEL 43 +#define CLK_TOP_NFI1X_SEL 44 +#define CLK_TOP_SPINFI_SEL 45 +#define CLK_TOP_PWM_SEL 46 +#define CLK_TOP_I2C_SEL 47 +#define CLK_TOP_PCIE_MBIST_250M_SEL 48 +#define CLK_TOP_PEXTP_TL_SEL 49 +#define CLK_TOP_PEXTP_TL_P1_SEL 50 +#define CLK_TOP_PEXTP_TL_P2_SEL 51 +#define CLK_TOP_PEXTP_TL_P3_SEL 52 +#define CLK_TOP_USB_SYS_SEL 53 +#define CLK_TOP_USB_SYS_P1_SEL 54 +#define CLK_TOP_USB_XHCI_SEL 55 +#define CLK_TOP_USB_XHCI_P1_SEL 56 +#define CLK_TOP_USB_FRMCNT_SEL 57 +#define CLK_TOP_USB_FRMCNT_P1_SEL 58 +#define CLK_TOP_AUD_SEL 59 +#define CLK_TOP_A1SYS_SEL 60 +#define CLK_TOP_AUD_L_SEL 61 +#define CLK_TOP_A_TUNER_SEL 62 +#define CLK_TOP_SSPXTP_SEL 63 +#define CLK_TOP_USB_PHY_SEL 64 +#define CLK_TOP_USXGMII_SBUS_0_SEL 65 +#define CLK_TOP_USXGMII_SBUS_1_SEL 66 +#define CLK_TOP_SGM_0_SEL 67 +#define CLK_TOP_SGM_SBUS_0_SEL 68 +#define CLK_TOP_SGM_1_SEL 69 +#define CLK_TOP_SGM_SBUS_1_SEL 70 +#define CLK_TOP_XFI_PHY_0_XTAL_SEL 71 +#define CLK_TOP_XFI_PHY_1_XTAL_SEL 72 +#define CLK_TOP_SYSAXI_SEL 73 +#define CLK_TOP_SYSAPB_SEL 74 +#define CLK_TOP_ETH_REFCK_50M_SEL 75 +#define CLK_TOP_ETH_SYS_200M_SEL 76 +#define CLK_TOP_ETH_SYS_SEL 77 +#define CLK_TOP_ETH_XGMII_SEL 78 +#define CLK_TOP_BUS_TOPS_SEL 79 +#define CLK_TOP_NPU_TOPS_SEL 80 +#define CLK_TOP_DRAMC_SEL 81 +#define CLK_TOP_DRAMC_MD32_SEL 82 +#define CLK_TOP_INFRA_F26M_SEL 83 +#define CLK_TOP_PEXTP_P0_SEL 84 +#define CLK_TOP_PEXTP_P1_SEL 85 +#define CLK_TOP_PEXTP_P2_SEL 86 +#define CLK_TOP_PEXTP_P3_SEL 87 +#define CLK_TOP_DA_XTP_GLB_P0_SEL 88 +#define CLK_TOP_DA_XTP_GLB_P1_SEL 89 +#define CLK_TOP_DA_XTP_GLB_P2_SEL 90 +#define CLK_TOP_DA_XTP_GLB_P3_SEL 91 +#define CLK_TOP_CKM_SEL 92 +#define CLK_TOP_DA_SEL 93 +#define CLK_TOP_PEXTP_SEL 94 +#define CLK_TOP_TOPS_P2_26M_SEL 95 +#define CLK_TOP_MCUSYS_BACKUP_625M_SEL 96 +#define CLK_TOP_NETSYS_SYNC_250M_SEL 97 +#define CLK_TOP_MACSEC_SEL 98 +#define CLK_TOP_NETSYS_TOPS_400M_SEL 99 +#define CLK_TOP_NETSYS_PPEFB_250M_SEL 100 +#define CLK_TOP_NETSYS_WARP_SEL 101 +#define CLK_TOP_ETH_MII_SEL 102 +#define CLK_TOP_NPU_SEL 103 /* APMIXEDSYS */ /* mtk_pll_data */ -#define CK_APMIXED_NETSYSPLL 0 -#define CK_APMIXED_MPLL 1 -#define CK_APMIXED_MMPLL 2 -#define CK_APMIXED_APLL2 3 -#define CK_APMIXED_NET1PLL 4 -#define CK_APMIXED_NET2PLL 5 -#define CK_APMIXED_WEDMCUPLL 6 -#define CK_APMIXED_SGMPLL 7 -#define CK_APMIXED_ARM_B 8 -#define CK_APMIXED_CCIPLL2_B 9 -#define CK_APMIXED_USXGMIIPLL 10 -#define CK_APMIXED_MSDCPLL 11 +#define CLK_APMIXED_NETSYSPLL 0 +#define CLK_APMIXED_MPLL 1 +#define CLK_APMIXED_MMPLL 2 +#define CLK_APMIXED_APLL2 3 +#define CLK_APMIXED_NET1PLL 4 +#define CLK_APMIXED_NET2PLL 5 +#define CLK_APMIXED_WEDMCUPLL 6 +#define CLK_APMIXED_SGMPLL 7 +#define CLK_APMIXED_ARM_B 8 +#define CLK_APMIXED_CCIPLL2_B 9 +#define CLK_APMIXED_USXGMIIPLL 10 +#define CLK_APMIXED_MSDCPLL 11 /* ETHSYS ETH DMA */ /* mtk_gate */ -#define CK_ETHDMA_FE_EN 0 +#define CLK_ETHDMA_FE_EN 0 /* SGMIISYS_0 */ /* mtk_gate */ -#define CK_SGM0_TX_EN 0 -#define CK_SGM0_RX_EN 1 +#define CLK_SGM0_TX_EN 0 +#define CLK_SGM0_RX_EN 1 /* SGMIISYS_1 */ /* mtk_gate */ -#define CK_SGM1_TX_EN 0 -#define CK_SGM1_RX_EN 1 +#define CLK_SGM1_TX_EN 0 +#define CLK_SGM1_RX_EN 1 /* ETHWARP */ /* mtk_gate */ -#define CK_ETHWARP_WOCPU2_EN 0 -#define CK_ETHWARP_WOCPU1_EN 1 -#define CK_ETHWARP_WOCPU0_EN 2 +#define CLK_ETHWARP_WOCPU2_EN 0 +#define CLK_ETHWARP_WOCPU1_EN 1 +#define CLK_ETHWARP_WOCPU0_EN 2 #endif /* _DT_BINDINGS_CLK_MT7988_H */ diff --git a/include/dt-bindings/clock/sophgo,cv1800.h b/include/dt-bindings/clock/sophgo,cv1800.h new file mode 100644 index 00000000000..cfbeca25a65 --- /dev/null +++ b/include/dt-bindings/clock/sophgo,cv1800.h @@ -0,0 +1,176 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Copyright (C) 2023 Sophgo Ltd. + */ + +#ifndef __DT_BINDINGS_SOPHGO_CV1800_CLK_H__ +#define __DT_BINDINGS_SOPHGO_CV1800_CLK_H__ + +#define CLK_MPLL 0 +#define CLK_TPLL 1 +#define CLK_FPLL 2 +#define CLK_MIPIMPLL 3 +#define CLK_A0PLL 4 +#define CLK_DISPPLL 5 +#define CLK_CAM0PLL 6 +#define CLK_CAM1PLL 7 + +#define CLK_MIPIMPLL_D3 8 +#define CLK_CAM0PLL_D2 9 +#define CLK_CAM0PLL_D3 10 + +#define CLK_TPU 11 +#define CLK_TPU_FAB 12 +#define CLK_AHB_ROM 13 +#define CLK_DDR_AXI_REG 14 +#define CLK_RTC_25M 15 +#define CLK_SRC_RTC_SYS_0 16 +#define CLK_TEMPSEN 17 +#define CLK_SARADC 18 +#define CLK_EFUSE 19 +#define CLK_APB_EFUSE 20 +#define CLK_DEBUG 21 +#define CLK_AP_DEBUG 22 +#define CLK_XTAL_MISC 23 +#define CLK_AXI4_EMMC 24 +#define CLK_EMMC 25 +#define CLK_EMMC_100K 26 +#define CLK_AXI4_SD0 27 +#define CLK_SD0 28 +#define CLK_SD0_100K 29 +#define CLK_AXI4_SD1 30 +#define CLK_SD1 31 +#define CLK_SD1_100K 32 +#define CLK_SPI_NAND 33 +#define CLK_ETH0_500M 34 +#define CLK_AXI4_ETH0 35 +#define CLK_ETH1_500M 36 +#define CLK_AXI4_ETH1 37 +#define CLK_APB_GPIO 38 +#define CLK_APB_GPIO_INTR 39 +#define CLK_GPIO_DB 40 +#define CLK_AHB_SF 41 +#define CLK_AHB_SF1 42 +#define CLK_A24M 43 +#define CLK_AUDSRC 44 +#define CLK_APB_AUDSRC 45 +#define CLK_SDMA_AXI 46 +#define CLK_SDMA_AUD0 47 +#define CLK_SDMA_AUD1 48 +#define CLK_SDMA_AUD2 49 +#define CLK_SDMA_AUD3 50 +#define CLK_I2C 51 +#define CLK_APB_I2C 52 +#define CLK_APB_I2C0 53 +#define CLK_APB_I2C1 54 +#define CLK_APB_I2C2 55 +#define CLK_APB_I2C3 56 +#define CLK_APB_I2C4 57 +#define CLK_APB_WDT 58 +#define CLK_PWM_SRC 59 +#define CLK_PWM 60 +#define CLK_SPI 61 +#define CLK_APB_SPI0 62 +#define CLK_APB_SPI1 63 +#define CLK_APB_SPI2 64 +#define CLK_APB_SPI3 65 +#define CLK_1M 66 +#define CLK_CAM0_200 67 +#define CLK_PM 68 +#define CLK_TIMER0 69 +#define CLK_TIMER1 70 +#define CLK_TIMER2 71 +#define CLK_TIMER3 72 +#define CLK_TIMER4 73 +#define CLK_TIMER5 74 +#define CLK_TIMER6 75 +#define CLK_TIMER7 76 +#define CLK_UART0 77 +#define CLK_APB_UART0 78 +#define CLK_UART1 79 +#define CLK_APB_UART1 80 +#define CLK_UART2 81 +#define CLK_APB_UART2 82 +#define CLK_UART3 83 +#define CLK_APB_UART3 84 +#define CLK_UART4 85 +#define CLK_APB_UART4 86 +#define CLK_APB_I2S0 87 +#define CLK_APB_I2S1 88 +#define CLK_APB_I2S2 89 +#define CLK_APB_I2S3 90 +#define CLK_AXI4_USB 91 +#define CLK_APB_USB 92 +#define CLK_USB_125M 93 +#define CLK_USB_33K 94 +#define CLK_USB_12M 95 +#define CLK_AXI4 96 +#define CLK_AXI6 97 +#define CLK_DSI_ESC 98 +#define CLK_AXI_VIP 99 +#define CLK_SRC_VIP_SYS_0 100 +#define CLK_SRC_VIP_SYS_1 101 +#define CLK_SRC_VIP_SYS_2 102 +#define CLK_SRC_VIP_SYS_3 103 +#define CLK_SRC_VIP_SYS_4 104 +#define CLK_CSI_BE_VIP 105 +#define CLK_CSI_MAC0_VIP 106 +#define CLK_CSI_MAC1_VIP 107 +#define CLK_CSI_MAC2_VIP 108 +#define CLK_CSI0_RX_VIP 109 +#define CLK_CSI1_RX_VIP 110 +#define CLK_ISP_TOP_VIP 111 +#define CLK_IMG_D_VIP 112 +#define CLK_IMG_V_VIP 113 +#define CLK_SC_TOP_VIP 114 +#define CLK_SC_D_VIP 115 +#define CLK_SC_V1_VIP 116 +#define CLK_SC_V2_VIP 117 +#define CLK_SC_V3_VIP 118 +#define CLK_DWA_VIP 119 +#define CLK_BT_VIP 120 +#define CLK_DISP_VIP 121 +#define CLK_DSI_MAC_VIP 122 +#define CLK_LVDS0_VIP 123 +#define CLK_LVDS1_VIP 124 +#define CLK_PAD_VI_VIP 125 +#define CLK_PAD_VI1_VIP 126 +#define CLK_PAD_VI2_VIP 127 +#define CLK_CFG_REG_VIP 128 +#define CLK_VIP_IP0 129 +#define CLK_VIP_IP1 130 +#define CLK_VIP_IP2 131 +#define CLK_VIP_IP3 132 +#define CLK_IVE_VIP 133 +#define CLK_RAW_VIP 134 +#define CLK_OSDC_VIP 135 +#define CLK_CAM0_VIP 136 +#define CLK_AXI_VIDEO_CODEC 137 +#define CLK_VC_SRC0 138 +#define CLK_VC_SRC1 139 +#define CLK_VC_SRC2 140 +#define CLK_H264C 141 +#define CLK_APB_H264C 142 +#define CLK_H265C 143 +#define CLK_APB_H265C 144 +#define CLK_JPEG 145 +#define CLK_APB_JPEG 146 +#define CLK_CAM0 147 +#define CLK_CAM1 148 +#define CLK_WGN 149 +#define CLK_WGN0 150 +#define CLK_WGN1 151 +#define CLK_WGN2 152 +#define CLK_KEYSCAN 153 +#define CLK_CFG_REG_VC 154 +#define CLK_C906_0 155 +#define CLK_C906_1 156 +#define CLK_A53 157 +#define CLK_CPU_AXI0 158 +#define CLK_CPU_GIC 159 +#define CLK_XTAL_AP 160 + +// Only for CV181x +#define CLK_DISP_SRC_VIP 161 + +#endif /* __DT_BINDINGS_SOPHGO_CV1800_CLK_H__ */ diff --git a/include/dt-bindings/pinctrl/sandbox-pinmux.h b/include/dt-bindings/pinctrl/sandbox-pinmux.h index 891af072e52..21c5a1762ab 100644 --- a/include/dt-bindings/pinctrl/sandbox-pinmux.h +++ b/include/dt-bindings/pinctrl/sandbox-pinmux.h @@ -13,6 +13,7 @@ #define SANDBOX_PINMUX_GPIO 4 #define SANDBOX_PINMUX_CS 5 #define SANDBOX_PINMUX_PWM 6 +#define SANDBOX_PINMUX_ONEWIRE 7 #define SANDBOX_PINMUX(pin, func) ((func) << 16 | (pin)) diff --git a/include/dwmmc.h b/include/dwmmc.h index 136a95b8cdb..6edb9e1a59c 100644 --- a/include/dwmmc.h +++ b/include/dwmmc.h @@ -15,170 +15,205 @@ #define DWMCI_CTRL 0x000 #define DWMCI_PWREN 0x004 #define DWMCI_CLKDIV 0x008 -#define DWMCI_CLKSRC 0x00C +#define DWMCI_CLKSRC 0x00c #define DWMCI_CLKENA 0x010 #define DWMCI_TMOUT 0x014 #define DWMCI_CTYPE 0x018 -#define DWMCI_BLKSIZ 0x01C +#define DWMCI_BLKSIZ 0x01c #define DWMCI_BYTCNT 0x020 #define DWMCI_INTMASK 0x024 #define DWMCI_CMDARG 0x028 -#define DWMCI_CMD 0x02C +#define DWMCI_CMD 0x02c #define DWMCI_RESP0 0x030 #define DWMCI_RESP1 0x034 #define DWMCI_RESP2 0x038 -#define DWMCI_RESP3 0x03C +#define DWMCI_RESP3 0x03c #define DWMCI_MINTSTS 0x040 #define DWMCI_RINTSTS 0x044 #define DWMCI_STATUS 0x048 -#define DWMCI_FIFOTH 0x04C +#define DWMCI_FIFOTH 0x04c #define DWMCI_CDETECT 0x050 #define DWMCI_WRTPRT 0x054 #define DWMCI_GPIO 0x058 -#define DWMCI_TCMCNT 0x05C +#define DWMCI_TCMCNT 0x05c #define DWMCI_TBBCNT 0x060 #define DWMCI_DEBNCE 0x064 #define DWMCI_USRID 0x068 -#define DWMCI_VERID 0x06C +#define DWMCI_VERID 0x06c #define DWMCI_HCON 0x070 #define DWMCI_UHS_REG 0x074 #define DWMCI_BMOD 0x080 #define DWMCI_PLDMND 0x084 +#define DWMCI_DATA 0x200 +/* Registers to support IDMAC 32-bit address mode */ #define DWMCI_DBADDR 0x088 -#define DWMCI_IDSTS 0x08C +#define DWMCI_IDSTS 0x08c #define DWMCI_IDINTEN 0x090 #define DWMCI_DSCADDR 0x094 #define DWMCI_BUFADDR 0x098 -#define DWMCI_DATA 0x200 +/* Registers to support IDMAC 64-bit address mode */ +#define DWMCI_DBADDRL 0x088 +#define DWMCI_DBADDRU 0x08c +#define DWMCI_IDSTS64 0x090 +#define DWMCI_IDINTEN64 0x094 +#define DWMCI_DSCADDRL 0x098 +#define DWMCI_DSCADDRU 0x09c +#define DWMCI_BUFADDRL 0x0a0 +#define DWMCI_BUFADDRU 0x0a4 /* Interrupt Mask register */ #define DWMCI_INTMSK_ALL 0xffffffff -#define DWMCI_INTMSK_RE (1 << 1) -#define DWMCI_INTMSK_CDONE (1 << 2) -#define DWMCI_INTMSK_DTO (1 << 3) -#define DWMCI_INTMSK_TXDR (1 << 4) -#define DWMCI_INTMSK_RXDR (1 << 5) -#define DWMCI_INTMSK_RCRC (1 << 6) -#define DWMCI_INTMSK_DCRC (1 << 7) -#define DWMCI_INTMSK_RTO (1 << 8) -#define DWMCI_INTMSK_DRTO (1 << 9) -#define DWMCI_INTMSK_HTO (1 << 10) -#define DWMCI_INTMSK_FRUN (1 << 11) -#define DWMCI_INTMSK_HLE (1 << 12) -#define DWMCI_INTMSK_SBE (1 << 13) -#define DWMCI_INTMSK_ACD (1 << 14) -#define DWMCI_INTMSK_EBE (1 << 15) - -/* Raw interrupt Regsiter */ -#define DWMCI_DATA_ERR (DWMCI_INTMSK_EBE | DWMCI_INTMSK_SBE | DWMCI_INTMSK_HLE |\ - DWMCI_INTMSK_FRUN | DWMCI_INTMSK_EBE | DWMCI_INTMSK_DCRC) -#define DWMCI_DATA_TOUT (DWMCI_INTMSK_HTO | DWMCI_INTMSK_DRTO) +#define DWMCI_INTMSK_RE BIT(1) +#define DWMCI_INTMSK_CDONE BIT(2) +#define DWMCI_INTMSK_DTO BIT(3) +#define DWMCI_INTMSK_TXDR BIT(4) +#define DWMCI_INTMSK_RXDR BIT(5) +#define DWMCI_INTMSK_RCRC BIT(6) +#define DWMCI_INTMSK_DCRC BIT(7) +#define DWMCI_INTMSK_RTO BIT(8) +#define DWMCI_INTMSK_DRTO BIT(9) +#define DWMCI_INTMSK_HTO BIT(10) +#define DWMCI_INTMSK_FRUN BIT(11) +#define DWMCI_INTMSK_HLE BIT(12) +#define DWMCI_INTMSK_SBE BIT(13) +#define DWMCI_INTMSK_ACD BIT(14) +#define DWMCI_INTMSK_EBE BIT(15) + +/* Raw interrupt register */ +#define DWMCI_DATA_ERR (DWMCI_INTMSK_EBE | DWMCI_INTMSK_SBE | \ + DWMCI_INTMSK_HLE | DWMCI_INTMSK_FRUN | \ + DWMCI_INTMSK_EBE | DWMCI_INTMSK_DCRC) +#define DWMCI_DATA_TOUT (DWMCI_INTMSK_HTO | DWMCI_INTMSK_DRTO) + /* CTRL register */ -#define DWMCI_CTRL_RESET (1 << 0) -#define DWMCI_CTRL_FIFO_RESET (1 << 1) -#define DWMCI_CTRL_DMA_RESET (1 << 2) -#define DWMCI_DMA_EN (1 << 5) -#define DWMCI_CTRL_SEND_AS_CCSD (1 << 10) -#define DWMCI_IDMAC_EN (1 << 25) +#define DWMCI_CTRL_RESET BIT(0) +#define DWMCI_CTRL_FIFO_RESET BIT(1) +#define DWMCI_CTRL_DMA_RESET BIT(2) +#define DWMCI_DMA_EN BIT(5) +#define DWMCI_CTRL_SEND_AS_CCSD BIT(10) +#define DWMCI_IDMAC_EN BIT(25) #define DWMCI_RESET_ALL (DWMCI_CTRL_RESET | DWMCI_CTRL_FIFO_RESET |\ DWMCI_CTRL_DMA_RESET) /* CMD register */ -#define DWMCI_CMD_RESP_EXP (1 << 6) -#define DWMCI_CMD_RESP_LENGTH (1 << 7) -#define DWMCI_CMD_CHECK_CRC (1 << 8) -#define DWMCI_CMD_DATA_EXP (1 << 9) -#define DWMCI_CMD_RW (1 << 10) -#define DWMCI_CMD_SEND_STOP (1 << 12) -#define DWMCI_CMD_ABORT_STOP (1 << 14) -#define DWMCI_CMD_PRV_DAT_WAIT (1 << 13) -#define DWMCI_CMD_UPD_CLK (1 << 21) -#define DWMCI_CMD_USE_HOLD_REG (1 << 29) -#define DWMCI_CMD_START (1 << 31) +#define DWMCI_CMD_RESP_EXP BIT(6) +#define DWMCI_CMD_RESP_LENGTH BIT(7) +#define DWMCI_CMD_CHECK_CRC BIT(8) +#define DWMCI_CMD_DATA_EXP BIT(9) +#define DWMCI_CMD_RW BIT(10) +#define DWMCI_CMD_SEND_STOP BIT(12) +#define DWMCI_CMD_ABORT_STOP BIT(14) +#define DWMCI_CMD_PRV_DAT_WAIT BIT(13) +#define DWMCI_CMD_UPD_CLK BIT(21) +#define DWMCI_CMD_USE_HOLD_REG BIT(29) +#define DWMCI_CMD_START BIT(31) /* CLKENA register */ -#define DWMCI_CLKEN_ENABLE (1 << 0) -#define DWMCI_CLKEN_LOW_PWR (1 << 16) +#define DWMCI_CLKEN_ENABLE BIT(0) +#define DWMCI_CLKEN_LOW_PWR BIT(16) -/* Card-type registe */ +/* Card type register */ #define DWMCI_CTYPE_1BIT 0 -#define DWMCI_CTYPE_4BIT (1 << 0) -#define DWMCI_CTYPE_8BIT (1 << 16) +#define DWMCI_CTYPE_4BIT BIT(0) +#define DWMCI_CTYPE_8BIT BIT(16) -/* Status Register */ -#define DWMCI_FIFO_EMPTY (1 << 2) -#define DWMCI_FIFO_FULL (1 << 3) -#define DWMCI_BUSY (1 << 9) +/* Status register */ +#define DWMCI_FIFO_EMPTY BIT(2) +#define DWMCI_FIFO_FULL BIT(3) +#define DWMCI_BUSY BIT(9) #define DWMCI_FIFO_MASK 0x1fff #define DWMCI_FIFO_SHIFT 17 -/* FIFOTH Register */ +/* FIFOTH register */ #define MSIZE(x) ((x) << 28) #define RX_WMARK(x) ((x) << 16) #define TX_WMARK(x) (x) #define RX_WMARK_SHIFT 16 #define RX_WMARK_MASK (0xfff << RX_WMARK_SHIFT) -#define DWMCI_IDMAC_OWN (1 << 31) -#define DWMCI_IDMAC_CH (1 << 4) -#define DWMCI_IDMAC_FS (1 << 3) -#define DWMCI_IDMAC_LD (1 << 2) +#define DWMCI_IDMAC_OWN BIT(31) +#define DWMCI_IDMAC_CH BIT(4) +#define DWMCI_IDMAC_FS BIT(3) +#define DWMCI_IDMAC_LD BIT(2) -/* Bus Mode Register */ -#define DWMCI_BMOD_IDMAC_RESET (1 << 0) -#define DWMCI_BMOD_IDMAC_FB (1 << 1) -#define DWMCI_BMOD_IDMAC_EN (1 << 7) +/* Bus Mode register */ +#define DWMCI_BMOD_IDMAC_RESET BIT(0) +#define DWMCI_BMOD_IDMAC_FB BIT(1) +#define DWMCI_BMOD_IDMAC_EN BIT(7) /* UHS register */ -#define DWMCI_DDR_MODE (1 << 16) +#define DWMCI_DDR_MODE BIT(16) /* Internal IDMAC interrupt defines */ -#define DWMCI_IDINTEN_RI BIT(1) -#define DWMCI_IDINTEN_TI BIT(0) - -#define DWMCI_IDINTEN_MASK (DWMCI_IDINTEN_TI | \ - DWMCI_IDINTEN_RI) +#define DWMCI_IDINTEN_RI BIT(1) +#define DWMCI_IDINTEN_TI BIT(0) +#define DWMCI_IDINTEN_MASK (DWMCI_IDINTEN_TI | DWMCI_IDINTEN_RI) -/* quirks */ -#define DWMCI_QUIRK_DISABLE_SMU (1 << 0) +/** + * struct dwmci_idmac_regs - Offsets of IDMAC registers + * + * @dbaddrl: Descriptor base address, lower 32 bits + * @dbaddru: Descriptor base address, upper 32 bits + * @idsts: Internal DMA status + * @idinten: Internal DMA interrupt enable + * @dscaddrl: IDMAC descriptor address, lower 32 bits + * @dscaddru: IDMAC descriptor address, upper 32 bits + * @bufaddrl: Current data buffer address, lower 32 bits + * @bufaddru: Current data buffer address, upper 32 bits + */ +struct dwmci_idmac_regs { + u32 dbaddrl; + u32 dbaddru; + u32 idsts; + u32 idinten; + u32 dscaddrl; + u32 dscaddru; + u32 bufaddrl; + u32 bufaddru; +}; /** * struct dwmci_host - Information about a designware MMC host * * @name: Device name * @ioaddr: Base I/O address of controller - * @quirks: Quick flags - see DWMCI_QUIRK_... * @caps: Capabilities - see MMC_MODE_... + * @clock: Current clock frequency (after internal divider), Hz * @bus_hz: Bus speed in Hz, if @get_mmc_clk() is NULL - * @div: Arbitrary clock divider value for use by controller * @dev_index: Arbitrary device index for use by controller * @dev_id: Arbitrary device ID for use by controller * @buswidth: Bus width in bits (8 or 4) - * @fifoth_val: Value for FIFOTH register (or 0 to leave unset) + * @fifo_depth: Depth of FIFO, bytes (or 0 for automatic detection) * @mmc: Pointer to generic MMC structure for this device * @priv: Private pointer for use by controller + * @clksel: (Optional) Platform function to run when speed/width is changed + * @board_init: (Optional) Platform function to run on init + * @cfg: Internal MMC configuration, for !CONFIG_BLK cases + * @fifo_mode: Use FIFO mode (not DMA) to read and write data + * @dma_64bit_address: Whether DMA supports 64-bit address mode or not + * @regs: Registers that can vary for different DW MMC block versions */ struct dwmci_host { const char *name; void *ioaddr; - unsigned int quirks; unsigned int caps; - unsigned int version; unsigned int clock; unsigned int bus_hz; - unsigned int div; int dev_index; int dev_id; int buswidth; - u32 fifoth_val; + u32 fifo_depth; struct mmc *mmc; void *priv; int (*clksel)(struct dwmci_host *host); void (*board_init)(struct dwmci_host *host); - /** - * Get / set a particular MMC clock frequency + * @get_mmc_clk: (Optional) Platform function to get/set a particular + * MMC clock frequency + * + * @host: DWMMC host + * @freq: Frequency the host is trying to achieve * * This is used to request the current clock frequency of the clock * that drives the DWMMC peripheral. The caller will then use this @@ -186,26 +221,18 @@ struct dwmci_host { * required MMC bus clock frequency. If you want to handle the * clock external to DWMMC, use @freq to select the frequency and * return that value too. Then DWMMC will put itself in bypass mode. - * - * @host: DWMMC host - * @freq: Frequency the host is trying to achieve */ unsigned int (*get_mmc_clk)(struct dwmci_host *host, uint freq); + #ifndef CONFIG_BLK struct mmc_config cfg; #endif - /* use fifo mode to read and write data */ bool fifo_mode; + bool dma_64bit_address; + const struct dwmci_idmac_regs *regs; }; -struct dwmci_idmac { - u32 flags; - u32 cnt; - u32 addr; - u32 next_addr; -} __aligned(ARCH_DMA_MINALIGN); - static inline void dwmci_writel(struct dwmci_host *host, int reg, u32 val) { writel(val, host->ioaddr + reg); @@ -220,6 +247,7 @@ static inline void dwmci_writeb(struct dwmci_host *host, int reg, u8 val) { writeb(val, host->ioaddr + reg); } + static inline u32 dwmci_readl(struct dwmci_host *host, int reg) { return readl(host->ioaddr + reg); @@ -236,8 +264,13 @@ static inline u8 dwmci_readb(struct dwmci_host *host, int reg) } #ifdef CONFIG_BLK + /** * dwmci_setup_cfg() - Set up the configuration for DWMMC + * @cfg: Configuration structure to fill in (generally &plat->mmc) + * @host: DWMMC host + * @max_clk: Maximum supported clock speed in Hz (e.g. 150000000) + * @min_clk: Minimum supported clock speed in Hz (e.g. 400000) * * This is used to set up a DWMMC device when you are using CONFIG_BLK. * @@ -262,44 +295,41 @@ static inline u8 dwmci_readb(struct dwmci_host *host, int reg) * struct rockchip_mmc_plat *plat = dev_get_plat(dev); * * See rockchip_dw_mmc.c for an example. - * - * @cfg: Configuration structure to fill in (generally &plat->mmc) - * @host: DWMMC host - * @max_clk: Maximum supported clock speed in HZ (e.g. 150000000) - * @min_clk: Minimum supported clock speed in HZ (e.g. 400000) */ void dwmci_setup_cfg(struct mmc_config *cfg, struct dwmci_host *host, - u32 max_clk, u32 min_clk); + u32 max_clk, u32 min_clk); /** * dwmci_bind() - Set up a new MMC block device + * @dev: Device to set up + * @mmc: Pointer to mmc structure (normally &plat->mmc) + * @cfg: Empty configuration structure (generally &plat->cfg). This is + * normally all zeroes at this point. The only purpose of passing + * this in is to set mmc->cfg to it. * * This is used to set up a DWMMC block device when you are using CONFIG_BLK. * It should be called from your driver's bind() method. * * See rockchip_dw_mmc.c for an example. * - * @dev: Device to set up - * @mmc: Pointer to mmc structure (normally &plat->mmc) - * @cfg: Empty configuration structure (generally &plat->cfg). This is - * normally all zeroes at this point. The only purpose of passing - * this in is to set mmc->cfg to it. * Return: 0 if OK, -ve if the block device could not be created */ int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg); #else + /** * add_dwmci() - Add a new DWMMC interface + * @host: DWMMC host structure + * @max_clk: Maximum supported clock speed in Hz (e.g. 150000000) + * @min_clk: Minimum supported clock speed in Hz (e.g. 400000) * * This is used when you are not using CONFIG_BLK. Convert your driver over! * - * @host: DWMMC host structure - * @max_clk: Maximum supported clock speed in HZ (e.g. 150000000) - * @min_clk: Minimum supported clock speed in HZ (e.g. 400000) * Return: 0 if OK, -ve on error */ int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk); + #endif /* !CONFIG_BLK */ #ifdef CONFIG_DM_MMC diff --git a/include/efi.h b/include/efi.h index d5af2139946..84640cf7b25 100644 --- a/include/efi.h +++ b/include/efi.h @@ -74,7 +74,7 @@ struct efi_device_path { * struct { u32 a; u16; b; u16 c; u8 d[8]; }; which is 4-byte * aligned. */ -typedef struct { +typedef struct efi_guid { u8 b[16]; } efi_guid_t __attribute__((aligned(4))); diff --git a/include/env/phytec/k3_mmc.env b/include/env/phytec/k3_mmc.env index 3d3595ceb7e..ad8d3a8b764 100644 --- a/include/env/phytec/k3_mmc.env +++ b/include/env/phytec/k3_mmc.env @@ -7,15 +7,17 @@ /* Logic for TI K3 based SoCs to boot from a MMC device. */ #include <env/phytec/overlays.env> +#include <env/phytec/rauc.env> mmcargs=setenv bootargs console=${console} earlycon=${earlycon} - root=/dev/mmcblk${mmcdev}p${mmcroot} rootwait rw -loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} Image -loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile} -mmcboot=run mmcargs; + root=/dev/mmcblk${mmcdev}p${mmcroot} ${raucargs} rootwait rw +mmcloadimage=load mmc ${mmcdev}:${mmcpart} ${kernel_addr_r} Image +mmcloadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile} +mmcboot=if test ${doraucboot} = 1; then run raucinit; fi; + run mmcargs; mmc dev ${mmcdev}; mmc rescan; - run loadimage; - run loadfdt; + run mmcloadimage; + run mmcloadfdt; run mmc_apply_overlays; - booti ${loadaddr} - ${fdt_addr_r} + booti ${kernel_addr_r} - ${fdt_addr_r} diff --git a/include/env/phytec/k3_net.env b/include/env/phytec/k3_net.env new file mode 100644 index 00000000000..377e406688d --- /dev/null +++ b/include/env/phytec/k3_net.env @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2024 PHYTEC Messtechnik GmbH + * Author: Daniel Schultz <d.schultz@phytec.de> + */ + +/* Logic for TI K3 based SoCs to boot via network. */ + +#include <env/phytec/overlays.env> + +netargs=setenv bootargs console=${console} root=/dev/nfs ip=dhcp rw + nfsroot=${serverip}:${nfsroot},vers=4,tcp +netloadimage=${net_fetch_cmd} ${kernel_addr_r} ${serverip}:/Image +netloadfdt=${net_fetch_cmd} ${fdt_addr_r} ${serverip}:/${fdtfile} +netboot=run netargs; + setenv autoload no; + dhcp; + run netloadimage; + run netloadfdt; + run net_apply_overlays; + run net_apply_extensions; + booti ${kernel_addr_r} - ${fdt_addr_r} diff --git a/include/env/phytec/k3_spi.env b/include/env/phytec/k3_spi.env new file mode 100644 index 00000000000..97d3a157058 --- /dev/null +++ b/include/env/phytec/k3_spi.env @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2024 PHYTEC Messtechnik GmbH + * Author: Daniel Schultz <d.schultz@phytec.de> + */ + +/* Logic for TI K3 based SoCs to boot from an OSPI/QSPI NOR flash. */ + +spiargs=setenv bootargs console=${console} earlycon=${earlycon} +spiloadimage=sf read ${kernel_addr_r} ${spi_image_addr} ${size_kern} +spiloadfdt=sf read ${fdt_addr_r} ${spi_fdt_addr} ${size_fdt} +spiloadramdisk=sf read ${ramdisk_addr_r} ${spi_ramdisk_addr} ${size_fs} +spiboot=run spiargs; + sf probe; + run spiloadimage; + run spiloadfdt; + run spiloadramdisk; + booti ${kernel_addr_r} ${ramdisk_addr_r}:0x${size_fs} ${fdt_addr_r} diff --git a/include/env_default.h b/include/env_default.h index 076ffdd44e9..aa3dd40f3fa 100644 --- a/include/env_default.h +++ b/include/env_default.h @@ -82,9 +82,6 @@ const char default_environment[] = { #ifdef CONFIG_SYS_LOAD_ADDR "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR)"\0" #endif -#if defined(CONFIG_PCI_BOOTDELAY) && (CONFIG_PCI_BOOTDELAY > 0) - "pcidelay=" __stringify(CONFIG_PCI_BOOTDELAY)"\0" -#endif #ifdef CONFIG_ENV_VARS_UBOOT_CONFIG "arch=" CONFIG_SYS_ARCH "\0" #ifdef CONFIG_SYS_CPU diff --git a/include/env_internal.h b/include/env_internal.h index 0a267e35592..c1c0727e4d0 100644 --- a/include/env_internal.h +++ b/include/env_internal.h @@ -100,6 +100,7 @@ extern const char default_environment[]; #include <env_flags.h> #include <search.h> +/* this is stored as bits in gd->env_has_init so is limited to 16 entries */ enum env_location { ENVL_UNKNOWN, ENVL_EEPROM, diff --git a/include/ext4fs.h b/include/ext4fs.h index d96edfd0576..41f9eb8bd33 100644 --- a/include/ext4fs.h +++ b/include/ext4fs.h @@ -34,12 +34,63 @@ struct disk_partition; #define EXT4_TOPDIR_FL 0x00020000 /* Top of directory hierarchies*/ #define EXT4_EXTENTS_FL 0x00080000 /* Inode uses extents */ #define EXT4_EXT_MAGIC 0xf30a -#define EXT4_FEATURE_RO_COMPAT_GDT_CSUM 0x0010 + +#define EXT4_FEATURE_RO_COMPAT_SPARSE_SUPER 0x0001 +#define EXT4_FEATURE_RO_COMPAT_LARGE_FILE 0x0002 +#define EXT4_FEATURE_RO_COMPAT_BTREE_DIR 0x0004 +#define EXT4_FEATURE_RO_COMPAT_HUGE_FILE 0x0008 +#define EXT4_FEATURE_RO_COMPAT_GDT_CSUM 0x0010 +#define EXT4_FEATURE_RO_COMPAT_DIR_NLINK 0x0020 +#define EXT4_FEATURE_RO_COMPAT_EXTRA_ISIZE 0x0040 +#define EXT4_FEATURE_RO_COMPAT_QUOTA 0x0100 +#define EXT4_FEATURE_RO_COMPAT_BIGALLOC 0x0200 #define EXT4_FEATURE_RO_COMPAT_METADATA_CSUM 0x0400 + +#define EXT4_FEATURE_INCOMPAT_FILETYPE 0x0002 +#define EXT4_FEATURE_INCOMPAT_RECOVER 0x0004 #define EXT4_FEATURE_INCOMPAT_EXTENTS 0x0040 #define EXT4_FEATURE_INCOMPAT_64BIT 0x0080 +#define EXT4_FEATURE_INCOMPAT_MMP 0x0100 +#define EXT4_FEATURE_INCOMPAT_FLEX_BG 0x0200 +#define EXT4_FEATURE_INCOMPAT_CSUM_SEED 0x2000 +#define EXT4_FEATURE_INCOMPAT_ENCRYPT 0x10000 + #define EXT4_INDIRECT_BLOCKS 12 +/* + * Incompat features supported by this implementation. + */ +#define EXT4_FEATURE_INCOMPAT_SUPP (EXT4_FEATURE_INCOMPAT_FILETYPE | \ + EXT4_FEATURE_INCOMPAT_RECOVER | \ + EXT4_FEATURE_INCOMPAT_EXTENTS | \ + EXT4_FEATURE_INCOMPAT_64BIT | \ + EXT4_FEATURE_INCOMPAT_FLEX_BG) + +/* + * Incompat features supported by this implementation only in a lazy + * way, good enough for reading files. + * + * - Multi mount protection (mmp) is not supported, but for read-only + * we get away with it. + * - Same for metadata_csum_seed and metadata_csum. + * - The implementation has also no clue about fscrypt, but it can read + * unencrypted files. Reading encrypted files will read garbage. + */ +#define EXT4_FEATURE_INCOMPAT_SUPP_LAZY_RO (EXT4_FEATURE_INCOMPAT_MMP | \ + EXT4_FEATURE_INCOMPAT_CSUM_SEED | \ + EXT4_FEATURE_INCOMPAT_ENCRYPT) + +/* + * Read-only compat features we support. + * If unknown ro compat features are detected, writing to the fs is denied. + */ +#define EXT4_FEATURE_RO_COMPAT_SUPP (EXT4_FEATURE_RO_COMPAT_SPARSE_SUPER | \ + EXT4_FEATURE_RO_COMPAT_LARGE_FILE | \ + EXT4_FEATURE_RO_COMPAT_HUGE_FILE | \ + EXT4_FEATURE_RO_COMPAT_GDT_CSUM | \ + EXT4_FEATURE_RO_COMPAT_DIR_NLINK | \ + EXT4_FEATURE_RO_COMPAT_EXTRA_ISIZE) + #define EXT4_BG_INODE_UNINIT 0x0001 #define EXT4_BG_BLOCK_UNINIT 0x0002 #define EXT4_BG_INODE_ZEROED 0x0004 diff --git a/include/fwu.h b/include/fwu.h index 77ec65e6180..c317613eaaa 100644 --- a/include/fwu.h +++ b/include/fwu.h @@ -10,7 +10,7 @@ #include <efi.h> #include <fwu_mdata.h> #include <mtd.h> -#include <uuid.h> +#include <u-boot/uuid.h> #include <linux/types.h> diff --git a/include/generic-phy.h b/include/generic-phy.h index eaab7491660..ba3321f4849 100644 --- a/include/generic-phy.h +++ b/include/generic-phy.h @@ -415,10 +415,13 @@ int generic_phy_power_off_bulk(struct phy_bulk *bulk); * @dev: The consumer device. * @phy: A pointer to the PHY port * @index: The index in the list of available PHYs + * @mode: PHY mode + * @submode: PHY submode * * Return: 0 if OK, or negative error code. */ -int generic_setup_phy(struct udevice *dev, struct phy *phy, int index); +int generic_setup_phy(struct udevice *dev, struct phy *phy, int index, + enum phy_mode mode, int submode); /** * generic_shutdown_phy() - Power off and de-initialize phy. @@ -509,7 +512,8 @@ static inline int generic_phy_power_off_bulk(struct phy_bulk *bulk) return 0; } -static inline int generic_setup_phy(struct udevice *dev, struct phy *phy, int index) +static inline int generic_setup_phy(struct udevice *dev, struct phy *phy, int index, + enum phy_mode mode, int submode) { return 0; } diff --git a/include/handoff.h b/include/handoff.h index c0ae7b19a75..0072ea832f8 100644 --- a/include/handoff.h +++ b/include/handoff.h @@ -32,6 +32,13 @@ void handoff_load_dram_size(struct spl_handoff *ho); void handoff_load_dram_banks(struct spl_handoff *ho); /** + * handoff_get() - Get the SPL handoff information + * + * Return: Pointer to SPL handoff if received, else NULL + */ +struct spl_handoff *handoff_get(void); + +/** * handoff_arch_save() - Save arch-specific info into the handoff area * * This is defined to an empty function by default, but arch-specific code can diff --git a/include/i2c.h b/include/i2c.h index 4e59009cd93..91917f54be9 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -645,20 +645,8 @@ void i2c_early_init_f(void); */ #define I2C_RXTX_LEN 128 /* maximum tx/rx buffer length */ -#if !defined(CFG_SYS_I2C_MAX_HOPS) /* no muxes used bus = i2c adapters */ -#define CFG_SYS_I2C_DIRECT_BUS 1 -#define CFG_SYS_I2C_MAX_HOPS 0 #define CFG_SYS_NUM_I2C_BUSES ll_entry_count(struct i2c_adapter, i2c) -#else -/* we use i2c muxes */ -#undef CFG_SYS_I2C_DIRECT_BUS -#endif - -/* define the I2C bus number for RTC and DTT if not already done */ -#if !defined(CFG_SYS_RTC_BUS_NUM) -#define CFG_SYS_RTC_BUS_NUM 0 -#endif struct i2c_adapter { void (*init)(struct i2c_adapter *adap, int speed, @@ -703,48 +691,13 @@ struct i2c_adapter { struct i2c_adapter *i2c_get_adapter(int index); -#ifndef CFG_SYS_I2C_DIRECT_BUS -struct i2c_mux { - int id; - char name[16]; -}; - -struct i2c_next_hop { - struct i2c_mux mux; - uint8_t chip; - uint8_t channel; -}; - -struct i2c_bus_hose { - int adapter; - struct i2c_next_hop next_hop[CFG_SYS_I2C_MAX_HOPS]; -}; -#define I2C_NULL_HOP {{-1, ""}, 0, 0} -extern struct i2c_bus_hose i2c_bus[]; - -#define I2C_ADAPTER(bus) i2c_bus[bus].adapter -#else #define I2C_ADAPTER(bus) bus -#endif #define I2C_BUS gd->cur_i2c_bus #define I2C_ADAP_NR(bus) i2c_get_adapter(I2C_ADAPTER(bus)) #define I2C_ADAP I2C_ADAP_NR(gd->cur_i2c_bus) #define I2C_ADAP_HWNR (I2C_ADAP->hwadapnr) -#ifndef CFG_SYS_I2C_DIRECT_BUS -#define I2C_MUX_PCA9540_ID 1 -#define I2C_MUX_PCA9540 {I2C_MUX_PCA9540_ID, "PCA9540B"} -#define I2C_MUX_PCA9542_ID 2 -#define I2C_MUX_PCA9542 {I2C_MUX_PCA9542_ID, "PCA9542A"} -#define I2C_MUX_PCA9544_ID 3 -#define I2C_MUX_PCA9544 {I2C_MUX_PCA9544_ID, "PCA9544A"} -#define I2C_MUX_PCA9547_ID 4 -#define I2C_MUX_PCA9547 {I2C_MUX_PCA9547_ID, "PCA9547A"} -#define I2C_MUX_PCA9548_ID 5 -#define I2C_MUX_PCA9548 {I2C_MUX_PCA9548_ID, "PCA9548"} -#endif - #ifndef I2C_SOFT_DECLARATIONS # if (defined(CONFIG_AT91RM9200) || \ defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) || \ @@ -938,66 +891,6 @@ int i2c_set_bus_speed(unsigned int); unsigned int i2c_get_bus_speed(void); #endif /* CONFIG_SYS_I2C_LEGACY */ -/* - * only for backwardcompatibility, should go away if we switched - * completely to new multibus support. - */ -#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || defined(CFG_I2C_MULTI_BUS) -# if !defined(CFG_SYS_MAX_I2C_BUS) -# define CFG_SYS_MAX_I2C_BUS 2 -# endif -# define I2C_MULTI_BUS 1 -#else -# define CFG_SYS_MAX_I2C_BUS 1 -# define I2C_MULTI_BUS 0 -#endif - -/* NOTE: These two functions MUST be always_inline to avoid code growth! */ -static inline unsigned int I2C_GET_BUS(void) __attribute__((always_inline)); -static inline unsigned int I2C_GET_BUS(void) -{ - return I2C_MULTI_BUS ? i2c_get_bus_num() : 0; -} - -static inline void I2C_SET_BUS(unsigned int bus) __attribute__((always_inline)); -static inline void I2C_SET_BUS(unsigned int bus) -{ - if (I2C_MULTI_BUS) - i2c_set_bus_num(bus); -} - -/* Multi I2C definitions */ -enum { - I2C_0, I2C_1, I2C_2, I2C_3, I2C_4, I2C_5, I2C_6, I2C_7, - I2C_8, I2C_9, I2C_10, -}; - -/** - * Get FDT values for i2c bus. - * - * @param blob Device tree blbo - * Return: the number of I2C bus - */ -void board_i2c_init(const void *blob); - -/** - * Find the I2C bus number by given a FDT I2C node. - * - * @param blob Device tree blbo - * @param node FDT I2C node to find - * Return: the number of I2C bus (zero based), or -1 on error - */ -int i2c_get_bus_num_fdt(int node); - -/** - * Reset the I2C bus represented by the given a FDT I2C node. - * - * @param blob Device tree blbo - * @param node FDT I2C node to find - * Return: 0 if port was reset, -1 if not found - */ -int i2c_reset_port_fdt(const void *blob, int node); - #endif /* !CONFIG_DM_I2C */ #endif /* _I2C_H_ */ diff --git a/include/image.h b/include/image.h index 2ab17075287..c52fced9b40 100644 --- a/include/image.h +++ b/include/image.h @@ -20,7 +20,6 @@ #include <stdbool.h> /* Define this to avoid #ifdefs later on */ -struct lmb; struct fdt_region; #ifdef USE_HOSTCC @@ -412,18 +411,8 @@ struct bootm_headers { #define BOOTM_STATE_PRE_LOAD 0x00000800 #define BOOTM_STATE_MEASURE 0x00001000 int state; - -#if defined(CONFIG_LMB) && !defined(USE_HOSTCC) - struct lmb lmb; /* for memory mgmt */ -#endif }; -#ifdef CONFIG_LMB -#define images_lmb(_images) (&(_images)->lmb) -#else -#define images_lmb(_images) NULL -#endif - extern struct bootm_headers images; /* @@ -835,13 +824,13 @@ int boot_get_fdt(void *buf, const char *select, uint arch, struct bootm_headers *images, char **of_flat_tree, ulong *of_size); -void boot_fdt_add_mem_rsv_regions(struct lmb *lmb, void *fdt_blob); -int boot_relocate_fdt(struct lmb *lmb, char **of_flat_tree, ulong *of_size); +void boot_fdt_add_mem_rsv_regions(void *fdt_blob); +int boot_relocate_fdt(char **of_flat_tree, ulong *of_size); -int boot_ramdisk_high(struct lmb *lmb, ulong rd_data, ulong rd_len, - ulong *initrd_start, ulong *initrd_end); -int boot_get_cmdline(struct lmb *lmb, ulong *cmd_start, ulong *cmd_end); -int boot_get_kbd(struct lmb *lmb, struct bd_info **kbd); +int boot_ramdisk_high(ulong rd_data, ulong rd_len, ulong *initrd_start, + ulong *initrd_end); +int boot_get_cmdline(ulong *cmd_start, ulong *cmd_end); +int boot_get_kbd(struct bd_info **kbd); /*******************************************************************/ /* Legacy format specific code (prefixed with image_) */ @@ -1029,11 +1018,10 @@ int image_decomp(int comp, ulong load, ulong image_start, int type, * * @images: Images information * @blob: FDT to update - * @lmb: Points to logical memory block structure + * @lmb: Flag indicating use of lmb for reserving FDT memory region * Return: 0 if ok, <0 on failure */ -int image_setup_libfdt(struct bootm_headers *images, void *blob, - struct lmb *lmb); +int image_setup_libfdt(struct bootm_headers *images, void *blob, bool lmb); /** * Set up the FDT to use for booting a kernel diff --git a/include/linux/compiler_types.h b/include/linux/compiler_types.h index 1a3060117f1..8b6ce9c11cd 100644 --- a/include/linux/compiler_types.h +++ b/include/linux/compiler_types.h @@ -71,6 +71,13 @@ extern void __chk_io_ptr(const volatile void __iomem *); #endif /* + * At least gcc 5.1 or clang 8 are needed. + */ +#ifndef COMPILER_HAS_GENERIC_BUILTIN_OVERFLOW +#error Unsupported compiler +#endif + +/* * Some architectures need to provide custom definitions of macros provided * by linux/compiler-*.h, and can do so using asm/compiler.h. We include that * conditionally rather than using an asm-generic wrapper in order to avoid diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index 537c62424a1..2d85b392465 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -247,6 +247,11 @@ enum nand_ecc_algo { * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers */ #define NAND_USE_BOUNCE_BUFFER 0x00100000 +/* + * Whether the NAND chip is a boot medium. Drivers might use this information + * to select ECC algorithms supported by the boot ROM or similar restrictions. + */ +#define NAND_IS_BOOT_MEDIUM 0x00400000 /* * Do not try to tweak the timings at runtime. This is needed when the diff --git a/include/linux/usb/atmel_usba_udc.h b/include/linux/usb/atmel_usba_udc.h index c1c810759c3..37c4f218493 100644 --- a/include/linux/usb/atmel_usba_udc.h +++ b/include/linux/usb/atmel_usba_udc.h @@ -20,6 +20,8 @@ struct usba_platform_data { struct usba_ep_data *ep; }; +#if !CONFIG_IS_ENABLED(DM_USB_GADGET) extern int usba_udc_probe(struct usba_platform_data *pdata); +#endif #endif /* __LINUX_USB_USBA_H */ diff --git a/include/lmb.h b/include/lmb.h index 231b68b27d9..fc2daaa7bfc 100644 --- a/include/lmb.h +++ b/include/lmb.h @@ -3,8 +3,10 @@ #define _LINUX_LMB_H #ifdef __KERNEL__ +#include <alist.h> #include <asm/types.h> #include <asm/u-boot.h> +#include <linux/bitops.h> /* * Logical memory blocks. @@ -18,115 +20,75 @@ * @LMB_NOMAP: don't add to mmu configuration */ enum lmb_flags { - LMB_NONE = 0x0, - LMB_NOMAP = 0x4, + LMB_NONE = 0, + LMB_NOMAP = BIT(1), + LMB_NOOVERWRITE = BIT(2), }; /** - * struct lmb_property - Description of one region. + * struct lmb_region - Description of one region. * * @base: Base address of the region. * @size: Size of the region * @flags: memory region attributes */ -struct lmb_property { +struct lmb_region { phys_addr_t base; phys_size_t size; enum lmb_flags flags; }; -/* - * For regions size management, see LMB configuration in KConfig - * all the #if test are done with CONFIG_LMB_USE_MAX_REGIONS (boolean) - * - * case 1. CONFIG_LMB_USE_MAX_REGIONS is defined (legacy mode) - * => CONFIG_LMB_MAX_REGIONS is used to configure the region size, - * directly in the array lmb_region.region[], with the same - * configuration for memory and reserved regions. +/** + * struct lmb - The LMB structure * - * case 2. CONFIG_LMB_USE_MAX_REGIONS is not defined, the size of each - * region is configurated *independently* with - * => CONFIG_LMB_MEMORY_REGIONS: struct lmb.memory_regions - * => CONFIG_LMB_RESERVED_REGIONS: struct lmb.reserved_regions - * lmb_region.region is only a pointer to the correct buffer, - * initialized in lmb_init(). This configuration is useful to manage - * more reserved memory regions with CONFIG_LMB_RESERVED_REGIONS. + * @free_mem: List of free memory regions + * @used_mem: List of used/reserved memory regions */ +struct lmb { + struct alist free_mem; + struct alist used_mem; +}; /** - * struct lmb_region - Description of a set of region. + * lmb_init() - Initialise the LMB module + * + * Initialise the LMB lists needed for keeping the memory map. There + * are two lists, in form of alloced list data structure. One for the + * available memory, and one for the used memory. Initialise the two + * lists as part of board init. Add memory to the available memory + * list and reserve common areas by adding them to the used memory + * list. * - * @cnt: Number of regions. - * @max: Size of the region array, max value of cnt. - * @region: Array of the region properties + * Return: 0 on success, -ve on error */ -struct lmb_region { - unsigned long cnt; - unsigned long max; -#if IS_ENABLED(CONFIG_LMB_USE_MAX_REGIONS) - struct lmb_property region[CONFIG_LMB_MAX_REGIONS]; -#else - struct lmb_property *region; -#endif -}; +int lmb_init(void); /** - * struct lmb - Logical memory block handle. + * lmb_add_memory() - Add memory range for LMB allocations * - * Clients provide storage for Logical memory block (lmb) handles. - * The content of the structure is managed by the lmb library. - * A lmb struct is initialized by lmb_init() functions. - * The lmb struct is passed to all other lmb APIs. + * Add the entire available memory range to the pool of memory that + * can be used by the LMB module for allocations. * - * @memory: Description of memory regions. - * @reserved: Description of reserved regions. - * @memory_regions: Array of the memory regions (statically allocated) - * @reserved_regions: Array of the reserved regions (statically allocated) + * Return: None */ -struct lmb { - struct lmb_region memory; - struct lmb_region reserved; -#if !IS_ENABLED(CONFIG_LMB_USE_MAX_REGIONS) - struct lmb_property memory_regions[CONFIG_LMB_MEMORY_REGIONS]; - struct lmb_property reserved_regions[CONFIG_LMB_RESERVED_REGIONS]; -#endif -}; +void lmb_add_memory(void); -void lmb_init(struct lmb *lmb); -void lmb_init_and_reserve(struct lmb *lmb, struct bd_info *bd, void *fdt_blob); -void lmb_init_and_reserve_range(struct lmb *lmb, phys_addr_t base, - phys_size_t size, void *fdt_blob); -long lmb_add(struct lmb *lmb, phys_addr_t base, phys_size_t size); -long lmb_reserve(struct lmb *lmb, phys_addr_t base, phys_size_t size); +long lmb_add(phys_addr_t base, phys_size_t size); +long lmb_reserve(phys_addr_t base, phys_size_t size); /** * lmb_reserve_flags - Reserve one region with a specific flags bitfield. * - * @lmb: the logical memory block struct * @base: base address of the memory region * @size: size of the memory region * @flags: flags for the memory region * Return: 0 if OK, > 0 for coalesced region or a negative error code. */ -long lmb_reserve_flags(struct lmb *lmb, phys_addr_t base, - phys_size_t size, enum lmb_flags flags); -phys_addr_t lmb_alloc(struct lmb *lmb, phys_size_t size, ulong align); -phys_addr_t lmb_alloc_base(struct lmb *lmb, phys_size_t size, ulong align, - phys_addr_t max_addr); -phys_addr_t __lmb_alloc_base(struct lmb *lmb, phys_size_t size, ulong align, - phys_addr_t max_addr); -phys_addr_t lmb_alloc_addr(struct lmb *lmb, phys_addr_t base, phys_size_t size); -phys_size_t lmb_get_free_size(struct lmb *lmb, phys_addr_t addr); - -/** - * lmb_is_reserved() - test if address is in reserved region - * - * The function checks if a reserved region comprising @addr exists. - * - * @lmb: the logical memory block struct - * @addr: address to be tested - * Return: 1 if reservation exists, 0 otherwise - */ -int lmb_is_reserved(struct lmb *lmb, phys_addr_t addr); +long lmb_reserve_flags(phys_addr_t base, phys_size_t size, + enum lmb_flags flags); +phys_addr_t lmb_alloc(phys_size_t size, ulong align); +phys_addr_t lmb_alloc_base(phys_size_t size, ulong align, phys_addr_t max_addr); +phys_addr_t lmb_alloc_addr(phys_addr_t base, phys_size_t size); +phys_size_t lmb_get_free_size(phys_addr_t addr); /** * lmb_is_reserved_flags() - test if address is in reserved region with flag bits set @@ -134,21 +96,20 @@ int lmb_is_reserved(struct lmb *lmb, phys_addr_t addr); * The function checks if a reserved region comprising @addr exists which has * all flag bits set which are set in @flags. * - * @lmb: the logical memory block struct * @addr: address to be tested * @flags: bitmap with bits to be tested * Return: 1 if matching reservation exists, 0 otherwise */ -int lmb_is_reserved_flags(struct lmb *lmb, phys_addr_t addr, int flags); +int lmb_is_reserved_flags(phys_addr_t addr, int flags); -long lmb_free(struct lmb *lmb, phys_addr_t base, phys_size_t size); +long lmb_free(phys_addr_t base, phys_size_t size); -void lmb_dump_all(struct lmb *lmb); -void lmb_dump_all_force(struct lmb *lmb); +void lmb_dump_all(void); +void lmb_dump_all_force(void); -void board_lmb_reserve(struct lmb *lmb); -void arch_lmb_reserve(struct lmb *lmb); -void arch_lmb_reserve_generic(struct lmb *lmb, ulong sp, ulong end, ulong align); +struct lmb *lmb_get(void); +int lmb_push(struct lmb *store); +void lmb_pop(struct lmb *store); #endif /* __KERNEL__ */ diff --git a/include/log.h b/include/log.h index fc0d5984472..69dcb339543 100644 --- a/include/log.h +++ b/include/log.h @@ -125,7 +125,7 @@ static inline int log_uc_cat(enum uclass_id id) * @level: Level of log record (indicating its severity) * @file: File name of file where log record was generated * @line: Line number in file where log record was generated - * @func: Function where log record was generated + * @func: Function where log record was generated, NULL if not known * @fmt: printf() format string for log record * @...: Optional parameters, according to the format string @fmt * Return: 0 if log record was emitted, -ve on error @@ -141,7 +141,7 @@ int _log(enum log_category_t cat, enum log_level_t level, const char *file, * @level: Level of log record (indicating its severity) * @file: File name of file where log record was generated * @line: Line number in file where log record was generated - * @func: Function where log record was generated + * @func: Function where log record was generated, NULL if not known * @addr: Starting address to display at start of line * @data: pointer to data buffer * @width: data value width. May be 1, 2, or 4. @@ -193,6 +193,12 @@ int _log_buffer(enum log_category_t cat, enum log_level_t level, #define _LOG_DEBUG 0 #endif +#ifdef CONFIG_LOGF_FUNC +#define _log_func __func__ +#else +#define _log_func NULL +#endif + #if CONFIG_IS_ENABLED(LOG) /* Emit a log record if the level is less that the maximum */ @@ -201,7 +207,7 @@ int _log_buffer(enum log_category_t cat, enum log_level_t level, if (_LOG_DEBUG != 0 || _l <= _LOG_MAX_LEVEL) \ _log((enum log_category_t)(_cat), \ (enum log_level_t)(_l | _LOG_DEBUG), __FILE__, \ - __LINE__, __func__, \ + __LINE__, _log_func, \ pr_fmt(_fmt), ##_args); \ }) @@ -211,7 +217,7 @@ int _log_buffer(enum log_category_t cat, enum log_level_t level, if (_LOG_DEBUG != 0 || _l <= _LOG_MAX_LEVEL) \ _log_buffer((enum log_category_t)(_cat), \ (enum log_level_t)(_l | _LOG_DEBUG), __FILE__, \ - __LINE__, __func__, _addr, _data, \ + __LINE__, _log_func, _addr, _data, \ _width, _count, _linelen); \ }) #else @@ -314,7 +320,7 @@ void __assert_fail(const char *assertion, const char *file, unsigned int line, #define assert_noisy(x) \ ({ bool _val = (x); \ if (!_val) \ - __assert_fail(#x, "?", __LINE__, __func__); \ + __assert_fail(#x, "?", __LINE__, _log_func); \ _val; \ }) diff --git a/include/mmc.h b/include/mmc.h index 155a8e9f420..f508cd15700 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -372,6 +372,32 @@ enum mmc_voltage { #define MMC_TIMING_MMC_HS200 9 #define MMC_TIMING_MMC_HS400 10 +/* emmc PARTITION_CONFIG BOOT_PARTITION_ENABLE values */ +enum emmc_boot_part { + EMMC_BOOT_PART_DEFAULT = 0, + EMMC_BOOT_PART_BOOT1 = 1, + EMMC_BOOT_PART_BOOT2 = 2, + EMMC_BOOT_PART_USER = 7, +}; + +/* emmc PARTITION_CONFIG BOOT_PARTITION_ENABLE names */ +extern const char *emmc_boot_part_names[8]; + +/* emmc PARTITION_CONFIG ACCESS_ENABLE values */ +enum emmc_hwpart { + EMMC_HWPART_DEFAULT = 0, /* user */ + EMMC_HWPART_BOOT1 = 1, + EMMC_HWPART_BOOT2 = 2, + EMMC_HWPART_RPMB = 3, + EMMC_HWPART_GP1 = 4, + EMMC_HWPART_GP2 = 5, + EMMC_HWPART_GP3 = 6, + EMMC_HWPART_GP4 = 7, +}; + +/* emmc PARTITION_CONFIG ACCESS_ENABLE names */ +extern const char *emmc_hwpart_names[8]; + /* Driver model support */ /** diff --git a/include/os.h b/include/os.h index 877404a6c13..4371270a1ee 100644 --- a/include/os.h +++ b/include/os.h @@ -29,7 +29,7 @@ int os_printf(const char *format, ...); * @fd: File descriptor as returned by os_open() * @buf: Buffer to place data * @count: Number of bytes to read - * Return: number of bytes read, or -1 on error + * Return: number of bytes read, or -errno on error */ ssize_t os_read(int fd, void *buf, size_t count); @@ -39,7 +39,7 @@ ssize_t os_read(int fd, void *buf, size_t count); * @fd: File descriptor as returned by os_open() * @buf: Buffer containing data to write * @count: Number of bytes to write - * Return: number of bytes written, or -1 on error + * Return: number of bytes written, or -errno on error */ ssize_t os_write(int fd, const void *buf, size_t count); @@ -49,7 +49,7 @@ ssize_t os_write(int fd, const void *buf, size_t count); * @fd: File descriptor as returned by os_open() * @offset: File offset (based on whence) * @whence: Position offset is relative to (see below) - * Return: new file offset + * Return: new file offset, or -errno on error */ off_t os_lseek(int fd, off_t offset, int whence); diff --git a/include/part.h b/include/part.h index 54b986cee63..797b542ef1f 100644 --- a/include/part.h +++ b/include/part.h @@ -8,7 +8,7 @@ #include <blk.h> #include <ide.h> -#include <uuid.h> +#include <u-boot/uuid.h> #include <linker_lists.h> #include <linux/errno.h> #include <linux/list.h> diff --git a/include/pci_ids.h b/include/pci_ids.h index 191d277bc8a..a8939b105f1 100644 --- a/include/pci_ids.h +++ b/include/pci_ids.h @@ -2600,6 +2600,15 @@ #define PCI_DEVICE_ID_DCI_PCCOM2 0x0004 #define PCI_VENDOR_ID_INTEL 0x8086 +#define PCI_DEVICE_ID_INTEL_EHL_RGMII1G 0x4b30 +#define PCI_DEVICE_ID_INTEL_EHL_SGMII1 0x4b31 +#define PCI_DEVICE_ID_INTEL_EHL_SGMII2G5 0x4b32 +#define PCI_DEVICE_ID_INTEL_EHL_PSE0_RGMII1G 0x4ba0 +#define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII1G 0x4ba1 +#define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII2G5 0x4ba2 +#define PCI_DEVICE_ID_INTEL_EHL_PSE1_RGMII1G 0x4bb0 +#define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII1G 0x4bb1 +#define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII2G5 0x4bb2 #define PCI_DEVICE_ID_INTEL_EESSC 0x0008 #define PCI_DEVICE_ID_INTEL_SNB_IMC 0x0100 #define PCI_DEVICE_ID_INTEL_IVB_IMC 0x0154 diff --git a/include/rkmtd.h b/include/rkmtd.h index 145fede6c84..b7479036b39 100644 --- a/include/rkmtd.h +++ b/include/rkmtd.h @@ -11,7 +11,7 @@ #define __RKMTD__ #include <part_efi.h> -#include <uuid.h> +#include <u-boot/uuid.h> #define LBA 64 + 512 + 33 diff --git a/include/sandbox_efi_capsule.h b/include/sandbox_efi_capsule.h index 3e288e8a84a..84d45ec5cfd 100644 --- a/include/sandbox_efi_capsule.h +++ b/include/sandbox_efi_capsule.h @@ -6,9 +6,9 @@ #if !defined(_SANDBOX_EFI_CAPSULE_H_) #define _SANDBOX_EFI_CAPSULE_H_ -#define SANDBOX_UBOOT_IMAGE_GUID "09d7cf52-0720-4710-91d1-08469b7fe9c8" -#define SANDBOX_UBOOT_ENV_IMAGE_GUID "5a7021f5-fef2-48b4-aaba-832e777418c0" -#define SANDBOX_FIT_IMAGE_GUID "3673b45d-6a7c-46f3-9e60-adabb03f7937" +#define SANDBOX_UBOOT_IMAGE_GUID "985f2937-7c2e-5e9a-8a5e-8e063312964b" +#define SANDBOX_UBOOT_ENV_IMAGE_GUID "9e339473-c2eb-530a-a69b-0cd6bbbed40e" +#define SANDBOX_FIT_IMAGE_GUID "46610520-469e-59dc-a8dd-c11832b877ea" #define SANDBOX_INCORRECT_GUID "058b7d83-50d5-4c47-a195-60d86ad341c4" #define UBOOT_FIT_IMAGE "u-boot_bin_env.itb" diff --git a/include/spl.h b/include/spl.h index 1eebea3f981..de808ccd413 100644 --- a/include/spl.h +++ b/include/spl.h @@ -282,55 +282,67 @@ static inline void *spl_image_fdt_addr(struct spl_image_info *info) #endif } +struct spl_load_info; + +/** + * spl_load_reader() - Read from device + * + * @load: Information about the load state + * @offset: Offset to read from in bytes. This must be a multiple of + * @load->bl_len. + * @count: Number of bytes to read. This must be a multiple of + * @load->bl_len. + * @buf: Buffer to read into + * @return number of bytes read, 0 on error + */ +typedef ulong (*spl_load_reader)(struct spl_load_info *load, ulong sector, + ulong count, void *buf); + /** * Information required to load data from a device * + * @read: Function to call to read from the device * @priv: Private data for the device * @bl_len: Block length for reading in bytes - * @read: Function to call to read from the device */ struct spl_load_info { + spl_load_reader read; void *priv; - /** - * read() - Read from device - * - * @load: Information about the load state - * @offset: Offset to read from in bytes. This must be a multiple of - * @load->bl_len. - * @count: Number of bytes to read. This must be a multiple of - * @load->bl_len. - * @buf: Buffer to read into - * @return number of bytes read, 0 on error - */ - ulong (*read)(struct spl_load_info *load, ulong sector, ulong count, - void *buf); #if IS_ENABLED(CONFIG_SPL_LOAD_BLOCK) int bl_len; +#endif }; static inline int spl_get_bl_len(struct spl_load_info *info) { +#if IS_ENABLED(CONFIG_SPL_LOAD_BLOCK) return info->bl_len; +#else + return 1; +#endif } static inline void spl_set_bl_len(struct spl_load_info *info, int bl_len) { +#if IS_ENABLED(CONFIG_SPL_LOAD_BLOCK) info->bl_len = bl_len; -} #else -}; - -static inline int spl_get_bl_len(struct spl_load_info *info) -{ - return 1; + if (bl_len != 1) + panic("CONFIG_SPL_LOAD_BLOCK not enabled"); +#endif } -static inline void spl_set_bl_len(struct spl_load_info *info, int bl_len) +/** + * spl_load_init() - Set up a new spl_load_info structure + */ +static inline void spl_load_init(struct spl_load_info *load, + spl_load_reader h_read, void *priv, + uint bl_len) { - if (bl_len != 1) - panic("CONFIG_SPL_LOAD_BLOCK not enabled"); + load->read = h_read; + load->priv = priv; + spl_set_bl_len(load, bl_len); } -#endif /* * We need to know the position of U-Boot in memory so we can jump to it. We @@ -1073,4 +1085,20 @@ static inline bool spl_decompression_enabled(void) { return IS_ENABLED(CONFIG_SPL_GZIP) || IS_ENABLED(CONFIG_SPL_LZMA); } + +/** + * spl_write_upl_handoff() - Write a Universal Payload hand-off structure + * + * @spl_image: Information about the image being booted + * Return: 0 if OK, -ve on error + */ +int spl_write_upl_handoff(struct spl_image_info *spl_image); + +/** + * spl_upl_init() - Get UPL ready for information to be added + * + * This must be called before upl_add_image(), etc. + */ +void spl_upl_init(void); + #endif diff --git a/include/spl_load.h b/include/spl_load.h index 1c2b296c0a2..935f7d336f2 100644 --- a/include/spl_load.h +++ b/include/spl_load.h @@ -22,7 +22,7 @@ static inline int _spl_load(struct spl_image_info *spl_image, read = info->read(info, offset, ALIGN(sizeof(*header), spl_get_bl_len(info)), header); - if (read < sizeof(*header)) + if (read < (int)sizeof(*header)) return -EIO; if (image_get_magic(header) == FDT_MAGIC) { @@ -83,6 +83,10 @@ static inline int _spl_load(struct spl_image_info *spl_image, read = info->read(info, offset + image_offset, size, map_sysmem(spl_image->load_addr - overhead, size)); + + if (read < 0) + return read; + return read < spl_image->size ? -EIO : 0; } diff --git a/include/test/log.h b/include/test/log.h index e9028914500..e3362b85e99 100644 --- a/include/test/log.h +++ b/include/test/log.h @@ -13,7 +13,8 @@ #define LOGF_TEST (BIT(LOGF_FUNC) | BIT(LOGF_MSG)) /* Declare a new logging test */ -#define LOG_TEST(_name) UNIT_TEST(_name, 0, log_test) -#define LOG_TEST_FLAGS(_name, _flags) UNIT_TEST(_name, _flags, log_test) +#define LOG_TEST(_name) UNIT_TEST(_name, UTF_CONSOLE, log_test) +#define LOG_TEST_FLAGS(_name, _flags) \ + UNIT_TEST(_name, _flags | UTF_CONSOLE, log_test) #endif /* __TEST_LOG_H__ */ diff --git a/include/test/spl.h b/include/test/spl.h index a2a5f33e328..5fd28d92706 100644 --- a/include/test/spl.h +++ b/include/test/spl.h @@ -154,6 +154,6 @@ SPL_TEST(func##_##type, flags) #define SPL_TEST_DATA_SIZE 4099 /* Flags necessary for accessing DM devices */ -#define DM_FLAGS (UT_TESTF_DM | UT_TESTF_SCAN_FDT) +#define DM_FLAGS (UTF_DM | UTF_SCAN_FDT) #endif /* TEST_SPL_H */ diff --git a/include/test/suites.h b/include/test/suites.h index 365d5f20dfe..2ceef577f7f 100644 --- a/include/test/suites.h +++ b/include/test/suites.h @@ -63,5 +63,6 @@ int do_ut_str(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); int do_ut_time(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); int do_ut_unicode(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); +int do_ut_upl(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); #endif /* __TEST_SUITES_H__ */ diff --git a/include/test/test.h b/include/test/test.h index 838e3ce8a8f..92eec2eb6f9 100644 --- a/include/test/test.h +++ b/include/test/test.h @@ -24,11 +24,11 @@ * @fdt_chksum: crc8 of the device tree contents * @fdt_copy: Copy of the device tree * @fdt_size: Size of the device-tree copy - * @other_fdt: Buffer for the other FDT (UT_TESTF_OTHER_FDT) - * @other_fdt_size: Size of the other FDT (UT_TESTF_OTHER_FDT) + * @other_fdt: Buffer for the other FDT (UTF_OTHER_FDT) + * @other_fdt_size: Size of the other FDT (UTF_OTHER_FDT) * @of_other: Live tree for the other FDT * @runs_per_test: Number of times to run each test (typically 1) - * @force_run: true to run tests marked with the UT_TESTF_MANUAL flag + * @force_run: true to run tests marked with the UTF_MANUAL flag * @expect_str: Temporary string used to hold expected string value * @actual_str: Temporary string used to hold actual string value */ @@ -55,24 +55,24 @@ struct unit_test_state { }; /* Test flags for each test */ -enum { - UT_TESTF_SCAN_PDATA = BIT(0), /* test needs platform data */ - UT_TESTF_PROBE_TEST = BIT(1), /* probe test uclass */ - UT_TESTF_SCAN_FDT = BIT(2), /* scan device tree */ - UT_TESTF_FLAT_TREE = BIT(3), /* test needs flat DT */ - UT_TESTF_LIVE_TREE = BIT(4), /* needs live device tree */ - UT_TESTF_CONSOLE_REC = BIT(5), /* needs console recording */ +enum ut_flags { + UTF_SCAN_PDATA = BIT(0), /* test needs platform data */ + UTF_PROBE_TEST = BIT(1), /* probe test uclass */ + UTF_SCAN_FDT = BIT(2), /* scan device tree */ + UTF_FLAT_TREE = BIT(3), /* test needs flat DT */ + UTF_LIVE_TREE = BIT(4), /* needs live device tree */ + UTF_CONSOLE = BIT(5), /* needs console recording */ /* do extra driver model init and uninit */ - UT_TESTF_DM = BIT(6), - UT_TESTF_OTHER_FDT = BIT(7), /* read in other device tree */ + UTF_DM = BIT(6), + UTF_OTHER_FDT = BIT(7), /* read in other device tree */ /* * Only run if explicitly requested with 'ut -f <suite> <test>'. The * test name must end in "_norun" so that pytest detects this also, * since it cannot access the flags. */ - UT_TESTF_MANUAL = BIT(8), - UT_TESTF_ETH_BOOTDEV = BIT(9), /* enable Ethernet bootdevs */ - UT_TESTF_SF_BOOTDEV = BIT(10), /* enable SPI flash bootdevs */ + UTF_MANUAL = BIT(8), + UTF_ETH_BOOTDEV = BIT(9), /* enable Ethernet bootdevs */ + UTF_SF_BOOTDEV = BIT(10), /* enable SPI flash bootdevs */ }; /** @@ -109,7 +109,7 @@ struct unit_test { * @_name: concatenation of name of the test suite, "_test_", and the name * of the test * @_flags: an integer field that can be evaluated by the test suite - * implementation + * implementation (see enum ut_flags) * @_suite: name of the test suite concatenated with "_test" */ #define UNIT_TEST(_name, _flags, _suite) \ diff --git a/include/test/ut.h b/include/test/ut.h index d3172af8083..c8838dad096 100644 --- a/include/test/ut.h +++ b/include/test/ut.h @@ -495,7 +495,7 @@ void test_set_state(struct unit_test_state *uts); * @select_name: Name of a single test to run (from the list provided). If NULL * then all tests are run * @runs_per_test: Number of times to run each test (typically 1) - * @force_run: Run tests that are marked as manual-only (UT_TESTF_MANUAL) + * @force_run: Run tests that are marked as manual-only (UTF_MANUAL) * @test_insert: String describing a test to run after n other tests run, in the * format n:name where n is the number of tests to run before this one and * name is the name of the test to run. This is used to find which test causes diff --git a/include/uuid.h b/include/u-boot/uuid.h index f5a941250f4..7f8414dc906 100644 --- a/include/uuid.h +++ b/include/u-boot/uuid.h @@ -11,6 +11,7 @@ #define __UUID_H__ #include <linux/bitops.h> +#include <linux/kconfig.h> /* * UUID - Universally Unique IDentifier - 128 bits unique number. @@ -46,8 +47,8 @@ * When converting to a binary UUID, le means the field should be converted * to little endian and be means it should be converted to big endian. * - * UUID is also used as GUID (Globally Unique Identifier) with the same binary - * format but it differs in string format like below. + * UUID is also used as GUID (Globally Unique Identifier) with the same format + * but with some fields stored in little endian. * * GUID: * 0 9 14 19 24 @@ -69,8 +70,8 @@ struct uuid { /* Bits of a bitmask specifying the output format for GUIDs */ #define UUID_STR_FORMAT_STD 0 -#define UUID_STR_FORMAT_GUID BIT(0) -#define UUID_STR_UPPER_CASE BIT(1) +#define UUID_STR_FORMAT_GUID 0x1 +#define UUID_STR_UPPER_CASE 0x2 /* Use UUID_STR_LEN + 1 for string space */ #define UUID_STR_LEN 36 @@ -143,6 +144,18 @@ void gen_rand_uuid(unsigned char *uuid_bin); */ void gen_rand_uuid_str(char *uuid_str, int str_format); +struct efi_guid; + +/** + * gen_v5_guid() - generate little endian v5 GUID from namespace and other seed data. + * + * @namespace: pointer to UUID namespace salt + * @guid: pointer to allocated GUID output + * @...: NULL terminated list of seed data as pairs of pointers + * to data and their lengths + */ +void gen_v5_guid(const struct uuid *namespace, struct efi_guid *guid, ...); + /** * uuid_str_to_le_bin() - Convert string UUID to little endian binary data. * @uuid_str: pointer to UUID string diff --git a/include/upl.h b/include/upl.h new file mode 100644 index 00000000000..2ec5ef1b5cf --- /dev/null +++ b/include/upl.h @@ -0,0 +1,382 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * UPL handoff generation + * + * Copyright 2024 Google LLC + * Written by Simon Glass <sjg@chromium.org> + */ + +#ifndef __UPL_WRITE_H +#define __UPL_WRITE_H + +#ifndef USE_HOSTCC + +#include <alist.h> +#include <image.h> +#include <dm/ofnode_decl.h> + +struct unit_test_state; + +#define UPLP_ADDRESS_CELLS "#address-cells" +#define UPLP_SIZE_CELLS "#size-cells" + +#define UPLN_OPTIONS "options" +#define UPLN_UPL_PARAMS "upl-params" +#define UPLP_SMBIOS "smbios" +#define UPLP_ACPI "acpi" +#define UPLP_BOOTMODE "bootmode" +#define UPLP_ADDR_WIDTH "addr-width" +#define UPLP_ACPI_NVS_SIZE "acpi-nvs-size" + +#define UPLPATH_UPL_IMAGE "/options/upl-image" +#define UPLN_UPL_IMAGE "upl-image" +#define UPLN_IMAGE "image" +#define UPLP_FIT "fit" +#define UPLP_CONF_OFFSET "conf-offset" +#define UPLP_LOAD "load" +#define UPLP_SIZE "size" +#define UPLP_OFFSET "offset" +#define UPLP_DESCRIPTION "description" + +#define UPLN_MEMORY "memory" +#define UPLP_HOTPLUGGABLE "hotpluggable" + +#define UPLPATH_MEMORY_MAP "/memory-map" +#define UPLN_MEMORY_MAP "memory-map" +#define UPLP_USAGE "usage" + +#define UPLN_MEMORY_RESERVED "reserved-memory" +#define UPLPATH_MEMORY_RESERVED "/reserved-memory" +#define UPLP_NO_MAP "no-map" + +#define UPLN_SERIAL "serial" +#define UPLP_REG "reg" +#define UPLP_COMPATIBLE "compatible" +#define UPLP_CLOCK_FREQUENCY "clock-frequency" +#define UPLP_CURRENT_SPEED "current-speed" +#define UPLP_REG_IO_SHIFT "reg-io-shift" +#define UPLP_REG_OFFSET "reg-offset" +#define UPLP_REG_IO_WIDTH "reg-io-width" +#define UPLP_VIRTUAL_REG "virtual-reg" +#define UPLP_ACCESS_TYPE "access-type" + +#define UPLN_GRAPHICS "framebuffer" +#define UPLC_GRAPHICS "simple-framebuffer" +#define UPLP_WIDTH "width" +#define UPLP_HEIGHT "height" +#define UPLP_STRIDE "stride" +#define UPLP_GRAPHICS_FORMAT "format" + +/** + * enum upl_boot_mode - Encodes the boot mode + * + * Each is a bit number from the boot_mode mask + */ +enum upl_boot_mode { + UPLBM_FULL, + UPLBM_MINIMAL, + UPLBM_FAST, + UPLBM_DIAG, + UPLBM_DEFAULT, + UPLBM_S2, + UPLBM_S3, + UPLBM_S4, + UPLBM_S5, + UPLBM_FACTORY, + UPLBM_FLASH, + UPLBM_RECOVERY, + + UPLBM_COUNT, +}; + +/** + * struct upl_image - UPL image informaiton + * + * @load: Address image was loaded to + * @size: Size of image in bytes + * @offset: Offset of the image in the FIT (0=none) + * @desc: Description of the iamge (taken from the FIT) + */ +struct upl_image { + ulong load; + ulong size; + uint offset; + const char *description; +}; + +/** + * struct memregion - Information about a region of memory + * + * @base: Base address + * @size: Size in bytes + */ +struct memregion { + ulong base; + ulong size; +}; + +/** + * struct upl_mem - Information about physical-memory layout + * + * TODO: Figure out initial-mapped-area + * + * @region: Memory region list (struct memregion) + * @hotpluggable: true if hotpluggable + */ +struct upl_mem { + struct alist region; + bool hotpluggable; +}; + +/** + * enum upl_usage - Encodes the usage + * + * Each is a bit number from the usage mask + */ +enum upl_usage { + UPLUS_ACPI_RECLAIM, + UPLUS_ACPI_NVS, + UPLUS_BOOT_CODE, + UPLUS_BOOT_DATA, + UPLUS_RUNTIME_CODE, + UPLUS_RUNTIME_DATA, + UPLUS_COUNT +}; + +/** + * struct upl_memmap - Information about logical-memory layout + * + * @name: Node name to use + * @region: Memory region list (struct memregion) + * @usage: Memory-usage mask (enum upl_usage) + */ +struct upl_memmap { + const char *name; + struct alist region; + uint usage; +}; + +/** + * struct upl_memres - Reserved memory + * + * @name: Node name to use + * @region: Reserved memory region list (struct memregion) + * @no_map: true to indicate that a virtual mapping must not be created + */ +struct upl_memres { + const char *name; + struct alist region; + bool no_map; +}; + +enum upl_serial_access_type { + UPLSAT_MMIO, + UPLSAT_IO, +}; + +/* serial defaults */ +enum { + UPLD_REG_IO_SHIFT = 0, + UPLD_REG_OFFSET = 0, + UPLD_REG_IO_WIDTH = 1, +}; + +/** + * enum upl_access_type - Access types + * + * @UPLAT_MMIO: Memory-mapped I/O + * @UPLAT_IO: Separate I/O + */ +enum upl_access_type { + UPLAT_MMIO, + UPLAT_IO, +}; + +/** + * struct upl_serial - Serial console + * + * @compatible: Compatible string (NULL if there is no serial console) + * @clock_frequency: Input clock frequency of UART + * @current_speed: Current baud rate of UART + * @reg: List of base address and size of registers (struct memregion) + * @reg_shift_log2: log2 of distance between each register + * @reg_offset: Offset of registers from the base address + * @reg_width: Register width in bytes + * @virtual_reg: Virtual register access (0 for none) + * @access_type: Register access type to use + */ +struct upl_serial { + const char *compatible; + uint clock_frequency; + uint current_speed; + struct alist reg; + uint reg_io_shift; + uint reg_offset; + uint reg_io_width; + ulong virtual_reg; + enum upl_serial_access_type access_type; +}; + +/** + * enum upl_graphics_format - Graphics formats + * + * @UPLGF_ARGB32: 32bpp format using 0xaarrggbb + * @UPLGF_ABGR32: 32bpp format using 0xaabbggrr + * @UPLGF_ARGB64: 64bpp format using 0xaaaabbbbggggrrrr + */ +enum upl_graphics_format { + UPLGF_ARGB32, + UPLGF_ABGR32, + UPLGF_ABGR64, +}; + +/** + * @reg: List of base address and size of registers (struct memregion) + * @width: Width of display in pixels + * @height: Height of display in pixels + * @stride: Number of bytes from one line to the next + * @format: Pixel format + */ +struct upl_graphics { + struct alist reg; + uint width; + uint height; + uint stride; + enum upl_graphics_format format; +}; + +/* + * Information about the UPL state + * + * @addr_cells: Number of address cells used in the handoff + * @size_cells: Number of size cells used in the handoff + * @bootmode: Boot-mode mask (enum upl_boot_mode) + * @fit: Address of FIT image that was loaded + * @conf_offset: Offset in FIT of the configuration that was selected + * @addr_width: Adress-bus width of machine, e.g. 46 for 46 bits + * @acpi_nvs_size: Size of the ACPI non-volatile-storage area in bytes + * @image: Information about each image (struct upl_image) + * @mem: Information about physical-memory regions (struct upl_mem) + * @nennap: Information about logical-memory regions (struct upl_memmap) + * @nennap: Information about reserved-memory regions (struct upl_memres) + */ +struct upl { + int addr_cells; + int size_cells; + + ulong smbios; + ulong acpi; + uint bootmode; + ulong fit; + uint conf_offset; + uint addr_width; + uint acpi_nvs_size; + + struct alist image; + struct alist mem; + struct alist memmap; + struct alist memres; + struct upl_serial serial; + struct upl_graphics graphics; +}; + +/** + * upl_write_handoff() - Write a Unversal Payload handoff structure + * + * upl: UPL state to write + * @root: root node to write it to + * @skip_existing: Avoid recreating any nodes which already exist in the + * devicetree. For example, if there is a serial node, just leave it alone, + * since don't need to create a new one + * Return: 0 on success, -ve on error + */ +int upl_write_handoff(const struct upl *upl, ofnode root, bool skip_existing); + +/** + * upl_create_handoff_tree() - Write a Unversal Payload handoff structure + * + * upl: UPL state to write + * @treep: Returns a new tree containing the handoff + * Return: 0 on success, -ve on error + */ +int upl_create_handoff_tree(const struct upl *upl, oftree *treep); + +/** + * upl_read_handoff() - Read a Unversal Payload handoff structure + * + * upl: UPL state to read into + * @tree: Devicetree containing the data to read + * Return: 0 on success, -ve on error + */ +int upl_read_handoff(struct upl *upl, oftree tree); + +/** + * upl_get_test_data() - Fill a UPL with some test data + * + * @uts: Test state (can be uninited) + * @upl: Returns test data + * Return: 0 on success, 1 on error + */ +int upl_get_test_data(struct unit_test_state *uts, struct upl *upl); +#endif /* USE_HOSTCC */ + +#if CONFIG_IS_ENABLED(UPL) && defined(CONFIG_SPL_BUILD) + +/** + * upl_set_fit_info() - Set up basic info about the FIT + * + * @fit: Address of FIT + * @conf_offset: Configuration node being used + * @entry_addr: Entry address for next phase + */ +void upl_set_fit_info(ulong fit, int conf_offset, ulong entry_addr); + +/** + * upl_set_fit_addr() - Set up the address of the FIT + * + * @fit: Address of FIT + */ +void upl_set_fit_addr(ulong fit); + +#else +static inline void upl_set_fit_addr(ulong fit) {} +static inline void upl_set_fit_info(ulong fit, int conf_offset, + ulong entry_addr) {} +#endif /* UPL && SPL */ + +/** + * _upl_add_image() - Internal function to add a new image to the UPL + * + * @node: Image node offset in FIT + * @load_addr: Address to which images was loaded + * @size: Image size in bytes + * @desc: Description of image + * Return: 0 if OK, -ENOMEM if out of memory + */ +int _upl_add_image(int node, ulong load_addr, ulong size, const char *desc); + +/** + * upl_add_image() - Add a new image to the UPL + * + * @fit: Pointer to FIT + * @node: Image node offset in FIT + * @load_addr: Address to which images was loaded + * @size: Image size in bytes + * Return: 0 if OK, -ENOMEM if out of memory + */ +static inline int upl_add_image(const void *fit, int node, ulong load_addr, + ulong size) +{ + if (CONFIG_IS_ENABLED(UPL) && IS_ENABLED(CONFIG_SPL_BUILD)) { + const char *desc = fdt_getprop(fit, node, FIT_DESC_PROP, NULL); + + return _upl_add_image(node, load_addr, size, desc); + } + + return 0; +} + +/** upl_init() - Set up a UPL struct */ +void upl_init(struct upl *upl); + +#endif /* __UPL_WRITE_H */ diff --git a/include/video.h b/include/video.h index 4013a949983..606c8a37fb8 100644 --- a/include/video.h +++ b/include/video.h @@ -420,4 +420,15 @@ int bmp_info(ulong addr); */ int video_reserve_from_bloblist(struct video_handoff *ho); +/** + * video_get_fb() - Get the first framebuffer address + * + * This function does not probe video devices, so can only be used after a video + * device has been activated. + * + * Return: address of the framebuffer of the first video device found, or 0 if + * there is no device + */ +ulong video_get_fb(void); + #endif |