diff options
Diffstat (limited to 'include')
29 files changed, 518 insertions, 120 deletions
diff --git a/include/charset.h b/include/charset.h index f1050c903d6..348bad5883a 100644 --- a/include/charset.h +++ b/include/charset.h @@ -16,7 +16,7 @@ /* * codepage_437 - Unicode to codepage 437 translation table */ -extern const u16 codepage_437[128]; +extern const u16 codepage_437[160]; /** * console_read_unicode() - read Unicode code point from console diff --git a/include/configs/am62px_evm.h b/include/configs/am62px_evm.h new file mode 100644 index 00000000000..06b12860e21 --- /dev/null +++ b/include/configs/am62px_evm.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration header file for K3 AM62Px SoC family + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef __CONFIG_AM62PX_EVM_H +#define __CONFIG_AM62PX_EVM_H + +/* Now for the remaining common defines */ +#include <configs/ti_armv7_common.h> + +#endif /* __CONFIG_AM62PX_EVM_H */ diff --git a/include/configs/jaguar_rk3588.h b/include/configs/jaguar_rk3588.h new file mode 100644 index 00000000000..843028c5385 --- /dev/null +++ b/include/configs/jaguar_rk3588.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2023 Theobroma Systems Design und Consulting GmbH + */ + +#ifndef __JAGUAR_RK3588_H +#define __JAGUAR_RK3588_H + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#include <configs/rk3588_common.h> + +#endif /* __JAGUAR_RK3588_H */ diff --git a/include/configs/phycore_imx8mp.h b/include/configs/phycore_imx8mp.h index 11a17be7fe1..206c4d50d27 100644 --- a/include/configs/phycore_imx8mp.h +++ b/include/configs/phycore_imx8mp.h @@ -13,49 +13,6 @@ #define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) -#define CFG_EXTRA_ENV_SETTINGS \ - "image=Image\0" \ - "console=ttymxc0,115200\0" \ - "fdt_addr=0x48000000\0" \ - "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "ip_dyn=yes\0" \ - "dofastboot=0\0" \ - "fastboot_raw_partition_bootloader=64 8128\0" \ - "fastboot_raw_partition_all=0 4194304\0" \ - "emmc_dev=2\0" \ - "sd_dev=1\0" \ - "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ - "mmcpart=1\0" \ - "mmcroot=2\0" \ - "mmcautodetect=yes\0" \ - "mmcargs=setenv bootargs console=${console} " \ - "root=/dev/mmcblk${mmcdev}p${mmcroot} rootwait rw\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "if run loadfdt; then " \ - "booti ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi;\0 " \ - "nfsroot=/nfs\0" \ - "netargs=setenv bootargs console=${console} root=/dev/nfs ip=dhcp " \ - "nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${loadaddr} ${image}; " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "booti ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi;\0" \ - /* Link Definitions */ #define CFG_SYS_INIT_RAM_ADDR 0x40000000 diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h index c2abd14e114..0bf9e8b9a2e 100644 --- a/include/configs/rk3036_common.h +++ b/include/configs/rk3036_common.h @@ -5,7 +5,6 @@ #ifndef __CONFIG_RK3036_COMMON_H #define __CONFIG_RK3036_COMMON_H -#include <asm/arch-rockchip/hardware.h> #include "rockchip-common.h" #define CFG_SYS_HZ_CLOCK 24000000 diff --git a/include/configs/rk3066_common.h b/include/configs/rk3066_common.h index d70c8f77d48..6a3b6900463 100644 --- a/include/configs/rk3066_common.h +++ b/include/configs/rk3066_common.h @@ -6,7 +6,6 @@ #ifndef __CONFIG_RK3066_COMMON_H #define __CONFIG_RK3066_COMMON_H -#include <asm/arch-rockchip/hardware.h> #include "rockchip-common.h" #define CFG_IRAM_BASE 0x10080000 diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h index a8cee1e44d4..98f2c25f3cf 100644 --- a/include/configs/rk3188_common.h +++ b/include/configs/rk3188_common.h @@ -6,7 +6,6 @@ #ifndef __CONFIG_RK3188_COMMON_H #define __CONFIG_RK3188_COMMON_H -#include <asm/arch-rockchip/hardware.h> #include "rockchip-common.h" #define CFG_IRAM_BASE 0x10080000 diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h index 15f77df3e17..bab4ca015f7 100644 --- a/include/configs/rk322x_common.h +++ b/include/configs/rk322x_common.h @@ -5,7 +5,6 @@ #ifndef __CONFIG_RK322X_COMMON_H #define __CONFIG_RK322X_COMMON_H -#include <asm/arch-rockchip/hardware.h> #include "rockchip-common.h" #define CFG_SYS_HZ_CLOCK 24000000 diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index 3063076a97a..0c449e31099 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -6,7 +6,6 @@ #ifndef __CONFIG_RK3288_COMMON_H #define __CONFIG_RK3288_COMMON_H -#include <asm/arch-rockchip/hardware.h> #include "rockchip-common.h" #define CFG_SYS_HZ_CLOCK 24000000 diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h index ccb5369b901..d488f8d477a 100644 --- a/include/configs/rk3368_common.h +++ b/include/configs/rk3368_common.h @@ -8,7 +8,6 @@ #include "rockchip-common.h" -#include <asm/arch-rockchip/hardware.h> #include <linux/sizes.h> #define CFG_SYS_SDRAM_BASE 0 diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index 96ba19c659b..4e75771055b 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -13,22 +13,6 @@ #define CFG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xf8000000 -#define ROCKPI_4B_IDBLOADER_IMAGE_GUID \ - EFI_GUID(0x02f4d760, 0xcfd5, 0x43bd, 0x8e, 0x2d, \ - 0xa4, 0x2a, 0xcb, 0x33, 0xc6, 0x60) - -#define ROCKPI_4B_UBOOT_IMAGE_GUID \ - EFI_GUID(0x4ce292da, 0x1dd8, 0x428d, 0xa1, 0xc2, \ - 0x77, 0x74, 0x3e, 0xf8, 0xb9, 0x6e) - -#define ROCKPI_4C_IDBLOADER_IMAGE_GUID \ - EFI_GUID(0xfd68510c, 0x12d3, 0x4f0a, 0xb8, 0xd3, \ - 0xd8, 0x79, 0xe1, 0xd3, 0xa5, 0x40) - -#define ROCKPI_4C_UBOOT_IMAGE_GUID \ - EFI_GUID(0xb81fb4ae, 0xe4f3, 0x471b, 0x99, 0xb4, \ - 0x0b, 0x3d, 0xa5, 0x49, 0xce, 0x13) - #ifndef CONFIG_SPL_BUILD #define ENV_MEM_LAYOUT_SETTINGS \ diff --git a/include/configs/rockpi4-rk3399.h b/include/configs/rockpi4-rk3399.h new file mode 100644 index 00000000000..1936e06ab3c --- /dev/null +++ b/include/configs/rockpi4-rk3399.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + */ + +#ifndef __ROCKPI4_RK3399_H +#define __ROCKPI4_RK3399_H + +#define ROCKPI_4B_IDBLOADER_IMAGE_GUID \ + EFI_GUID(0x02f4d760, 0xcfd5, 0x43bd, 0x8e, 0x2d, \ + 0xa4, 0x2a, 0xcb, 0x33, 0xc6, 0x60) + +#define ROCKPI_4B_UBOOT_IMAGE_GUID \ + EFI_GUID(0x4ce292da, 0x1dd8, 0x428d, 0xa1, 0xc2, \ + 0x77, 0x74, 0x3e, 0xf8, 0xb9, 0x6e) + +#define ROCKPI_4C_IDBLOADER_IMAGE_GUID \ + EFI_GUID(0xfd68510c, 0x12d3, 0x4f0a, 0xb8, 0xd3, \ + 0xd8, 0x79, 0xe1, 0xd3, 0xa5, 0x40) + +#define ROCKPI_4C_UBOOT_IMAGE_GUID \ + EFI_GUID(0xb81fb4ae, 0xe4f3, 0x471b, 0x99, 0xb4, \ + 0x0b, 0x3d, 0xa5, 0x49, 0xce, 0x13) + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdin=serial,usbkbd\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#include <configs/rk3399_common.h> + +#endif diff --git a/include/configs/rv1108_common.h b/include/configs/rv1108_common.h index 3bf70a0e0ae..ff28236a21d 100644 --- a/include/configs/rv1108_common.h +++ b/include/configs/rv1108_common.h @@ -5,7 +5,6 @@ #ifndef __CONFIG_RV1108_COMMON_H #define __CONFIG_RV1108_COMMON_H -#include <asm/arch-rockchip/hardware.h> #include "rockchip-common.h" #define CFG_IRAM_BASE 0x10080000 diff --git a/include/configs/socfpga_agilex5_socdk.h b/include/configs/socfpga_agilex5_socdk.h new file mode 100644 index 00000000000..b5b5bd767fb --- /dev/null +++ b/include/configs/socfpga_agilex5_socdk.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2024 Intel Corporation <www.intel.com> + * + */ + +#ifndef __CONFIG_SOCFGPA_AGILEX5_H__ +#define __CONFIG_SOCFGPA_AGILEX5_H__ + +#include <configs/socfpga_soc64_common.h> + +#endif /* __CONFIG_SOCFGPA_AGILEX5_H__ */ diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index 820372c28b3..b7ee1dbf201 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 * - * Copyright (C) 2017-2019 Intel Corporation <www.intel.com> + * Copyright (C) 2017-2024 Intel Corporation <www.intel.com> * */ @@ -26,8 +26,13 @@ /* * U-Boot run time memory configurations */ +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#define CFG_SYS_INIT_RAM_ADDR 0x0 +#define CFG_SYS_INIT_RAM_SIZE 0x80000 +#else #define CFG_SYS_INIT_RAM_ADDR 0xFFE00000 #define CFG_SYS_INIT_RAM_SIZE 0x40000 +#endif /* * U-Boot environment configurations @@ -36,9 +41,121 @@ /* * Environment variable */ +#if IS_ENABLED(CONFIG_DISTRO_DEFAULTS) +#if IS_ENABLED(CONFIG_CMD_MMC) +#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) +#else +#define BOOT_TARGET_DEVICES_MMC(func) +#endif + +#if IS_ENABLED(CONFIG_CMD_SF) +#define BOOT_TARGET_DEVICES_QSPI(func) func(QSPI, qspi, na) +#else +#define BOOT_TARGET_DEVICES_QSPI(func) +#endif + +#define BOOTENV_DEV_QSPI(devtypeu, devtypel, instance) \ + "bootcmd_qspi=ubi detach; sf probe && " \ + "if ubi part root && ubi readvol ${scriptaddr} script; " \ + "then echo QSPI: Running script from UBIFS; " \ + "elif sf read ${scriptaddr} ${qspiscriptaddr} ${scriptsize}; " \ + "then echo QSPI: Running script from JFFS2; fi; " \ + "echo QSPI: Trying to boot script at ${scriptaddr} && " \ + "source ${scriptaddr}; " \ + "echo QSPI: SCRIPT FAILED: continuing...; ubi detach;\0" + +#define BOOTENV_DEV_NAME_QSPI(devtypeu, devtypel, instance) \ + "qspi " + +#define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_DEVICES_MMC(func) \ + BOOT_TARGET_DEVICES_QSPI(func) + +#include <config_distro_bootcmd.h> + +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) + #define CFG_EXTRA_ENV_SETTINGS \ + "kernel_addr_r=0x82000000\0" \ + "fdt_addr_r=0x86000000\0" \ + "qspiscriptaddr=0x02110000\0" \ + "scriptsize=0x00010000\0" \ + "qspibootimageaddr=0x02120000\0" \ + "bootimagesize=0x03200000\0" \ "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "bootfile=" CONFIG_BOOTFILE "\0" \ + "mmcroot=/dev/mmcblk0p2\0" \ + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + "linux_qspi_enable=if sf probe; then " \ + "echo Enabling QSPI at Linux DTB...;" \ + "fdt addr ${fdt_addr}; fdt resize;" \ + "fdt set /soc/spi@108d2000 status okay;" \ + "if fdt set /clocks/qspi-clk clock-frequency" \ + " ${qspi_clock}; then echo QSPI clock frequency updated;" \ + " elif fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency" \ + " ${qspi_clock}; then echo QSPI clock frequency updated;" \ + " else fdt set /clocks/qspi-clk clock-frequency" \ + " ${qspi_clock}; echo QSPI clock frequency updated; fi; fi\0" \ + "scriptaddr=0x81000000\0" \ + "scriptfile=boot.scr\0" \ + "socfpga_legacy_reset_compat=1\0" \ + "smc_fid_rd=0xC2000007\0" \ + "smc_fid_wr=0xC2000008\0" \ + "smc_fid_upd=0xC2000009\0 " \ + BOOTENV + +#else + +#define CFG_EXTRA_ENV_SETTINGS \ + "kernel_addr_r=0x2000000\0" \ + "fdt_addr_r=0x6000000\0" \ + "qspiscriptaddr=0x02110000\0" \ + "scriptsize=0x00010000\0" \ + "qspibootimageaddr=0x02120000\0" \ + "bootimagesize=0x03200000\0" \ + "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "bootfile=" CONFIG_BOOTFILE "\0" \ + "mmcroot=/dev/mmcblk0p2\0" \ + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + "linux_qspi_enable=if sf probe; then " \ + "echo Enabling QSPI at Linux DTB...;" \ + "fdt addr ${fdt_addr}; fdt resize;" \ + "fdt set /soc/spi@ff8d2000 status okay;" \ + "if fdt set /soc/clocks/qspi-clk clock-frequency" \ + " ${qspi_clock}; then echo QSPI clock frequency updated;" \ + " elif fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency" \ + " ${qspi_clock}; then echo QSPI clock frequency updated;" \ + " else fdt set /clocks/qspi-clk clock-frequency" \ + " ${qspi_clock}; echo QSPI clock frequency updated; fi; fi\0" \ + "scriptaddr=0x05FF0000\0" \ + "scriptfile=boot.scr\0" \ + "socfpga_legacy_reset_compat=1\0" \ + "smc_fid_rd=0xC2000007\0" \ + "smc_fid_wr=0xC2000008\0" \ + "smc_fid_upd=0xC2000009\0 " \ + BOOTENV +#endif /*#IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)*/ + +#else + +#define CFG_EXTRA_ENV_SETTINGS \ + "kernel_comp_addr_r=0x9000000\0" \ + "kernel_comp_size=0x01000000\0" \ + "qspibootimageaddr=0x020E0000\0" \ + "qspifdtaddr=0x020D0000\0" \ + "bootimagesize=0x01F00000\0" \ + "fdtimagesize=0x00010000\0" \ + "qspiload=sf read ${loadaddr} ${qspibootimageaddr} ${bootimagesize};" \ + "sf read ${fdt_addr} ${qspifdtaddr} ${fdtimagesize}\0" \ + "qspiboot=setenv bootargs earlycon root=/dev/mtdblock1 rw " \ + "rootfstype=jffs2 rootwait;booti ${loadaddr} - ${fdt_addr}\0" \ + "qspifitload=sf read ${loadaddr} ${qspibootimageaddr} ${bootimagesize}\0" \ + "qspifitboot=setenv bootargs earlycon root=/dev/mtdblock1 rw " \ + "rootfstype=jffs2 rootwait;bootm ${loadaddr}\0" \ + "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "bootfile=" CONFIG_BOOTFILE "\0" \ "fdt_addr=8000000\0" \ "fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ "mmcroot=/dev/mmcblk0p2\0" \ @@ -53,24 +170,40 @@ "bootm ${loadaddr}\0" \ "mmcfitload=mmc rescan;" \ "load mmc 0:1 ${loadaddr} ${bootfile}\0" \ + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "linux_qspi_enable=if sf probe; then " \ "echo Enabling QSPI at Linux DTB...;" \ "fdt addr ${fdt_addr}; fdt resize;" \ "fdt set /soc/spi@ff8d2000 status okay;" \ - "fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency " \ - " ${qspi_clock}; fi; \0" \ + "if fdt set /soc/clocks/qspi-clk clock-frequency" \ + " ${qspi_clock}; then echo QSPI clock frequency updated;" \ + " elif fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency" \ + " ${qspi_clock}; then echo QSPI clock frequency updated;" \ + " else fdt set /clocks/qspi-clk clock-frequency" \ + " ${qspi_clock}; echo QSPI clock frequency updated; fi; fi\0" \ "scriptaddr=0x02100000\0" \ "scriptfile=u-boot.scr\0" \ "fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \ - "then source ${scriptaddr}; fi\0" \ - "socfpga_legacy_reset_compat=1\0" + "then source ${scriptaddr}:script; fi\0" \ + "socfpga_legacy_reset_compat=1\0" \ + "smc_fid_rd=0xC2000007\0" \ + "smc_fid_wr=0xC2000008\0" \ + "smc_fid_upd=0xC2000009\0 " +#endif /*#if IS_ENABLED(CONFIG_DISTRO_DEFAULTS)*/ /* * External memory configurations */ +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_1_SIZE (1 * 1024 * 1024 * 1024) +#define CFG_SYS_SDRAM_BASE 0x80000000 +#else #define PHYS_SDRAM_1 0x0 #define PHYS_SDRAM_1_SIZE (1 * 1024 * 1024 * 1024) #define CFG_SYS_SDRAM_BASE 0 +#endif /* * Serial / UART configurations diff --git a/include/configs/starfive-visionfive2.h b/include/configs/starfive-visionfive2.h index 29c74470c71..049b0a06301 100644 --- a/include/configs/starfive-visionfive2.h +++ b/include/configs/starfive-visionfive2.h @@ -15,17 +15,6 @@ #define __io -/* Environment options */ - -#define BOOT_TARGET_DEVICES(func) \ - func(NVME, nvme, 0) \ - func(USB, usb, 0) \ - func(MMC, mmc, 0) \ - func(MMC, mmc, 1) \ - func(DHCP, dhcp, na) - -#include <config_distro_bootcmd.h> - #define TYPE_GUID_SPL "2E54B353-1271-4842-806F-E436D6AF6985" #define TYPE_GUID_UBOOT "BC13C2FF-59E6-4262-A352-B275FD6F7172" #define TYPE_GUID_SYSTEM "EBD0A0A2-B9E5-4433-87C0-68B6B72699C7" @@ -48,7 +37,6 @@ "type_guid_gpt_loader2=" TYPE_GUID_UBOOT "\0" \ "type_guid_gpt_system=" TYPE_GUID_SYSTEM "\0" \ "partitions=" PARTS_DEFAULT "\0" \ - "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ - BOOTENV + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" #endif /* _STARFIVE_VISIONFIVE2_H */ diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h deleted file mode 100644 index 7eadb6d421e..00000000000 --- a/include/configs/stv0991.h +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014, STMicroelectronics - All Rights Reserved - * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. - */ - -#ifndef __CONFIG_STV0991_H -#define __CONFIG_STV0991_H -#define CFG_SYS_EXCEPTION_VECTORS_HIGH - -/* ram memory-related information */ -#define PHYS_SDRAM_1 0x00000000 -#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define PHYS_SDRAM_1_SIZE 0x00198000 - -/* user interface */ - -/* MISC */ -#define CFG_SYS_INIT_RAM_SIZE 0x8000 -#define CFG_SYS_INIT_RAM_ADDR 0x00190000 -/* U-Boot Load Address */ - -/* Misc configuration */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/toybrick_rk3588.h b/include/configs/toybrick_rk3588.h new file mode 100644 index 00000000000..faa2e6c19c3 --- /dev/null +++ b/include/configs/toybrick_rk3588.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + */ + +#ifndef __TOYBRICK_RK3588_H +#define __TOYBRICK_RK3588_H + +#include <configs/rk3588_common.h> + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#endif diff --git a/include/cp1250.h b/include/cp1250.h index adacf8a9580..b762c78d9f6 100644 --- a/include/cp1250.h +++ b/include/cp1250.h @@ -1,10 +1,18 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Constant CP1250 contains the Unicode code points for characters 0x80 - 0xff - * of the code page 1250. + * Constant CP1250 contains the Unicode code points for characters 0x00 - 0x1f + * and 0x80 - 0xff of the code page 1250. */ #define CP1250 { \ + 0x0000, 0x0000, 0x0000, 0x0000, \ + 0x0000, 0x0000, 0x0000, 0x0000, \ + 0x0000, 0x0000, 0x0000, 0x0000, \ + 0x0000, 0x0000, 0x0000, 0x0000, \ + 0x0000, 0x0000, 0x0000, 0x0000, \ + 0x0000, 0x0000, 0x0000, 0x0000, \ + 0x0000, 0x0000, 0x0000, 0x0000, \ + 0x0000, 0x0000, 0x0000, 0x0000, \ 0x20ac, 0x0000, 0x201a, 0x0000, \ 0x201e, 0x2026, 0x2020, 0x2021, \ 0x0000, 0x2030, 0x0160, 0x2039, \ diff --git a/include/cp437.h b/include/cp437.h index 0b2b97132e3..5093130f5ed 100644 --- a/include/cp437.h +++ b/include/cp437.h @@ -1,10 +1,18 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Constant CP437 contains the Unicode code points for characters 0x80 - 0xff - * of the code page 437. + * Constant CP437 contains the Unicode code points for characters 0x00 - 0x1f + * and 0x80 - 0xff of the code page 437. */ #define CP437 { \ + 0x0000, 0x263a, 0x263b, 0x2665, \ + 0x2666, 0x2663, 0x2660, 0x2022, \ + 0x25d8, 0x25cb, 0x25d9, 0x2642, \ + 0x2640, 0x266a, 0x266b, 0x263c, \ + 0x25ba, 0x25c4, 0x2195, 0x203c, \ + 0x00b6, 0x00a7, 0x25ac, 0x21a8, \ + 0x2191, 0x2193, 0x2192, 0x2190, \ + 0x221f, 0x2194, 0x25b2, 0x25bc, \ 0x00c7, 0x00fc, 0x00e9, 0x00e2, \ 0x00e4, 0x00e0, 0x00e5, 0x00e7, \ 0x00ea, 0x00eb, 0x00e8, 0x00ef, \ diff --git a/include/dt-bindings/clock/agilex5-clock.h b/include/dt-bindings/clock/agilex5-clock.h new file mode 100644 index 00000000000..c84fa51540c --- /dev/null +++ b/include/dt-bindings/clock/agilex5-clock.h @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2024, Intel Corporation + */ + +#ifndef __AGILEX5_CLOCK_H +#define __AGILEX5_CLOCK_H + +/* fixed rate clocks */ +#define AGILEX5_OSC1 0 +#define AGILEX5_CB_INTOSC_HS_DIV2_CLK 1 +#define AGILEX5_CB_INTOSC_LS_CLK 2 +#define AGILEX5_L4_SYS_FREE_CLK 3 +#define AGILEX5_F2S_FREE_CLK 4 + +/* PLL clocks */ +#define AGILEX5_MAIN_PLL_CLK 5 +#define AGILEX5_MAIN_PLL_C0_CLK 6 +#define AGILEX5_MAIN_PLL_C1_CLK 7 +#define AGILEX5_MAIN_PLL_C2_CLK 8 +#define AGILEX5_MAIN_PLL_C3_CLK 9 +#define AGILEX5_PERIPH_PLL_CLK 10 +#define AGILEX5_PERIPH_PLL_C0_CLK 11 +#define AGILEX5_PERIPH_PLL_C1_CLK 12 +#define AGILEX5_PERIPH_PLL_C2_CLK 13 +#define AGILEX5_PERIPH_PLL_C3_CLK 14 +#define AGILEX5_MPU_FREE_CLK 15 +#define AGILEX5_MPU_CCU_CLK 16 +#define AGILEX5_BOOT_CLK 17 + +/* fixed factor clocks */ +#define AGILEX5_L3_MAIN_FREE_CLK 18 +#define AGILEX5_NOC_FREE_CLK 19 +#define AGILEX5_S2F_USR0_CLK 20 +#define AGILEX5_NOC_CLK 21 +#define AGILEX5_EMAC_A_FREE_CLK 22 +#define AGILEX5_EMAC_B_FREE_CLK 23 +#define AGILEX5_EMAC_PTP_FREE_CLK 24 +#define AGILEX5_GPIO_DB_FREE_CLK 25 +#define AGILEX5_SDMMC_FREE_CLK 26 +#define AGILEX5_S2F_USER0_FREE_CLK 27 +#define AGILEX5_S2F_USER1_FREE_CLK 28 +#define AGILEX5_PSI_REF_FREE_CLK 29 + +/* Gate clocks */ +#define AGILEX5_MPU_CLK 30 +#define AGILEX5_MPU_PERIPH_CLK 31 +#define AGILEX5_L4_MAIN_CLK 32 +#define AGILEX5_L4_MP_CLK 33 +#define AGILEX5_L4_SP_CLK 34 +#define AGILEX5_CS_AT_CLK 35 +#define AGILEX5_CS_TRACE_CLK 36 +#define AGILEX5_CS_PDBG_CLK 37 +#define AGILEX5_CS_TIMER_CLK 38 +#define AGILEX5_S2F_USER0_CLK 39 +#define AGILEX5_EMAC0_CLK 40 +#define AGILEX5_EMAC1_CLK 41 +#define AGILEX5_EMAC2_CLK 42 +#define AGILEX5_EMAC_PTP_CLK 43 +#define AGILEX5_GPIO_DB_CLK 44 +#define AGILEX5_NAND_CLK 45 +#define AGILEX5_PSI_REF_CLK 46 +#define AGILEX5_S2F_USER1_CLK 47 +#define AGILEX5_SDMMC_CLK 48 +#define AGILEX5_SPI_M_CLK 49 +#define AGILEX5_USB_CLK 50 +#define AGILEX5_NAND_X_CLK 51 +#define AGILEX5_NAND_ECC_CLK 52 +#define AGILEX5_NUM_CLKS 53 + +#endif /* __AGILEX5_CLOCK_H */ diff --git a/include/dt-bindings/reset/altr,rst-mgr-agx5.h b/include/dt-bindings/reset/altr,rst-mgr-agx5.h new file mode 100644 index 00000000000..1dba270aed4 --- /dev/null +++ b/include/dt-bindings/reset/altr,rst-mgr-agx5.h @@ -0,0 +1,80 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2024 Intel Corporation. All rights reserved + */ + +#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_AGX_EDGE_H +#define _DT_BINDINGS_RESET_ALTR_RST_MGR_AGX_EDGE_H + +/* PER0MODRST */ +#define EMAC0_RESET 0 +#define EMAC1_RESET 1 +#define EMAC2_RESET 2 +#define USB0_RESET 3 +#define USB1_RESET 4 +#define NAND_RESET 5 +#define COMBOPHY_RESET 6 +#define SDMMC_RESET 7 +#define EMAC0_OCP_RESET 8 +#define EMAC1_OCP_RESET 9 +#define EMAC2_OCP_RESET 10 +#define USB0_OCP_RESET 11 +#define USB1_OCP_RESET 12 +#define NAND_OCP_RESET 13 +/* 14 is empty */ +#define SDMMC_OCP_RESET 15 +#define DMA_RESET 16 +#define SPIM0_RESET 17 +#define SPIM1_RESET 18 +#define SPIS0_RESET 19 +#define SPIS1_RESET 20 +#define DMA_OCP_RESET 21 +#define EMAC_PTP_RESET 22 +/* 23 is empty*/ +#define DMAIF0_RESET 24 +#define DMAIF1_RESET 25 +#define DMAIF2_RESET 26 +#define DMAIF3_RESET 27 +#define DMAIF4_RESET 28 +#define DMAIF5_RESET 29 +#define DMAIF6_RESET 30 +#define DMAIF7_RESET 31 + +/* PER1MODRST */ +#define WATCHDOG0_RESET 32 +#define WATCHDOG1_RESET 33 +#define WATCHDOG2_RESET 34 +#define WATCHDOG3_RESET 35 +#define L4SYSTIMER0_RESET 36 +#define L4SYSTIMER1_RESET 37 +#define SPTIMER0_RESET 38 +#define SPTIMER1_RESET 39 +#define I2C0_RESET 40 +#define I2C1_RESET 41 +#define I2C2_RESET 42 +#define I2C3_RESET 43 +#define I2C4_RESET 44 +#define I3C0_RESET 45 +#define I3C1_RESET 46 +/* 47 is empty */ +#define UART0_RESET 48 +#define UART1_RESET 49 +/* 50-55 is empty */ +#define GPIO0_RESET 56 +#define GPIO1_RESET 57 +#define WATCHDOG4_RESET 58 +/* 59-63 is empty */ + +/* BRGMODRST */ +#define SOC2FPGA_RESET 64 +#define LWHPS2FPGA_RESET 65 +#define FPGA2SOC_RESET 66 +#define F2SSDRAM_RESET 67 +/* 68-69 is empty */ +#define DDRSCH_RESET 70 +/* 71-95 is empty */ + +/* DBGMODRST */ +#define DBG_RESET 192 + +#endif diff --git a/include/env/phytec/rauc.env b/include/env/phytec/rauc.env new file mode 100644 index 00000000000..89e17ff70ec --- /dev/null +++ b/include/env/phytec/rauc.env @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +/* Logic to select a boot partition based on environment variables and switch + * to the other if the boot fails. */ + +doraucboot=0 + +raucbootpart0=1 +raucrootpart0=5 +raucbootpart1=2 +raucrootpart1=6 + +raucinit= + echo Booting RAUC A/B system; + test -n "${BOOT_ORDER}" || env set BOOT_ORDER "system0 system1"; + test -n "${BOOT_system0_LEFT}" || env set BOOT_system0_LEFT 3; + test -n "${BOOT_system1_LEFT}" || env set BOOT_system1_LEFT 3; + env set raucstatus; + for BOOT_SLOT in "${BOOT_ORDER}"; do + if test "x${raucstatus}" != "x"; then + echo Skipping remaing slots!; + elif test "x${BOOT_SLOT}" = "xsystem0"; then + if test ${BOOT_system0_LEFT} -gt 0; then + echo Found valid slot A, ${BOOT_system0_LEFT} attempts remaining; + setexpr BOOT_system0_LEFT ${BOOT_system0_LEFT} - 1; + env set mmcpart ${raucbootpart0}; + env set mmcroot ${raucrootpart0}; + env set raucargs rauc.slot=system0; + env set raucstatus success; + fi; + elif test "x${BOOT_SLOT}" = "xsystem1"; then + if test ${BOOT_system1_LEFT} -gt 0; then + echo Found valid slot B, ${BOOT_system1_LEFT} attempts remaining; + setexpr BOOT_system1_LEFT ${BOOT_system1_LEFT} - 1; + env set mmcpart ${raucbootpart1}; + env set mmcroot ${raucrootpart1}; + env set raucargs rauc.slot=system1; + env set raucstatus success; + fi; + fi; + done; + if test -n "${raucstatus}"; then + env delete raucstatus; + env save; + else + echo WARN: No valid slot found; + env set BOOT_system0_LEFT 3; + env set BOOT_system1_LEFT 3; + env delete raucstatus; + env save; + reset; + fi; diff --git a/include/k3-clk.h b/include/k3-clk.h index e161f09c0f5..7bc42ecbb0c 100644 --- a/include/k3-clk.h +++ b/include/k3-clk.h @@ -177,6 +177,7 @@ extern const struct ti_k3_clk_platdata j721s2_clk_platdata; extern const struct ti_k3_clk_platdata am62x_clk_platdata; extern const struct ti_k3_clk_platdata am62ax_clk_platdata; extern const struct ti_k3_clk_platdata j784s4_clk_platdata; +extern const struct ti_k3_clk_platdata am62px_clk_platdata; struct clk *clk_register_ti_pll(const char *name, const char *parent_name, void __iomem *reg); diff --git a/include/k3-dev.h b/include/k3-dev.h index a9d1ada8041..0c5ae9aa426 100644 --- a/include/k3-dev.h +++ b/include/k3-dev.h @@ -81,6 +81,7 @@ extern const struct ti_k3_pd_platdata j721s2_pd_platdata; extern const struct ti_k3_pd_platdata am62x_pd_platdata; extern const struct ti_k3_pd_platdata am62ax_pd_platdata; extern const struct ti_k3_pd_platdata j784s4_pd_platdata; +extern const struct ti_k3_pd_platdata am62px_pd_platdata; u8 ti_pd_state(struct ti_pd *pd); u8 lpsc_get_state(struct ti_lpsc *lpsc); diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h index f44e9e8f930..da3d29aabee 100644 --- a/include/linux/arm-smccc.h +++ b/include/linux/arm-smccc.h @@ -55,8 +55,14 @@ #define ARM_SMCCC_QUIRK_NONE 0 #define ARM_SMCCC_QUIRK_QCOM_A6 1 /* Save/restore register a6 */ +#define ARM_SMCCC_VERSION 0x80000000 #define ARM_SMCCC_ARCH_FEATURES 0x80000001 +#define ARM_SMCCC_VERSION_1_0 0x10000 +#define ARM_SMCCC_VERSION_1_1 0x10001 +#define ARM_SMCCC_VERSION_1_2 0x10002 +#define ARM_SMCCC_VERSION_1_3 0x10003 + #define ARM_SMCCC_RET_NOT_SUPPORTED ((unsigned long)-1) #ifndef __ASSEMBLY__ diff --git a/include/power/rk8xx_pmic.h b/include/power/rk8xx_pmic.h index 3cbfc021956..31221aa46b6 100644 --- a/include/power/rk8xx_pmic.h +++ b/include/power/rk8xx_pmic.h @@ -183,7 +183,18 @@ enum { }; enum { + RK806_POWER_SLP_EN0 = 0x06, + RK806_POWER_SLP_EN1, + RK806_POWER_SLP_EN2, + RK806_REG_SYS_CFG3 = 0x72, + RK806_WDT_REG, + RK806_ON_SOURCE, + RK806_OFF_SOURCE +}; + +enum { RK805_ID = 0x8050, + RK806_ID = 0x8060, RK808_ID = 0x0000, RK809_ID = 0x8090, RK816_ID = 0x8160, @@ -201,6 +212,14 @@ enum { #define RK817_POWER_EN_SAVE0 0x99 #define RK817_POWER_EN_SAVE1 0xa4 +#define RK806_POWER_EN(x) (0x00 + (x)) +/* POWER_ENx register lower 4 bits are write-protected unless the associated top bit is set */ +#define RK806_POWER_EN_CLRSETBITS(bit, val) (((val) << (bit)) | (1 << ((bit) + 4))) + +#define RK806_POWER_SLP_EN(x) (0x06 + (x)) + +#define RK806_ID_MSB 0x5a +#define RK806_ID_LSB 0x5b #define RK817_ID_MSB 0xed #define RK817_ID_LSB 0xee #define RK8XX_ID_MSK 0xfff0 @@ -233,7 +252,5 @@ struct rk8xx_priv { }; int rk8xx_spl_configure_buck(struct udevice *pmic, int buck, int uvolt); -int rk818_spl_configure_usb_input_current(struct udevice *pmic, int current_ma); -int rk818_spl_configure_usb_chrg_shutdown(struct udevice *pmic, int uvolt); #endif diff --git a/include/remoteproc.h b/include/remoteproc.h index 91a88791a47..6f8068e1496 100644 --- a/include/remoteproc.h +++ b/include/remoteproc.h @@ -403,6 +403,7 @@ enum rproc_mem_type { * @name: Platform-specific way of naming the Remote proc * @mem_type: one of 'enum rproc_mem_type' * @driver_plat_data: driver specific platform data that may be needed. + * @fw_name: firmware name * * This can be accessed with dev_get_uclass_plat() for any UCLASS_REMOTEPROC * device. @@ -412,6 +413,7 @@ struct dm_rproc_uclass_pdata { const char *name; enum rproc_mem_type mem_type; void *driver_plat_data; + char *fw_name; }; /** @@ -705,6 +707,34 @@ unsigned long rproc_parse_resource_table(struct udevice *dev, struct resource_table *rproc_find_resource_table(struct udevice *dev, unsigned int addr, int *tablesz); +/** + * rproc_set_firmware() - assign a new firmware name + * @rproc_dev: device for which new firmware name is being assigned + * @fw_name: new firmware name to be assigned + * + * This function allows remoteproc drivers or clients to configure a custom + * firmware name. The function does not trigger a remote processor boot, + * only sets the firmware name used for a subsequent boot. + * + * This function sets the fw_name field in uclass pdata of the Remote proc + * + * Return: 0 on success or a negative value upon failure + */ +int rproc_set_firmware(struct udevice *rproc_dev, const char *fw_name); + +/** + * rproc_boot() - boot a remote processor + * @rproc_dev: rproc device to boot + * + * Boot a remote processor (i.e. load its firmware, power it on, ...). + * + * This function first loads the firmware set in the uclass pdata of Remote + * processor to a buffer and then loads firmware to the remote processor + * using rproc_load(). + * + * Return: 0 on success, and an appropriate error value otherwise + */ +int rproc_boot(struct udevice *rproc_dev); #else static inline int rproc_init(void) { return -ENOSYS; } static inline int rproc_dev_init(int id) { return -ENOSYS; } @@ -744,6 +774,10 @@ static inline int rproc_elf_load_rsc_table(struct udevice *dev, ulong fw_addr, ulong fw_size, ulong *rsc_addr, ulong *rsc_size) { return -ENOSYS; } +static inline int rproc_set_firmware(struct udevice *rproc_dev, const char *fw_name) +{ return -ENOSYS; } +static inline int rproc_boot(struct udevice *rproc_dev) +{ return -ENOSYS; } #endif #endif /* _RPROC_H_ */ diff --git a/include/video_console.h b/include/video_console.h index bde67fa9a5a..8b5928dc5eb 100644 --- a/include/video_console.h +++ b/include/video_console.h @@ -43,6 +43,7 @@ enum { * @col_saved: Saved X position, in fractional units (VID_TO_POS(x)) * @row_saved: Saved Y position in pixels (0=top) * @escape_buf: Buffer to accumulate escape sequence + * @utf8_buf: Buffer to accumulate UTF-8 byte sequence */ struct vidconsole_priv { struct stdio_dev sdev; @@ -66,6 +67,7 @@ struct vidconsole_priv { int row_saved; int col_saved; char escape_buf[32]; + char utf8_buf[5]; }; /** @@ -124,12 +126,12 @@ struct vidconsole_ops { * @x_frac: Fractional pixel X position (0=left-most pixel) which * is the X position multipled by VID_FRAC_DIV. * @y: Pixel Y position (0=top-most pixel) - * @ch: Character to write + * @cp: UTF-32 code point to write * @return number of fractional pixels that the cursor should move, * if all is OK, -EAGAIN if we ran out of space on this line, other -ve * on error */ - int (*putc_xy)(struct udevice *dev, uint x_frac, uint y, char ch); + int (*putc_xy)(struct udevice *dev, uint x_frac, uint y, int cp); /** * move_rows() - Move text rows from one place to another @@ -403,12 +405,12 @@ void vidconsole_pop_colour(struct udevice *dev, struct vidconsole_colour *old); * @x_frac: Fractional pixel X position (0=left-most pixel) which * is the X position multipled by VID_FRAC_DIV. * @y: Pixel Y position (0=top-most pixel) - * @ch: Character to write + * @cp: UTF-32 code point to write * Return: number of fractional pixels that the cursor should move, * if all is OK, -EAGAIN if we ran out of space on this line, other -ve * on error */ -int vidconsole_putc_xy(struct udevice *dev, uint x, uint y, char ch); +int vidconsole_putc_xy(struct udevice *dev, uint x, uint y, int cp); /** * vidconsole_move_rows() - Move text rows from one place to another |