summaryrefslogtreecommitdiff
path: root/include
diff options
context:
space:
mode:
Diffstat (limited to 'include')
-rw-r--r--include/configs/MPC8569MDS.h489
-rw-r--r--include/configs/hikey.h4
-rw-r--r--include/configs/mx25pdk.h178
-rw-r--r--include/configs/mx53ard.h170
-rw-r--r--include/configs/mx53smd.h111
-rw-r--r--include/configs/sksimx6.h85
-rw-r--r--include/configs/vexpress_aemv8a.h3
-rw-r--r--include/malloc.h3
-rw-r--r--include/u-boot/rsa-mod-exp.h2
9 files changed, 9 insertions, 1036 deletions
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
deleted file mode 100644
index f50f53ec3fc..00000000000
--- a/include/configs/MPC8569MDS.h
+++ /dev/null
@@ -1,489 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2009-2011 Freescale Semiconductor, Inc.
- */
-
-/*
- * mpc8569mds board configuration file
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_SYS_SRIO
-#define CONFIG_SRIO1 /* SRIO port 1 */
-
-#define CONFIG_PCIE1 1 /* PCIE controller */
-#define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
-#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-
-#ifndef __ASSEMBLY__
-extern unsigned long get_clock_freq(void);
-#endif
-/* Replace a call to get_clock_freq (after it is implemented)*/
-#define CONFIG_SYS_CLK_FREQ 66666666
-#define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ
-
-#ifdef CONFIG_ATM
-#define CONFIG_PQ_MDS_PIB
-#define CONFIG_PQ_MDS_PIB_ATM
-#endif
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE /* toggle L2 cache */
-#define CONFIG_BTB /* toggle branch predition */
-
-#ifndef CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-#endif
-
-/*
- * Only possible on E500 Version 2 or newer cores.
- */
-#define CONFIG_ENABLE_36BIT_PHYS 1
-
-#define CONFIG_HWCONFIG
-
-/*
- * Config the L2 Cache as L2 SRAM
- */
-#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
-#define CONFIG_SYS_L2_SIZE (512 << 10)
-#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
-
-#define CONFIG_SYS_CCSRBAR 0xe0000000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
-
-#if defined(CONFIG_NAND_SPL)
-#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
-#endif
-
-/* DDR Setup */
-#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
-#define CONFIG_DDR_SPD
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
-
-#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
- /* DDR is system memory*/
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
-
-/* I2C addresses of SPD EEPROMs */
-#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
-
-/* These are used when DDR doesn't use SPD. */
-#define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1024MB */
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
-#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
-#define CONFIG_SYS_DDR_TIMING_3 0x00020000
-#define CONFIG_SYS_DDR_TIMING_0 0x00330004
-#define CONFIG_SYS_DDR_TIMING_1 0x6F6B4644
-#define CONFIG_SYS_DDR_TIMING_2 0x002888D0
-#define CONFIG_SYS_DDR_SDRAM_CFG 0x47000000
-#define CONFIG_SYS_DDR_SDRAM_CFG_2 0x04401040
-#define CONFIG_SYS_DDR_SDRAM_MODE 0x40401521
-#define CONFIG_SYS_DDR_SDRAM_MODE_2 0x8000C000
-#define CONFIG_SYS_DDR_SDRAM_INTERVAL 0x03E00000
-#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
-#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x01000000
-#define CONFIG_SYS_DDR_TIMING_4 0x00220001
-#define CONFIG_SYS_DDR_TIMING_5 0x03402400
-#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600
-#define CONFIG_SYS_DDR_WRLVL_CNTL 0x0655A604
-#define CONFIG_SYS_DDR_CDR_1 0x80040000
-#define CONFIG_SYS_DDR_CDR_2 0x00000000
-#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
-#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
-#define CONFIG_SYS_DDR_CONTROL 0xc7000000 /* Type = DDR3 */
-#define CONFIG_SYS_DDR_CONTROL2 0x24400000
-
-#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
-#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
-#define CONFIG_SYS_DDR_SBE 0x00010000
-
-/*
- * Local Bus Definitions
- */
-
-#define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */
-#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
-
-#define CONFIG_SYS_BCSR_BASE 0xf8000000
-#define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE
-
-/*Chip select 0 - Flash*/
-#define CONFIG_FLASH_BR_PRELIM 0xfe000801
-#define CONFIG_FLASH_OR_PRELIM 0xfe000ff7
-
-/*Chip select 1 - BCSR*/
-#define CONFIG_SYS_BR1_PRELIM 0xf8000801
-#define CONFIG_SYS_OR1_PRELIM 0xffffe9f7
-
-/*Chip select 4 - PIB*/
-#define CONFIG_SYS_BR4_PRELIM 0xf8008801
-#define CONFIG_SYS_OR4_PRELIM 0xffffe9f7
-
-/*Chip select 5 - PIB*/
-#define CONFIG_SYS_BR5_PRELIM 0xf8010801
-#define CONFIG_SYS_OR5_PRELIM 0xffffe9f7
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-#undef CONFIG_SYS_RAMBOOT
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-/* Chip select 3 - NAND */
-#ifndef CONFIG_NAND_SPL
-#define CONFIG_SYS_NAND_BASE 0xFC000000
-#else
-#define CONFIG_SYS_NAND_BASE 0xFFF00000
-#endif
-
-/* NAND boot: 4K NAND loader config */
-#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
-#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
-#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
-#define CONFIG_SYS_NAND_U_BOOT_START \
- (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
-#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
-#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
-#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
-
-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_NAND_FSL_ELBC 1
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
-#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \
- | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
- | BR_PS_8 /* Port Size = 8 bit */ \
- | BR_MS_FCM /* MSEL = FCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
- | OR_FCM_CSCT \
- | OR_FCM_CST \
- | OR_FCM_CHT \
- | OR_FCM_SCY_1 \
- | OR_FCM_TRLX \
- | OR_FCM_EHTR)
-
-#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
-#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
-#define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
-#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-
-#define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */
-#define CONFIG_SYS_LBC_LBCR 0x00040000 /* LB config reg */
-#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
-#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
-
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
-
-/* Serial Port */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-#ifdef CONFIG_NAND_SPL
-#define CONFIG_NS16550_MIN_FUNCTIONS
-#endif
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
-
-/*
- * I2C2 EEPROM
- */
-#define CONFIG_ID_EEPROM
-#ifdef CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#endif
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_BUS_NUM 1
-
-#define PLPPAR1_I2C_BIT_MASK 0x0000000F
-#define PLPPAR1_I2C2_VAL 0x00000000
-#define PLPPAR1_ESDHC_VAL 0x0000000A
-#define PLPDIR1_I2C_BIT_MASK 0x0000000F
-#define PLPDIR1_I2C2_VAL 0x0000000F
-#define PLPDIR1_ESDHC_VAL 0x00000006
-#define PLPPAR1_UART0_BIT_MASK 0x00000fc0
-#define PLPPAR1_ESDHC_4BITS_VAL 0x00000a80
-#define PLPDIR1_UART0_BIT_MASK 0x00000fc0
-#define PLPDIR1_ESDHC_4BITS_VAL 0x00000a80
-
-/*
- * General PCI
- * Memory Addresses are mapped 1-1. I/O is mapped from 0
- */
-#define CONFIG_SYS_PCIE1_NAME "Slot"
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
-
-#define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000
-#define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000
-#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS
-#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
-
-#ifdef CONFIG_QE
-/*
- * QE UEC ethernet configuration
- */
-#define CONFIG_SYS_UCC_RGMII_MODE /* Set UCC work at RGMII by default */
-#undef CONFIG_SYS_UCC_RMII_MODE /* Set UCC work at RMII mode */
-
-#define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
-#define CONFIG_UEC_ETH
-#define CONFIG_ETHPRIME "UEC0"
-#define CONFIG_PHY_MODE_NEED_CHANGE
-
-#define CONFIG_UEC_ETH1 /* GETH1 */
-#define CONFIG_HAS_ETH0
-
-#ifdef CONFIG_UEC_ETH1
-#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
-#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE
-#if defined(CONFIG_SYS_UCC_RGMII_MODE)
-#define CONFIG_SYS_UEC1_TX_CLK QE_CLK12
-#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
-#define CONFIG_SYS_UEC1_PHY_ADDR 7
-#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
-#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
-#elif defined(CONFIG_SYS_UCC_RMII_MODE)
-#define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 /* CLK16 for RMII */
-#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
-#define CONFIG_SYS_UEC1_PHY_ADDR 8 /* 0x8 for RMII */
-#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
-#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
-#endif /* CONFIG_SYS_UCC_RGMII_MODE */
-#endif /* CONFIG_UEC_ETH1 */
-
-#define CONFIG_UEC_ETH2 /* GETH2 */
-#define CONFIG_HAS_ETH1
-
-#ifdef CONFIG_UEC_ETH2
-#define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
-#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE
-#if defined(CONFIG_SYS_UCC_RGMII_MODE)
-#define CONFIG_SYS_UEC2_TX_CLK QE_CLK17
-#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
-#define CONFIG_SYS_UEC2_PHY_ADDR 1
-#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
-#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
-#elif defined(CONFIG_SYS_UCC_RMII_MODE)
-#define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 /* CLK 16 for RMII */
-#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
-#define CONFIG_SYS_UEC2_PHY_ADDR 0x9 /* 0x9 for RMII */
-#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
-#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
-#endif /* CONFIG_SYS_UCC_RGMII_MODE */
-#endif /* CONFIG_UEC_ETH2 */
-
-#define CONFIG_UEC_ETH3 /* GETH3 */
-#define CONFIG_HAS_ETH2
-
-#ifdef CONFIG_UEC_ETH3
-#define CONFIG_SYS_UEC3_UCC_NUM 2 /* UCC3 */
-#define CONFIG_SYS_UEC3_RX_CLK QE_CLK_NONE
-#if defined(CONFIG_SYS_UCC_RGMII_MODE)
-#define CONFIG_SYS_UEC3_TX_CLK QE_CLK12
-#define CONFIG_SYS_UEC3_ETH_TYPE GIGA_ETH
-#define CONFIG_SYS_UEC3_PHY_ADDR 2
-#define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
-#define CONFIG_SYS_UEC3_INTERFACE_SPEED 1000
-#elif defined(CONFIG_SYS_UCC_RMII_MODE)
-#define CONFIG_SYS_UEC3_TX_CLK QE_CLK16 /* CLK_16 for RMII */
-#define CONFIG_SYS_UEC3_ETH_TYPE FAST_ETH
-#define CONFIG_SYS_UEC3_PHY_ADDR 0xA /* 0xA for RMII */
-#define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
-#define CONFIG_SYS_UEC3_INTERFACE_SPEED 100
-#endif /* CONFIG_SYS_UCC_RGMII_MODE */
-#endif /* CONFIG_UEC_ETH3 */
-
-#define CONFIG_UEC_ETH4 /* GETH4 */
-#define CONFIG_HAS_ETH3
-
-#ifdef CONFIG_UEC_ETH4
-#define CONFIG_SYS_UEC4_UCC_NUM 3 /* UCC4 */
-#define CONFIG_SYS_UEC4_RX_CLK QE_CLK_NONE
-#if defined(CONFIG_SYS_UCC_RGMII_MODE)
-#define CONFIG_SYS_UEC4_TX_CLK QE_CLK17
-#define CONFIG_SYS_UEC4_ETH_TYPE GIGA_ETH
-#define CONFIG_SYS_UEC4_PHY_ADDR 3
-#define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
-#define CONFIG_SYS_UEC4_INTERFACE_SPEED 1000
-#elif defined(CONFIG_SYS_UCC_RMII_MODE)
-#define CONFIG_SYS_UEC4_TX_CLK QE_CLK16 /* CLK16 for RMII */
-#define CONFIG_SYS_UEC4_ETH_TYPE FAST_ETH
-#define CONFIG_SYS_UEC4_PHY_ADDR 0xB /* 0xB for RMII */
-#define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
-#define CONFIG_SYS_UEC4_INTERFACE_SPEED 100
-#endif /* CONFIG_SYS_UCC_RGMII_MODE */
-#endif /* CONFIG_UEC_ETH4 */
-
-#undef CONFIG_UEC_ETH6 /* GETH6 */
-#define CONFIG_HAS_ETH5
-
-#ifdef CONFIG_UEC_ETH6
-#define CONFIG_SYS_UEC6_UCC_NUM 5 /* UCC6 */
-#define CONFIG_SYS_UEC6_RX_CLK QE_CLK_NONE
-#define CONFIG_SYS_UEC6_TX_CLK QE_CLK_NONE
-#define CONFIG_SYS_UEC6_ETH_TYPE GIGA_ETH
-#define CONFIG_SYS_UEC6_PHY_ADDR 4
-#define CONFIG_SYS_UEC6_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII
-#define CONFIG_SYS_UEC6_INTERFACE_SPEED 1000
-#endif /* CONFIG_UEC_ETH6 */
-
-#undef CONFIG_UEC_ETH8 /* GETH8 */
-#define CONFIG_HAS_ETH7
-
-#ifdef CONFIG_UEC_ETH8
-#define CONFIG_SYS_UEC8_UCC_NUM 7 /* UCC8 */
-#define CONFIG_SYS_UEC8_RX_CLK QE_CLK_NONE
-#define CONFIG_SYS_UEC8_TX_CLK QE_CLK_NONE
-#define CONFIG_SYS_UEC8_ETH_TYPE GIGA_ETH
-#define CONFIG_SYS_UEC8_PHY_ADDR 6
-#define CONFIG_SYS_UEC8_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII
-#define CONFIG_SYS_UEC8_INTERFACE_SPEED 1000
-#endif /* CONFIG_UEC_ETH8 */
-
-#endif /* CONFIG_QE */
-
-#if defined(CONFIG_PCI)
-
-#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-
-#endif /* CONFIG_PCI */
-
-/*
- * Environment
- */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-/* QE microcode/firmware address */
-#define CONFIG_SYS_QE_FW_ADDR 0xfff00000
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#ifdef CONFIG_MMC
-#define CONFIG_FSL_ESDHC_PIN_MUX
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 2048 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
- /* Boot Argument Buffer Size */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-#define CONFIG_HOSTNAME "mpc8569mds"
-#define CONFIG_ROOTPATH "/nfsroot"
-#define CONFIG_BOOTFILE "your.uImage"
-
-#define CONFIG_SERVERIP 192.168.1.1
-#define CONFIG_GATEWAYIP 192.168.1.1
-#define CONFIG_NETMASK 255.255.255.0
-
-#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=600000\0" \
- "ramdiskfile=your.ramdisk.u-boot\0" \
- "fdtaddr=400000\0" \
- "fdtfile=your.fdt.dtb\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs\0" \
- "ramargs=setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs\0" \
-
-#define CONFIG_NFSBOOTCOMMAND \
- "run nfsargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "run ramargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "bootm $loadaddr $ramdiskaddr"
-
-#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/hikey.h b/include/configs/hikey.h
index a323a0bf69b..659fbee052d 100644
--- a/include/configs/hikey.h
+++ b/include/configs/hikey.h
@@ -47,9 +47,7 @@
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_8M)
-#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_DWC2_REG_ADDR 0xF72C0000
-/*#define CONFIG_DWC2_DFLT_SPEED_FULL*/
+#ifdef CONFIG_USB_DWC2
#define CONFIG_DWC2_ENABLE_DYNAMIC_FIFO
#endif
diff --git a/include/configs/mx25pdk.h b/include/configs/mx25pdk.h
deleted file mode 100644
index 27d0c25ac73..00000000000
--- a/include/configs/mx25pdk.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2011 Freescale Semiconductor, Inc.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <asm/arch/imx-regs.h>
-
-/* High Level Configuration Options */
-
-#define CONFIG_SYS_TEXT_BASE 0x81200000
-#define CONFIG_SYS_FSL_CLK
-
-#define CONFIG_SYS_TIMER_RATE 32768
-#define CONFIG_SYS_TIMER_COUNTER \
- (&((struct gpt_regs *)IMX_GPT1_BASE)->counter)
-
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
-#define CONFIG_MACH_TYPE MACH_TYPE_MX25_3DS
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
-
-/* Physical Memory Map */
-
-#define PHYS_SDRAM_1 0x80000000
-#define PHYS_SDRAM_1_SIZE (64 * 1024 * 1024)
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_ADDR IMX_RAM_BASE
-#define CONFIG_SYS_INIT_RAM_SIZE IMX_RAM_SIZE
-
-#define CONFIG_SYS_INIT_SP_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-
-/* Memory Test */
-
-/* Serial Info */
-#define CONFIG_MXC_UART_BASE UART1_BASE
-
-/* No NOR flash present */
-
-/* U-Boot general configuration */
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-/* Ethernet */
-#define CONFIG_FEC_MXC
-#define CONFIG_FEC_MXC_PHYADDR 0x1f
-
-/* ESDHC driver */
-#define CONFIG_SYS_FSL_ESDHC_ADDR IMX_MMC_SDHC1_BASE
-#define CONFIG_SYS_FSL_ESDHC_NUM 1
-
-/* PMIC Configs */
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
-#define CONFIG_POWER_FSL
-#define CONFIG_POWER_FSL_MC34704
-#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x54
-
-/* I2C Configs */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-
-/* RTC */
-#define CONFIG_RTC_IMXDI
-
-/* Fuse API support */
-#define CONFIG_FSL_IIM
-
-/* Ethernet Configs */
-
-
-#define CONFIG_LOADADDR 0x81000000 /* loadaddr env var */
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "script=boot.scr\0" \
- "image=zImage\0" \
- "console=ttymxc0\0" \
- "splashpos=m,m\0" \
- "fdt_high=0xffffffff\0" \
- "initrd_high=0xffffffff\0" \
- "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
- "fdt_addr=0x82000000\0" \
- "boot_fdt=try\0" \
- "ip_dyn=yes\0" \
- "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
- "mmcpart=1\0" \
- "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
- "update_sd_firmware_filename=u-boot.imx\0" \
- "update_sd_firmware=" \
- "if test ${ip_dyn} = yes; then " \
- "setenv get_cmd dhcp; " \
- "else " \
- "setenv get_cmd tftp; " \
- "fi; " \
- "if mmc dev ${mmcdev}; then " \
- "if ${get_cmd} ${update_sd_firmware_filename}; then " \
- "setexpr fw_sz ${filesize} / 0x200; " \
- "setexpr fw_sz ${fw_sz} + 1; " \
- "mmc write ${loadaddr} 0x2 ${fw_sz}; " \
- "fi; " \
- "fi\0" \
- "mmcargs=setenv bootargs console=${console},${baudrate} " \
- "root=${mmcroot}\0" \
- "loadbootscript=" \
- "load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
- "bootscript=echo Running bootscript from mmc ...; " \
- "source\0" \
- "loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
- "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
- "mmcboot=echo Booting from mmc ...; " \
- "run mmcargs; " \
- "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
- "if run loadfdt; then " \
- "bootz ${loadaddr} - ${fdt_addr}; " \
- "else " \
- "if test ${boot_fdt} = try; then " \
- "bootz; " \
- "else " \
- "echo WARN: Cannot load the DT; " \
- "fi; " \
- "fi; " \
- "else " \
- "bootz; " \
- "fi;\0" \
- "netargs=setenv bootargs console=${console},${baudrate} " \
- "root=/dev/nfs " \
- "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
- "netboot=echo Booting from net ...; " \
- "run netargs; " \
- "if test ${ip_dyn} = yes; then " \
- "setenv get_cmd dhcp; " \
- "else " \
- "setenv get_cmd tftp; " \
- "fi; " \
- "${get_cmd} ${image}; " \
- "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
- "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
- "bootz ${loadaddr} - ${fdt_addr}; " \
- "else " \
- "if test ${boot_fdt} = try; then " \
- "bootz; " \
- "else " \
- "echo WARN: Cannot load the DT; " \
- "fi; " \
- "fi; " \
- "else " \
- "bootz; " \
- "fi;\0"
-
-#define CONFIG_BOOTCOMMAND \
- "mmc dev ${mmcdev}; if mmc rescan; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loadimage; then " \
- "run mmcboot; " \
- "else run netboot; " \
- "fi; " \
- "fi; " \
- "else run netboot; fi"
-
-/* Miscellaneous configurable options */
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h
deleted file mode 100644
index b613e9816da..00000000000
--- a/include/configs/mx53ard.h
+++ /dev/null
@@ -1,170 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2011 Freescale Semiconductor, Inc.
- *
- * Configuration settings for the MX53ARD Freescale board.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_MACH_TYPE MACH_TYPE_MX53_ARD
-
-#include <asm/arch/imx-regs.h>
-
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_REVISION_TAG
-
-#define CONFIG_SYS_FSL_CLK
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
-
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR_AXI
-#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI
-#define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR
-#define CONFIG_SYS_NAND_LARGEPAGE
-#define CONFIG_MXC_NAND_HWECC
-
-#define CONFIG_MXC_UART_BASE UART1_BASE
-
-/* I2C Configs */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
-
-/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_FSL_ESDHC_NUM 2
-
-/* Eth Configs */
-#define CONFIG_HAS_ETH1
-
-/* Command definition */
-
-#define CONFIG_ETHPRIME "smc911x"
-
-#define CONFIG_LOADADDR 0x72000000 /* loadaddr env var */
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "script=boot.scr\0" \
- "uimage=zImage\0" \
- "console=ttymxc0\0" \
- "fdt_high=0xffffffff\0" \
- "initrd_high=0xffffffff\0" \
- "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
- "fdt_addr=0x78000000\0" \
- "boot_fdt=try\0" \
- "ip_dyn=yes\0" \
- "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
- "mmcpart=1\0" \
- "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
- "update_sd_firmware_filename=u-boot.imx\0" \
- "update_sd_firmware=" \
- "if test ${ip_dyn} = yes; then " \
- "setenv get_cmd dhcp; " \
- "else " \
- "setenv get_cmd tftp; " \
- "fi; " \
- "if mmc dev ${mmcdev}; then " \
- "if ${get_cmd} ${update_sd_firmware_filename}; then " \
- "setexpr fw_sz ${filesize} / 0x200; " \
- "setexpr fw_sz ${fw_sz} + 1; " \
- "mmc write ${loadaddr} 0x2 ${fw_sz}; " \
- "fi; " \
- "fi\0" \
- "mmcargs=setenv bootargs console=${console},${baudrate} " \
- "root=${mmcroot}\0" \
- "loadbootscript=" \
- "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
- "bootscript=echo Running bootscript from mmc ...; " \
- "source\0" \
- "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
- "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
- "mmcboot=echo Booting from mmc ...; " \
- "run mmcargs; " \
- "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
- "if run loadfdt; then " \
- "bootz ${loadaddr} - ${fdt_addr}; " \
- "else " \
- "if test ${boot_fdt} = try; then " \
- "bootz; " \
- "else " \
- "echo WARN: Cannot load the DT; " \
- "fi; " \
- "fi; " \
- "else " \
- "bootz; " \
- "fi;\0" \
- "netargs=setenv bootargs console=${console},${baudrate} " \
- "root=/dev/nfs " \
- "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
- "netboot=echo Booting from net ...; " \
- "run netargs; " \
- "if test ${ip_dyn} = yes; then " \
- "setenv get_cmd dhcp; " \
- "else " \
- "setenv get_cmd tftp; " \
- "fi; " \
- "${get_cmd} ${uimage}; " \
- "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
- "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
- "bootz ${loadaddr} - ${fdt_addr}; " \
- "else " \
- "if test ${boot_fdt} = try; then " \
- "bootz; " \
- "else " \
- "echo WARN: Cannot load the DT; " \
- "fi; " \
- "fi; " \
- "else " \
- "bootz; " \
- "fi;\0"
-
-#define CONFIG_BOOTCOMMAND \
- "mmc dev ${mmcdev}; if mmc rescan; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loaduimage; then " \
- "run mmcboot; " \
- "else run netboot; " \
- "fi; " \
- "fi; " \
- "else run netboot; fi"
-
-#define CONFIG_ARP_TIMEOUT 200UL
-
-/* Miscellaneous configurable options */
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
-/* Physical Memory Map */
-#define PHYS_SDRAM_1 CSD0_BASE_ADDR
-#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
-#define PHYS_SDRAM_2 CSD1_BASE_ADDR
-#define PHYS_SDRAM_2_SIZE (512 * 1024 * 1024)
-#define PHYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
-
-#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
-#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
-#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
-
-#define CONFIG_SYS_INIT_SP_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-
-/* environment organization */
-
-#define MX53ARD_CS1GCR1 (CSEN | DSZ(2))
-#define MX53ARD_CS1RCR1 (RCSN(2) | OEN (1) | RWSC(22))
-#define MX53ARD_CS1RCR2 RBEN(2)
-#define MX53ARD_CS1WCR1 (WCSN(2) | WEN(2) | WBEN(2) | WWSC(22))
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/mx53smd.h b/include/configs/mx53smd.h
deleted file mode 100644
index 79c86725a27..00000000000
--- a/include/configs/mx53smd.h
+++ /dev/null
@@ -1,111 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2011 Freescale Semiconductor, Inc.
- *
- * Configuration settings for the MX53SMD Freescale board.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_MACH_TYPE MACH_TYPE_MX53_SMD
-
-#include <asm/arch/imx-regs.h>
-
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_REVISION_TAG
-
-#define CONFIG_SYS_FSL_CLK
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
-
-#define CONFIG_MXC_UART_BASE UART1_BASE
-
-/* I2C Configs */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
-
-/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_FSL_ESDHC_NUM 1
-
-/* Eth Configs */
-#define CONFIG_HAS_ETH1
-
-#define CONFIG_FEC_MXC
-#define IMX_FEC_BASE FEC_BASE_ADDR
-#define CONFIG_FEC_MXC_PHYADDR 0x1F
-
-/* Command definition */
-
-#define CONFIG_ETHPRIME "FEC0"
-
-#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "script=boot.scr\0" \
- "uimage=uImage\0" \
- "mmcdev=0\0" \
- "mmcpart=2\0" \
- "mmcroot=/dev/mmcblk0p3 rw\0" \
- "mmcrootfstype=ext3 rootwait\0" \
- "mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \
- "root=${mmcroot} " \
- "rootfstype=${mmcrootfstype}\0" \
- "loadbootscript=" \
- "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
- "bootscript=echo Running bootscript from mmc ...; " \
- "source\0" \
- "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
- "mmcboot=echo Booting from mmc ...; " \
- "run mmcargs; " \
- "bootm\0" \
- "netargs=setenv bootargs console=ttymxc0,${baudrate} " \
- "root=/dev/nfs " \
- "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
- "netboot=echo Booting from net ...; " \
- "run netargs; " \
- "dhcp ${uimage}; bootm\0" \
-
-#define CONFIG_BOOTCOMMAND \
- "mmc dev ${mmcdev}; if mmc rescan; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loaduimage; then " \
- "run mmcboot; " \
- "else run netboot; " \
- "fi; " \
- "fi; " \
- "else run netboot; fi"
-#define CONFIG_ARP_TIMEOUT 200UL
-
-/* Miscellaneous configurable options */
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
-/* Physical Memory Map */
-#define PHYS_SDRAM_1 CSD0_BASE_ADDR
-#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
-#define PHYS_SDRAM_2 CSD1_BASE_ADDR
-#define PHYS_SDRAM_2_SIZE (512 * 1024 * 1024)
-#define PHYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
-
-#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
-#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
-#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
-
-#define CONFIG_SYS_INIT_SP_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-
-/* environment organization */
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/sksimx6.h b/include/configs/sksimx6.h
deleted file mode 100644
index 7052d8049e4..00000000000
--- a/include/configs/sksimx6.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) Stefano Babic <sbabic@denx.de>
- */
-
-
-#ifndef __SKSIMX6_CONFIG_H
-#define __SKSIMX6_CONFIG_H
-
-#include "mx6_common.h"
-#include "imx6_spl.h"
-
-/* Serial */
-#define CONFIG_MXC_UART_BASE UART1_BASE
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (8 * SZ_1M)
-
-/* Ethernet */
-#define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE RGMII
-#define CONFIG_ETHPRIME "FEC"
-#define CONFIG_FEC_MXC_PHYADDR 0x01
-
-#define CONFIG_PHY_MICREL_KSZ9021
-
-/* I2C Configs */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C2
-#define CONFIG_SYS_I2C_SPEED 100000
-
-/* Filesystem support */
-
-/* Physical Memory Map */
-#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
-
-#define CONFIG_SYS_INIT_SP_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-
-/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_FSL_USDHC_NUM 1
-
-/* Environment organization */
-
-/* Default environment */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "addcons=setenv bootargs ${bootargs} " \
- "console=${console},${baudrate}\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:" \
- "${netmask}:${hostname}:${netdev}:off\0" \
- "addmisc=setenv bootargs ${bootargs} ${miscargs}\0" \
- "bootcmd=run mmcboot\0" \
- "bootfile=uImage\0" \
- "bootimage=uImage\0" \
- "console=ttymxc0\0" \
- "fdt_addr_r=0x18000000\0" \
- "fdt_file=imx6dl-sks-cts.dtb\0" \
- "fdt_high=0xffffffff\0" \
- "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
- "miscargs=quiet\0" \
- "mmcargs=setenv bootargs root=${mmcroot} rw rootwait\0" \
- "mmcboot=if run mmcload;then " \
- "run mmcargs addcons addmisc;" \
- "bootm;fi\0" \
- "mmcload=mmc rescan;" \
- "load mmc 0:${mmcpart} ${kernel_addr_r} boot/fitImage\0"\
- "mmcpart=1\0" \
- "mmcroot=/dev/mmcblk0p1\0" \
- "net_nfs=tftp ${kernel_addr_r} ${board_name}/${bootfile};" \
- "tftp ${fdt_addr_r} ${board_name}/${fdt_file};" \
- "run nfsargs addip addcons addmisc;" \
- "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
- "nfsargs=setenv bootargs root=/dev/nfs " \
- "nfsroot=${serverip}:${nfsroot},v3 panic=1\0"
-
-#endif
diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h
index 566bee5b87b..7318fb6c585 100644
--- a/include/configs/vexpress_aemv8a.h
+++ b/include/configs/vexpress_aemv8a.h
@@ -117,6 +117,9 @@
#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
#define PHYS_SDRAM_2 (0x880000000)
#define PHYS_SDRAM_2_SIZE 0x180000000
+#elif CONFIG_TARGET_VEXPRESS64_BASE_FVP && CONFIG_NR_DRAM_BANKS == 2
+#define PHYS_SDRAM_2 (0x880000000)
+#define PHYS_SDRAM_2_SIZE 0x80000000
#endif
/* Enable memtest */
diff --git a/include/malloc.h b/include/malloc.h
index f66c2e86176..e15e528a2e3 100644
--- a/include/malloc.h
+++ b/include/malloc.h
@@ -361,8 +361,11 @@ extern "C" {
#if (__STD_C || defined(HAVE_MEMCPY))
#if __STD_C
+/* U-Boot defines memset() and memcpy in /include/linux/string.h
void* memset(void*, int, size_t);
void* memcpy(void*, const void*, size_t);
+*/
+#include <linux/string.h>
#else
#ifdef WIN32
/* On Win32 platforms, 'memset()' and 'memcpy()' are already declared in */
diff --git a/include/u-boot/rsa-mod-exp.h b/include/u-boot/rsa-mod-exp.h
index 7b7c2915a94..fc9557c7819 100644
--- a/include/u-boot/rsa-mod-exp.h
+++ b/include/u-boot/rsa-mod-exp.h
@@ -9,6 +9,8 @@
#include <errno.h>
#include <image.h>
+struct udevice;
+
/**
* struct key_prop - holder for a public key properties
*
generated by cgit v1.2.3 (git 2.0.4) at 2025-07-24 12:06:49 +0000