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-rw-r--r--include/asm-generic/pe.h3
-rw-r--r--include/bootcount.h50
-rw-r--r--include/charset.h3
-rw-r--r--include/configs/ls1088a_common.h5
-rw-r--r--include/configs/xilinx_zynqmp_r5.h51
-rw-r--r--include/configs/xilinx_zynqmp_zc1275_revB.h15
-rw-r--r--include/efi_driver.h3
-rw-r--r--include/efi_loader.h3
-rw-r--r--include/efi_selftest.h3
-rw-r--r--include/fsl-mc/fsl_dpbp.h2
-rw-r--r--include/fsl-mc/fsl_dpio.h2
-rw-r--r--include/fsl-mc/fsl_dpmac.h2
-rw-r--r--include/fsl-mc/fsl_dpni.h2
-rw-r--r--include/fsl-mc/fsl_dprc.h2
-rw-r--r--include/fsl-mc/fsl_mc_cmd.h2
-rw-r--r--include/fsl-mc/fsl_mc_private.h2
-rw-r--r--include/fsl_ifc.h4
-rw-r--r--include/image.h4
-rw-r--r--include/linux/log2.h63
-rw-r--r--include/net.h2
-rw-r--r--include/pe.h3
-rw-r--r--include/sdhci.h8
-rw-r--r--include/zynqmp_tap_delay.h19
-rw-r--r--include/zynqpl.h89
24 files changed, 233 insertions, 109 deletions
diff --git a/include/asm-generic/pe.h b/include/asm-generic/pe.h
index d1683f238af..9a8b5e82e38 100644
--- a/include/asm-generic/pe.h
+++ b/include/asm-generic/pe.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Portable Executable and Common Object Constants
*
@@ -5,8 +6,6 @@
*
* based on the "Microsoft Portable Executable and Common Object File Format
* Specification", revision 11, 2017-01-23
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_PE_H
diff --git a/include/bootcount.h b/include/bootcount.h
index 3eb802470a2..671adcc4101 100644
--- a/include/bootcount.h
+++ b/include/bootcount.h
@@ -3,11 +3,15 @@
* (C) Copyright 2012
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*/
+#ifndef _BOOTCOUNT_H__
+#define _BOOTCOUNT_H__
#include <common.h>
#include <asm/io.h>
#include <asm/byteorder.h>
+#if defined(CONFIG_SPL_BOOTCOUNT_LIMIT) || defined(CONFIG_BOOTCOUNT_LIMIT)
+
#if !defined(CONFIG_SYS_BOOTCOUNT_LE) && !defined(CONFIG_SYS_BOOTCOUNT_BE)
# if __BYTE_ORDER == __LITTLE_ENDIAN
# define CONFIG_SYS_BOOTCOUNT_LE
@@ -37,3 +41,49 @@ static inline u32 raw_bootcount_load(volatile u32 *addr)
return in_be32(addr);
}
#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+static inline int bootcount_error(void)
+{
+ unsigned long bootcount = bootcount_load();
+ unsigned long bootlimit = env_get_ulong("bootlimit", 10, 0);
+
+ if (bootlimit && bootcount > bootlimit) {
+ printf("Warning: Bootlimit (%lu) exceeded.", bootlimit);
+ if (!(gd->flags & GD_FLG_SPL_INIT))
+ printf(" Using altbootcmd.");
+ printf("\n");
+
+ return 1;
+ }
+
+ return 0;
+}
+
+static inline void bootcount_inc(void)
+{
+ unsigned long bootcount = bootcount_load();
+
+ if (gd->flags & GD_FLG_SPL_INIT) {
+ bootcount_store(++bootcount);
+ return;
+ }
+
+#ifndef CONFIG_SPL_BUILD
+ /* Only increment bootcount when no bootcount support in SPL */
+#ifndef CONFIG_SPL_BOOTCOUNT_LIMIT
+ bootcount_store(++bootcount);
+#endif
+ env_set_ulong("bootcount", bootcount);
+#endif /* !CONFIG_SPL_BUILD */
+}
+
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_BOOTCOUNT_LIMIT)
+void bootcount_store(ulong a) {};
+ulong bootcount_load(void) { return 0; }
+#endif /* CONFIG_SPL_BUILD && !CONFIG_SPL_BOOTCOUNT_LIMIT */
+#else
+static inline int bootcount_error(void) { return 0; }
+static inline void bootcount_inc(void) {}
+#endif /* CONFIG_SPL_BOOTCOUNT_LIMIT || CONFIG_BOOTCOUNT_LIMIT */
+#endif /* _BOOTCOUNT_H__ */
diff --git a/include/charset.h b/include/charset.h
index 2662c2f7c9a..11832cbd122 100644
--- a/include/charset.h
+++ b/include/charset.h
@@ -1,9 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* charset conversion utils
*
* Copyright (c) 2017 Rob Clark
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CHARSET_H_
diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h
index 0df90161d75..ea48421bbeb 100644
--- a/include/configs/ls1088a_common.h
+++ b/include/configs/ls1088a_common.h
@@ -148,7 +148,6 @@ unsigned long long get_qixis_addr(void);
#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024)
#endif
/* Command line configuration */
-#define CONFIG_CMD_GREPENV
#define CONFIG_CMD_CACHE
/* Miscellaneous configurable options */
@@ -195,10 +194,6 @@ unsigned long long get_qixis_addr(void);
"mcinitcmd=fsl_mc start mc 0x580a00000" \
" 0x580e00000 \0"
-#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \
- "earlycon=uart8250,mmio,0x21c0500 " \
- "ramdisk_size=0x3000000 default_hugepagesz=2m" \
- " hugepagesz=2m hugepages=256"
#if defined(CONFIG_QSPI_BOOT)
#define CONFIG_BOOTCOMMAND "sf probe 0:0;" \
"sf read 0x80200000 0xd00000 0x100000;"\
diff --git a/include/configs/xilinx_zynqmp_r5.h b/include/configs/xilinx_zynqmp_r5.h
new file mode 100644
index 00000000000..05105e5d44e
--- /dev/null
+++ b/include/configs/xilinx_zynqmp_r5.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * (C) Copyright 2018 Xilinx, Inc. (Michal Simek)
+ */
+
+#ifndef __CONFIG_ZYNQMP_R5_H
+#define __CONFIG_ZYNQMP_R5_H
+
+#define CONFIG_EXTRA_ENV_SETTINGS
+
+/* CPU clock */
+#define CONFIG_CPU_FREQ_HZ 500000000
+
+/* Serial drivers */
+/* The following table includes the supported baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
+
+# define CONFIG_ENV_SIZE (128 << 10)
+
+/* Allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Boot configuration */
+#define CONFIG_SYS_LOAD_ADDR 0 /* default? */
+
+#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
+
+#define CONFIG_NR_DRAM_BANKS 1
+
+#define CONFIG_SYS_MALLOC_LEN 0x1400000
+
+#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+
+/* Extend size of kernel image for uncompression */
+#define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024)
+
+#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/* 0x0 - 0x40 is used for placing exception vectors */
+#define CONFIG_SYS_MEMTEST_START 0x40
+#define CONFIG_SYS_MEMTEST_END 0x100
+#define CONFIG_SYS_MEMTEST_SCRATCH 0
+
+#endif /* __CONFIG_ZYNQ_ZYNQMP_R5_H */
diff --git a/include/configs/xilinx_zynqmp_zc1275_revB.h b/include/configs/xilinx_zynqmp_zc1275_revB.h
new file mode 100644
index 00000000000..f0880db0b05
--- /dev/null
+++ b/include/configs/xilinx_zynqmp_zc1275_revB.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration for Xilinx ZynqMP zc1275 RevB
+ *
+ * (C) Copyright 2018 Xilinx, Inc.
+ */
+
+#ifndef __CONFIG_ZYNQMP_ZC1275_REVB_H
+#define __CONFIG_ZYNQMP_ZC1275_REVB_H
+
+#define CONFIG_ZYNQ_SDHCI1
+
+#include <configs/xilinx_zynqmp.h>
+
+#endif /* __CONFIG_ZYNQMP_ZC1275_REVB_H */
diff --git a/include/efi_driver.h b/include/efi_driver.h
index 010e55a4739..840483a416a 100644
--- a/include/efi_driver.h
+++ b/include/efi_driver.h
@@ -1,9 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* EFI application loader
*
* Copyright (c) 2017 Heinrich Schuchardt
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _EFI_DRIVER_H
diff --git a/include/efi_loader.h b/include/efi_loader.h
index 8d21ba74b1d..2868ca25abb 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -1,9 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* EFI application loader
*
* Copyright (c) 2016 Alexander Graf
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _EFI_LOADER_H
diff --git a/include/efi_selftest.h b/include/efi_selftest.h
index c23bc24bed0..d0a76d70cae 100644
--- a/include/efi_selftest.h
+++ b/include/efi_selftest.h
@@ -1,9 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* EFI application loader
*
* Copyright (c) 2017 Heinrich Schuchardt <xypron.glpk@gmx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _EFI_SELFTEST_H
diff --git a/include/fsl-mc/fsl_dpbp.h b/include/fsl-mc/fsl_dpbp.h
index 8d7c14d97db..2278ac952ea 100644
--- a/include/fsl-mc/fsl_dpbp.h
+++ b/include/fsl-mc/fsl_dpbp.h
@@ -2,7 +2,7 @@
/*
* Freescale Layerscape MC I/O wrapper
*
- * Copyright (C) 2013-2016 Freescale Semiconductor, Inc.
+ * Copyright 2013-2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
*/
/*!
diff --git a/include/fsl-mc/fsl_dpio.h b/include/fsl-mc/fsl_dpio.h
index c300c94e202..7788e1962e6 100644
--- a/include/fsl-mc/fsl_dpio.h
+++ b/include/fsl-mc/fsl_dpio.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright (C) 2013-2016 Freescale Semiconductor
+ * Copyright 2013-2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
*/
diff --git a/include/fsl-mc/fsl_dpmac.h b/include/fsl-mc/fsl_dpmac.h
index 66cf3bf6a21..1cea123a316 100644
--- a/include/fsl-mc/fsl_dpmac.h
+++ b/include/fsl-mc/fsl_dpmac.h
@@ -2,7 +2,7 @@
/*
* Freescale Layerscape MC I/O wrapper
*
- * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
* Author: Prabhakar Kushwaha <prabhakar@freescale.com>
*/
diff --git a/include/fsl-mc/fsl_dpni.h b/include/fsl-mc/fsl_dpni.h
index 309d323acf7..96d81d99349 100644
--- a/include/fsl-mc/fsl_dpni.h
+++ b/include/fsl-mc/fsl_dpni.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright (C) 2013-2016 Freescale Semiconductor
+ * Copyright 2013-2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
*/
#ifndef _FSL_DPNI_H
diff --git a/include/fsl-mc/fsl_dprc.h b/include/fsl-mc/fsl_dprc.h
index 779d6f95672..950ecb07569 100644
--- a/include/fsl-mc/fsl_dprc.h
+++ b/include/fsl-mc/fsl_dprc.h
@@ -2,7 +2,7 @@
/*
* Freescale Layerscape MC I/O wrapper
*
- * Copyright (C) 2013-2016 Freescale Semiconductor, Inc.
+ * Copyright 2013-2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
*/
#ifndef _FSL_DPRC_H
diff --git a/include/fsl-mc/fsl_mc_cmd.h b/include/fsl-mc/fsl_mc_cmd.h
index 179f6698283..591cda96851 100644
--- a/include/fsl-mc/fsl_mc_cmd.h
+++ b/include/fsl-mc/fsl_mc_cmd.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0+ */
-/* Copyright 2013-2016 Freescale Semiconductor Inc.
+/* Copyright 2013-2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
*/
#ifndef __FSL_MC_CMD_H
diff --git a/include/fsl-mc/fsl_mc_private.h b/include/fsl-mc/fsl_mc_private.h
index f4b5a99e15d..ba0bc379d5b 100644
--- a/include/fsl-mc/fsl_mc_private.h
+++ b/include/fsl-mc/fsl_mc_private.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright (C) 2014-2016 Freescale Semiconductor
+ * Copyright 2014-2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
*/
diff --git a/include/fsl_ifc.h b/include/fsl_ifc.h
index d051e92ce4c..8120ca0de86 100644
--- a/include/fsl_ifc.h
+++ b/include/fsl_ifc.h
@@ -891,8 +891,8 @@ struct fsl_ifc_nand {
u32 nand_erattr1;
u32 res19[0x10];
u32 nand_fsr;
- u32 res20[0x3];
- u32 nand_eccstat[6];
+ u32 res20[0x1];
+ u32 nand_eccstat[8];
u32 res21[0x1c];
u32 nanndcr;
u32 res22[0x2];
diff --git a/include/image.h b/include/image.h
index 6a22c98b4ae..df701e34705 100644
--- a/include/image.h
+++ b/include/image.h
@@ -259,7 +259,7 @@ enum {
IH_TYPE_MXSIMAGE, /* Freescale MXSBoot Image */
IH_TYPE_GPIMAGE, /* TI Keystone GPHeader Image */
IH_TYPE_ATMELIMAGE, /* ATMEL ROM bootable Image */
- IH_TYPE_SOCFPGAIMAGE, /* Altera SOCFPGA Preloader */
+ IH_TYPE_SOCFPGAIMAGE, /* Altera SOCFPGA CV/AV Preloader */
IH_TYPE_X86_SETUP, /* x86 setup.bin Image */
IH_TYPE_LPC32XXIMAGE, /* x86 setup.bin Image */
IH_TYPE_LOADABLE, /* A list of typeless images */
@@ -268,12 +268,14 @@ enum {
IH_TYPE_RKSPI, /* Rockchip SPI image */
IH_TYPE_ZYNQIMAGE, /* Xilinx Zynq Boot Image */
IH_TYPE_ZYNQMPIMAGE, /* Xilinx ZynqMP Boot Image */
+ IH_TYPE_ZYNQMPBIF, /* Xilinx ZynqMP Boot Image (bif) */
IH_TYPE_FPGA, /* FPGA Image */
IH_TYPE_VYBRIDIMAGE, /* VYBRID .vyb Image */
IH_TYPE_TEE, /* Trusted Execution Environment OS Image */
IH_TYPE_FIRMWARE_IVT, /* Firmware Image with HABv4 IVT */
IH_TYPE_PMMC, /* TI Power Management Micro-Controller Firmware */
IH_TYPE_STM32IMAGE, /* STMicroelectronics STM32 Image */
+ IH_TYPE_SOCFPGAIMAGE_V1, /* Altera SOCFPGA A10 Preloader */
IH_TYPE_COUNT, /* Number of image types */
};
diff --git a/include/linux/log2.h b/include/linux/log2.h
index 4ded5ee68a9..d4e32ecfc64 100644
--- a/include/linux/log2.h
+++ b/include/linux/log2.h
@@ -3,6 +3,11 @@
*
* Copyright (C) 2006 Red Hat, Inc. All Rights Reserved.
* Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
*/
#ifndef _LINUX_LOG2_H
@@ -12,12 +17,6 @@
#include <linux/bitops.h>
/*
- * deal with unrepresentable constant logarithms
- */
-extern __attribute__((const, noreturn))
-int ____ilog2_NaN(void);
-
-/*
* non-constant log of base 2 calculators
* - the arch may override these in asm/bitops.h if they can be implemented
* more efficiently than using fls() and fls64()
@@ -39,19 +38,23 @@ int __ilog2_u64(u64 n)
}
#endif
-/*
- * Determine whether some value is a power of two, where zero is
+/**
+ * is_power_of_2() - check if a value is a power of two
+ * @n: the value to check
+ *
+ * Determine whether some value is a power of two, where zero is
* *not* considered a power of two.
+ * Return: true if @n is a power of 2, otherwise false.
*/
-
static inline __attribute__((const))
bool is_power_of_2(unsigned long n)
{
return (n != 0 && ((n & (n - 1)) == 0));
}
-/*
- * round up to nearest power of two
+/**
+ * __roundup_pow_of_two() - round up to nearest power of two
+ * @n: value to round up
*/
static inline __attribute__((const))
unsigned long __roundup_pow_of_two(unsigned long n)
@@ -59,8 +62,9 @@ unsigned long __roundup_pow_of_two(unsigned long n)
return 1UL << fls_long(n - 1);
}
-/*
- * round down to nearest power of two
+/**
+ * __rounddown_pow_of_two() - round down to nearest power of two
+ * @n: value to round down
*/
static inline __attribute__((const))
unsigned long __rounddown_pow_of_two(unsigned long n)
@@ -69,19 +73,19 @@ unsigned long __rounddown_pow_of_two(unsigned long n)
}
/**
- * ilog2 - log of base 2 of 32-bit or a 64-bit unsigned value
- * @n - parameter
+ * ilog2 - log base 2 of 32-bit or a 64-bit unsigned value
+ * @n: parameter
*
* constant-capable log of base 2 calculation
* - this can be used to initialise global variables from constant data, hence
- * the massive ternary operator construction
+ * the massive ternary operator construction
*
* selects the appropriately-sized optimised version depending on sizeof(n)
*/
#define ilog2(n) \
( \
__builtin_constant_p(n) ? ( \
- (n) < 1 ? ____ilog2_NaN() : \
+ (n) < 2 ? 0 : \
(n) & (1ULL << 63) ? 63 : \
(n) & (1ULL << 62) ? 62 : \
(n) & (1ULL << 61) ? 61 : \
@@ -144,10 +148,7 @@ unsigned long __rounddown_pow_of_two(unsigned long n)
(n) & (1ULL << 4) ? 4 : \
(n) & (1ULL << 3) ? 3 : \
(n) & (1ULL << 2) ? 2 : \
- (n) & (1ULL << 1) ? 1 : \
- (n) & (1ULL << 0) ? 0 : \
- ____ilog2_NaN() \
- ) : \
+ 1) : \
(sizeof(n) <= 4) ? \
__ilog2_u32(n) : \
__ilog2_u64(n) \
@@ -155,7 +156,7 @@ unsigned long __rounddown_pow_of_two(unsigned long n)
/**
* roundup_pow_of_two - round the given value up to nearest power of two
- * @n - parameter
+ * @n: parameter
*
* round the given value up to the nearest power of two
* - the result is undefined when n == 0
@@ -172,7 +173,7 @@ unsigned long __rounddown_pow_of_two(unsigned long n)
/**
* rounddown_pow_of_two - round the given value down to nearest power of two
- * @n - parameter
+ * @n: parameter
*
* round the given value down to the nearest power of two
* - the result is undefined when n == 0
@@ -185,6 +186,12 @@ unsigned long __rounddown_pow_of_two(unsigned long n)
__rounddown_pow_of_two(n) \
)
+static inline __attribute_const__
+int __order_base_2(unsigned long n)
+{
+ return n > 1 ? ilog2(n - 1) + 1 : 0;
+}
+
/**
* order_base_2 - calculate the (rounded up) base 2 order of the argument
* @n: parameter
@@ -198,7 +205,11 @@ unsigned long __rounddown_pow_of_two(unsigned long n)
* ob2(5) = 3
* ... and so on.
*/
-
-#define order_base_2(n) ilog2(roundup_pow_of_two(n))
-
+#define order_base_2(n) \
+( \
+ __builtin_constant_p(n) ? ( \
+ ((n) == 0 || (n) == 1) ? 0 : \
+ ilog2((n) - 1) + 1) : \
+ __order_base_2(n) \
+)
#endif /* _LINUX_LOG2_H */
diff --git a/include/net.h b/include/net.h
index 3469811aa0e..65f51d77a55 100644
--- a/include/net.h
+++ b/include/net.h
@@ -1,9 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0 */
/*
* LiMon Monitor (LiMon) - Network.
*
* Copyright 1994 - 2000 Neil Russell.
* (See License)
- * SPDX-License-Identifier: GPL-2.0
*
* History
* 9/16/00 bor adapted to TQM823L/STK8xxL board, RARP/TFTP boot added
diff --git a/include/pe.h b/include/pe.h
index e7845bb7d2c..d73eb142cb3 100644
--- a/include/pe.h
+++ b/include/pe.h
@@ -1,11 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Portable Executable binary format structures
*
* Copyright (c) 2016 Alexander Graf
*
* Based on wine code
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _PE_H
diff --git a/include/sdhci.h b/include/sdhci.h
index 1e0c92c4cba..bef37df982e 100644
--- a/include/sdhci.h
+++ b/include/sdhci.h
@@ -166,6 +166,11 @@
#define SDHCI_CAN_64BIT BIT(28)
#define SDHCI_CAPABILITIES_1 0x44
+#define SDHCI_SUPPORT_SDR50 0x00000001
+#define SDHCI_SUPPORT_SDR104 0x00000002
+#define SDHCI_SUPPORT_DDR50 0x00000004
+#define SDHCI_USE_SDR50_TUNING 0x00002000
+
#define SDHCI_CLOCK_MUL_MASK 0x00FF0000
#define SDHCI_CLOCK_MUL_SHIFT 16
@@ -220,6 +225,7 @@
#define SDHCI_QUIRK_BROKEN_HISPD_MODE BIT(5)
#define SDHCI_QUIRK_WAIT_SEND_CMD (1 << 6)
#define SDHCI_QUIRK_USE_WIDE8 (1 << 8)
+#define SDHCI_QUIRK_NO_1_8_V (1 << 9)
/* to make gcc happy */
struct sdhci_host;
@@ -242,6 +248,8 @@ struct sdhci_ops {
void (*set_control_reg)(struct sdhci_host *host);
void (*set_ios_post)(struct sdhci_host *host);
void (*set_clock)(struct sdhci_host *host, u32 div);
+ int (*platform_execute_tuning)(struct mmc *host, u8 opcode);
+ void (*set_delay)(struct sdhci_host *host);
};
struct sdhci_host {
diff --git a/include/zynqmp_tap_delay.h b/include/zynqmp_tap_delay.h
new file mode 100644
index 00000000000..b07e3e06922
--- /dev/null
+++ b/include/zynqmp_tap_delay.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Xilinx ZynqMP SoC Tap Delay Programming
+ *
+ * Copyright (C) 2018 Xilinx, Inc.
+ */
+
+#ifndef __ZYNQMP_TAP_DELAY_H__
+#define __ZYNQMP_TAP_DELAY_H__
+
+#ifdef CONFIG_ARCH_ZYNQMP
+void zynqmp_dll_reset(u8 deviceid);
+void arasan_zynqmp_set_tapdelay(u8 device_id, u8 uhsmode, u8 bank);
+#else
+inline void zynqmp_dll_reset(u8 deviceid) {}
+inline void arasan_zynqmp_set_tapdelay(u8 device_id, u8 uhsmode, u8 bank) {}
+#endif
+
+#endif
diff --git a/include/zynqpl.h b/include/zynqpl.h
index 9c63c016f50..cdfd8a205ab 100644
--- a/include/zynqpl.h
+++ b/include/zynqpl.h
@@ -11,23 +11,18 @@
#include <xilinx.h>
-#if defined(CONFIG_FPGA_ZYNQPL)
extern struct xilinx_fpga_op zynq_op;
-# define FPGA_ZYNQPL_OPS &zynq_op
-#else
-# define FPGA_ZYNQPL_OPS NULL
-#endif
-#define XILINX_ZYNQ_7007S 0x3
-#define XILINX_ZYNQ_7010 0x2
-#define XILINX_ZYNQ_7012S 0x1c
-#define XILINX_ZYNQ_7014S 0x8
-#define XILINX_ZYNQ_7015 0x1b
-#define XILINX_ZYNQ_7020 0x7
-#define XILINX_ZYNQ_7030 0xc
-#define XILINX_ZYNQ_7035 0x12
-#define XILINX_ZYNQ_7045 0x11
-#define XILINX_ZYNQ_7100 0x16
+#define XILINX_ZYNQ_XC7Z007S 0x3
+#define XILINX_ZYNQ_XC7Z010 0x2
+#define XILINX_ZYNQ_XC7Z012S 0x1c
+#define XILINX_ZYNQ_XC7Z014S 0x8
+#define XILINX_ZYNQ_XC7Z015 0x1b
+#define XILINX_ZYNQ_XC7Z020 0x7
+#define XILINX_ZYNQ_XC7Z030 0xc
+#define XILINX_ZYNQ_XC7Z035 0x12
+#define XILINX_ZYNQ_XC7Z045 0x11
+#define XILINX_ZYNQ_XC7Z100 0x16
/* Device Image Sizes */
#define XILINX_XC7Z007S_SIZE 16669920/8
@@ -41,45 +36,29 @@ extern struct xilinx_fpga_op zynq_op;
#define XILINX_XC7Z045_SIZE 106571232/8
#define XILINX_XC7Z100_SIZE 139330784/8
-/* Descriptor Macros */
-#define XILINX_XC7Z007S_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z007S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
- "7z007s" }
-
-#define XILINX_XC7Z010_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
- "7z010" }
-
-#define XILINX_XC7Z012S_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z012S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
- "7z012s" }
-
-#define XILINX_XC7Z014S_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z014S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
- "7z014s" }
-
-#define XILINX_XC7Z015_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
- "7z015" }
-
-#define XILINX_XC7Z020_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
- "7z020" }
-
-#define XILINX_XC7Z030_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
- "7z030" }
-
-#define XILINX_XC7Z035_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z035_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
- "7z035" }
-
-#define XILINX_XC7Z045_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
- "7z045" }
-
-#define XILINX_XC7Z100_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z100_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
- "7z100" }
+/* Device Names */
+#define XILINX_XC7Z007S_NAME "7z007s"
+#define XILINX_XC7Z010_NAME "7z010"
+#define XILINX_XC7Z012S_NAME "7z012s"
+#define XILINX_XC7Z014S_NAME "7z014s"
+#define XILINX_XC7Z015_NAME "7z015"
+#define XILINX_XC7Z020_NAME "7z020"
+#define XILINX_XC7Z030_NAME "7z030"
+#define XILINX_XC7Z035_NAME "7z035"
+#define XILINX_XC7Z045_NAME "7z045"
+#define XILINX_XC7Z100_NAME "7z100"
+
+#if defined(CONFIG_FPGA)
+#define ZYNQ_DESC(name) { \
+ .idcode = XILINX_ZYNQ_XC##name, \
+ .fpga_size = XILINX_XC##name##_SIZE, \
+ .devicename = XILINX_XC##name##_NAME \
+ }
+#else
+#define ZYNQ_DESC(name) { \
+ .idcode = XILINX_ZYNQ_XC##name, \
+ .devicename = XILINX_XC##name##_NAME \
+ }
+#endif
#endif /* _ZYNQPL_H_ */
generated by cgit v1.2.3 (git 2.0.4) at 2025-09-24 23:56:08 +0000