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-rw-r--r--include/bloblist.h7
-rw-r--r--include/configs/bananapi-f3.h13
-rw-r--r--include/configs/j721e_evm.h9
-rw-r--r--include/configs/licheerv_nano.h24
-rw-r--r--include/configs/ls1028ardb.h1
-rw-r--r--include/configs/phycore_am62ax.h15
-rw-r--r--include/configs/rcar-gen2-common.h10
-rw-r--r--include/configs/rcar-gen3-common.h19
-rw-r--r--include/configs/rcar-gen4-common.h8
-rw-r--r--include/dt-bindings/clock/starfive,jh7110-crg.h258
-rw-r--r--include/dt-bindings/reset/starfive,jh7110-crg.h183
-rw-r--r--include/efi.h2
-rw-r--r--include/fdtdec.h33
-rw-r--r--include/image.h31
-rw-r--r--include/limits.h3
-rw-r--r--include/lmb.h149
-rw-r--r--include/net-common.h2
-rw-r--r--include/net-legacy.h5
-rw-r--r--include/net/tcp.h257
-rw-r--r--include/net/wget.h8
-rw-r--r--include/ns16550.h18
-rw-r--r--include/ppc_asm.tmpl66
-rw-r--r--include/spl.h28
-rw-r--r--include/trace.h2
-rw-r--r--include/u-boot/crc.h3
25 files changed, 517 insertions, 637 deletions
diff --git a/include/bloblist.h b/include/bloblist.h
index ff32d3fecfd..f999391f74b 100644
--- a/include/bloblist.h
+++ b/include/bloblist.h
@@ -357,6 +357,7 @@ int bloblist_new(ulong addr, uint size, uint flags, uint align_log2);
*/
int bloblist_check(ulong addr, uint size);
+#if CONFIG_IS_ENABLED(BLOBLIST)
/**
* bloblist_finish() - Set up the bloblist for the next U-Boot part
*
@@ -366,6 +367,12 @@ int bloblist_check(ulong addr, uint size);
* Return: 0
*/
int bloblist_finish(void);
+#else
+static inline int bloblist_finish(void)
+{
+ return 0;
+}
+#endif /* BLOBLIST */
/**
* bloblist_get_stats() - Get information about the bloblist
diff --git a/include/configs/bananapi-f3.h b/include/configs/bananapi-f3.h
new file mode 100644
index 00000000000..97cf4d72df0
--- /dev/null
+++ b/include/configs/bananapi-f3.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com>
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CFG_SYS_SDRAM_BASE 0x0
+#define CFG_SYS_NS16550_IER 0x40 /* UART Unit Enable */
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h
index bdf12ee8f7e..85120629529 100644
--- a/include/configs/j721e_evm.h
+++ b/include/configs/j721e_evm.h
@@ -15,11 +15,14 @@
#define CFG_SYS_FLASH_BASE 0x000000000
/* SPL Loader Configuration */
-#if defined(CONFIG_TARGET_J721E_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM)
+#if defined(CONFIG_TARGET_J721E_A72_EVM)
#define CFG_SYS_UBOOT_BASE 0x50280000
-/* Image load address in RAM for DFU boot*/
-#else
+#elif defined(CONFIG_TARGET_J7200_A72_EVM)
+#define CFG_SYS_UBOOT_BASE 0x50300000
+#elif defined(CONFIG_TARGET_J721E_R5_EVM)
#define CFG_SYS_UBOOT_BASE 0x50080000
+#else
+#define CFG_SYS_UBOOT_BASE 0x50100000
#endif
/**
diff --git a/include/configs/licheerv_nano.h b/include/configs/licheerv_nano.h
new file mode 100644
index 00000000000..2ea7943f66f
--- /dev/null
+++ b/include/configs/licheerv_nano.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2024, Thomas Bonnefille <thomas.bonnefille@bootlin.com>
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <config_distro_bootcmd.h>
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 0)
+
+#define CFG_SYS_SDRAM_BASE 0x80000000
+
+#define CFG_EXTRA_ENV_SETTINGS "consoledev=ttyS0\0" \
+ "baudrate=115200\0" \
+ "fdt_addr_r=0x82000000\0" \
+ "kernel_addr_r=0x81000000\0" \
+ "scriptaddr=0x80c00000\0" \
+ BOOTENV
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/ls1028ardb.h b/include/configs/ls1028ardb.h
index d44ce45fd6b..9c869ee6840 100644
--- a/include/configs/ls1028ardb.h
+++ b/include/configs/ls1028ardb.h
@@ -53,6 +53,7 @@
#define CFG_EXTRA_ENV_SETTINGS \
"board=ls1028ardb\0" \
"hwconfig=fsl_ddr:bank_intlv=auto\0" \
+ "fdtfile=fsl-ls1028a-rdb.dtb\0" \
"ramdisk_addr=0x800000\0" \
"ramdisk_size=0x2000000\0" \
"bootm_size=0x10000000\0" \
diff --git a/include/configs/phycore_am62ax.h b/include/configs/phycore_am62ax.h
new file mode 100644
index 00000000000..661ba8f73ca
--- /dev/null
+++ b/include/configs/phycore_am62ax.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later OR MIT */
+/*
+ * Configuration header file for PHYTEC phyCORE-AM62Ax
+ *
+ * Copyright (C) 2024 PHYTEC America LLC
+ * Author: Garrett Giordano <ggiordano@phytec.com>
+ */
+
+#ifndef __PHYCORE_AM62AX_H
+#define __PHYCORE_AM62AX_H
+
+/* DDR Configuration */
+#define CFG_SYS_SDRAM_BASE 0x80000000
+
+#endif /* __PHYCORE_AM62AX_H */
diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h
index 67c9faeca57..020e79ca2a8 100644
--- a/include/configs/rcar-gen2-common.h
+++ b/include/configs/rcar-gen2-common.h
@@ -1,8 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* include/configs/rcar-gen2-common.h
+ * This file is R-Car Gen2 common configuration file.
*
- * Copyright (C) 2013,2014 Renesas Electronics Corporation
+ * Copyright (C) 2013-2024 Renesas Electronics Corporation
*/
#ifndef __RCAR_GEN2_COMMON_H
@@ -10,14 +11,15 @@
#include <asm/arch/renesas.h>
-/* console */
-#define CFG_SYS_BAUDRATE_TABLE { 38400, 115200 }
+/* Console */
+#define CFG_SYS_BAUDRATE_TABLE { 38400, 115200 }
+/* Memory */
#define CFG_SYS_SDRAM_BASE (RCAR_GEN2_SDRAM_BASE)
#define CFG_SYS_SDRAM_SIZE (RCAR_GEN2_UBOOT_SDRAM_SIZE)
/* Timer */
-#define CFG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */
+#define CFG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */
#define CFG_SYS_TIMER_RATE (get_board_sys_clk() / 8)
#endif /* __RCAR_GEN2_COMMON_H */
diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h
index 3f0831a901c..bedb1c0843e 100644
--- a/include/configs/rcar-gen3-common.h
+++ b/include/configs/rcar-gen3-common.h
@@ -3,7 +3,7 @@
* include/configs/rcar-gen3-common.h
* This file is R-Car Gen3 common configuration file.
*
- * Copyright (C) 2015-2017 Renesas Electronics Corporation
+ * Copyright (C) 2015-2024 Renesas Electronics Corporation
*/
#ifndef __RCAR_GEN3_COMMON_H
@@ -11,24 +11,17 @@
#include <asm/arch/renesas.h>
-/* boot option */
+/* Console */
+#define CFG_SYS_BAUDRATE_TABLE { 115200, 38400 }
-/* Generic Interrupt Controller Definitions */
-#define GICD_BASE 0xF1010000
-#define GICC_BASE 0xF1020000
-
-/* console */
-#define CFG_SYS_BAUDRATE_TABLE { 115200, 38400 }
-
-/* MEMORY */
+/* Memory */
#define DRAM_RSV_SIZE 0x08000000
#define CFG_SYS_SDRAM_BASE (0x40000000 + DRAM_RSV_SIZE)
#define CFG_SYS_SDRAM_SIZE (0x80000000u - DRAM_RSV_SIZE)
#define CFG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE)
-/* ENV setting */
-
-#define CFG_EXTRA_ENV_SETTINGS \
+/* Environment setting */
+#define CFG_EXTRA_ENV_SETTINGS \
"bootm_size=0x10000000\0"
#endif /* __RCAR_GEN3_COMMON_H */
diff --git a/include/configs/rcar-gen4-common.h b/include/configs/rcar-gen4-common.h
index 37a37c013df..1a00adb79d1 100644
--- a/include/configs/rcar-gen4-common.h
+++ b/include/configs/rcar-gen4-common.h
@@ -3,7 +3,7 @@
* include/configs/rcar-gen4-common.h
* This file is R-Car Gen4 common configuration file.
*
- * Copyright (C) 2021 Renesas Electronics Corporation
+ * Copyright (C) 2021-2024 Renesas Electronics Corporation
*/
#ifndef __RCAR_GEN4_COMMON_H
@@ -12,7 +12,7 @@
#include <asm/arch/renesas.h>
/* Console */
-#define CFG_SYS_BAUDRATE_TABLE { 38400, 115200, 921600, 1843200 }
+#define CFG_SYS_BAUDRATE_TABLE { 38400, 115200, 921600, 1843200 }
/* Memory */
#define DRAM_RSV_SIZE 0x08000000
@@ -20,10 +20,8 @@
#define CFG_SYS_SDRAM_SIZE (0x80000000u - DRAM_RSV_SIZE)
#define CFG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE)
-/* PHY needs a longer autoneg timeout */
-
/* Environment setting */
-#define CFG_EXTRA_ENV_SETTINGS \
+#define CFG_EXTRA_ENV_SETTINGS \
"bootm_size=0x10000000\0"
#endif /* __RCAR_GEN4_COMMON_H */
diff --git a/include/dt-bindings/clock/starfive,jh7110-crg.h b/include/dt-bindings/clock/starfive,jh7110-crg.h
deleted file mode 100644
index b51e3829ff4..00000000000
--- a/include/dt-bindings/clock/starfive,jh7110-crg.h
+++ /dev/null
@@ -1,258 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2022 StarFive Technology Co., Ltd.
- *
- * Author: Yanhong Wang <yanhong.wang@starfivetech.com>
- */
-
-#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__
-#define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__
-
-#define JH7110_SYSCLK_PLL0_OUT 0
-#define JH7110_SYSCLK_PLL1_OUT 1
-#define JH7110_SYSCLK_PLL2_OUT 2
-#define JH7110_PLLCLK_END 3
-
-#define JH7110_SYSCLK_CPU_ROOT 0
-#define JH7110_SYSCLK_CPU_CORE 1
-#define JH7110_SYSCLK_CPU_BUS 2
-#define JH7110_SYSCLK_GPU_ROOT 3
-#define JH7110_SYSCLK_PERH_ROOT 4
-#define JH7110_SYSCLK_BUS_ROOT 5
-#define JH7110_SYSCLK_NOCSTG_BUS 6
-#define JH7110_SYSCLK_AXI_CFG0 7
-#define JH7110_SYSCLK_STG_AXIAHB 8
-#define JH7110_SYSCLK_AHB0 9
-#define JH7110_SYSCLK_AHB1 10
-#define JH7110_SYSCLK_APB_BUS 11
-#define JH7110_SYSCLK_APB0 12
-#define JH7110_SYSCLK_PLL0_DIV2 13
-#define JH7110_SYSCLK_PLL1_DIV2 14
-#define JH7110_SYSCLK_PLL2_DIV2 15
-#define JH7110_SYSCLK_AUDIO_ROOT 16
-#define JH7110_SYSCLK_MCLK_INNER 17
-#define JH7110_SYSCLK_MCLK 18
-#define JH7110_SYSCLK_MCLK_OUT 19
-#define JH7110_SYSCLK_ISP_2X 20
-#define JH7110_SYSCLK_ISP_AXI 21
-#define JH7110_SYSCLK_GCLK0 22
-#define JH7110_SYSCLK_GCLK1 23
-#define JH7110_SYSCLK_GCLK2 24
-#define JH7110_SYSCLK_CORE 25
-#define JH7110_SYSCLK_CORE1 26
-#define JH7110_SYSCLK_CORE2 27
-#define JH7110_SYSCLK_CORE3 28
-#define JH7110_SYSCLK_CORE4 29
-#define JH7110_SYSCLK_DEBUG 30
-#define JH7110_SYSCLK_RTC_TOGGLE 31
-#define JH7110_SYSCLK_TRACE0 32
-#define JH7110_SYSCLK_TRACE1 33
-#define JH7110_SYSCLK_TRACE2 34
-#define JH7110_SYSCLK_TRACE3 35
-#define JH7110_SYSCLK_TRACE4 36
-#define JH7110_SYSCLK_TRACE_COM 37
-#define JH7110_SYSCLK_NOC_BUS_CPU_AXI 38
-#define JH7110_SYSCLK_NOC_BUS_AXICFG0_AXI 39
-#define JH7110_SYSCLK_OSC_DIV2 40
-#define JH7110_SYSCLK_PLL1_DIV4 41
-#define JH7110_SYSCLK_PLL1_DIV8 42
-#define JH7110_SYSCLK_DDR_BUS 43
-#define JH7110_SYSCLK_DDR_AXI 44
-#define JH7110_SYSCLK_GPU_CORE 45
-#define JH7110_SYSCLK_GPU_CORE_CLK 46
-#define JH7110_SYSCLK_GPU_SYS_CLK 47
-#define JH7110_SYSCLK_GPU_APB 48
-#define JH7110_SYSCLK_GPU_RTC_TOGGLE 49
-#define JH7110_SYSCLK_NOC_BUS_GPU_AXI 50
-#define JH7110_SYSCLK_ISP_TOP_CLK_ISPCORE_2X 51
-#define JH7110_SYSCLK_ISP_TOP_CLK_ISP_AXI 52
-#define JH7110_SYSCLK_NOC_BUS_ISP_AXI 53
-#define JH7110_SYSCLK_HIFI4_CORE 54
-#define JH7110_SYSCLK_HIFI4_AXI 55
-#define JH7110_SYSCLK_AXI_CFG1_DEC_MAIN 56
-#define JH7110_SYSCLK_AXI_CFG1_DEC_AHB 57
-#define JH7110_SYSCLK_VOUT_SRC 58
-#define JH7110_SYSCLK_VOUT_AXI 59
-#define JH7110_SYSCLK_NOC_BUS_DISP_AXI 60
-#define JH7110_SYSCLK_VOUT_TOP_CLK_VOUT_AHB 61
-#define JH7110_SYSCLK_VOUT_TOP_CLK_VOUT_AXI 62
-#define JH7110_SYSCLK_VOUT_TOP_CLK_HDMITX0_MCLK 63
-#define JH7110_SYSCLK_VOUT_TOP_CLK_MIPIPHY_REF 64
-#define JH7110_SYSCLK_JPEGC_AXI 65
-#define JH7110_SYSCLK_CODAJ12_AXI 66
-#define JH7110_SYSCLK_CODAJ12_CORE 67
-#define JH7110_SYSCLK_CODAJ12_APB 68
-#define JH7110_SYSCLK_VDEC_AXI 69
-#define JH7110_SYSCLK_WAVE511_AXI 70
-#define JH7110_SYSCLK_WAVE511_BPU 71
-#define JH7110_SYSCLK_WAVE511_VCE 72
-#define JH7110_SYSCLK_WAVE511_APB 73
-#define JH7110_SYSCLK_VDEC_JPG_ARB_JPG 74
-#define JH7110_SYSCLK_VDEC_JPG_ARB_MAIN 75
-#define JH7110_SYSCLK_NOC_BUS_VDEC_AXI 76
-#define JH7110_SYSCLK_VENC_AXI 77
-#define JH7110_SYSCLK_WAVE420L_AXI 78
-#define JH7110_SYSCLK_WAVE420L_BPU 79
-#define JH7110_SYSCLK_WAVE420L_VCE 80
-#define JH7110_SYSCLK_WAVE420L_APB 81
-#define JH7110_SYSCLK_NOC_BUS_VENC_AXI 82
-#define JH7110_SYSCLK_AXI_CFG0_DEC_MAIN_DIV 83
-#define JH7110_SYSCLK_AXI_CFG0_DEC_MAIN 84
-#define JH7110_SYSCLK_AXI_CFG0_DEC_HIFI4 85
-#define JH7110_SYSCLK_AXIMEM2_AXI 86
-#define JH7110_SYSCLK_QSPI_AHB 87
-#define JH7110_SYSCLK_QSPI_APB 88
-#define JH7110_SYSCLK_QSPI_REF_SRC 89
-#define JH7110_SYSCLK_QSPI_REF 90
-#define JH7110_SYSCLK_SDIO0_AHB 91
-#define JH7110_SYSCLK_SDIO1_AHB 92
-#define JH7110_SYSCLK_SDIO0_SDCARD 93
-#define JH7110_SYSCLK_SDIO1_SDCARD 94
-#define JH7110_SYSCLK_USB_125M 95
-#define JH7110_SYSCLK_NOC_BUS_STG_AXI 96
-#define JH7110_SYSCLK_GMAC1_AHB 97
-#define JH7110_SYSCLK_GMAC1_AXI 98
-#define JH7110_SYSCLK_GMAC_SRC 99
-#define JH7110_SYSCLK_GMAC1_GTXCLK 100
-#define JH7110_SYSCLK_GMAC1_RMII_RTX 101
-#define JH7110_SYSCLK_GMAC1_PTP 102
-#define JH7110_SYSCLK_GMAC1_RX 103
-#define JH7110_SYSCLK_GMAC1_RX_INV 104
-#define JH7110_SYSCLK_GMAC1_TX 105
-#define JH7110_SYSCLK_GMAC1_TX_INV 106
-#define JH7110_SYSCLK_GMAC1_GTXC 107
-#define JH7110_SYSCLK_GMAC0_GTXCLK 108
-#define JH7110_SYSCLK_GMAC0_PTP 109
-#define JH7110_SYSCLK_GMAC_PHY 110
-#define JH7110_SYSCLK_GMAC0_GTXC 111
-#define JH7110_SYSCLK_IOMUX_APB 112
-#define JH7110_SYSCLK_MAILBOX 113
-#define JH7110_SYSCLK_INT_CTRL_APB 114
-#define JH7110_SYSCLK_CAN0_APB 115
-#define JH7110_SYSCLK_CAN0_TIMER 116
-#define JH7110_SYSCLK_CAN0_CAN 117
-#define JH7110_SYSCLK_CAN1_APB 118
-#define JH7110_SYSCLK_CAN1_TIMER 119
-#define JH7110_SYSCLK_CAN1_CAN 120
-#define JH7110_SYSCLK_PWM_APB 121
-#define JH7110_SYSCLK_WDT_APB 122
-#define JH7110_SYSCLK_WDT_CORE 123
-#define JH7110_SYSCLK_TIMER_APB 124
-#define JH7110_SYSCLK_TIMER0 125
-#define JH7110_SYSCLK_TIMER1 126
-#define JH7110_SYSCLK_TIMER2 127
-#define JH7110_SYSCLK_TIMER3 128
-#define JH7110_SYSCLK_TEMP_APB 129
-#define JH7110_SYSCLK_TEMP_CORE 130
-#define JH7110_SYSCLK_SPI0_APB 131
-#define JH7110_SYSCLK_SPI1_APB 132
-#define JH7110_SYSCLK_SPI2_APB 133
-#define JH7110_SYSCLK_SPI3_APB 134
-#define JH7110_SYSCLK_SPI4_APB 135
-#define JH7110_SYSCLK_SPI5_APB 136
-#define JH7110_SYSCLK_SPI6_APB 137
-#define JH7110_SYSCLK_I2C0_APB 138
-#define JH7110_SYSCLK_I2C1_APB 139
-#define JH7110_SYSCLK_I2C2_APB 140
-#define JH7110_SYSCLK_I2C3_APB 141
-#define JH7110_SYSCLK_I2C4_APB 142
-#define JH7110_SYSCLK_I2C5_APB 143
-#define JH7110_SYSCLK_I2C6_APB 144
-#define JH7110_SYSCLK_UART0_APB 145
-#define JH7110_SYSCLK_UART0_CORE 146
-#define JH7110_SYSCLK_UART1_APB 147
-#define JH7110_SYSCLK_UART1_CORE 148
-#define JH7110_SYSCLK_UART2_APB 149
-#define JH7110_SYSCLK_UART2_CORE 150
-#define JH7110_SYSCLK_UART3_APB 151
-#define JH7110_SYSCLK_UART3_CORE 152
-#define JH7110_SYSCLK_UART4_APB 153
-#define JH7110_SYSCLK_UART4_CORE 154
-#define JH7110_SYSCLK_UART5_APB 155
-#define JH7110_SYSCLK_UART5_CORE 156
-#define JH7110_SYSCLK_PWMDAC_APB 157
-#define JH7110_SYSCLK_PWMDAC_CORE 158
-#define JH7110_SYSCLK_SPDIF_APB 159
-#define JH7110_SYSCLK_SPDIF_CORE 160
-#define JH7110_SYSCLK_I2STX0_APB 161
-#define JH7110_SYSCLK_I2STX0_BCLK_MST 162
-#define JH7110_SYSCLK_I2STX0_BCLK_MST_INV 163
-#define JH7110_SYSCLK_I2STX0_LRCK_MST 164
-#define JH7110_SYSCLK_I2STX0_BCLK 165
-#define JH7110_SYSCLK_I2STX0_BCLK_INV 166
-#define JH7110_SYSCLK_I2STX0_LRCK 167
-#define JH7110_SYSCLK_I2STX1_APB 168
-#define JH7110_SYSCLK_I2STX1_BCLK_MST 169
-#define JH7110_SYSCLK_I2STX1_BCLK_MST_INV 170
-#define JH7110_SYSCLK_I2STX1_LRCK_MST 171
-#define JH7110_SYSCLK_I2STX1_BCLK 172
-#define JH7110_SYSCLK_I2STX1_BCLK_INV 173
-#define JH7110_SYSCLK_I2STX1_LRCK 174
-#define JH7110_SYSCLK_I2SRX_APB 175
-#define JH7110_SYSCLK_I2SRX_BCLK_MST 176
-#define JH7110_SYSCLK_I2SRX_BCLK_MST_INV 177
-#define JH7110_SYSCLK_I2SRX_LRCK_MST 178
-#define JH7110_SYSCLK_I2SRX_BCLK 179
-#define JH7110_SYSCLK_I2SRX_BCLK_INV 180
-#define JH7110_SYSCLK_I2SRX_LRCK 181
-#define JH7110_SYSCLK_PDM_DMIC 182
-#define JH7110_SYSCLK_PDM_APB 183
-#define JH7110_SYSCLK_TDM_AHB 184
-#define JH7110_SYSCLK_TDM_APB 185
-#define JH7110_SYSCLK_TDM_INTERNAL 186
-#define JH7110_SYSCLK_TDM_CLK_TDM 187
-#define JH7110_SYSCLK_TDM_CLK_TDM_N 188
-#define JH7110_SYSCLK_JTAG_CERTIFICATION_TRNG 189
-
-#define JH7110_SYSCLK_END 190
-
-#define JH7110_AONCLK_OSC_DIV4 0
-#define JH7110_AONCLK_APB_FUNC 1
-#define JH7110_AONCLK_GMAC0_AHB 2
-#define JH7110_AONCLK_GMAC0_AXI 3
-#define JH7110_AONCLK_GMAC0_RMII_RTX 4
-#define JH7110_AONCLK_GMAC0_TX 5
-#define JH7110_AONCLK_GMAC0_TX_INV 6
-#define JH7110_AONCLK_GMAC0_RX 7
-#define JH7110_AONCLK_GMAC0_RX_INV 8
-#define JH7110_AONCLK_OTPC_APB 9
-#define JH7110_AONCLK_RTC_APB 10
-#define JH7110_AONCLK_RTC_INTERNAL 11
-#define JH7110_AONCLK_RTC_32K 12
-#define JH7110_AONCLK_RTC_CAL 13
-
-#define JH7110_AONCLK_END 14
-
-#define JH7110_STGCLK_HIFI4_CORE 0
-#define JH7110_STGCLK_USB_APB 1
-#define JH7110_STGCLK_USB_UTMI_APB 2
-#define JH7110_STGCLK_USB_AXI 3
-#define JH7110_STGCLK_USB_LPM 4
-#define JH7110_STGCLK_USB_STB 5
-#define JH7110_STGCLK_USB_APP_125 6
-#define JH7110_STGCLK_USB_REFCLK 7
-#define JH7110_STGCLK_PCIE0_AXI 8
-#define JH7110_STGCLK_PCIE0_APB 9
-#define JH7110_STGCLK_PCIE0_TL 10
-#define JH7110_STGCLK_PCIE1_AXI 11
-#define JH7110_STGCLK_PCIE1_APB 12
-#define JH7110_STGCLK_PCIE1_TL 13
-#define JH7110_STGCLK_PCIE01_MAIN 14
-#define JH7110_STGCLK_SEC_HCLK 15
-#define JH7110_STGCLK_SEC_MISCAHB 16
-#define JH7110_STGCLK_MTRX_GRP0_MAIN 17
-#define JH7110_STGCLK_MTRX_GRP0_BUS 18
-#define JH7110_STGCLK_MTRX_GRP0_STG 19
-#define JH7110_STGCLK_MTRX_GRP1_MAIN 20
-#define JH7110_STGCLK_MTRX_GRP1_BUS 21
-#define JH7110_STGCLK_MTRX_GRP1_STG 22
-#define JH7110_STGCLK_MTRX_GRP1_HIFI 23
-#define JH7110_STGCLK_E2_RTC 24
-#define JH7110_STGCLK_E2_CORE 25
-#define JH7110_STGCLK_E2_DBG 26
-#define JH7110_STGCLK_DMA1P_AXI 27
-#define JH7110_STGCLK_DMA1P_AHB 28
-
-#define JH7110_STGCLK_END 29
-
-#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ */
diff --git a/include/dt-bindings/reset/starfive,jh7110-crg.h b/include/dt-bindings/reset/starfive,jh7110-crg.h
deleted file mode 100644
index 1d596581da7..00000000000
--- a/include/dt-bindings/reset/starfive,jh7110-crg.h
+++ /dev/null
@@ -1,183 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2022 StarFive Technology Co., Ltd.
- *
- * Author: Yanhong Wang <yanhong.wang@starfivetech.com>
- */
-
-#ifndef __DT_BINDINGS_RESET_STARFIVE_JH7110_H__
-#define __DT_BINDINGS_RESET_STARFIVE_JH7110_H__
-
-/* SYSCRG resets */
-#define JH7110_SYSRST_JTAG2APB 0
-#define JH7110_SYSRST_SYSCON 1
-#define JH7110_SYSRST_IOMUX_APB 2
-#define JH7110_SYSRST_BUS 3
-#define JH7110_SYSRST_DEBUG 4
-#define JH7110_SYSRST_CORE0 5
-#define JH7110_SYSRST_CORE1 6
-#define JH7110_SYSRST_CORE2 7
-#define JH7110_SYSRST_CORE3 8
-#define JH7110_SYSRST_CORE4 9
-#define JH7110_SYSRST_CORE0_ST 10
-#define JH7110_SYSRST_CORE1_ST 11
-#define JH7110_SYSRST_CORE2_ST 12
-#define JH7110_SYSRST_CORE3_ST 13
-#define JH7110_SYSRST_CORE4_ST 14
-#define JH7110_SYSRST_TRACE0 15
-#define JH7110_SYSRST_TRACE1 16
-#define JH7110_SYSRST_TRACE2 17
-#define JH7110_SYSRST_TRACE3 18
-#define JH7110_SYSRST_TRACE4 19
-#define JH7110_SYSRST_TRACE_COM 20
-#define JH7110_SYSRST_GPU_APB 21
-#define JH7110_SYSRST_GPU_DOMA 22
-#define JH7110_SYSRST_NOC_BUS_APB_BUS 23
-#define JH7110_SYSRST_NOC_BUS_AXICFG0_AXI 24
-#define JH7110_SYSRST_NOC_BUS_CPU_AXI 25
-#define JH7110_SYSRST_NOC_BUS_DISP_AXI 26
-#define JH7110_SYSRST_NOC_BUS_GPU_AXI 27
-#define JH7110_SYSRST_NOC_BUS_ISP_AXI 28
-#define JH7110_SYSRST_NOC_BUS_DDRC 29
-#define JH7110_SYSRST_NOC_BUS_STG_AXI 30
-#define JH7110_SYSRST_NOC_BUS_VDEC_AXI 31
-
-#define JH7110_SYSRST_NOC_BUS_VENC_AXI 32
-#define JH7110_SYSRST_AXI_CFG1_DEC_AHB 33
-#define JH7110_SYSRST_AXI_CFG1_DEC_MAIN 34
-#define JH7110_SYSRST_AXI_CFG0_DEC_MAIN 35
-#define JH7110_SYSRST_AXI_CFG0_DEC_MAIN_DIV 36
-#define JH7110_SYSRST_AXI_CFG0_DEC_HIFI4 37
-#define JH7110_SYSRST_DDR_AXI 38
-#define JH7110_SYSRST_DDR_OSC 39
-#define JH7110_SYSRST_DDR_APB 40
-#define JH7110_SYSRST_DOM_ISP_TOP_N 41
-#define JH7110_SYSRST_DOM_ISP_TOP_AXI 42
-#define JH7110_SYSRST_DOM_VOUT_TOP_SRC 43
-#define JH7110_SYSRST_CODAJ12_AXI 44
-#define JH7110_SYSRST_CODAJ12_CORE 45
-#define JH7110_SYSRST_CODAJ12_APB 46
-#define JH7110_SYSRST_WAVE511_AXI 47
-#define JH7110_SYSRST_WAVE511_BPU 48
-#define JH7110_SYSRST_WAVE511_VCE 49
-#define JH7110_SYSRST_WAVE511_APB 50
-#define JH7110_SYSRST_VDEC_JPG_ARB_JPG 51
-#define JH7110_SYSRST_VDEC_JPG_ARB_MAIN 52
-#define JH7110_SYSRST_AXIMEM0_AXI 53
-#define JH7110_SYSRST_WAVE420L_AXI 54
-#define JH7110_SYSRST_WAVE420L_BPU 55
-#define JH7110_SYSRST_WAVE420L_VCE 56
-#define JH7110_SYSRST_WAVE420L_APB 57
-#define JH7110_SYSRST_AXIMEM1_AXI 58
-#define JH7110_SYSRST_AXIMEM2_AXI 59
-#define JH7110_SYSRST_INTMEM 60
-#define JH7110_SYSRST_QSPI_AHB 61
-#define JH7110_SYSRST_QSPI_APB 62
-#define JH7110_SYSRST_QSPI_REF 63
-
-#define JH7110_SYSRST_SDIO0_AHB 64
-#define JH7110_SYSRST_SDIO1_AHB 65
-#define JH7110_SYSRST_GMAC1_AXI 66
-#define JH7110_SYSRST_GMAC1_AHB 67
-#define JH7110_SYSRST_MAILBOX 68
-#define JH7110_SYSRST_SPI0_APB 69
-#define JH7110_SYSRST_SPI1_APB 70
-#define JH7110_SYSRST_SPI2_APB 71
-#define JH7110_SYSRST_SPI3_APB 72
-#define JH7110_SYSRST_SPI4_APB 73
-#define JH7110_SYSRST_SPI5_APB 74
-#define JH7110_SYSRST_SPI6_APB 75
-#define JH7110_SYSRST_I2C0_APB 76
-#define JH7110_SYSRST_I2C1_APB 77
-#define JH7110_SYSRST_I2C2_APB 78
-#define JH7110_SYSRST_I2C3_APB 79
-#define JH7110_SYSRST_I2C4_APB 80
-#define JH7110_SYSRST_I2C5_APB 81
-#define JH7110_SYSRST_I2C6_APB 82
-#define JH7110_SYSRST_UART0_APB 83
-#define JH7110_SYSRST_UART0_CORE 84
-#define JH7110_SYSRST_UART1_APB 85
-#define JH7110_SYSRST_UART1_CORE 86
-#define JH7110_SYSRST_UART2_APB 87
-#define JH7110_SYSRST_UART2_CORE 88
-#define JH7110_SYSRST_UART3_APB 89
-#define JH7110_SYSRST_UART3_CORE 90
-#define JH7110_SYSRST_UART4_APB 91
-#define JH7110_SYSRST_UART4_CORE 92
-#define JH7110_SYSRST_UART5_APB 93
-#define JH7110_SYSRST_UART5_CORE 94
-#define JH7110_SYSRST_SPDIF_APB 95
-
-#define JH7110_SYSRST_PWMDAC_APB 96
-#define JH7110_SYSRST_PDM_DMIC 97
-#define JH7110_SYSRST_PDM_APB 98
-#define JH7110_SYSRST_I2SRX_APB 99
-#define JH7110_SYSRST_I2SRX_BCLK 100
-#define JH7110_SYSRST_I2STX0_APB 101
-#define JH7110_SYSRST_I2STX0_BCLK 102
-#define JH7110_SYSRST_I2STX1_APB 103
-#define JH7110_SYSRST_I2STX1_BCLK 104
-#define JH7110_SYSRST_TDM_AHB 105
-#define JH7110_SYSRST_TDM_CORE 106
-#define JH7110_SYSRST_TDM_APB 107
-#define JH7110_SYSRST_PWM_APB 108
-#define JH7110_SYSRST_WDT_APB 109
-#define JH7110_SYSRST_WDT_CORE 110
-#define JH7110_SYSRST_CAN0_APB 111
-#define JH7110_SYSRST_CAN0_CORE 112
-#define JH7110_SYSRST_CAN0_TIMER 113
-#define JH7110_SYSRST_CAN1_APB 114
-#define JH7110_SYSRST_CAN1_CORE 115
-#define JH7110_SYSRST_CAN1_TIMER 116
-#define JH7110_SYSRST_TIMER_APB 117
-#define JH7110_SYSRST_TIMER0 118
-#define JH7110_SYSRST_TIMER1 119
-#define JH7110_SYSRST_TIMER2 120
-#define JH7110_SYSRST_TIMER3 121
-#define JH7110_SYSRST_INT_CTRL_APB 122
-#define JH7110_SYSRST_TEMP_APB 123
-#define JH7110_SYSRST_TEMP_CORE 124
-#define JH7110_SYSRST_JTAG_CERTIFICATION 125
-
-#define JH7110_SYSRST_END 126
-
-/* AONCRG resets */
-#define JH7110_AONRST_GMAC0_AXI 0
-#define JH7110_AONRST_GMAC0_AHB 1
-#define JH7110_AONRST_IOMUX 2
-#define JH7110_AONRST_PMU_APB 3
-#define JH7110_AONRST_PMU_WKUP 4
-#define JH7110_AONRST_RTC_APB 5
-#define JH7110_AONRST_RTC_CAL 6
-#define JH7110_AONRST_RTC_32K 7
-
-#define JH7110_AONRST_END 8
-
-/* STGCRG resets */
-#define JH7110_STGRST_SYSCON_PRESETN 0
-#define JH7110_STGRST_HIFI4_CORE 1
-#define JH7110_STGRST_HIFI4_AXI 2
-#define JH7110_STGRST_SEC_TOP_HRESETN 3
-#define JH7110_STGRST_E24_CORE 4
-#define JH7110_STGRST_DMA1P_AXI 5
-#define JH7110_STGRST_DMA1P_AHB 6
-#define JH7110_STGRST_USB_AXI 7
-#define JH7110_STGRST_USB_APB 8
-#define JH7110_STGRST_USB_UTMI_APB 9
-#define JH7110_STGRST_USB_PWRUP 10
-#define JH7110_STGRST_PCIE0_MST0 11
-#define JH7110_STGRST_PCIE0_SLV0 12
-#define JH7110_STGRST_PCIE0_SLV 13
-#define JH7110_STGRST_PCIE0_BRG 14
-#define JH7110_STGRST_PCIE0_CORE 15
-#define JH7110_STGRST_PCIE0_APB 16
-#define JH7110_STGRST_PCIE1_MST0 17
-#define JH7110_STGRST_PCIE1_SLV0 18
-#define JH7110_STGRST_PCIE1_SLV 19
-#define JH7110_STGRST_PCIE1_BRG 20
-#define JH7110_STGRST_PCIE1_CORE 21
-#define JH7110_STGRST_PCIE1_APB 22
-
-#define JH7110_STGRST_END 23
-
-#endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_H__ */
diff --git a/include/efi.h b/include/efi.h
index c559fda3004..d50b3d3cec9 100644
--- a/include/efi.h
+++ b/include/efi.h
@@ -175,7 +175,7 @@ enum efi_allocate_type {
EFI_ALLOCATE_MAX_ADDRESS,
/**
* @EFI_ALLOCATE_ADDRESS:
- * Allocate a memory block starting at the indicatged adress.
+ * Allocate a memory block starting at the indicated address.
*/
EFI_ALLOCATE_ADDRESS,
/**
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 555c9520379..d9fcd037ed2 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -136,23 +136,6 @@ struct fdt_pci_addr {
u32 phys_lo;
};
-extern u8 __dtb_dt_begin[]; /* embedded device tree blob */
-extern u8 __dtb_dt_spl_begin[]; /* embedded device tree blob for SPL/TPL */
-
-/* Get a pointer to the embedded devicetree, if there is one, else NULL */
-static inline u8 *dtb_dt_embedded(void)
-{
-#ifdef CONFIG_OF_EMBED
-# ifdef CONFIG_XPL_BUILD
- return __dtb_dt_spl_begin;
-# else
- return __dtb_dt_begin;
-# endif
-#else
- return NULL;
-#endif
-}
-
/**
* Compute the size of a resource.
*
@@ -1156,6 +1139,13 @@ int fdtdec_set_carveout(void *blob, const char *node, const char *prop_name,
unsigned int count, unsigned long flags);
/**
+ * fdtdec_setup_embed - pick up embedded DTS
+ *
+ * Should be invoked under CONFIG_OF_EMBED guard.
+ */
+void fdtdec_setup_embed(void);
+
+/**
* Set up the device tree ready for use
*/
int fdtdec_setup(void);
@@ -1191,11 +1181,12 @@ int fdtdec_resetup(int *rescan);
*
* The existing devicetree is available at gd->fdt_blob
*
- * @err: 0 on success, -EEXIST if the devicetree is already correct, or other
- * internal error code if we fail to setup a DTB
- * @returns new devicetree blob pointer
+ * @fdtp: Existing devicetree blob pointer; update this and return 0 if a
+ * different devicetree should be used
+ * Return: 0 on success, -EEXIST if the existing FDT is OK, -ve error code if we
+ * fail to setup a DTB
*/
-void *board_fdt_blob_setup(int *err);
+int board_fdt_blob_setup(void **fdtp);
/*
* Decode the size of memory
diff --git a/include/image.h b/include/image.h
index 9be5acd8158..0a61dfd556c 100644
--- a/include/image.h
+++ b/include/image.h
@@ -1172,6 +1172,18 @@ int fit_image_get_data_and_size(const void *fit, int noffset,
const void **data, size_t *size);
/**
+ * fit_image_get_phase() - Get the phase from a FIT image
+ *
+ * @fit: FIT to read from
+ * @offset: offset node to read
+ * @phasep: Returns phase, if any
+ * Return: 0 if read OK and *phasep is value, -ENOENT if there was no phase
+ * property in the node, other -ve value on other error
+ */
+int fit_image_get_phase(const void *fit, int offset,
+ enum image_phase_t *phasep);
+
+/**
* fit_get_data_node() - Get verified image data for an image
* @fit: Pointer to the FIT format image header
* @image_uname: The name of the image node
@@ -1399,7 +1411,9 @@ int fit_check_format(const void *fit, ulong size);
* copied into the configuration node in the FIT image. This is required to
* match configurations with compressed FDTs.
*
- * Returns: offset to the configuration to use if one was found, -1 otherwise
+ * Returns: offset to the configuration to use if one was found, -EINVAL if
+ * there a /configurations or /images node is missing, -ENOENT if no match was
+ * found, -ENXIO if the FDT node has no compatible string
*/
int fit_conf_find_compat(const void *fit, const void *fdt);
@@ -1788,6 +1802,21 @@ struct cipher_algo {
const unsigned char *data, int data_len,
unsigned char **cipher, int *cipher_len);
+ /**
+ * add_cipher_data() - Add cipher data to the FIT and device tree
+ *
+ * This is used to add the ciphered data to the FIT and other cipher
+ * related information (key and initialization vector) to a device tree.
+ *
+ * @info: Pointer to image cipher information.
+ * @keydest: Pointer to a device tree where the key and IV can be
+ * stored. keydest can be NULL when the key is retrieved at
+ * runtime by another mean.
+ * @fit: Pointer to the FIT image.
+ * @node_noffset: Offset where the cipher information are stored in the
+ * FIT.
+ * return: 0 on success, a negative error code otherwise.
+ */
int (*add_cipher_data)(struct image_cipher_info *info,
void *keydest, void *fit, int node_noffset);
diff --git a/include/limits.h b/include/limits.h
index 4700cc7a59f..1d0bbf69be7 100644
--- a/include/limits.h
+++ b/include/limits.h
@@ -9,7 +9,8 @@
#define UINT32_MAX 0xffffffffU
#define UINT64_MAX 0xffffffffffffffffULL
-#ifdef CONFIG_64BIT
+#if (defined(CONFIG_64BIT) && !defined(CONFIG_SPL_BUILD)) || \
+ (defined(CONFIG_SPL_64BIT) && defined(CONFIG_SPL_BUILD))
#define UINTPTR_MAX UINT64_MAX
#else
#define UINTPTR_MAX UINT32_MAX
diff --git a/include/lmb.h b/include/lmb.h
index f221f0cce8f..d9d7435a431 100644
--- a/include/lmb.h
+++ b/include/lmb.h
@@ -1,6 +1,13 @@
/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Logical memory blocks.
+ *
+ * Copyright (C) 2001 Peter Bergner, IBM Corp.
+ */
+
#ifndef _LINUX_LMB_H
#define _LINUX_LMB_H
+
#ifdef __KERNEL__
#include <alist.h>
@@ -8,101 +15,106 @@
#include <asm/u-boot.h>
#include <linux/bitops.h>
-/*
- * Logical memory blocks.
- *
- * Copyright (C) 2001 Peter Bergner, IBM Corp.
- */
-
-#define LMB_ALLOC_ANYWHERE 0
-#define LMB_ALIST_INITIAL_SIZE 4
+#define LMB_ALLOC_ANYWHERE 0
+#define LMB_ALIST_INITIAL_SIZE 4
/**
- * enum lmb_flags - definition of memory region attributes
- * @LMB_NONE: no special request
- * @LMB_NOMAP: don't add to mmu configuration
- * @LMB_NOOVERWRITE: the memory region cannot be overwritten/re-reserved
- * @LMB_NONOTIFY: do not notify other modules of changes to this memory region
- */
-enum lmb_flags {
- LMB_NONE = 0,
- LMB_NOMAP = BIT(1),
- LMB_NOOVERWRITE = BIT(2),
- LMB_NONOTIFY = BIT(3),
-};
+ * DOC: Memory region attribute flags.
+ *
+ * %LMB_NONE: No special request
+ * %LMB_NOMAP: Don't add to MMU configuration
+ * %LMB_NOOVERWRITE: The memory region cannot be overwritten/re-reserved
+ * %LMB_NONOTIFY: Do not notify other modules of changes to this memory region
+ */
+#define LMB_NONE 0
+#define LMB_NOMAP BIT(0)
+#define LMB_NOOVERWRITE BIT(1)
+#define LMB_NONOTIFY BIT(2)
/**
- * struct lmb_region - Description of one region.
- *
- * @base: Base address of the region.
- * @size: Size of the region
- * @flags: memory region attributes
+ * struct lmb_region - Description of one region
+ * @base: Base address of the region
+ * @size: Size of the region
+ * @flags: Memory region attributes
*/
struct lmb_region {
phys_addr_t base;
phys_size_t size;
- enum lmb_flags flags;
+ u32 flags;
};
/**
* struct lmb - The LMB structure
- *
- * @free_mem: List of free memory regions
- * @used_mem: List of used/reserved memory regions
- * @test: Is structure being used for LMB tests
+ * @available_mem: List of memory available to LMB
+ * @used_mem: List of used/reserved memory regions
+ * @test: Is structure being used for LMB tests
*/
struct lmb {
- struct alist free_mem;
+ struct alist available_mem;
struct alist used_mem;
bool test;
};
/**
- * lmb_init() - Initialise the LMB module
+ * lmb_init() - Initialise the LMB module.
+ *
+ * Return: 0 on success, negative error code on failure.
*
* Initialise the LMB lists needed for keeping the memory map. There
- * are two lists, in form of alloced list data structure. One for the
+ * are two lists, in form of allocated list data structure. One for the
* available memory, and one for the used memory. Initialise the two
* lists as part of board init. Add memory to the available memory
* list and reserve common areas by adding them to the used memory
* list.
- *
- * Return: 0 on success, -ve on error
*/
int lmb_init(void);
/**
- * lmb_add_memory() - Add memory range for LMB allocations
+ * lmb_add_memory() - Add memory range for LMB allocations.
*
* Add the entire available memory range to the pool of memory that
* can be used by the LMB module for allocations.
- *
- * Return: None
*/
void lmb_add_memory(void);
long lmb_add(phys_addr_t base, phys_size_t size);
-long lmb_reserve(phys_addr_t base, phys_size_t size);
+
/**
- * lmb_reserve_flags - Reserve one region with a specific flags bitfield.
- *
- * @base: base address of the memory region
- * @size: size of the memory region
- * @flags: flags for the memory region
- * Return: 0 if OK, > 0 for coalesced region or a negative error code.
+ * lmb_reserve() - Reserve one region with a specific flags bitfield
+ * @base: Base address of the memory region
+ * @size: Size of the memory region
+ * @flags: Flags for the memory region
+ *
+ * Return:
+ * * %0 - Added successfully, or it's already added (only if LMB_NONE)
+ * * %-EEXIST - The region is already added, and flags != LMB_NONE
+ * * %-1 - Failure
*/
-long lmb_reserve_flags(phys_addr_t base, phys_size_t size,
- enum lmb_flags flags);
+long lmb_reserve(phys_addr_t base, phys_size_t size, u32 flags);
+
phys_addr_t lmb_alloc(phys_size_t size, ulong align);
-phys_addr_t lmb_alloc_base(phys_size_t size, ulong align, phys_addr_t max_addr);
-phys_addr_t lmb_alloc_addr(phys_addr_t base, phys_size_t size);
phys_size_t lmb_get_free_size(phys_addr_t addr);
-phys_addr_t lmb_alloc_base_flags(phys_size_t size, ulong align,
- phys_addr_t max_addr, uint flags);
+/**
+ * lmb_alloc_base() - Allocate specified memory region with specified
+ * attributes
+ * @size: Size of the region requested
+ * @align: Alignment of the memory region requested
+ * @max_addr: Maximum address of the requested region
+ * @flags: Memory region attributes to be set
+ *
+ * Allocate a region of memory with the attributes specified through the
+ * parameter. The max_addr parameter is used to specify the maximum address
+ * below which the requested region should be allocated.
+ *
+ * Return: Base address on success, 0 on error.
+ */
+phys_addr_t lmb_alloc_base(phys_size_t size, ulong align, phys_addr_t max_addr,
+ uint flags);
/**
- * lmb_alloc_addr_flags() - Allocate specified memory address with specified attributes
+ * lmb_alloc_addr() - Allocate specified memory address with specified attributes
+ *
* @base: Base Address requested
* @size: Size of the region requested
* @flags: Memory region attributes to be set
@@ -111,20 +123,20 @@ phys_addr_t lmb_alloc_base_flags(phys_size_t size, ulong align,
* parameter. The base parameter is used to specify the base address
* of the requested region.
*
- * Return: base address on success, 0 on error
+ * Return: Base address on success, 0 on error.
*/
-phys_addr_t lmb_alloc_addr_flags(phys_addr_t base, phys_size_t size,
- uint flags);
+phys_addr_t lmb_alloc_addr(phys_addr_t base, phys_size_t size, u32 flags);
/**
- * lmb_is_reserved_flags() - test if address is in reserved region with flag bits set
+ * lmb_is_reserved_flags() - Test if address is in reserved region with flag
+ * bits set
+ * @addr: Address to be tested
+ * @flags: Bitmap with bits to be tested
*
* The function checks if a reserved region comprising @addr exists which has
* all flag bits set which are set in @flags.
*
- * @addr: address to be tested
- * @flags: bitmap with bits to be tested
- * Return: 1 if matching reservation exists, 0 otherwise
+ * Return: 1 if matching reservation exists, 0 otherwise.
*/
int lmb_is_reserved_flags(phys_addr_t addr, int flags);
@@ -134,9 +146,7 @@ int lmb_is_reserved_flags(phys_addr_t addr, int flags);
* @size: Size of the region to be freed
* @flags: Memory region attributes
*
- * Free up a region of memory.
- *
- * Return: 0 if successful, -1 on failure
+ * Return: 0 on success, negative error code on failure.
*/
long lmb_free_flags(phys_addr_t base, phys_size_t size, uint flags);
@@ -153,14 +163,14 @@ void lmb_pop(struct lmb *store);
static inline int lmb_read_check(phys_addr_t addr, phys_size_t len)
{
- return lmb_alloc_addr(addr, len) == addr ? 0 : -1;
+ return lmb_alloc_addr(addr, len, LMB_NONE) == addr ? 0 : -1;
}
/**
* io_lmb_setup() - Initialize LMB struct
* @io_lmb: IO LMB to initialize
*
- * Returns: 0 on success, negative error code on failure
+ * Return: 0 on success, negative error code on failure.
*/
int io_lmb_setup(struct lmb *io_lmb);
@@ -178,12 +188,13 @@ void io_lmb_teardown(struct lmb *io_lmb);
*
* Add the IOVA space [base, base + size] to be managed by io_lmb.
*
- * Returns: 0 if the region addition was successful, -1 on failure
+ * Return: 0 on success, negative error code on failure.
*/
long io_lmb_add(struct lmb *io_lmb, phys_addr_t base, phys_size_t size);
/**
- * io_lmb_alloc() - Allocate specified IO memory address with specified alignment
+ * io_lmb_alloc() - Allocate specified IO memory address with specified
+ * alignment
* @io_lmb: LMB to alloc from
* @size: Size of the region requested
* @align: Required address and size alignment
@@ -191,7 +202,7 @@ long io_lmb_add(struct lmb *io_lmb, phys_addr_t base, phys_size_t size);
* Allocate a region of IO memory. The base parameter is used to specify the
* base address of the requested region.
*
- * Return: base IO address on success, 0 on error
+ * Return: Base IO address on success, 0 on error.
*/
phys_addr_t io_lmb_alloc(struct lmb *io_lmb, phys_size_t size, ulong align);
@@ -201,9 +212,7 @@ phys_addr_t io_lmb_alloc(struct lmb *io_lmb, phys_size_t size, ulong align);
* @base: Base Address of region to be freed
* @size: Size of the region to be freed
*
- * Free up a region of IOVA space.
- *
- * Return: 0 if successful, -1 on failure
+ * Return: 0 on success, negative error code on failure.
*/
long io_lmb_free(struct lmb *io_lmb, phys_addr_t base, phys_size_t size);
diff --git a/include/net-common.h b/include/net-common.h
index 8fc1bac47f5..29d31f37263 100644
--- a/include/net-common.h
+++ b/include/net-common.h
@@ -427,7 +427,7 @@ void string_to_enetaddr(const char *addr, uint8_t *enetaddr);
struct in_addr string_to_ip(const char *s);
/**
- * ip_to_string() - Convert a string to ip address
+ * ip_to_string() - Convert an IPv4 address to a string
*
* Implemented in lib/net_utils.c (built unconditionally)
*
diff --git a/include/net-legacy.h b/include/net-legacy.h
index 1f62ebff51d..bc0f0cde9fe 100644
--- a/include/net-legacy.h
+++ b/include/net-legacy.h
@@ -416,6 +416,7 @@ int net_send_ip_packet(uchar *ether, struct in_addr dest, int dport, int sport,
/**
* net_send_tcp_packet() - Transmit TCP packet.
* @payload_len: length of payload
+ * @dhost: Destination host
* @dport: Destination TCP port
* @sport: Source TCP port
* @action: TCP action to be performed
@@ -424,8 +425,8 @@ int net_send_ip_packet(uchar *ether, struct in_addr dest, int dport, int sport,
*
* Return: 0 on success, other value on failure
*/
-int net_send_tcp_packet(int payload_len, int dport, int sport, u8 action,
- u32 tcp_seq_num, u32 tcp_ack_num);
+int net_send_tcp_packet(int payload_len, struct in_addr dhost, int dport,
+ int sport, u8 action, u32 tcp_seq_num, u32 tcp_ack_num);
int net_send_udp_packet(uchar *ether, struct in_addr dest, int dport,
int sport, int payload_len);
diff --git a/include/net/tcp.h b/include/net/tcp.h
index c29d4ce24a7..5022fa9dc1b 100644
--- a/include/net/tcp.h
+++ b/include/net/tcp.h
@@ -265,6 +265,7 @@ union tcp_build_pkt {
* @TCP_CLOSING: Rec FIN, sent FIN, ACK waiting for ACK
* @TCP_FIN_WAIT_1: Sent FIN waiting for response
* @TCP_FIN_WAIT_2: Rec ACK from FIN sent, waiting for FIN
+ * @TCP_LAST_ACK: Waiting for ACK of the connection termination
*/
enum tcp_state {
TCP_CLOSED,
@@ -274,30 +275,248 @@ enum tcp_state {
TCP_CLOSE_WAIT,
TCP_CLOSING,
TCP_FIN_WAIT_1,
- TCP_FIN_WAIT_2
+ TCP_FIN_WAIT_2,
+ TCP_LAST_ACK,
};
-enum tcp_state tcp_get_tcp_state(void);
-void tcp_set_tcp_state(enum tcp_state new_state);
-int tcp_set_tcp_header(uchar *pkt, int dport, int sport, int payload_len,
- u8 action, u32 tcp_seq_num, u32 tcp_ack_num);
+/**
+ * enum tcp_status - TCP stream status for connection
+ * @TCP_ERR_OK: no rx/tx errors
+ * @TCP_ERR_TOUT: rx/tx timeout happened
+ * @TCP_ERR_RST: connection was reset
+ * @TCP_ERR_IO: input/output error
+ */
+enum tcp_status {
+ TCP_ERR_OK = 0,
+ TCP_ERR_TOUT,
+ TCP_ERR_RST,
+ TCP_ERR_IO
+};
/**
- * rxhand_tcp() - An incoming packet handler.
- * @pkt: pointer to the application packet
- * @dport: destination TCP port
- * @sip: source IP address
- * @sport: source TCP port
- * @tcp_seq_num: TCP sequential number
- * @tcp_ack_num: TCP acknowledgment number
- * @action: TCP action (SYN, ACK, FIN, etc)
- * @len: packet length
+ * struct tcp_stream - TCP data stream structure
+ * @rhost: Remote host, network byte order
+ * @rport: Remote port, host byte order
+ * @lport: Local port, host byte order
+ *
+ * @priv: User private data (not used by tcp module)
+ *
+ * @max_retry_count: Maximum retransmit attempts (default 3)
+ * @initial_timeout: Timeout from initial TX to reTX (default 2 sec)
+ * @rx_inactiv_timeout: Maximum time from last rx till connection drop
+ * (default 30 sec)
+ *
+ * @on_closed: User callback, called just before destroying TCP stream
+ * @on_established: User callback, called when TCP stream enters
+ * TCP_ESTABLISHED state
+ * @on_rcv_nxt_update: User callback, called when all data in the segment
+ * [0..rx_bytes - 1] was received
+ * @on_snd_una_update: User callback, called when all data in the segment
+ * [0..tx_bytes - 1] were transferred and acknowledged
+ * @rx: User callback, called on receive of segment
+ * [rx_offs..rx_offs+len-1]. If NULL -- all incoming data
+ * will be ignored. User SHOULD store the segment and
+ * return the number of accepted bytes or negative value
+ * on error.
+ * WARNING: Previous segmengs may not be received yet
+ * @tx: User callback, called on transmit/retransmit of segment
+ * [tx_offs..tx_offs+maxlen-1]. If NULL -- no data will
+ * be transmitted. User SHOULD fill provided buffer and
+ * return the number of bytes in the buffer or negative
+ * value on error.
+ * WARNING: do not use tcp_stream_close() from this
+ * callback (it will break stream). Better use
+ * on_snd_una_update() callback for such purposes.
+ *
+ * @time_last_rx: Arrival time of last valid incoming package (ticks)
+ * @time_start: Timeout start time (ticks)
+ * @time_delta: Timeout duration (ticks)
+ * @time_handler Timeout handler for a stream
+ *
+ * @state: TCP connection state
+ * @status: TCP stream status (OK or ERR)
+ * @rx_packets: total number of received packets
+ * @tx_packets: total number of transmitted packets
+ *
+ * @fin_rx: Non-zero if TCP_FIN was received
+ * @fin_rx_seq: TCP sequence of rx FIN bit
+ * @fin_tx: Non-zero if TCP_FIN was sent (or planned to send)
+ * @fin_tx_seq: TCP sequence of tx FIN bit
+ *
+ * @iss: Initial send sequence number
+ * @snd_una: Send unacknowledged
+ * @snd_nxt: Send next
+ * @snd_wnd: Send window (in bytes)
+ * @snd_wl1: Segment sequence number used for last window update
+ * @snd_wl2: Segment acknowledgment number used for last window update
+ *
+ * @irs: Initial receive sequence number
+ * @rcv_nxt: Receive next
+ * @rcv_wnd: Receive window (in bytes)
+ *
+ * @loc_timestamp: Local timestamp
+ * @rmt_timestamp: Remote timestamp
+ *
+ * @rmt_win_scale: Remote window scale factor
+ *
+ * @lost: Used for SACK
+ *
+ * @retry_cnt: Number of retry attempts remaining. Only SYN, FIN
+ * or DATA segments are tried to retransmit.
+ * @retry_timeout: Current retry timeout (ms)
+ * @retry_action: TCP flags used for sending
+ * @retry_seq_num: TCP sequence for retransmit
+ * retry_tx_len: Number of data to transmit
+ * @retry_tx_offs: Position in the TX stream
*/
-typedef void rxhand_tcp(uchar *pkt, u16 dport,
- struct in_addr sip, u16 sport,
- u32 tcp_seq_num, u32 tcp_ack_num,
- u8 action, unsigned int len);
-void tcp_set_tcp_handler(rxhand_tcp *f);
+struct tcp_stream {
+ struct in_addr rhost;
+ u16 rport;
+ u16 lport;
+
+ void *priv;
+
+ int max_retry_count;
+ int initial_timeout;
+ int rx_inactiv_timeout;
+
+ void (*on_closed)(struct tcp_stream *tcp);
+ void (*on_established)(struct tcp_stream *tcp);
+ void (*on_rcv_nxt_update)(struct tcp_stream *tcp, u32 rx_bytes);
+ void (*on_snd_una_update)(struct tcp_stream *tcp, u32 tx_bytes);
+ int (*rx)(struct tcp_stream *tcp, u32 rx_offs, void *buf, int len);
+ int (*tx)(struct tcp_stream *tcp, u32 tx_offs, void *buf, int maxlen);
+
+ ulong time_last_rx;
+ ulong time_start;
+ ulong time_delta;
+ void (*time_handler)(struct tcp_stream *tcp);
+
+ enum tcp_state state;
+ enum tcp_status status;
+ u32 rx_packets;
+ u32 tx_packets;
+
+ int fin_rx;
+ u32 fin_rx_seq;
+
+ int fin_tx;
+ u32 fin_tx_seq;
+
+ u32 iss;
+ u32 snd_una;
+ u32 snd_nxt;
+ u32 snd_wnd;
+ u32 snd_wl1;
+ u32 snd_wl2;
+
+ u32 irs;
+ u32 rcv_nxt;
+ u32 rcv_wnd;
+
+ /* TCP option timestamp */
+ u32 loc_timestamp;
+ u32 rmt_timestamp;
+
+ /* TCP window scale */
+ u8 rmt_win_scale;
+
+ /* TCP sliding window control used to request re-TX */
+ struct tcp_sack_v lost;
+
+ /* used for data retransmission */
+ int retry_cnt;
+ int retry_timeout;
+ u8 retry_action;
+ u32 retry_seq_num;
+ u32 retry_tx_len;
+ u32 retry_tx_offs;
+};
+
+void tcp_init(void);
+
+/*
+ * This function sets user callback called on TCP stream creation.
+ * Callback should:
+ * + Check TCP stream endpoint and make connection verdict
+ * - return non-zero value to accept connection
+ * - return zero to drop connection
+ * + Setup TCP stream callbacks like: on_closed(), on_established(),
+ * n_rcv_nxt_update(), on_snd_una_update(), rx() and tx().
+ * + Setup other stream related data
+ *
+ * WARNING: User MUST setup TCP stream on_create handler. Without it
+ * no connection (including outgoung) will be created.
+ */
+void tcp_stream_set_on_create_handler(int (*on_create)(struct tcp_stream *));
+
+/*
+ * tcp_stream_get -- Get or create TCP stream
+ * @is_new: if non-zero and no stream found, then create a new one
+ * @rhost: Remote host, network byte order
+ * @rport: Remote port, host byte order
+ * @lport: Local port, host byte order
+ *
+ * Returns: TCP stream structure or NULL (if not found/created)
+ */
+struct tcp_stream *tcp_stream_get(int is_new, struct in_addr rhost,
+ u16 rport, u16 lport);
+
+/*
+ * tcp_stream_connect -- Create new TCP stream for remote connection.
+ * @rhost: Remote host, network byte order
+ * @rport: Remote port, host byte order
+ *
+ * Returns: TCP new stream structure or NULL (if not created).
+ * Random local port will be used.
+ */
+struct tcp_stream *tcp_stream_connect(struct in_addr rhost, u16 rport);
+
+/*
+ * tcp_stream_put -- Return stream to a TCP subsystem. Subsystem will
+ * check stream and destroy it (if stream was already
+ * closed). Otherwize no stream change will happen.
+ * @tcp: TCP stream to put
+ */
+void tcp_stream_put(struct tcp_stream *tcp);
+
+/*
+ * tcp_stream_restart_rx_timer -- Restart RX inactivity timer. Usually there
+ * is no needs to call this function. Timer
+ * will be restarted on receiving of any valid
+ * tcp packet belonging to a stream.
+ *
+ * This function may be used to prevent connection
+ * break in the following case:
+ * - u-boot is busy with very long data processing
+ * - remote side waits for u-boot reply
+ *
+ * @tcp: TCP stream to put
+ */
+void tcp_stream_restart_rx_timer(struct tcp_stream *tcp);
+
+enum tcp_state tcp_stream_get_state(struct tcp_stream *tcp);
+enum tcp_status tcp_stream_get_status(struct tcp_stream *tcp);
+
+/*
+ * tcp_stream_rx_offs(),
+ * tcp_stream_tx_offs() -- Returns offset of first unacknowledged byte
+ * in receive/transmit stream correspondingly.
+ * The result is NOT affected by sin/fin flags.
+ * @tcp: TCP stream
+ */
+u32 tcp_stream_rx_offs(struct tcp_stream *tcp);
+u32 tcp_stream_tx_offs(struct tcp_stream *tcp);
+
+/* reset tcp stream */
+void tcp_stream_reset(struct tcp_stream *tcp);
+/* force TCP stream closing, do NOT use from tcp->tx callback */
+void tcp_stream_close(struct tcp_stream *tcp);
+
+void tcp_streams_poll(void);
+
+int tcp_set_tcp_header(struct tcp_stream *tcp, uchar *pkt, int payload_len,
+ u8 action, u32 tcp_seq_num, u32 tcp_ack_num);
void rxhand_tcp_f(union tcp_build_pkt *b, unsigned int len);
diff --git a/include/net/wget.h b/include/net/wget.h
index 6714f7ea573..9a423b30414 100644
--- a/include/net/wget.h
+++ b/include/net/wget.h
@@ -8,14 +8,6 @@
*/
void wget_start(void);
-enum wget_state {
- WGET_CLOSED,
- WGET_CONNECTING,
- WGET_CONNECTED,
- WGET_TRANSFERRING,
- WGET_TRANSFERRED
-};
-
#define DEBUG_WGET 0 /* Set to 1 for debug messages */
#define WGET_RETRY_COUNT 30
#define WGET_TIMEOUT 2000UL
diff --git a/include/ns16550.h b/include/ns16550.h
index 7f481300083..5d9ff105411 100644
--- a/include/ns16550.h
+++ b/include/ns16550.h
@@ -25,6 +25,7 @@
#define __ns16550_h
#include <linux/types.h>
+#include <serial.h>
#if CONFIG_IS_ENABLED(DM_SERIAL) || defined(CONFIG_NS16550_DYNAMIC) || \
defined(CONFIG_DEBUG_UART)
@@ -116,6 +117,15 @@ struct ns16550 {
#endif
};
+#if CONFIG_IS_ENABLED(DM_SERIAL)
+#define serial_out(value, addr) \
+ ns16550_writeb(com_port, \
+ (unsigned char *)(addr) - (unsigned char *)com_port, value)
+#define serial_in(addr) \
+ ns16550_readb(com_port, \
+ (unsigned char *)(addr) - (unsigned char *)com_port)
+#endif
+
#define thr rbr
#define iir fcr
#define dll rbr
@@ -225,6 +235,14 @@ void ns16550_putc(struct ns16550 *com_port, char c);
char ns16550_getc(struct ns16550 *com_port);
int ns16550_tstc(struct ns16550 *com_port);
void ns16550_reinit(struct ns16550 *com_port, int baud_divisor);
+int ns16550_serial_putc(struct udevice *dev, const char ch);
+int ns16550_serial_pending(struct udevice *dev, bool input);
+int ns16550_serial_getc(struct udevice *dev);
+int ns16550_serial_setbrg(struct udevice *dev, int baudrate);
+int ns16550_serial_setconfig(struct udevice *dev, uint serial_config);
+int ns16550_serial_getinfo(struct udevice *dev, struct serial_device_info *info);
+void ns16550_writeb(struct ns16550 *port, int offset, int value);
+void ns16550_setbrg(struct ns16550 *com_port, int baud_divisor);
/**
* ns16550_calc_divisor() - calculate the divisor given clock and baud rate
diff --git a/include/ppc_asm.tmpl b/include/ppc_asm.tmpl
index db7b1668d99..0b858c41e32 100644
--- a/include/ppc_asm.tmpl
+++ b/include/ppc_asm.tmpl
@@ -45,40 +45,40 @@
/***************************************************************************
- * Register names
+ * Register names. The %r1 offers some error-checking in GNU as.
*/
-#define r0 0
-#define r1 1
-#define r2 2
-#define r3 3
-#define r4 4
-#define r5 5
-#define r6 6
-#define r7 7
-#define r8 8
-#define r9 9
-#define r10 10
-#define r11 11
-#define r12 12
-#define r13 13
-#define r14 14
-#define r15 15
-#define r16 16
-#define r17 17
-#define r18 18
-#define r19 19
-#define r20 20
-#define r21 21
-#define r22 22
-#define r23 23
-#define r24 24
-#define r25 25
-#define r26 26
-#define r27 27
-#define r28 28
-#define r29 29
-#define r30 30
-#define r31 31
+#define r0 %r0
+#define r1 %r1
+#define r2 %r2
+#define r3 %r3
+#define r4 %r4
+#define r5 %r5
+#define r6 %r6
+#define r7 %r7
+#define r8 %r8
+#define r9 %r9
+#define r10 %r10
+#define r11 %r11
+#define r12 %r12
+#define r13 %r13
+#define r14 %r14
+#define r15 %r15
+#define r16 %r16
+#define r17 %r17
+#define r18 %r18
+#define r19 %r19
+#define r20 %r20
+#define r21 %r21
+#define r22 %r22
+#define r23 %r23
+#define r24 %r24
+#define r25 %r25
+#define r26 %r26
+#define r27 %r27
+#define r28 %r28
+#define r29 %r29
+#define r30 %r30
+#define r31 %r31
#if defined(CONFIG_MPC8xx)
diff --git a/include/spl.h b/include/spl.h
index 269e36bb441..43b344dbc55 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -268,8 +268,8 @@ enum spl_sandbox_flags {
struct spl_image_info {
const char *name;
u8 os;
- uintptr_t load_addr;
- uintptr_t entry_point;
+ ulong load_addr;
+ ulong entry_point;
#if CONFIG_IS_ENABLED(LOAD_FIT) || CONFIG_IS_ENABLED(LOAD_FIT_FULL)
void *fdt_addr;
#endif
@@ -951,9 +951,9 @@ void __noreturn spl_invoke_atf(struct spl_image_info *spl_image);
*
* Return: bl31 params structure pointer
*/
-struct bl31_params *bl2_plat_get_bl31_params(uintptr_t bl32_entry,
- uintptr_t bl33_entry,
- uintptr_t fdt_addr);
+struct bl31_params *bl2_plat_get_bl31_params(ulong bl32_entry,
+ ulong bl33_entry,
+ ulong fdt_addr);
/**
* bl2_plat_get_bl31_params_default() - prepare params for bl31.
@@ -972,9 +972,9 @@ struct bl31_params *bl2_plat_get_bl31_params(uintptr_t bl32_entry,
*
* Return: bl31 params structure pointer
*/
-struct bl31_params *bl2_plat_get_bl31_params_default(uintptr_t bl32_entry,
- uintptr_t bl33_entry,
- uintptr_t fdt_addr);
+struct bl31_params *bl2_plat_get_bl31_params_default(ulong bl32_entry,
+ ulong bl33_entry,
+ ulong fdt_addr);
/**
* bl2_plat_get_bl31_params_v2() - return params for bl31
@@ -988,9 +988,9 @@ struct bl31_params *bl2_plat_get_bl31_params_default(uintptr_t bl32_entry,
*
* Return: bl31 params structure pointer
*/
-struct bl_params *bl2_plat_get_bl31_params_v2(uintptr_t bl32_entry,
- uintptr_t bl33_entry,
- uintptr_t fdt_addr);
+struct bl_params *bl2_plat_get_bl31_params_v2(ulong bl32_entry,
+ ulong bl33_entry,
+ ulong fdt_addr);
/**
* bl2_plat_get_bl31_params_v2_default() - prepare params for bl31.
@@ -1007,9 +1007,9 @@ struct bl_params *bl2_plat_get_bl31_params_v2(uintptr_t bl32_entry,
*
* Return: bl31 params structure pointer
*/
-struct bl_params *bl2_plat_get_bl31_params_v2_default(uintptr_t bl32_entry,
- uintptr_t bl33_entry,
- uintptr_t fdt_addr);
+struct bl_params *bl2_plat_get_bl31_params_v2_default(ulong bl32_entry,
+ ulong bl33_entry,
+ ulong fdt_addr);
/**
* spl_optee_entry - entry function for optee
*
diff --git a/include/trace.h b/include/trace.h
index 763d6d1255a..2bbaed9ba12 100644
--- a/include/trace.h
+++ b/include/trace.h
@@ -100,6 +100,8 @@ void trace_set_enabled(int enabled);
int trace_early_init(void);
+int trace_wipe(void);
+
/**
* Init the trace system
*
diff --git a/include/u-boot/crc.h b/include/u-boot/crc.h
index 5174bd7ac41..b2badaf6a97 100644
--- a/include/u-boot/crc.h
+++ b/include/u-boot/crc.h
@@ -25,6 +25,9 @@
*/
unsigned int crc8(unsigned int crc_start, const unsigned char *vptr, int len);
+void crc8_wd_buf(const unsigned char *input, unsigned int len,
+ unsigned char output[1], unsigned int chunk_sz);
+
/* lib/crc16.c - 16 bit CRC with polynomial x^16 + x^15 + x^2 + 1 */
uint16_t crc16(uint16_t crc, const unsigned char *buffer, size_t len);
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-05 17:19:10 +0000