diff options
Diffstat (limited to 'include')
40 files changed, 1510 insertions, 101 deletions
diff --git a/include/api.h b/include/api.h index 84d81dc8177..83412a7c87f 100644 --- a/include/api.h +++ b/include/api.h @@ -7,6 +7,14 @@ #ifndef __API_H #define __API_H -void api_init(void); +/** + * api_init() - Initialize API for external applications + * + * Initialize API for external (standalone) applications running on top of + * U-Boot. It is called during the generic post-relocation init sequence. + * + * Return: 0 if OK + */ +int api_init(void); #endif diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index efa09a1943e..19f70393b45 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -412,12 +412,12 @@ struct global_data { * @new_bloblist: relocated blob list information */ struct bloblist_hdr *new_bloblist; -# ifdef CONFIG_SPL +#endif +#if CONFIG_IS_ENABLED(HANDOFF) /** * @spl_handoff: SPL hand-off information */ struct spl_handoff *spl_handoff; -# endif #endif #if defined(CONFIG_TRANSLATION_OFFSET) /** diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h index c9862260a38..2627c2a6a54 100644 --- a/include/config_distro_bootcmd.h +++ b/include/config_distro_bootcmd.h @@ -123,14 +123,20 @@ #endif #endif - -#define BOOTENV_SHARED_EFI \ +#ifdef CONFIG_CMD_BOOTEFI_BOOTMGR +#define BOOTENV_EFI_BOOTMGR \ "boot_efi_bootmgr=" \ "if fdt addr ${fdt_addr_r}; then " \ "bootefi bootmgr ${fdt_addr_r};" \ "else " \ "bootefi bootmgr;" \ - "fi\0" \ + "fi\0" +#else +#define BOOTENV_EFI_BOOTMGR +#endif + +#define BOOTENV_SHARED_EFI \ + BOOTENV_EFI_BOOTMGR \ \ "boot_efi_binary=" \ "load ${devtype} ${devnum}:${distro_bootpart} " \ diff --git a/include/configs/ax25-ae350.h b/include/configs/ax25-ae350.h index b2606e794dd..bd9c371f835 100644 --- a/include/configs/ax25-ae350.h +++ b/include/configs/ax25-ae350.h @@ -17,6 +17,11 @@ #endif #endif +#define RISCV_MMODE_TIMERBASE 0xe6000000 +#define RISCV_MMODE_TIMER_FREQ 60000000 + +#define RISCV_SMODE_TIMER_FREQ 60000000 + /* * CPU and Board Configuration Options */ diff --git a/include/configs/evb_ast2600.h b/include/configs/evb_ast2600.h new file mode 100644 index 00000000000..e7975bf66d2 --- /dev/null +++ b/include/configs/evb_ast2600.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) Aspeed Technology Inc. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <configs/aspeed-common.h> + +#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE + +/* Memory Info */ +#define CONFIG_SYS_LOAD_ADDR 0x83000000 + +#endif /* __CONFIG_H */ diff --git a/include/configs/microchip_mpfs_icicle.h b/include/configs/microchip_mpfs_icicle.h index 8a7470545b9..24990370cf0 100644 --- a/include/configs/microchip_mpfs_icicle.h +++ b/include/configs/microchip_mpfs_icicle.h @@ -7,53 +7,34 @@ #ifndef __CONFIG_H #define __CONFIG_H -/* - * CPU and Board Configuration Options - */ +#include <linux/sizes.h> -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) -/* - * Print Buffer Size - */ -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) -/* - * max number of command args - */ -#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_MALLOC_LEN SZ_8M -/* - * Boot Argument Buffer Size - */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* - * Size of malloc() pool - * 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough - */ -#define CONFIG_SYS_MALLOC_LEN (512 << 10) +#define CONFIG_SYS_BOOTM_LEN SZ_64M -/* - * Physical Memory Map - */ -#define PHYS_SDRAM_0 0x80000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_0_SIZE 0x40000000 /* 1 GB */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 +#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 -/* Init Stack Pointer */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x200000) +/* Environment options */ -#define CONFIG_SYS_LOAD_ADDR 0x80000000 /* SDRAM */ +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(DHCP, dhcp, na) -/* - * memtest works on DRAM - */ +#include <config_distro_bootcmd.h> -/* When we use RAM as ENV */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootm_size=0x10000000\0" \ + "kernel_addr_r=0x84000000\0" \ + "fdt_addr_r=0x88000000\0" \ + "scriptaddr=0x88100000\0" \ + "pxefile_addr_r=0x88200000\0" \ + "ramdisk_addr_r=0x88300000\0" \ + BOOTENV #endif /* __CONFIG_H */ diff --git a/include/configs/presidio_asic.h b/include/configs/presidio_asic.h index 34235b5a00c..710731efd56 100644 --- a/include/configs/presidio_asic.h +++ b/include/configs/presidio_asic.h @@ -67,4 +67,13 @@ #define CONFIG_SYS_MAXARGS 64 #define CONFIG_EXTRA_ENV_SETTINGS "silent=y\0" +/* nand driver parameters */ +#ifdef CONFIG_TARGET_PRESIDIO_ASIC + #define CONFIG_SYS_NAND_ONFI_DETECTION + #define CONFIG_SYS_MAX_NAND_DEVICE 1 + #define CONFIG_SYS_NAND_MAX_CHIPS 1 + #define CONFIG_SYS_NAND_BASE CONFIG_SYS_FLASH_BASE + #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#endif + #endif /* __PRESIDIO_ASIC_H */ diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h index a2f33587c24..5291de83f8d 100644 --- a/include/configs/qemu-riscv.h +++ b/include/configs/qemu-riscv.h @@ -29,6 +29,11 @@ #define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 +#define RISCV_MMODE_TIMERBASE 0x2000000 +#define RISCV_MMODE_TIMER_FREQ 1000000 + +#define RISCV_SMODE_TIMER_FREQ 1000000 + /* Environment options */ #ifndef CONFIG_SPL_BUILD diff --git a/include/configs/sifive-fu540.h b/include/configs/sifive-fu540.h index c1c79db1474..0d69d1c5482 100644 --- a/include/configs/sifive-fu540.h +++ b/include/configs/sifive-fu540.h @@ -36,6 +36,11 @@ #define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 +#define RISCV_MMODE_TIMERBASE 0x2000000 +#define RISCV_MMODE_TIMER_FREQ 1000000 + +#define RISCV_SMODE_TIMER_FREQ 1000000 + /* Environment options */ #ifndef CONFIG_SPL_BUILD diff --git a/include/configs/sipeed-maix.h b/include/configs/sipeed-maix.h index 36ff522e4b6..08acb25075b 100644 --- a/include/configs/sipeed-maix.h +++ b/include/configs/sipeed-maix.h @@ -24,10 +24,13 @@ #ifndef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x80060000\0" \ - "fdt_addr_r=0x80028000\0" \ + "fdt_addr_r=0x80400000\0" \ "scriptaddr=0x80020000\0" \ "kernel_addr_r=0x80060000\0" \ - "fdtfile=kendryte/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" + "fdtfile=kendryte/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ + "k210_bootcmd=load mmc 0:1 $loadaddr /uImage && " \ + "load mmc 0:1 $fdt_addr_r /k210.dtb && " \ + "bootm $loadaddr - $fdt_addr_r\0" #endif #endif /* CONFIGS_SIPEED_MAIX_H */ diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 3d71759da4b..62b327cd6e5 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -22,8 +22,10 @@ #if defined(CONFIG_TARGET_SOCFPGA_GEN5) #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 #define CONFIG_SYS_INIT_RAM_SIZE SOCFPGA_PHYS_OCRAM_SIZE +#define CONFIG_SPL_PAD_TO 0x10000 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000 +#define CONFIG_SPL_PAD_TO 0x40000 /* SPL memory allocation configuration, this is for FAT implementation */ #ifndef CONFIG_SYS_SPL_MALLOC_SIZE #define CONFIG_SYS_SPL_MALLOC_SIZE 0x10000 diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index fb5e2e8aafa..fdcd7d3e9ae 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -40,9 +40,14 @@ */ #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000 #define CONFIG_SYS_INIT_RAM_SIZE 0x40000 +#ifdef CONFIG_SPL_BUILD #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR \ + CONFIG_SYS_INIT_RAM_SIZE \ - S10_HANDOFF_SIZE) +#else +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE \ + + 0x100000) +#endif #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_SP_ADDR) #define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024) @@ -78,12 +83,20 @@ unsigned int cm_get_qspi_controller_clk_hz(void); * CONFIG_BOOTARGS goes into the environment value "bootargs". * Do note the value will override also the chosen node in FDT blob. */ + +#ifdef CONFIG_FIT +#define CONFIG_BOOTFILE "kernel.itb" +#define CONFIG_BOOTCOMMAND "run fatscript; run mmcfitload;run linux_qspi_enable;" \ + "run mmcfitboot" +#else +#define CONFIG_BOOTFILE "Image" #define CONFIG_BOOTCOMMAND "run fatscript; run mmcload;run linux_qspi_enable;" \ "run mmcboot" +#endif #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ - "bootfile=Image\0" \ + "bootfile=" CONFIG_BOOTFILE "\0" \ "fdt_addr=8000000\0" \ "fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ "mmcroot=/dev/mmcblk0p2\0" \ @@ -93,6 +106,11 @@ unsigned int cm_get_qspi_controller_clk_hz(void); "mmcload=mmc rescan;" \ "load mmc 0:1 ${loadaddr} ${bootfile};" \ "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ + "mmcfitboot=setenv bootargs " CONFIG_BOOTARGS \ + " root=${mmcroot} rw rootwait;" \ + "bootm ${loadaddr}\0" \ + "mmcfitload=mmc rescan;" \ + "load mmc 0:1 ${loadaddr} ${bootfile}\0" \ "linux_qspi_enable=if sf probe; then " \ "echo Enabling QSPI at Linux DTB...;" \ "fdt addr ${fdt_addr}; fdt resize;" \ @@ -193,6 +211,10 @@ unsigned int cm_get_l4_sys_free_clk_hz(void); - CONFIG_SYS_SPL_MALLOC_SIZE) /* SPL SDMMC boot support */ +#ifdef CONFIG_SPL_LOAD_FIT +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.itb" +#else #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" +#endif #endif /* __CONFIG_SOCFPGA_SOC64_COMMON_H__ */ diff --git a/include/configs/stm32mp1.h b/include/configs/stm32mp1.h index 1aa7514ac79..863b652ca4f 100644 --- a/include/configs/stm32mp1.h +++ b/include/configs/stm32mp1.h @@ -69,7 +69,6 @@ /* Ethernet need */ #ifdef CONFIG_DWC_ETH_QOS -#define CONFIG_SYS_NONCACHED_MEMORY (1 * SZ_1M) /* 1M */ #define CONFIG_SERVERIP 192.168.1.1 #define CONFIG_BOOTP_SERVERIP #define CONFIG_SYS_AUTOLOAD "no" diff --git a/include/console.h b/include/console.h index 432f892b6cc..7e628c0cf83 100644 --- a/include/console.h +++ b/include/console.h @@ -8,6 +8,7 @@ #define __CONSOLE_H #include <stdbool.h> +#include <stdio_dev.h> #include <linux/errno.h> extern char console_buffer[]; @@ -15,6 +16,8 @@ extern char console_buffer[]; /* common/console.c */ int console_init_f(void); /* Before relocation; uses the serial stuff */ int console_init_r(void); /* After relocation; uses the console stuff */ +int console_start(int file, struct stdio_dev *sdev); /* Start a console device */ +void console_stop(int file, struct stdio_dev *sdev); /* Stop a console device */ int console_assign(int file, const char *devname); /* Assign the console */ int ctrlc(void); int had_ctrlc(void); /* have we had a Control-C since last clear? */ @@ -22,6 +25,18 @@ void clear_ctrlc(void); /* clear the Control-C condition */ int disable_ctrlc(int); /* 1 to disable, 0 to enable Control-C detect */ int confirm_yesno(void); /* 1 if input is "y", "Y", "yes" or "YES" */ +/** + * console_search_dev() - search for stdio device with given flags and name + * @flags: device flags as per input/output/system + * @name: device name + * + * Iterates over registered STDIO devices and match them with given @flags + * and @name. + * + * @return pointer to the &struct stdio_dev if found, or NULL otherwise + */ +struct stdio_dev *console_search_dev(int flags, const char *name); + #ifdef CONFIG_CONSOLE_RECORD /** * console_record_init() - set up the console recording buffers diff --git a/include/dm/uclass.h b/include/dm/uclass.h index b5f066dbf48..d95683740cb 100644 --- a/include/dm/uclass.h +++ b/include/dm/uclass.h @@ -377,6 +377,17 @@ int uclass_first_device_drvdata(enum uclass_id id, ulong driver_data, struct udevice **devp); /** + * uclass_probe_all() - Probe all devices based on an uclass ID + * + * This function probes all devices associated with a uclass by + * looking for its ID. + * + * @id: uclass ID to look up + * @return 0 if OK, other -ve on error + */ +int uclass_probe_all(enum uclass_id id); + +/** * uclass_id_foreach_dev() - Helper function to iteration through devices * * This creates a for() loop which works through the available devices in diff --git a/include/dt-bindings/clock/ast2600-clock.h b/include/dt-bindings/clock/ast2600-clock.h new file mode 100644 index 00000000000..36294a5140b --- /dev/null +++ b/include/dt-bindings/clock/ast2600-clock.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) ASPEED Technology Inc. + */ + +#define ASPEED_CLK_GATE_ECLK 0 +#define ASPEED_CLK_GATE_GCLK 1 +#define ASPEED_CLK_GATE_MCLK 2 +#define ASPEED_CLK_GATE_VCLK 3 +#define ASPEED_CLK_GATE_BCLK 4 +#define ASPEED_CLK_GATE_DCLK 5 +#define ASPEED_CLK_GATE_LCLK 6 +#define ASPEED_CLK_GATE_YCLK 7 +#define ASPEED_CLK_GATE_LHCCLK 8 +#define ASPEED_CLK_GATE_REFCLK 9 +#define ASPEED_CLK_GATE_ESPICLK 10 +#define ASPEED_CLK_GATE_UART1CLK 11 +#define ASPEED_CLK_GATE_UART2CLK 12 +#define ASPEED_CLK_GATE_UART3CLK 13 +#define ASPEED_CLK_GATE_UART4CLK 14 +#define ASPEED_CLK_GATE_UART5CLK 15 +#define ASPEED_CLK_GATE_UART6CLK 16 +#define ASPEED_CLK_GATE_UART7CLK 17 +#define ASPEED_CLK_GATE_UART8CLK 18 +#define ASPEED_CLK_GATE_UART9CLK 19 +#define ASPEED_CLK_GATE_UART10CLK 20 +#define ASPEED_CLK_GATE_UART11CLK 21 +#define ASPEED_CLK_GATE_UART12CLK 22 +#define ASPEED_CLK_GATE_UART13CLK 23 +#define ASPEED_CLK_GATE_MAC1CLK 24 +#define ASPEED_CLK_GATE_MAC2CLK 25 +#define ASPEED_CLK_GATE_MAC3CLK 26 +#define ASPEED_CLK_GATE_MAC4CLK 27 +#define ASPEED_CLK_GATE_RSACLK 28 +#define ASPEED_CLK_GATE_SDCLK 29 +#define ASPEED_CLK_GATE_SDEXTCLK 30 +#define ASPEED_CLK_GATE_EMMCCLK 31 +#define ASPEED_CLK_GATE_EMMCEXTCLK 32 +#define ASPEED_CLK_GATE_USBUHCICLK 33 +#define ASPEED_CLK_GATE_USBPORT1CLK 34 +#define ASPEED_CLK_GATE_USBPORT2CLK 35 +#define ASPEED_CLK_GATE_FSICLK 36 + +#define ASPEED_CLK_APLL 37 +#define ASPEED_CLK_EPLL 38 +#define ASPEED_CLK_DPLL 39 +#define ASPEED_CLK_HPLL 40 +#define ASPEED_CLK_AHB 41 +#define ASPEED_CLK_APB1 42 +#define ASPEED_CLK_APB2 43 +#define ASPEED_CLK_UART 44 +#define ASPEED_CLK_SDIO 45 +#define ASPEED_CLK_ECLK 46 +#define ASPEED_CLK_ECLK_MUX 47 +#define ASPEED_CLK_LHCLK 48 +#define ASPEED_CLK_MAC 49 +#define ASPEED_CLK_BCLK 50 +#define ASPEED_CLK_MPLL 51 +#define ASPEED_CLK_24M 52 +#define ASPEED_CLK_EMMC 53 +#define ASPEED_CLK_UARTX 54 +#define ASPEED_CLK_HUARTX 55 diff --git a/include/dt-bindings/clock/microchip-mpfs-clock.h b/include/dt-bindings/clock/microchip-mpfs-clock.h new file mode 100644 index 00000000000..55fe64693f6 --- /dev/null +++ b/include/dt-bindings/clock/microchip-mpfs-clock.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (C) 2020 Microchip Technology Inc. + * Padmarao Begari <padmarao.begari@microchip.com> + */ + +#ifndef _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_ +#define _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_ + +#define CLK_CPU 0 +#define CLK_AXI 1 +#define CLK_AHB 2 + +#define CLK_ENVM 3 +#define CLK_MAC0 4 +#define CLK_MAC1 5 +#define CLK_MMC 6 +#define CLK_TIMER 7 +#define CLK_MMUART0 8 +#define CLK_MMUART1 9 +#define CLK_MMUART2 10 +#define CLK_MMUART3 11 +#define CLK_MMUART4 12 +#define CLK_SPI0 13 +#define CLK_SPI1 14 +#define CLK_I2C0 15 +#define CLK_I2C1 16 +#define CLK_CAN0 17 +#define CLK_CAN1 18 +#define CLK_USB 19 +#define CLK_RESERVED 20 +#define CLK_RTC 21 +#define CLK_QSPI 22 +#define CLK_GPIO0 23 +#define CLK_GPIO1 24 +#define CLK_GPIO2 25 +#define CLK_DDRC 26 +#define CLK_FIC0 27 +#define CLK_FIC1 28 +#define CLK_FIC2 29 +#define CLK_FIC3 30 +#define CLK_ATHENA 31 +#define CLK_CFM 32 + +#endif /* _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_ */ diff --git a/include/dt-bindings/clock/mt8183-clk.h b/include/dt-bindings/clock/mt8183-clk.h new file mode 100644 index 00000000000..f7e6367ce84 --- /dev/null +++ b/include/dt-bindings/clock/mt8183-clk.h @@ -0,0 +1,329 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020 MediaTek Inc. + * Author: Weiyi Lu <weiyi.lu@mediatek.com> + */ + +#ifndef _DT_BINDINGS_CLK_MT8183_H +#define _DT_BINDINGS_CLK_MT8183_H + +/* APMIXED */ +#define CLK_APMIXED_ARMPLL_LL 0 +#define CLK_APMIXED_ARMPLL_L 1 +#define CLK_APMIXED_CCIPLL 2 +#define CLK_APMIXED_MAINPLL 3 +#define CLK_APMIXED_UNIV2PLL 4 +#define CLK_APMIXED_MSDCPLL 5 +#define CLK_APMIXED_MMPLL 6 +#define CLK_APMIXED_MFGPLL 7 +#define CLK_APMIXED_TVDPLL 8 +#define CLK_APMIXED_APLL1 9 +#define CLK_APMIXED_APLL2 10 +#define CLK_APMIXED_SSUSB_26M 11 +#define CLK_APMIXED_APPLL_26M 12 +#define CLK_APMIXED_MIPIC0_26M 13 +#define CLK_APMIXED_MDPLLGP_26M 14 +#define CLK_APMIXED_MMSYS_26M 15 +#define CLK_APMIXED_UFS_26M 16 +#define CLK_APMIXED_MIPIC1_26M 17 +#define CLK_APMIXED_MEMPLL_26M 18 +#define CLK_APMIXED_CLKSQ_LVPLL_26M 19 +#define CLK_APMIXED_MIPID0_26M 20 +#define CLK_APMIXED_MIPID1_26M 21 +#define CLK_APMIXED_NR_CLK 22 + +/* TOPCKGEN */ +#define CLK_TOP_CLK26M 0 +#define CLK_TOP_ULPOSC 1 +#define CLK_TOP_UNIVP_192M 2 +#define CLK_TOP_CLK13M 3 +#define CLK_TOP_F26M_CK_D2 4 +#define CLK_TOP_SYSPLL_CK 5 +#define CLK_TOP_SYSPLL_D2 6 +#define CLK_TOP_SYSPLL_D3 7 +#define CLK_TOP_SYSPLL_D5 8 +#define CLK_TOP_SYSPLL_D7 9 +#define CLK_TOP_SYSPLL_D2_D2 10 +#define CLK_TOP_SYSPLL_D2_D4 11 +#define CLK_TOP_SYSPLL_D2_D8 12 +#define CLK_TOP_SYSPLL_D2_D16 13 +#define CLK_TOP_SYSPLL_D3_D2 14 +#define CLK_TOP_SYSPLL_D3_D4 15 +#define CLK_TOP_SYSPLL_D3_D8 16 +#define CLK_TOP_SYSPLL_D5_D2 17 +#define CLK_TOP_SYSPLL_D5_D4 18 +#define CLK_TOP_SYSPLL_D7_D2 19 +#define CLK_TOP_SYSPLL_D7_D4 20 +#define CLK_TOP_UNIVPLL_CK 21 +#define CLK_TOP_UNIVPLL_D2 22 +#define CLK_TOP_UNIVPLL_D3 23 +#define CLK_TOP_UNIVPLL_D5 24 +#define CLK_TOP_UNIVPLL_D7 25 +#define CLK_TOP_UNIVPLL_D2_D2 26 +#define CLK_TOP_UNIVPLL_D2_D4 27 +#define CLK_TOP_UNIVPLL_D2_D8 28 +#define CLK_TOP_UNIVPLL_D3_D2 29 +#define CLK_TOP_UNIVPLL_D3_D4 30 +#define CLK_TOP_UNIVPLL_D3_D8 31 +#define CLK_TOP_UNIVPLL_D5_D2 32 +#define CLK_TOP_UNIVPLL_D5_D4 33 +#define CLK_TOP_UNIVPLL_D5_D8 34 +#define CLK_TOP_UNIVP_192M_CK 35 +#define CLK_TOP_UNIVP_192M_D2 36 +#define CLK_TOP_UNIVP_192M_D4 37 +#define CLK_TOP_UNIVP_192M_D8 38 +#define CLK_TOP_UNIVP_192M_D16 39 +#define CLK_TOP_UNIVP_192M_D32 40 +#define CLK_TOP_APLL1_CK 41 +#define CLK_TOP_APLL1_D2 42 +#define CLK_TOP_APLL1_D4 43 +#define CLK_TOP_APLL1_D8 44 +#define CLK_TOP_APLL2_CK 45 +#define CLK_TOP_APLL2_D2 46 +#define CLK_TOP_APLL2_D4 47 +#define CLK_TOP_APLL2_D8 48 +#define CLK_TOP_TVDPLL_CK 49 +#define CLK_TOP_TVDPLL_D2 50 +#define CLK_TOP_TVDPLL_D4 51 +#define CLK_TOP_TVDPLL_D8 52 +#define CLK_TOP_TVDPLL_D16 53 +#define CLK_TOP_MMPLL_CK 54 +#define CLK_TOP_MMPLL_D4 55 +#define CLK_TOP_MMPLL_D4_D2 56 +#define CLK_TOP_MMPLL_D4_D4 57 +#define CLK_TOP_MMPLL_D5 58 +#define CLK_TOP_MMPLL_D5_D2 59 +#define CLK_TOP_MMPLL_D5_D4 60 +#define CLK_TOP_MMPLL_D6 61 +#define CLK_TOP_MMPLL_D7 62 +#define CLK_TOP_MFGPLL_CK 63 +#define CLK_TOP_MSDCPLL_CK 64 +#define CLK_TOP_MSDCPLL_D2 65 +#define CLK_TOP_MSDCPLL_D4 66 +#define CLK_TOP_MSDCPLL_D8 67 +#define CLK_TOP_MSDCPLL_D16 68 +#define CLK_TOP_AD_OSC_CK 69 +#define CLK_TOP_OSC_D2 70 +#define CLK_TOP_OSC_D4 71 +#define CLK_TOP_OSC_D8 72 +#define CLK_TOP_OSC_D16 73 +#define CLK_TOP_UNIVPLL 74 +#define CLK_TOP_UNIVPLL_D3_D16 75 +#define CLK_TOP_APLL12_DIV0 76 +#define CLK_TOP_APLL12_DIV1 77 +#define CLK_TOP_APLL12_DIV2 78 +#define CLK_TOP_APLL12_DIV3 79 +#define CLK_TOP_APLL12_DIV4 80 +#define CLK_TOP_APLL12_DIVB 81 +#define CLK_TOP_ARMPLL_DIV_PLL1 82 +#define CLK_TOP_ARMPLL_DIV_PLL2 83 +#define CLK_TOP_MUX_AXI 84 +#define CLK_TOP_MUX_MM 85 +#define CLK_TOP_MUX_IMG 86 +#define CLK_TOP_MUX_CAM 87 +#define CLK_TOP_MUX_DSP 88 +#define CLK_TOP_MUX_DSP1 89 +#define CLK_TOP_MUX_DSP2 90 +#define CLK_TOP_MUX_IPU_IF 91 +#define CLK_TOP_MUX_MFG 92 +#define CLK_TOP_MUX_F52M_MFG 93 +#define CLK_TOP_MUX_CAMTG 94 +#define CLK_TOP_MUX_CAMTG2 95 +#define CLK_TOP_MUX_CAMTG3 96 +#define CLK_TOP_MUX_CAMTG4 97 +#define CLK_TOP_MUX_UART 98 +#define CLK_TOP_MUX_SPI 99 +#define CLK_TOP_MUX_MSDC50_0_HCLK 100 +#define CLK_TOP_MUX_MSDC50_0 101 +#define CLK_TOP_MUX_MSDC30_1 102 +#define CLK_TOP_MUX_MSDC30_2 103 +#define CLK_TOP_MUX_AUDIO 104 +#define CLK_TOP_MUX_AUD_INTBUS 105 +#define CLK_TOP_MUX_PMICSPI 106 +#define CLK_TOP_MUX_FPWRAP_ULPOSC 107 +#define CLK_TOP_MUX_ATB 108 +#define CLK_TOP_MUX_SSPM 109 +#define CLK_TOP_MUX_DPI0 110 +#define CLK_TOP_MUX_SCAM 111 +#define CLK_TOP_MUX_DISP_PWM 112 +#define CLK_TOP_MUX_USB_TOP 113 +#define CLK_TOP_MUX_SSUSB_TOP_XHCI 114 +#define CLK_TOP_MUX_SPM 115 +#define CLK_TOP_MUX_I2C 116 +#define CLK_TOP_MUX_SCP 117 +#define CLK_TOP_MUX_SENINF 118 +#define CLK_TOP_MUX_DXCC 119 +#define CLK_TOP_MUX_AUD_ENG1 120 +#define CLK_TOP_MUX_AUD_ENG2 121 +#define CLK_TOP_MUX_FAES_UFSFDE 122 +#define CLK_TOP_MUX_FUFS 123 +#define CLK_TOP_MUX_AUD_1 124 +#define CLK_TOP_MUX_AUD_2 125 +#define CLK_TOP_MUX_APLL_I2S0 126 +#define CLK_TOP_MUX_APLL_I2S1 127 +#define CLK_TOP_MUX_APLL_I2S2 128 +#define CLK_TOP_MUX_APLL_I2S3 129 +#define CLK_TOP_MUX_APLL_I2S4 130 +#define CLK_TOP_MUX_APLL_I2S5 131 +#define CLK_TOP_NR_CLK 132 + +/* INFRACFG_AO */ +#define CLK_INFRA_PMIC_TMR 0 +#define CLK_INFRA_PMIC_AP 1 +#define CLK_INFRA_PMIC_MD 2 +#define CLK_INFRA_PMIC_CONN 3 +#define CLK_INFRA_SCPSYS 4 +#define CLK_INFRA_SEJ 5 +#define CLK_INFRA_APXGPT 6 +#define CLK_INFRA_ICUSB 7 +#define CLK_INFRA_GCE 8 +#define CLK_INFRA_THERM 9 +#define CLK_INFRA_I2C0 10 +#define CLK_INFRA_I2C1 11 +#define CLK_INFRA_I2C2 12 +#define CLK_INFRA_I2C3 13 +#define CLK_INFRA_PWM_HCLK 14 +#define CLK_INFRA_PWM1 15 +#define CLK_INFRA_PWM2 16 +#define CLK_INFRA_PWM3 17 +#define CLK_INFRA_PWM4 18 +#define CLK_INFRA_PWM 19 +#define CLK_INFRA_UART0 20 +#define CLK_INFRA_UART1 21 +#define CLK_INFRA_UART2 22 +#define CLK_INFRA_UART3 23 +#define CLK_INFRA_GCE_26M 24 +#define CLK_INFRA_CQ_DMA_FPC 25 +#define CLK_INFRA_BTIF 26 +#define CLK_INFRA_SPI0 27 +#define CLK_INFRA_MSDC0 28 +#define CLK_INFRA_MSDC1 29 +#define CLK_INFRA_MSDC2 30 +#define CLK_INFRA_MSDC0_SCK 31 +#define CLK_INFRA_DVFSRC 32 +#define CLK_INFRA_GCPU 33 +#define CLK_INFRA_TRNG 34 +#define CLK_INFRA_AUXADC 35 +#define CLK_INFRA_CPUM 36 +#define CLK_INFRA_CCIF1_AP 37 +#define CLK_INFRA_CCIF1_MD 38 +#define CLK_INFRA_AUXADC_MD 39 +#define CLK_INFRA_MSDC1_SCK 40 +#define CLK_INFRA_MSDC2_SCK 41 +#define CLK_INFRA_AP_DMA 42 +#define CLK_INFRA_XIU 43 +#define CLK_INFRA_DEVICE_APC 44 +#define CLK_INFRA_CCIF_AP 45 +#define CLK_INFRA_DEBUGSYS 46 +#define CLK_INFRA_AUDIO 47 +#define CLK_INFRA_CCIF_MD 48 +#define CLK_INFRA_DXCC_SEC_CORE 49 +#define CLK_INFRA_DXCC_AO 50 +#define CLK_INFRA_DRAMC_F26M 51 +#define CLK_INFRA_IRTX 52 +#define CLK_INFRA_DISP_PWM 53 +#define CLK_INFRA_CLDMA_BCLK 54 +#define CLK_INFRA_AUDIO_26M_BCLK 55 +#define CLK_INFRA_SPI1 56 +#define CLK_INFRA_I2C4 57 +#define CLK_INFRA_MODEM_TEMP_SHARE 58 +#define CLK_INFRA_SPI2 59 +#define CLK_INFRA_SPI3 60 +#define CLK_INFRA_UNIPRO_SCK 61 +#define CLK_INFRA_UNIPRO_TICK 62 +#define CLK_INFRA_UFS_MP_SAP_BCLK 63 +#define CLK_INFRA_MD32_BCLK 64 +#define CLK_INFRA_SSPM 65 +#define CLK_INFRA_UNIPRO_MBIST 66 +#define CLK_INFRA_SSPM_BUS_HCLK 67 +#define CLK_INFRA_I2C5 68 +#define CLK_INFRA_I2C5_ARBITER 69 +#define CLK_INFRA_I2C5_IMM 70 +#define CLK_INFRA_I2C1_ARBITER 71 +#define CLK_INFRA_I2C1_IMM 72 +#define CLK_INFRA_I2C2_ARBITER 73 +#define CLK_INFRA_I2C2_IMM 74 +#define CLK_INFRA_SPI4 75 +#define CLK_INFRA_SPI5 76 +#define CLK_INFRA_CQ_DMA 77 +#define CLK_INFRA_UFS 78 +#define CLK_INFRA_AES_UFSFDE 79 +#define CLK_INFRA_UFS_TICK 80 +#define CLK_INFRA_MSDC0_SELF 81 +#define CLK_INFRA_MSDC1_SELF 82 +#define CLK_INFRA_MSDC2_SELF 83 +#define CLK_INFRA_SSPM_26M_SELF 84 +#define CLK_INFRA_SSPM_32K_SELF 85 +#define CLK_INFRA_UFS_AXI 86 +#define CLK_INFRA_I2C6 87 +#define CLK_INFRA_AP_MSDC0 88 +#define CLK_INFRA_MD_MSDC0 89 +#define CLK_INFRA_USB 90 +#define CLK_INFRA_DEVMPU_BCLK 91 +#define CLK_INFRA_CCIF2_AP 92 +#define CLK_INFRA_CCIF2_MD 93 +#define CLK_INFRA_CCIF3_AP 94 +#define CLK_INFRA_CCIF3_MD 95 +#define CLK_INFRA_SEJ_F13M 96 +#define CLK_INFRA_AES_BCLK 97 +#define CLK_INFRA_I2C7 98 +#define CLK_INFRA_I2C8 99 +#define CLK_INFRA_FBIST2FPC 100 +#define CLK_INFRA_NR_CLK 101 + +/* MMSYS_CONFIG */ +#define CLK_MM_SMI_COMMON 0 +#define CLK_MM_SMI_LARB0 1 +#define CLK_MM_SMI_LARB1 2 +#define CLK_MM_GALS_COMM0 3 +#define CLK_MM_GALS_COMM1 4 +#define CLK_MM_GALS_CCU2MM 5 +#define CLK_MM_GALS_IPU12MM 6 +#define CLK_MM_GALS_IMG2MM 7 +#define CLK_MM_GALS_CAM2MM 8 +#define CLK_MM_GALS_IPU2MM 9 +#define CLK_MM_MDP_DL_TXCK 10 +#define CLK_MM_IPU_DL_TXCK 11 +#define CLK_MM_MDP_RDMA0 12 +#define CLK_MM_MDP_RDMA1 13 +#define CLK_MM_MDP_RSZ0 14 +#define CLK_MM_MDP_RSZ1 15 +#define CLK_MM_MDP_TDSHP 16 +#define CLK_MM_MDP_WROT0 17 +#define CLK_MM_FAKE_ENG 18 +#define CLK_MM_DISP_OVL0 19 +#define CLK_MM_DISP_OVL0_2L 20 +#define CLK_MM_DISP_OVL1_2L 21 +#define CLK_MM_DISP_RDMA0 22 +#define CLK_MM_DISP_RDMA1 23 +#define CLK_MM_DISP_WDMA0 24 +#define CLK_MM_DISP_COLOR0 25 +#define CLK_MM_DISP_CCORR0 26 +#define CLK_MM_DISP_AAL0 27 +#define CLK_MM_DISP_GAMMA0 28 +#define CLK_MM_DISP_DITHER0 29 +#define CLK_MM_DISP_SPLIT 30 +#define CLK_MM_DSI0_MM 31 +#define CLK_MM_DSI0_IF 32 +#define CLK_MM_DPI_MM 33 +#define CLK_MM_DPI_IF 34 +#define CLK_MM_FAKE_ENG2 35 +#define CLK_MM_MDP_DL_RX 36 +#define CLK_MM_IPU_DL_RX 37 +#define CLK_MM_26M 38 +#define CLK_MM_MMSYS_R2Y 39 +#define CLK_MM_DISP_RSZ 40 +#define CLK_MM_MDP_WDMA0 41 +#define CLK_MM_MDP_AAL 42 +#define CLK_MM_MDP_CCORR 43 +#define CLK_MM_DBI_MM 44 +#define CLK_MM_DBI_IF 45 +#define CLK_MM_NR_CLK 46 + +/* MCUCFG */ +#define CLK_MCU_MP0_SEL 0 +#define CLK_MCU_MP2_SEL 1 +#define CLK_MCU_BUS_SEL 2 +#define CLK_MCU_NR_CLK 3 + +#endif /* _DT_BINDINGS_CLK_MT8183_H */ diff --git a/include/dt-bindings/power/meson-axg-power.h b/include/dt-bindings/power/meson-axg-power.h new file mode 100644 index 00000000000..e5243884b24 --- /dev/null +++ b/include/dt-bindings/power/meson-axg-power.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* + * Copyright (c) 2020 BayLibre, SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +#ifndef _DT_BINDINGS_MESON_AXG_POWER_H +#define _DT_BINDINGS_MESON_AXG_POWER_H + +#define PWRC_AXG_VPU_ID 0 +#define PWRC_AXG_ETHERNET_MEM_ID 1 +#define PWRC_AXG_AUDIO_ID 2 + +#endif diff --git a/include/dt-bindings/power/meson-gxbb-power.h b/include/dt-bindings/power/meson-gxbb-power.h new file mode 100644 index 00000000000..1262dac696c --- /dev/null +++ b/include/dt-bindings/power/meson-gxbb-power.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* + * Copyright (c) 2019 BayLibre, SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +#ifndef _DT_BINDINGS_MESON_GXBB_POWER_H +#define _DT_BINDINGS_MESON_GXBB_POWER_H + +#define PWRC_GXBB_VPU_ID 0 +#define PWRC_GXBB_ETHERNET_MEM_ID 1 + +#endif diff --git a/include/dt-bindings/reset/ast2600-reset.h b/include/dt-bindings/reset/ast2600-reset.h new file mode 100644 index 00000000000..b6d0f79917a --- /dev/null +++ b/include/dt-bindings/reset/ast2600-reset.h @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) ASPEED Technology Inc. + */ + +#ifndef _ABI_MACH_ASPEED_AST2600_RESET_H_ +#define _ABI_MACH_ASPEED_AST2600_RESET_H_ + +#define ASPEED_RESET_FSI (59) +#define ASPEED_RESET_RESERVED58 (58) +#define ASPEED_RESET_RESERVED57 (57) +#define ASPEED_RESET_SD (56) +#define ASPEED_RESET_ADC (55) +#define ASPEED_RESET_JTAG_MASTER2 (54) +#define ASPEED_RESET_MAC4 (53) +#define ASPEED_RESET_MAC3 (52) +#define ASPEED_RESET_RESERVE51 (51) +#define ASPEED_RESET_RESERVE50 (50) +#define ASPEED_RESET_RESERVE49 (49) +#define ASPEED_RESET_RESERVE48 (48) +#define ASPEED_RESET_RESERVE47 (47) +#define ASPEED_RESET_RESERVE46 (46) +#define ASPEED_RESET_I3C5 (45) +#define ASPEED_RESET_I3C4 (44) +#define ASPEED_RESET_I3C3 (43) +#define ASPEED_RESET_I3C2 (42) +#define ASPEED_RESET_I3C1 (41) +#define ASPEED_RESET_I3C0 (40) +#define ASPEED_RESET_I3C_DMA (39) +#define ASPEED_RESET_RESERVED38 (38) +#define ASPEED_RESET_PWM (37) +#define ASPEED_RESET_PECI (36) +#define ASPEED_RESET_MII (35) +#define ASPEED_RESET_I2C (34) +#define ASPEED_RESET_RESERVED33 (33) +#define ASPEED_RESET_LPC_ESPI (32) +#define ASPEED_RESET_H2X (31) +#define ASPEED_RESET_GP_MCU (30) +#define ASPEED_RESET_DP_MCU (29) +#define ASPEED_RESET_DP (28) +#define ASPEED_RESET_RC_XDMA (27) +#define ASPEED_RESET_GRAPHICS (26) +#define ASPEED_RESET_DEV_XDMA (25) +#define ASPEED_RESET_DEV_MCTP (24) +#define ASPEED_RESET_RC_MCTP (23) +#define ASPEED_RESET_JTAG_MASTER (22) +#define ASPEED_RESET_PCIE_DEV_OE (21) +#define ASPEED_RESET_PCIE_DEV_O (20) +#define ASPEED_RESET_PCIE_RC_OE (19) +#define ASPEED_RESET_PCIE_RC_O (18) +#define ASPEED_RESET_RESERVED17 (17) +#define ASPEED_RESET_EMMC (16) +#define ASPEED_RESET_UHCI (15) +#define ASPEED_RESET_EHCI_P1 (14) +#define ASPEED_RESET_CRT (13) +#define ASPEED_RESET_MAC2 (12) +#define ASPEED_RESET_MAC1 (11) +#define ASPEED_RESET_RESERVED10 (10) +#define ASPEED_RESET_RVAS (9) +#define ASPEED_RESET_PCI_VGA (8) +#define ASPEED_RESET_2D (7) +#define ASPEED_RESET_VIDEO (6) +#define ASPEED_RESET_PCI_DP (5) +#define ASPEED_RESET_HACE (4) +#define ASPEED_RESET_EHCI_P2 (3) +#define ASPEED_RESET_RESERVED2 (2) +#define ASPEED_RESET_AHB (1) +#define ASPEED_RESET_SDRAM (0) + +#endif /* _ABI_MACH_ASPEED_AST2600_RESET_H_ */ diff --git a/include/dwmmc.h b/include/dwmmc.h index 51ab74ead35..5fc8ed8395f 100644 --- a/include/dwmmc.h +++ b/include/dwmmc.h @@ -174,7 +174,7 @@ struct dwmci_host { struct mmc *mmc; void *priv; - void (*clksel)(struct dwmci_host *host); + int (*clksel)(struct dwmci_host *host); void (*board_init)(struct dwmci_host *host); /** diff --git a/include/efi.h b/include/efi.h index 5695273ce9a..503fbf060bf 100644 --- a/include/efi.h +++ b/include/efi.h @@ -20,6 +20,11 @@ #include <linux/string.h> #include <linux/types.h> +/* Type INTN in UEFI specification */ +#define efi_intn_t ssize_t +/* Type UINTN in UEFI specification*/ +#define efi_uintn_t size_t + /* * EFI on x86_64 uses the Microsoft ABI which is not the default for GCC. * diff --git a/include/efi_api.h b/include/efi_api.h index ecb43a06070..48e48a6263b 100644 --- a/include/efi_api.h +++ b/include/efi_api.h @@ -34,8 +34,6 @@ enum efi_timer_delay { EFI_TIMER_RELATIVE = 2 }; -#define efi_intn_t ssize_t -#define efi_uintn_t size_t typedef void *efi_hii_handle_t; typedef u16 *efi_string_t; typedef u16 efi_string_id_t; @@ -703,10 +701,10 @@ struct efi_simple_text_output_protocol { char extended_verification); efi_status_t (EFIAPI *output_string)( struct efi_simple_text_output_protocol *this, - const efi_string_t str); + const u16 *str); efi_status_t (EFIAPI *test_string)( struct efi_simple_text_output_protocol *this, - const efi_string_t str); + const u16 *str); efi_status_t(EFIAPI *query_mode)( struct efi_simple_text_output_protocol *this, unsigned long mode_number, unsigned long *columns, @@ -1589,35 +1587,35 @@ struct efi_file_io_token { struct efi_file_handle { u64 rev; - efi_status_t (EFIAPI *open)(struct efi_file_handle *file, + efi_status_t (EFIAPI *open)(struct efi_file_handle *this, struct efi_file_handle **new_handle, u16 *file_name, u64 open_mode, u64 attributes); - efi_status_t (EFIAPI *close)(struct efi_file_handle *file); - efi_status_t (EFIAPI *delete)(struct efi_file_handle *file); - efi_status_t (EFIAPI *read)(struct efi_file_handle *file, + efi_status_t (EFIAPI *close)(struct efi_file_handle *this); + efi_status_t (EFIAPI *delete)(struct efi_file_handle *this); + efi_status_t (EFIAPI *read)(struct efi_file_handle *this, efi_uintn_t *buffer_size, void *buffer); - efi_status_t (EFIAPI *write)(struct efi_file_handle *file, + efi_status_t (EFIAPI *write)(struct efi_file_handle *this, efi_uintn_t *buffer_size, void *buffer); - efi_status_t (EFIAPI *getpos)(struct efi_file_handle *file, + efi_status_t (EFIAPI *getpos)(struct efi_file_handle *this, u64 *pos); - efi_status_t (EFIAPI *setpos)(struct efi_file_handle *file, + efi_status_t (EFIAPI *setpos)(struct efi_file_handle *this, u64 pos); - efi_status_t (EFIAPI *getinfo)(struct efi_file_handle *file, + efi_status_t (EFIAPI *getinfo)(struct efi_file_handle *this, const efi_guid_t *info_type, efi_uintn_t *buffer_size, void *buffer); - efi_status_t (EFIAPI *setinfo)(struct efi_file_handle *file, + efi_status_t (EFIAPI *setinfo)(struct efi_file_handle *this, const efi_guid_t *info_type, efi_uintn_t buffer_size, void *buffer); - efi_status_t (EFIAPI *flush)(struct efi_file_handle *file); - efi_status_t (EFIAPI *open_ex)(struct efi_file_handle *file, + efi_status_t (EFIAPI *flush)(struct efi_file_handle *this); + efi_status_t (EFIAPI *open_ex)(struct efi_file_handle *this, struct efi_file_handle **new_handle, u16 *file_name, u64 open_mode, u64 attributes, struct efi_file_io_token *token); - efi_status_t (EFIAPI *read_ex)(struct efi_file_handle *file, + efi_status_t (EFIAPI *read_ex)(struct efi_file_handle *this, struct efi_file_io_token *token); - efi_status_t (EFIAPI *write_ex)(struct efi_file_handle *file, + efi_status_t (EFIAPI *write_ex)(struct efi_file_handle *this, struct efi_file_io_token *token); - efi_status_t (EFIAPI *flush_ex)(struct efi_file_handle *file, + efi_status_t (EFIAPI *flush_ex)(struct efi_file_handle *this, struct efi_file_io_token *token); }; @@ -1695,10 +1693,6 @@ struct efi_driver_binding_protocol { efi_handle_t driver_binding_handle; }; -/* Deprecated version of the Unicode collation protocol */ -#define EFI_UNICODE_COLLATION_PROTOCOL_GUID \ - EFI_GUID(0x1d85cd7f, 0xf43d, 0x11d2, \ - 0x9a, 0x0c, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d) /* Current version of the Unicode collation protocol */ #define EFI_UNICODE_COLLATION_PROTOCOL2_GUID \ EFI_GUID(0xa4c751fc, 0x23ae, 0x4c3e, \ diff --git a/include/efi_dt_fixup.h b/include/efi_dt_fixup.h new file mode 100644 index 00000000000..9066e8dd8e1 --- /dev/null +++ b/include/efi_dt_fixup.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * EFI_DT_FIXUP_PROTOCOL + * + * Copyright (c) 2020 Heinrich Schuchardt + */ + +#include <efi_api.h> + +#define EFI_DT_FIXUP_PROTOCOL_GUID \ + EFI_GUID(0xe617d64c, 0xfe08, 0x46da, 0xf4, 0xdc, \ + 0xbb, 0xd5, 0x87, 0x0c, 0x73, 0x00) + +#define EFI_DT_FIXUP_PROTOCOL_REVISION 0x00010000 + +/* Add nodes and update properties */ +#define EFI_DT_APPLY_FIXUPS 0x00000001 +/* + * Reserve memory according to the /reserved-memory node + * and the memory reservation block + */ +#define EFI_DT_RESERVE_MEMORY 0x00000002 +/* Install the device-tree as configuration table */ +#define EFI_DT_INSTALL_TABLE 0x00000004 + +#define EFI_DT_ALL (EFI_DT_APPLY_FIXUPS | \ + EFI_DT_RESERVE_MEMORY | \ + EFI_DT_INSTALL_TABLE) + +struct efi_dt_fixup_protocol { + u64 revision; + efi_status_t (EFIAPI *fixup) (struct efi_dt_fixup_protocol *this, + void *dtb, + efi_uintn_t *buffer_size, + u32 flags); +}; + +extern struct efi_dt_fixup_protocol efi_dt_fixup_prot; +extern const efi_guid_t efi_guid_dt_fixup_protocol; diff --git a/include/efi_loader.h b/include/efi_loader.h index 4719fa93f06..f470bbd636f 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -147,9 +147,6 @@ extern const struct efi_device_path_to_text_protocol efi_device_path_to_text; /* implementation of the EFI_DEVICE_PATH_UTILITIES_PROTOCOL */ extern const struct efi_device_path_utilities_protocol efi_device_path_utilities; -/* deprecated version of the EFI_UNICODE_COLLATION_PROTOCOL */ -extern const struct efi_unicode_collation_protocol - efi_unicode_collation_protocol; /* current version of the EFI_UNICODE_COLLATION_PROTOCOL */ extern const struct efi_unicode_collation_protocol efi_unicode_collation_protocol2; @@ -411,6 +408,8 @@ void efi_runtime_detach(void); /* efi_convert_pointer() - convert pointer to virtual address */ efi_status_t EFIAPI efi_convert_pointer(efi_uintn_t debug_disposition, void **address); +/* Carve out DT reserved memory ranges */ +void efi_carve_out_dt_rsv(void *fdt); /* Called by bootefi to make console interface available */ efi_status_t efi_console_register(void); /* Called by bootefi to make all disk storage accessible as EFI objects */ @@ -460,6 +459,8 @@ efi_status_t efi_set_watchdog(unsigned long timeout); /* Called from places to check whether a timer expired */ void efi_timer_check(void); +/* Check if a buffer contains a PE-COFF image */ +efi_status_t efi_check_pe(void *buffer, size_t size, void **nt_header); /* PE loader implementation */ efi_status_t efi_load_pe(struct efi_loaded_image_obj *handle, void *efi, size_t efi_size, @@ -472,7 +473,8 @@ void efi_restore_gd(void); /* Call this to relocate the runtime section to an address space */ void efi_runtime_relocate(ulong offset, struct efi_mem_desc *map); /* Call this to set the current device name */ -void efi_set_bootdev(const char *dev, const char *devnr, const char *path); +void efi_set_bootdev(const char *dev, const char *devnr, const char *path, + void *buffer, size_t buffer_size); /* Add a new object to the object list. */ void efi_add_handle(efi_handle_t obj); /* Create handle */ @@ -559,7 +561,7 @@ struct efi_file_handle *efi_file_from_path(struct efi_device_path *fp); * @size: size in bytes * Return: size in pages */ -#define efi_size_in_pages(size) ((size + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT) +#define efi_size_in_pages(size) (((size) + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT) /* Generic EFI memory allocator, call this to get memory */ void *efi_alloc(uint64_t len, int memory_type); /* More specific EFI memory allocator, called by EFI payloads */ @@ -871,7 +873,8 @@ static inline efi_status_t efi_add_runtime_mmio(void *mmio_ptr, u64 len) /* No loader configured, stub out EFI_ENTRY */ static inline void efi_restore_gd(void) { } static inline void efi_set_bootdev(const char *dev, const char *devnr, - const char *path) { } + const char *path, void *buffer, + size_t buffer_size) { } static inline void efi_net_set_dhcp_ack(void *pkt, int len) { } static inline void efi_print_image_infos(void *pc) { } static inline efi_status_t efi_launch_capsules(void) diff --git a/include/efi_variable.h b/include/efi_variable.h index bf5076233e4..4623a641427 100644 --- a/include/efi_variable.h +++ b/include/efi_variable.h @@ -306,4 +306,15 @@ efi_status_t __efi_runtime EFIAPI efi_get_next_variable_name_runtime(efi_uintn_t *variable_name_size, u16 *variable_name, efi_guid_t *guid); +/** + * efi_var_buf_update() - udpate memory buffer for variables + * + * @var_buf: source buffer + * + * This function copies to the memory buffer for UEFI variables. Call this + * function in ExitBootServices() if memory backed variables are only used + * at runtime to fill the buffer. + */ +void efi_var_buf_update(struct efi_var_file *var_buf); + #endif diff --git a/include/exports.h b/include/exports.h index b3005540916..faf0f592443 100644 --- a/include/exports.h +++ b/include/exports.h @@ -15,8 +15,14 @@ struct cmd_tbl; struct spi_slave; -/* Set up the jump table for use by the API */ -void jumptable_init(void); +/** + * jumptable_init() - Set up the jump table for use by the API + * + * It is called during the generic post-relocation init sequence. + * + * Return: 0 if OK + */ +int jumptable_init(void); /* These are declarations of exported functions available in C code */ unsigned long get_version(void); diff --git a/include/init.h b/include/init.h index 0f48ccb57ad..980be279936 100644 --- a/include/init.h +++ b/include/init.h @@ -164,6 +164,41 @@ int arch_setup_bdinfo(void); int setup_bdinfo(void); /** + * cpu_secondary_init_r() - CPU-specific secondary initialization + * + * After non-volatile devices, environment and cpu code are setup, have + * another round to deal with any initialization that might require + * full access to the environment or loading of some image (firmware) + * from a non-volatile device. + * + * It is called during the generic post-relocation init sequence. + * + * Return: 0 if OK + */ +int cpu_secondary_init_r(void); + +/** + * pci_ep_init() - Initialize pci endpoint devices + * + * It is called during the generic post-relocation init sequence. + * + * Return: 0 if OK + */ +int pci_ep_init(void); + +/** + * pci_init() - Enumerate pci devices + * + * It is called during the generic post-relocation init sequence to enumerate + * pci buses. This is needed, for instance, in the case of DM PCI-based + * Ethernet devices, which will not be detected without having the enumeration + * performed earlier. + * + * Return: 0 if OK + */ +int pci_init(void); + +/** * init_cache_f_r() - Turn on the cache in preparation for relocation * * Return: 0 if OK, -ve on error @@ -234,8 +269,6 @@ int mac_read_from_eeprom(void); int set_cpu_clk_info(void); int update_flash_size(int flash_size); int arch_early_init_r(void); -void pci_init(void); -void pci_ep_init(void); int misc_init_r(void); #if defined(CONFIG_VID) int init_func_vid(void); @@ -267,7 +300,15 @@ int board_early_init_r(void); /* TODO(sjg@chromium.org): Drop this when DM_PCI migration is completed */ void pci_init_board(void); -void trap_init(unsigned long reloc_addr); +/** + * arch_initr_trap() - Init traps + * + * Arch specific routine for initializing traps. It is called during the + * generic board init sequence, after relocation. + * + * Return: 0 if OK + */ +int arch_initr_trap(void); /** * main_loop() - Enter the main loop of U-Boot diff --git a/include/iomux.h b/include/iomux.h index e6e1097db5b..da7ff697d21 100644 --- a/include/iomux.h +++ b/include/iomux.h @@ -26,6 +26,5 @@ extern int cd_count[MAX_FILES]; int iomux_doenv(const int, const char *); void iomux_printdevs(const int); -struct stdio_dev *search_device(int, const char *); #endif /* _IO_MUX_H */ diff --git a/include/linux/intel-smc.h b/include/linux/intel-smc.h new file mode 100644 index 00000000000..cacb410691b --- /dev/null +++ b/include/linux/intel-smc.h @@ -0,0 +1,573 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2017-2018, Intel Corporation + */ + +#ifndef __INTEL_SMC_H +#define __INTEL_SMC_H + +#include <linux/arm-smccc.h> +#include <linux/bitops.h> + +/* + * This file defines the Secure Monitor Call (SMC) message protocol used for + * service layer driver in normal world (EL1) to communicate with secure + * monitor software in Secure Monitor Exception Level 3 (EL3). + * + * This file is shared with secure firmware (FW) which is out of u-boot tree. + * + * An ARM SMC instruction takes a function identifier and up to 6 64-bit + * register values as arguments, and can return up to 4 64-bit register + * values. The operation of the secure monitor is determined by the parameter + * values passed in through registers. + + * EL1 and EL3 communicates pointer as physical address rather than the + * virtual address. + */ + +/* + * Functions specified by ARM SMC Calling convention: + * + * FAST call executes atomic operations, returns when the requested operation + * has completed. + * STD call starts a operation which can be preempted by a non-secure + * interrupt. The call can return before the requested operation has + * completed. + * + * a0..a7 is used as register names in the descriptions below, on arm32 + * that translates to r0..r7 and on arm64 to w0..w7. + */ + +#define INTEL_SIP_SMC_STD_CALL_VAL(func_num) \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_STD_CALL, ARM_SMCCC_SMC_64, \ + ARM_SMCCC_OWNER_SIP, (func_num)) + +#define INTEL_SIP_SMC_FAST_CALL_VAL(func_num) \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_64, \ + ARM_SMCCC_OWNER_SIP, (func_num)) + +/* + * Return values in INTEL_SIP_SMC_* call + * + * INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION: + * Secure monitor software doesn't recognize the request. + * + * INTEL_SIP_SMC_STATUS_OK: + * SMC call completed successfully, + * In case of FPGA configuration write operation, it means secure monitor + * software can accept the next chunk of FPGA configuration data. + * + * INTEL_SIP_SMC_STATUS_BUSY: + * In case of FPGA configuration write operation, it means secure monitor + * software is still processing previous data & can't accept the next chunk + * of data. Service driver needs to issue + * INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE call to query the + * completed block(s). + * + * INTEL_SIP_SMC_STATUS_ERROR: + * There is error during the SMC call process. + * + * INTEL_SIP_SMC_REG_ERROR: + * There is error during a read or write operation of the protected + * registers. + */ +#define INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION 0xFFFFFFFF +#define INTEL_SIP_SMC_STATUS_OK 0x0 +#define INTEL_SIP_SMC_STATUS_BUSY 0x1 +#define INTEL_SIP_SMC_STATUS_REJECTED 0x2 +#define INTEL_SIP_SMC_STATUS_ERROR 0x4 +#define INTEL_SIP_SMC_REG_ERROR 0x5 +#define INTEL_SIP_SMC_RSU_ERROR 0x7 + +/* + * Request INTEL_SIP_SMC_FPGA_CONFIG_START + * + * Sync call used by service driver at EL1 to request the FPGA in EL3 to + * be prepare to receive a new configuration. + * + * Call register usage: + * a0: INTEL_SIP_SMC_FPGA_CONFIG_START. + * a1: flag for full or partial configuration + * 0 full reconfiguration. + * 1 partial reconfiguration. + * a2-7: not used. + * + * Return status: + * a0: INTEL_SIP_SMC_STATUS_OK, or INTEL_SIP_SMC_STATUS_ERROR. + * a1-3: not used. + */ +#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_START 1 +#define INTEL_SIP_SMC_FPGA_CONFIG_START \ + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_START) + +/* + * Request INTEL_SIP_SMC_FPGA_CONFIG_WRITE + * + * Async call used by service driver at EL1 to provide FPGA configuration data + * to secure world. + * + * Call register usage: + * a0: INTEL_SIP_SMC_FPGA_CONFIG_WRITE. + * a1: 64bit physical address of the configuration data memory block + * a2: Size of configuration data block. + * a3-7: not used. + * + * Return status: + * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_STATUS_BUSY, + * INTEL_SIP_SMC_STATUS_REJECTED or INTEL_SIP_SMC_STATUS_ERROR. + * a1: 64bit physical address of 1st completed memory block if any completed + * block, otherwise zero value. + * a2: 64bit physical address of 2nd completed memory block if any completed + * block, otherwise zero value. + * a3: 64bit physical address of 3rd completed memory block if any completed + * block, otherwise zero value. + */ +#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_WRITE 2 +#define INTEL_SIP_SMC_FPGA_CONFIG_WRITE \ + INTEL_SIP_SMC_STD_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_WRITE) + +/* + * Request INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE + * + * Sync call used by service driver at EL1 to track the completed write + * transactions. This request is called after INTEL_SIP_SMC_FPGA_CONFIG_WRITE + * call returns INTEL_SIP_SMC_STATUS_BUSY. + * + * Call register usage: + * a0: INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE. + * a1-7: not used. + * + * Return status: + * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_STATUS_BUSY or + * INTEL_SIP_SMC_STATUS_ERROR. + * a1: 64bit physical address of 1st completed memory block. + * a2: 64bit physical address of 2nd completed memory block if + * any completed block, otherwise zero value. + * a3: 64bit physical address of 3rd completed memory block if + * any completed block, otherwise zero value. + */ +#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE 3 +#define INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE \ +INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE) + +/* + * Request INTEL_SIP_SMC_FPGA_CONFIG_ISDONE + * + * Sync call used by service driver at EL1 to inform secure world that all + * data are sent, to check whether or not the secure world had completed + * the FPGA configuration process. + * + * Call register usage: + * a0: INTEL_SIP_SMC_FPGA_CONFIG_ISDONE. + * a1-7: not used. + * + * Return status: + * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_STATUS_BUSY or + * INTEL_SIP_SMC_STATUS_ERROR. + * a1-3: not used. + */ +#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_ISDONE 4 +#define INTEL_SIP_SMC_FPGA_CONFIG_ISDONE \ + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_ISDONE) + +/* + * Request INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM + * + * Sync call used by service driver at EL1 to query the physical address of + * memory block reserved by secure monitor software. + * + * Call register usage: + * a0:INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM. + * a1-7: not used. + * + * Return status: + * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_STATUS_ERROR. + * a1: start of physical address of reserved memory block. + * a2: size of reserved memory block. + * a3: not used. + */ +#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_GET_MEM 5 +#define INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM \ + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_GET_MEM) + +/* + * Request INTEL_SIP_SMC_FPGA_CONFIG_LOOPBACK + * + * For SMC loop-back mode only, used for internal integration, debugging + * or troubleshooting. + * + * Call register usage: + * a0: INTEL_SIP_SMC_FPGA_CONFIG_LOOPBACK. + * a1-7: not used. + * + * Return status: + * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_STATUS_ERROR. + * a1-3: not used. + */ +#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_LOOPBACK 6 +#define INTEL_SIP_SMC_FPGA_CONFIG_LOOPBACK \ + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_LOOPBACK) + +/* + * Request INTEL_SIP_SMC_REG_READ + * + * Read a protected register using SMCCC + * + * Call register usage: + * a0: INTEL_SIP_SMC_REG_READ. + * a1: register address. + * a2-7: not used. + * + * Return status: + * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_REG_ERROR. + * a1: Value in the register + * a2-3: not used. + */ +#define INTEL_SIP_SMC_FUNCID_REG_READ 7 +#define INTEL_SIP_SMC_REG_READ \ + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_REG_READ) + +/* + * Request INTEL_SIP_SMC_REG_WRITE + * + * Write a protected register using SMCCC + * + * Call register usage: + * a0: INTEL_SIP_SMC_REG_WRITE. + * a1: register address + * a2: value to program into register. + * a3-7: not used. + * + * Return status: + * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_REG_ERROR. + * a1-3: not used. + */ +#define INTEL_SIP_SMC_FUNCID_REG_WRITE 8 +#define INTEL_SIP_SMC_REG_WRITE \ + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_REG_WRITE) + +/* + * Request INTEL_SIP_SMC_FUNCID_REG_UPDATE + * + * Update one or more bits in a protected register using a + * read-modify-write operation. + * + * Call register usage: + * a0: INTEL_SIP_SMC_REG_UPDATE. + * a1: register address + * a2: Write Mask. + * a3: Value to write. + * a4-7: not used. + * + * Return status: + * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_REG_ERROR. + * a1-3: Not used. + */ +#define INTEL_SIP_SMC_FUNCID_REG_UPDATE 9 +#define INTEL_SIP_SMC_REG_UPDATE \ + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_REG_UPDATE) + +/* +* Request INTEL_SIP_SMC_RSU_STATUS +* +* Sync call used by service driver at EL1 to query the RSU status +* +* Call register usage: +* a0 INTEL_SIP_SMC_RSU_STATUS +* a1-7 not used +* +* Return status +* a0: Current Image +* a1: Last Failing Image +* a2: Version [width 32 bit] | State [width 32 bit] +* a3: Error details [width 32 bit] | Error location [width 32 bit] +* +* Or +* +* a0: INTEL_SIP_SMC_RSU_ERROR +*/ +#define INTEL_SIP_SMC_FUNCID_RSU_STATUS 11 +#define INTEL_SIP_SMC_RSU_STATUS \ + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_STATUS) + +/* +* Request INTEL_SIP_SMC_RSU_UPDATE +* +* Sync call used by service driver at EL1 to tell you next reboot is RSU_UPDATE +* +* Call register usage: +* a0 INTEL_SIP_SMC_RSU_UPDATE +* a1 64bit physical address of the configuration data memory in flash +* a2-7 not used +* +* Return status + * a0 INTEL_SIP_SMC_STATUS_OK +*/ +#define INTEL_SIP_SMC_FUNCID_RSU_UPDATE 12 +#define INTEL_SIP_SMC_RSU_UPDATE \ + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_UPDATE) + +/* + * Request INTEL_SIP_SMC_ECC_DBE + * + * Sync call used by service driver at EL1 alert EL3 that a Double Bit + * ECC error has occurred. + * + * Call register usage: + * a0 INTEL_SIP_SMC_ECC_DBE + * a1 SysManager Double Bit Error value + * a2-7 not used + * + * Return status + * a0 INTEL_SIP_SMC_STATUS_OK + */ +#define INTEL_SIP_SMC_FUNCID_ECC_DBE 13 +#define INTEL_SIP_SMC_ECC_DBE \ + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_ECC_DBE) + +/* +* Request INTEL_SIP_SMC_RSU_NOTIFY +* +* Sync call used by service driver at EL1 to report HPS software execution stage +* +* Call register usage: +* a0 INTEL_SIP_SMC_RSU_NOTIFY +* a1 32bit HPS software execution stage +* a2-7 not used +* +* Return status + * a0 INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_REG_ERROR. +*/ +#define INTEL_SIP_SMC_FUNCID_RSU_NOTIFY 14 +#define INTEL_SIP_SMC_RSU_NOTIFY \ + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_NOTIFY) + +/* + * Request INTEL_SIP_SMC_RSU_RETRY_COUNTER + * + * Sync call used by service driver at EL1 to query the RSU retry counter + * + * Call register usage: + * a0 INTEL_SIP_SMC_RSU_RETRY_COUNTER + * a1-7 not used + * + * Return status + * a0 INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_RSU_ERROR. + * a1 retry counter +*/ +#define INTEL_SIP_SMC_FUNCID_RSU_RETRY_COUNTER 15 +#define INTEL_SIP_SMC_RSU_RETRY_COUNTER \ + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_RETRY_COUNTER) + +/* + * Request INTEL_SIP_SMC_RSU_DCMF_VERSION + * + * Sync call used by service driver at EL1 to query DCMF version + * + * Call register usage: + * a0 INTEL_SIP_SMC_RSU_DCMF_VERSION + * a1-7 not used + * + * Return status + * a0 INTEL_SIP_SMC_STATUS_OK + * a1 dcmf1 version | dcmf0 version + * a2 dcmf3 version | dcmf2 version + * + * Or + * + * a0 INTEL_SIP_SMC_RSU_ERROR + */ +#define INTEL_SIP_SMC_FUNCID_RSU_DCMF_VERSION 16 +#define INTEL_SIP_SMC_RSU_DCMF_VERSION \ + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_DCMF_VERSION) + +/* + * Request INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION + * + * Sync call used by SSBL (EL2) to copy DCMF version to ATF memory + * + * Call register usage: + * a0 INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION + * a1 dcmf1 version | dcmf0 version + * a2 dcmf3 version | dcmf2 version + * + * Return status + * a0 INTEL_SIP_SMC_STATUS_OK + */ +#define INTEL_SIP_SMC_FUNCID_RSU_COPY_DCMF_VERSION 17 +#define INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION \ + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_COPY_DCMF_VERSION) + +/* + * Request INTEL_SIP_SMC_RSU_MAX_RETRY + * + * Sync call used by service driver at EL1 to query max_retry parameter + * + * Call register usage: + * a0 INTEL_SIP_SMC_RSU_MAX_RETRY + * a1-7 not used + * + * Return status + * a0 INTEL_SIP_SMC_STATUS_OK + * a1 max_retry + * + * Or + * + * a0 INTEL_SIP_SMC_RSU_ERROR + */ +#define INTEL_SIP_SMC_FUNCID_RSU_MAX_RETRY 18 +#define INTEL_SIP_SMC_RSU_MAX_RETRY \ + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_MAX_RETRY) + +/* + * Request INTEL_SIP_SMC_RSU_COPY_MAX_RETRY + * + * Sync call used by SSBL (EL2) to copy RSU 'max retry' to ATF memory + * + * Call register usage: + * a0 INTEL_SIP_SMC_RSU_COPY_MAX_RETRY + * a1 max retry + * a2-7 not used + * + * Return status + * a0 INTEL_SIP_SMC_STATUS_OK + */ +#define INTEL_SIP_SMC_FUNCID_RSU_COPY_MAX_RETRY 19 +#define INTEL_SIP_SMC_RSU_COPY_MAX_RETRY \ + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_COPY_MAX_RETRY) + +/* + * Request INTEL_SIP_SMC_RSU_DCMF_STATUS + * + * Sync call used by service driver at EL1 to query DCMF status + * + * Call register usage: + * a0 INTEL_SIP_SMC_RSU_DCMF_STATUS + * a1-7 not used + * + * Return status + * a0 INTEL_SIP_SMC_STATUS_OK + * a1 dcmf3 status | dcmf2 status | dcmf1 status | dcmf0 status + * + * Or + * + * a0 INTEL_SIP_SMC_RSU_ERROR + */ +#define INTEL_SIP_SMC_FUNCID_RSU_DCMF_STATUS 20 +#define INTEL_SIP_SMC_RSU_DCMF_STATUS \ + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_DCMF_STATUS) + +/* + * Request INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS + * + * Sync call used by SSBL (EL2) to copy RSU 'dcmf status' to ATF memory + * + * Call register usage: + * a0 INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS + * a1 dcmf status + * a2-7 not used + * + * Return status + * a0 INTEL_SIP_SMC_STATUS_OK + */ +#define INTEL_SIP_SMC_FUNCID_RSU_COPY_DCMF_STATUS 21 +#define INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS \ + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_COPY_DCMF_STATUS) + +/* + * Request INTEL_SIP_SMC_HPS_SET_BRIDGES + * + * Enable/disable the SoC FPGA bridges + * + * Call register usage: + * a0 INTEL_SIP_SMC_HPS_SET_BRIDGES + * a1 Set bridges status: + * 0 - Disable + * 1 - Enable + * a2-7 not used + * + * Return status + * a0 INTEL_SIP_SMC_STATUS_OK + */ +#define INTEL_SIP_SMC_FUNCID_HPS_SET_BRIDGES 50 +#define INTEL_SIP_SMC_HPS_SET_BRIDGES \ + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_HPS_SET_BRIDGES) + +/* + * Request INTEL_SIP_SMC_MBOX_SEND_CMD + * + * Send mailbox command to SDM + * + * Call register usage: + * a0 INTEL_SIP_SMC_MBOX_SEND_CMD + * a1 Mailbox command + * a2 64bit physical address pointer to command's arguments + * a3 Length of the argument + * a4 Urgent command: + * 0 - Disable + * 1 - Enable + * a5 64bit physical address pointer to a buffer for receiving responses + * a6 Length of the buffer + * + * Return status + * a0 INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_STATUS_ERROR + * a1 Status of mailbox response + * a2 Received length in the buffer + */ +#define INTEL_SIP_SMC_FUNCID_MBOX_SEND_CMD 60 +#define INTEL_SIP_SMC_MBOX_SEND_CMD \ + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_MBOX_SEND_CMD) + +/* + * Request INTEL_SIP_SMC_HPS_SET_PHYINTF + * + * Select EMACx PHY interface + * + * Call register usage: + * a0 INTEL_SIP_SMC_HPS_SET_PHYINTF + * a1 EMAC number: + * 0 - EMAC0 + * 1 - EMAC1 + * 2 - EMAC2 + * a2 Type of PHY interface: + * 0 - GMII_MII + * 1 - RGMII + * 2 - RMII + * 3 - RESET + * a3-7 not used + * + * Return status + * a0 INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_STATUS_ERROR + */ +#define INTEL_SIP_SMC_FUNCID_HPS_SET_PHYINTF 61 +#define INTEL_SIP_SMC_HPS_SET_PHYINTF \ + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_HPS_SET_PHYINTF) + +/* + * Request INTEL_SIP_SMC_HPS_SET_SDMMC_CCLK + * + * Select which phase shift of the clocks (drvsel & smplsel) for SDMMC + * + * Call register usage: + * a0 INTEL_SIP_SMC_HPS_SET_SDMMC_CCLK + * a1 Select which phase shift of the clock for cclk_in_drv (drvsel): + * 0 - 0 degree + * 1 - 45 degrees + * 2 - 90 degrees + * 3 - 135 degrees + * 4 - 180 degrees + * 5 - 225 degrees + * 6 - 270 degrees + * 7 - 315 degrees + * a2 Select which phase shift of the clock for cclk_in_sample (smplsel): + * (Same as above) + * a3-7 not used + * + * Return status + * a0 INTEL_SIP_SMC_STATUS_OK + */ +#define INTEL_SIP_SMC_FUNCID_HPS_SET_SDMMC_CCLK 62 +#define INTEL_SIP_SMC_HPS_SET_SDMMC_CCLK \ + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_HPS_SET_SDMMC_CCLK) + +#endif diff --git a/include/log.h b/include/log.h index 6bce5606489..2d27f9f657e 100644 --- a/include/log.h +++ b/include/log.h @@ -156,6 +156,9 @@ static inline int _log_nop(enum log_category_t cat, enum log_level_t level, */ #if CONFIG_IS_ENABLED(LOG) #define _LOG_MAX_LEVEL CONFIG_VAL(LOG_MAX_LEVEL) +#define log_emer(_fmt...) log(LOG_CATEGORY, LOGL_EMERG, ##_fmt) +#define log_alert(_fmt...) log(LOG_CATEGORY, LOGL_ALERT, ##_fmt) +#define log_crit(_fmt...) log(LOG_CATEGORY, LOGL_CRIT, ##_fmt) #define log_err(_fmt...) log(LOG_CATEGORY, LOGL_ERR, ##_fmt) #define log_warning(_fmt...) log(LOG_CATEGORY, LOGL_WARNING, ##_fmt) #define log_notice(_fmt...) log(LOG_CATEGORY, LOGL_NOTICE, ##_fmt) @@ -163,12 +166,17 @@ static inline int _log_nop(enum log_category_t cat, enum log_level_t level, #define log_debug(_fmt...) log(LOG_CATEGORY, LOGL_DEBUG, ##_fmt) #define log_content(_fmt...) log(LOG_CATEGORY, LOGL_DEBUG_CONTENT, ##_fmt) #define log_io(_fmt...) log(LOG_CATEGORY, LOGL_DEBUG_IO, ##_fmt) +#define log_cont(_fmt...) log(LOGC_CONT, LOGL_CONT, ##_fmt) #else #define _LOG_MAX_LEVEL LOGL_INFO +#define log_emerg(_fmt, ...) printf(_fmt, ##__VA_ARGS__) +#define log_alert(_fmt, ...) printf(_fmt, ##__VA_ARGS__) +#define log_crit(_fmt, ...) printf(_fmt, ##__VA_ARGS__) #define log_err(_fmt, ...) printf(_fmt, ##__VA_ARGS__) #define log_warning(_fmt, ...) printf(_fmt, ##__VA_ARGS__) #define log_notice(_fmt, ...) printf(_fmt, ##__VA_ARGS__) #define log_info(_fmt, ...) printf(_fmt, ##__VA_ARGS__) +#define log_cont(_fmt, ...) printf(_fmt, ##__VA_ARGS__) #define log_debug(_fmt, ...) debug(_fmt, ##__VA_ARGS__) #define log_content(_fmt...) log_nop(LOG_CATEGORY, \ LOGL_DEBUG_CONTENT, ##_fmt) @@ -217,10 +225,9 @@ static inline int _log_nop(enum log_category_t cat, enum log_level_t level, #if !_DEBUG && CONFIG_IS_ENABLED(LOG) #define debug_cond(cond, fmt, args...) \ - do { \ - if (1) \ - log(LOG_CATEGORY, LOGL_DEBUG, fmt, ##args); \ - } while (0) +({ \ + log(LOG_CATEGORY, LOGL_DEBUG, fmt, ##args); \ +}) #else /* _DEBUG */ @@ -229,11 +236,11 @@ static inline int _log_nop(enum log_category_t cat, enum log_level_t level, * computed by a preprocessor in the best case, allowing for the best * optimization. */ -#define debug_cond(cond, fmt, args...) \ - do { \ - if (cond) \ - printf(pr_fmt(fmt), ##args); \ - } while (0) +#define debug_cond(cond, fmt, args...) \ +({ \ + if (cond) \ + printf(pr_fmt(fmt), ##args); \ +}) #endif /* _DEBUG */ diff --git a/include/miiphy.h b/include/miiphy.h index 61c136b114c..8b77bac01e6 100644 --- a/include/miiphy.h +++ b/include/miiphy.h @@ -81,7 +81,15 @@ struct bb_miiphy_bus { extern struct bb_miiphy_bus bb_miiphy_buses[]; extern int bb_miiphy_buses_num; -void bb_miiphy_init(void); +/** + * bb_miiphy_init() - Initialize bit-banged MII bus driver + * + * It is called during the generic post-relocation init sequence. + * + * Return: 0 if OK + */ +int bb_miiphy_init(void); + int bb_miiphy_read(struct mii_dev *miidev, int addr, int devad, int reg); int bb_miiphy_write(struct mii_dev *miidev, int addr, int devad, int reg, u16 value); diff --git a/include/part.h b/include/part.h index 55be724d20f..815515aa809 100644 --- a/include/part.h +++ b/include/part.h @@ -9,6 +9,7 @@ #include <blk.h> #include <ide.h> #include <uuid.h> +#include <linker_lists.h> #include <linux/list.h> struct block_drvr { @@ -465,16 +466,49 @@ int get_disk_guid(struct blk_desc *dev_desc, char *guid); int is_valid_dos_buf(void *buf); /** - * write_mbr_partition() - write DOS MBR + * write_mbr_sector() - write DOS MBR * * @param dev_desc - block device descriptor * @param buf - buffer which contains the MBR * * @return - '0' on success, otherwise error */ -int write_mbr_partition(struct blk_desc *dev_desc, void *buf); +int write_mbr_sector(struct blk_desc *dev_desc, void *buf); + +int write_mbr_partitions(struct blk_desc *dev, + struct disk_partition *p, int count, unsigned int disksig); +int layout_mbr_partitions(struct disk_partition *p, int count, + lbaint_t total_sectors); #endif +#ifdef CONFIG_PARTITIONS +/** + * part_driver_get_count() - get partition driver count + * + * @return - number of partition drivers + */ +static inline int part_driver_get_count(void) +{ + return ll_entry_count(struct part_driver, part_driver); +} + +/** + * part_driver_get_first() - get first partition driver + * + * @return - pointer to first partition driver on success, otherwise NULL + */ +static inline struct part_driver *part_driver_get_first(void) +{ + return ll_entry_start(struct part_driver, part_driver); +} + +#else +static inline int part_driver_get_count(void) +{ return 0; } + +static inline struct part_driver *part_driver_get_first(void) +{ return NULL; } +#endif /* CONFIG_PARTITIONS */ #endif /* _PART_H */ diff --git a/include/part_efi.h b/include/part_efi.h index 1929e4400f1..c68529b4daf 100644 --- a/include/part_efi.h +++ b/include/part_efi.h @@ -56,6 +56,9 @@ #define PARTITION_LINUX_LVM_GUID \ EFI_GUID( 0xe6d6d379, 0xf507, 0x44c2, \ 0xa2, 0x3c, 0x23, 0x8f, 0x2a, 0x3d, 0xf9, 0x28) +#define PARTITION_U_BOOT_ENVIRONMENT \ + EFI_GUID( 0x3de21764, 0x95bd, 0x54bd, \ + 0xa5, 0xc3, 0x4a, 0xbe, 0x78, 0x6f, 0x38, 0xa8) /* linux/include/efi.h */ typedef u16 efi_char16_t; diff --git a/include/post.h b/include/post.h index eb218acde5f..5695e2b5334 100644 --- a/include/post.h +++ b/include/post.h @@ -107,7 +107,6 @@ int post_init_f (void); void post_bootmode_init (void); int post_bootmode_get (unsigned int * last_test); void post_bootmode_clear (void); -void post_output_backlog ( void ); int post_run (char *name, int flags); int post_info (char *name); int post_log (char *format, ...); @@ -116,6 +115,16 @@ void post_reloc (void); #endif unsigned long post_time_ms (unsigned long base); +/** + * post_output_backlog() - Print POST results + * + * Print POST results during the generic board init sequence, after + * relocation. + * + * Return: 0 if OK + */ +int post_output_backlog(void); + extern struct post_test post_list[]; extern unsigned int post_list_size; extern int post_hotkeys_pressed(void); diff --git a/include/power/mp5416.h b/include/power/mp5416.h new file mode 100644 index 00000000000..dc096fed3f2 --- /dev/null +++ b/include/power/mp5416.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* Copyright (C) 2020 Gateworks Corporation */ + +#ifndef MP5416_H_ +#define MP5416_H_ + +#define MP6416_REGULATOR_DRIVER "mp5416_regulator" + +enum { + MP5416_CTL0 = 0x00, + MP5416_CTL1 = 0x01, + MP5416_CTL2 = 0x02, + MP5416_ILIMIT = 0x03, + MP5416_VSET_SW1 = 0x04, + MP5416_VSET_SW2 = 0x05, + MP5416_VSET_SW3 = 0x06, + MP5416_VSET_SW4 = 0x07, + MP5416_VSET_LDO2 = 0x08, + MP5416_VSET_LDO3 = 0x09, + MP5416_VSET_LDO4 = 0x0a, + MP5416_VSET_LDO5 = 0x0b, + MP5416_STATUS1 = 0x0d, + MP5416_STATUS2 = 0x0e, + MP5416_STATUS3 = 0x0f, + MP5416_ID2 = 0x11, + MP5416_NUM_OF_REGS = 0x12, +}; + +#define MP5416_VSET_EN BIT(7) +#define MP5416_VSET_SW1_GVAL(x) ((((x) & 0x7f) * 12500) + 600000) +#define MP5416_VSET_SW2_GVAL(x) ((((x) & 0x7f) * 25000) + 800000) +#define MP5416_VSET_SW3_GVAL(x) ((((x) & 0x7f) * 12500) + 600000) +#define MP5416_VSET_SW4_GVAL(x) ((((x) & 0x7f) * 25000) + 800000) +#define MP5416_VSET_LDO_GVAL(x) ((((x) & 0x7f) * 25000) + 800000) +#define MP5416_VSET_LDO_SVAL(x) ((((x) & 0x7f) * 25000) + 800000) +#define MP5416_VSET_SW1_SVAL(x) (((x) - 600000) / 12500) +#define MP5416_VSET_SW2_SVAL(x) (((x) - 800000) / 25000) +#define MP5416_VSET_SW3_SVAL(x) (((x) - 600000) / 12500) +#define MP5416_VSET_SW4_SVAL(x) (((x) - 800000) / 25000) + +#endif diff --git a/include/test/ut.h b/include/test/ut.h index 3f2ee7514b8..17400c73ea9 100644 --- a/include/test/ut.h +++ b/include/test/ut.h @@ -338,4 +338,22 @@ ulong ut_check_free(void); */ long ut_check_delta(ulong last); +/** + * ut_silence_console() - Silence the console if requested by the user + * + * This stops test output from appear on the console. It is the default on + * sandbox, unless the -v flag is given. For other boards, this does nothing. + * + * @uts: Test state (in case in future we want to keep state here) + */ +void ut_silence_console(struct unit_test_state *uts); + +/** + * ut_unsilence_console() - Unsilence the console after a test + * + * This restarts console output again and turns off console recording. This + * happens on all boards, including sandbox. + */ +void ut_unsilence_console(struct unit_test_state *uts); + #endif diff --git a/include/uuid.h b/include/uuid.h index 73c5a89ec7c..0c653cb0874 100644 --- a/include/uuid.h +++ b/include/uuid.h @@ -39,10 +39,8 @@ int uuid_str_to_bin(const char *uuid_str, unsigned char *uuid_bin, int str_format); void uuid_bin_to_str(const unsigned char *uuid_bin, char *uuid_str, int str_format); -#ifdef CONFIG_PARTITION_TYPE_GUID int uuid_guid_get_bin(const char *guid_str, unsigned char *guid_bin); -int uuid_guid_get_str(const unsigned char *guid_bin, char *guid_str); -#endif +const char *uuid_guid_get_str(const unsigned char *guid_bin); void gen_rand_uuid(unsigned char *uuid_bin); void gen_rand_uuid_str(char *uuid_str, int str_format); #endif diff --git a/include/xen.h b/include/xen.h index a952a2c84b8..868132156e9 100644 --- a/include/xen.h +++ b/include/xen.h @@ -11,7 +11,7 @@ * Map Xen memory pages, initialize event handler and xenbus, * setup the grant table. */ -void xen_init(void); +int xen_init(void); /** * xen_fini() - Board cleanup before Linux kernel start |