diff options
Diffstat (limited to 'include')
516 files changed, 4855 insertions, 6004 deletions
diff --git a/include/config_fallbacks.h b/include/config_fallbacks.h index 17c76bcf3db..d60f494b58b 100644 --- a/include/config_fallbacks.h +++ b/include/config_fallbacks.h @@ -17,8 +17,8 @@ #endif #endif -#ifndef CONFIG_SYS_BAUDRATE_TABLE -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#ifndef CFG_SYS_BAUDRATE_TABLE +#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } #endif #endif /* __CONFIG_FALLBACKS_H */ diff --git a/include/configs/10m50_devboard.h b/include/configs/10m50_devboard.h index afd7cc89bf8..3a4fbc6eab8 100644 --- a/include/configs/10m50_devboard.h +++ b/include/configs/10m50_devboard.h @@ -15,7 +15,6 @@ /* * SERIAL */ -#define CONFIG_SYS_NS16550_MEM32 /* * Flash @@ -31,8 +30,8 @@ * -The heap is placed below the monitor * -The stack is placed below the heap (&grows down). */ -#define CONFIG_SYS_SDRAM_BASE 0xc8000000 -#define CONFIG_SYS_SDRAM_SIZE 0x08000000 +#define CFG_SYS_SDRAM_BASE 0xc8000000 +#define CFG_SYS_SDRAM_SIZE 0x08000000 #define CONFIG_MONITOR_IS_IN_RAM #endif /* __CONFIG_H */ diff --git a/include/configs/3c120_devboard.h b/include/configs/3c120_devboard.h index ad7bd133200..ab889180eed 100644 --- a/include/configs/3c120_devboard.h +++ b/include/configs/3c120_devboard.h @@ -26,8 +26,8 @@ * -The heap is placed below the monitor * -The stack is placed below the heap (&grows down). */ -#define CONFIG_SYS_SDRAM_BASE 0xD0000000 -#define CONFIG_SYS_SDRAM_SIZE 0x08000000 +#define CFG_SYS_SDRAM_BASE 0xD0000000 +#define CFG_SYS_SDRAM_SIZE 0x08000000 #define CONFIG_MONITOR_IS_IN_RAM #endif /* __CONFIG_H */ diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h index 25c3f22bea1..b360238b332 100644 --- a/include/configs/M5208EVBE.h +++ b/include/configs/M5208EVBE.h @@ -13,9 +13,7 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_SYS_UART_PORT (0) - -#define CONFIG_WATCHDOG_TIMEOUT 5000 +#define CFG_SYS_UART_PORT (0) /* I2C */ @@ -41,11 +39,11 @@ #define CONFIG_PRAM 512 /* 512 KB */ -#define CONFIG_SYS_CLK 166666666 /* CPU Core Clock */ -#define CONFIG_SYS_PLL_ODR 0x36 -#define CONFIG_SYS_PLL_FDR 0x7D +#define CFG_SYS_CLK 166666666 /* CPU Core Clock */ +#define CFG_SYS_PLL_ODR 0x36 +#define CFG_SYS_PLL_FDR 0x7D -#define CONFIG_SYS_MBAR 0xFC000000 +#define CFG_SYS_MBAR 0xFC000000 /* * Low Level Configuration Settings @@ -53,36 +51,36 @@ * You should know what you are doing if you make changes here. */ /* Definitions for initial stack pointer and data area (in DPRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in internal SRAM */ -#define CONFIG_SYS_INIT_RAM_CTRL 0x221 +#define CFG_SYS_INIT_RAM_ADDR 0x80000000 +#define CFG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in internal SRAM */ +#define CFG_SYS_INIT_RAM_CTRL 0x221 /* * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ -#define CONFIG_SYS_SDRAM_CFG1 0x43711630 -#define CONFIG_SYS_SDRAM_CFG2 0x56670000 -#define CONFIG_SYS_SDRAM_CTRL 0xE1002000 -#define CONFIG_SYS_SDRAM_EMOD 0x80010000 -#define CONFIG_SYS_SDRAM_MODE 0x00CD0000 +#define CFG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ +#define CFG_SYS_SDRAM_CFG1 0x43711630 +#define CFG_SYS_SDRAM_CFG2 0x56670000 +#define CFG_SYS_SDRAM_CTRL 0xE1002000 +#define CFG_SYS_SDRAM_EMOD 0x80010000 +#define CFG_SYS_SDRAM_MODE 0x00CD0000 /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) +#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) /* FLASH organization */ #ifdef CONFIG_SYS_FLASH_CFI -# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ +# define CFG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ #endif -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE +#define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE /* * Configuration for environment @@ -95,15 +93,15 @@ /* Cache Configuration */ -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ +#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 4) +#define CFG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) +#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ +#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ CF_CACR_DISD | CF_CACR_INVI | \ CF_CACR_CEIB | CF_CACR_DCM | \ CF_CACR_EUSP) @@ -117,8 +115,8 @@ * CS4 - Available * CS5 - Available */ -#define CONFIG_SYS_CS0_BASE 0 -#define CONFIG_SYS_CS0_MASK 0x007F0001 -#define CONFIG_SYS_CS0_CTRL 0x00001FA0 +#define CFG_SYS_CS0_BASE 0 +#define CFG_SYS_CS0_MASK 0x007F0001 +#define CFG_SYS_CS0_CTRL 0x00001FA0 #endif /* _M5208EVBE_H */ diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h index f200d706a92..ed45eccb62c 100644 --- a/include/configs/M5235EVB.h +++ b/include/configs/M5235EVB.h @@ -18,14 +18,12 @@ * (easy to change) */ -#define CONFIG_SYS_UART_PORT (0) - -#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ +#define CFG_SYS_UART_PORT (0) /* I2C */ -#define CONFIG_SYS_I2C_PINMUX_REG (gpio->par_qspi) -#define CONFIG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK) -#define CONFIG_SYS_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA) +#define CFG_SYS_I2C_PINMUX_REG (gpio->par_qspi) +#define CFG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK) +#define CFG_SYS_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA) /* this must be included AFTER the definition of CONFIG COMMANDS (if any) */ #ifdef CONFIG_MCFFEC @@ -50,10 +48,10 @@ #define CONFIG_PRAM 512 /* 512 KB */ -#define CONFIG_SYS_CLK 75000000 -#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2 +#define CFG_SYS_CLK 75000000 +#define CFG_SYS_CPU_CLK CFG_SYS_CLK * 2 -#define CONFIG_SYS_MBAR 0x40000000 +#define CFG_SYS_MBAR 0x40000000 /* * Low Level Configuration Settings @@ -63,17 +61,17 @@ /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ -#define CONFIG_SYS_INIT_RAM_CTRL 0x21 +#define CFG_SYS_INIT_RAM_ADDR 0x20000000 +#define CFG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ +#define CFG_SYS_INIT_RAM_CTRL 0x21 /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ +#define CFG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ /* * For booting Linux, the board info and command line data @@ -81,16 +79,16 @@ * the maximum mapped by the Linux kernel during initialization ?? */ /* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) +#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) /*----------------------------------------------------------------------- * FLASH organization */ #ifdef CONFIG_SYS_FLASH_CFI -# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ +# define CFG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ #endif -#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) +#define CFG_SYS_FLASH_BASE (CFG_SYS_CS0_BASE) /* Configuration for environment * Environment is embedded in u-boot in the second sector of the flash @@ -104,15 +102,15 @@ * Cache Configuration */ -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ +#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 4) +#define CFG_SYS_ICACHE_INV (CF_CACR_CINV) +#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ +#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ CF_CACR_CEIB | CF_CACR_DCM | \ CF_CACR_EUSP) @@ -130,13 +128,13 @@ * CS7 - Available */ #ifdef CONFIG_NORFLASH_PS32BIT -# define CONFIG_SYS_CS0_BASE 0xFFC00000 -# define CONFIG_SYS_CS0_MASK 0x003f0001 -# define CONFIG_SYS_CS0_CTRL 0x00001D00 +# define CFG_SYS_CS0_BASE 0xFFC00000 +# define CFG_SYS_CS0_MASK 0x003f0001 +# define CFG_SYS_CS0_CTRL 0x00001D00 #else -# define CONFIG_SYS_CS0_BASE 0xFFE00000 -# define CONFIG_SYS_CS0_MASK 0x001f0001 -# define CONFIG_SYS_CS0_CTRL 0x00001D80 +# define CFG_SYS_CS0_BASE 0xFFE00000 +# define CFG_SYS_CS0_MASK 0x001f0001 +# define CFG_SYS_CS0_CTRL 0x00001D80 #endif #endif /* _M5329EVB_H */ diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h index 9ff66d751c6..0e38eeb4a36 100644 --- a/include/configs/M5249EVB.h +++ b/include/configs/M5249EVB.h @@ -18,7 +18,7 @@ * (easy to change) */ -#define CONFIG_SYS_UART_PORT (0) +#define CFG_SYS_UART_PORT (0) #undef CONFIG_MONITOR_IS_IN_RAM /* no pre-loader required!!! ;-) */ @@ -26,9 +26,9 @@ * Clock configuration: enable only one of the following options */ -#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ -#define CONFIG_SYS_FAST_CLK 1 /* MCF5249 can run at 140MHz */ -#define CONFIG_SYS_CLK 132025600 /* MCF5249 can run at 140MHz */ +#undef CFG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ +#define CFG_SYS_FAST_CLK 1 /* MCF5249 can run at 140MHz */ +#define CFG_SYS_CLK 132025600 /* MCF5249 can run at 140MHz */ /* * Low Level Configuration Settings @@ -36,14 +36,14 @@ * You should know what you are doing if you make changes here. */ -#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ -#define CONFIG_SYS_MBAR2 0x80000000 +#define CFG_SYS_MBAR 0x10000000 /* Register Base Addrs */ +#define CFG_SYS_MBAR2 0x80000000 /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ +#define CFG_SYS_INIT_RAM_ADDR 0x20000000 +#define CFG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ #define LDS_BOARD_TEXT \ . = DEFINED(env_offset) ? env_offset : .; \ @@ -52,11 +52,11 @@ /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ -#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) +#define CFG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ +#define CFG_SYS_FLASH_BASE (CFG_SYS_CS0_BASE) #if 0 /* test-only */ #define CONFIG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */ @@ -67,33 +67,33 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) +#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) /*----------------------------------------------------------------------- * FLASH organization */ #ifdef CONFIG_SYS_FLASH_CFI -# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ -# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } +# define CFG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ +# define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE } #endif /*----------------------------------------------------------------------- * Cache Configuration */ -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ +#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 4) +#define CFG_SYS_ICACHE_INV (CF_CACR_DCM) +#define CFG_SYS_CACHE_ACR0 (CFG_SYS_FLASH_BASE | \ CF_ADDRMASK(2) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ +#define CFG_SYS_CACHE_ACR1 (CFG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ +#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ CF_CACR_DBWE) /*----------------------------------------------------------------------- @@ -101,25 +101,25 @@ */ /* CS0 - AMD Flash, address 0xffc00000 */ -#define CONFIG_SYS_CS0_BASE 0xffe00000 -#define CONFIG_SYS_CS0_CTRL 0x00001980 /* WS=0110, AA=1, PS=10 */ +#define CFG_SYS_CS0_BASE 0xffe00000 +#define CFG_SYS_CS0_CTRL 0x00001980 /* WS=0110, AA=1, PS=10 */ /** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/ -#define CONFIG_SYS_CS0_MASK 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */ +#define CFG_SYS_CS0_MASK 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */ /* CS1 - FPGA, address 0xe0000000 */ -#define CONFIG_SYS_CS1_BASE 0xe0000000 -#define CONFIG_SYS_CS1_CTRL 0x00000d80 /* WS=0011, AA=1, PS=10 */ -#define CONFIG_SYS_CS1_MASK 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/ +#define CFG_SYS_CS1_BASE 0xe0000000 +#define CFG_SYS_CS1_CTRL 0x00000d80 /* WS=0011, AA=1, PS=10 */ +#define CFG_SYS_CS1_MASK 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/ /*----------------------------------------------------------------------- * Port configuration */ -#define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ -#define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54*/ -#define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ -#define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ -#define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ -#define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ -#define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */ +#define CFG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ +#define CFG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54*/ +#define CFG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ +#define CFG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ +#define CFG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ +#define CFG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ +#define CFG_SYS_GPIO1_LED 0x00400000 /* user led */ #endif /* M5249 */ diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h index f7bfe598a80..7e37c6d1199 100644 --- a/include/configs/M5253DEMO.h +++ b/include/configs/M5253DEMO.h @@ -8,7 +8,7 @@ #include <linux/stringify.h> -#define CONFIG_SYS_UART_PORT (0) +#define CFG_SYS_UART_PORT (0) /* Configuration for environment @@ -20,7 +20,7 @@ env/embedded.o(.text*); #ifdef CONFIG_DRIVER_DM9000 -# define CONFIG_DM9000_BASE (CONFIG_SYS_CS1_BASE | 0x300) +# define CONFIG_DM9000_BASE (CFG_SYS_CS1_BASE | 0x300) # define DM9000_IO CONFIG_DM9000_BASE # define DM9000_DATA (CONFIG_DM9000_BASE + 4) # undef CONFIG_DM9000_DEBUG @@ -45,18 +45,18 @@ #define CONFIG_HOSTNAME "M5253DEMO" /* I2C */ -#define CONFIG_SYS_I2C_PINMUX_REG (*(u32 *) (CONFIG_SYS_MBAR+0x19C)) -#define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF) -#define CONFIG_SYS_I2C_PINMUX_SET (0) - -#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ -#define CONFIG_SYS_FAST_CLK -#ifdef CONFIG_SYS_FAST_CLK -# define CONFIG_SYS_PLLCR 0x1243E054 -# define CONFIG_SYS_CLK 140000000 +#define CFG_SYS_I2C_PINMUX_REG (*(u32 *) (CFG_SYS_MBAR+0x19C)) +#define CFG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF) +#define CFG_SYS_I2C_PINMUX_SET (0) + +#undef CFG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ +#define CFG_SYS_FAST_CLK +#ifdef CFG_SYS_FAST_CLK +# define CFG_SYS_PLLCR 0x1243E054 +# define CFG_SYS_CLK 140000000 #else -# define CONFIG_SYS_PLLCR 0x135a4140 -# define CONFIG_SYS_CLK 70000000 +# define CFG_SYS_PLLCR 0x135a4140 +# define CFG_SYS_CLK 70000000 #endif /* @@ -65,32 +65,32 @@ * You should know what you are doing if you make changes here. */ -#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ -#define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */ +#define CFG_SYS_MBAR 0x10000000 /* Register Base Addrs */ +#define CFG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */ /* * Definitions for initial stack pointer and data area (in DPRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ +#define CFG_SYS_INIT_RAM_ADDR 0x20000000 +#define CFG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ /* * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ +#define CFG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) +#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) /* FLASH organization */ -#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) +#define CFG_SYS_FLASH_BASE (CFG_SYS_CS0_BASE) #define FLASH_SST6401B 0x200 #define SST_ID_xF6401B 0x236D236D @@ -101,45 +101,45 @@ * Amd/Atmel use 0x30 for sector erase, SST use 0x50. * 0x30 is block erase in SST */ -# define CONFIG_SYS_FLASH_SIZE 0x800000 +# define CFG_SYS_FLASH_SIZE 0x800000 #else -# define CONFIG_SYS_SST_SECT 2048 -# define CONFIG_SYS_SST_SECTSZ 0x1000 +# define CFG_SYS_SST_SECT 2048 +# define CFG_SYS_SST_SECTSZ 0x1000 #endif /* Cache Configuration */ -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ +#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 4) +#define CFG_SYS_ICACHE_INV (CF_CACR_DCM) +#define CFG_SYS_CACHE_ACR0 (CFG_SYS_FLASH_BASE | \ CF_ADDRMASK(8) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ +#define CFG_SYS_CACHE_ACR1 (CFG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ +#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ CF_CACR_DBWE) -#define CONFIG_SYS_CS0_BASE 0xFF800000 -#define CONFIG_SYS_CS0_MASK 0x007F0021 -#define CONFIG_SYS_CS0_CTRL 0x00001D80 +#define CFG_SYS_CS0_BASE 0xFF800000 +#define CFG_SYS_CS0_MASK 0x007F0021 +#define CFG_SYS_CS0_CTRL 0x00001D80 -#define CONFIG_SYS_CS1_BASE 0xE0000000 -#define CONFIG_SYS_CS1_MASK 0x00000001 -#define CONFIG_SYS_CS1_CTRL 0x00003DD8 +#define CFG_SYS_CS1_BASE 0xE0000000 +#define CFG_SYS_CS1_MASK 0x00000001 +#define CFG_SYS_CS1_CTRL 0x00003DD8 /*----------------------------------------------------------------------- * Port configuration */ -#define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ -#define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */ -#define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ -#define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ -#define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ -#define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ -#define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */ +#define CFG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ +#define CFG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */ +#define CFG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ +#define CFG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ +#define CFG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ +#define CFG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ +#define CFG_SYS_GPIO1_LED 0x00400000 /* user led */ #endif /* _M5253DEMO_H */ diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h index dcd83650f22..a9339e50525 100644 --- a/include/configs/M5272C3.h +++ b/include/configs/M5272C3.h @@ -17,9 +17,7 @@ * (easy to change) */ -#define CONFIG_SYS_UART_PORT (0) - -#define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */ +#define CFG_SYS_UART_PORT (0) #undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */ @@ -51,59 +49,59 @@ "save\0" \ "" -#define CONFIG_SYS_CLK 66000000 +#define CFG_SYS_CLK 66000000 /* * Low Level Configuration Settings * (address mappings, register initial values, etc.) * You should know what you are doing if you make changes here. */ -#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ -#define CONFIG_SYS_SCR 0x0003 -#define CONFIG_SYS_SPR 0xffff +#define CFG_SYS_MBAR 0x10000000 /* Register Base Addrs */ +#define CFG_SYS_SCR 0x0003 +#define CFG_SYS_SPR 0xffff /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ +#define CFG_SYS_INIT_RAM_ADDR 0x20000000 +#define CFG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_SIZE 4 /* SDRAM size in MB */ -#define CONFIG_SYS_FLASH_BASE 0xffe00000 +#define CFG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_SIZE 4 /* SDRAM size in MB */ +#define CFG_SYS_FLASH_BASE 0xffe00000 /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) +#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) /* * FLASH organization */ #ifdef CONFIG_SYS_FLASH_CFI -# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ +# define CFG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ #endif /*----------------------------------------------------------------------- * Cache Configuration */ -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ +#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 4) +#define CFG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) +#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ +#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ CF_CACR_DISD | CF_CACR_INVI | \ CF_CACR_CEIB | CF_CACR_DCM | \ CF_CACR_EUSP) @@ -111,11 +109,11 @@ /*----------------------------------------------------------------------- * Port configuration */ -#define CONFIG_SYS_PACNT 0x00000000 -#define CONFIG_SYS_PADDR 0x0000 -#define CONFIG_SYS_PADAT 0x0000 -#define CONFIG_SYS_PBCNT 0x55554155 /* Ethernet/UART configuration */ -#define CONFIG_SYS_PBDDR 0x0000 -#define CONFIG_SYS_PBDAT 0x0000 -#define CONFIG_SYS_PDCNT 0x00000000 +#define CFG_SYS_PACNT 0x00000000 +#define CFG_SYS_PADDR 0x0000 +#define CFG_SYS_PADAT 0x0000 +#define CFG_SYS_PBCNT 0x55554155 /* Ethernet/UART configuration */ +#define CFG_SYS_PBDDR 0x0000 +#define CFG_SYS_PBDAT 0x0000 +#define CFG_SYS_PDCNT 0x00000000 #endif /* _M5272C3_H */ diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h index 9012794501a..ff9f8535896 100644 --- a/include/configs/M5275EVB.h +++ b/include/configs/M5275EVB.h @@ -21,7 +21,7 @@ * (easy to change) */ -#define CONFIG_SYS_UART_PORT (0) +#define CFG_SYS_UART_PORT (0) /* Configuration for environment * Environment is embedded in u-boot in the second sector of the flash @@ -34,9 +34,9 @@ /* Available command configuration */ /* I2C */ -#define CONFIG_SYS_I2C_PINMUX_REG (gpio_reg->par_feci2c) -#define CONFIG_SYS_I2C_PINMUX_CLR (0xFFF0) -#define CONFIG_SYS_I2C_PINMUX_SET (0x000F) +#define CFG_SYS_I2C_PINMUX_REG (gpio_reg->par_feci2c) +#define CFG_SYS_I2C_PINMUX_CLR (0xFFF0) +#define CFG_SYS_I2C_PINMUX_SET (0x000F) #ifdef CONFIG_MCFFEC # define CONFIG_OVERWRITE_ETHADDR_ONCE @@ -54,7 +54,7 @@ "save\0" \ "" -#define CONFIG_SYS_CLK 150000000 +#define CFG_SYS_CLK 150000000 /* * Low Level Configuration Settings @@ -62,49 +62,49 @@ * You should know what you are doing if you make changes here. */ -#define CONFIG_SYS_MBAR 0x40000000 +#define CFG_SYS_MBAR 0x40000000 /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ +#define CFG_SYS_INIT_RAM_ADDR 0x20000000 +#define CFG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE +#define CFG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ +#define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) +#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) /*----------------------------------------------------------------------- * FLASH organization */ -#define CONFIG_SYS_FLASH_SIZE 0x200000 +#define CFG_SYS_FLASH_SIZE 0x200000 /*----------------------------------------------------------------------- * Cache Configuration */ -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ +#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 4) +#define CFG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) +#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ +#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ CF_CACR_DISD | CF_CACR_INVI | \ CF_CACR_CEIB | CF_CACR_DCM | \ CF_CACR_EUSP) @@ -112,12 +112,12 @@ /*----------------------------------------------------------------------- * Memory bank definitions */ -#define CONFIG_SYS_CS0_BASE 0xffe00000 -#define CONFIG_SYS_CS0_CTRL 0x00001980 -#define CONFIG_SYS_CS0_MASK 0x001F0001 +#define CFG_SYS_CS0_BASE 0xffe00000 +#define CFG_SYS_CS0_CTRL 0x00001980 +#define CFG_SYS_CS0_MASK 0x001F0001 -#define CONFIG_SYS_CS1_BASE 0x30000000 -#define CONFIG_SYS_CS1_CTRL 0x00001900 -#define CONFIG_SYS_CS1_MASK 0x00070001 +#define CFG_SYS_CS1_BASE 0x30000000 +#define CFG_SYS_CS1_CTRL 0x00001900 +#define CFG_SYS_CS1_MASK 0x00070001 #endif /* _M5275EVB_H */ diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h index e191dc615bc..bde9e770e52 100644 --- a/include/configs/M5282EVB.h +++ b/include/configs/M5282EVB.h @@ -17,7 +17,7 @@ * (easy to change) */ -#define CONFIG_SYS_UART_PORT (0) +#define CFG_SYS_UART_PORT (0) #undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */ @@ -49,98 +49,92 @@ "save\0" \ "" -#define CONFIG_SYS_CLK 64000000 +#define CFG_SYS_CLK 64000000 /* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */ -#define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */ -#define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */ +#define CFG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */ +#define CFG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */ /* * Low Level Configuration Settings * (address mappings, register initial values, etc.) * You should know what you are doing if you make changes here. */ -#define CONFIG_SYS_MBAR 0x40000000 +#define CFG_SYS_MBAR 0x40000000 /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ +#define CFG_SYS_INIT_RAM_ADDR 0x20000000 +#define CFG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE -#define CONFIG_SYS_INT_FLASH_BASE 0xf0000000 -#define CONFIG_SYS_INT_FLASH_ENABLE 0x21 +#define CFG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ +#define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE +#define CFG_SYS_INT_FLASH_BASE 0xf0000000 +#define CFG_SYS_INT_FLASH_ENABLE 0x21 /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) +#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) /*----------------------------------------------------------------------- * FLASH organization */ #ifdef CONFIG_SYS_FLASH_CFI -# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ -# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } +# define CFG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ +# define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE } #endif /*----------------------------------------------------------------------- * Cache Configuration */ -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ +#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 4) +#define CFG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM) +#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ +#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ CF_CACR_CEIB | CF_CACR_DBWE | \ CF_CACR_EUSP) /*----------------------------------------------------------------------- * Memory bank definitions */ -#define CONFIG_SYS_CS0_BASE 0xFFE00000 -#define CONFIG_SYS_CS0_CTRL 0x00001980 -#define CONFIG_SYS_CS0_MASK 0x001F0001 +#define CFG_SYS_CS0_BASE 0xFFE00000 +#define CFG_SYS_CS0_CTRL 0x00001980 +#define CFG_SYS_CS0_MASK 0x001F0001 /*----------------------------------------------------------------------- * Port configuration */ -#define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */ -#define CONFIG_SYS_PADDR 0x0000000 -#define CONFIG_SYS_PADAT 0x0000000 - -#define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */ -#define CONFIG_SYS_PBDDR 0x0000000 -#define CONFIG_SYS_PBDAT 0x0000000 - -#define CONFIG_SYS_PCCNT 0x0000000 /* Port C D[15:08] */ -#define CONFIG_SYS_PCDDR 0x0000000 -#define CONFIG_SYS_PCDAT 0x0000000 - -#define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */ -#define CONFIG_SYS_PCDDR 0x0000000 -#define CONFIG_SYS_PCDAT 0x0000000 - -#define CONFIG_SYS_PEHLPAR 0xC0 -#define CONFIG_SYS_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */ -#define CONFIG_SYS_DDRUA 0x05 -#define CONFIG_SYS_PJPAR 0xFF +#define CFG_SYS_PACNT 0x0000000 /* Port A D[31:24] */ +#define CFG_SYS_PADDR 0x0000000 +#define CFG_SYS_PADAT 0x0000000 + +#define CFG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */ +#define CFG_SYS_PBDDR 0x0000000 +#define CFG_SYS_PBDAT 0x0000000 + +#define CFG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */ + +#define CFG_SYS_PEHLPAR 0xC0 +#define CFG_SYS_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */ +#define CFG_SYS_DDRUA 0x05 +#define CFG_SYS_PJPAR 0xFF #endif /* _CONFIG_M5282EVB_H */ diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h index 79a4e6171d2..42b74aeb9b5 100644 --- a/include/configs/M53017EVB.h +++ b/include/configs/M53017EVB.h @@ -18,17 +18,15 @@ * (easy to change) */ -#define CONFIG_SYS_UART_PORT (0) - -#define CONFIG_WATCHDOG_TIMEOUT 5000 +#define CFG_SYS_UART_PORT (0) #ifdef CONFIG_MCFFEC -# define CONFIG_SYS_TX_ETH_BUFFER 8 -# define CONFIG_SYS_FEC_BUF_USE_SRAM +# define CFG_SYS_TX_ETH_BUFFER 8 +# define CFG_SYS_FEC_BUF_USE_SRAM #endif -#define CONFIG_SYS_RTC_CNT (0x8000) -#define CONFIG_SYS_RTC_SETUP (RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN) +#define CFG_SYS_RTC_CNT (0x8000) +#define CFG_SYS_RTC_SETUP (RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN) /* I2C */ @@ -54,10 +52,10 @@ #define CONFIG_PRAM 512 /* 512 KB */ -#define CONFIG_SYS_CLK 80000000 -#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 +#define CFG_SYS_CLK 80000000 +#define CFG_SYS_CPU_CLK CFG_SYS_CLK * 3 -#define CONFIG_SYS_MBAR 0xFC000000 +#define CFG_SYS_MBAR 0xFC000000 /* * Low Level Configuration Settings @@ -67,39 +65,39 @@ /* * Definitions for initial stack pointer and data area (in DPRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x20000 /* Size of used area in internal SRAM */ -#define CONFIG_SYS_INIT_RAM_CTRL 0x221 +#define CFG_SYS_INIT_RAM_ADDR 0x80000000 +#define CFG_SYS_INIT_RAM_SIZE 0x20000 /* Size of used area in internal SRAM */ +#define CFG_SYS_INIT_RAM_CTRL 0x221 /* * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */ -#define CONFIG_SYS_SDRAM_CFG1 0x43711630 -#define CONFIG_SYS_SDRAM_CFG2 0x56670000 -#define CONFIG_SYS_SDRAM_CTRL 0xE1092000 -#define CONFIG_SYS_SDRAM_EMOD 0x80010000 -#define CONFIG_SYS_SDRAM_MODE 0x00CD0000 +#define CFG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */ +#define CFG_SYS_SDRAM_CFG1 0x43711630 +#define CFG_SYS_SDRAM_CFG2 0x56670000 +#define CFG_SYS_SDRAM_CTRL 0xE1092000 +#define CFG_SYS_SDRAM_EMOD 0x80010000 +#define CFG_SYS_SDRAM_MODE 0x00CD0000 /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) +#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) /*----------------------------------------------------------------------- * FLASH organization */ #ifdef CONFIG_SYS_FLASH_CFI # define CONFIG_FLASH_SPANSION_S29WS_N 1 -# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ +# define CFG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ #endif -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE +#define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE /* Configuration for environment * Environment is embedded in u-boot in the second sector of the flash @@ -113,15 +111,15 @@ * Cache Configuration */ -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ +#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 4) +#define CFG_SYS_ICACHE_INV (CF_CACR_CINVA) +#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ +#define CFG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ CF_CACR_DCM_P) /*----------------------------------------------------------------------- @@ -135,12 +133,12 @@ * CS4 - Available * CS5 - Available */ -#define CONFIG_SYS_CS0_BASE 0 -#define CONFIG_SYS_CS0_MASK 0x00FF0001 -#define CONFIG_SYS_CS0_CTRL 0x00001FA0 +#define CFG_SYS_CS0_BASE 0 +#define CFG_SYS_CS0_MASK 0x00FF0001 +#define CFG_SYS_CS0_CTRL 0x00001FA0 -#define CONFIG_SYS_CS1_BASE 0xC0000000 -#define CONFIG_SYS_CS1_MASK 0x00070001 -#define CONFIG_SYS_CS1_CTRL 0x00001FA0 +#define CFG_SYS_CS1_BASE 0xC0000000 +#define CFG_SYS_CS1_MASK 0x00070001 +#define CFG_SYS_CS1_CTRL 0x00001FA0 #endif /* _M53017EVB_H */ diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h index 47ea51c5072..72f0c63a1e2 100644 --- a/include/configs/M5329EVB.h +++ b/include/configs/M5329EVB.h @@ -18,9 +18,7 @@ * (easy to change) */ -#define CONFIG_SYS_UART_PORT (0) - -#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ +#define CFG_SYS_UART_PORT (0) /* I2C */ @@ -46,12 +44,12 @@ #define CONFIG_PRAM 512 /* 512 KB */ -#define CONFIG_SYS_CLK 80000000 -#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 +#define CFG_SYS_CLK 80000000 +#define CFG_SYS_CPU_CLK CFG_SYS_CLK * 3 -#define CONFIG_SYS_MBAR 0xFC000000 +#define CFG_SYS_MBAR 0xFC000000 -#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000) +#define CFG_SYS_LATCH_ADDR (CFG_SYS_CS1_BASE + 0x80000) /* * Low Level Configuration Settings @@ -61,45 +59,44 @@ /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ -#define CONFIG_SYS_INIT_RAM_CTRL 0x221 +#define CFG_SYS_INIT_RAM_ADDR 0x80000000 +#define CFG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ +#define CFG_SYS_INIT_RAM_CTRL 0x221 /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ -#define CONFIG_SYS_SDRAM_CFG1 0x53722730 -#define CONFIG_SYS_SDRAM_CFG2 0x56670000 -#define CONFIG_SYS_SDRAM_CTRL 0xE1092000 -#define CONFIG_SYS_SDRAM_EMOD 0x40010000 -#define CONFIG_SYS_SDRAM_MODE 0x018D0000 +#define CFG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ +#define CFG_SYS_SDRAM_CFG1 0x53722730 +#define CFG_SYS_SDRAM_CFG2 0x56670000 +#define CFG_SYS_SDRAM_CTRL 0xE1092000 +#define CFG_SYS_SDRAM_EMOD 0x40010000 +#define CFG_SYS_SDRAM_MODE 0x018D0000 /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) +#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) /*----------------------------------------------------------------------- * FLASH organization */ #ifdef CONFIG_SYS_FLASH_CFI -# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ +# define CFG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ #endif #ifdef CONFIG_CMD_NAND -# define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE -# define CONFIG_SYS_NAND_SIZE 1 -# define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +# define CFG_SYS_NAND_BASE CFG_SYS_CS2_BASE +# define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } # define NAND_ALLOW_ERASE_ALL 1 #endif -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE +#define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE /* Configuration for environment * Environment is embedded in u-boot in the second sector of the flash @@ -113,15 +110,15 @@ * Cache Configuration */ -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ +#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 4) +#define CFG_SYS_ICACHE_INV (CF_CACR_CINVA) +#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ +#define CFG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ CF_CACR_DCM_P) /*----------------------------------------------------------------------- @@ -135,18 +132,18 @@ * CS4 - Available * CS5 - Available */ -#define CONFIG_SYS_CS0_BASE 0 -#define CONFIG_SYS_CS0_MASK 0x007f0001 -#define CONFIG_SYS_CS0_CTRL 0x00001fa0 +#define CFG_SYS_CS0_BASE 0 +#define CFG_SYS_CS0_MASK 0x007f0001 +#define CFG_SYS_CS0_CTRL 0x00001fa0 -#define CONFIG_SYS_CS1_BASE 0x10000000 -#define CONFIG_SYS_CS1_MASK 0x001f0001 -#define CONFIG_SYS_CS1_CTRL 0x002A3780 +#define CFG_SYS_CS1_BASE 0x10000000 +#define CFG_SYS_CS1_MASK 0x001f0001 +#define CFG_SYS_CS1_CTRL 0x002A3780 #ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_CS2_BASE 0x20000000 -#define CONFIG_SYS_CS2_MASK (16 << 20) -#define CONFIG_SYS_CS2_CTRL 0x00001f60 +#define CFG_SYS_CS2_BASE 0x20000000 +#define CFG_SYS_CS2_MASK (16 << 20) +#define CFG_SYS_CS2_CTRL 0x00001f60 #endif #endif /* _M5329EVB_H */ diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h index a2e36cc8673..4e8b54e01f4 100644 --- a/include/configs/M5373EVB.h +++ b/include/configs/M5373EVB.h @@ -20,9 +20,7 @@ * (easy to change) */ -#define CONFIG_SYS_UART_PORT (0) - -#define CONFIG_WATCHDOG_TIMEOUT 3360 /* timeout in ms, max is 3.36 sec */ +#define CFG_SYS_UART_PORT (0) /* I2C */ @@ -48,12 +46,12 @@ #define CONFIG_PRAM 512 /* 512 KB */ -#define CONFIG_SYS_CLK 80000000 -#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 +#define CFG_SYS_CLK 80000000 +#define CFG_SYS_CPU_CLK CFG_SYS_CLK * 3 -#define CONFIG_SYS_MBAR 0xFC000000 +#define CFG_SYS_MBAR 0xFC000000 -#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000) +#define CFG_SYS_LATCH_ADDR (CFG_SYS_CS1_BASE + 0x80000) /* * Low Level Configuration Settings @@ -63,43 +61,42 @@ /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ -#define CONFIG_SYS_INIT_RAM_CTRL 0x221 +#define CFG_SYS_INIT_RAM_ADDR 0x80000000 +#define CFG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ +#define CFG_SYS_INIT_RAM_CTRL 0x221 /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ -#define CONFIG_SYS_SDRAM_CFG1 0x53722730 -#define CONFIG_SYS_SDRAM_CFG2 0x56670000 -#define CONFIG_SYS_SDRAM_CTRL 0xE1092000 -#define CONFIG_SYS_SDRAM_EMOD 0x40010000 -#define CONFIG_SYS_SDRAM_MODE 0x018D0000 +#define CFG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ +#define CFG_SYS_SDRAM_CFG1 0x53722730 +#define CFG_SYS_SDRAM_CFG2 0x56670000 +#define CFG_SYS_SDRAM_CTRL 0xE1092000 +#define CFG_SYS_SDRAM_EMOD 0x40010000 +#define CFG_SYS_SDRAM_MODE 0x018D0000 /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) +#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) /*----------------------------------------------------------------------- * FLASH organization */ #ifdef CONFIG_SYS_FLASH_CFI -# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ +# define CFG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ #endif -# define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE -# define CONFIG_SYS_NAND_SIZE 1 -# define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +# define CFG_SYS_NAND_BASE CFG_SYS_CS2_BASE +# define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } # define NAND_ALLOW_ERASE_ALL 1 -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE +#define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE /* Configuration for environment * Environment is embedded in u-boot in the second sector of the flash @@ -113,15 +110,15 @@ * Cache Configuration */ -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ +#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 4) +#define CFG_SYS_ICACHE_INV (CF_CACR_CINVA) +#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ +#define CFG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ CF_CACR_DCM_P) /*----------------------------------------------------------------------- @@ -135,16 +132,16 @@ * CS4 - Available * CS5 - Available */ -#define CONFIG_SYS_CS0_BASE 0 -#define CONFIG_SYS_CS0_MASK 0x007f0001 -#define CONFIG_SYS_CS0_CTRL 0x00001fa0 +#define CFG_SYS_CS0_BASE 0 +#define CFG_SYS_CS0_MASK 0x007f0001 +#define CFG_SYS_CS0_CTRL 0x00001fa0 -#define CONFIG_SYS_CS1_BASE 0x10000000 -#define CONFIG_SYS_CS1_MASK 0x001f0001 -#define CONFIG_SYS_CS1_CTRL 0x002A3780 +#define CFG_SYS_CS1_BASE 0x10000000 +#define CFG_SYS_CS1_MASK 0x001f0001 +#define CFG_SYS_CS1_CTRL 0x002A3780 -#define CONFIG_SYS_CS2_BASE 0x20000000 -#define CONFIG_SYS_CS2_MASK (16 << 20) -#define CONFIG_SYS_CS2_CTRL 0x00001f60 +#define CFG_SYS_CS2_BASE 0x20000000 +#define CFG_SYS_CS2_MASK (16 << 20) +#define CFG_SYS_CS2_CTRL 0x00001f60 #endif /* _M5373EVB_H */ diff --git a/include/configs/MCR3000.h b/include/configs/MCR3000.h index b0809332bb5..232cf9e9984 100644 --- a/include/configs/MCR3000.h +++ b/include/configs/MCR3000.h @@ -59,21 +59,21 @@ /* Miscellaneous configurable options */ /* Definitions for initial stack pointer and data area (in DPRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x2800) -#define CONFIG_SYS_INIT_RAM_SIZE (0x2e00 - 0x2800) +#define CFG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x2800) +#define CFG_SYS_INIT_RAM_SIZE (0x2e00 - 0x2800) -/* RAM configuration (note that CONFIG_SYS_SDRAM_BASE must be zero) */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +/* RAM configuration (note that CFG_SYS_SDRAM_BASE must be zero) */ +#define CFG_SYS_SDRAM_BASE 0x00000000 /* FLASH organization */ -#define CONFIG_SYS_FLASH_BASE CONFIG_TEXT_BASE +#define CFG_SYS_FLASH_BASE CONFIG_TEXT_BASE /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) +#define CFG_SYS_BOOTMAPSZ (8 << 20) /* Environment Configuration */ @@ -82,6 +82,6 @@ /* Ethernet configuration part */ /* NAND configuration part */ -#define CONFIG_SYS_NAND_BASE 0x0C000000 +#define CFG_SYS_NAND_BASE 0x0C000000 #endif /* __CONFIG_H */ diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index bb93c287441..95a90199a42 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -14,31 +14,24 @@ * High Level Configuration Options */ -#define CONFIG_HWCONFIG - -/* - * On-board devices - */ -#define CONFIG_VSC7385_ENET - /* System performance - define the value i.e. CONFIG_SYS_XXX */ /* System Clock Configuration Register */ -#define CONFIG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */ -#define CONFIG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */ -#define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* SATA1-4 clock mode (0-3) */ +#define CFG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */ +#define CFG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */ +#define CFG_SYS_SCCR_SATACM SCCR_SATACM_2 /* SATA1-4 clock mode (0-3) */ /* * System IO Config */ -#define CONFIG_SYS_SICRH 0x08200000 -#define CONFIG_SYS_SICRL 0x00000000 +#define CFG_SYS_SICRH 0x08200000 +#define CFG_SYS_SICRL 0x00000000 /* * Output Buffer Impedance */ -#define CONFIG_SYS_OBIR 0x30100000 +#define CFG_SYS_OBIR 0x30100000 /* * Device configurations @@ -59,25 +52,25 @@ /* * DDR Setup */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#define CFG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000 -#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN) +#define CFG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN) #undef CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */ /* * Manually set up DDR parameters */ -#define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 MiB */ -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ +#define CFG_SYS_SDRAM_SIZE 0x10000000 /* 256 MiB */ +#define CFG_SYS_DDR_CS0_BNDS 0x0000000f +#define CFG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ | CSCONFIG_ODT_WR_ONLY_CURRENT \ | CSCONFIG_ROW_BIT_13 \ | CSCONFIG_COL_BIT_10) -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 -#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ +#define CFG_SYS_DDR_TIMING_3 0x00000000 +#define CFG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ | (0 << TIMING_CFG0_WRT_SHIFT) \ | (0 << TIMING_CFG0_RRT_SHIFT) \ | (0 << TIMING_CFG0_WWT_SHIFT) \ @@ -86,7 +79,7 @@ | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) /* 0x00260802 */ /* DDR400 */ -#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ +#define CFG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \ | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ | (7 << TIMING_CFG1_CASLAT_SHIFT) \ @@ -95,7 +88,7 @@ | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ | (2 << TIMING_CFG1_WRTORD_SHIFT)) /* 0x3937d322 */ -#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ +#define CFG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ | (5 << TIMING_CFG2_CPO_SHIFT) \ | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ @@ -104,23 +97,23 @@ | (8 << TIMING_CFG2_FOUR_ACT_SHIFT)) /* 0x02984cc8 */ -#define CONFIG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \ +#define CFG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \ | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) /* 0x06090100 */ -#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ +#define CFG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ | SDRAM_CFG_SDRAM_TYPE_DDR2) /* 0x43000000 */ -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ -#define CONFIG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \ +#define CFG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ +#define CFG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \ | (0x0442 << SDRAM_MODE_SD_SHIFT)) /* 0x04400442 */ /* DDR400 */ -#define CONFIG_SYS_DDR_MODE2 0x00000000 +#define CFG_SYS_DDR_MODE2 0x00000000 /* * Memory test */ -#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ +#undef CFG_SYS_DRAM_TEST /* memory test, takes time */ /* * The reserved memory @@ -129,65 +122,61 @@ /* * Initial RAM Base Address Setup */ -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ +#define CFG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CFG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ /* * FLASH on the Local Bus */ -#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ -#define CONFIG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */ +#define CFG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ +#define CFG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */ /* * NAND Flash on the Local Bus */ -#define CONFIG_SYS_NAND_BASE 0xE0600000 +#define CFG_SYS_NAND_BASE 0xE0600000 /* Vitesse 7385 */ -#define CONFIG_SYS_VSC7385_BASE 0xF0000000 +#define CFG_SYS_VSC7385_BASE 0xF0000000 /* * Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) +#define CFG_SYS_NS16550_CLK get_bus_freq(0) -#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) +#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) +#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) /* SERDES */ -#define CONFIG_FSL_SERDES #define CONFIG_FSL_SERDES1 0xe3000 #define CONFIG_FSL_SERDES2 0xe3100 /* I2C */ -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } +#define CFG_SYS_I2C_NOPROBES { {0, 0x51} } /* * Config on-board RTC */ -#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ +#define CFG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ /* * General PCI * Addresses are mapped 1-1. */ -#define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000 -#define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000 +#define CFG_SYS_PCIE1_CFG_BASE 0xA0000000 +#define CFG_SYS_PCIE1_CFG_SIZE 0x08000000 +#define CFG_SYS_PCIE1_MEM_PHYS 0xA8000000 +#define CFG_SYS_PCIE1_IO_PHYS 0xB8000000 -#define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000 -#define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000 -#define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000 +#define CFG_SYS_PCIE2_CFG_BASE 0xC0000000 +#define CFG_SYS_PCIE2_CFG_SIZE 0x08000000 +#define CFG_SYS_PCIE2_MEM_PHYS 0xC8000000 +#define CFG_SYS_PCIE2_IO_PHYS 0xD8000000 /* * TSEC @@ -200,7 +189,7 @@ #ifdef CONFIG_TSEC1 #define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_SYS_TSEC1_OFFSET 0x24000 +#define CFG_SYS_TSEC1_OFFSET 0x24000 #define TSEC1_PHY_ADDR 2 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) #define TSEC1_PHYIDX 0 @@ -228,7 +217,7 @@ * have to be in the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ +#define CFG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ /* * Environment Configuration diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index b241939fc38..780ee5ae865 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -13,11 +13,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_SRIO -#define CONFIG_SRIO1 /* SRIO port 1 */ - -#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ - #ifndef __ASSEMBLY__ #include <linux/stringify.h> #endif @@ -31,16 +26,15 @@ * Only possible on E500 Version 2 or newer cores. */ -#define CONFIG_SYS_CCSRBAR 0xe0000000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR +#define CFG_SYS_CCSRBAR 0xe0000000 +#define CFG_SYS_CCSRBAR_PHYS_LOW CFG_SYS_CCSRBAR /* DDR Setup */ -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE /* I2C addresses of SPD EEPROMs */ #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ @@ -115,32 +109,30 @@ * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx */ -#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ +#define CFG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_FLASH_BASE_PHYS 0xfff000000ull +#define CFG_SYS_FLASH_BASE_PHYS 0xfff000000ull #else -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE #endif -#define CONFIG_SYS_FLASH_BANKS_LIST \ - {CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS} - -#define CONFIG_HWCONFIG /* enable hwconfig */ +#define CFG_SYS_FLASH_BANKS_LIST \ + {CFG_SYS_FLASH_BASE_PHYS + 0x800000, CFG_SYS_FLASH_BASE_PHYS} /* * SDRAM on the Local Bus */ -#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ +#define CFG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull +#define CFG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull #else -#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS CONFIG_SYS_LBC_SDRAM_BASE +#define CFG_SYS_LBC_SDRAM_BASE_PHYS CFG_SYS_LBC_SDRAM_BASE #endif -#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ +#define CFG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ /* * Base Register 2 and Option Register 2 configure SDRAM. - * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. + * The SDRAM base address, CFG_SYS_LBC_SDRAM_BASE, is 0xf0000000. * * For BR2, need: * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 @@ -152,12 +144,12 @@ * 0 4 8 12 16 20 24 28 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 * - * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into + * FIXME: CFG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into * FIXME: the top 17 bits of BR2. */ /* - * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. + * The SDRAM size in MB, CFG_SYS_LBC_SDRAM_SIZE, is 64. * * For OR2, need: * 64MB mask for AM, OR2[0:7] = 1111 1100 @@ -170,10 +162,10 @@ * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 */ -#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ -#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ -#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ +#define CFG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ +#define CFG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ +#define CFG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ +#define CFG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ /* * Common settings for all Local Bus SDRAM commands. @@ -181,7 +173,7 @@ * or BSMA1617 (for CPU 1.0) (old) * is OR'ed in too. */ -#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ +#define CFG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ | LSDMR_PRETOACT7 \ | LSDMR_ACTTORW7 \ | LSDMR_BL8 \ @@ -220,8 +212,6 @@ * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 */ -#define CONFIG_FSL_CADMUS - #define CADMUS_BASE_ADDR 0xf8000000 #ifdef CONFIG_PHYS_64BIT #define CADMUS_BASE_ADDR_PHYS 0xff8000000ull @@ -229,76 +219,69 @@ #define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR #endif -#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ +#define CFG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ +#define CFG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /* Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) +#define CFG_SYS_NS16550_CLK get_bus_freq(0) -#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) +#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x4500) +#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x4600) /* * I2C */ #if !CONFIG_IS_ENABLED(DM_I2C) -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } +#define CFG_SYS_I2C_NOPROBES { {0, 0x69} } #endif /* * General PCI * Memory space is mapped 1-1, but I/O space must start from 0. */ -#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 +#define CFG_SYS_PCI1_MEM_VIRT 0x80000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCI1_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull +#define CFG_SYS_PCI1_MEM_PHYS 0xc00000000ull #else -#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 +#define CFG_SYS_PCI1_MEM_PHYS 0x80000000 #endif -#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 -#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 +#define CFG_SYS_PCI1_IO_VIRT 0xe2000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull +#define CFG_SYS_PCI1_IO_PHYS 0xfe2000000ull #else -#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 +#define CFG_SYS_PCI1_IO_PHYS 0xe2000000 #endif -#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ #ifdef CONFIG_PCIE1 -#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 +#define CFG_SYS_PCIE1_MEM_VIRT 0xa0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull +#define CFG_SYS_PCIE1_MEM_PHYS 0xc20000000ull #else -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 +#define CFG_SYS_PCIE1_MEM_PHYS 0xa0000000 #endif -#define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000 +#define CFG_SYS_PCIE1_IO_VIRT 0xe3000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_IO_PHYS 0xfe3000000ull +#define CFG_SYS_PCIE1_IO_PHYS 0xfe3000000ull #else -#define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 +#define CFG_SYS_PCIE1_IO_PHYS 0xe3000000 #endif #endif /* * RapidIO MMU */ -#define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000 +#define CFG_SYS_SRIO1_MEM_VIRT 0xc0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc40000000ull +#define CFG_SYS_SRIO1_MEM_PHYS 0xc40000000ull #else -#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc0000000 +#define CFG_SYS_SRIO1_MEM_PHYS 0xc0000000 #endif -#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ #if defined(CONFIG_TSEC_ENET) @@ -336,7 +319,7 @@ * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ +#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ /* * Environment Configuration diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index addb306d57f..b1d6b15811d 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -16,10 +16,10 @@ #include <asm/config_mpc85xx.h> #ifdef CONFIG_SDCARD -#define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10) -#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) -#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) -#define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10) +#define CFG_SYS_MMC_U_BOOT_SIZE (512 << 10) +#define CFG_SYS_MMC_U_BOOT_DST (0x11000000) +#define CFG_SYS_MMC_U_BOOT_START (0x11000000) +#define CFG_SYS_MMC_U_BOOT_OFFS (96 << 10) #endif #ifdef CONFIG_SPIFLASH @@ -27,27 +27,27 @@ #define CONFIG_RAMBOOT_SPIFLASH #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc #else -#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10) +#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10) +#define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) +#define CFG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) +#define CFG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10) #endif #endif #ifdef CONFIG_MTD_RAW_NAND #ifdef CONFIG_NXP_ESBC -#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) -#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) -#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 +#define CFG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) +#define CFG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) +#define CFG_SYS_NAND_U_BOOT_START 0x00200000 #else #ifdef CONFIG_TPL_BUILD -#define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) -#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) +#define CFG_SYS_NAND_U_BOOT_SIZE (576 << 10) +#define CFG_SYS_NAND_U_BOOT_DST (0x11000000) +#define CFG_SYS_NAND_U_BOOT_START (0x11000000) #elif defined(CONFIG_SPL_BUILD) -#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000 -#define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000 +#define CFG_SYS_NAND_U_BOOT_SIZE (128 << 10) +#define CFG_SYS_NAND_U_BOOT_DST 0xD0000000 +#define CFG_SYS_NAND_U_BOOT_START 0xD0000000 #endif #endif #endif @@ -68,35 +68,34 @@ * Memory space is mapped 1-1, but I/O space must start from 0. */ /* controller 1, Slot 1, tgtid 1, Base address a000 */ -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull #else -#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 +#define CFG_SYS_PCIE1_MEM_PHYS 0x80000000 #endif -#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 +#define CFG_SYS_PCIE1_IO_VIRT 0xffc00000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull +#define CFG_SYS_PCIE1_IO_PHYS 0xfffc00000ull #else -#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 +#define CFG_SYS_PCIE1_IO_PHYS 0xffc00000 #endif /* controller 2, Slot 2, tgtid 2, Base address 9000 */ -#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#define CFG_SYS_PCIE2_MEM_VIRT 0xa0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#define CFG_SYS_PCIE2_MEM_PHYS 0xc20000000ull #else -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 +#define CFG_SYS_PCIE2_MEM_PHYS 0xa0000000 #endif -#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 +#define CFG_SYS_PCIE2_IO_VIRT 0xffc10000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull +#define CFG_SYS_PCIE2_IO_PHYS 0xfffc10000ull #else -#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 +#define CFG_SYS_PCIE2_IO_PHYS 0xffc10000 #endif #endif -#define CONFIG_HWCONFIG /* * These can be toggled for performance analysis, otherwise use default. */ @@ -110,12 +109,12 @@ #ifndef __ASSEMBLY__ extern unsigned long get_sdram_size(void); #endif -#define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ +#define CFG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_CCSRBAR 0xffe00000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR +#define CFG_SYS_CCSRBAR 0xffe00000 +#define CFG_SYS_CCSRBAR_PHYS_LOW CFG_SYS_CCSRBAR /* * Memory map @@ -136,54 +135,52 @@ extern unsigned long get_sdram_size(void); */ /* NOR Flash on IFC */ -#define CONFIG_SYS_FLASH_BASE 0xee000000 +#define CFG_SYS_FLASH_BASE 0xee000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) +#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE) #else -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE #endif -#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ +#define CFG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024) -#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7) +#define CFG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024) +#define CFG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7) /* NOR Flash Timing Params */ -#define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \ +#define CFG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \ FTIM0_NOR_TEADC(0x5) | \ FTIM0_NOR_TEAHC(0x5) -#define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \ +#define CFG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \ FTIM1_NOR_TRAD_NOR(0x0f) -#define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \ +#define CFG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \ FTIM2_NOR_TCH(0x4) | \ FTIM2_NOR_TWP(0x1c) -#define CONFIG_SYS_NOR_FTIM3 0x0 +#define CFG_SYS_NOR_FTIM3 0x0 -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} +#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS} #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ /* CFI for NOR Flash */ /* NAND Flash on IFC */ -#define CONFIG_SYS_NAND_BASE 0xff800000 +#define CFG_SYS_NAND_BASE 0xff800000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull +#define CFG_SYS_NAND_BASE_PHYS 0xfff800000ull #else -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE #endif -#define CONFIG_MTD_PARTITION - -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ +#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_NAND \ | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) +#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024) #if defined(CONFIG_TARGET_P1010RDB_PA) -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ +#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \ @@ -192,7 +189,7 @@ extern unsigned long get_sdram_size(void); | CSOR_NAND_PB(32)) /* 32 Pages Per Block */ #elif defined(CONFIG_TARGET_P1010RDB_PB) -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ +#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ @@ -201,141 +198,134 @@ extern unsigned long get_sdram_size(void); | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */ #endif -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #if defined(CONFIG_TARGET_P1010RDB_PA) /* NAND Flash Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \ +#define CFG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \ FTIM0_NAND_TWP(0x0C) | \ FTIM0_NAND_TWCHT(0x04) | \ FTIM0_NAND_TWH(0x05) -#define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \ +#define CFG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \ FTIM1_NAND_TWBE(0x1d) | \ FTIM1_NAND_TRR(0x07) | \ FTIM1_NAND_TRP(0x0c) -#define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \ +#define CFG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \ FTIM2_NAND_TREH(0x05) | \ FTIM2_NAND_TWHRE(0x0f) -#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) +#define CFG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) #elif defined(CONFIG_TARGET_P1010RDB_PB) /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */ /* ONFI NAND Flash mode0 Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \ +#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \ FTIM0_NAND_TWP(0x18) | \ FTIM0_NAND_TWCHT(0x07) | \ FTIM0_NAND_TWH(0x0a)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \ +#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \ FTIM1_NAND_TWBE(0x39) | \ FTIM1_NAND_TRR(0x0e) | \ FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ +#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ FTIM2_NAND_TREH(0x0a) | \ FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 +#define CFG_SYS_NAND_FTIM3 0x0 #endif -#define CONFIG_SYS_NAND_DDR_LAW 11 - /* Set up IFC registers for boot location NOR/NAND */ #if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT) -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR1 CFG_SYS_NOR_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 #else -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR0 CFG_SYS_NOR_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 #endif /* CPLD on IFC */ -#define CONFIG_SYS_CPLD_BASE 0xffb00000 +#define CFG_SYS_CPLD_BASE 0xffb00000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull +#define CFG_SYS_CPLD_BASE_PHYS 0xfffb00000ull #else -#define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE +#define CFG_SYS_CPLD_BASE_PHYS CFG_SYS_CPLD_BASE #endif -#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ +#define CFG_SYS_CSPR3 (CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE_PHYS) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) -#define CONFIG_SYS_CSOR3 0x0 +#define CFG_SYS_AMASK3 IFC_AMASK(64*1024) +#define CFG_SYS_CSOR3 0x0 /* CPLD Timing parameters for IFC CS3 */ -#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ +#define CFG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ FTIM0_GPCM_TEADC(0x0e) | \ FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ +#define CFG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ FTIM1_GPCM_TRAD(0x1f)) -#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ +#define CFG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ FTIM2_GPCM_TCH(0x8) | \ FTIM2_GPCM_TWP(0x1f)) -#define CONFIG_SYS_CS3_FTIM3 0x0 +#define CFG_SYS_CS3_FTIM3 0x0 -#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ +#define CFG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ +#define CFG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /* * Config the L2 Cache as L2 SRAM */ #if defined(CONFIG_SPL_BUILD) #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) -#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 -#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) +#define CFG_SYS_INIT_L2_ADDR 0xD0000000 +#define CFG_SYS_INIT_L2_ADDR_PHYS CFG_SYS_INIT_L2_ADDR +#define CFG_SYS_INIT_L2_END (CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) #elif defined(CONFIG_MTD_RAW_NAND) #ifdef CONFIG_TPL_BUILD -#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 -#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) +#define CFG_SYS_INIT_L2_ADDR 0xD0000000 +#define CFG_SYS_INIT_L2_ADDR_PHYS CFG_SYS_INIT_L2_ADDR +#define CFG_SYS_INIT_L2_END (CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) #else -#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 -#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) +#define CFG_SYS_INIT_L2_ADDR 0xD0000000 +#define CFG_SYS_INIT_L2_ADDR_PHYS CFG_SYS_INIT_L2_ADDR +#define CFG_SYS_INIT_L2_END (CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) #endif #endif #endif /* Serial Port */ #undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) -#if defined(CONFIG_SPL_BUILD) && CONFIG_IS_ENABLED(INIT_MINIMAL) -#define CONFIG_NS16550_MIN_FUNCTIONS -#endif +#define CFG_SYS_NS16550_CLK get_bus_freq(0) -#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) +#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x4500) +#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x4600) /* I2C */ #define I2C_PCA9557_ADDR1 0x18 @@ -349,8 +339,7 @@ extern unsigned long get_sdram_size(void); /* enable read and write access to EEPROM */ /* RTC */ -#define CONFIG_RTC_PT7C4338 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CFG_SYS_I2C_RTC_ADDR 0x68 /* * SPI interface will not be available in case of NAND boot SPI CS0 will be @@ -400,7 +389,7 @@ extern unsigned long get_sdram_size(void); */ #if defined(CONFIG_MTD_RAW_NAND) #ifdef CONFIG_TPL_BUILD -#define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) +#define SPL_ENV_ADDR (CFG_SYS_INIT_L2_ADDR + (160 << 10)) #endif #endif @@ -417,7 +406,7 @@ extern unsigned long get_sdram_size(void); * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ +#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ /* * Environment Configuration diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 08c1bccb2b7..8b901ca47a0 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -18,9 +18,9 @@ #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE /* Set 1M boot space */ -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000) -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) +#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000) +#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ + (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #endif @@ -30,13 +30,7 @@ #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc #endif -#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS - -#define CONFIG_SYS_SRIO -#define CONFIG_SRIO1 /* SRIO port 1 */ -#define CONFIG_SRIO2 /* SRIO port 2 */ -#define CONFIG_SRIO_PCIE_BOOT_MASTER -#define CONFIG_SYS_DPAA_RMAN /* RMan */ +#define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS #ifndef __ASSEMBLY__ #include <linux/stringify.h> @@ -45,53 +39,53 @@ /* * These can be toggled for performance analysis, otherwise use default. */ -#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E +#define CFG_SYS_INIT_L2CSR0 L2CSR0_L2E -#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ +#define CFG_POST CFG_SYS_POST_MEMORY /* test POST memory test */ /* * Config the L3 Cache as L3 SRAM */ -#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE +#define CFG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \ +#define CFG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \ CONFIG_RAMBOOT_TEXT_BASE) #else -#define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR +#define CFG_SYS_INIT_L3_ADDR_PHYS CFG_SYS_INIT_L3_ADDR #endif #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_DCSRBAR 0xf0000000 -#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull +#define CFG_SYS_DCSRBAR 0xf0000000 +#define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull #endif /* * DDR Setup */ #define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE #define SPD_EEPROM_ADDRESS 0x52 -#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ +#define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ /* * Local Bus Definitions */ /* Set the local bus clock 1/8 of platform clock */ -#define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 +#define CFG_SYS_LBC_LCRR LCRR_CLKDIV_8 /* * This board doesn't have a promjet connector. * However, it uses commone corenet board LAW and TLB. * It is necessary to use the same start address with proper offset. */ -#define CONFIG_SYS_FLASH_BASE 0xe0000000 +#define CFG_SYS_FLASH_BASE 0xe0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull +#define CFG_SYS_FLASH_BASE_PHYS 0xfe0000000ull #else -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE #endif #define CONFIG_FSL_CPLD @@ -111,22 +105,22 @@ /* Nand Flash */ #ifdef CONFIG_NAND_FSL_ELBC -#define CONFIG_SYS_NAND_BASE 0xffa00000 +#define CFG_SYS_NAND_BASE 0xffa00000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull +#define CFG_SYS_NAND_BASE_PHYS 0xfffa00000ull #else -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE #endif -#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} +#define CFG_SYS_NAND_BASE_LIST {CFG_SYS_NAND_BASE} /* NAND flash config */ -#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ +#define CFG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ | BR_V) /* valid */ -#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ +#define CFG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ | OR_FCM_PGS /* Large Page*/ \ | OR_FCM_CSCT \ | OR_FCM_CST \ @@ -136,44 +130,40 @@ | OR_FCM_EHTR) #endif /* CONFIG_NAND_FSL_ELBC */ -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} - -#define CONFIG_HWCONFIG +#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS + 0x8000000} /* define to use L1 as initial stack */ #define CONFIG_L1_INIT_RAM -#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ +#define CFG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR +#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR /* The assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#define CFG_SYS_INIT_RAM_ADDR_PHYS \ + ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CFG_SYS_INIT_RAM_ADDR_PHYS_LOW) #else -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS +#define CFG_SYS_INIT_RAM_ADDR_PHYS CFG_SYS_INIT_RAM_ADDR +#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 +#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR_PHYS #endif -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 +#define CFG_SYS_INIT_RAM_SIZE 0x00004000 -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /* Serial Port - controlled on board with jumper J8 * open - index 2 * shorted - index 1 */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) +#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2) -#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) -#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) +#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500) +#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600) +#define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500) +#define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600) /* I2C */ @@ -181,49 +171,49 @@ /* * RapidIO */ -#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 +#define CFG_SYS_SRIO1_MEM_VIRT 0xa0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull +#define CFG_SYS_SRIO1_MEM_PHYS 0xc20000000ull #else -#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 +#define CFG_SYS_SRIO1_MEM_PHYS 0xa0000000 #endif -#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 +#define CFG_SYS_SRIO2_MEM_VIRT 0xb0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull +#define CFG_SYS_SRIO2_MEM_PHYS 0xc30000000ull #else -#define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 +#define CFG_SYS_SRIO2_MEM_PHYS 0xb0000000 #endif -#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ /* * for slave u-boot IMAGE instored in master memory space, * PHYS must be aligned based on the SIZE */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull +#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull +#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull +#define CFG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ +#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull /* * for slave UCODE and ENV instored in master memory space, * PHYS must be aligned based on the SIZE */ -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ +#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull +#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull +#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ /* slave core release by master*/ -#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 -#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ +#define CFG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 +#define CFG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ /* * SRIO_PCIE_BOOT - SLAVE */ #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) +#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 +#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ + (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) #endif /* @@ -236,75 +226,68 @@ */ /* controller 1, direct to uli, tgtid 3, Base address 20000 */ -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull +#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CFG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull /* controller 2, Slot 2, tgtid 2, Base address 201000 */ -#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull +#define CFG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#define CFG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#define CFG_SYS_PCIE2_IO_VIRT 0xf8010000 +#define CFG_SYS_PCIE2_IO_PHYS 0xff8010000ull /* controller 3, Slot 1, tgtid 1, Base address 202000 */ -#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull -#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull +#define CFG_SYS_PCIE3_MEM_VIRT 0xc0000000 +#define CFG_SYS_PCIE3_MEM_PHYS 0xc40000000ull /* Qman/Bman */ -#define CONFIG_SYS_BMAN_NUM_PORTALS 10 -#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 +#define CFG_SYS_BMAN_NUM_PORTALS 10 +#define CFG_SYS_BMAN_MEM_BASE 0xf4000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull #else -#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE +#define CFG_SYS_BMAN_MEM_PHYS CFG_SYS_BMAN_MEM_BASE #endif -#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 -#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE -#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ - CONFIG_SYS_BMAN_CENA_SIZE) -#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 -#define CONFIG_SYS_QMAN_NUM_PORTALS 10 -#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 +#define CFG_SYS_BMAN_MEM_SIZE 0x00200000 +#define CFG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE +#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \ + CFG_SYS_BMAN_CENA_SIZE) +#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08 +#define CFG_SYS_QMAN_NUM_PORTALS 10 +#define CFG_SYS_QMAN_MEM_BASE 0xf4200000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull +#define CFG_SYS_QMAN_MEM_PHYS 0xff4200000ull #else -#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE +#define CFG_SYS_QMAN_MEM_PHYS CFG_SYS_QMAN_MEM_BASE #endif -#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 -#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE -#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ - CONFIG_SYS_QMAN_CENA_SIZE) -#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 - -#define CONFIG_SYS_DPAA_FMAN -#define CONFIG_SYS_DPAA_PME +#define CFG_SYS_QMAN_MEM_SIZE 0x00200000 +#define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \ + CFG_SYS_QMAN_CENA_SIZE) +#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08 #ifdef CONFIG_FMAN_ENET -#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2 -#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3 -#define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4 -#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1 -#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0 +#define CFG_SYS_FM1_DTSEC1_PHY_ADDR 0x2 +#define CFG_SYS_FM1_DTSEC2_PHY_ADDR 0x3 +#define CFG_SYS_FM1_DTSEC3_PHY_ADDR 0x4 +#define CFG_SYS_FM1_DTSEC4_PHY_ADDR 0x1 +#define CFG_SYS_FM1_DTSEC5_PHY_ADDR 0x0 -#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c -#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d -#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e -#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f +#define CFG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c +#define CFG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d +#define CFG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e +#define CFG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f -#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0 +#define CFG_SYS_FM1_10GEC1_PHY_ADDR 0 -#define CONFIG_SYS_TBIPA_VALUE 8 +#define CFG_SYS_TBIPA_VALUE 8 #endif #ifdef CONFIG_MMC @@ -320,7 +303,7 @@ * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */ +#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */ /* * Environment Configuration diff --git a/include/configs/SBx81LIFKW.h b/include/configs/SBx81LIFKW.h index 9629d735a27..bad34d9771e 100644 --- a/include/configs/SBx81LIFKW.h +++ b/include/configs/SBx81LIFKW.h @@ -7,15 +7,13 @@ #define _CONFIG_SBX81LIFKW_H /* additions for new ARM relocation support */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 /* * NS16550 Configuration */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK -#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE +#define CFG_SYS_NS16550_CLK CFG_SYS_TCLK +#define CFG_SYS_NS16550_COM1 KW_UART0_BASE /* * Serial Port configuration @@ -34,7 +32,7 @@ * U-Boot bootcode configuration */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/ +#define CFG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/ /* size in bytes reserved for initial data */ diff --git a/include/configs/SBx81LIFXCAT.h b/include/configs/SBx81LIFXCAT.h index 67e42b94c11..9a9663b34ba 100644 --- a/include/configs/SBx81LIFXCAT.h +++ b/include/configs/SBx81LIFXCAT.h @@ -7,15 +7,13 @@ #define _CONFIG_SBX81LIFXCAT_H /* additions for new ARM relocation support */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 /* * NS16550 Configuration */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK -#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE +#define CFG_SYS_NS16550_CLK CFG_SYS_TCLK +#define CFG_SYS_NS16550_COM1 KW_UART0_BASE /* * Serial Port configuration @@ -39,7 +37,7 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/ +#define CFG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/ /* size in bytes reserved for initial data */ diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 62c4177f309..623d4cf5562 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -15,32 +15,32 @@ /* High Level Configuration Options */ -#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS +#define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS #ifdef CONFIG_RAMBOOT_PBL #define RESET_VECTOR_OFFSET 0x27FFC #define BOOT_PAGE_OFFSET 0x27000 #ifdef CONFIG_MTD_RAW_NAND -#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 -#define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 +#define CFG_SYS_NAND_U_BOOT_SIZE (768 << 10) +#define CFG_SYS_NAND_U_BOOT_DST 0x30000000 +#define CFG_SYS_NAND_U_BOOT_START 0x30000000 #endif #ifdef CONFIG_SPIFLASH #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC -#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) +#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) +#define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) +#define CFG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) +#define CFG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) #endif #ifdef CONFIG_SDCARD #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC -#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) -#define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) -#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) +#define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10) +#define CFG_SYS_MMC_U_BOOT_DST (0x30000000) +#define CFG_SYS_MMC_U_BOOT_START (0x30000000) +#define CFG_SYS_MMC_U_BOOT_OFFS (260 << 10) #endif #endif /* CONFIG_RAMBOOT_PBL */ @@ -49,53 +49,51 @@ #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc #endif -/* PCIe Boot - Master */ -#define CONFIG_SRIO_PCIE_BOOT_MASTER /* * for slave u-boot IMAGE instored in master memory space, * PHYS must be aligned based on the SIZE */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ +#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull +#define CFG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull +#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull +#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull #else -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 +#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 +#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 #endif /* * for slave UCODE and ENV instored in master memory space, * PHYS must be aligned based on the SIZE */ #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull +#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull +#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull #else -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 +#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 +#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 #endif -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ +#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ /* slave core release by master*/ -#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 -#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ +#define CFG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 +#define CFG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ /* PCIe Boot - Slave */ #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) +#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 +#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ + (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) /* Set 1M boot space for PCIe boot */ -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000) -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) +#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000) +#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ + (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #endif /* * These can be toggled for performance analysis, otherwise use default. */ -#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E +#define CFG_SYS_INIT_L2CSR0 L2CSR0_L2E #ifdef CONFIG_DDR_ECC #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif @@ -103,107 +101,107 @@ /* * Config the L3 Cache as L3 SRAM */ -#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +#define CFG_SYS_INIT_L3_ADDR 0xFFFC0000 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_DCSRBAR 0xf0000000 -#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull +#define CFG_SYS_DCSRBAR 0xf0000000 +#define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull #endif /* * DDR Setup */ #define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE #if defined(CONFIG_TARGET_T1024RDB) #define SPD_EEPROM_ADDRESS 0x51 -#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ +#define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ #elif defined(CONFIG_TARGET_T1023RDB) -#define CONFIG_SYS_SDRAM_SIZE 2048 +#define CFG_SYS_SDRAM_SIZE 2048 #endif /* * IFC Definitions */ -#define CONFIG_SYS_FLASH_BASE 0xe8000000 +#define CFG_SYS_FLASH_BASE 0xe8000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) +#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE) #else -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE #endif -#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ +#define CFG_SYS_NOR0_CSPR_EXT (0xf) +#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) +#define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) /* NOR Flash Timing Params */ #if defined(CONFIG_TARGET_T1024RDB) -#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 +#define CFG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 #elif defined(CONFIG_TARGET_T1023RDB) -#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \ +#define CFG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \ CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN) #endif -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ +#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ FTIM0_NOR_TEADC(0x5) | \ FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ +#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ FTIM1_NOR_TRAD_NOR(0x1A) |\ FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ +#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ FTIM2_NOR_TCH(0x4) | \ FTIM2_NOR_TWPH(0x0E) | \ FTIM2_NOR_TWP(0x1c)) -#define CONFIG_SYS_NOR_FTIM3 0x0 +#define CFG_SYS_NOR_FTIM3 0x0 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} +#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS} #ifdef CONFIG_TARGET_T1024RDB /* CPLD on IFC */ -#define CONFIG_SYS_CPLD_BASE 0xffdf0000 -#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) -#define CONFIG_SYS_CSPR2_EXT (0xf) -#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ +#define CFG_SYS_CPLD_BASE 0xffdf0000 +#define CFG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CFG_SYS_CPLD_BASE) +#define CFG_SYS_CSPR2_EXT (0xf) +#define CFG_SYS_CSPR2 (CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) -#define CONFIG_SYS_CSOR2 0x0 +#define CFG_SYS_AMASK2 IFC_AMASK(64*1024) +#define CFG_SYS_CSOR2 0x0 /* CPLD Timing parameters for IFC CS2 */ -#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ +#define CFG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ FTIM0_GPCM_TEADC(0x0e) | \ FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ +#define CFG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ FTIM1_GPCM_TRAD(0x1f)) -#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ +#define CFG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ FTIM2_GPCM_TCH(0x8) | \ FTIM2_GPCM_TWP(0x1f)) -#define CONFIG_SYS_CS2_FTIM3 0x0 +#define CFG_SYS_CS2_FTIM3 0x0 #endif /* NAND Flash on IFC */ -#define CONFIG_SYS_NAND_BASE 0xff800000 +#define CFG_SYS_NAND_BASE 0xff800000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) +#define CFG_SYS_NAND_BASE_PHYS (0xf00000000ull | CFG_SYS_NAND_BASE) #else -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE #endif -#define CONFIG_SYS_NAND_CSPR_EXT (0xf) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ +#define CFG_SYS_NAND_CSPR_EXT (0xf) +#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \ | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ | CSPR_MSEL_NAND /* MSEL = NAND */ \ | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) +#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024) #if defined(CONFIG_TARGET_T1024RDB) -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ +#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ @@ -211,7 +209,7 @@ | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ #elif defined(CONFIG_TARGET_T1023RDB) -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ +#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | CSOR_NAND_RAL_3 /* RAL 3Bytes */ \ @@ -221,91 +219,86 @@ #endif /* ONFI NAND Flash mode0 Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ +#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ FTIM0_NAND_TWP(0x18) | \ FTIM0_NAND_TWCHT(0x07) | \ FTIM0_NAND_TWH(0x0a)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ +#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ FTIM1_NAND_TWBE(0x39) | \ FTIM1_NAND_TRR(0x0e) | \ FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ +#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ FTIM2_NAND_TREH(0x0a) | \ FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 +#define CFG_SYS_NAND_FTIM3 0x0 -#define CONFIG_SYS_NAND_DDR_LAW 11 -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #if defined(CONFIG_MTD_RAW_NAND) -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 #else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 #endif -#define CONFIG_HWCONFIG - /* define to use L1 as initial stack */ #define CONFIG_L1_INIT_RAM -#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ +#define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 +#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 /* The assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#define CFG_SYS_INIT_RAM_ADDR_PHYS \ + ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CFG_SYS_INIT_RAM_ADDR_PHYS_LOW) #else -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS +#define CFG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ +#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 +#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR_PHYS #endif -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 +#define CFG_SYS_INIT_RAM_SIZE 0x00004000 -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /* Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) +#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2) -#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) -#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) +#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500) +#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600) +#define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500) +#define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600) /* I2C */ @@ -318,9 +311,7 @@ /* * RTC configuration */ -#define RTC -#define CONFIG_RTC_DS1337 1 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CFG_SYS_I2C_RTC_ADDR 0x68 /* * eSPI - Enhanced SPI @@ -334,26 +325,24 @@ #ifdef CONFIG_PCI /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #ifdef CONFIG_PCIE1 -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull +#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CFG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull #endif /* controller 2, Slot 2, tgtid 2, Base address 201000 */ #ifdef CONFIG_PCIE2 -#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull -#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull +#define CFG_SYS_PCIE2_MEM_VIRT 0x90000000 +#define CFG_SYS_PCIE2_MEM_PHYS 0xc10000000ull +#define CFG_SYS_PCIE2_IO_VIRT 0xf8010000 +#define CFG_SYS_PCIE2_IO_PHYS 0xff8010000ull #endif /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #ifdef CONFIG_PCIE3 -#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull +#define CFG_SYS_PCIE3_MEM_VIRT 0xa0000000 +#define CFG_SYS_PCIE3_MEM_PHYS 0xc20000000ull #endif #endif /* CONFIG_PCI */ @@ -370,40 +359,37 @@ /* Qman/Bman */ #ifndef CONFIG_NOBQFMAN -#define CONFIG_SYS_BMAN_NUM_PORTALS 10 -#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 +#define CFG_SYS_BMAN_NUM_PORTALS 10 +#define CFG_SYS_BMAN_MEM_BASE 0xf4000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull #else -#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE +#define CFG_SYS_BMAN_MEM_PHYS CFG_SYS_BMAN_MEM_BASE #endif -#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE -#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ - CONFIG_SYS_BMAN_CENA_SIZE) -#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 -#define CONFIG_SYS_QMAN_NUM_PORTALS 10 -#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 +#define CFG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CFG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE +#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \ + CFG_SYS_BMAN_CENA_SIZE) +#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08 +#define CFG_SYS_QMAN_NUM_PORTALS 10 +#define CFG_SYS_QMAN_MEM_BASE 0xf6000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull +#define CFG_SYS_QMAN_MEM_PHYS 0xff6000000ull #else -#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE +#define CFG_SYS_QMAN_MEM_PHYS CFG_SYS_QMAN_MEM_BASE #endif -#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE -#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ - CONFIG_SYS_QMAN_CENA_SIZE) -#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 - -#define CONFIG_SYS_DPAA_FMAN +#define CFG_SYS_QMAN_MEM_SIZE 0x02000000 +#define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \ + CFG_SYS_QMAN_CENA_SIZE) +#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08 + #endif /* CONFIG_NOBQFMAN */ #ifdef CONFIG_SYS_DPAA_FMAN @@ -432,7 +418,7 @@ * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ /* * Environment Configuration diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index ad8037e7a8c..b6938056bbe 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -25,29 +25,29 @@ * HDR would be appended at end of image and copied to DDR along * with U-Boot image. */ -#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \ +#define CFG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \ CONFIG_U_BOOT_HDR_SIZE) #else -#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) +#define CFG_SYS_NAND_U_BOOT_SIZE (768 << 10) #endif -#define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 -#define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 +#define CFG_SYS_NAND_U_BOOT_DST 0x30000000 +#define CFG_SYS_NAND_U_BOOT_START 0x30000000 #endif #ifdef CONFIG_SPIFLASH #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC -#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) +#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) +#define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) +#define CFG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) +#define CFG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) #endif #ifdef CONFIG_SDCARD #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC -#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) -#define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) -#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) +#define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10) +#define CFG_SYS_MMC_U_BOOT_DST (0x30000000) +#define CFG_SYS_MMC_U_BOOT_START (0x30000000) +#define CFG_SYS_MMC_U_BOOT_OFFS (260 << 10) #endif #endif @@ -58,12 +58,12 @@ #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc #endif -#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS +#define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS /* * These can be toggled for performance analysis, otherwise use default. */ -#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E +#define CFG_SYS_INIT_L2CSR0 L2CSR0_L2E #ifdef CONFIG_DDR_ECC #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif @@ -71,41 +71,41 @@ /* * Config the L3 Cache as L3 SRAM */ -#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +#define CFG_SYS_INIT_L3_ADDR 0xFFFC0000 /* - * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence - * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address - * (CONFIG_SYS_INIT_L3_VADDR) will be different. + * For Secure Boot CFG_SYS_INIT_L3_ADDR will be redefined and hence + * Physical address (CFG_SYS_INIT_L3_ADDR) and virtual address + * (CFG_SYS_INIT_L3_VADDR) will be different. */ -#define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000 +#define CFG_SYS_INIT_L3_VADDR 0xFFFC0000 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) -#define CONFIG_SYS_DCSRBAR 0xf0000000 -#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull +#define CFG_SYS_DCSRBAR 0xf0000000 +#define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull /* * DDR Setup */ #define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE #define SPD_EEPROM_ADDRESS 0x51 -#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ +#define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ /* * IFC Definitions */ -#define CONFIG_SYS_FLASH_BASE 0xe8000000 -#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) +#define CFG_SYS_FLASH_BASE 0xe8000000 +#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE) -#define CONFIG_SYS_NOR_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ +#define CFG_SYS_NOR_CSPR_EXT (0xf) +#define CFG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) +#define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) /* * TDM Definition @@ -113,22 +113,22 @@ #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 /* NOR Flash Timing Params */ -#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ +#define CFG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 +#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ FTIM0_NOR_TEADC(0x5) | \ FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ +#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ FTIM1_NOR_TRAD_NOR(0x1A) |\ FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ +#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ FTIM2_NOR_TCH(0x4) | \ FTIM2_NOR_TWPH(0x0E) | \ FTIM2_NOR_TWP(0x1c)) -#define CONFIG_SYS_NOR_FTIM3 0x0 +#define CFG_SYS_NOR_FTIM3 0x0 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} +#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS} /* CPLD on IFC */ #define CPLD_LBMAP_MASK 0x3F @@ -157,38 +157,38 @@ #define CPLD_INT_MASK_TDMR2 0x01 #endif -#define CONFIG_SYS_CPLD_BASE 0xffdf0000 -#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) -#define CONFIG_SYS_CSPR2_EXT (0xf) -#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ +#define CFG_SYS_CPLD_BASE 0xffdf0000 +#define CFG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CFG_SYS_CPLD_BASE) +#define CFG_SYS_CSPR2_EXT (0xf) +#define CFG_SYS_CSPR2 (CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE_PHYS) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) -#define CONFIG_SYS_CSOR2 0x0 +#define CFG_SYS_AMASK2 IFC_AMASK(64*1024) +#define CFG_SYS_CSOR2 0x0 /* CPLD Timing parameters for IFC CS2 */ -#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ +#define CFG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ FTIM0_GPCM_TEADC(0x0e) | \ FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ +#define CFG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ FTIM1_GPCM_TRAD(0x1f)) -#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ +#define CFG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ FTIM2_GPCM_TCH(0x8) | \ FTIM2_GPCM_TWP(0x1f)) -#define CONFIG_SYS_CS2_FTIM3 0x0 +#define CFG_SYS_CS2_FTIM3 0x0 /* NAND Flash on IFC */ -#define CONFIG_SYS_NAND_BASE 0xff800000 -#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) +#define CFG_SYS_NAND_BASE 0xff800000 +#define CFG_SYS_NAND_BASE_PHYS (0xf00000000ull | CFG_SYS_NAND_BASE) -#define CONFIG_SYS_NAND_CSPR_EXT (0xf) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ +#define CFG_SYS_NAND_CSPR_EXT (0xf) +#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \ | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ | CSPR_MSEL_NAND /* MSEL = NAND */ \ | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) +#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024) -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ +#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ @@ -197,88 +197,83 @@ | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ /* ONFI NAND Flash mode0 Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ +#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ FTIM0_NAND_TWP(0x18) | \ FTIM0_NAND_TWCHT(0x07) | \ FTIM0_NAND_TWH(0x0a)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ +#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ FTIM1_NAND_TWBE(0x39) | \ FTIM1_NAND_TRR(0x0e) | \ FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ +#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ FTIM2_NAND_TREH(0x0a) | \ FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 +#define CFG_SYS_NAND_FTIM3 0x0 -#define CONFIG_SYS_NAND_DDR_LAW 11 -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #if defined(CONFIG_MTD_RAW_NAND) -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 #else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 #endif -#define CONFIG_HWCONFIG - /* define to use L1 as initial stack */ #define CONFIG_L1_INIT_RAM -#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 +#define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ +#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 /* The assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 +#define CFG_SYS_INIT_RAM_ADDR_PHYS \ + ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CFG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#define CFG_SYS_INIT_RAM_SIZE 0x00004000 -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /* Serial Port - controlled on board with jumper J8 * open - index 2 * shorted - index 1 */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) +#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2) -#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) -#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) +#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500) +#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600) +#define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500) +#define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600) /* I2C bus multiplexer */ #define I2C_MUX_PCA_ADDR 0x70 @@ -290,9 +285,7 @@ /* * RTC configuration */ -#define RTC -#define CONFIG_RTC_DS1337 1 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CFG_SYS_I2C_RTC_ADDR 0x68 /*DVI encoder*/ #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75 @@ -310,34 +303,30 @@ #ifdef CONFIG_PCI /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #ifdef CONFIG_PCIE1 -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull +#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CFG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull #endif /* controller 2, Slot 2, tgtid 2, Base address 201000 */ #ifdef CONFIG_PCIE2 -#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull -#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull +#define CFG_SYS_PCIE2_MEM_VIRT 0x90000000 +#define CFG_SYS_PCIE2_MEM_PHYS 0xc10000000ull +#define CFG_SYS_PCIE2_IO_VIRT 0xf8010000 +#define CFG_SYS_PCIE2_IO_PHYS 0xff8010000ull #endif /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #ifdef CONFIG_PCIE3 -#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull +#define CFG_SYS_PCIE3_MEM_VIRT 0xa0000000 +#define CFG_SYS_PCIE3_MEM_PHYS 0xc20000000ull #endif /* controller 4, Base address 203000 */ #ifdef CONFIG_PCIE4 -#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 -#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull -#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 -#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull +#define CFG_SYS_PCIE4_MEM_VIRT 0xb0000000 +#define CFG_SYS_PCIE4_MEM_PHYS 0xc30000000ull #endif #endif /* CONFIG_PCI */ @@ -351,63 +340,57 @@ /* Qman/Bman */ #ifndef CONFIG_NOBQFMAN -#define CONFIG_SYS_BMAN_NUM_PORTALS 10 -#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 -#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull -#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE -#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ - CONFIG_SYS_BMAN_CENA_SIZE) -#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 -#define CONFIG_SYS_QMAN_NUM_PORTALS 10 -#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 -#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull -#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE -#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ - CONFIG_SYS_QMAN_CENA_SIZE) -#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 - -#define CONFIG_SYS_DPAA_FMAN -#define CONFIG_SYS_DPAA_PME +#define CFG_SYS_BMAN_NUM_PORTALS 10 +#define CFG_SYS_BMAN_MEM_BASE 0xf4000000 +#define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#define CFG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CFG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE +#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \ + CFG_SYS_BMAN_CENA_SIZE) +#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08 +#define CFG_SYS_QMAN_NUM_PORTALS 10 +#define CFG_SYS_QMAN_MEM_BASE 0xf6000000 +#define CFG_SYS_QMAN_MEM_PHYS 0xff6000000ull +#define CFG_SYS_QMAN_MEM_SIZE 0x02000000 +#define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \ + CFG_SYS_QMAN_CENA_SIZE) +#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08 #endif /* CONFIG_NOBQFMAN */ #ifdef CONFIG_FMAN_ENET #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB) -#define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 +#define CFG_SYS_SGMII1_PHY_ADDR 0x03 #elif defined(CONFIG_TARGET_T1040D4RDB) -#define CONFIG_SYS_SGMII1_PHY_ADDR 0x01 +#define CFG_SYS_SGMII1_PHY_ADDR 0x01 #elif defined(CONFIG_TARGET_T1042D4RDB) -#define CONFIG_SYS_SGMII1_PHY_ADDR 0x02 -#define CONFIG_SYS_SGMII2_PHY_ADDR 0x03 -#define CONFIG_SYS_SGMII3_PHY_ADDR 0x01 +#define CFG_SYS_SGMII1_PHY_ADDR 0x02 +#define CFG_SYS_SGMII2_PHY_ADDR 0x03 +#define CFG_SYS_SGMII3_PHY_ADDR 0x01 #endif #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB) -#define CONFIG_SYS_RGMII1_PHY_ADDR 0x04 -#define CONFIG_SYS_RGMII2_PHY_ADDR 0x05 +#define CFG_SYS_RGMII1_PHY_ADDR 0x04 +#define CFG_SYS_RGMII2_PHY_ADDR 0x05 #else -#define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 -#define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 +#define CFG_SYS_RGMII1_PHY_ADDR 0x01 +#define CFG_SYS_RGMII2_PHY_ADDR 0x02 #endif /* Enable VSC9953 L2 Switch driver on T1040 SoC */ #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB) -#define CONFIG_VSC9953 #ifdef CONFIG_TARGET_T1040RDB -#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 -#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 +#define CFG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 +#define CFG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 #else -#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08 -#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c +#define CFG_SYS_FM1_QSGMII11_PHY_ADDR 0x08 +#define CFG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c #endif #endif #endif @@ -421,7 +404,7 @@ * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ /* * Dynamic MTD Partition support with mtdparts diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 2dcaeda78b8..a93e05dd4d2 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -14,50 +14,44 @@ #include <linux/stringify.h> #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ -#if defined(CONFIG_ARCH_T2080) -#define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */ -#define CONFIG_SRIO1 /* SRIO port 1 */ -#define CONFIG_SRIO2 /* SRIO port 2 */ -#endif /* High Level Configuration Options */ -#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS +#define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS #ifdef CONFIG_RAMBOOT_PBL #define RESET_VECTOR_OFFSET 0x27FFC #define BOOT_PAGE_OFFSET 0x27000 #ifdef CONFIG_MTD_RAW_NAND -#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 -#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 +#define CFG_SYS_NAND_U_BOOT_SIZE (768 << 10) +#define CFG_SYS_NAND_U_BOOT_DST 0x00200000 +#define CFG_SYS_NAND_U_BOOT_START 0x00200000 #endif #ifdef CONFIG_SPIFLASH #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC -#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) +#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) +#define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) +#define CFG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) +#define CFG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) #endif #ifdef CONFIG_SDCARD #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC -#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) -#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) -#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) +#define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10) +#define CFG_SYS_MMC_U_BOOT_DST (0x00200000) +#define CFG_SYS_MMC_U_BOOT_START (0x00200000) +#define CFG_SYS_MMC_U_BOOT_OFFS (260 << 10) #endif #endif /* CONFIG_RAMBOOT_PBL */ -#define CONFIG_SRIO_PCIE_BOOT_MASTER #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE /* Set 1M boot space */ -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000) -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) +#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000) +#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ + (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #endif @@ -75,19 +69,19 @@ /* * Config the L3 Cache as L3 SRAM */ -#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +#define CFG_SYS_INIT_L3_ADDR 0xFFFC0000 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) -#define CONFIG_SYS_DCSRBAR 0xf0000000 -#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull +#define CFG_SYS_DCSRBAR 0xf0000000 +#define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull /* * DDR Setup */ #define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ +#define CFG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 @@ -96,39 +90,39 @@ /* * IFC Definitions */ -#define CONFIG_SYS_FLASH_BASE 0xe0000000 -#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ +#define CFG_SYS_FLASH_BASE 0xe0000000 +#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE) +#define CFG_SYS_NOR0_CSPR_EXT (0xf) +#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS \ + 0x8000000) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR1_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ +#define CFG_SYS_NOR1_CSPR_EXT (0xf) +#define CFG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) +#define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) /* NOR Flash Timing Params */ -#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 +#define CFG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ +#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ FTIM0_NOR_TEADC(0x5) | \ FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ +#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ FTIM1_NOR_TRAD_NOR(0x1A) |\ FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ +#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ FTIM2_NOR_TCH(0x4) | \ FTIM2_NOR_TWPH(0x0E) | \ FTIM2_NOR_TWP(0x1c)) -#define CONFIG_SYS_NOR_FTIM3 0x0 +#define CFG_SYS_NOR_FTIM3 0x0 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ - + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} +#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS \ + + 0x8000000, CFG_SYS_FLASH_BASE_PHYS} #define QIXIS_BASE 0xffdf0000 #define QIXIS_LBMAP_SWITCH 6 @@ -147,36 +141,36 @@ #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) -#define CONFIG_SYS_CSPR3_EXT (0xf) -#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ +#define CFG_SYS_CSPR3_EXT (0xf) +#define CFG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) -#define CONFIG_SYS_CSOR3 0x0 +#define CFG_SYS_AMASK3 IFC_AMASK(64 * 1024) +#define CFG_SYS_CSOR3 0x0 /* QIXIS Timing parameters for IFC CS3 */ -#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ +#define CFG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ FTIM0_GPCM_TEADC(0x0e) | \ FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ +#define CFG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ FTIM1_GPCM_TRAD(0x3f)) -#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ +#define CFG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ FTIM2_GPCM_TCH(0x8) | \ FTIM2_GPCM_TWP(0x1f)) -#define CONFIG_SYS_CS3_FTIM3 0x0 +#define CFG_SYS_CS3_FTIM3 0x0 /* NAND Flash on IFC */ -#define CONFIG_SYS_NAND_BASE 0xff800000 -#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) +#define CFG_SYS_NAND_BASE 0xff800000 +#define CFG_SYS_NAND_BASE_PHYS (0xf00000000ull | CFG_SYS_NAND_BASE) -#define CONFIG_SYS_NAND_CSPR_EXT (0xf) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ +#define CFG_SYS_NAND_CSPR_EXT (0xf) +#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \ | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ | CSPR_MSEL_NAND /* MSEL = NAND */ \ | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) +#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024) -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ +#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ @@ -185,100 +179,95 @@ | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ /* ONFI NAND Flash mode0 Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ +#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ FTIM0_NAND_TWP(0x18) | \ FTIM0_NAND_TWCHT(0x07) | \ FTIM0_NAND_TWH(0x0a)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ +#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ FTIM1_NAND_TWBE(0x39) | \ FTIM1_NAND_TRR(0x0e) | \ FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ +#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ FTIM2_NAND_TREH(0x0a) | \ FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 +#define CFG_SYS_NAND_FTIM3 0x0 -#define CONFIG_SYS_NAND_DDR_LAW 11 -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #if defined(CONFIG_MTD_RAW_NAND) -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NOR1_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NOR1_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 #else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR1_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 #endif -#define CONFIG_HWCONFIG - /* define to use L1 as initial stack */ #define CONFIG_L1_INIT_RAM -#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 +#define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ +#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 /* The assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CFG_SYS_INIT_RAM_ADDR_PHYS \ + ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CFG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#define CFG_SYS_INIT_RAM_SIZE 0x00004000 +#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /* * Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) -#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2) +#define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) -#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) +#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500) +#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600) +#define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500) +#define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600) /* * I2C @@ -304,39 +293,39 @@ /* * RapidIO */ -#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 -#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull -#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_SYS_SRIO1_MEM_VIRT 0xa0000000 +#define CFG_SYS_SRIO1_MEM_PHYS 0xc20000000ull +#define CFG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_SYS_SRIO2_MEM_VIRT 0xb0000000 +#define CFG_SYS_SRIO2_MEM_PHYS 0xc30000000ull +#define CFG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ /* * for slave u-boot IMAGE instored in master memory space, * PHYS must be aligned based on the SIZE */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull +#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull +#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull +#define CFG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ +#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull /* * for slave UCODE and ENV instored in master memory space, * PHYS must be aligned based on the SIZE */ -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ +#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull +#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull +#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ /* slave core release by master*/ -#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 -#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ +#define CFG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 +#define CFG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ /* * SRIO_PCIE_BOOT - SLAVE */ #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) +#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 +#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ + (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) #endif /* @@ -348,60 +337,49 @@ * Memory space is mapped 1-1, but I/O space must start from 0. */ /* controller 1, direct to uli, tgtid 3, Base address 20000 */ -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull +#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CFG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull /* controller 2, Slot 2, tgtid 2, Base address 201000 */ -#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull +#define CFG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#define CFG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#define CFG_SYS_PCIE2_IO_VIRT 0xf8010000 +#define CFG_SYS_PCIE2_IO_PHYS 0xff8010000ull /* controller 3, Slot 1, tgtid 1, Base address 202000 */ -#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull -#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull +#define CFG_SYS_PCIE3_MEM_VIRT 0xb0000000 +#define CFG_SYS_PCIE3_MEM_PHYS 0xc30000000ull /* controller 4, Base address 203000 */ -#define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 -#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull -#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull +#define CFG_SYS_PCIE4_MEM_VIRT 0xc0000000 +#define CFG_SYS_PCIE4_MEM_PHYS 0xc40000000ull /* Qman/Bman */ #ifndef CONFIG_NOBQFMAN -#define CONFIG_SYS_BMAN_NUM_PORTALS 18 -#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 -#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull -#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE -#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ - CONFIG_SYS_BMAN_CENA_SIZE) -#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 -#define CONFIG_SYS_QMAN_NUM_PORTALS 18 -#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 -#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull -#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE -#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ - CONFIG_SYS_QMAN_CENA_SIZE) -#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 - -#define CONFIG_SYS_DPAA_FMAN -#define CONFIG_SYS_DPAA_PME -#define CONFIG_SYS_PMAN -#define CONFIG_SYS_DPAA_DCE -#define CONFIG_SYS_DPAA_RMAN /* RMan */ +#define CFG_SYS_BMAN_NUM_PORTALS 18 +#define CFG_SYS_BMAN_MEM_BASE 0xf4000000 +#define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#define CFG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CFG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE +#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \ + CFG_SYS_BMAN_CENA_SIZE) +#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08 +#define CFG_SYS_QMAN_NUM_PORTALS 18 +#define CFG_SYS_QMAN_MEM_BASE 0xf6000000 +#define CFG_SYS_QMAN_MEM_PHYS 0xff6000000ull +#define CFG_SYS_QMAN_MEM_SIZE 0x02000000 +#define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \ + CFG_SYS_QMAN_CENA_SIZE) +#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08 #endif /* CONFIG_NOBQFMAN */ #ifdef CONFIG_SYS_DPAA_FMAN @@ -438,7 +416,7 @@ * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ /* * Environment Configuration diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 223c8567517..cf65a0da188 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -17,42 +17,41 @@ /* High Level Configuration Options */ -#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS +#define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS #ifdef CONFIG_RAMBOOT_PBL #define RESET_VECTOR_OFFSET 0x27FFC #define BOOT_PAGE_OFFSET 0x27000 #ifdef CONFIG_MTD_RAW_NAND -#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 -#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 +#define CFG_SYS_NAND_U_BOOT_SIZE (768 << 10) +#define CFG_SYS_NAND_U_BOOT_DST 0x00200000 +#define CFG_SYS_NAND_U_BOOT_START 0x00200000 #endif #ifdef CONFIG_SPIFLASH #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC -#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) +#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) +#define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) +#define CFG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) +#define CFG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) #endif #ifdef CONFIG_SDCARD #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC -#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) -#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) -#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) +#define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10) +#define CFG_SYS_MMC_U_BOOT_DST (0x00200000) +#define CFG_SYS_MMC_U_BOOT_START (0x00200000) +#define CFG_SYS_MMC_U_BOOT_OFFS (260 << 10) #endif #endif /* CONFIG_RAMBOOT_PBL */ -#define CONFIG_SRIO_PCIE_BOOT_MASTER #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE /* Set 1M boot space */ -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000) -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) +#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000) +#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ + (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #endif @@ -70,19 +69,19 @@ /* * Config the L3 Cache as L3 SRAM */ -#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +#define CFG_SYS_INIT_L3_ADDR 0xFFFC0000 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) -#define CONFIG_SYS_DCSRBAR 0xf0000000 -#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull +#define CFG_SYS_DCSRBAR 0xf0000000 +#define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull /* * DDR Setup */ #define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ +#define CFG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 @@ -91,68 +90,68 @@ /* * IFC Definitions */ -#define CONFIG_SYS_FLASH_BASE 0xe8000000 -#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ +#define CFG_SYS_FLASH_BASE 0xe8000000 +#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE) +#define CFG_SYS_NOR0_CSPR_EXT (0xf) +#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) +#define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) /* NOR Flash Timing Params */ -#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 +#define CFG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ +#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ FTIM0_NOR_TEADC(0x5) | \ FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ +#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ FTIM1_NOR_TRAD_NOR(0x1A) |\ FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ +#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ FTIM2_NOR_TCH(0x4) | \ FTIM2_NOR_TWPH(0x0E) | \ FTIM2_NOR_TWP(0x1c)) -#define CONFIG_SYS_NOR_FTIM3 0x0 +#define CFG_SYS_NOR_FTIM3 0x0 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS } +#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS } /* CPLD on IFC */ -#define CONFIG_SYS_CPLD_BASE 0xffdf0000 -#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) -#define CONFIG_SYS_CSPR2_EXT (0xf) -#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ +#define CFG_SYS_CPLD_BASE 0xffdf0000 +#define CFG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CFG_SYS_CPLD_BASE) +#define CFG_SYS_CSPR2_EXT (0xf) +#define CFG_SYS_CSPR2 (CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) -#define CONFIG_SYS_CSOR2 0x0 +#define CFG_SYS_AMASK2 IFC_AMASK(64*1024) +#define CFG_SYS_CSOR2 0x0 /* CPLD Timing parameters for IFC CS2 */ -#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ +#define CFG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ FTIM0_GPCM_TEADC(0x0e) | \ FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ +#define CFG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ FTIM1_GPCM_TRAD(0x1f)) -#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ +#define CFG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ FTIM2_GPCM_TCH(0x8) | \ FTIM2_GPCM_TWP(0x1f)) -#define CONFIG_SYS_CS2_FTIM3 0x0 +#define CFG_SYS_CS2_FTIM3 0x0 /* NAND Flash on IFC */ -#define CONFIG_SYS_NAND_BASE 0xff800000 -#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) +#define CFG_SYS_NAND_BASE 0xff800000 +#define CFG_SYS_NAND_BASE_PHYS (0xf00000000ull | CFG_SYS_NAND_BASE) -#define CONFIG_SYS_NAND_CSPR_EXT (0xf) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ +#define CFG_SYS_NAND_CSPR_EXT (0xf) +#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \ | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ | CSPR_MSEL_NAND /* MSEL = NAND */ \ | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) +#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024) -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ +#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ @@ -161,84 +160,79 @@ | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ /* ONFI NAND Flash mode0 Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ +#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ FTIM0_NAND_TWP(0x18) | \ FTIM0_NAND_TWCHT(0x07) | \ FTIM0_NAND_TWH(0x0a)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ +#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ FTIM1_NAND_TWBE(0x39) | \ FTIM1_NAND_TRR(0x0e) | \ FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ +#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ FTIM2_NAND_TREH(0x0a) | \ FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 +#define CFG_SYS_NAND_FTIM3 0x0 -#define CONFIG_SYS_NAND_DDR_LAW 11 -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #if defined(CONFIG_MTD_RAW_NAND) -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 #else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 #endif -#define CONFIG_HWCONFIG - /* define to use L1 as initial stack */ #define CONFIG_L1_INIT_RAM -#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 +#define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ +#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 /* The assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CFG_SYS_INIT_RAM_ADDR_PHYS \ + ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CFG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#define CFG_SYS_INIT_RAM_SIZE 0x00004000 +#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /* * Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) -#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2) +#define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) -#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) +#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500) +#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600) +#define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500) +#define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600) /* * I2C @@ -258,39 +252,39 @@ /* * RapidIO */ -#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 -#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull -#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_SYS_SRIO1_MEM_VIRT 0xa0000000 +#define CFG_SYS_SRIO1_MEM_PHYS 0xc20000000ull +#define CFG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_SYS_SRIO2_MEM_VIRT 0xb0000000 +#define CFG_SYS_SRIO2_MEM_PHYS 0xc30000000ull +#define CFG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ /* * for slave u-boot IMAGE instored in master memory space, * PHYS must be aligned based on the SIZE */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull +#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull +#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull +#define CFG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ +#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull /* * for slave UCODE and ENV instored in master memory space, * PHYS must be aligned based on the SIZE */ -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ +#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull +#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull +#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ /* slave core release by master*/ -#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 -#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ +#define CFG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 +#define CFG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ /* * SRIO_PCIE_BOOT - SLAVE */ #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) +#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 +#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ + (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) #endif /* @@ -302,60 +296,49 @@ * Memory space is mapped 1-1, but I/O space must start from 0. */ /* controller 1, direct to uli, tgtid 3, Base address 20000 */ -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull +#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CFG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull /* controller 2, Slot 2, tgtid 2, Base address 201000 */ -#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull +#define CFG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#define CFG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#define CFG_SYS_PCIE2_IO_VIRT 0xf8010000 +#define CFG_SYS_PCIE2_IO_PHYS 0xff8010000ull /* controller 3, Slot 1, tgtid 1, Base address 202000 */ -#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull -#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull +#define CFG_SYS_PCIE3_MEM_VIRT 0xb0000000 +#define CFG_SYS_PCIE3_MEM_PHYS 0xc30000000ull /* controller 4, Base address 203000 */ -#define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 -#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull -#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull +#define CFG_SYS_PCIE4_MEM_VIRT 0xc0000000 +#define CFG_SYS_PCIE4_MEM_PHYS 0xc40000000ull /* Qman/Bman */ #ifndef CONFIG_NOBQFMAN -#define CONFIG_SYS_BMAN_NUM_PORTALS 18 -#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 -#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull -#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE -#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ - CONFIG_SYS_BMAN_CENA_SIZE) -#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 -#define CONFIG_SYS_QMAN_NUM_PORTALS 18 -#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 -#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull -#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE -#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ - CONFIG_SYS_QMAN_CENA_SIZE) -#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 - -#define CONFIG_SYS_DPAA_FMAN -#define CONFIG_SYS_DPAA_PME -#define CONFIG_SYS_PMAN -#define CONFIG_SYS_DPAA_DCE -#define CONFIG_SYS_DPAA_RMAN /* RMan */ +#define CFG_SYS_BMAN_NUM_PORTALS 18 +#define CFG_SYS_BMAN_MEM_BASE 0xf4000000 +#define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#define CFG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CFG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE +#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \ + CFG_SYS_BMAN_CENA_SIZE) +#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08 +#define CFG_SYS_QMAN_NUM_PORTALS 18 +#define CFG_SYS_QMAN_MEM_BASE 0xf6000000 +#define CFG_SYS_QMAN_MEM_PHYS 0xff6000000ull +#define CFG_SYS_QMAN_MEM_SIZE 0x02000000 +#define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \ + CFG_SYS_QMAN_CENA_SIZE) +#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08 #endif /* CONFIG_NOBQFMAN */ #ifdef CONFIG_SYS_DPAA_FMAN @@ -399,7 +382,7 @@ * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ /* * Environment Configuration diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 12edfdd68db..b51762264ad 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -24,10 +24,10 @@ #ifdef CONFIG_SDCARD #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC -#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 -#define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 -#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) +#define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10) +#define CFG_SYS_MMC_U_BOOT_DST 0x00200000 +#define CFG_SYS_MMC_U_BOOT_START 0x00200000 +#define CFG_SYS_MMC_U_BOOT_OFFS (260 << 10) #endif #endif @@ -39,7 +39,7 @@ #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc #endif -#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS +#define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS /* * These can be toggled for performance analysis, otherwise use default. @@ -51,55 +51,51 @@ /* * Config the L3 Cache as L3 SRAM */ -#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +#define CFG_SYS_INIT_L3_ADDR 0xFFFC0000 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) -#define CONFIG_SYS_DCSRBAR 0xf0000000 -#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull +#define CFG_SYS_DCSRBAR 0xf0000000 +#define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull /* * DDR Setup */ #define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE /* * IFC Definitions */ -#define CONFIG_SYS_FLASH_BASE 0xe0000000 -#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) - -#define CONFIG_HWCONFIG +#define CFG_SYS_FLASH_BASE 0xe0000000 +#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE) /* define to use L1 as initial stack */ #define CONFIG_L1_INIT_RAM -#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 +#define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ +#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 /* The assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 +#define CFG_SYS_INIT_RAM_ADDR_PHYS \ + ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CFG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#define CFG_SYS_INIT_RAM_SIZE 0x00004000 -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /* Serial Port - controlled on board with jumper J8 * open - index 2 * shorted - index 1 */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) +#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2) -#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) -#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) +#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500) +#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600) +#define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500) +#define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600) /* I2C */ @@ -109,27 +105,24 @@ */ /* controller 1, direct to uli, tgtid 3, Base address 20000 */ -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull +#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CFG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull /* controller 2, Slot 2, tgtid 2, Base address 201000 */ -#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull +#define CFG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#define CFG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#define CFG_SYS_PCIE2_IO_VIRT 0xf8010000 +#define CFG_SYS_PCIE2_IO_PHYS 0xff8010000ull /* controller 3, Slot 1, tgtid 1, Base address 202000 */ -#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull -#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull +#define CFG_SYS_PCIE3_MEM_VIRT 0xc0000000 +#define CFG_SYS_PCIE3_MEM_PHYS 0xc40000000ull /* controller 4, Base address 203000 */ -#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull -#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull +#define CFG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CFG_SYS_PCIE4_MEM_PHYS 0xc60000000ull /* * Miscellaneous configurable options @@ -140,7 +133,7 @@ * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ /* * Environment Configuration @@ -159,57 +152,55 @@ #define SPD_EEPROM_ADDRESS2 0x54 #define SPD_EEPROM_ADDRESS3 0x56 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ -#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ +#define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ /* * IFC Definitions */ -#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ +#define CFG_SYS_NOR0_CSPR_EXT (0xf) +#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS \ + 0x8000000) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR1_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ +#define CFG_SYS_NOR1_CSPR_EXT (0xf) +#define CFG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) +#define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) /* NOR Flash Timing Params */ -#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 +#define CFG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ +#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ FTIM0_NOR_TEADC(0x5) | \ FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ +#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ FTIM1_NOR_TRAD_NOR(0x1A) |\ FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ +#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ FTIM2_NOR_TCH(0x4) | \ FTIM2_NOR_TWPH(0x0E) | \ FTIM2_NOR_TWP(0x1c)) -#define CONFIG_SYS_NOR_FTIM3 0x0 +#define CFG_SYS_NOR_FTIM3 0x0 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ - + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} +#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS \ + + 0x8000000, CFG_SYS_FLASH_BASE_PHYS} /* NAND Flash on IFC */ -#define CONFIG_SYS_NAND_MAX_ECCPOS 256 -#define CONFIG_SYS_NAND_MAX_OOBFREE 2 -#define CONFIG_SYS_NAND_BASE 0xff800000 -#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) +#define CFG_SYS_NAND_BASE 0xff800000 +#define CFG_SYS_NAND_BASE_PHYS (0xf00000000ull | CFG_SYS_NAND_BASE) -#define CONFIG_SYS_NAND_CSPR_EXT (0xf) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ +#define CFG_SYS_NAND_CSPR_EXT (0xf) +#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \ | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ | CSPR_MSEL_NAND /* MSEL = NAND */ \ | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) +#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024) -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ +#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ @@ -218,88 +209,87 @@ | CSOR_NAND_PB(128)) /*Page Per Block = 128*/ /* ONFI NAND Flash mode0 Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ +#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ FTIM0_NAND_TWP(0x18) | \ FTIM0_NAND_TWCHT(0x07) | \ FTIM0_NAND_TWH(0x0a)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ +#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ FTIM1_NAND_TWBE(0x39) | \ FTIM1_NAND_TRR(0x0e) | \ FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ +#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ FTIM2_NAND_TREH(0x0a) | \ FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 +#define CFG_SYS_NAND_FTIM3 0x0 -#define CONFIG_SYS_NAND_DDR_LAW 11 -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #if defined(CONFIG_MTD_RAW_NAND) -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 #else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 #endif -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NOR1_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NOR1_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 /* CPLD on IFC */ -#define CONFIG_SYS_CPLD_BASE 0xffdf0000 -#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) -#define CONFIG_SYS_CSPR3_EXT (0xf) -#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ +#define CFG_SYS_CPLD_BASE 0xffdf0000 +#define CFG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CFG_SYS_CPLD_BASE) +#define CFG_SYS_CSPR3_EXT (0xf) +#define CFG_SYS_CSPR3 (CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE_PHYS) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) -#define CONFIG_SYS_CSOR3 0x0 +#define CFG_SYS_AMASK3 IFC_AMASK(64 * 1024) +#define CFG_SYS_CSOR3 0x0 /* CPLD Timing parameters for IFC CS3 */ -#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ +#define CFG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ FTIM0_GPCM_TEADC(0x0e) | \ FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ +#define CFG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ FTIM1_GPCM_TRAD(0x1f)) -#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ +#define CFG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ FTIM2_GPCM_TCH(0x8) | \ FTIM2_GPCM_TWP(0x1f)) -#define CONFIG_SYS_CS3_FTIM3 0x0 +#define CFG_SYS_CS3_FTIM3 0x0 /* I2C */ #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ @@ -326,36 +316,28 @@ /* Qman/Bman */ #ifndef CONFIG_NOBQFMAN -#define CONFIG_SYS_BMAN_NUM_PORTALS 50 -#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 -#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull -#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE -#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ - CONFIG_SYS_BMAN_CENA_SIZE) -#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 -#define CONFIG_SYS_QMAN_NUM_PORTALS 50 -#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 -#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull -#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE -#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ - CONFIG_SYS_QMAN_CENA_SIZE) -#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 - -#define CONFIG_SYS_DPAA_FMAN -#define CONFIG_SYS_DPAA_PME -#define CONFIG_SYS_PMAN -#define CONFIG_SYS_DPAA_DCE -#define CONFIG_SYS_DPAA_RMAN +#define CFG_SYS_BMAN_NUM_PORTALS 50 +#define CFG_SYS_BMAN_MEM_BASE 0xf4000000 +#define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#define CFG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CFG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE +#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \ + CFG_SYS_BMAN_CENA_SIZE) +#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08 +#define CFG_SYS_QMAN_NUM_PORTALS 50 +#define CFG_SYS_QMAN_MEM_BASE 0xf6000000 +#define CFG_SYS_QMAN_MEM_PHYS 0xff6000000ull +#define CFG_SYS_QMAN_MEM_SIZE 0x02000000 +#define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \ + CFG_SYS_QMAN_CENA_SIZE) +#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08 #endif /* CONFIG_NOBQFMAN */ #ifdef CONFIG_SYS_DPAA_FMAN diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 8eefaf24b28..755f7fae3e4 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -158,20 +158,17 @@ #endif /* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ -#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ -#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ -#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ -#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ -#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ - -/* PMIC support */ -#define CONFIG_POWER_TPS65910 +#define CFG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ +#define CFG_SYS_NS16550_COM2 0x48022000 /* UART1 */ +#define CFG_SYS_NS16550_COM3 0x48024000 /* UART2 */ +#define CFG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ +#define CFG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ +#define CFG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ #ifdef CONFIG_MTD_RAW_NAND /* NAND: device related configs */ /* NAND: driver related configs */ -#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ +#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 10, 11, 12, 13, 14, 15, 16, 17, \ 18, 19, 20, 21, 22, 23, 24, 25, \ 26, 27, 28, 29, 30, 31, 32, 33, \ @@ -179,8 +176,8 @@ 42, 43, 44, 45, 46, 47, 48, 49, \ 50, 51, 52, 53, 54, 55, 56, 57, } -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 14 +#define CFG_SYS_NAND_ECCSIZE 512 +#define CFG_SYS_NAND_ECCBYTES 14 #endif /* !CONFIG_MTD_RAW_NAND */ /* USB Device Firmware Update support */ @@ -205,8 +202,8 @@ * 0x4C0000 - 0xFFFFFF : Userland (11 MiB + 256 KiB) */ #if defined(CONFIG_NOR) -#define CONFIG_SYS_FLASH_BASE (0x08000000) -#define CONFIG_SYS_FLASH_SIZE 0x01000000 +#define CFG_SYS_FLASH_BASE (0x08000000) +#define CFG_SYS_FLASH_SIZE 0x01000000 #endif /* NOR support */ #endif /* ! __CONFIG_AM335X_EVM_H */ diff --git a/include/configs/am335x_guardian.h b/include/configs/am335x_guardian.h index 7fa1847c1fc..7c5e7ce475e 100644 --- a/include/configs/am335x_guardian.h +++ b/include/configs/am335x_guardian.h @@ -83,15 +83,15 @@ #define CONSOLE_COLOR_RED 0x001F /* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ -#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ -#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ -#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ -#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ -#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ +#define CFG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ +#define CFG_SYS_NS16550_COM2 0x48022000 /* UART1 */ +#define CFG_SYS_NS16550_COM3 0x48024000 /* UART2 */ +#define CFG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ +#define CFG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ +#define CFG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ #ifdef CONFIG_MTD_RAW_NAND -#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ +#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \ 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \ 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, \ @@ -113,8 +113,8 @@ 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, \ 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, \ } -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 26 +#define CFG_SYS_NAND_ECCSIZE 512 +#define CFG_SYS_NAND_ECCBYTES 26 #define MTDIDS_DEFAULT "nand0=nand.0" #endif /* CONFIG_MTD_RAW_NAND */ diff --git a/include/configs/am335x_igep003x.h b/include/configs/am335x_igep003x.h index 3952783ee1a..abd868c1453 100644 --- a/include/configs/am335x_igep003x.h +++ b/include/configs/am335x_igep003x.h @@ -88,14 +88,14 @@ "echo WARNING: Could not determine device tree to use; fi; \0" /* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ +#define CFG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ /* Ethernet support */ /* NAND support */ /* NAND config */ -#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ +#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 10, 11, 12, 13, 14, 15, 16, 17, \ 18, 19, 20, 21, 22, 23, 24, 25, \ 26, 27, 28, 29, 30, 31, 32, 33, \ @@ -103,7 +103,7 @@ 42, 43, 44, 45, 46, 47, 48, 49, \ 50, 51, 52, 53, 54, 55, 56, 57, } -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 14 +#define CFG_SYS_NAND_ECCSIZE 512 +#define CFG_SYS_NAND_ECCBYTES 14 #endif /* ! __CONFIG_IGEP003X_H */ diff --git a/include/configs/am335x_shc.h b/include/configs/am335x_shc.h index 08bae9b886f..452887d6995 100644 --- a/include/configs/am335x_shc.h +++ b/include/configs/am335x_shc.h @@ -136,11 +136,11 @@ #endif /* Regular Boot */ /* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ -#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ -#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ -#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ -#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ -#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ +#define CFG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ +#define CFG_SYS_NS16550_COM2 0x48022000 /* UART1 */ +#define CFG_SYS_NS16550_COM3 0x48024000 /* UART2 */ +#define CFG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ +#define CFG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ +#define CFG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ #endif /* ! __CONFIG_AM335X_SHC_H */ diff --git a/include/configs/am335x_sl50.h b/include/configs/am335x_sl50.h index 7df5f140551..342a068c855 100644 --- a/include/configs/am335x_sl50.h +++ b/include/configs/am335x_sl50.h @@ -36,18 +36,11 @@ BOOTENV /* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ -#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ -#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ -#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ -#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ -#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ - -/* PMIC support */ -#define CONFIG_POWER_TPS65910 - -/* SPL */ - -/* Network. */ +#define CFG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ +#define CFG_SYS_NS16550_COM2 0x48022000 /* UART1 */ +#define CFG_SYS_NS16550_COM3 0x48024000 /* UART2 */ +#define CFG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ +#define CFG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ +#define CFG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ #endif /* ! __CONFIG_AM335X_SL50_H */ diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index e0f5f2b0440..c57a0ddc21d 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -16,18 +16,16 @@ /* Board NAND Info. */ #ifdef CONFIG_MTD_RAW_NAND -#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, 10, \ +#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, 10, \ 11, 12, 13, 14, 16, 17, 18, 19, 20, \ 21, 22, 23, 24, 25, 26, 27, 28, 30, \ 31, 32, 33, 34, 35, 36, 37, 38, 39, \ 40, 41, 42, 44, 45, 46, 47, 48, 49, \ 50, 51, 52, 53, 54, 55, 56 } -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 13 -#define CONFIG_SYS_NAND_MAX_OOBFREE 2 -#define CONFIG_SYS_NAND_MAX_ECCPOS 56 -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_NAND_ECCSIZE 512 +#define CFG_SYS_NAND_ECCBYTES 13 +#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE /* NAND block size is 128 KiB. Synchronize these values with * corresponding Device Tree entries in Linux: * MLO(SPL) 4 * NAND_BLOCK_SIZE = 512 KiB @ 0x000000 @@ -91,7 +89,7 @@ /* on one chip */ #if defined(CONFIG_MTD_RAW_NAND) -#define CONFIG_SYS_FLASH_BASE NAND_BASE +#define CFG_SYS_FLASH_BASE NAND_BASE #endif #endif /* __CONFIG_H */ diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index fc82a8c003e..7659c1cc061 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -9,27 +9,15 @@ #define __CONFIG_AM43XX_EVM_H #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 21) /* 2GB */ -#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ +#define CFG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ #include <asm/arch/omap.h> /* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_CLK 48000000 -#if !defined(CONFIG_SPL_DM) || !defined(CONFIG_DM_SERIAL) -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_SERIAL -#endif - -/* I2C Configuration */ - -/* Power */ -#define CONFIG_POWER_TPS65218 -#define CONFIG_POWER_TPS62362 - -/* SPL defines. */ +#define CFG_SYS_NS16550_CLK 48000000 /* Enabling L2 Cache */ -#define CONFIG_SYS_PL310_BASE 0x48242000 +#define CFG_SYS_PL310_BASE 0x48242000 /* * When building U-Boot such that there is no previous loader @@ -45,7 +33,7 @@ #define V_SCLK (V_OSCK) /* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ +#define CFG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ #ifndef CONFIG_SPL_BUILD /* USB Device Firmware Update support */ @@ -120,7 +108,7 @@ #ifdef CONFIG_MTD_RAW_NAND /* NAND: device related configs */ /* NAND: driver related configs */ -#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ +#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \ 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \ 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, \ @@ -142,8 +130,8 @@ 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, \ 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, \ } -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 26 +#define CFG_SYS_NAND_ECCSIZE 512 +#define CFG_SYS_NAND_ECCBYTES 26 #define NANDARGS \ "nandargs=setenv bootargs console=${console} " \ "${optargs} " \ diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h index d8b0531673f..dacfd41cced 100644 --- a/include/configs/am57xx_evm.h +++ b/include/configs/am57xx_evm.h @@ -14,13 +14,9 @@ #include <environment/ti/dfu.h> #include <linux/sizes.h> -#define CONFIG_IODELAY_RECALIBRATION - -#define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */ -#define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ -#define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ - -#define CONFIG_SYS_OMAP_ABE_SYSCK +#define CFG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */ +#define CFG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ +#define CFG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ #ifndef CONFIG_SPL_BUILD #define DFUARGS \ @@ -55,9 +51,9 @@ * 0x1E0000 - 0x9E0000 : QSPI.kernel (8MiB) * 0x9E0000 - 0x2000000 : USERLAND */ -#define CONFIG_SYS_SPI_KERNEL_OFFS 0x1E0000 -#define CONFIG_SYS_SPI_ARGS_OFFS 0x140000 -#define CONFIG_SYS_SPI_ARGS_SIZE 0x80000 +#define CFG_SYS_SPI_KERNEL_OFFS 0x1E0000 +#define CFG_SYS_SPI_ARGS_OFFS 0x140000 +#define CFG_SYS_SPI_ARGS_SIZE 0x80000 /* SPI SPL */ diff --git a/include/configs/am62x_evm.h b/include/configs/am62x_evm.h index 78201adc07f..57f3f37908d 100644 --- a/include/configs/am62x_evm.h +++ b/include/configs/am62x_evm.h @@ -13,7 +13,7 @@ #include <environment/ti/mmc.h> /* DDR Configuration */ -#define CONFIG_SYS_SDRAM_BASE1 0x880000000 +#define CFG_SYS_SDRAM_BASE1 0x880000000 #define PARTS_DEFAULT \ /* Linux partitions */ \ diff --git a/include/configs/am64x_evm.h b/include/configs/am64x_evm.h index 140940730d0..25c71f00a20 100644 --- a/include/configs/am64x_evm.h +++ b/include/configs/am64x_evm.h @@ -16,7 +16,7 @@ #include <environment/ti/k3_dfu.h> /* DDR Configuration */ -#define CONFIG_SYS_SDRAM_BASE1 0x880000000 +#define CFG_SYS_SDRAM_BASE1 0x880000000 #define PARTS_DEFAULT \ /* Linux partitions */ \ diff --git a/include/configs/am65x_evm.h b/include/configs/am65x_evm.h index 0345160787e..0307426e4ab 100644 --- a/include/configs/am65x_evm.h +++ b/include/configs/am65x_evm.h @@ -15,7 +15,7 @@ #include <environment/ti/k3_dfu.h> /* DDR Configuration */ -#define CONFIG_SYS_SDRAM_BASE1 0x880000000 +#define CFG_SYS_SDRAM_BASE1 0x880000000 #define PARTS_DEFAULT \ /* Linux partitions */ \ diff --git a/include/configs/amcore.h b/include/configs/amcore.h index 2bda66fe033..ee0be972d24 100644 --- a/include/configs/amcore.h +++ b/include/configs/amcore.h @@ -10,7 +10,7 @@ #define CONFIG_HOSTNAME "AMCORE" -#define CONFIG_SYS_UART_PORT 0 +#define CFG_SYS_UART_PORT 0 #define CONFIG_EXTRA_ENV_SETTINGS \ "upgrade_uboot=loady; " \ @@ -24,21 +24,21 @@ "erase 0xfff00000 0xffffffff; " \ "cp.b 0x20000 0xfff00000 ${filesize}\0" -#define CONFIG_SYS_CLK 45000000 -#define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 2) +#define CFG_SYS_CLK 45000000 +#define CFG_SYS_CPU_CLK (CFG_SYS_CLK * 2) /* Register Base Addrs */ -#define CONFIG_SYS_MBAR 0x10000000 +#define CFG_SYS_MBAR 0x10000000 /* Definitions for initial stack pointer and data area (in DPRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 +#define CFG_SYS_INIT_RAM_ADDR 0x20000000 /* size of internal SRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 +#define CFG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_SIZE 0x1000000 -#define CONFIG_SYS_FLASH_BASE 0xffc00000 +#define CFG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_SIZE 0x1000000 +#define CFG_SYS_FLASH_BASE 0xffc00000 /* amcore design has flash data bytes wired swapped */ -#define CONFIG_SYS_WRITE_SWAPPED_DATA +#define CFG_SYS_WRITE_SWAPPED_DATA /* reserve 128-4KB */ #define LDS_BOARD_TEXT \ @@ -46,7 +46,7 @@ env/embedded.o(.text*); /* memory map space for linux boot data */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) +#define CFG_SYS_BOOTMAPSZ (8 << 20) /* * Cache Configuration @@ -56,25 +56,25 @@ * sdram - single region - no masks */ -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) -#define CONFIG_SYS_CACHE_ACR0 (CF_ACR_CM_WT | CF_ACR_SM_ALL | \ +#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 4) +#define CFG_SYS_ICACHE_INV (CF_CACR_CINVA) +#define CFG_SYS_CACHE_ACR0 (CF_ACR_CM_WT | CF_ACR_SM_ALL | \ CF_ACR_EN) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_DCM_P | CF_CACR_ESB | \ +#define CFG_SYS_CACHE_ICACR (CF_CACR_DCM_P | CF_CACR_ESB | \ CF_CACR_EC) /* CS0 - AMD Flash, address 0xffc00000 */ -#define CONFIG_SYS_CS0_BASE (CONFIG_SYS_FLASH_BASE>>16) +#define CFG_SYS_CS0_BASE (CFG_SYS_FLASH_BASE>>16) /* 4MB, AA=0,V=1 C/I BIT for errata */ -#define CONFIG_SYS_CS0_MASK 0x003f0001 +#define CFG_SYS_CS0_MASK 0x003f0001 /* WS=10, AA=1, PS=16bit (10) */ -#define CONFIG_SYS_CS0_CTRL 0x1980 +#define CFG_SYS_CS0_CTRL 0x1980 /* CS1 - DM9000 Ethernet Controller, address 0x30000000 */ -#define CONFIG_SYS_CS1_BASE 0x3000 -#define CONFIG_SYS_CS1_MASK 0x00070001 -#define CONFIG_SYS_CS1_CTRL 0x0100 +#define CFG_SYS_CS1_BASE 0x3000 +#define CFG_SYS_CS1_MASK 0x00070001 +#define CFG_SYS_CS1_CTRL 0x0100 #endif /* __AMCORE_CONFIG_H */ diff --git a/include/configs/ap121.h b/include/configs/ap121.h index 650140bb724..9c6f76383de 100644 --- a/include/configs/ap121.h +++ b/include/configs/ap121.h @@ -6,10 +6,10 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 +#define CFG_SYS_INIT_RAM_ADDR 0xbd000000 +#define CFG_SYS_INIT_RAM_SIZE 0x8000 /* Miscellaneous configurable options */ diff --git a/include/configs/ap143.h b/include/configs/ap143.h index 0eed8db23bd..034cd7a7cdf 100644 --- a/include/configs/ap143.h +++ b/include/configs/ap143.h @@ -6,15 +6,15 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 +#define CFG_SYS_INIT_RAM_ADDR 0xbd000000 +#define CFG_SYS_INIT_RAM_SIZE 0x2000 /* * Serial Port */ -#define CONFIG_SYS_NS16550_CLK 25000000 +#define CFG_SYS_NS16550_CLK 25000000 /* Miscellaneous configurable options */ diff --git a/include/configs/ap152.h b/include/configs/ap152.h index 71247111190..c56b35150a5 100644 --- a/include/configs/ap152.h +++ b/include/configs/ap152.h @@ -6,15 +6,15 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 +#define CFG_SYS_INIT_RAM_ADDR 0xbd000000 +#define CFG_SYS_INIT_RAM_SIZE 0x2000 /* * Serial Port */ -#define CONFIG_SYS_NS16550_CLK 25000000 +#define CFG_SYS_NS16550_CLK 25000000 /* Miscellaneous configurable options */ diff --git a/include/configs/apalis-imx8.h b/include/configs/apalis-imx8.h index e2e491bdb0a..cf23837863b 100644 --- a/include/configs/apalis-imx8.h +++ b/include/configs/apalis-imx8.h @@ -63,7 +63,7 @@ /* On Apalis iMX8 USDHC1 is eMMC, USDHC2 is 8-bit and USDHC3 is 4-bit MMC/SD */ #define CFG_SYS_FSL_USDHC_NUM 3 -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_2 0x880000000 #define PHYS_SDRAM_1_SIZE SZ_2G /* 2 GB */ diff --git a/include/configs/apalis-tk1.h b/include/configs/apalis-tk1.h index 6a4092a83e2..f0a02ae1795 100644 --- a/include/configs/apalis-tk1.h +++ b/include/configs/apalis-tk1.h @@ -14,7 +14,7 @@ /* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTA -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE #define FDT_MODULE "apalis-v1.2" #define FDT_MODULE_V1_0 "apalis" diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h index 192c9cf0c30..a3c86545f07 100644 --- a/include/configs/apalis_imx6.h +++ b/include/configs/apalis_imx6.h @@ -15,10 +15,6 @@ #include <asm/arch/imx-regs.h> #include <asm/mach-imx/gpio.h> -#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - #define CONFIG_MXC_UART_BASE UART1_BASE /* MMC Configs */ @@ -36,8 +32,6 @@ #define CONFIG_USBD_HS /* Framebuffer and LCD */ -#define CONFIG_IMX_HDMI -#define CONFIG_IMX_VIDEO_SKIP /* Command definition */ @@ -110,8 +104,8 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE #endif /* __CONFIG_H */ diff --git a/include/configs/apalis_t30.h b/include/configs/apalis_t30.h index 84bd88f835a..4f00b3bad3f 100644 --- a/include/configs/apalis_t30.h +++ b/include/configs/apalis_t30.h @@ -21,7 +21,7 @@ * Apalis UART4: NVIDIA UARTC */ #define CONFIG_TEGRA_ENABLE_UARTA -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE #define UBOOT_UPDATE \ "uboot_hwpart=1\0" \ diff --git a/include/configs/arbel.h b/include/configs/arbel.h index f7deba4f566..60758b0ca02 100644 --- a/include/configs/arbel.h +++ b/include/configs/arbel.h @@ -6,10 +6,10 @@ #ifndef __CONFIG_ARBEL_H #define __CONFIG_ARBEL_H -#define CONFIG_SYS_SDRAM_BASE 0x0 -#define CONFIG_SYS_BOOTMAPSZ (20 << 20) -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 +#define CFG_SYS_SDRAM_BASE 0x0 +#define CFG_SYS_BOOTMAPSZ (20 << 20) +#define CFG_SYS_INIT_RAM_ADDR CFG_SYS_SDRAM_BASE +#define CFG_SYS_INIT_RAM_SIZE 0x8000 /* Default environemnt variables */ #define CONFIG_EXTRA_ENV_SETTINGS "uimage_flash_addr=80200000\0" \ diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index 1f2b3b58ca6..6faf544d21b 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -20,7 +20,7 @@ #endif /* Framebuffer */ -#define CONFIG_SYS_LDB_CLOCK 28341000 +#define CFG_SYS_LDB_CLOCK 28341000 #include "mx6_common.h" @@ -30,8 +30,6 @@ #define CONFIG_FEC_MXC_PHYADDR 0 -#define CONFIG_SYS_SPI_ST_ENABLE_WP_PIN - #ifdef CONFIG_IMX_HAB #define HAB_EXTRA_SETTINGS \ "hab_check_addr=" \ @@ -408,9 +406,9 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE #define CFG_SYS_FSL_USDHC_NUM 2 @@ -422,12 +420,6 @@ /* UBI support */ -/* Framebuffer */ -/* check this console not needed, after test remove it */ -#define CONFIG_IMX_VIDEO_SKIP - -#define CONFIG_IMX6_PWM_PER_CLK 66000000 - #define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mw,serial#:sw,board_type:sw," \ "sysnum:dw,panel:sw,ipaddr:iw,serverip:iw" diff --git a/include/configs/aspeed-common.h b/include/configs/aspeed-common.h index 5c9005805e1..bb1bd50838a 100644 --- a/include/configs/aspeed-common.h +++ b/include/configs/aspeed-common.h @@ -14,14 +14,14 @@ /* Misc CPU related */ -#define CONFIG_SYS_SDRAM_BASE ASPEED_DRAM_BASE +#define CFG_SYS_SDRAM_BASE ASPEED_DRAM_BASE #ifdef CONFIG_PRE_CON_BUF_SZ -#define CONFIG_SYS_INIT_RAM_ADDR (ASPEED_SRAM_BASE + CONFIG_PRE_CON_BUF_SZ) -#define CONFIG_SYS_INIT_RAM_SIZE (ASPEED_SRAM_SIZE - CONFIG_PRE_CON_BUF_SZ) +#define CFG_SYS_INIT_RAM_ADDR (ASPEED_SRAM_BASE + CONFIG_PRE_CON_BUF_SZ) +#define CFG_SYS_INIT_RAM_SIZE (ASPEED_SRAM_SIZE - CONFIG_PRE_CON_BUF_SZ) #else -#define CONFIG_SYS_INIT_RAM_ADDR (ASPEED_SRAM_BASE) -#define CONFIG_SYS_INIT_RAM_SIZE (ASPEED_SRAM_SIZE) +#define CFG_SYS_INIT_RAM_ADDR (ASPEED_SRAM_BASE) +#define CFG_SYS_INIT_RAM_SIZE (ASPEED_SRAM_SIZE) #endif /* diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h index 58635df149b..62aa99342a0 100644 --- a/include/configs/astro_mcf5373l.h +++ b/include/configs/astro_mcf5373l.h @@ -55,29 +55,19 @@ * interface etc. */ -#define CONFIG_SYS_CLK 80000000 -#define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 3) -#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ +#define CFG_SYS_CLK 80000000 +#define CFG_SYS_CPU_CLK (CFG_SYS_CLK * 3) +#define CFG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ /* * Define baudrate for UART1 (console output, tftp, ...) * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud - * CONFIG_SYS_BAUDRATE_TABLE defines values that can be selected + * CFG_SYS_BAUDRATE_TABLE defines values that can be selected * in u-boot command interface */ -#define CONFIG_SYS_UART_PORT (2) -#define CONFIG_SYS_UART2_ALT3_GPIO - -/* - * Watchdog configuration; Watchdog is disabled for running from RAM - * and set to highest possible value else. Beware there is no check - * in the watchdog code to validate the timeout value set here! - */ - -#ifndef CONFIG_MONITOR_IS_IN_RAM -#define CONFIG_WATCHDOG_TIMEOUT 3355 /* timeout in milliseconds */ -#endif +#define CFG_SYS_UART_PORT (2) +#define CFG_SYS_UART2_ALT3_GPIO /* * Configuration for environment @@ -125,7 +115,7 @@ * it needs non-blocking CFI routines. */ -#define CONFIG_SYS_FPGA_WAIT 1000 +#define CFG_SYS_FPGA_WAIT 1000 /* End of user parameters to be customized */ @@ -139,26 +129,26 @@ /* Base register address */ -#define CONFIG_SYS_MBAR 0xFC000000 /* Register Base Addrs */ +#define CFG_SYS_MBAR 0xFC000000 /* Register Base Addrs */ /* System Conf. Reg. & System Protection Reg. */ -#define CONFIG_SYS_SCR 0x0003; -#define CONFIG_SYS_SPR 0xffff; +#define CFG_SYS_SCR 0x0003; +#define CFG_SYS_SPR 0xffff; /* * Definitions for initial stack pointer and data area (in internal SRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 -#define CONFIG_SYS_INIT_RAM_CTRL 0x221 +#define CFG_SYS_INIT_RAM_ADDR 0x80000000 +#define CFG_SYS_INIT_RAM_SIZE 0x8000 +#define CFG_SYS_INIT_RAM_CTRL 0x221 /* * Start addresses for the final memory configuration * (Set up by the startup code) * for MCF5373, the allowable range is 0x40000000 to 0x7FF00000 */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 /* * Chipselect bank definitions @@ -170,23 +160,23 @@ * CS4 - unused * CS5 - unused */ -#define CONFIG_SYS_CS0_BASE 0 -#define CONFIG_SYS_CS0_MASK 0x00ff0001 -#define CONFIG_SYS_CS0_CTRL 0x00001fc0 +#define CFG_SYS_CS0_BASE 0 +#define CFG_SYS_CS0_MASK 0x00ff0001 +#define CFG_SYS_CS0_CTRL 0x00001fc0 -#define CONFIG_SYS_CS1_BASE 0x01000000 -#define CONFIG_SYS_CS1_MASK 0x00ff0001 -#define CONFIG_SYS_CS1_CTRL 0x00001fc0 +#define CFG_SYS_CS1_BASE 0x01000000 +#define CFG_SYS_CS1_MASK 0x00ff0001 +#define CFG_SYS_CS1_CTRL 0x00001fc0 -#define CONFIG_SYS_CS2_BASE 0x20000000 -#define CONFIG_SYS_CS2_MASK 0x00ff0001 -#define CONFIG_SYS_CS2_CTRL 0x0000fec0 +#define CFG_SYS_CS2_BASE 0x20000000 +#define CFG_SYS_CS2_MASK 0x00ff0001 +#define CFG_SYS_CS2_CTRL 0x0000fec0 -#define CONFIG_SYS_CS3_BASE 0x21000000 -#define CONFIG_SYS_CS3_MASK 0x00ff0001 -#define CONFIG_SYS_CS3_CTRL 0x0000fec0 +#define CFG_SYS_CS3_BASE 0x21000000 +#define CFG_SYS_CS3_MASK 0x00ff0001 +#define CFG_SYS_CS3_CTRL 0x0000fec0 -#define CONFIG_SYS_FLASH_BASE 0x00000000 +#define CFG_SYS_FLASH_BASE 0x00000000 /* Reserve 256 kB for Monitor */ @@ -195,12 +185,12 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \ - (CONFIG_SYS_SDRAM_SIZE << 20)) +#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + \ + (CFG_SYS_SDRAM_SIZE << 20)) /* FLASH organization */ -#define CONFIG_SYS_FLASH_SIZE 0x2000000 +#define CFG_SYS_FLASH_SIZE 0x2000000 #define LDS_BOARD_TEXT \ . = DEFINED(env_offset) ? env_offset : .; \ @@ -208,15 +198,15 @@ /* Cache Configuration */ -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ +#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 4) +#define CFG_SYS_ICACHE_INV (CF_CACR_CINVA) +#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ +#define CFG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ CF_CACR_DCM_P) #endif /* _CONFIG_ASTRO_MCF5373L_H */ diff --git a/include/configs/at91-sama5_common.h b/include/configs/at91-sama5_common.h index 4631acfd664..4aa876a9f79 100644 --- a/include/configs/at91-sama5_common.h +++ b/include/configs/at91-sama5_common.h @@ -12,7 +12,7 @@ #include <linux/kconfig.h> /* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 +#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ #endif diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index d51da9d5067..b9cc7ba974d 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -24,34 +24,33 @@ */ /* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* main clock xtal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ +#define CFG_SYS_AT91_MAIN_CLOCK 18432000 /* main clock xtal */ /* * SDRAM: 1 bank, min 32, max 128 MB * Initialized before u-boot gets started. */ -#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 -#define CONFIG_SYS_SDRAM_SIZE 0x04000000 +#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1 +#define CFG_SYS_SDRAM_SIZE 0x04000000 -#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024) +#define CFG_SYS_INIT_RAM_SIZE (16 * 1024) #ifdef CONFIG_AT91SAM9XE -# define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM +# define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM #else -# define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 +# define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 #endif /* NAND flash */ #ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 -#define CONFIG_SYS_NAND_DBW_8 -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13 +#define CFG_SYS_NAND_BASE ATMEL_BASE_CS3 +#define CFG_SYS_NAND_MASK_ALE (1 << 21) +#define CFG_SYS_NAND_MASK_CLE (1 << 22) +#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 +#define CFG_SYS_NAND_READY_PIN AT91_PIN_PC13 #endif /* USB */ -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9260_UHP_BASE */ +#define CFG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9260_UHP_BASE */ #endif diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h index 5dc8f21a853..56247e390bf 100644 --- a/include/configs/at91sam9261ek.h +++ b/include/configs/at91sam9261ek.h @@ -11,27 +11,26 @@ #define __CONFIG_H /* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ +#define CFG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ #include <asm/hardware.h> /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x04000000 -#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024) -#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE 0x04000000 +#define CFG_SYS_INIT_RAM_SIZE (16 * 1024) +#define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM /* NAND flash */ #ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_DBW_8 +#define CFG_SYS_NAND_BASE 0x40000000 /* our ALE is AD22 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 22) +#define CFG_SYS_NAND_MASK_ALE (1 << 22) /* our CLE is AD21 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 21) -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC15 +#define CFG_SYS_NAND_MASK_CLE (1 << 21) +#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 +#define CFG_SYS_NAND_READY_PIN AT91_PIN_PC15 #endif @@ -43,6 +42,6 @@ #define CONFIG_DM9000_NO_SROM /* USB */ -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9261_UHP_BASE */ +#define CFG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9261_UHP_BASE */ #endif diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index d31a7742a17..afdb74785f8 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -19,20 +19,20 @@ #include <asm/hardware.h> /* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 +#define CFG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 -#define CONFIG_SYS_SDRAM_SIZE 0x04000000 +#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1 +#define CFG_SYS_SDRAM_SIZE 0x04000000 -#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024) -#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 +#define CFG_SYS_INIT_RAM_SIZE (16 * 1024) +#define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 /* NOR flash, if populated */ #ifdef CONFIG_SYS_USE_NORFLASH #define PHYS_FLASH_1 0x10000000 -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CFG_SYS_FLASH_BASE PHYS_FLASH_1 /* Address and size of Primary Environment Sector */ @@ -50,9 +50,9 @@ #define MASTER_PLL_OUT 3 /* clocks */ -#define CONFIG_SYS_MOR_VAL \ +#define CFG_SYS_MOR_VAL \ (AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255)) -#define CONFIG_SYS_PLLAR_VAL \ +#define CFG_SYS_PLLAR_VAL \ (AT91_PMC_PLLAR_29 | \ AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \ AT91_PMC_PLLXR_PLLCOUNT(63) | \ @@ -60,31 +60,31 @@ AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV)) /* PCK/2 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR1_VAL \ +#define CFG_SYS_MCKR1_VAL \ (AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 | \ AT91_PMC_MCKR_MDIV_2) /* PCK/2 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR2_VAL \ +#define CFG_SYS_MCKR2_VAL \ (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \ AT91_PMC_MCKR_MDIV_2) /* define PDC[31:16] as DATA[31:16] */ -#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 +#define CFG_SYS_PIOD_PDR_VAL1 0xFFFF0000 /* no pull-up for D[31:16] */ -#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 +#define CFG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ -#define CONFIG_SYS_MATRIX_EBICSA_VAL \ +#define CFG_SYS_MATRIX_EBICSA_VAL \ (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \ AT91_MATRIX_CSA_EBI_CS1A) /* SDRAM */ /* SDRAMC_MR Mode register */ -#define CONFIG_SYS_SDRC_MR_VAL1 0 +#define CFG_SYS_SDRC_MR_VAL1 0 /* SDRAMC_TR - Refresh Timer register */ -#define CONFIG_SYS_SDRC_TR_VAL1 0x13C +#define CFG_SYS_SDRC_TR_VAL1 0x13C /* SDRAMC_CR - Configuration register*/ -#define CONFIG_SYS_SDRC_CR_VAL \ +#define CFG_SYS_SDRC_CR_VAL \ (AT91_SDRAMC_NC_9 | \ AT91_SDRAMC_NR_13 | \ AT91_SDRAMC_NB_4 | \ @@ -98,47 +98,47 @@ (1 << 28)) /* Exit Self Refresh to Active Delay */ /* Memory Device Register -> SDRAM */ -#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM -#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE -#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH -#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR -#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL -#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ -#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM +#define CFG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE +#define CFG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH +#define CFG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR +#define CFG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL +#define CFG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ +#define CFG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ -#define CONFIG_SYS_SMC0_SETUP0_VAL \ +#define CFG_SYS_SMC0_SETUP0_VAL \ (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) -#define CONFIG_SYS_SMC0_PULSE0_VAL \ +#define CFG_SYS_SMC0_PULSE0_VAL \ (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) -#define CONFIG_SYS_SMC0_CYCLE0_VAL \ +#define CFG_SYS_SMC0_CYCLE0_VAL \ (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) -#define CONFIG_SYS_SMC0_MODE0_VAL \ +#define CFG_SYS_SMC0_MODE0_VAL \ (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ AT91_SMC_MODE_DBW_16 | \ AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6)) /* user reset enable */ -#define CONFIG_SYS_RSTC_RMR_VAL \ +#define CFG_SYS_RSTC_RMR_VAL \ (AT91_RSTC_KEY | \ AT91_RSTC_MR_URSTEN | \ AT91_RSTC_MR_ERSTL(15)) /* Disable Watchdog */ -#define CONFIG_SYS_WDTC_WDMR_VAL \ +#define CFG_SYS_WDTC_WDMR_VAL \ (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ AT91_WDT_MR_WDV(0xfff) | \ AT91_WDT_MR_WDDIS | \ @@ -150,17 +150,16 @@ /* NAND flash */ #ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 -#define CONFIG_SYS_NAND_DBW_8 1 +#define CFG_SYS_NAND_BASE ATMEL_BASE_CS3 /* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +#define CFG_SYS_NAND_MASK_ALE (1 << 21) /* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22 +#define CFG_SYS_NAND_MASK_CLE (1 << 22) +#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15 +#define CFG_SYS_NAND_READY_PIN AT91_PIN_PA22 #endif /* USB */ -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ +#define CFG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ #endif diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h index 01085476a43..2ceb8067d58 100644 --- a/include/configs/at91sam9m10g45ek.h +++ b/include/configs/at91sam9m10g45ek.h @@ -11,40 +11,39 @@ #define __CONFIG_H /* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 +#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x70000000 -#define CONFIG_SYS_SDRAM_SIZE 0x08000000 +#define CFG_SYS_SDRAM_BASE 0x70000000 +#define CFG_SYS_SDRAM_SIZE 0x08000000 /* NAND flash */ #ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 -#define CONFIG_SYS_NAND_DBW_8 +#define CFG_SYS_NAND_BASE ATMEL_BASE_CS3 /* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +#define CFG_SYS_NAND_MASK_ALE (1 << 21) /* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8 +#define CFG_SYS_NAND_MASK_CLE (1 << 22) +#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 +#define CFG_SYS_NAND_READY_PIN AT91_PIN_PC8 #endif #ifdef CONFIG_SD_BOOT #elif CONFIG_NAND_BOOT -#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000 +#define CFG_SYS_NAND_U_BOOT_SIZE 0x80000 -#define CONFIG_SYS_NAND_ECCSIZE 256 -#define CONFIG_SYS_NAND_ECCBYTES 3 -#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ +#define CFG_SYS_NAND_ECCSIZE 256 +#define CFG_SYS_NAND_ECCBYTES 3 +#define CFG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ 48, 49, 50, 51, 52, 53, 54, 55, \ 56, 57, 58, 59, 60, 61, 62, 63, } #endif -#define CONFIG_SYS_MASTER_CLOCK 132096000 -#define CONFIG_SYS_AT91_PLLA 0x20c73f03 -#define CONFIG_SYS_MCKR 0x1301 -#define CONFIG_SYS_MCKR_CSS 0x1302 +#define CFG_SYS_MASTER_CLOCK 132096000 +#define CFG_SYS_AT91_PLLA 0x20c73f03 +#define CFG_SYS_MCKR 0x1301 +#define CFG_SYS_MCKR_CSS 0x1302 #endif diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h index 00f57749ad4..0f9e2cfb582 100644 --- a/include/configs/at91sam9n12ek.h +++ b/include/configs/at91sam9n12ek.h @@ -10,22 +10,22 @@ #define __AT91SAM9N12_CONFIG_H_ /* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 16000000 /* main clock xtal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ +#define CFG_SYS_AT91_MAIN_CLOCK 16000000 /* main clock xtal */ /* Misc CPU related */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x08000000 +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE 0x08000000 /* DataFlash */ /* NAND flash */ #ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(4) -#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PD(5) +#define CFG_SYS_NAND_BASE 0x40000000 +#define CFG_SYS_NAND_MASK_ALE (1 << 21) +#define CFG_SYS_NAND_MASK_CLE (1 << 22) +#define CFG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(4) +#define CFG_SYS_NAND_READY_PIN GPIO_PIN_PD(5) #endif #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -35,9 +35,9 @@ /* SPL */ -#define CONFIG_SYS_MASTER_CLOCK 132096000 -#define CONFIG_SYS_AT91_PLLA 0x20953f03 -#define CONFIG_SYS_MCKR 0x1301 -#define CONFIG_SYS_MCKR_CSS 0x1302 +#define CFG_SYS_MASTER_CLOCK 132096000 +#define CFG_SYS_AT91_PLLA 0x20953f03 +#define CFG_SYS_MCKR 0x1301 +#define CFG_SYS_MCKR_CSS 0x1302 #endif diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h index c60c248b747..cad00f647b6 100644 --- a/include/configs/at91sam9rlek.h +++ b/include/configs/at91sam9rlek.h @@ -13,26 +13,25 @@ #include <asm/hardware.h> /* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* main clock xtal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ +#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* main clock xtal */ /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 -#define CONFIG_SYS_SDRAM_SIZE 0x04000000 +#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1 +#define CFG_SYS_SDRAM_SIZE 0x04000000 -#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024) -#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM +#define CFG_SYS_INIT_RAM_SIZE (16 * 1024) +#define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM /* NAND flash */ #ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 -#define CONFIG_SYS_NAND_DBW_8 1 +#define CFG_SYS_NAND_BASE ATMEL_BASE_CS3 /* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +#define CFG_SYS_NAND_MASK_ALE (1 << 21) /* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PB6 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD17 +#define CFG_SYS_NAND_MASK_CLE (1 << 22) +#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PB6 +#define CFG_SYS_NAND_READY_PIN AT91_PIN_PD17 #endif diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h index 71a2863bfc2..509c458e5fa 100644 --- a/include/configs/at91sam9x5ek.h +++ b/include/configs/at91sam9x5ek.h @@ -9,8 +9,8 @@ #define __CONFIG_H__ /* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 +#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ /* general purpose I/O */ @@ -20,28 +20,27 @@ */ /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */ +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */ /* DataFlash */ /* NAND flash */ #ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_DBW_8 1 +#define CFG_SYS_NAND_BASE 0x40000000 /* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +#define CFG_SYS_NAND_MASK_ALE (1 << 21) /* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5 +#define CFG_SYS_NAND_MASK_CLE (1 << 22) +#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4 +#define CFG_SYS_NAND_READY_PIN AT91_PIN_PD5 #endif /* SPL */ -#define CONFIG_SYS_MASTER_CLOCK 132096000 -#define CONFIG_SYS_AT91_PLLA 0x20c73f03 -#define CONFIG_SYS_MCKR 0x1301 -#define CONFIG_SYS_MCKR_CSS 0x1302 +#define CFG_SYS_MASTER_CLOCK 132096000 +#define CFG_SYS_AT91_PLLA 0x20c73f03 +#define CFG_SYS_MCKR 0x1301 +#define CFG_SYS_MCKR_CSS 0x1302 #endif diff --git a/include/configs/ax25-ae350.h b/include/configs/ax25-ae350.h index cf5125fdfa6..03e04e6e680 100644 --- a/include/configs/ax25-ae350.h +++ b/include/configs/ax25-ae350.h @@ -28,30 +28,26 @@ (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */ #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_0 /* * Serial console configuration */ -#define CONFIG_SYS_NS16550_SERIAL -#ifndef CONFIG_DM_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#endif -#define CONFIG_SYS_NS16550_CLK 19660800 +#define CFG_SYS_NS16550_CLK 19660800 /* Init Stack Pointer */ /* support JEDEC */ #define PHYS_FLASH_1 0x88000000 /* BANK 0 */ -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, } +#define CFG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CFG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, } /* max number of memory banks */ /* * There are 4 banks supported for this Controller, * but we have only 1 bank connected to flash on board */ -#define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000} +#define CFG_SYS_FLASH_BANKS_SIZES {0x4000000} /* max number of sectors on one chip */ #define CONFIG_FLASH_SECTOR_SIZE (0x10000*2) @@ -67,7 +63,7 @@ */ /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) +#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Increase max gunzip size */ /* Support autoboot from RAM (kernel image is loaded via debug port) */ diff --git a/include/configs/axs10x.h b/include/configs/axs10x.h index f2357b5785a..04dc50b1cb2 100644 --- a/include/configs/axs10x.h +++ b/include/configs/axs10x.h @@ -19,16 +19,14 @@ * Memory configuration */ -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SDRAM_SIZE SZ_512M +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_SIZE SZ_512M /* * UART configuration */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_CLK 33333333 -#define CONFIG_SYS_NS16550_MEM32 +#define CFG_SYS_NS16550_CLK 33333333 /* * Ethernet PHY configuration diff --git a/include/configs/baltos.h b/include/configs/baltos.h index f4161d7a6de..6f6552e6dc3 100644 --- a/include/configs/baltos.h +++ b/include/configs/baltos.h @@ -181,21 +181,18 @@ /*DFUARGS*/ /* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ -#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ -#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ -#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ -#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ -#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ - -/* PMIC support */ -#define CONFIG_POWER_TPS65910 +#define CFG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ +#define CFG_SYS_NS16550_COM2 0x48022000 /* UART1 */ +#define CFG_SYS_NS16550_COM3 0x48024000 /* UART2 */ +#define CFG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ +#define CFG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ +#define CFG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ /* SPL */ #ifndef CONFIG_NOR_BOOT #ifdef CONFIG_MTD_RAW_NAND -#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ +#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 10, 11, 12, 13, 14, 15, 16, 17, \ 18, 19, 20, 21, 22, 23, 24, 25, \ 26, 27, 28, 29, 30, 31, 32, 33, \ @@ -203,9 +200,9 @@ 42, 43, 44, 45, 46, 47, 48, 49, \ 50, 51, 52, 53, 54, 55, 56, 57, } -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 14 -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_NAND_ECCSIZE 512 +#define CFG_SYS_NAND_ECCBYTES 14 +#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE #endif #endif diff --git a/include/configs/bcm7260.h b/include/configs/bcm7260.h index 1bae49e15f3..43edc91b101 100644 --- a/include/configs/bcm7260.h +++ b/include/configs/bcm7260.h @@ -10,9 +10,9 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_NS16550_COM1 0xf040c000 +#define CFG_SYS_NS16550_COM1 0xf040c000 -#define CONFIG_SYS_INIT_RAM_ADDR 0x10200000 +#define CFG_SYS_INIT_RAM_ADDR 0x10200000 #include "bcmstb.h" diff --git a/include/configs/bcm7445.h b/include/configs/bcm7445.h index 4b41dc220b1..114337294e0 100644 --- a/include/configs/bcm7445.h +++ b/include/configs/bcm7445.h @@ -10,9 +10,9 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_NS16550_COM1 0xf040ab00 +#define CFG_SYS_NS16550_COM1 0xf040ab00 -#define CONFIG_SYS_INIT_RAM_ADDR 0x80200000 +#define CFG_SYS_INIT_RAM_ADDR 0x80200000 #include "bcmstb.h" diff --git a/include/configs/bcm947622.h b/include/configs/bcm947622.h index d0c46a2c823..b02ed1bfe0e 100644 --- a/include/configs/bcm947622.h +++ b/include/configs/bcm947622.h @@ -6,7 +6,7 @@ #ifndef __BCM947622_H #define __BCM947622_H -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 #define COUNTER_FREQUENCY 50000000 #endif diff --git a/include/configs/bcm94908.h b/include/configs/bcm94908.h index 1346ace4bf6..246feb66b29 100644 --- a/include/configs/bcm94908.h +++ b/include/configs/bcm94908.h @@ -6,6 +6,6 @@ #ifndef __BCM94908_H #define __BCM94908_H -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 #endif diff --git a/include/configs/bcm94912.h b/include/configs/bcm94912.h index f3d17ddaacf..c428b1ab578 100644 --- a/include/configs/bcm94912.h +++ b/include/configs/bcm94912.h @@ -6,6 +6,6 @@ #ifndef __BCM94912_H #define __BCM94912_H -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 #endif diff --git a/include/configs/bcm963138.h b/include/configs/bcm963138.h index 361569a8c5f..c61acf6b86b 100644 --- a/include/configs/bcm963138.h +++ b/include/configs/bcm963138.h @@ -6,7 +6,7 @@ #ifndef __BCM963138_H #define __BCM963138_H -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_HZ_CLOCK 500000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_HZ_CLOCK 500000000 #endif diff --git a/include/configs/bcm963146.h b/include/configs/bcm963146.h index edbdfc3c51a..90dfa98311d 100644 --- a/include/configs/bcm963146.h +++ b/include/configs/bcm963146.h @@ -6,6 +6,6 @@ #ifndef __BCM963146_H #define __BCM963146_H -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 #endif diff --git a/include/configs/bcm963148.h b/include/configs/bcm963148.h index 5a24cccba10..54f6750c743 100644 --- a/include/configs/bcm963148.h +++ b/include/configs/bcm963148.h @@ -6,6 +6,6 @@ #ifndef __BCM963148_H #define __BCM963148_H -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 #endif diff --git a/include/configs/bcm963158.h b/include/configs/bcm963158.h index b15c4111c96..2fdd22d1b0d 100644 --- a/include/configs/bcm963158.h +++ b/include/configs/bcm963158.h @@ -6,6 +6,6 @@ #ifndef __BCM963158_H #define __BCM963158_H -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 #endif diff --git a/include/configs/bcm963178.h b/include/configs/bcm963178.h index b25f6a12819..32fc4a5e390 100644 --- a/include/configs/bcm963178.h +++ b/include/configs/bcm963178.h @@ -6,6 +6,6 @@ #ifndef __BCM963178_H #define __BCM963178_H -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 #endif diff --git a/include/configs/bcm96756.h b/include/configs/bcm96756.h index c8f32672b7d..c69d177da2e 100644 --- a/include/configs/bcm96756.h +++ b/include/configs/bcm96756.h @@ -6,6 +6,6 @@ #ifndef __BCM96756_H #define __BCM96756_H -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 #endif diff --git a/include/configs/bcm96813.h b/include/configs/bcm96813.h index 5d9e87b693a..37d2d91d96f 100644 --- a/include/configs/bcm96813.h +++ b/include/configs/bcm96813.h @@ -6,6 +6,6 @@ #ifndef __BCM96813_H #define __BCM96813_H -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 #endif diff --git a/include/configs/bcm96846.h b/include/configs/bcm96846.h index 1d6d5d61669..581fd559856 100644 --- a/include/configs/bcm96846.h +++ b/include/configs/bcm96846.h @@ -6,6 +6,6 @@ #ifndef __BCM96846_H #define __BCM96846_H -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 #endif diff --git a/include/configs/bcm96855.h b/include/configs/bcm96855.h index 6e420f2c66f..3fb1ab9230c 100644 --- a/include/configs/bcm96855.h +++ b/include/configs/bcm96855.h @@ -6,6 +6,6 @@ #ifndef __BCM96855_H #define __BCM96855_H -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 #endif diff --git a/include/configs/bcm96856.h b/include/configs/bcm96856.h index a7ae71eeaaf..5f5af321897 100644 --- a/include/configs/bcm96856.h +++ b/include/configs/bcm96856.h @@ -6,6 +6,6 @@ #ifndef __BCM96856_H #define __BCM96856_H -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 #endif diff --git a/include/configs/bcm96858.h b/include/configs/bcm96858.h index 4e584b41fb3..9a0d89a7519 100644 --- a/include/configs/bcm96858.h +++ b/include/configs/bcm96858.h @@ -6,6 +6,6 @@ #ifndef __BCM96858_H #define __BCM96858_H -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 #endif diff --git a/include/configs/bcm96878.h b/include/configs/bcm96878.h index 3e23e94ac4b..7702d1f5682 100644 --- a/include/configs/bcm96878.h +++ b/include/configs/bcm96878.h @@ -6,6 +6,6 @@ #ifndef __BCM96878_H #define __BCM96878_H -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 #endif diff --git a/include/configs/bcm_ns3.h b/include/configs/bcm_ns3.h index 795de469384..b5469880fe2 100644 --- a/include/configs/bcm_ns3.h +++ b/include/configs/bcm_ns3.h @@ -15,7 +15,7 @@ #define V2M_BASE 0x80000000 #define PHYS_SDRAM_1 V2M_BASE -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 /* * Initial SP before reloaction is placed at end of first DRAM bank, @@ -26,7 +26,7 @@ /* 12MB Malloc size */ /* console configuration */ -#define CONFIG_SYS_NS16550_CLK 25000000 +#define CFG_SYS_NS16550_CLK 25000000 /* * Increase max uncompressed/gunzip size, keeping size same as EMMC linux diff --git a/include/configs/bcmstb.h b/include/configs/bcmstb.h index 5aa720da3d7..57360b60ca9 100644 --- a/include/configs/bcmstb.h +++ b/include/configs/bcmstb.h @@ -81,8 +81,8 @@ extern phys_addr_t prior_stage_fdt_address; * MiB. However, BOLT can be configured to allow loading larger * initramfs images, in which case this limitation is eliminated. */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x100000 +#define CFG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_INIT_RAM_SIZE 0x100000 /* * CONFIG_SYS_LOAD_ADDR - 1 MiB. @@ -97,14 +97,12 @@ extern phys_addr_t prior_stage_fdt_address; */ #define V_NS16550_CLK 81000000 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK +#define CFG_SYS_NS16550_CLK V_NS16550_CLK /* * Serial console configuration. */ -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ +#define CFG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ 115200} /* diff --git a/include/configs/beaver.h b/include/configs/beaver.h index 1d51bb4e4c4..6b5f650811b 100644 --- a/include/configs/beaver.h +++ b/include/configs/beaver.h @@ -18,7 +18,7 @@ /* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTA -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE /* SPI */ #define CONFIG_TEGRA_SLINK_CTRLS 6 diff --git a/include/configs/bitmain_antminer_s9.h b/include/configs/bitmain_antminer_s9.h index 829e816ad66..556bfa08ebb 100644 --- a/include/configs/bitmain_antminer_s9.h +++ b/include/configs/bitmain_antminer_s9.h @@ -6,8 +6,8 @@ #ifndef __CONFIG_BITMAIN_ANTMINER_S9_H #define __CONFIG_BITMAIN_ANTMINER_S9_H -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_SIZE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_SIZE 0x40000000 #define CONFIG_EXTRA_ENV_SETTINGS \ "pxefile_addr_r=0x2000000\0" \ diff --git a/include/configs/bk4r1.h b/include/configs/bk4r1.h index ca2bc1907e3..0842a4a8f54 100644 --- a/include/configs/bk4r1.h +++ b/include/configs/bk4r1.h @@ -199,8 +199,8 @@ #define PHYS_SDRAM (0x80000000) #define PHYS_SDRAM_SIZE (SZ_512M) -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE #endif /* __CONFIG_H */ diff --git a/include/configs/blanche.h b/include/configs/blanche.h index 0b1fc91d9e1..cb28ae28dd3 100644 --- a/include/configs/blanche.h +++ b/include/configs/blanche.h @@ -26,10 +26,10 @@ #define CONFIG_SH_QSPI_BASE 0xE6B10000 #else #define CONFIG_FLASH_SHOW_PROGRESS 45 -#define CONFIG_SYS_FLASH_BASE 0x00000000 -#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MB */ -#define CONFIG_SYS_FLASH_BANKS_LIST { (CONFIG_SYS_FLASH_BASE) } -#define CONFIG_SYS_FLASH_BANKS_SIZES { (CONFIG_SYS_FLASH_SIZE) } +#define CFG_SYS_FLASH_BASE 0x00000000 +#define CFG_SYS_FLASH_SIZE 0x04000000 /* 64 MB */ +#define CFG_SYS_FLASH_BANKS_LIST { (CFG_SYS_FLASH_BASE) } +#define CFG_SYS_FLASH_BANKS_SIZES { (CFG_SYS_FLASH_SIZE) } #endif /* Board Clock */ diff --git a/include/configs/bmips_bcm3380.h b/include/configs/bmips_bcm3380.h index c328f414201..0d254cd7f9c 100644 --- a/include/configs/bmips_bcm3380.h +++ b/include/configs/bmips_bcm3380.h @@ -9,12 +9,12 @@ #include <linux/sizes.h> /* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 /* U-Boot */ #if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K +#define CFG_SYS_INIT_SP_OFFSET SZ_8K #endif #endif /* __CONFIG_BMIPS_BCM3380_H */ diff --git a/include/configs/bmips_bcm6318.h b/include/configs/bmips_bcm6318.h index d16d50e5ec2..7865b9c17e5 100644 --- a/include/configs/bmips_bcm6318.h +++ b/include/configs/bmips_bcm6318.h @@ -9,12 +9,12 @@ #include <linux/sizes.h> /* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 /* U-Boot */ #if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K +#define CFG_SYS_INIT_SP_OFFSET SZ_8K #endif #endif /* __CONFIG_BMIPS_BCM6318_H */ diff --git a/include/configs/bmips_bcm63268.h b/include/configs/bmips_bcm63268.h index f69c46b11c4..93426d2661d 100644 --- a/include/configs/bmips_bcm63268.h +++ b/include/configs/bmips_bcm63268.h @@ -9,12 +9,12 @@ #include <linux/sizes.h> /* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 /* U-Boot */ #if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K +#define CFG_SYS_INIT_SP_OFFSET SZ_8K #endif #endif /* __CONFIG_BMIPS_BCM63268_H */ diff --git a/include/configs/bmips_bcm6328.h b/include/configs/bmips_bcm6328.h index acd021ecadc..e992fe6a560 100644 --- a/include/configs/bmips_bcm6328.h +++ b/include/configs/bmips_bcm6328.h @@ -9,12 +9,12 @@ #include <linux/sizes.h> /* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 /* U-Boot */ #if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K +#define CFG_SYS_INIT_SP_OFFSET SZ_8K #endif #endif /* __CONFIG_BMIPS_BCM6328_H */ diff --git a/include/configs/bmips_bcm6338.h b/include/configs/bmips_bcm6338.h index fa9e5f02a08..224b6977747 100644 --- a/include/configs/bmips_bcm6338.h +++ b/include/configs/bmips_bcm6338.h @@ -9,14 +9,14 @@ #include <linux/sizes.h> /* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 /* U-Boot */ #if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K +#define CFG_SYS_INIT_SP_OFFSET SZ_8K #endif -#define CONFIG_SYS_FLASH_BASE 0xbfc00000 +#define CFG_SYS_FLASH_BASE 0xbfc00000 #endif /* __CONFIG_BMIPS_BCM6338_H */ diff --git a/include/configs/bmips_bcm6348.h b/include/configs/bmips_bcm6348.h index bcf5c874d32..3211d23049e 100644 --- a/include/configs/bmips_bcm6348.h +++ b/include/configs/bmips_bcm6348.h @@ -9,14 +9,14 @@ #include <linux/sizes.h> /* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 /* U-Boot */ #if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K +#define CFG_SYS_INIT_SP_OFFSET SZ_8K #endif -#define CONFIG_SYS_FLASH_BASE 0xbfc00000 +#define CFG_SYS_FLASH_BASE 0xbfc00000 #endif /* __CONFIG_BMIPS_BCM6348_H */ diff --git a/include/configs/bmips_bcm6358.h b/include/configs/bmips_bcm6358.h index e31b8bc719e..7e2449ca24f 100644 --- a/include/configs/bmips_bcm6358.h +++ b/include/configs/bmips_bcm6358.h @@ -9,14 +9,14 @@ #include <linux/sizes.h> /* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 /* U-Boot */ #if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K +#define CFG_SYS_INIT_SP_OFFSET SZ_8K #endif -#define CONFIG_SYS_FLASH_BASE 0xbe000000 +#define CFG_SYS_FLASH_BASE 0xbe000000 #endif /* __CONFIG_BMIPS_BCM6358_H */ diff --git a/include/configs/bmips_bcm6362.h b/include/configs/bmips_bcm6362.h index 6e707d341b7..443ee470107 100644 --- a/include/configs/bmips_bcm6362.h +++ b/include/configs/bmips_bcm6362.h @@ -9,12 +9,12 @@ #include <linux/sizes.h> /* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 /* U-Boot */ #if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K +#define CFG_SYS_INIT_SP_OFFSET SZ_8K #endif #endif /* __CONFIG_BMIPS_BCM6362_H */ diff --git a/include/configs/bmips_bcm6368.h b/include/configs/bmips_bcm6368.h index bb72c8cb533..c550f97b935 100644 --- a/include/configs/bmips_bcm6368.h +++ b/include/configs/bmips_bcm6368.h @@ -9,14 +9,14 @@ #include <linux/sizes.h> /* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 /* U-Boot */ #if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K +#define CFG_SYS_INIT_SP_OFFSET SZ_8K #endif -#define CONFIG_SYS_FLASH_BASE 0xb8000000 +#define CFG_SYS_FLASH_BASE 0xb8000000 #endif /* __CONFIG_BMIPS_BCM6368_H */ diff --git a/include/configs/bmips_bcm6838.h b/include/configs/bmips_bcm6838.h index a1c992b7a6e..f2129140725 100644 --- a/include/configs/bmips_bcm6838.h +++ b/include/configs/bmips_bcm6838.h @@ -9,12 +9,12 @@ #include <linux/sizes.h> /* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 /* U-Boot */ #if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K +#define CFG_SYS_INIT_SP_OFFSET SZ_8K #endif #endif /* __CONFIG_BMIPS_BCM6838_H */ diff --git a/include/configs/bmips_common.h b/include/configs/bmips_common.h index 7e358a6314b..3cdd0e47eae 100644 --- a/include/configs/bmips_common.h +++ b/include/configs/bmips_common.h @@ -9,7 +9,7 @@ #include <linux/sizes.h> /* UART */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ +#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ 230400, 500000, 1500000 } #endif /* __CONFIG_BMIPS_COMMON_H */ diff --git a/include/configs/boston.h b/include/configs/boston.h index a09e831c540..14ce8a4c0f3 100644 --- a/include/configs/boston.h +++ b/include/configs/boston.h @@ -22,12 +22,12 @@ * Memory map */ #ifdef CONFIG_64BIT -# define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000 +# define CFG_SYS_SDRAM_BASE 0xffffffff80000000 #else -# define CONFIG_SYS_SDRAM_BASE 0x80000000 +# define CFG_SYS_SDRAM_BASE 0x80000000 #endif -#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 +#define CFG_SYS_INIT_SP_OFFSET 0x400000 /* * Console diff --git a/include/configs/brppt2.h b/include/configs/brppt2.h index 0c7fe5f3abb..d35c7c4a591 100644 --- a/include/configs/brppt2.h +++ b/include/configs/brppt2.h @@ -13,7 +13,7 @@ /* -- i.mx6 specifica -- */ #ifndef CONFIG_SYS_L2CACHE_OFF -#define CONFIG_SYS_PL310_BASE L2_PL310_BASE +#define CFG_SYS_PL310_BASE L2_PL310_BASE #endif /* !CONFIG_SYS_L2CACHE_OFF */ #define CONFIG_MXC_GPT_HCLK @@ -76,9 +76,9 @@ BUR_COMMON_ENV \ /* RAM */ #define PHYS_SDRAM_1 MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* Ethernet */ #define CONFIG_FEC_FIXED_SPEED _1000BASET @@ -86,9 +86,4 @@ BUR_COMMON_ENV \ /* USB Configs */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -/* SPL */ -#ifdef CONFIG_SPL -#include "imx6_spl.h" - -#endif /* CONFIG_SPL */ #endif /* __CONFIG_BRPP2_IMX6_H */ diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h index a6de28a42b2..3e0b4250788 100644 --- a/include/configs/bur_am335x_common.h +++ b/include/configs/bur_am335x_common.h @@ -14,17 +14,15 @@ /* legacy #defines for non DM bur-board */ #ifndef CONFIG_DM -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK (48000000) -#define CONFIG_SYS_NS16550_COM1 0x44e09000 +#define CFG_SYS_NS16550_CLK (48000000) +#define CFG_SYS_NS16550_COM1 0x44e09000 #endif /* CONFIG_DM */ #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ /* Timer information */ -#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ +#define CFG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ #include <asm/arch/omap.h> @@ -47,7 +45,7 @@ * always, even when we have more. We always start at 0x80000000, * and we place the initial stack pointer in our SRAM. */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 /* * Our platforms make use of SPL to initalize the hardware (primarily diff --git a/include/configs/capricorn-common.h b/include/configs/capricorn-common.h index c4110f84c0b..474ad69d996 100644 --- a/include/configs/capricorn-common.h +++ b/include/configs/capricorn-common.h @@ -92,7 +92,7 @@ /* On CCP board, USDHC1 is for eMMC */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_2 0x880000000 /* DDR3 board total DDR is 1 GB */ diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h index f3416b534b2..35c5a4f1226 100644 --- a/include/configs/cardhu.h +++ b/include/configs/cardhu.h @@ -22,7 +22,7 @@ /* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTA -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE /* SPI */ #define CONFIG_TEGRA_SLINK_CTRLS 6 diff --git a/include/configs/cei-tk1-som.h b/include/configs/cei-tk1-som.h index 0672b7dbbe9..55e2d744c4a 100644 --- a/include/configs/cei-tk1-som.h +++ b/include/configs/cei-tk1-som.h @@ -20,7 +20,7 @@ /* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTD -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE /* SPI */ #define CONFIG_SPI_FLASH_SIZE (4 << 20) diff --git a/include/configs/cgtqmx8.h b/include/configs/cgtqmx8.h index c395384c8d3..6f3396bad4c 100644 --- a/include/configs/cgtqmx8.h +++ b/include/configs/cgtqmx8.h @@ -19,7 +19,7 @@ /* Flat Device Tree Definitions */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) +#define CFG_SYS_BOOTMAPSZ (256 << 20) #define CFG_SYS_FSL_ESDHC_ADDR 0 #define USDHC1_BASE_ADDR 0x5B010000 #define USDHC2_BASE_ADDR 0x5B020000 @@ -111,7 +111,7 @@ #define CFG_SYS_FSL_USDHC_NUM 3 -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_2 0x880000000 #define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */ diff --git a/include/configs/chiliboard.h b/include/configs/chiliboard.h index fdbcbf5d96e..1e5154af0a1 100644 --- a/include/configs/chiliboard.h +++ b/include/configs/chiliboard.h @@ -97,18 +97,18 @@ NANDARGS /* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ -#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ -#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ -#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ -#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ -#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ +#define CFG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ +#define CFG_SYS_NS16550_COM2 0x48022000 /* UART1 */ +#define CFG_SYS_NS16550_COM3 0x48024000 /* UART2 */ +#define CFG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ +#define CFG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ +#define CFG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ /* SPL */ /* NAND: device related configs */ /* NAND: driver related configs */ -#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ +#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 10, 11, 12, 13, 14, 15, 16, 17, \ 18, 19, 20, 21, 22, 23, 24, 25, \ 26, 27, 28, 29, 30, 31, 32, 33, \ @@ -116,7 +116,7 @@ 42, 43, 44, 45, 46, 47, 48, 49, \ 50, 51, 52, 53, 54, 55, 56, 57, } -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 14 +#define CFG_SYS_NAND_ECCSIZE 512 +#define CFG_SYS_NAND_ECCBYTES 14 #endif /* ! __CONFIG_CHILIBOARD_H */ diff --git a/include/configs/chromebook_coral.h b/include/configs/chromebook_coral.h index 0eeea80b32f..d14c1d445b2 100644 --- a/include/configs/chromebook_coral.h +++ b/include/configs/chromebook_coral.h @@ -18,7 +18,4 @@ "stdout=vidconsole,serial\0" \ "stderr=vidconsole,serial\0" -#define CONFIG_SYS_NS16550_MEM32 -#undef CONFIG_SYS_NS16550_PORT_MAPPED - #endif /* __CONFIG_H */ diff --git a/include/configs/ci20.h b/include/configs/ci20.h index 63dac1d4a79..3329c24fa68 100644 --- a/include/configs/ci20.h +++ b/include/configs/ci20.h @@ -11,11 +11,11 @@ /* Memory configuration */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* cached (KSEG0) address */ -#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 +#define CFG_SYS_SDRAM_BASE 0x80000000 /* cached (KSEG0) address */ +#define CFG_SYS_INIT_SP_OFFSET 0x400000 /* NS16550-ish UARTs */ -#define CONFIG_SYS_NS16550_CLK 48000000 +#define CFG_SYS_NS16550_CLK 48000000 /* Ethernet: davicom DM9000 */ #define CONFIG_DM9000_BASE 0xb6000000 diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h index cbf85341a64..5c9004cbd93 100644 --- a/include/configs/cl-som-imx7.h +++ b/include/configs/cl-som-imx7.h @@ -19,12 +19,10 @@ #define IMX_FEC_BASE ENET_IPS_BASE_ADDR /* PMIC */ -#define CONFIG_POWER_PFUZE3000 #define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 -#define CONFIG_PCA953X -#define CONFIG_SYS_I2C_PCA953X_ADDR 0x20 -#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x20, 16} } +#define CFG_SYS_I2C_PCA953X_ADDR 0x20 +#define CFG_SYS_I2C_PCA953X_WIDTH { {0x20, 16} } #undef CONFIG_EXTRA_ENV_SETTINGS @@ -82,9 +80,9 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* SPI Flash support */ @@ -101,7 +99,4 @@ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -/* SPL */ -#include "imx7_spl.h" - #endif /* __CONFIG_H */ diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index 874c0eb2175..9df8baa8a96 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -21,9 +21,9 @@ /* RAM */ #define PHYS_SDRAM_1 MMDC0_ARB_BASE_ADDR #define PHYS_SDRAM_2 MMDC1_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* Serial console */ #define CONFIG_MXC_UART_BASE UART4_BASE @@ -128,7 +128,7 @@ #include <config_distro_bootcmd.h> /* NAND */ -#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CFG_SYS_NAND_BASE 0x40000000 /* APBH DMA is required for NAND support */ /* Ethernet */ @@ -139,16 +139,10 @@ #define CONFIG_MXC_USB_FLAGS 0 /* Boot */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) +#define CFG_SYS_BOOTMAPSZ (8 << 20) /* misc */ -/* SPL */ -#include "imx6_spl.h" - -/* Display */ -#define CONFIG_IMX_HDMI - /* EEPROM */ #endif /* __CONFIG_CM_FX6_H */ diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h index f0fbbe2870b..fcc17fc6b7c 100644 --- a/include/configs/cm_t43.h +++ b/include/configs/cm_t43.h @@ -9,22 +9,18 @@ #define __CONFIG_CM_T43_H #define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2GB */ -#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ +#define CFG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ #include <asm/arch/omap.h> /* Serial support */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_CLK 48000000 -#define CONFIG_SYS_NS16550_COM1 0x44e09000 -#if !defined(CONFIG_SPL_DM) || !defined(CONFIG_DM_SERIAL) -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#endif +#define CFG_SYS_NS16550_CLK 48000000 +#define CFG_SYS_NS16550_COM1 0x44e09000 /* NAND support */ -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 14 -#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ +#define CFG_SYS_NAND_ECCSIZE 512 +#define CFG_SYS_NAND_ECCBYTES 14 +#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 10, 11, 12, 13, 14, 15, 16, 17, \ 18, 19, 20, 21, 22, 23, 24, 25, \ 26, 27, 28, 29, 30, 31, 32, 33, \ @@ -32,11 +28,8 @@ 42, 43, 44, 45, 46, 47, 48, 49, \ 50, 51, 52, 53, 54, 55, 56, 57, } -/* Power */ -#define CONFIG_POWER_TPS65218 - /* Enabling L2 Cache */ -#define CONFIG_SYS_PL310_BASE 0x48242000 +#define CFG_SYS_PL310_BASE 0x48242000 /* * Since SPL did pll and ddr initialization for us, diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h index 52000b58b73..6d6e2fc6962 100644 --- a/include/configs/cobra5272.h +++ b/include/configs/cobra5272.h @@ -29,30 +29,18 @@ * --- */ -#define CONFIG_SYS_CLK 66000000 -#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ +#define CFG_SYS_CLK 66000000 +#define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ /* --- * Define baudrate for UART1 (console output, tftp, ...) * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud - * CONFIG_SYS_BAUDRATE_TABLE defines values that can be selected in u-boot command + * CFG_SYS_BAUDRATE_TABLE defines values that can be selected in u-boot command * interface * --- */ -#define CONFIG_SYS_UART_PORT (0) - -/* --- - * set "#if 0" to "#if 1" if (Hardware)-WATCHDOG should be enabled & change - * timeout acc. to your needs - * #define CONFIG_WATCHDOG_TIMEOUT x , x is timeout in milliseconds, e. g. 10000 - * for 10 sec - * --- - */ - -#if 0 -#define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */ -#endif +#define CFG_SYS_UART_PORT (0) /* --- * CONFIG_MONITOR_IS_IN_RAM defines if u-boot is started from a different @@ -133,28 +121,28 @@ enter a valid image address in flash */ * --- */ -#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ +#define CFG_SYS_MBAR 0x10000000 /* Register Base Addrs */ /* --- * System Conf. Reg. & System Protection Reg. * --- */ -#define CONFIG_SYS_SCR 0x0003 -#define CONFIG_SYS_SPR 0xffff +#define CFG_SYS_SCR 0x0003 +#define CFG_SYS_SPR 0xffff /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in internal SRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ +#define CFG_SYS_INIT_RAM_ADDR 0x20000000 +#define CFG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 /* *------------------------------------------------------------------------- @@ -162,34 +150,34 @@ enter a valid image address in flash */ *----------------------------------------------------------------------- */ -/* #define CONFIG_SYS_SDRAM_SIZE 16 */ +/* #define CFG_SYS_SDRAM_SIZE 16 */ /* *----------------------------------------------------------------------- */ -#define CONFIG_SYS_FLASH_BASE 0xffe00000 +#define CFG_SYS_FLASH_BASE 0xffe00000 /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CFG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /*----------------------------------------------------------------------- * Cache Configuration */ -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ +#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 4) +#define CFG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) +#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ +#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ CF_CACR_DISD | CF_CACR_INVI | \ CF_CACR_CEIB | CF_CACR_DCM | \ CF_CACR_EUSP) @@ -209,15 +197,15 @@ enter a valid image address in flash */ /*----------------------------------------------------------------------- * Port configuration (GPIO) */ -#define CONFIG_SYS_PACNT 0x00000000 /* PortA control reg.: All pins are external +#define CFG_SYS_PACNT 0x00000000 /* PortA control reg.: All pins are external GPIO*/ -#define CONFIG_SYS_PADDR 0x00FF /* PortA direction reg.: PA7 to PA0 are outputs +#define CFG_SYS_PADDR 0x00FF /* PortA direction reg.: PA7 to PA0 are outputs (1^=output, 0^=input) */ -#define CONFIG_SYS_PADAT LED_STAT_0 /* PortA value reg.: Turn all LED off */ -#define CONFIG_SYS_PBCNT 0x55554155 /* PortB control reg.: Ethernet/UART +#define CFG_SYS_PADAT LED_STAT_0 /* PortA value reg.: Turn all LED off */ +#define CFG_SYS_PBCNT 0x55554155 /* PortB control reg.: Ethernet/UART configuration */ -#define CONFIG_SYS_PBDDR 0x0000 /* PortB direction: All pins configured as inputs */ -#define CONFIG_SYS_PBDAT 0x0000 /* PortB value reg. */ -#define CONFIG_SYS_PDCNT 0x00000000 /* PortD control reg. */ +#define CFG_SYS_PBDDR 0x0000 /* PortB direction: All pins configured as inputs */ +#define CFG_SYS_PBDAT 0x0000 /* PortB value reg. */ +#define CFG_SYS_PDCNT 0x00000000 /* PortD control reg. */ #endif /* _CONFIG_COBRA5272_H */ diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h index d7e181b942a..c0c3b4e0359 100644 --- a/include/configs/colibri-imx6ull.h +++ b/include/configs/colibri-imx6ull.h @@ -11,7 +11,6 @@ #define __COLIBRI_IMX6ULL_CONFIG_H #include "mx6_common.h" -#define CONFIG_IOMUX_LPSR #define PHYS_SDRAM_SIZE SZ_1G @@ -116,14 +115,14 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE #ifdef CONFIG_TARGET_COLIBRI_IMX6ULL_NAND /* NAND stuff */ -/* used to initialize CONFIG_SYS_NAND_BASE_LIST which is unused */ -#define CONFIG_SYS_NAND_BASE -1 +/* used to initialize CFG_SYS_NAND_BASE_LIST which is unused */ +#define CFG_SYS_NAND_BASE -1 #endif /* USB Configs */ diff --git a/include/configs/colibri-imx8x.h b/include/configs/colibri-imx8x.h index d641fbf47e7..6002d8d5c9f 100644 --- a/include/configs/colibri-imx8x.h +++ b/include/configs/colibri-imx8x.h @@ -96,7 +96,7 @@ /* On Colibri iMX8X USDHC1 is eMMC, USDHC2 is 4-bit SD */ #define CFG_SYS_FSL_USDHC_NUM 2 -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_2 0x880000000 #define PHYS_SDRAM_1_SIZE SZ_2G /* 2 GB */ diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h index 14fdf5b50e6..60a3862a4d1 100644 --- a/include/configs/colibri_imx6.h +++ b/include/configs/colibri_imx6.h @@ -15,10 +15,6 @@ #include <asm/arch/imx-regs.h> #include <asm/mach-imx/gpio.h> -#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - #define CONFIG_MXC_UART_BASE UART1_BASE /* MMC Configs */ @@ -32,10 +28,6 @@ /* Client */ #define CONFIG_USBD_HS -/* Framebuffer and LCD */ -#define CONFIG_IMX_HDMI -#define CONFIG_IMX_VIDEO_SKIP - /* Command definition */ #undef CONFIG_IPADDR @@ -104,8 +96,8 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE #endif /* __CONFIG_H */ diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index 7380440ae7a..32a79b02554 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -160,14 +160,13 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE #ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND /* NAND stuff */ -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_MX7_GPMI_62_ECC_BYTES +#define CFG_SYS_NAND_BASE 0x40000000 #endif /* USB Configs */ diff --git a/include/configs/colibri_t20.h b/include/configs/colibri_t20.h index b758086b86d..2ba3c3bc87d 100644 --- a/include/configs/colibri_t20.h +++ b/include/configs/colibri_t20.h @@ -13,7 +13,7 @@ /* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTA #define CONFIG_TEGRA_UARTA_SDIO1 -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE /* NAND support */ diff --git a/include/configs/colibri_t30.h b/include/configs/colibri_t30.h index c9d384e2bdb..ffed71a2e82 100644 --- a/include/configs/colibri_t30.h +++ b/include/configs/colibri_t30.h @@ -22,7 +22,7 @@ * Colibri UART-C: NVIDIA UARTB */ #define CONFIG_TEGRA_ENABLE_UARTA -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE #define UBOOT_UPDATE \ "uboot_hwpart=1\0" \ diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h index 0f6f99d244f..fa778ec9e2b 100644 --- a/include/configs/colibri_vf.h +++ b/include/configs/colibri_vf.h @@ -85,9 +85,9 @@ #define PHYS_SDRAM (0x80000000) #define PHYS_SDRAM_SIZE (256 * SZ_1M) -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* USB Host Support */ diff --git a/include/configs/corstone1000.h b/include/configs/corstone1000.h index 8e0230c135e..8aec52d508e 100644 --- a/include/configs/corstone1000.h +++ b/include/configs/corstone1000.h @@ -22,7 +22,7 @@ #define PHYS_SDRAM_1 (V2M_BASE) #define PHYS_SDRAM_1_SIZE 0x80000000 -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define BOOT_TARGET_DEVICES(func) \ func(USB, usb, 0) diff --git a/include/configs/corvus.h b/include/configs/corvus.h index 0596afbf9fa..8a61086ecc1 100644 --- a/include/configs/corvus.h +++ b/include/configs/corvus.h @@ -24,27 +24,26 @@ */ /* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 +#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ /* serial console */ #define CONFIG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID ATMEL_ID_SYS /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS6 -#define CONFIG_SYS_SDRAM_SIZE 0x08000000 +#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS6 +#define CFG_SYS_SDRAM_SIZE 0x08000000 /* NAND flash */ #ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 -#define CONFIG_SYS_NAND_DBW_8 +#define CFG_SYS_NAND_BASE ATMEL_BASE_CS3 /* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +#define CFG_SYS_NAND_MASK_ALE (1 << 21) /* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8 +#define CFG_SYS_NAND_MASK_CLE (1 << 22) +#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 +#define CFG_SYS_NAND_READY_PIN AT91_PIN_PC8 #endif /* DFU class support */ @@ -54,20 +53,20 @@ /* Defines for SPL */ -#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000 -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE +#define CFG_SYS_NAND_U_BOOT_SIZE 0x80000 +#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE -#define CONFIG_SYS_NAND_ECCSIZE 256 -#define CONFIG_SYS_NAND_ECCBYTES 3 -#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ +#define CFG_SYS_NAND_ECCSIZE 256 +#define CFG_SYS_NAND_ECCBYTES 3 +#define CFG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ 48, 49, 50, 51, 52, 53, 54, 55, \ 56, 57, 58, 59, 60, 61, 62, 63, } -#define CONFIG_SYS_MASTER_CLOCK 132096000 +#define CFG_SYS_MASTER_CLOCK 132096000 #define AT91_PLL_LOCK_TIMEOUT 1000000 -#define CONFIG_SYS_AT91_PLLA 0x20c73f03 -#define CONFIG_SYS_MCKR 0x1301 -#define CONFIG_SYS_MCKR_CSS 0x1302 +#define CFG_SYS_AT91_PLLA 0x20c73f03 +#define CFG_SYS_MCKR 0x1301 +#define CFG_SYS_MCKR_CSS 0x1302 #endif diff --git a/include/configs/cougarcanyon2.h b/include/configs/cougarcanyon2.h index efd0b778435..b64c7df1b25 100644 --- a/include/configs/cougarcanyon2.h +++ b/include/configs/cougarcanyon2.h @@ -8,8 +8,6 @@ #include <configs/x86-common.h> -#define CONFIG_SMSC_SIO1007 - #define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd,usbkbd\0" \ "stdout=serial,vga\0" \ "stderr=serial,vga\0" diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h index e8a8af7e649..ff74deb3d40 100644 --- a/include/configs/crownbay.h +++ b/include/configs/crownbay.h @@ -12,8 +12,6 @@ #include <configs/x86-common.h> -#define CONFIG_SMSC_LPC47M - #define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd,usbkbd\0" \ "stdout=serial,vidconsole\0" \ "stderr=serial,vidconsole\0" diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index 281cbe37f9d..a818a4b39f8 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -17,13 +17,13 @@ /* * SoC Configuration */ -#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH -#define CONFIG_SYS_OSCIN_FREQ 24000000 -#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE -#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) +#define CFG_SYS_EXCEPTION_VECTORS_HIGH +#define CFG_SYS_OSCIN_FREQ 24000000 +#define CFG_SYS_TIMERBASE DAVINCI_TIMER0_BASE +#define CFG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) #ifdef CONFIG_MTD_NOR_FLASH -#define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11) +#define CFG_SYS_DV_NOR_BOOT_CFG (0x11) #endif /* @@ -36,7 +36,7 @@ /* memtest will be run on 16MB */ -#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ +#define CFG_SYS_DA850_SYSCFG_SUSPSRC ( \ DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ DAVINCI_SYSCFG_SUSPSRC_SPI1 | \ DAVINCI_SYSCFG_SUSPSRC_UART2 | \ @@ -47,17 +47,17 @@ * PLL configuration */ -#define CONFIG_SYS_DA850_PLL0_PLLM 24 -#define CONFIG_SYS_DA850_PLL1_PLLM 21 +#define CFG_SYS_DA850_PLL0_PLLM 24 +#define CFG_SYS_DA850_PLL1_PLLM 21 /* * DDR2 memory configuration */ -#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ +#define CFG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ DV_DDR_PHY_EXT_STRBEN | \ (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT)) -#define CONFIG_SYS_DA850_DDR2_SDBCR ( \ +#define CFG_SYS_DA850_DDR2_SDBCR ( \ (1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \ (1 << DV_DDR_SDCR_DDREN_SHIFT) | \ (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ @@ -67,9 +67,9 @@ (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */ -#define CONFIG_SYS_DA850_DDR2_SDBCR2 0 +#define CFG_SYS_DA850_DDR2_SDBCR2 0 -#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \ +#define CFG_SYS_DA850_DDR2_SDTIMR ( \ (14 << DV_DDR_SDTMR1_RFC_SHIFT) | \ (2 << DV_DDR_SDTMR1_RP_SHIFT) | \ (2 << DV_DDR_SDTMR1_RCD_SHIFT) | \ @@ -79,7 +79,7 @@ (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ (0 << DV_DDR_SDTMR1_WTR_SHIFT)) -#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \ +#define CFG_SYS_DA850_DDR2_SDTIMR2 ( \ (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ (0 << DV_DDR_SDTMR2_XP_SHIFT) | \ (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ @@ -88,51 +88,44 @@ (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \ (0 << DV_DDR_SDTMR2_CKE_SHIFT)) -#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000494 -#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30 +#define CFG_SYS_DA850_DDR2_SDRCR 0x00000494 +#define CFG_SYS_DA850_DDR2_PBBPR 0x30 /* * Serial Driver info */ -#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) +#define CFG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) -#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) +#define CFG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) /* * I2C Configuration */ -#define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20 +#define CFG_SYS_I2C_EXPANDER_ADDR 0x20 /* * Flash & Environment */ #ifdef CONFIG_MTD_RAW_NAND -#define CONFIG_SYS_NAND_PAGE_2K -#define CONFIG_SYS_NAND_CS 3 -#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE -#define CONFIG_SYS_NAND_MASK_CLE 0x10 -#define CONFIG_SYS_NAND_MASK_ALE 0x8 -#undef CONFIG_SYS_NAND_HW_ECC -#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST -#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x40000 -#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000 -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST -#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \ - CONFIG_SYS_NAND_U_BOOT_SIZE - \ - CONFIG_SYS_MALLOC_LEN - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_NAND_ECCPOS { \ +#define CFG_SYS_NAND_CS 3 +#define CFG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE +#define CFG_SYS_NAND_MASK_CLE 0x10 +#define CFG_SYS_NAND_MASK_ALE 0x8 +#define CFG_SYS_NAND_U_BOOT_SIZE 0x40000 +#define CFG_SYS_NAND_U_BOOT_DST 0xc1080000 +#define CFG_SYS_NAND_U_BOOT_START CFG_SYS_NAND_U_BOOT_DST +#define CFG_SYS_NAND_ECCPOS { \ 24, 25, 26, 27, 28, \ 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \ 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \ 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \ 59, 60, 61, 62, 63 } -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 10 +#define CFG_SYS_NAND_ECCSIZE 512 +#define CFG_SYS_NAND_ECCBYTES 10 #endif #ifdef CONFIG_MTD_NOR_FLASH -#define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE +#define CFG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE #define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */ #endif @@ -144,7 +137,6 @@ * Linux Information */ #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) -#define CONFIG_HWCONFIG /* enable hwconfig */ #define DEFAULT_LINUX_BOOT_ENV \ "loadaddr=0xc0700000\0" \ @@ -173,7 +165,7 @@ /* Load U-Boot Image From MMC */ /* additions for new relocation code, must added to all boards */ -#define CONFIG_SYS_SDRAM_BASE 0xc0000000 +#define CFG_SYS_SDRAM_BASE 0xc0000000 #include <asm/arch/hardware.h> diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h index e03a24adca4..24cf554649b 100644 --- a/include/configs/dalmore.h +++ b/include/configs/dalmore.h @@ -15,7 +15,7 @@ /* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTD -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE /* Environment in eMMC, at the end of 2nd "boot sector" */ diff --git a/include/configs/dart_6ul.h b/include/configs/dart_6ul.h index 6079596caec..4b31bbf4e11 100644 --- a/include/configs/dart_6ul.h +++ b/include/configs/dart_6ul.h @@ -10,9 +10,6 @@ #include <linux/stringify.h> #include "mx6_common.h" -/* SPL options */ -#include "imx6_spl.h" - /* NAND pin conflicts with usdhc2 */ #ifdef CONFIG_CMD_NAND #define CFG_SYS_FSL_USDHC_NUM 1 @@ -45,9 +42,9 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define PHYS_SDRAM_SIZE SZ_512M -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* USB Configs */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h index 7b305955c96..bf8b35102ad 100644 --- a/include/configs/db-mv784mp-gp.h +++ b/include/configs/db-mv784mp-gp.h @@ -45,7 +45,4 @@ /* SPL */ /* Defines for SPL */ -/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ -#define CONFIG_SPD_EEPROM 0x4e - #endif /* _CONFIG_DB_MV7846MP_GP_H */ diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h index 42366123cb1..66aa6d5c3c4 100644 --- a/include/configs/devkit3250.h +++ b/include/configs/devkit3250.h @@ -15,8 +15,8 @@ /* * Memory configurations */ -#define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE -#define CONFIG_SYS_SDRAM_SIZE SZ_64M +#define CFG_SYS_SDRAM_BASE EMC_DYCS0_BASE +#define CFG_SYS_SDRAM_SIZE SZ_64M /* * DMA @@ -29,14 +29,14 @@ /* * NOR Flash */ -#define CONFIG_SYS_FLASH_BASE EMC_CS0_BASE -#define CONFIG_SYS_FLASH_SIZE SZ_4M +#define CFG_SYS_FLASH_BASE EMC_CS0_BASE +#define CFG_SYS_FLASH_SIZE SZ_4M /* * NAND controller */ -#define CONFIG_SYS_NAND_BASE SLC_NAND_BASE -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CFG_SYS_NAND_BASE SLC_NAND_BASE +#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } /* * NAND chip timings @@ -79,10 +79,10 @@ */ /* U-Boot will be 0x60000 bytes, loaded and run at CONFIG_TEXT_BASE */ -#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000 +#define CFG_SYS_NAND_U_BOOT_SIZE 0x60000 -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE +#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE /* See common/spl/spl.c spl_set_header_raw_uboot() */ diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index d45115bdf68..46410595c2b 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -100,12 +100,12 @@ /* Defines for SPL */ /* NAND boot config */ -#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ +#define CFG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ 10, 11, 12, 13} -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CFG_SYS_NAND_ECCSIZE 512 +#define CFG_SYS_NAND_ECCBYTES 3 -#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x200000 +#define CFG_SYS_NAND_U_BOOT_SIZE 0x200000 #endif /* __CONFIG_H */ diff --git a/include/configs/dfi-bt700.h b/include/configs/dfi-bt700.h index 4297047e8ce..52f2d50118a 100644 --- a/include/configs/dfi-bt700.h +++ b/include/configs/dfi-bt700.h @@ -14,7 +14,6 @@ #ifndef CONFIG_INTERNAL_UART /* Use BayTrail internal HS UART which is memory-mapped */ -#undef CONFIG_SYS_NS16550_PORT_MAPPED #endif #define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \ diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h index 54b2192b4a8..f9b3d19480e 100644 --- a/include/configs/dh_imx6.h +++ b/include/configs/dh_imx6.h @@ -21,9 +21,6 @@ * 0x12_0000-0x1f_ffff ... UNUSED */ -/* SPL */ -#include "imx6_spl.h" /* common IMX6 SPL configuration */ - /* Miscellaneous configurable options */ /* MMC Configs */ @@ -75,9 +72,9 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* Environment */ diff --git a/include/configs/display5.h b/include/configs/display5.h index eb65f17cbe4..7636d2869a9 100644 --- a/include/configs/display5.h +++ b/include/configs/display5.h @@ -30,11 +30,9 @@ */ /* Below values are "dummy" - only to avoid build break */ -#define CONFIG_SYS_SPI_KERNEL_OFFS 0x150000 -#define CONFIG_SYS_SPI_ARGS_OFFS 0x140000 -#define CONFIG_SYS_SPI_ARGS_SIZE 0x10000 - -#include "imx6_spl.h" +#define CFG_SYS_SPI_KERNEL_OFFS 0x150000 +#define CFG_SYS_SPI_ARGS_OFFS 0x140000 +#define CFG_SYS_SPI_ARGS_SIZE 0x10000 #define CONFIG_MXC_UART_BASE UART5_BASE @@ -285,10 +283,10 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* ENV config */ #ifdef CONFIG_ENV_IS_IN_SPI_FLASH diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 6cf716e293d..ac3fcacc68e 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -13,8 +13,6 @@ #include <environment/ti/dfu.h> -#define CONFIG_IODELAY_RECALIBRATION - #define CONFIG_VERY_BIG_RAM #define CONFIG_MAX_MEM_MAPPED 0x80000000 @@ -27,11 +25,9 @@ #elif (CONFIG_CONS_INDEX == 3) #define CONSOLEDEV "ttyS2" #endif -#define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */ -#define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ -#define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ - -#define CONFIG_SYS_OMAP_ABE_SYSCK +#define CFG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */ +#define CFG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ +#define CFG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ #ifndef CONFIG_SPL_BUILD #define DFUARGS \ @@ -65,9 +61,9 @@ * 0x1E0000 - 0x9E0000 : QSPI.kernel (8MiB) * 0x9E0000 - 0x2000000 : USERLAND */ -#define CONFIG_SYS_SPI_KERNEL_OFFS 0x1E0000 -#define CONFIG_SYS_SPI_ARGS_OFFS 0x140000 -#define CONFIG_SYS_SPI_ARGS_SIZE 0x80000 +#define CFG_SYS_SPI_KERNEL_OFFS 0x1E0000 +#define CFG_SYS_SPI_ARGS_OFFS 0x140000 +#define CFG_SYS_SPI_ARGS_SIZE 0x80000 /* SPI SPL */ @@ -75,22 +71,22 @@ #ifdef CONFIG_MTD_RAW_NAND /* NAND: device related configs */ /* NAND: driver related configs */ -#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ +#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 10, 11, 12, 13, 14, 15, 16, 17, \ 18, 19, 20, 21, 22, 23, 24, 25, \ 26, 27, 28, 29, 30, 31, 32, 33, \ 34, 35, 36, 37, 38, 39, 40, 41, \ 42, 43, 44, 45, 46, 47, 48, 49, \ 50, 51, 52, 53, 54, 55, 56, 57, } -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 14 +#define CFG_SYS_NAND_ECCSIZE 512 +#define CFG_SYS_NAND_ECCBYTES 14 #endif /* !CONFIG_MTD_RAW_NAND */ /* Parallel NOR Support */ #if defined(CONFIG_NOR) /* NOR: device related configs */ -#define CONFIG_SYS_FLASH_SIZE (64 * 1024 * 1024) /* 64 MB */ -#define CONFIG_SYS_FLASH_BASE (0x08000000) +#define CFG_SYS_FLASH_SIZE (64 * 1024 * 1024) /* 64 MB */ +#define CFG_SYS_FLASH_BASE (0x08000000) /* Reduce SPL size by removing unlikey targets */ #endif /* NOR support */ diff --git a/include/configs/draak.h b/include/configs/draak.h index 8bfba78dc8e..8140bc469c5 100644 --- a/include/configs/draak.h +++ b/include/configs/draak.h @@ -14,7 +14,7 @@ /* Environment in eMMC, at the end of 2nd "boot sector" */ #define CONFIG_FLASH_SHOW_PROGRESS 45 -#define CONFIG_SYS_FLASH_BANKS_LIST { 0x08000000 } -#define CONFIG_SYS_WRITE_SWAPPED_DATA +#define CFG_SYS_FLASH_BANKS_LIST { 0x08000000 } +#define CFG_SYS_WRITE_SWAPPED_DATA #endif /* __DRAAK_H */ diff --git a/include/configs/dragonboard410c.h b/include/configs/dragonboard410c.h index c37b4c635b2..daf7ecd7975 100644 --- a/include/configs/dragonboard410c.h +++ b/include/configs/dragonboard410c.h @@ -17,7 +17,7 @@ #define PHYS_SDRAM_1 0x80000000 /* Note: 8 MiB (0x86000000 - 0x86800000) are reserved for tz/smem/hyp/rmtfs/rfsa */ #define PHYS_SDRAM_1_SIZE SZ_1G -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 /* Environment */ #define BOOT_TARGET_DEVICES(func) \ diff --git a/include/configs/dragonboard820c.h b/include/configs/dragonboard820c.h index 1fa5d05e7b4..31cd8536de4 100644 --- a/include/configs/dragonboard820c.h +++ b/include/configs/dragonboard820c.h @@ -19,7 +19,7 @@ #define PHYS_SDRAM_2 0x100000000 #define PHYS_SDRAM_2_SIZE 0x5ea4ffff -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 #include <config_distro_bootcmd.h> diff --git a/include/configs/dragonboard845c.h b/include/configs/dragonboard845c.h index 677a4856230..bd88c42a3ba 100644 --- a/include/configs/dragonboard845c.h +++ b/include/configs/dragonboard845c.h @@ -11,7 +11,7 @@ #include <linux/sizes.h> #include <asm/arch/sysmap-sdm845.h> -#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 } +#define CFG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 } #define CONFIG_EXTRA_ENV_SETTINGS \ "bootm_size=0x5000000\0" \ diff --git a/include/configs/durian.h b/include/configs/durian.h index 8f0e8be4330..001596c00a4 100644 --- a/include/configs/durian.h +++ b/include/configs/durian.h @@ -11,7 +11,7 @@ /* Sdram Bank #1 Address */ #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_1_SIZE 0x7B000000 -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 /* BOOT */ diff --git a/include/configs/ea-lpc3250devkitv2.h b/include/configs/ea-lpc3250devkitv2.h index 1d655292d7e..fc1c2aed778 100644 --- a/include/configs/ea-lpc3250devkitv2.h +++ b/include/configs/ea-lpc3250devkitv2.h @@ -13,7 +13,7 @@ /* * RAM */ -#define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE +#define CFG_SYS_SDRAM_BASE EMC_DYCS0_BASE /* * cmd diff --git a/include/configs/eb_cpu5282.h b/include/configs/eb_cpu5282.h index aaa2ef039d9..21eab9b3a47 100644 --- a/include/configs/eb_cpu5282.h +++ b/include/configs/eb_cpu5282.h @@ -12,7 +12,7 @@ * High Level Configuration Options (easy to change) * *----------------------------------------------------------------------*/ -#define CONFIG_SYS_UART_PORT (0) +#define CFG_SYS_UART_PORT (0) #undef CONFIG_MONITOR_IS_IN_RAM /* starts uboot direct */ @@ -27,18 +27,18 @@ * Environment is in the second sector of the first 256k of flash * *----------------------------------------------------------------------*/ -/*#define CONFIG_SYS_DRAM_TEST 1 */ -#undef CONFIG_SYS_DRAM_TEST +/*#define CFG_SYS_DRAM_TEST 1 */ +#undef CFG_SYS_DRAM_TEST /*----------------------------------------------------------------------* * Clock and PLL Configuration * *----------------------------------------------------------------------*/ -#define CONFIG_SYS_CLK 80000000 /* 8MHz * 8 */ +#define CFG_SYS_CLK 80000000 /* 8MHz * 8 */ /* PLL Configuration: Ext Clock * 8 (see table 9-4 of MCF user manual) */ -#define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */ -#define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */ +#define CFG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */ +#define CFG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */ /*----------------------------------------------------------------------* * Network * @@ -54,59 +54,59 @@ * You should know what you are doing if you make changes here. *-----------------------------------------------------------------------*/ -#define CONFIG_SYS_MBAR 0x40000000 +#define CFG_SYS_MBAR 0x40000000 /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) *-----------------------------------------------------------------------*/ -#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 +#define CFG_SYS_INIT_RAM_ADDR 0x20000000 +#define CFG_SYS_INIT_RAM_SIZE 0x10000 /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CONFIG_SYS_SDRAM_BASE0 0x00000000 -#define CONFIG_SYS_SDRAM_SIZE0 16 /* SDRAM size in MB */ +#define CFG_SYS_SDRAM_BASE0 0x00000000 +#define CFG_SYS_SDRAM_SIZE0 16 /* SDRAM size in MB */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM_BASE0 -#define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM_SIZE0 +#define CFG_SYS_SDRAM_BASE CFG_SYS_SDRAM_BASE0 +#define CFG_SYS_SDRAM_SIZE CFG_SYS_SDRAM_SIZE0 /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CFG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /*----------------------------------------------------------------------- * FLASH organization */ #define CONFIG_FLASH_SHOW_PROGRESS 45 -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE -#define CONFIG_SYS_INT_FLASH_BASE 0xF0000000 -#define CONFIG_SYS_INT_FLASH_ENABLE 0x21 +#define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE +#define CFG_SYS_INT_FLASH_BASE 0xF0000000 +#define CFG_SYS_INT_FLASH_ENABLE 0x21 -#define CONFIG_SYS_FLASH_SIZE 16*1024*1024 +#define CFG_SYS_FLASH_SIZE 16*1024*1024 -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } +#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE } /*----------------------------------------------------------------------- * Cache Configuration */ -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ +#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 4) +#define CFG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM) +#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ +#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ CF_CACR_CEIB | CF_CACR_DBWE | \ CF_CACR_EUSP) @@ -114,75 +114,44 @@ * Memory bank definitions */ -#define CONFIG_SYS_CS0_BASE 0xFF000000 -#define CONFIG_SYS_CS0_CTRL 0x00001980 -#define CONFIG_SYS_CS0_MASK 0x00FF0001 +#define CFG_SYS_CS0_BASE 0xFF000000 +#define CFG_SYS_CS0_CTRL 0x00001980 +#define CFG_SYS_CS0_MASK 0x00FF0001 -#define CONFIG_SYS_CS2_BASE 0xE0000000 -#define CONFIG_SYS_CS2_CTRL 0x00001980 -#define CONFIG_SYS_CS2_MASK 0x000F0001 +#define CFG_SYS_CS2_BASE 0xE0000000 +#define CFG_SYS_CS2_CTRL 0x00001980 +#define CFG_SYS_CS2_MASK 0x000F0001 -#define CONFIG_SYS_CS3_BASE 0xE0100000 -#define CONFIG_SYS_CS3_CTRL 0x00001980 -#define CONFIG_SYS_CS3_MASK 0x000F0001 +#define CFG_SYS_CS3_BASE 0xE0100000 +#define CFG_SYS_CS3_CTRL 0x00001980 +#define CFG_SYS_CS3_MASK 0x000F0001 /*----------------------------------------------------------------------- * Port configuration */ -#define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */ -#define CONFIG_SYS_PADDR 0x0000000 -#define CONFIG_SYS_PADAT 0x0000000 +#define CFG_SYS_PACNT 0x0000000 /* Port A D[31:24] */ +#define CFG_SYS_PADDR 0x0000000 +#define CFG_SYS_PADAT 0x0000000 -#define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */ -#define CONFIG_SYS_PBDDR 0x0000000 -#define CONFIG_SYS_PBDAT 0x0000000 +#define CFG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */ +#define CFG_SYS_PBDDR 0x0000000 +#define CFG_SYS_PBDAT 0x0000000 -#define CONFIG_SYS_PCCNT 0x0000000 /* Port C D[15:08] */ -#define CONFIG_SYS_PCDDR 0x0000000 -#define CONFIG_SYS_PCDAT 0x0000000 +#define CFG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */ -#define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */ -#define CONFIG_SYS_PCDDR 0x0000000 -#define CONFIG_SYS_PCDAT 0x0000000 - -#define CONFIG_SYS_PASPAR 0x0F0F -#define CONFIG_SYS_PEHLPAR 0xC0 -#define CONFIG_SYS_PUAPAR 0x0F -#define CONFIG_SYS_DDRUA 0x05 -#define CONFIG_SYS_PJPAR 0xFF +#define CFG_SYS_PASPAR 0x0F0F +#define CFG_SYS_PEHLPAR 0xC0 +#define CFG_SYS_PUAPAR 0x0F +#define CFG_SYS_DDRUA 0x05 +#define CFG_SYS_PJPAR 0xFF /*----------------------------------------------------------------------- * I2C */ #ifdef CONFIG_CMD_DATE -#define CONFIG_RTC_DS1338 #define CONFIG_I2C_RTC_ADDR 0x68 #endif -/*----------------------------------------------------------------------- - * VIDEO configuration - */ - -#define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN 2 -#define CONFIG_SYS_VCXK_DOUBLEBUFFERED 1 -#define CONFIG_SYS_VCXK_BASE CONFIG_SYS_CS2_BASE - -#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT MCFGPTB_GPTPORT -#define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR MCFGPTB_GPTDDR -#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN 0x0001 - -#define CONFIG_SYS_VCXK_ENABLE_PORT MCFGPTB_GPTPORT -#define CONFIG_SYS_VCXK_ENABLE_DDR MCFGPTB_GPTDDR -#define CONFIG_SYS_VCXK_ENABLE_PIN 0x0002 - -#define CONFIG_SYS_VCXK_REQUEST_PORT MCFGPTB_GPTPORT -#define CONFIG_SYS_VCXK_REQUEST_DDR MCFGPTB_GPTDDR -#define CONFIG_SYS_VCXK_REQUEST_PIN 0x0004 - -#define CONFIG_SYS_VCXK_INVERT_PORT MCFGPIO_PORTE -#define CONFIG_SYS_VCXK_INVERT_DDR MCFGPIO_DDRE -#define CONFIG_SYS_VCXK_INVERT_PIN MCFGPIO_PORT2 - #endif /* _CONFIG_M5282EVB_H */ /*---------------------------------------------------------------------*/ diff --git a/include/configs/ebisu.h b/include/configs/ebisu.h index 597efd6745c..d1882a9646b 100644 --- a/include/configs/ebisu.h +++ b/include/configs/ebisu.h @@ -16,7 +16,7 @@ /* Environment in eMMC, at the end of 2nd "boot sector" */ #define CONFIG_FLASH_SHOW_PROGRESS 45 -#define CONFIG_SYS_FLASH_BANKS_LIST { 0x08000000 } -#define CONFIG_SYS_WRITE_SWAPPED_DATA +#define CFG_SYS_FLASH_BANKS_LIST { 0x08000000 } +#define CFG_SYS_WRITE_SWAPPED_DATA #endif /* __EBISU_H */ diff --git a/include/configs/edison.h b/include/configs/edison.h index b05141ad645..455a889b64c 100644 --- a/include/configs/edison.h +++ b/include/configs/edison.h @@ -10,6 +10,6 @@ /* Miscellaneous configurable options */ -#define CONFIG_SYS_STACK_SIZE (32 * 1024) +#define CFG_SYS_STACK_SIZE (32 * 1024) #endif diff --git a/include/configs/el6x_common.h b/include/configs/el6x_common.h index affe20a1019..89e071c0df6 100644 --- a/include/configs/el6x_common.h +++ b/include/configs/el6x_common.h @@ -12,16 +12,11 @@ #include "mx6_common.h" -#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - /* MMC Configs */ #define CFG_SYS_FSL_ESDHC_ADDR 0 #define CFG_SYS_FSL_USDHC_NUM 2 /* PMIC */ -#define CONFIG_POWER_PFUZE100 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 /* Commands */ @@ -54,9 +49,9 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* environment organization */ diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h index 555239b8e81..22e0fa5aabf 100644 --- a/include/configs/embestmx6boards.h +++ b/include/configs/embestmx6boards.h @@ -27,9 +27,9 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* Environment organization */ @@ -43,18 +43,8 @@ #define CFG_SYS_FSL_USDHC_NUM 2 #endif -/* Framebuffer */ -#define CONFIG_IMX_HDMI -#define CONFIG_IMX_VIDEO_SKIP - #include "mx6_common.h" -#ifdef CONFIG_SPL -#include "imx6_spl.h" -/* RiOTboard */ - -#endif - /* 256M RAM (minimum), 32M uncompressed kernel, 16M compressed kernel, 1M fdt, * 1M script, 1M pxe and the ramdisk at the end */ #define MEM_LAYOUT_ENV_SETTINGS \ diff --git a/include/configs/emsdp.h b/include/configs/emsdp.h index 60fab0419f5..c2b921e7cb8 100644 --- a/include/configs/emsdp.h +++ b/include/configs/emsdp.h @@ -8,8 +8,8 @@ #include <linux/sizes.h> -#define CONFIG_SYS_SDRAM_BASE 0x10000000 -#define CONFIG_SYS_SDRAM_SIZE SZ_16M +#define CFG_SYS_SDRAM_BASE 0x10000000 +#define CFG_SYS_SDRAM_SIZE SZ_16M /* * Environment diff --git a/include/configs/espresso7420.h b/include/configs/espresso7420.h index 2f067a44248..b4f14a9a589 100644 --- a/include/configs/espresso7420.h +++ b/include/configs/espresso7420.h @@ -10,7 +10,7 @@ #include <configs/exynos7420-common.h> -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 /* DRAM Memory Banks */ #define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ diff --git a/include/configs/etamin.h b/include/configs/etamin.h index 75322a37322..6647148c96f 100644 --- a/include/configs/etamin.h +++ b/include/configs/etamin.h @@ -14,10 +14,10 @@ #include "siemens-am33x-common.h" /* NAND specific changes for etamin due to different page size */ -#undef CONFIG_SYS_NAND_ECCPOS +#undef CFG_SYS_NAND_ECCPOS -#define CONFIG_SYS_ENV_SECT_SIZE (512 << 10) /* 512 KiB */ -#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ +#define CFG_SYS_ENV_SECT_SIZE (512 << 10) /* 512 KiB */ +#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \ 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \ 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, \ @@ -40,14 +40,14 @@ 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, \ } -#undef CONFIG_SYS_NAND_ECCSIZE -#undef CONFIG_SYS_NAND_ECCBYTES -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 26 +#undef CFG_SYS_NAND_ECCSIZE +#undef CFG_SYS_NAND_ECCBYTES +#define CFG_SYS_NAND_ECCSIZE 512 +#define CFG_SYS_NAND_ECCBYTES 26 -#define CONFIG_SYS_NAND_BASE2 (0x18000000) /* physical address */ -#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \ - CONFIG_SYS_NAND_BASE2} +#define CFG_SYS_NAND_BASE2 (0x18000000) /* physical address */ +#define CFG_SYS_NAND_BASE_LIST {CFG_SYS_NAND_BASE, \ + CFG_SYS_NAND_BASE2} #define DDR_PLL_FREQ 303 diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h index 22647abee0d..52eb0be6761 100644 --- a/include/configs/ethernut5.h +++ b/include/configs/ethernut5.h @@ -18,32 +18,31 @@ /* CPU information */ /* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ +#define CFG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ /* 32kB internal SRAM */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x00300000 /*AT91SAM9XE_SRAM_BASE */ -#define CONFIG_SYS_INIT_RAM_SIZE (32 << 10) +#define CFG_SYS_INIT_RAM_ADDR 0x00300000 /*AT91SAM9XE_SRAM_BASE */ +#define CFG_SYS_INIT_RAM_SIZE (32 << 10) /* 128MB SDRAM in 1 bank */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE (128 << 20) +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE (128 << 20) /* 512kB on-chip NOR flash */ -# define CONFIG_SYS_FLASH_BASE 0x00200000 /* AT91SAM9XE_FLASH_BASE */ +# define CFG_SYS_FLASH_BASE 0x00200000 /* AT91SAM9XE_FLASH_BASE */ /* bootstrap + u-boot + env + linux in dataflash on CS0 */ /* NAND flash */ #ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_DBW_8 +#define CFG_SYS_NAND_BASE 0x40000000 /* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +#define CFG_SYS_NAND_MASK_ALE (1 << 21) /* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14) +#define CFG_SYS_NAND_MASK_CLE (1 << 22) +#define CFG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14) #endif /* JFFS2 */ @@ -54,16 +53,16 @@ /* MMC */ #ifdef CONFIG_CMD_MMC -#define CONFIG_SYS_MMC_CD_PIN AT91_PIO_PORTC, 8 +#define CFG_SYS_MMC_CD_PIN AT91_PIO_PORTC, 8 #endif /* RTC */ #if defined(CONFIG_CMD_DATE) || defined(CONFIG_CMD_SNTP) -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 +#define CFG_SYS_I2C_RTC_ADDR 0x51 #endif /* I2C */ -#define CONFIG_SYS_MAX_I2C_BUS 1 +#define CFG_SYS_MAX_I2C_BUS 1 #define I2C_SOFT_DECLARATIONS diff --git a/include/configs/evb_ast2500.h b/include/configs/evb_ast2500.h index cd6cb062eca..bec1660cf48 100644 --- a/include/configs/evb_ast2500.h +++ b/include/configs/evb_ast2500.h @@ -11,7 +11,7 @@ #include <configs/aspeed-common.h> -#define CONFIG_SYS_UBOOT_BASE CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE /* Misc */ #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/evb_ast2600.h b/include/configs/evb_ast2600.h index ecd05fe15ce..c9c988b9374 100644 --- a/include/configs/evb_ast2600.h +++ b/include/configs/evb_ast2600.h @@ -8,7 +8,7 @@ #include <configs/aspeed-common.h> -#define CONFIG_SYS_UBOOT_BASE CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE /* Misc */ #define STR_HELPER(s) #s diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index 44f5cb1e83f..dd322c2b3a7 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -29,21 +29,21 @@ #define CONFIG_RD_LVL -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) +#define PHYS_SDRAM_2 (CFG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) #define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_3 (CFG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_4 (CFG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_5 (CFG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_6 (CFG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_7 (CFG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_8 (CFG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE /* SPI */ diff --git a/include/configs/exynos5-dt-common.h b/include/configs/exynos5-dt-common.h index a94f5a15f0d..c9e0c13172c 100644 --- a/include/configs/exynos5-dt-common.h +++ b/include/configs/exynos5-dt-common.h @@ -15,7 +15,7 @@ "stdout=serial,vidconsole\0" \ "stderr=serial,vidconsole\0" -#define CONFIG_SYS_SPI_BASE 0x12D30000 +#define CFG_SYS_SPI_BASE 0x12D30000 #define FLASH_SIZE (4 << 20) #define CONFIG_SPI_BOOTING diff --git a/include/configs/exynos5250-common.h b/include/configs/exynos5250-common.h index 8e2f135f934..cc0cf5ecbfb 100644 --- a/include/configs/exynos5250-common.h +++ b/include/configs/exynos5250-common.h @@ -9,7 +9,7 @@ #ifndef __CONFIG_5250_H #define __CONFIG_5250_H -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 /* DRAM Memory Banks */ #define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ diff --git a/include/configs/exynos7420-common.h b/include/configs/exynos7420-common.h index a8bef860c2f..cff910c1bd5 100644 --- a/include/configs/exynos7420-common.h +++ b/include/configs/exynos7420-common.h @@ -23,21 +23,21 @@ /* select serial console configuration */ -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) +#define PHYS_SDRAM_2 (CFG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) #define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_3 (CFG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_4 (CFG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_5 (CFG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_6 (CFG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_7 (CFG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_8 (CFG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE /* Configuration of ENV Blocks */ diff --git a/include/configs/exynos78x0-common.h b/include/configs/exynos78x0-common.h index b05846d0b92..8672b9e9527 100644 --- a/include/configs/exynos78x0-common.h +++ b/include/configs/exynos78x0-common.h @@ -18,35 +18,35 @@ #define CPU_RELEASE_ADDR secondary_boot_addr -#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ {9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600} -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 /* DRAM Memory Banks */ #define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) +#define PHYS_SDRAM_2 (CFG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) #define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_3 (CFG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_4 (CFG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_5 (CFG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_6 (CFG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_7 (CFG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_8 (CFG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_9 (CONFIG_SYS_SDRAM_BASE + (8 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_9 (CFG_SYS_SDRAM_BASE + (8 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_9_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_10 (CONFIG_SYS_SDRAM_BASE + (9 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_10 (CFG_SYS_SDRAM_BASE + (9 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_10_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_11 (CONFIG_SYS_SDRAM_BASE + (10 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_11 (CFG_SYS_SDRAM_BASE + (10 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_11_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_12 (CONFIG_SYS_SDRAM_BASE + (11 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_12 (CFG_SYS_SDRAM_BASE + (11 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_12_SIZE SDRAM_BANK_SIZE #ifndef MEM_LAYOUT_ENV_SETTINGS diff --git a/include/configs/galileo.h b/include/configs/galileo.h index 545408a4baa..472f236b9b6 100644 --- a/include/configs/galileo.h +++ b/include/configs/galileo.h @@ -13,7 +13,6 @@ #include <configs/x86-common.h> /* ns16550 UART is memory-mapped in Quark SoC */ -#undef CONFIG_SYS_NS16550_PORT_MAPPED #define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \ "stdout=serial\0" \ diff --git a/include/configs/gardena-smart-gateway-at91sam.h b/include/configs/gardena-smart-gateway-at91sam.h index 52b9fe2b171..89e531649a6 100644 --- a/include/configs/gardena-smart-gateway-at91sam.h +++ b/include/configs/gardena-smart-gateway-at91sam.h @@ -14,32 +14,31 @@ #endif /* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 +#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */ +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */ /* NAND flash */ -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_DBW_8 1 +#define CFG_SYS_NAND_BASE 0x40000000 /* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE BIT(21) +#define CFG_SYS_NAND_MASK_ALE BIT(21) /* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE BIT(22) -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5 +#define CFG_SYS_NAND_MASK_CLE BIT(22) +#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4 +#define CFG_SYS_NAND_READY_PIN AT91_PIN_PD5 /* SPL */ -#define CONFIG_SYS_MASTER_CLOCK 132096000 -#define CONFIG_SYS_AT91_PLLA 0x20c73f03 -#define CONFIG_SYS_MCKR 0x1301 -#define CONFIG_SYS_MCKR_CSS 0x1302 +#define CFG_SYS_MASTER_CLOCK 132096000 +#define CFG_SYS_AT91_PLLA 0x20c73f03 +#define CFG_SYS_MCKR 0x1301 +#define CFG_SYS_MCKR_CSS 0x1302 -#define CONFIG_SYS_NAND_U_BOOT_SIZE 0xa0000 -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE +#define CFG_SYS_NAND_U_BOOT_SIZE 0xa0000 +#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE #endif diff --git a/include/configs/gardena-smart-gateway-mt7688.h b/include/configs/gardena-smart-gateway-mt7688.h index 965fa87c657..0ba4efe67ac 100644 --- a/include/configs/gardena-smart-gateway-mt7688.h +++ b/include/configs/gardena-smart-gateway-mt7688.h @@ -7,27 +7,25 @@ #define __CONFIG_GARDENA_SMART_GATEWAY_H /* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 +#define CFG_SYS_INIT_SP_OFFSET 0x400000 /* SPL */ -#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE /* Dummy value */ -#define CONFIG_SYS_UBOOT_BASE 0 +#define CFG_SYS_UBOOT_BASE 0 /* Serial SPL */ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) -#define CONFIG_SYS_NS16550_MEM32 -#define CONFIG_SYS_NS16550_CLK 40000000 -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#define CONFIG_SYS_NS16550_COM1 0xb0000c00 +#define CFG_SYS_NS16550_CLK 40000000 +#define CFG_SYS_NS16550_COM1 0xb0000c00 #endif /* UART */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ +#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ 230400, 460800, 921600 } /* RAM */ diff --git a/include/configs/gazerbeam.h b/include/configs/gazerbeam.h index fa6f0e63ac5..36dcee87c5f 100644 --- a/include/configs/gazerbeam.h +++ b/include/configs/gazerbeam.h @@ -12,9 +12,9 @@ /* * DDR Setup */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -/* TODO: Check: Can this be unified with CONFIG_SYS_SDRAM_BASE? */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ +/* TODO: Check: Can this be unified with CFG_SYS_SDRAM_BASE? */ +#define CFG_SYS_DDR_SDRAM_BASE CFG_SYS_SDRAM_BASE /* * Memory test @@ -28,16 +28,16 @@ /* * Initial RAM Base Address Setup */ -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ +#define CFG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CFG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ /* * FLASH on the Local Bus */ -#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ -#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */ +#define CFG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ +#define CFG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */ -#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} /* @@ -49,7 +49,7 @@ * have to be in the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ +#define CFG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ /* * Environment Configuration diff --git a/include/configs/ge_b1x5v2.h b/include/configs/ge_b1x5v2.h index 176f80bb09b..1458b187de2 100644 --- a/include/configs/ge_b1x5v2.h +++ b/include/configs/ge_b1x5v2.h @@ -12,11 +12,6 @@ #include "mx6_common.h" -#include "imx6_spl.h" - -/* PWM */ -#define CONFIG_IMX6_PWM_PER_CLK 66000000 - /* UART */ #define CONFIG_MXC_UART_BASE UART3_BASE @@ -33,15 +28,12 @@ #define CONFIG_MXC_USB_FLAGS 0 #define CONFIG_USBD_HS -/* Video */ -#define CONFIG_IMX_VIDEO_SKIP - /* Memory */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* Command definition */ #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index d519384d026..f62b8f175e1 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -92,20 +92,14 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */ +#define CFG_SYS_BOOTMAPSZ (256 << 20) /* 256M */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* environment organization */ #define CFG_SYS_FSL_USDHC_NUM 3 -/* Framebuffer */ -#define CONFIG_IMX_HDMI -#define CONFIG_IMX_VIDEO_SKIP - -#define CONFIG_IMX6_PWM_PER_CLK 66000000 - #endif /* __GE_BX50V3_CONFIG_H */ diff --git a/include/configs/grpeach.h b/include/configs/grpeach.h index d2138c220f0..dd6b22de7ba 100644 --- a/include/configs/grpeach.h +++ b/include/configs/grpeach.h @@ -13,8 +13,8 @@ /* Miscellaneous */ /* Internal RAM Size (RZ/A1=3M, RZ/A1M=5M, RZ/A1H=10M) */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE (10 * 1024 * 1024) +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE (10 * 1024 * 1024) /* Network interface */ #define CONFIG_SH_ETHER_USE_PORT 0 diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index a9ef35ebeb6..4d0a78c6269 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -13,7 +13,6 @@ /* Falcon Mode - MMC support: args@1MB kernel@2MB */ -#include "imx6_spl.h" /* common IMX6 SPL configuration */ #include "mx6_common.h" /* Serial */ @@ -31,9 +30,7 @@ /* * PMIC */ -#define CONFIG_POWER_PFUZE100 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 -#define CONFIG_POWER_LTC3676 #define CONFIG_POWER_LTC3676_I2C_ADDR 0x3c /* Various command support */ @@ -43,20 +40,15 @@ #define CONFIG_MXC_USB_FLAGS 0 #define CONFIG_USBD_HS -/* Framebuffer and LCD */ -#define CONFIG_IMX_HDMI -#define CONFIG_IMX_VIDEO_SKIP - /* Miscellaneous configurable options */ -#define CONFIG_HWCONFIG /* Memory configuration */ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* * MTD Command for mtdparts diff --git a/include/configs/gxp.h b/include/configs/gxp.h index e3c97b20d51..2b0b04891cc 100644 --- a/include/configs/gxp.h +++ b/include/configs/gxp.h @@ -10,6 +10,6 @@ #ifndef _GXP_H_ #define _GXP_H_ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #endif diff --git a/include/configs/harmony.h b/include/configs/harmony.h index fe4b02c0ce2..211dab4d233 100644 --- a/include/configs/harmony.h +++ b/include/configs/harmony.h @@ -17,10 +17,10 @@ #define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: keyboard satellite board UART, default */ -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE #ifdef CONFIG_TEGRA_ENABLE_UARTA /* UARTA: debug board UART */ -#define CONFIG_SYS_NS16550_COM2 NV_PA_APB_UARTA_BASE +#define CFG_SYS_NS16550_COM2 NV_PA_APB_UARTA_BASE #endif /* NAND support */ diff --git a/include/configs/highbank.h b/include/configs/highbank.h index 5e2b50bbac1..4aef0b4abd1 100644 --- a/include/configs/highbank.h +++ b/include/configs/highbank.h @@ -6,7 +6,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_BOOTMAPSZ (16 << 20) +#define CFG_SYS_BOOTMAPSZ (16 << 20) #define CONFIG_PL011_CLOCK 150000000 @@ -14,12 +14,7 @@ * Miscellaneous configurable options */ -/* Environment data setup -*/ -#define CONFIG_SYS_NVRAM_BASE_ADDR 0xfff88000 /* NVRAM base address */ -#define CONFIG_SYS_NVRAM_SIZE 0x8000 /* NVRAM size */ - -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 #define CONFIG_EXTRA_ENV_SETTINGS \ "fdt_high=0x20000000\0" \ diff --git a/include/configs/hikey.h b/include/configs/hikey.h index 18c1e83aeb4..d4280decc9f 100644 --- a/include/configs/hikey.h +++ b/include/configs/hikey.h @@ -13,8 +13,6 @@ #include <linux/sizes.h> -#define CONFIG_POWER_HI6553 - /* Physical Memory Map */ /* CONFIG_TEXT_BASE needs to align with where ATF loads bl33.bin */ @@ -24,16 +22,14 @@ /* 1008 MB (the last 16Mb are secured for TrustZone by ATF*/ #define PHYS_SDRAM_1_SIZE 0x3EFFFFFF -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 +#define CFG_SYS_INIT_RAM_SIZE 0x1000 /* Generic Interrupt Controller Definitions */ #define GICD_BASE 0xf6801000 #define GICC_BASE 0xf6802000 -#define CONFIG_HIKEY_GPIO - /* Initial environment variables */ /* diff --git a/include/configs/hikey960.h b/include/configs/hikey960.h index 973df8e4abc..fad1f980481 100644 --- a/include/configs/hikey960.h +++ b/include/configs/hikey960.h @@ -16,9 +16,9 @@ #define PHYS_SDRAM_1 0x00000000 #define PHYS_SDRAM_1_SIZE 0xC0000000 -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 +#define CFG_SYS_INIT_RAM_SIZE 0x1000 /* Generic Interrupt Controller Definitions */ #define GICD_BASE 0xe82b1000 diff --git a/include/configs/hsdk-4xd.h b/include/configs/hsdk-4xd.h index 4af845ea9c2..59ea8960071 100644 --- a/include/configs/hsdk-4xd.h +++ b/include/configs/hsdk-4xd.h @@ -21,16 +21,14 @@ * Memory configuration */ -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SDRAM_SIZE SZ_1G +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_SIZE SZ_1G /* * UART configuration */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_CLK 33330000 -#define CONFIG_SYS_NS16550_MEM32 +#define CFG_SYS_NS16550_CLK 33330000 /* * Ethernet PHY configuration diff --git a/include/configs/hsdk.h b/include/configs/hsdk.h index 0ce65e7755e..fbfcded4712 100644 --- a/include/configs/hsdk.h +++ b/include/configs/hsdk.h @@ -20,16 +20,14 @@ * Memory configuration */ -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SDRAM_SIZE SZ_1G +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_SIZE SZ_1G /* * UART configuration */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_CLK 33330000 -#define CONFIG_SYS_NS16550_MEM32 +#define CFG_SYS_NS16550_CLK 33330000 /* * Ethernet PHY configuration diff --git a/include/configs/imgtec_xilfpga.h b/include/configs/imgtec_xilfpga.h index 1fc45f9060b..f1ca28b7ca3 100644 --- a/include/configs/imgtec_xilfpga.h +++ b/include/configs/imgtec_xilfpga.h @@ -21,8 +21,8 @@ */ /* SDRAM Configuration (for final code, data, stack, heap) */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 Mbytes */ +#define CFG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_SIZE 0x08000000 /* 128 Mbytes */ /*---------------------------------------------------------------------- * Commands diff --git a/include/configs/imx27lite-common.h b/include/configs/imx27lite-common.h deleted file mode 100644 index 232f7868cc2..00000000000 --- a/include/configs/imx27lite-common.h +++ /dev/null @@ -1,134 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2010 Heiko Schocher <hs@denx.de> - * - * based on: - * Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com> - */ - -#ifndef __IMX27LITE_COMMON_CONFIG_H -#define __IMX27LITE_COMMON_CONFIG_H - -/* - * SoC Configuration - */ -#define CONFIG_MX27 -#define CONFIG_MX27_CLK32 32768 /* OSC32K frequency */ - -/* - * Lowlevel configuration - */ -#define SDRAM_ESDCFG_REGISTER_VAL(cas) \ - (ESDCFG_TRC(10) | \ - ESDCFG_TRCD(3) | \ - ESDCFG_TCAS(cas) | \ - ESDCFG_TRRD(1) | \ - ESDCFG_TRAS(5) | \ - ESDCFG_TWR | \ - ESDCFG_TMRD(2) | \ - ESDCFG_TRP(2) | \ - ESDCFG_TXP(3)) - -#define SDRAM_ESDCTL_REGISTER_VAL \ - (ESDCTL_PRCT(0) | \ - ESDCTL_BL | \ - ESDCTL_PWDT(0) | \ - ESDCTL_SREFR(3) | \ - ESDCTL_DSIZ_32 | \ - ESDCTL_COL10 | \ - ESDCTL_ROW13 | \ - ESDCTL_SDE) - -#define SDRAM_ALL_VAL 0xf00 - -#define SDRAM_MODE_REGISTER_VAL 0x33 /* BL: 8, CAS: 3 */ -#define SDRAM_EXT_MODE_REGISTER_VAL 0x1000000 - -#define MPCTL0_VAL 0x1ef15d5 - -#define SPCTL0_VAL 0x043a1c09 - -#define CSCR_VAL 0x33f08107 - -#define PCDR0_VAL 0x120470c3 -#define PCDR1_VAL 0x03030303 -#define PCCR0_VAL 0xffffffff -#define PCCR1_VAL 0xfffffffc - -#define AIPI1_PSR0_VAL 0x20040304 -#define AIPI1_PSR1_VAL 0xdffbfcfb -#define AIPI2_PSR0_VAL 0x07ffc200 -#define AIPI2_PSR1_VAL 0xffffffff - -/* - * Memory Info - */ -/* memtest start address */ -#define PHYS_SDRAM_1 0xA0000000 /* DDR Start */ -#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */ - -/* - * Serial Driver info - */ -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1) - -/* - * Flash & Environment - */ -/* Use buffered writes (~10x faster) */ -/* Use hardware sector protection */ -/* CS2 Base address */ -#define PHYS_FLASH_1 0xc0000000 -/* Flash Base for U-Boot */ -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -/* Address and size of Redundant Environment Sector */ - -/* - * Ethernet - */ -#define CONFIG_FEC_MXC_PHYADDR 0x1f - -/* - * MTD - */ - -/* - * NAND - */ -#define CONFIG_MXC_NAND_REGS_BASE 0xd8000000 -#define CONFIG_SYS_NAND_BASE 0xd8000000 -#define CONFIG_MXC_NAND_HWECC - -/* - * U-Boot general configuration - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs}" \ - " console=ttymxc0,${baudrate}\0" \ - "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "addmisc=setenv bootargs ${bootargs}\0" \ - "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \ - "kernel_addr_r=a0800000\0" \ - "bootfile=" CONFIG_HOSTNAME "/uImage\0" \ - "rootpath=/opt/eldk-4.2-arm/arm\0" \ - "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ - "run nfsargs addip addtty addmtd addmisc;" \ - "bootm\0" \ - "bootcmd=run net_nfs\0" \ - "load=tftp ${loadaddr} ${u-boot}\0" \ - "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ - " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ - " +${filesize};cp.b ${fileaddr} " \ - __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ - "upd=run load update\0" \ - -/* additions for new relocation code, must be added to all boards */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#endif /* __IMX27LITE_COMMON_CONFIG_H */ diff --git a/include/configs/imx6-engicam.h b/include/configs/imx6-engicam.h index f52367cc1a0..36b6b95b84d 100644 --- a/include/configs/imx6-engicam.h +++ b/include/configs/imx6-engicam.h @@ -109,9 +109,9 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* UART */ #ifdef CONFIG_MXC_UART @@ -126,25 +126,10 @@ /* NAND */ #ifdef CONFIG_NAND_MXS -# define CONFIG_SYS_NAND_BASE 0x40000000 -# define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE +# define CFG_SYS_NAND_BASE 0x40000000 +# define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE /* MTD device */ #endif -/* Falcon Mode */ -#ifdef CONFIG_SPL_OS_BOOT -/* MMC support: args@1MB kernel@2MB */ -#endif - -/* Framebuffer */ -#ifdef CONFIG_VIDEO_IPUV3 -# define CONFIG_IMX_VIDEO_SKIP -#endif - -/* SPL */ -#ifdef CONFIG_SPL -# include "imx6_spl.h" -#endif - #endif /* __IMX6_ENGICAM_CONFIG_H */ diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h index 008fc079a65..4e23f1a2dc5 100644 --- a/include/configs/imx6_logic.h +++ b/include/configs/imx6_logic.h @@ -11,10 +11,6 @@ #define CONFIG_MXC_UART_BASE UART1_BASE #define CONSOLE_DEV "ttymxc0" -#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - #include "mx6_common.h" /* MMC Configs */ @@ -109,15 +105,15 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* Environment organization */ /* NAND stuff */ -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_NAND_BASE 0x40000000 +#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE /* USB Configs */ #ifdef CONFIG_CMD_USB diff --git a/include/configs/imx6_spl.h b/include/configs/imx6_spl.h deleted file mode 100644 index 3afe418b67d..00000000000 --- a/include/configs/imx6_spl.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014 Gateworks Corporation - * Author: Tim Harvey <tharvey@gateworks.com> - */ -#ifndef __IMX6_SPL_CONFIG_H -#define __IMX6_SPL_CONFIG_H - -#ifdef CONFIG_SPL - -/* MMC support */ - -/* SATA support */ -#if defined(CONFIG_SPL_SATA) -#define CONFIG_SYS_SATA_FAT_BOOT_PARTITION 1 -#endif - -#endif - -#endif diff --git a/include/configs/imx6dl-mamoj.h b/include/configs/imx6dl-mamoj.h index 909453cd66f..402f83c18ea 100644 --- a/include/configs/imx6dl-mamoj.h +++ b/include/configs/imx6dl-mamoj.h @@ -55,11 +55,8 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -/* SPL */ -#include "imx6_spl.h" +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE #endif /* __IMX6DL_MAMOJ_CONFIG_H */ diff --git a/include/configs/imx6q-bosch-acc.h b/include/configs/imx6q-bosch-acc.h index 5025ad9d9f2..99da081cdae 100644 --- a/include/configs/imx6q-bosch-acc.h +++ b/include/configs/imx6q-bosch-acc.h @@ -85,13 +85,12 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* SPL */ #ifdef CONFIG_SPL -#include "imx6_spl.h" #ifdef CONFIG_SPL_BUILD #define CFG_SYS_FSL_USDHC_NUM 2 diff --git a/include/configs/imx6ulz_smm_m2.h b/include/configs/imx6ulz_smm_m2.h index 46a96f1f828..2d9d3c34b0d 100644 --- a/include/configs/imx6ulz_smm_m2.h +++ b/include/configs/imx6ulz_smm_m2.h @@ -12,9 +12,6 @@ #include <linux/sizes.h> #include <linux/stringify.h> -/* SPL options */ -#include "imx6_spl.h" - #define CONFIG_MXC_UART_BASE UART4_BASE #ifndef CONFIG_SPL_BUILD @@ -66,12 +63,12 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define PHYS_SDRAM_SIZE SZ_128M -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* NAND */ -#define CONFIG_SYS_NAND_BASE 0x20000000 +#define CFG_SYS_NAND_BASE 0x20000000 #endif diff --git a/include/configs/imx7-cm.h b/include/configs/imx7-cm.h index caa6a11d407..76771fd66ce 100644 --- a/include/configs/imx7-cm.h +++ b/include/configs/imx7-cm.h @@ -69,9 +69,9 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* MMC Config*/ #define CFG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR @@ -83,7 +83,4 @@ #define CONFIG_USBD_HS -/* SPL */ -#include "imx7_spl.h" - #endif /* __CONFIG_H */ diff --git a/include/configs/imx7_spl.h b/include/configs/imx7_spl.h deleted file mode 100644 index 362b98075f0..00000000000 --- a/include/configs/imx7_spl.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * SPL definitions for the i.MX7 SPL - * - * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com - * - * Author: Uri Mashiach <uri.mashiach@compulab.co.il> - */ - -#ifndef __IMX7_SPL_CONFIG_H -#define __IMX7_SPL_CONFIG_H - -#ifdef CONFIG_SPL - -/* MMC support */ - -#endif /* CONFIG_SPL */ - -#endif /* __IMX7_SPL_CONFIG_H */ diff --git a/include/configs/imx8mm-cl-iot-gate.h b/include/configs/imx8mm-cl-iot-gate.h index 917d567d2ec..c228cf7f37b 100644 --- a/include/configs/imx8mm-cl-iot-gate.h +++ b/include/configs/imx8mm-cl-iot-gate.h @@ -11,7 +11,7 @@ #include <asm/arch/imx-regs.h> #include <config_distro_bootcmd.h> -#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD @@ -123,11 +123,11 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x80000 -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ diff --git a/include/configs/imx8mm_beacon.h b/include/configs/imx8mm_beacon.h index 8e088994580..03325e6c3a7 100644 --- a/include/configs/imx8mm_beacon.h +++ b/include/configs/imx8mm_beacon.h @@ -9,7 +9,7 @@ #include <linux/sizes.h> #include <asm/arch/imx-regs.h> -#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD @@ -71,10 +71,10 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x200000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x200000 -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ diff --git a/include/configs/imx8mm_data_modul_edm_sbc.h b/include/configs/imx8mm_data_modul_edm_sbc.h index dd9f93f35c2..80321cf2d8d 100644 --- a/include/configs/imx8mm_data_modul_edm_sbc.h +++ b/include/configs/imx8mm_data_modul_edm_sbc.h @@ -18,10 +18,10 @@ #endif /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x200000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x200000 -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x40000000 /* Minimum 1 GiB DDR */ diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h index f1d1c1c9c3d..8a694c88a53 100644 --- a/include/configs/imx8mm_evk.h +++ b/include/configs/imx8mm_evk.h @@ -15,10 +15,10 @@ #define UBOOT_ITB_OFFSET_FSPI \ (UBOOT_ITB_OFFSET + FSPI_CONF_BLOCK_SIZE) #ifdef CONFIG_FSPI_CONF_HEADER -#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + UBOOT_ITB_OFFSET_FSPI) #else -#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #endif @@ -53,11 +53,11 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x200000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x200000 -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ diff --git a/include/configs/imx8mm_icore_mx8mm.h b/include/configs/imx8mm_icore_mx8mm.h index 9cdba70493b..41ab9307793 100644 --- a/include/configs/imx8mm_icore_mx8mm.h +++ b/include/configs/imx8mm_icore_mx8mm.h @@ -10,7 +10,7 @@ #include <linux/sizes.h> #include <asm/arch/imx-regs.h> -#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD @@ -38,10 +38,10 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE SZ_2M +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE SZ_2M -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 /* SDRAM configuration */ #define PHYS_SDRAM 0x40000000 diff --git a/include/configs/imx8mm_venice.h b/include/configs/imx8mm_venice.h index 065356341fc..28ce834769c 100644 --- a/include/configs/imx8mm_venice.h +++ b/include/configs/imx8mm_venice.h @@ -9,7 +9,7 @@ #include <asm/arch/imx-regs.h> #include <linux/sizes.h> -#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD @@ -29,10 +29,10 @@ "splblk=0x42\0" \ BOOTENV -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE SZ_2M +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE SZ_2M -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 /* SDRAM configuration */ #define PHYS_SDRAM 0x40000000 diff --git a/include/configs/imx8mn_beacon.h b/include/configs/imx8mn_beacon.h index 0ae3da12ad3..85fd5e2371f 100644 --- a/include/configs/imx8mn_beacon.h +++ b/include/configs/imx8mn_beacon.h @@ -9,7 +9,7 @@ #include <linux/sizes.h> #include <asm/arch/imx-regs.h> -#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) /* Initial environment variables */ @@ -75,10 +75,10 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x200000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x200000 -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #if CONFIG_IS_ENABLED(IMX8MN_BEACON_2GB_LPDDR) #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ diff --git a/include/configs/imx8mn_bsh_smm_s2.h b/include/configs/imx8mn_bsh_smm_s2.h index a2323bd6716..a768ff35510 100644 --- a/include/configs/imx8mn_bsh_smm_s2.h +++ b/include/configs/imx8mn_bsh_smm_s2.h @@ -44,6 +44,6 @@ /* NAND */ -#define CONFIG_SYS_NAND_BASE 0x20000000 +#define CFG_SYS_NAND_BASE 0x20000000 #endif /* __IMX8MN_BSH_SMM_S2_H */ diff --git a/include/configs/imx8mn_bsh_smm_s2_common.h b/include/configs/imx8mn_bsh_smm_s2_common.h index d6959ac95a1..204fc4b3164 100644 --- a/include/configs/imx8mn_bsh_smm_s2_common.h +++ b/include/configs/imx8mn_bsh_smm_s2_common.h @@ -10,7 +10,7 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h> -#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #define MEM_LAYOUT_ENV_SETTINGS \ @@ -23,10 +23,10 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE SZ_512K +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE SZ_512K -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #endif /* __IMX8MN_BSH_SMM_S2_COMMON_H */ diff --git a/include/configs/imx8mn_evk.h b/include/configs/imx8mn_evk.h index 9c75e3eec15..024b86c7f1d 100644 --- a/include/configs/imx8mn_evk.h +++ b/include/configs/imx8mn_evk.h @@ -10,7 +10,7 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h> -#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #define BOOT_TARGET_DEVICES(func) \ @@ -45,11 +45,11 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x200000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x200000 -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ diff --git a/include/configs/imx8mn_var_som.h b/include/configs/imx8mn_var_som.h index a484d913649..4633843d1bb 100644 --- a/include/configs/imx8mn_var_som.h +++ b/include/configs/imx8mn_var_som.h @@ -10,7 +10,7 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h> -#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #define BOOT_TARGET_DEVICES(func) \ @@ -43,10 +43,10 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE SZ_512K +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE SZ_512K -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE SZ_1G /* 1GB DDR */ diff --git a/include/configs/imx8mn_venice.h b/include/configs/imx8mn_venice.h index d5252abb218..a585cbf87e4 100644 --- a/include/configs/imx8mn_venice.h +++ b/include/configs/imx8mn_venice.h @@ -9,7 +9,7 @@ #include <asm/arch/imx-regs.h> #include <linux/sizes.h> -#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) /* Enable Distro Boot */ @@ -23,10 +23,10 @@ "splblk=0x40\0" \ BOOTENV -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE SZ_2M +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE SZ_2M -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 /* SDRAM configuration */ #define PHYS_SDRAM 0x40000000 diff --git a/include/configs/imx8mp_dhcom_pdk2.h b/include/configs/imx8mp_dhcom_pdk2.h index bf878251364..5443022b04c 100644 --- a/include/configs/imx8mp_dhcom_pdk2.h +++ b/include/configs/imx8mp_dhcom_pdk2.h @@ -11,10 +11,10 @@ #include <asm/arch/imx-regs.h> /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x200000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x200000 -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x20000000 /* Minimum 512 MiB DDR */ diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h index 1b533e2c142..738677ff37c 100644 --- a/include/configs/imx8mp_evk.h +++ b/include/configs/imx8mp_evk.h @@ -10,7 +10,7 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h> -#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) +#define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ @@ -50,12 +50,12 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x80000 /* Totally 2GB DDR */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 diff --git a/include/configs/imx8mp_icore_mx8mp.h b/include/configs/imx8mp_icore_mx8mp.h index 7986d20eed1..d67bad8971d 100644 --- a/include/configs/imx8mp_icore_mx8mp.h +++ b/include/configs/imx8mp_icore_mx8mp.h @@ -11,7 +11,7 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h> -#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) +#define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ @@ -52,11 +52,11 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x80000 /* Totally 2GB DDR */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 diff --git a/include/configs/imx8mp_rsb3720.h b/include/configs/imx8mp_rsb3720.h index 5be46090a14..58f7dc6518c 100644 --- a/include/configs/imx8mp_rsb3720.h +++ b/include/configs/imx8mp_rsb3720.h @@ -12,7 +12,7 @@ #include <asm/arch/imx-regs.h> #include <config_distro_bootcmd.h> -#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) +#define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) /* GUIDs for capsule updatable firmware images */ #define IMX8MP_RSB3720A1_4G_FIT_IMAGE_GUID \ @@ -131,12 +131,12 @@ "fi;\0" /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x80000 /* Totally 6GB or 4G DDR */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #if defined(CONFIG_TARGET_IMX8MP_RSB3720A1_6G) #define PHYS_SDRAM_SIZE 0xC0000000 /* 3 GB */ @@ -166,7 +166,7 @@ #ifdef CONFIG_NAND_MXS /* NAND stuff */ -#define CONFIG_SYS_NAND_BASE 0x20000000 +#define CFG_SYS_NAND_BASE 0x20000000 #endif /* CONFIG_NAND_MXS */ #endif /* __IMX8MP_RSB3720_H */ diff --git a/include/configs/imx8mp_venice.h b/include/configs/imx8mp_venice.h index b1c213cc89b..e79aa570753 100644 --- a/include/configs/imx8mp_venice.h +++ b/include/configs/imx8mp_venice.h @@ -9,7 +9,7 @@ #include <asm/arch/imx-regs.h> #include <linux/sizes.h> -#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) /* Enable Distro Boot */ @@ -23,10 +23,10 @@ "splblk=0x40\0" \ BOOTENV -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE SZ_2M +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE SZ_2M -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 /* SDRAM configuration */ #define PHYS_SDRAM 0x40000000 diff --git a/include/configs/imx8mq_cm.h b/include/configs/imx8mq_cm.h index 4b2107e4057..4df98e3f373 100644 --- a/include/configs/imx8mq_cm.h +++ b/include/configs/imx8mq_cm.h @@ -46,11 +46,11 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x80000 -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x40000000 /* 1 GB DDR */ diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h index 2d4c8d78c67..688c0bf7008 100644 --- a/include/configs/imx8mq_evk.h +++ b/include/configs/imx8mq_evk.h @@ -18,7 +18,6 @@ #define CONFIG_MALLOC_F_ADDR 0x182000 /* For RAW image gives a error info not panic */ -#define CONFIG_POWER_PFUZE100 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 #endif @@ -52,11 +51,11 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x80000 -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */ diff --git a/include/configs/imx8mq_phanbell.h b/include/configs/imx8mq_phanbell.h index 1905e538c5b..3b4cd656223 100644 --- a/include/configs/imx8mq_phanbell.h +++ b/include/configs/imx8mq_phanbell.h @@ -84,11 +84,11 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x80000 -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x40000000 /* 1GB DDR */ diff --git a/include/configs/imx8qm_mek.h b/include/configs/imx8qm_mek.h index 7f6d59db3aa..f1f907f3e5a 100644 --- a/include/configs/imx8qm_mek.h +++ b/include/configs/imx8qm_mek.h @@ -103,7 +103,7 @@ /* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_2 0x880000000 #define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */ diff --git a/include/configs/imx8qm_rom7720.h b/include/configs/imx8qm_rom7720.h index 67f19bc1922..2e2e5ed43cd 100644 --- a/include/configs/imx8qm_rom7720.h +++ b/include/configs/imx8qm_rom7720.h @@ -10,7 +10,7 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h> -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) +#define CFG_SYS_BOOTMAPSZ (256 << 20) #define CFG_SYS_FSL_ESDHC_ADDR 0 #define USDHC1_BASE_ADDR 0x5B010000 #define USDHC2_BASE_ADDR 0x5B020000 @@ -108,7 +108,7 @@ */ #define CFG_SYS_FSL_USDHC_NUM 3 -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_2 0x880000000 #define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */ diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h index 567351fcad6..d75b8bf0c18 100644 --- a/include/configs/imx8qxp_mek.h +++ b/include/configs/imx8qxp_mek.h @@ -103,17 +103,13 @@ /* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_2 0x880000000 #define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */ /* LPDDR4 board total DDR is 3GB */ #define PHYS_SDRAM_2_SIZE 0x40000000 /* 1 GB */ -#ifndef CONFIG_DM_PCA953X -#define CONFIG_PCA953X -#endif - /* Misc configuration */ #endif /* __IMX8QXP_MEK_H */ diff --git a/include/configs/imx8ulp_evk.h b/include/configs/imx8ulp_evk.h index 7bf0ce784c5..d313bdc2a44 100644 --- a/include/configs/imx8ulp_evk.h +++ b/include/configs/imx8ulp_evk.h @@ -9,7 +9,7 @@ #include <linux/sizes.h> #include <asm/arch/imx-regs.h> -#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) +#define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD #define CONFIG_MALLOC_F_ADDR 0x22040000 @@ -50,11 +50,11 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CFG_SYS_INIT_RAM_ADDR 0x80000000 +#define CFG_SYS_INIT_RAM_SIZE 0x80000 -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM 0x80000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ diff --git a/include/configs/imx93_evk.h b/include/configs/imx93_evk.h index b2814664086..895c50f6025 100644 --- a/include/configs/imx93_evk.h +++ b/include/configs/imx93_evk.h @@ -10,7 +10,7 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h> -#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD @@ -124,10 +124,10 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x200000 +#define CFG_SYS_INIT_RAM_ADDR 0x80000000 +#define CFG_SYS_INIT_RAM_SIZE 0x200000 -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM 0x80000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ diff --git a/include/configs/imxrt1020-evk.h b/include/configs/imxrt1020-evk.h index a2c004880a7..e180387c687 100644 --- a/include/configs/imxrt1020-evk.h +++ b/include/configs/imxrt1020-evk.h @@ -22,6 +22,6 @@ * Configuration of the external SDRAM memory */ -#define CONFIG_SYS_UBOOT_START 0x800023FD +#define CFG_SYS_UBOOT_START 0x800023FD #endif /* __IMXRT1020_EVK_H */ diff --git a/include/configs/imxrt1050-evk.h b/include/configs/imxrt1050-evk.h index d1a7dab37c5..84228676c7f 100644 --- a/include/configs/imxrt1050-evk.h +++ b/include/configs/imxrt1050-evk.h @@ -29,6 +29,6 @@ * Configuration of the external SDRAM memory */ -#define CONFIG_SYS_UBOOT_START 0x800023FD +#define CFG_SYS_UBOOT_START 0x800023FD #endif /* __IMXRT1050_EVK_H */ diff --git a/include/configs/imxrt1170-evk.h b/include/configs/imxrt1170-evk.h index 2459fe24e24..f83429082ac 100644 --- a/include/configs/imxrt1170-evk.h +++ b/include/configs/imxrt1170-evk.h @@ -23,7 +23,7 @@ #define DMAMEM_BASE (PHYS_SDRAM + PHYS_SDRAM_SIZE - \ DMAMEM_SZ_ALL) /* For SPL */ -#define CONFIG_SYS_UBOOT_START 0x202403FD +#define CFG_SYS_UBOOT_START 0x202403FD /* For SPL ends */ #endif /* __IMXRT1170_EVK_H */ diff --git a/include/configs/integrator-common.h b/include/configs/integrator-common.h index 512e0e61aa7..7a55c6aeefc 100644 --- a/include/configs/integrator-common.h +++ b/include/configs/integrator-common.h @@ -6,7 +6,7 @@ * Common ARM Integrator configuration settings */ -#define CONFIG_SYS_TIMERBASE 0x13000100 /* Timer1 */ +#define CFG_SYS_TIMERBASE 0x13000100 /* Timer1 */ /* * The ARM boot monitor initializes the board. @@ -30,7 +30,7 @@ */ #define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 /* * FLASH and environment organization @@ -41,6 +41,6 @@ * - SIB block * - U-Boot environment */ -#define CONFIG_SYS_FLASH_BASE 0x24000000 +#define CFG_SYS_FLASH_BASE 0x24000000 /* Timeout values in ticks */ diff --git a/include/configs/integratorap.h b/include/configs/integratorap.h index c8457d97161..6bee098d6a8 100644 --- a/include/configs/integratorap.h +++ b/include/configs/integratorap.h @@ -17,10 +17,10 @@ #include "integrator-common.h" /* Integrator/AP-specific configuration */ -#define CONFIG_SYS_HZ_CLOCK 24000000 /* Timer 1 is clocked at 24Mhz */ +#define CFG_SYS_HZ_CLOCK 24000000 /* Timer 1 is clocked at 24Mhz */ /* Flash settings */ -#define CONFIG_SYS_FLASH_SIZE 0x02000000 /* 32 MiB */ +#define CFG_SYS_FLASH_SIZE 0x02000000 /* 32 MiB */ /*----------------------------------------------------------------------- * PCI definitions diff --git a/include/configs/integratorcp.h b/include/configs/integratorcp.h index bf09510d02f..25bb41ebc46 100644 --- a/include/configs/integratorcp.h +++ b/include/configs/integratorcp.h @@ -17,7 +17,7 @@ #include "integrator-common.h" /* Integrator CP-specific configuration */ -#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer 1 is clocked at 1Mhz */ +#define CFG_SYS_HZ_CLOCK 1000000 /* Timer 1 is clocked at 1Mhz */ #define CONFIG_SERVERIP 192.168.1.100 #define CONFIG_IPADDR 192.168.1.104 diff --git a/include/configs/iot_devkit.h b/include/configs/iot_devkit.h index a2e50c3b8df..5a769e07871 100644 --- a/include/configs/iot_devkit.h +++ b/include/configs/iot_devkit.h @@ -32,12 +32,12 @@ * : : * : Specified explicitly by CONFIG_CUSTOM_SYS_INIT_SP_ADDR * : - * Specified explicitly by CONFIG_SYS_SDRAM_BASE + * Specified explicitly by CFG_SYS_SDRAM_BASE * * NOTES: * - Stack starts from CONFIG_CUSTOM_SYS_INIT_SP_ADDR and grows down, - * i.e. towards CONFIG_SYS_SDRAM_BASE but nothing stops it from crossing - * that CONFIG_SYS_SDRAM_BASE in which case data won't be really saved on + * i.e. towards CFG_SYS_SDRAM_BASE but nothing stops it from crossing + * that CFG_SYS_SDRAM_BASE in which case data won't be really saved on * stack any longer and values popped from stack will contain garbage * leading to unexpected behavior, typically but not limited to: * - "Returning" back to bogus caller function @@ -50,16 +50,16 @@ #define DCCM_BASE 0x80000000 #define DCCM_SIZE SZ_128K -#define CONFIG_SYS_SDRAM_BASE DCCM_BASE -#define CONFIG_SYS_SDRAM_SIZE DCCM_SIZE +#define CFG_SYS_SDRAM_BASE DCCM_BASE +#define CFG_SYS_SDRAM_SIZE DCCM_SIZE #define ROM_BASE CONFIG_SYS_MONITOR_BASE #define ROM_SIZE SZ_256K #define RAM_DATA_BASE SYS_INIT_SP_ADDR -#define RAM_DATA_SIZE CONFIG_SYS_SDRAM_SIZE - \ +#define RAM_DATA_SIZE CFG_SYS_SDRAM_SIZE - \ (SYS_INIT_SP_ADDR - \ - CONFIG_SYS_SDRAM_BASE) - \ + CFG_SYS_SDRAM_BASE) - \ CONFIG_SYS_MALLOC_LEN - \ CONFIG_ENV_SIZE #endif /* _CONFIG_IOT_DEVKIT_H_ */ diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h index 9f54f259994..e66f994a375 100644 --- a/include/configs/j721e_evm.h +++ b/include/configs/j721e_evm.h @@ -16,16 +16,16 @@ #include <environment/ti/k3_dfu.h> /* DDR Configuration */ -#define CONFIG_SYS_SDRAM_BASE1 0x880000000 +#define CFG_SYS_SDRAM_BASE1 0x880000000 /* FLASH Configuration */ -#define CONFIG_SYS_FLASH_BASE 0x000000000 +#define CFG_SYS_FLASH_BASE 0x000000000 /* SPL Loader Configuration */ #if defined(CONFIG_TARGET_J721E_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM) -#define CONFIG_SYS_UBOOT_BASE 0x50280000 +#define CFG_SYS_UBOOT_BASE 0x50280000 /* Image load address in RAM for DFU boot*/ #else -#define CONFIG_SYS_UBOOT_BASE 0x50080000 +#define CFG_SYS_UBOOT_BASE 0x50080000 #endif /* HyperFlash related configuration */ diff --git a/include/configs/j721s2_evm.h b/include/configs/j721s2_evm.h index 932d7d3c8cb..ab204c62b7d 100644 --- a/include/configs/j721s2_evm.h +++ b/include/configs/j721s2_evm.h @@ -17,14 +17,14 @@ #include <environment/ti/k3_dfu.h> /* DDR Configuration */ -#define CONFIG_SYS_SDRAM_BASE1 0x880000000 +#define CFG_SYS_SDRAM_BASE1 0x880000000 /* SPL Loader Configuration */ #if defined(CONFIG_TARGET_J721S2_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM) -#define CONFIG_SYS_UBOOT_BASE 0x50280000 +#define CFG_SYS_UBOOT_BASE 0x50280000 /* Image load address in RAM for DFU boot*/ #else -#define CONFIG_SYS_UBOOT_BASE 0x50080000 +#define CFG_SYS_UBOOT_BASE 0x50080000 #endif /* U-Boot general configuration */ diff --git a/include/configs/jetson-tk1.h b/include/configs/jetson-tk1.h index 69aa55f86c5..b846889541c 100644 --- a/include/configs/jetson-tk1.h +++ b/include/configs/jetson-tk1.h @@ -16,7 +16,7 @@ /* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTD -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE /* Environment in eMMC, at the end of 2nd "boot sector" */ diff --git a/include/configs/k2e_evm.h b/include/configs/k2e_evm.h index 9b25c349822..bbc58be511e 100644 --- a/include/configs/k2e_evm.h +++ b/include/configs/k2e_evm.h @@ -36,9 +36,6 @@ #define SPI_MTD_PARTS KEYSTONE_SPI0_MTD_PARTS -/* NAND Configuration */ -#define CONFIG_SYS_NAND_PAGE_2K - /* Network */ #define CONFIG_KSNET_NETCP_V1_5 #define CONFIG_KSNET_CPSW_NUM_PORTS 9 diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h index 887fda90d6a..bb91751d5d9 100644 --- a/include/configs/k2g_evm.h +++ b/include/configs/k2g_evm.h @@ -50,9 +50,6 @@ "get_mon_mmc=load mmc ${bootpart} ${addr_mon} ${bootdir}/${name_mon}\0"\ "name_fs=arago-base-tisdk-image-k2g-evm.cpio\0" -/* NAND Configuration */ -#define CONFIG_SYS_NAND_PAGE_2K - /* Network */ #define CONFIG_KSNET_NETCP_V1_5 #define CONFIG_KSNET_CPSW_NUM_PORTS 2 diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h index cfc34c7da6d..68cbe98b553 100644 --- a/include/configs/k2hk_evm.h +++ b/include/configs/k2hk_evm.h @@ -36,9 +36,6 @@ #define SPI_MTD_PARTS KEYSTONE_SPI0_MTD_PARTS -/* NAND Configuration */ -#define CONFIG_SYS_NAND_PAGE_2K - /* Network */ #define CONFIG_KSNET_NETCP_V1_0 #define CONFIG_KSNET_CPSW_NUM_PORTS 5 diff --git a/include/configs/k2l_evm.h b/include/configs/k2l_evm.h index 65988fff06e..a18158a7eb3 100644 --- a/include/configs/k2l_evm.h +++ b/include/configs/k2l_evm.h @@ -36,9 +36,6 @@ #define SPI_MTD_PARTS KEYSTONE_SPI0_MTD_PARTS -/* NAND Configuration */ -#define CONFIG_SYS_NAND_PAGE_4K - /* Network */ #define CONFIG_KSNET_NETCP_V1_5 #define CONFIG_KSNET_CPSW_NUM_PORTS 5 diff --git a/include/configs/km/keymile-common.h b/include/configs/km/keymile-common.h index 35cf27a2eb9..cc5ec219b8d 100644 --- a/include/configs/km/keymile-common.h +++ b/include/configs/km/keymile-common.h @@ -13,7 +13,7 @@ * Miscellaneous configurable options */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } +#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } #ifndef CONFIG_KM_DEF_ENV_BOOTPARAMS #define CONFIG_KM_DEF_ENV_BOOTPARAMS \ diff --git a/include/configs/km/km-mpc832x.h b/include/configs/km/km-mpc832x.h index 888bb2981f7..f64c0eee1bb 100644 --- a/include/configs/km/km-mpc832x.h +++ b/include/configs/km/km-mpc832x.h @@ -1,34 +1,34 @@ /* * System IO Config */ -#define CONFIG_SYS_SICRL SICRL_IRQ_CKS +#define CFG_SYS_SICRL SICRL_IRQ_CKS -#define CONFIG_SYS_DDRCDR (\ +#define CFG_SYS_DDRCDR (\ DDRCDR_EN | \ DDRCDR_PZ_MAXZ | \ DDRCDR_NZ_MAXZ | \ DDRCDR_M_ODR) -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f -#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ +#define CFG_SYS_DDR_CS0_BNDS 0x0000007f +#define CFG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ SDRAM_CFG_32_BE | \ SDRAM_CFG_SREN | \ SDRAM_CFG_HSE) -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 -#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) -#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ +#define CFG_SYS_DDR_SDRAM_CFG2 0x00401000 +#define CFG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) +#define CFG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ +#define CFG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ CSCONFIG_ODT_WR_CFG | \ CSCONFIG_ROW_BIT_13 | \ CSCONFIG_COL_BIT_10) -#define CONFIG_SYS_DDR_MODE 0x47860242 -#define CONFIG_SYS_DDR_MODE2 0x8080c000 +#define CFG_SYS_DDR_MODE 0x47860242 +#define CFG_SYS_DDR_MODE2 0x8080c000 -#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ +#define CFG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ @@ -37,7 +37,7 @@ (0 << TIMING_CFG0_WRT_SHIFT) | \ (0 << TIMING_CFG0_RWT_SHIFT)) -#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ +#define CFG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ (2 << TIMING_CFG1_WRTORD_SHIFT) | \ (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ (3 << TIMING_CFG1_WRREC_SHIFT) | \ @@ -46,7 +46,7 @@ (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ (3 << TIMING_CFG1_PRETOACT_SHIFT)) -#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ +#define CFG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ @@ -54,7 +54,7 @@ (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ (5 << TIMING_CFG2_CPO_SHIFT)) -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 +#define CFG_SYS_DDR_TIMING_3 0x00000000 -#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 -#define CONFIG_SYS_KMBEC_FPGA_SIZE 128 +#define CFG_SYS_KMBEC_FPGA_BASE 0xE8000000 +#define CFG_SYS_KMBEC_FPGA_SIZE 128 diff --git a/include/configs/km/km-mpc8360.h b/include/configs/km/km-mpc8360.h index 92e046d02d7..5c9f912383d 100644 --- a/include/configs/km/km-mpc8360.h +++ b/include/configs/km/km-mpc8360.h @@ -1,6 +1,6 @@ /* KMBEC FPGA (PRIO) */ -#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 -#define CONFIG_SYS_KMBEC_FPGA_SIZE 64 +#define CFG_SYS_KMBEC_FPGA_BASE 0xE8000000 +#define CFG_SYS_KMBEC_FPGA_SIZE 64 /* * High Level Configuration Options @@ -9,34 +9,34 @@ /* * System IO Setup */ -#define CONFIG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI) +#define CFG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI) /** * DDR RAM settings */ -#define CONFIG_SYS_DDR_SDRAM_CFG (\ +#define CFG_SYS_DDR_SDRAM_CFG (\ SDRAM_CFG_SDRAM_TYPE_DDR2 | \ SDRAM_CFG_SREN | \ SDRAM_CFG_HSE) -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 +#define CFG_SYS_DDR_SDRAM_CFG2 0x00401000 -#define CONFIG_SYS_DDR_CLK_CNTL (\ +#define CFG_SYS_DDR_CLK_CNTL (\ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) -#define CONFIG_SYS_DDR_INTERVAL (\ +#define CFG_SYS_DDR_INTERVAL (\ (0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ (0x203 << SDRAM_INTERVAL_REFINT_SHIFT)) -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f +#define CFG_SYS_DDR_CS0_BNDS 0x0000007f -#define CONFIG_SYS_DDRCDR (\ +#define CFG_SYS_DDRCDR (\ DDRCDR_EN | \ DDRCDR_Q_DRN) -#define CONFIG_SYS_DDR_MODE 0x47860452 -#define CONFIG_SYS_DDR_MODE2 0x8080c000 +#define CFG_SYS_DDR_MODE 0x47860452 +#define CFG_SYS_DDR_MODE2 0x8080c000 -#define CONFIG_SYS_DDR_TIMING_0 (\ +#define CFG_SYS_DDR_TIMING_0 (\ (2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ @@ -46,7 +46,7 @@ (0 << TIMING_CFG0_WRT_SHIFT) | \ (0 << TIMING_CFG0_RWT_SHIFT)) -#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \ +#define CFG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \ (2 << TIMING_CFG1_WRTORD_SHIFT) | \ (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ (3 << TIMING_CFG1_WRREC_SHIFT) | \ @@ -55,7 +55,7 @@ (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ (3 << TIMING_CFG1_PRETOACT_SHIFT)) -#define CONFIG_SYS_DDR_TIMING_2 (\ +#define CFG_SYS_DDR_TIMING_2 (\ (0xa << TIMING_CFG2_FOUR_ACT_SHIFT) | \ (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ @@ -64,12 +64,11 @@ (5 << TIMING_CFG2_CPO_SHIFT) | \ (0 << TIMING_CFG2_ADD_LAT_SHIFT)) -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 +#define CFG_SYS_DDR_TIMING_3 0x00000000 /* EEprom support */ /* * PAXE on the local bus CS3 */ -#define CONFIG_SYS_PAXE_BASE 0xA0000000 -#define CONFIG_SYS_PAXE_SIZE 256 +#define CFG_SYS_PAXE_BASE 0xA0000000 diff --git a/include/configs/km/km-mpc83xx.h b/include/configs/km/km-mpc83xx.h index 181ed1b8fae..840a4d5401f 100644 --- a/include/configs/km/km-mpc83xx.h +++ b/include/configs/km/km-mpc83xx.h @@ -7,10 +7,9 @@ /* * DDR Setup */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ +#define CFG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ +#define CFG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) #define CFG_83XX_DDR_USES_CS0 @@ -18,20 +17,20 @@ /* * Manually set up DDR parameters */ -#define CONFIG_SYS_SDRAM_SIZE 0x80000000 /* 2048 MiB */ +#define CFG_SYS_SDRAM_SIZE 0x80000000 /* 2048 MiB */ /* * The reserved memory */ -#define CONFIG_SYS_FLASH_BASE 0xF0000000 +#define CFG_SYS_FLASH_BASE 0xF0000000 /* Reserve 768 kB for Mon */ /* * Initial RAM Base Address Setup */ -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ +#define CFG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CFG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ /* * Init Local Bus Memory Controller: * @@ -45,21 +44,20 @@ /* * FLASH on the Local Bus */ -#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ +#define CFG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } +#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE } /* I2C */ -#define CONFIG_SYS_NUM_I2C_BUSES 4 -#define CONFIG_SYS_I2C_MAX_HOPS 1 -#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ +#define CFG_SYS_NUM_I2C_BUSES 4 +#define CFG_SYS_I2C_MAX_HOPS 1 +#define CFG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ {1, {I2C_NULL_HOP} } } #if defined(CONFIG_CMD_NAND) -#define CONFIG_NAND_KMETER1 -#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE +#define CFG_SYS_NAND_BASE CFG_SYS_KMBEC_FPGA_BASE #endif /* @@ -67,7 +65,7 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) +#define CFG_SYS_BOOTMAPSZ (8 << 20) /* * Environment diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h index 0613b77e966..dfa81c037f4 100644 --- a/include/configs/km/pg-wcom-ls102xa.h +++ b/include/configs/km/pg-wcom-ls102xa.h @@ -9,8 +9,8 @@ /* include common defines/options for all Keymile boards */ #include "keymile-common.h" -#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE OCRAM_SIZE #define CONFIG_PRAM ((CONFIG_KM_PNVRAM + \ CONFIG_KM_PHRAM + \ @@ -19,75 +19,75 @@ #define PHYS_SDRAM 0x80000000 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE #define SPD_EEPROM_ADDRESS 0x54 /* POST memory regions test */ -#define CONFIG_POST (CONFIG_SYS_POST_MEM_REGIONS) -#define CONFIG_POST_EXTERNAL_WORD_FUNCS +#define CFG_POST (CFG_SYS_POST_MEM_REGIONS) +#define CFG_POST_EXTERNAL_WORD_FUNCS /* * IFC Definitions */ /* NOR Flash Definitions */ -#define CONFIG_SYS_FLASH_BASE 0x60000000 -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#define CFG_SYS_FLASH_BASE 0x60000000 +#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE -#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ +#define CFG_SYS_NOR0_CSPR_EXT (0x0) +#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_TE | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(64 * 1024 * 1024) +#define CFG_SYS_NOR_AMASK IFC_AMASK(64 * 1024 * 1024) -#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_AVD_TGL_PGM_EN | \ +#define CFG_SYS_NOR_CSOR (CSOR_NOR_AVD_TGL_PGM_EN | \ CSOR_NOR_ADM_SHIFT(0x4) | \ CSOR_NOR_NOR_MODE_ASYNC_NOR | \ CSOR_NOR_TRHZ_20 | \ CSOR_NOR_BCTLD) -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ +#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ FTIM0_NOR_TEADC(0x7) | \ FTIM0_NOR_TAVDS(0x0) | \ FTIM0_NOR_TEAHC(0x1)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ +#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ FTIM1_NOR_TRAD_NOR(0x21) | \ FTIM1_NOR_TSEQRAD_NOR(0x21)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) | \ +#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) | \ FTIM2_NOR_TCH(0x1) | \ FTIM2_NOR_TWPH(0x6) | \ FTIM2_NOR_TWP(0xb)) -#define CONFIG_SYS_NOR_FTIM3 0 +#define CFG_SYS_NOR_FTIM3 0 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } +#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE_PHYS } -#define CONFIG_SYS_WRITE_SWAPPED_DATA +#define CFG_SYS_WRITE_SWAPPED_DATA -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 /* NAND Flash Definitions */ -#define CONFIG_SYS_NAND_BASE 0x68000000 -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#define CFG_SYS_NAND_BASE 0x68000000 +#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE -#define CONFIG_SYS_NAND_CSPR_EXT (0x0) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE) | \ +#define CFG_SYS_NAND_CSPR_EXT (0x0) +#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE) | \ CSPR_PORT_SIZE_8 | \ CSPR_TE | \ CSPR_MSEL_NAND | \ CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN \ +#define CFG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) +#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN \ | CSOR_NAND_ECC_DEC_EN \ | CSOR_NAND_ECC_MODE_4 \ | CSOR_NAND_RAL_3 \ @@ -97,85 +97,76 @@ | CSOR_NAND_TRHZ_40 \ | CSOR_NAND_BCTLD) -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x3) | \ +#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x3) | \ FTIM0_NAND_TWP(0x8) | \ FTIM0_NAND_TWCHT(0x3) | \ FTIM0_NAND_TWH(0x5)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1e) | \ +#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1e) | \ FTIM1_NAND_TWBE(0x1e) | \ FTIM1_NAND_TRR(0x6) | \ FTIM1_NAND_TRP(0x8)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x9) | \ +#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x9) | \ FTIM2_NAND_TREH(0x5) | \ FTIM2_NAND_TWHRE(0x3c)) -#define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x1e)) +#define CFG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x1e)) -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } /* QRIO FPGA Definitions */ -#define CONFIG_SYS_QRIO_BASE 0x70000000 -#define CONFIG_SYS_QRIO_BASE_PHYS CONFIG_SYS_QRIO_BASE +#define CFG_SYS_QRIO_BASE 0x70000000 +#define CFG_SYS_QRIO_BASE_PHYS CFG_SYS_QRIO_BASE -#define CONFIG_SYS_CSPR2_EXT (0x00) -#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE) | \ +#define CFG_SYS_CSPR2_EXT (0x00) +#define CFG_SYS_CSPR2 (CSPR_PHYS_ADDR(CFG_SYS_QRIO_BASE) | \ CSPR_PORT_SIZE_8 | \ CSPR_TE | \ CSPR_MSEL_GPCM | \ CSPR_V) -#define CONFIG_SYS_AMASK2 IFC_AMASK(64 * 1024) -#define CONFIG_SYS_CSOR2 (CSOR_GPCM_ADM_SHIFT(0x4) | \ +#define CFG_SYS_AMASK2 IFC_AMASK(64 * 1024) +#define CFG_SYS_CSOR2 (CSOR_GPCM_ADM_SHIFT(0x4) | \ CSOR_GPCM_TRHZ_20 | \ CSOR_GPCM_BCTLD) -#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x2) | \ +#define CFG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x2) | \ FTIM0_GPCM_TEADC(0x8) | \ FTIM0_GPCM_TEAHC(0x2)) -#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x2) | \ +#define CFG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x2) | \ FTIM1_GPCM_TRAD(0x6)) -#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x1) | \ +#define CFG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x1) | \ FTIM2_GPCM_TCH(0x1) | \ FTIM2_GPCM_TWP(0x7)) -#define CONFIG_SYS_CS2_FTIM3 0x04000000 +#define CFG_SYS_CS2_FTIM3 0x04000000 /* * Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_CLK get_serial_clock() +#define CFG_SYS_NS16550_CLK get_serial_clock() /* * I2C */ #define CONFIG_I2C_MULTI_BUS -#define CONFIG_SYS_I2C_MAX_HOPS 1 -#define CONFIG_SYS_NUM_I2C_BUSES 3 +#define CFG_SYS_I2C_MAX_HOPS 1 +#define CFG_SYS_NUM_I2C_BUSES 3 #define I2C_MUX_PCA_ADDR 0x70 #define I2C_MUX_CH_DEFAULT 0x0 -#define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \ +#define CFG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \ {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \ {1, {I2C_NULL_HOP} }, \ } #define CONFIG_SMP_PEN_ADDR 0x01ee0200 -#define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 256 -#define CONFIG_FSL_DEVICE_DISABLE - -/* - * Miscellaneous configurable options - */ - -#define CONFIG_LS102XA_STREAM_ID /* * Environment @@ -206,12 +197,12 @@ __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize} && " \ "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \ " +${filesize}\0" \ - "update-nor=protect off " __stringify(CONFIG_SYS_FLASH_BASE) \ + "update-nor=protect off " __stringify(CFG_SYS_FLASH_BASE) \ " +${filesize} && " \ - "erase " __stringify(CONFIG_SYS_FLASH_BASE) \ + "erase " __stringify(CFG_SYS_FLASH_BASE) \ " +${filesize} && " \ "cp.b ${load_addr_r} " \ - __stringify(CONFIG_SYS_FLASH_BASE) " ${filesize} && " \ + __stringify(CFG_SYS_FLASH_BASE) " ${filesize} && " \ "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \ " +" __stringify(CONFIG_SYS_MONITOR_LEN)"\0" \ "set_fdthigh=true\0" \ @@ -239,6 +230,6 @@ "ethrotate=no\0" \ "" -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Increase map for Linux */ +#define CFG_SYS_BOOTMAPSZ (256 << 20) /* Increase map for Linux */ #endif diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h index 2e1459e3e4f..527f0383bc6 100644 --- a/include/configs/kmcent2.h +++ b/include/configs/kmcent2.h @@ -25,10 +25,10 @@ #define SYS_LAWAPP_BASE_PHYS (0xf00000000ull | SYS_LAWAPP_BASE) /* Application IFC CS4 MRAM */ -#define CONFIG_SYS_MRAM_BASE SYS_LAWAPP_BASE +#define CFG_SYS_MRAM_BASE SYS_LAWAPP_BASE #define SYS_MRAM_BASE_PHYS SYS_LAWAPP_BASE_PHYS #define SYS_MRAM_CSPR_EXT (0x0f) -#define SYS_MRAM_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_MRAM_BASE) | \ +#define SYS_MRAM_CSPR (CSPR_PHYS_ADDR(CFG_SYS_MRAM_BASE) | \ CSPR_PORT_SIZE_8 | /* 8 bit */ \ CSPR_MSEL_GPCM | /* msel = gpcm */ \ CSPR_V /* bank is valid */) @@ -44,14 +44,14 @@ FTIM2_GPCM_TCH(0x2) | \ FTIM2_GPCM_TWP(0x8)) #define SYS_MRAM_FTIM3 0x04000000 -#define CONFIG_SYS_CSPR4_EXT SYS_MRAM_CSPR_EXT -#define CONFIG_SYS_CSPR4 SYS_MRAM_CSPR -#define CONFIG_SYS_AMASK4 SYS_MRAM_AMASK -#define CONFIG_SYS_CSOR4 SYS_MRAM_CSOR -#define CONFIG_SYS_CS4_FTIM0 SYS_MRAM_FTIM0 -#define CONFIG_SYS_CS4_FTIM1 SYS_MRAM_FTIM1 -#define CONFIG_SYS_CS4_FTIM2 SYS_MRAM_FTIM2 -#define CONFIG_SYS_CS4_FTIM3 SYS_MRAM_FTIM3 +#define CFG_SYS_CSPR4_EXT SYS_MRAM_CSPR_EXT +#define CFG_SYS_CSPR4 SYS_MRAM_CSPR +#define CFG_SYS_AMASK4 SYS_MRAM_AMASK +#define CFG_SYS_CSOR4 SYS_MRAM_CSOR +#define CFG_SYS_CS4_FTIM0 SYS_MRAM_FTIM0 +#define CFG_SYS_CS4_FTIM1 SYS_MRAM_FTIM1 +#define CFG_SYS_CS4_FTIM2 SYS_MRAM_FTIM2 +#define CFG_SYS_CS4_FTIM3 SYS_MRAM_FTIM3 /* Application IFC CS6: BFTIC */ #define SYS_BFTIC_BASE 0xd0000000 @@ -73,20 +73,20 @@ FTIM2_GPCM_TCH(0x1) | \ FTIM2_GPCM_TWP(0x12)) #define SYS_BFTIC_FTIM3 0x04000000 -#define CONFIG_SYS_CSPR6_EXT SYS_BFTIC_CSPR_EXT -#define CONFIG_SYS_CSPR6 SYS_BFTIC_CSPR -#define CONFIG_SYS_AMASK6 SYS_BFTIC_AMASK -#define CONFIG_SYS_CSOR6 SYS_BFTIC_CSOR -#define CONFIG_SYS_CS6_FTIM0 SYS_BFTIC_FTIM0 -#define CONFIG_SYS_CS6_FTIM1 SYS_BFTIC_FTIM1 -#define CONFIG_SYS_CS6_FTIM2 SYS_BFTIC_FTIM2 -#define CONFIG_SYS_CS6_FTIM3 SYS_BFTIC_FTIM3 +#define CFG_SYS_CSPR6_EXT SYS_BFTIC_CSPR_EXT +#define CFG_SYS_CSPR6 SYS_BFTIC_CSPR +#define CFG_SYS_AMASK6 SYS_BFTIC_AMASK +#define CFG_SYS_CSOR6 SYS_BFTIC_CSOR +#define CFG_SYS_CS6_FTIM0 SYS_BFTIC_FTIM0 +#define CFG_SYS_CS6_FTIM1 SYS_BFTIC_FTIM1 +#define CFG_SYS_CS6_FTIM2 SYS_BFTIC_FTIM2 +#define CFG_SYS_CS6_FTIM3 SYS_BFTIC_FTIM3 /* Application IFC CS7 PAXE */ -#define CONFIG_SYS_PAXE_BASE 0xd8000000 -#define SYS_PAXE_BASE_PHYS (0xf00000000ull | CONFIG_SYS_PAXE_BASE) +#define CFG_SYS_PAXE_BASE 0xd8000000 +#define SYS_PAXE_BASE_PHYS (0xf00000000ull | CFG_SYS_PAXE_BASE) #define SYS_PAXE_CSPR_EXT (0x0f) -#define SYS_PAXE_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_PAXE_BASE) | \ +#define SYS_PAXE_CSPR (CSPR_PHYS_ADDR(CFG_SYS_PAXE_BASE) | \ CSPR_PORT_SIZE_8 | /* Port size = 8 bit */\ CSPR_MSEL_GPCM | /* MSEL = GPCM */\ CSPR_V) /* valid */ @@ -102,14 +102,14 @@ FTIM2_GPCM_TCH(0x1) | \ FTIM2_GPCM_TWP(0x12)) #define SYS_PAXE_FTIM3 0x04000000 -#define CONFIG_SYS_CSPR7_EXT SYS_PAXE_CSPR_EXT -#define CONFIG_SYS_CSPR7 SYS_PAXE_CSPR -#define CONFIG_SYS_AMASK7 SYS_PAXE_AMASK -#define CONFIG_SYS_CSOR7 SYS_PAXE_CSOR -#define CONFIG_SYS_CS7_FTIM0 SYS_PAXE_FTIM0 -#define CONFIG_SYS_CS7_FTIM1 SYS_PAXE_FTIM1 -#define CONFIG_SYS_CS7_FTIM2 SYS_PAXE_FTIM2 -#define CONFIG_SYS_CS7_FTIM3 SYS_PAXE_FTIM3 +#define CFG_SYS_CSPR7_EXT SYS_PAXE_CSPR_EXT +#define CFG_SYS_CSPR7 SYS_PAXE_CSPR +#define CFG_SYS_AMASK7 SYS_PAXE_AMASK +#define CFG_SYS_CSOR7 SYS_PAXE_CSOR +#define CFG_SYS_CS7_FTIM0 SYS_PAXE_FTIM0 +#define CFG_SYS_CS7_FTIM1 SYS_PAXE_FTIM1 +#define CFG_SYS_CS7_FTIM2 SYS_PAXE_FTIM2 +#define CFG_SYS_CS7_FTIM3 SYS_PAXE_FTIM3 /* PRST */ #define KM_BFTIC4_RST 0 @@ -136,7 +136,7 @@ #define CONFIG_RESET_VECTOR_ADDRESS 0xebfffffc -#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS +#define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS /* Environment in parallel NOR-Flash */ #define CONFIG_ENV_TOTAL_SIZE 0x040000 @@ -145,28 +145,28 @@ /* * These can be toggled for performance analysis, otherwise use default. */ -#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E +#define CFG_SYS_INIT_L2CSR0 L2CSR0_L2E /* POST memory regions test */ -#define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS +#define CFG_POST CFG_SYS_POST_MEM_REGIONS /* * Config the L3 Cache as L3 SRAM */ -#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +#define CFG_SYS_INIT_L3_ADDR 0xFFFC0000 -#define CONFIG_SYS_DCSRBAR 0xf0000000 -#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull +#define CFG_SYS_DCSRBAR 0xf0000000 +#define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull /* * DDR Setup */ #define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE #define SPD_EEPROM_ADDRESS 0x54 -#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ +#define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ /****************************************************************************** * (PRAM usage) @@ -189,60 +189,60 @@ * IFC Definitions */ /* NOR flash on IFC CS0 */ -#define CONFIG_SYS_FLASH_BASE 0xe8000000 -#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | \ - CONFIG_SYS_FLASH_BASE) +#define CFG_SYS_FLASH_BASE 0xe8000000 +#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | \ + CFG_SYS_FLASH_BASE) -#define CONFIG_SYS_NOR_CSPR_EXT (0x0f) -#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ +#define CFG_SYS_NOR_CSPR_EXT (0x0f) +#define CFG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE) | \ CSPR_PORT_SIZE_16 | /* Port size = 16 bit */\ 0x00000010 | /* drive TE high */\ CSPR_MSEL_NOR | /* MSEL = NOR */\ CSPR_V) /* valid */ -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(64 * 1024 * 1024) /* 64MB */ -#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_AVD_TGL_PGM_EN | /* AVD toggle */\ +#define CFG_SYS_NOR_AMASK IFC_AMASK(64 * 1024 * 1024) /* 64MB */ +#define CFG_SYS_NOR_CSOR (CSOR_NOR_AVD_TGL_PGM_EN | /* AVD toggle */\ CSOR_NOR_TRHZ_20 | \ CSOR_NOR_BCTLD) /* NOR Flash Timing Params */ -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ +#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ FTIM0_NOR_TEADC(0x7) | \ FTIM0_NOR_TEAHC(0x1)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ +#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ FTIM1_NOR_TRAD_NOR(0x21) | \ FTIM1_NOR_TSEQRAD_NOR(0x21)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCH(0x1) | \ +#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCH(0x1) | \ FTIM2_NOR_TCS(0x1) | \ FTIM2_NOR_TWP(0xb) | \ FTIM2_NOR_TWPH(0x6)) -#define CONFIG_SYS_NOR_FTIM3 0x0 +#define CFG_SYS_NOR_FTIM3 0x0 -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 /* More NOR Flash params */ -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} +#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS} /* NAND Flash on IFC CS1*/ -#define CONFIG_SYS_NAND_BASE 0xfa000000 -#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) +#define CFG_SYS_NAND_BASE 0xfa000000 +#define CFG_SYS_NAND_BASE_PHYS (0xf00000000ull | CFG_SYS_NAND_BASE) -#define CONFIG_SYS_NAND_CSPR_EXT (0x0f) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE) | \ +#define CFG_SYS_NAND_CSPR_EXT (0x0f) +#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE) | \ CSPR_PORT_SIZE_8 | /* Port Size = 8 bit */\ 0x00000010 | /* drive TE high */\ CSPR_MSEL_NAND | /* MSEL = NAND */\ CSPR_V) /* valid */ -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) /* 64kB */ +#define CFG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) /* 64kB */ -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN | /* ECC encoder on */ \ +#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN | /* ECC encoder on */ \ CSOR_NAND_ECC_DEC_EN | /* ECC decoder on */ \ CSOR_NAND_ECC_MODE_4 | /* 4-bit ECC */ \ CSOR_NAND_RAL_3 | /* RAL = 3Bytes */ \ @@ -253,36 +253,36 @@ CSOR_NAND_BCTLD) /**/ /* ONFI NAND Flash mode0 Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x3) | \ +#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x3) | \ FTIM0_NAND_TWP(0x8) | \ FTIM0_NAND_TWCHT(0x3) | \ FTIM0_NAND_TWH(0x5)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1e) | \ +#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1e) | \ FTIM1_NAND_TWBE(0x1e) | \ FTIM1_NAND_TRR(0x6) | \ FTIM1_NAND_TRP(0x8)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x9) | \ +#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x9) | \ FTIM2_NAND_TREH(0x5) | \ FTIM2_NAND_TWHRE(0x3c)) -#define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x1e)) +#define CFG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x1e)) -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 /* More NAND Flash Params */ -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } /* QRIO on IFC CS2 */ -#define CONFIG_SYS_QRIO_BASE 0xfb000000 -#define CONFIG_SYS_QRIO_BASE_PHYS (0xf00000000ull | CONFIG_SYS_QRIO_BASE) +#define CFG_SYS_QRIO_BASE 0xfb000000 +#define CFG_SYS_QRIO_BASE_PHYS (0xf00000000ull | CFG_SYS_QRIO_BASE) #define SYS_QRIO_CSPR_EXT (0x0f) -#define SYS_QRIO_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE) | \ +#define SYS_QRIO_CSPR (CSPR_PHYS_ADDR(CFG_SYS_QRIO_BASE) | \ CSPR_PORT_SIZE_8 | /* Port size = 8 bit */\ 0x00000010 | /* drive TE high */\ CSPR_MSEL_GPCM | /* MSEL = GPCM */\ @@ -300,28 +300,26 @@ FTIM2_GPCM_TCH(0x1) | \ FTIM2_GPCM_TWP(0x7)) #define SYS_QRIO_FTIM3 0x04000000 -#define CONFIG_SYS_CSPR2_EXT SYS_QRIO_CSPR_EXT -#define CONFIG_SYS_CSPR2 SYS_QRIO_CSPR -#define CONFIG_SYS_AMASK2 SYS_QRIO_AMASK -#define CONFIG_SYS_CSOR2 SYS_QRIO_CSOR -#define CONFIG_SYS_CS2_FTIM0 SYS_QRIO_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 SYS_QRIO_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 SYS_QRIO_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 SYS_QRIO_FTIM3 - -#define CONFIG_HWCONFIG +#define CFG_SYS_CSPR2_EXT SYS_QRIO_CSPR_EXT +#define CFG_SYS_CSPR2 SYS_QRIO_CSPR +#define CFG_SYS_AMASK2 SYS_QRIO_AMASK +#define CFG_SYS_CSOR2 SYS_QRIO_CSOR +#define CFG_SYS_CS2_FTIM0 SYS_QRIO_FTIM0 +#define CFG_SYS_CS2_FTIM1 SYS_QRIO_FTIM1 +#define CFG_SYS_CS2_FTIM2 SYS_QRIO_FTIM2 +#define CFG_SYS_CS2_FTIM3 SYS_QRIO_FTIM3 /* define to use L1 as initial stack */ -#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 +#define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ +#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 /* The assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 +#define CFG_SYS_INIT_RAM_ADDR_PHYS \ + ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CFG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#define CFG_SYS_INIT_RAM_SIZE 0x00004000 -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /* * Serial Port - controlled on board with jumper J8 @@ -330,10 +328,8 @@ * Retain non-DM serial port for debug purposes. */ #if !defined(CONFIG_DM_SERIAL) -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2) -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x11C500) +#define CFG_SYS_NS16550_CLK (get_bus_freq(0) / 2) +#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR + 0x11C500) #endif #ifndef __ASSEMBLY__ @@ -348,38 +344,35 @@ int get_scl(void); * Memory space is mapped 1-1, but I/O space must start from 0. */ /* controller 1 */ -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull - -#define CONFIG_SYS_BMAN_NUM_PORTALS 10 -#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 -#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull -#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ - CONFIG_SYS_BMAN_CENA_SIZE) -#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 -#define CONFIG_SYS_QMAN_NUM_PORTALS 10 -#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 -#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull -#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ - CONFIG_SYS_QMAN_CENA_SIZE) -#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 - -#define CONFIG_SYS_DPAA_FMAN -#define CONFIG_SYS_DPAA_PME +#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CFG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull + +#define CFG_SYS_BMAN_NUM_PORTALS 10 +#define CFG_SYS_BMAN_MEM_BASE 0xf4000000 +#define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#define CFG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \ + CFG_SYS_BMAN_CENA_SIZE) +#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08 +#define CFG_SYS_QMAN_NUM_PORTALS 10 +#define CFG_SYS_QMAN_MEM_BASE 0xf6000000 +#define CFG_SYS_QMAN_MEM_PHYS 0xff6000000ull +#define CFG_SYS_QMAN_MEM_SIZE 0x02000000 +#define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \ + CFG_SYS_QMAN_CENA_SIZE) +#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08 /* Qman / Bman */ /* RGMII (FM1@DTESC5) is local managemant interface */ -#define CONFIG_SYS_RGMII2_PHY_ADDR 0x11 +#define CFG_SYS_RGMII2_PHY_ADDR 0x11 /* * Hardware Watchdog @@ -392,7 +385,7 @@ int get_scl(void); * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ /* * Environment Configuration @@ -417,12 +410,12 @@ int get_scl(void); __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize} && " \ "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \ " +${filesize}\0" \ - "update-nor=protect off " __stringify(CONFIG_SYS_FLASH_BASE) \ + "update-nor=protect off " __stringify(CFG_SYS_FLASH_BASE) \ " +${filesize} && " \ - "erase " __stringify(CONFIG_SYS_FLASH_BASE) \ + "erase " __stringify(CFG_SYS_FLASH_BASE) \ " +${filesize} && " \ "cp.b ${load_addr_r} " \ - __stringify(CONFIG_SYS_FLASH_BASE) " ${filesize} && " \ + __stringify(CFG_SYS_FLASH_BASE) " ${filesize} && " \ "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \ " +" __stringify(CONFIG_SYS_MONITOR_LEN) "\0" \ "set_fdthigh=true\0" \ diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h index d6b60d8139a..6b30fb4b617 100644 --- a/include/configs/kmcoge5ne.h +++ b/include/configs/kmcoge5ne.h @@ -9,10 +9,8 @@ #define __CONFIG_H #define CONFIG_HOSTNAME "kmcoge5ne" -#define CONFIG_NAND_ECC_BCH -#define CONFIG_NAND_KMETER1 #define NAND_MAX_CHIPS 1 -#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */ +#define CFG_SYS_NAND_BASE CFG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */ #define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0" #define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1" @@ -26,7 +24,7 @@ /** * KMCOGE5NE has 512 MB RAM */ -#define CONFIG_SYS_DDR_CS0_CONFIG (\ +#define CFG_SYS_DDR_CS0_CONFIG (\ CSCONFIG_EN | \ CSCONFIG_AP | \ CSCONFIG_ODT_WR_ONLY_CURRENT | \ @@ -35,8 +33,8 @@ CSCONFIG_COL_BIT_10) /* enable POST tests */ -#define CONFIG_POST (CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS) -#define CONFIG_POST_EXTERNAL_WORD_FUNCS /* use own functions, not generic */ +#define CFG_POST (CFG_SYS_POST_MEMORY|CFG_SYS_POST_MEM_REGIONS) +#define CFG_POST_EXTERNAL_WORD_FUNCS /* use own functions, not generic */ #define CPM_POST_WORD_ADDR CONFIG_SYS_MEMTEST_END #define CONFIG_TESTPIN_REG gprt3 /* for kmcoge5ne */ #define CONFIG_TESTPIN_MASK 0x20 /* for kmcoge5ne */ diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index 4245875e39e..910fc1b2cb2 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -16,7 +16,7 @@ #include "km/km-mpc83xx.h" #include "km/km-mpc8360.h" -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ +#define CFG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ CSCONFIG_ROW_BIT_13 | \ CSCONFIG_COL_BIT_10 | \ CSCONFIG_ODT_WR_ONLY_CURRENT) diff --git a/include/configs/kontron-sl-mx6ul.h b/include/configs/kontron-sl-mx6ul.h index d3447a80ca5..6fcacdb0c66 100644 --- a/include/configs/kontron-sl-mx6ul.h +++ b/include/configs/kontron-sl-mx6ul.h @@ -11,18 +11,15 @@ #include <linux/sizes.h> #include "mx6_common.h" -#ifdef CONFIG_SPL_BUILD -#include "imx6_spl.h" -#endif /* RAM */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_UBOOT_BASE CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE /* Board and environment settings */ #define CONFIG_MXC_UART_BASE UART4_BASE diff --git a/include/configs/kontron-sl-mx8mm.h b/include/configs/kontron-sl-mx8mm.h index a2aedefcec2..80a32304606 100644 --- a/include/configs/kontron-sl-mx8mm.h +++ b/include/configs/kontron-sl-mx8mm.h @@ -17,10 +17,10 @@ /* RAM */ #define PHYS_SDRAM DDR_CSD1_BASE_ADDR #define PHYS_SDRAM_SIZE (SZ_4G) -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x200000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x200000 /* Board and environment settings */ #define CONFIG_HOSTNAME "kontron-mx8mm" diff --git a/include/configs/kontron_pitx_imx8m.h b/include/configs/kontron_pitx_imx8m.h index 6acd2f79253..17c63d83410 100644 --- a/include/configs/kontron_pitx_imx8m.h +++ b/include/configs/kontron_pitx_imx8m.h @@ -20,7 +20,6 @@ /* For RAW image gives a error info not panic */ -#define CONFIG_POWER_PFUZE100 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 #endif @@ -61,10 +60,10 @@ BOOTENV -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x80000 -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */ diff --git a/include/configs/kontron_sl28.h b/include/configs/kontron_sl28.h index 38860bfd5ca..9c3174d0e02 100644 --- a/include/configs/kontron_sl28.h +++ b/include/configs/kontron_sl28.h @@ -12,17 +12,17 @@ /* we don't have secure memory unless we have a BL31 */ #ifndef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT -#undef CONFIG_SYS_MEM_RESERVE_SECURE +#undef CFG_SYS_MEM_RESERVE_SECURE #endif /* DDR */ #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000 #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL /* early stack pointer */ @@ -35,7 +35,7 @@ #define CONFIG_MALLOC_F_ADDR CFG_SYS_FSL_OCRAM_BASE /* serial port */ -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2) +#define CFG_SYS_NS16550_CLK (get_bus_freq(0) / 2) /* SPL */ diff --git a/include/configs/kp_imx53.h b/include/configs/kp_imx53.h index c401fd32169..c551585a206 100644 --- a/include/configs/kp_imx53.h +++ b/include/configs/kp_imx53.h @@ -67,9 +67,9 @@ #define PHYS_SDRAM_1_SIZE (512 * SZ_1M) #define PHYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE) -#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) -#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) -#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) +#define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1) +#define CFG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) +#define CFG_SYS_INIT_RAM_SIZE (IRAM_SIZE) /* environment organization */ diff --git a/include/configs/kp_imx6q_tpc.h b/include/configs/kp_imx6q_tpc.h index 1823a793988..136e228682a 100644 --- a/include/configs/kp_imx6q_tpc.h +++ b/include/configs/kp_imx6q_tpc.h @@ -12,9 +12,6 @@ #include "mx6_common.h" -/* SPL */ -#include "imx6_spl.h" /* common IMX6 SPL configuration */ - /* Miscellaneous configurable options */ /* FEC ethernet */ @@ -89,9 +86,9 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* Environment */ diff --git a/include/configs/lacie_kw.h b/include/configs/lacie_kw.h index 9b70eed46f7..828f9109634 100644 --- a/include/configs/lacie_kw.h +++ b/include/configs/lacie_kw.h @@ -31,7 +31,7 @@ #ifdef CONFIG_CMD_I2C /* I2C EEPROM HT24LC04 (512B - 32 pages of 16 Bytes) */ #if defined(CONFIG_NET2BIG_V2) -#define CONFIG_SYS_I2C_G762_ADDR 0x3e +#define CFG_SYS_I2C_G762_ADDR 0x3e #endif #endif /* CONFIG_CMD_I2C */ diff --git a/include/configs/legoev3.h b/include/configs/legoev3.h index f0ae9248af3..abe470fe890 100644 --- a/include/configs/legoev3.h +++ b/include/configs/legoev3.h @@ -17,10 +17,10 @@ /* * SoC Configuration */ -#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH -#define CONFIG_SYS_OSCIN_FREQ 24000000 -#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE -#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) +#define CFG_SYS_EXCEPTION_VECTORS_HIGH +#define CFG_SYS_OSCIN_FREQ 24000000 +#define CFG_SYS_TIMERBASE DAVINCI_TIMER0_BASE +#define CFG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) /* * Memory Info @@ -36,10 +36,9 @@ /* * Serial Driver info */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) +#define CFG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) -#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI0_CLKID) +#define CFG_SYS_SPI_CLK clk_get(DAVINCI_SPI0_CLKID) /* * U-Boot general configuration @@ -49,7 +48,6 @@ * Linux Information */ #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) -#define CONFIG_HWCONFIG /* enable hwconfig */ #define CONFIG_SETUP_INITRD_TAG #define CONFIG_EXTRA_ENV_SETTINGS \ "bootenvfile=uEnv.txt\0" \ @@ -86,7 +84,7 @@ "bootscript=source ${bootscraddr}\0" /* additions for new relocation code, must added to all boards */ -#define CONFIG_SYS_SDRAM_BASE 0xc0000000 +#define CFG_SYS_SDRAM_BASE 0xc0000000 #include <asm/arch/hardware.h> diff --git a/include/configs/librem5.h b/include/configs/librem5.h index dbd7d107dae..11b3fa6c857 100644 --- a/include/configs/librem5.h +++ b/include/configs/librem5.h @@ -79,10 +79,10 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x80000 -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0xc0000000 /* 3GB LPDDR4 one Rank */ diff --git a/include/configs/linkit-smart-7688.h b/include/configs/linkit-smart-7688.h index 9eedd47c07e..f16c7e91221 100644 --- a/include/configs/linkit-smart-7688.h +++ b/include/configs/linkit-smart-7688.h @@ -7,28 +7,26 @@ #define __CONFIG_LINKIT_SMART_7688_H /* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 +#define CFG_SYS_INIT_SP_OFFSET 0x400000 /* SPL */ -#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE /* Dummy value */ -#define CONFIG_SYS_UBOOT_BASE 0 +#define CFG_SYS_UBOOT_BASE 0 /* Serial SPL */ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) -#define CONFIG_SYS_NS16550_MEM32 -#define CONFIG_SYS_NS16550_CLK 40000000 -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#define CONFIG_SYS_NS16550_COM3 0xb0000e00 +#define CFG_SYS_NS16550_CLK 40000000 +#define CFG_SYS_NS16550_COM3 0xb0000e00 #endif /* UART */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ +#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ 230400, 460800, 921600 } /* RAM */ diff --git a/include/configs/liteboard.h b/include/configs/liteboard.h index a784002158b..721da818633 100644 --- a/include/configs/liteboard.h +++ b/include/configs/liteboard.h @@ -13,9 +13,6 @@ #include <linux/stringify.h> #include "mx6_common.h" -/* SPL options */ -#include "imx6_spl.h" - #define CONFIG_MXC_UART_BASE UART1_BASE /* MMC Configs */ @@ -90,9 +87,9 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* FLASH and environment organization */ diff --git a/include/configs/ls1012a2g5rdb.h b/include/configs/ls1012a2g5rdb.h index f0248e64646..f0a9e9ab315 100644 --- a/include/configs/ls1012a2g5rdb.h +++ b/include/configs/ls1012a2g5rdb.h @@ -9,11 +9,7 @@ #include "ls1012a_common.h" /* DDR */ -#define CONFIG_SYS_SDRAM_SIZE 0x40000000 - -/* SATA */ - -#define CONFIG_SYS_SATA AHCI_BASE_ADDR +#define CFG_SYS_SDRAM_SIZE 0x40000000 #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index 77f84e1c9ea..9e4f949016e 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -10,27 +10,20 @@ #include <asm/arch/stream_id_lsch2.h> #include <linux/sizes.h> -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000 #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_BLOCK2_BASE 0x880000000ULL /*SPI device */ #define CFG_SYS_FSL_QSPI_BASE 0x40000000 -/* SATA */ - -#define CONFIG_SYS_SATA AHCI_BASE_ADDR - /* I2C */ /* GPIO */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_serial_clock()) +#define CFG_SYS_NS16550_CLK (get_serial_clock()) -#define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 #define BOOT_TARGET_DEVICES(func) \ diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h index 674bcbeb758..c19ed2f43ec 100644 --- a/include/configs/ls1012afrdm.h +++ b/include/configs/ls1012afrdm.h @@ -10,7 +10,7 @@ #include "ls1012a_common.h" /* DDR */ -#define CONFIG_SYS_SDRAM_SIZE 0x20000000 +#define CFG_SYS_SDRAM_SIZE 0x20000000 #undef BOOT_TARGET_DEVICES #define BOOT_TARGET_DEVICES(func) \ diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h index 9ad3a120118..495bb3911b3 100644 --- a/include/configs/ls1012aqds.h +++ b/include/configs/ls1012aqds.h @@ -10,14 +10,14 @@ #include "ls1012a_common.h" /* DDR */ -#define CONFIG_SYS_SDRAM_SIZE 0x40000000 +#define CFG_SYS_SDRAM_SIZE 0x40000000 /* * QIXIS Definitions */ #ifdef CONFIG_FSL_QIXIS -#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define CFG_SYS_I2C_FPGA_ADDR 0x66 #define QIXIS_LBMAP_BRDCFG_REG 0x04 #define QIXIS_LBMAP_SWITCH 6 #define QIXIS_LBMAP_MASK 0x08 @@ -46,8 +46,7 @@ /* * RTC configuration */ -#define RTC -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ +#define CFG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ /* Voltage monitor on channel 2*/ diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h index 4f77acdaede..d74936d1281 100644 --- a/include/configs/ls1012ardb.h +++ b/include/configs/ls1012ardb.h @@ -10,7 +10,7 @@ #include "ls1012a_common.h" /* DDR */ -#define CONFIG_SYS_SDRAM_SIZE 0x40000000 +#define CFG_SYS_SDRAM_SIZE 0x40000000 /* * I2C IO expander diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index 885774f63d4..024a7185275 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -7,8 +7,8 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE OCRAM_SIZE /* * DDR: 800 MHz ( 1600 MT/s data rate ) @@ -41,15 +41,13 @@ #define SDRAM_CFG2_FRC_SR 0x80000000 #define SDRAM_CFG_BI 0x00000001 -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE /* * Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() +#define CFG_SYS_NS16550_CLK get_serial_clock() /* * I2C @@ -94,11 +92,8 @@ #define CONFIG_PEN_ADDR_BIG_ENDIAN #define CONFIG_SMP_PEN_ADDR 0x01ee0200 -#define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 256 -#define CONFIG_FSL_DEVICE_DISABLE - #define CONFIG_EXTRA_ENV_SETTINGS \ "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ "initrd_high=0xffffffff\0" @@ -106,9 +101,7 @@ /* * Miscellaneous configurable options */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) - -#define CONFIG_LS102XA_STREAM_ID +#define CFG_SYS_BOOTMAPSZ (256 << 20) #include <asm/fsl_secure_boot.h> diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 926c85805b7..5a91cc3efec 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -7,20 +7,20 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE OCRAM_SIZE #ifdef CONFIG_NAND_BOOT -#define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_NAND_U_BOOT_SIZE (400 << 10) +#define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE +#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE #endif #define SPD_EEPROM_ADDRESS 0x51 -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE #ifdef CONFIG_DDR_ECC #define CONFIG_MEM_INIT_VALUE 0xdeadbeef @@ -30,57 +30,57 @@ * IFC Definitions */ #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_SYS_FLASH_BASE 0x60000000 -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#define CFG_SYS_FLASH_BASE 0x60000000 +#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE -#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ +#define CFG_SYS_NOR0_CSPR_EXT (0x0) +#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR1_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ +#define CFG_SYS_NOR1_CSPR_EXT (0x0) +#define CFG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS \ + 0x8000000) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) +#define CFG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) -#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ +#define CFG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ CSOR_NOR_TRHZ_80) -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ +#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ FTIM0_NOR_TEADC(0x5) | \ FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ +#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ FTIM1_NOR_TRAD_NOR(0x1a) | \ FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ +#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ FTIM2_NOR_TCH(0x4) | \ FTIM2_NOR_TWPH(0xe) | \ FTIM2_NOR_TWP(0x1c)) -#define CONFIG_SYS_NOR_FTIM3 0 +#define CFG_SYS_NOR_FTIM3 0 #define CONFIG_FLASH_SHOW_PROGRESS 45 -#define CONFIG_SYS_WRITE_SWAPPED_DATA +#define CFG_SYS_WRITE_SWAPPED_DATA -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ - CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} +#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS, \ + CFG_SYS_FLASH_BASE_PHYS + 0x8000000} /* * NAND Flash Definitions */ -#define CONFIG_SYS_NAND_BASE 0x7e800000 -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#define CFG_SYS_NAND_BASE 0x7e800000 +#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE -#define CONFIG_SYS_NAND_CSPR_EXT (0x0) +#define CFG_SYS_NAND_CSPR_EXT (0x0) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ +#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_NAND \ | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ +#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024) +#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ @@ -88,20 +88,20 @@ | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ +#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ FTIM0_NAND_TWP(0x18) | \ FTIM0_NAND_TWCHT(0x7) | \ FTIM0_NAND_TWH(0xa)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ +#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ FTIM1_NAND_TWBE(0x39) | \ FTIM1_NAND_TRR(0xe) | \ FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ +#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ FTIM2_NAND_TREH(0xa) | \ FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 +#define CFG_SYS_NAND_FTIM3 0x0 -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #endif /* @@ -111,7 +111,7 @@ #ifdef CONFIG_FSL_QIXIS #define QIXIS_BASE 0x7fb00000 #define QIXIS_BASE_PHYS QIXIS_BASE -#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define CFG_SYS_I2C_FPGA_ADDR 0x66 #define QIXIS_LBMAP_SWITCH 6 #define QIXIS_LBMAP_MASK 0x0f #define QIXIS_LBMAP_SHIFT 0 @@ -131,107 +131,103 @@ #define QIXIS_PWR_CTL2 0x21 #define QIXIS_PWR_CTL2_PCTL 0x2 -#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) -#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ +#define CFG_SYS_FPGA_CSPR_EXT (0x0) +#define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ CSPR_PORT_SIZE_8 | \ CSPR_MSEL_GPCM | \ CSPR_V) -#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) -#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ +#define CFG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) +#define CFG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ CSOR_NOR_NOR_MODE_AVD_NOR | \ CSOR_NOR_TRHZ_80) /* * QIXIS Timing parameters for IFC GPCM */ -#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \ +#define CFG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \ FTIM0_GPCM_TEADC(0xe) | \ FTIM0_GPCM_TEAHC(0xe)) -#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \ +#define CFG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \ FTIM1_GPCM_TRAD(0x1f)) -#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \ +#define CFG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \ FTIM2_GPCM_TCH(0xe) | \ FTIM2_GPCM_TWP(0xf0)) -#define CONFIG_SYS_FPGA_FTIM3 0x0 +#define CFG_SYS_FPGA_FTIM3 0x0 #endif #if defined(CONFIG_NAND_BOOT) -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 -#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 -#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 -#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NOR1_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NOR1_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT +#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR +#define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK +#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR +#define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0 +#define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1 +#define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2 +#define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3 #else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 -#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 -#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 -#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR1_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT +#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR +#define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK +#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR +#define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0 +#define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1 +#define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2 +#define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3 #endif /* * Serial Port */ #ifndef CONFIG_LPUART -#define CONFIG_SYS_NS16550_SERIAL -#ifndef CONFIG_DM_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#endif -#define CONFIG_SYS_NS16550_CLK get_serial_clock() +#define CFG_SYS_NS16550_CLK get_serial_clock() #endif /* @@ -280,11 +276,8 @@ #define CONFIG_PEN_ADDR_BIG_ENDIAN #define CONFIG_SMP_PEN_ADDR 0x01ee0200 -#define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 256 -#define CONFIG_FSL_DEVICE_DISABLE - #ifdef CONFIG_LPUART #define CONFIG_EXTRA_ENV_SETTINGS \ "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ @@ -300,9 +293,7 @@ /* * Miscellaneous configurable options */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) - -#define CONFIG_LS102XA_STREAM_ID +#define CFG_SYS_BOOTMAPSZ (256 << 20) /* * Environment diff --git a/include/configs/ls1021atsn.h b/include/configs/ls1021atsn.h index fce91192dff..5612c60ae90 100644 --- a/include/configs/ls1021atsn.h +++ b/include/configs/ls1021atsn.h @@ -6,8 +6,8 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE OCRAM_SIZE /* XHCI Support - enabled by default */ @@ -56,26 +56,19 @@ #define PHYS_SDRAM 0x80000000 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE /* Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#ifndef CONFIG_DM_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#endif -#define CONFIG_SYS_NS16550_CLK get_serial_clock() +#define CFG_SYS_NS16550_CLK get_serial_clock() /* I2C */ /* PCIe */ #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" -#define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 256 -#define CONFIG_FSL_DEVICE_DISABLE - #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ func(USB, usb, 0) \ @@ -145,9 +138,7 @@ "bootm $load_addr#$board\0" /* Miscellaneous configurable options */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) - -#define CONFIG_LS102XA_STREAM_ID +#define CFG_SYS_BOOTMAPSZ (256 << 20) /* Environment */ diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 2c96b6f7789..3c4c207edd0 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -7,8 +7,8 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE OCRAM_SIZE #define DDR_SDRAM_CFG 0x470c0008 #define DDR_CS0_BNDS 0x008000bf @@ -59,97 +59,93 @@ #define PHYS_SDRAM 0x80000000 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE /* * IFC Definitions */ #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_SYS_FLASH_BASE 0x60000000 -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#define CFG_SYS_FLASH_BASE 0x60000000 +#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE -#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ +#define CFG_SYS_NOR0_CSPR_EXT (0x0) +#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) +#define CFG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) /* NOR Flash Timing Params */ -#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ +#define CFG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ CSOR_NOR_TRHZ_80) -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ +#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ FTIM0_NOR_TEADC(0x5) | \ FTIM0_NOR_TAVDS(0x0) | \ FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ +#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ FTIM1_NOR_TRAD_NOR(0x1A) | \ FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ +#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ FTIM2_NOR_TCH(0x4) | \ FTIM2_NOR_TWP(0x1c) | \ FTIM2_NOR_TWPH(0x0e)) -#define CONFIG_SYS_NOR_FTIM3 0 +#define CFG_SYS_NOR_FTIM3 0 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } +#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE_PHYS } -#define CONFIG_SYS_WRITE_SWAPPED_DATA +#define CFG_SYS_WRITE_SWAPPED_DATA #endif /* CPLD */ -#define CONFIG_SYS_CPLD_BASE 0x7fb00000 -#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE +#define CFG_SYS_CPLD_BASE 0x7fb00000 +#define CPLD_BASE_PHYS CFG_SYS_CPLD_BASE -#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) -#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ +#define CFG_SYS_FPGA_CSPR_EXT (0x0) +#define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ CSPR_PORT_SIZE_8 | \ CSPR_MSEL_GPCM | \ CSPR_V) -#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) -#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ +#define CFG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) +#define CFG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ CSOR_NOR_NOR_MODE_AVD_NOR | \ CSOR_NOR_TRHZ_80) /* CPLD Timing parameters for IFC GPCM */ -#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ +#define CFG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ FTIM0_GPCM_TEADC(0xf) | \ FTIM0_GPCM_TEAHC(0xf)) -#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ +#define CFG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ FTIM1_GPCM_TRAD(0x3f)) -#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ +#define CFG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ FTIM2_GPCM_TCH(0xf) | \ FTIM2_GPCM_TWP(0xff)) -#define CONFIG_SYS_FPGA_FTIM3 0x0 -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#define CFG_SYS_FPGA_FTIM3 0x0 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_FPGA_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_FPGA_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_FPGA_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_FPGA_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_FPGA_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_FPGA_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_FPGA_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_FPGA_FTIM3 /* * Serial Port */ #ifndef CONFIG_LPUART -#define CONFIG_SYS_NS16550_SERIAL -#ifndef CONFIG_DM_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#endif -#define CONFIG_SYS_NS16550_CLK get_serial_clock() +#define CFG_SYS_NS16550_CLK get_serial_clock() #endif /* @@ -161,11 +157,8 @@ #define CONFIG_PEN_ADDR_BIG_ENDIAN #define CONFIG_SMP_PEN_ADDR 0x01ee0200 -#define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 256 -#define CONFIG_FSL_DEVICE_DISABLE - #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ func(USB, usb, 0) \ @@ -302,9 +295,7 @@ /* * Miscellaneous configurable options */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) - -#define CONFIG_LS102XA_STREAM_ID +#define CFG_SYS_BOOTMAPSZ (256 << 20) /* * Environment diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h index 43dbeea1b3b..b190bfe9c8e 100644 --- a/include/configs/ls1028a_common.h +++ b/include/configs/ls1028a_common.h @@ -13,10 +13,10 @@ /* Link Definitions */ #define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL /* * SMP Definitinos @@ -28,15 +28,12 @@ /* I2C */ /* Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2) +#define CFG_SYS_NS16550_CLK (get_bus_freq(0) / 2) /* Miscellaneous configurable options */ /* Physical Memory Map */ -#define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 #define BOOT_TARGET_DEVICES(func) \ diff --git a/include/configs/ls1028aqds.h b/include/configs/ls1028aqds.h index 25391151866..228fb122f5f 100644 --- a/include/configs/ls1028aqds.h +++ b/include/configs/ls1028aqds.h @@ -17,7 +17,7 @@ #ifdef CONFIG_FSL_QIXIS #define QIXIS_BASE 0x7fb00000 #define QIXIS_BASE_PHYS QIXIS_BASE -#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define CFG_SYS_I2C_FPGA_ADDR 0x66 #define QIXIS_LBMAP_SWITCH 1 #define QIXIS_LBMAP_MASK 0x0f #define QIXIS_LBMAP_SHIFT 5 @@ -35,19 +35,19 @@ #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 #define QIXIS_RST_FORCE_MEM 0x01 -#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) -#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ +#define CFG_SYS_FPGA_CSPR_EXT (0x0) +#define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ CSPR_PORT_SIZE_8 | \ CSPR_MSEL_GPCM | \ CSPR_V) -#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) -#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ +#define CFG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) +#define CFG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ CSOR_NOR_NOR_MODE_AVD_NOR | \ CSOR_NOR_TRHZ_80) #endif /* RTC */ -#define CONFIG_SYS_RTC_BUS_NUM 1 +#define CFG_SYS_RTC_BUS_NUM 1 #define I2C_MUX_CH_RTC 0xB /* Store environment at top of flash */ diff --git a/include/configs/ls1028ardb.h b/include/configs/ls1028ardb.h index e7b2543b730..5c134612576 100644 --- a/include/configs/ls1028ardb.h +++ b/include/configs/ls1028ardb.h @@ -10,7 +10,7 @@ #define COUNTER_FREQUENCY_REAL (get_board_sys_clk() / 4) -#define CONFIG_SYS_RTC_BUS_NUM 0 +#define CFG_SYS_RTC_BUS_NUM 0 /* Store environment at top of flash */ @@ -21,7 +21,7 @@ #ifdef CONFIG_FSL_QIXIS #define QIXIS_BASE 0x7fb00000 #define QIXIS_BASE_PHYS QIXIS_BASE -#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define CFG_SYS_I2C_FPGA_ADDR 0x66 #define QIXIS_LBMAP_SWITCH 2 #define QIXIS_LBMAP_MASK 0xe0 #define QIXIS_LBMAP_SHIFT 0x5 @@ -39,12 +39,12 @@ #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 #define QIXIS_RST_FORCE_MEM 0x01 -#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) -#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ +#define CFG_SYS_FPGA_CSPR_EXT (0x0) +#define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ CSPR_PORT_SIZE_8 | \ CSPR_MSEL_GPCM | \ CSPR_V) -#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ +#define CFG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ CSOR_NOR_NOR_MODE_AVD_NOR | \ CSOR_NOR_TRHZ_80) #endif diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 8c19468141a..a3fa92d1ff4 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -32,17 +32,15 @@ /* Link Definitions */ #define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000 #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_BLOCK2_BASE 0x880000000ULL #define CPU_RELEASE_ADDR secondary_boot_addr /* Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_serial_clock()) +#define CFG_SYS_NS16550_CLK (get_serial_clock()) /* SD boot SPL */ #ifdef CONFIG_SD_BOOT @@ -59,8 +57,8 @@ /* NAND SPL */ #ifdef CONFIG_NAND_BOOT -#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE +#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE #ifdef CONFIG_NXP_ESBC #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) @@ -84,14 +82,14 @@ #if defined(CONFIG_TFABOOT) || \ (!defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)) /* - * CONFIG_SYS_FLASH_BASE has the final address (core view) - * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) - * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address + * CFG_SYS_FLASH_BASE has the final address (core view) + * CFG_SYS_FLASH_BASE_PHYS has the final address (IFC view) + * CFG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address * CONFIG_TEXT_BASE is linked to 0x60000000 for booting */ -#define CONFIG_SYS_FLASH_BASE 0x60000000 -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 +#define CFG_SYS_FLASH_BASE 0x60000000 +#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE +#define CFG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 #ifdef CONFIG_MTD_NOR_FLASH #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ @@ -105,15 +103,13 @@ /* FMan ucode */ #ifndef SPL_NO_FMAN -#define CONFIG_SYS_DPAA_FMAN #ifdef CONFIG_SYS_DPAA_FMAN -#define CONFIG_SYS_FM_MURAM_SIZE 0x60000 +#define CFG_SYS_FM_MURAM_SIZE 0x60000 #endif #endif /* Miscellaneous configurable options */ -#define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 #ifndef SPL_NO_MISC diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index d207e475fc0..dab57382edd 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -35,61 +35,57 @@ #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB #endif -/* SATA */ - -#define CONFIG_SYS_SATA AHCI_BASE_ADDR - /* * IFC Definitions */ #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ +#define CFG_SYS_NOR0_CSPR_EXT (0x0) +#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR1_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ +#define CFG_SYS_NOR1_CSPR_EXT (0x0) +#define CFG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS \ + 0x8000000) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) +#define CFG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) -#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ +#define CFG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ CSOR_NOR_TRHZ_80) -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ +#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ FTIM0_NOR_TEADC(0x5) | \ FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ +#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ FTIM1_NOR_TRAD_NOR(0x1a) | \ FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ +#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ FTIM2_NOR_TCH(0x4) | \ FTIM2_NOR_TWPH(0xe) | \ FTIM2_NOR_TWP(0x1c)) -#define CONFIG_SYS_NOR_FTIM3 0 +#define CFG_SYS_NOR_FTIM3 0 -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ - CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} +#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS, \ + CFG_SYS_FLASH_BASE_PHYS + 0x8000000} -#define CONFIG_SYS_WRITE_SWAPPED_DATA +#define CFG_SYS_WRITE_SWAPPED_DATA /* * NAND Flash Definitions */ -#define CONFIG_SYS_NAND_BASE 0x7e800000 -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#define CFG_SYS_NAND_BASE 0x7e800000 +#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE -#define CONFIG_SYS_NAND_CSPR_EXT (0x0) +#define CFG_SYS_NAND_CSPR_EXT (0x0) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ +#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_NAND \ | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ +#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024) +#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ @@ -97,25 +93,25 @@ | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ +#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ FTIM0_NAND_TWP(0x18) | \ FTIM0_NAND_TWCHT(0x7) | \ FTIM0_NAND_TWH(0xa)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ +#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ FTIM1_NAND_TWBE(0x39) | \ FTIM1_NAND_TRR(0xe) | \ FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ +#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ FTIM2_NAND_TREH(0xa) | \ FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 +#define CFG_SYS_NAND_FTIM3 0x0 -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #define CONFIG_MTD_NAND_VERIFY_WRITE #endif #ifdef CONFIG_NAND_BOOT -#define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10) +#define CFG_SYS_NAND_U_BOOT_SIZE (640 << 10) #endif #if defined(CONFIG_TFABOOT) || \ @@ -129,7 +125,7 @@ #ifdef CONFIG_FSL_QIXIS #define QIXIS_BASE 0x7fb00000 #define QIXIS_BASE_PHYS QIXIS_BASE -#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define CFG_SYS_I2C_FPGA_ADDR 0x66 #define QIXIS_LBMAP_SWITCH 6 #define QIXIS_LBMAP_MASK 0x0f #define QIXIS_LBMAP_SHIFT 0 @@ -147,130 +143,130 @@ #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 -#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) -#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ +#define CFG_SYS_FPGA_CSPR_EXT (0x0) +#define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ CSPR_PORT_SIZE_8 | \ CSPR_MSEL_GPCM | \ CSPR_V) -#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) -#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ +#define CFG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) +#define CFG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ CSOR_NOR_NOR_MODE_AVD_NOR | \ CSOR_NOR_TRHZ_80) /* * QIXIS Timing parameters for IFC GPCM */ -#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \ +#define CFG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \ FTIM0_GPCM_TEADC(0x20) | \ FTIM0_GPCM_TEAHC(0x10)) -#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \ +#define CFG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \ FTIM1_GPCM_TRAD(0x1f)) -#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \ +#define CFG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \ FTIM2_GPCM_TCH(0x8) | \ FTIM2_GPCM_TWP(0xf0)) -#define CONFIG_SYS_FPGA_FTIM3 0x0 +#define CFG_SYS_FPGA_FTIM3 0x0 #endif #ifdef CONFIG_TFABOOT -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 -#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 -#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 -#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR1_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT +#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR +#define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK +#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR +#define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0 +#define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1 +#define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2 +#define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3 #else #ifdef CONFIG_NAND_BOOT -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 -#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 -#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 -#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NOR1_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NOR1_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT +#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR +#define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK +#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR +#define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0 +#define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1 +#define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2 +#define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3 #else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 -#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 -#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 -#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR1_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT +#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR +#define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK +#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR +#define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0 +#define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1 +#define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2 +#define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3 #endif #endif diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index 206de7e1380..12c4853ea96 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -18,49 +18,49 @@ /* * NOR Flash Definitions */ -#define CONFIG_SYS_NOR_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) -#define CONFIG_SYS_NOR_CSPR \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ +#define CFG_SYS_NOR_CSPR_EXT (0x0) +#define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) +#define CFG_SYS_NOR_CSPR \ + (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) /* NOR Flash Timing Params */ -#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ +#define CFG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ CSOR_NOR_TRHZ_80) -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ +#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ FTIM0_NOR_TEADC(0x1) | \ FTIM0_NOR_TAVDS(0x0) | \ FTIM0_NOR_TEAHC(0xc)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1c) | \ +#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1c) | \ FTIM1_NOR_TRAD_NOR(0xb) | \ FTIM1_NOR_TSEQRAD_NOR(0x9)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) | \ +#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) | \ FTIM2_NOR_TCH(0x4) | \ FTIM2_NOR_TWPH(0x8) | \ FTIM2_NOR_TWP(0x10)) -#define CONFIG_SYS_NOR_FTIM3 0 -#define CONFIG_SYS_IFC_CCR 0x01000000 +#define CFG_SYS_NOR_FTIM3 0 +#define CFG_SYS_IFC_CCR 0x01000000 -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } +#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE_PHYS } -#define CONFIG_SYS_WRITE_SWAPPED_DATA +#define CFG_SYS_WRITE_SWAPPED_DATA /* * NAND Flash Definitions */ -#define CONFIG_SYS_NAND_BASE 0x7e800000 -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#define CFG_SYS_NAND_BASE 0x7e800000 +#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE -#define CONFIG_SYS_NAND_CSPR_EXT (0x0) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ +#define CFG_SYS_NAND_CSPR_EXT (0x0) +#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_NAND \ | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ +#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024) +#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ @@ -68,120 +68,120 @@ | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ +#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ FTIM0_NAND_TWP(0x18) | \ FTIM0_NAND_TWCHT(0x7) | \ FTIM0_NAND_TWH(0xa)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ +#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ FTIM1_NAND_TWBE(0x39) | \ FTIM1_NAND_TRR(0xe) | \ FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ +#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ FTIM2_NAND_TREH(0xa) | \ FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 +#define CFG_SYS_NAND_FTIM3 0x0 -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #define CONFIG_MTD_NAND_VERIFY_WRITE #ifdef CONFIG_NAND_BOOT -#define CONFIG_SYS_NAND_U_BOOT_SIZE (1024 << 10) +#define CFG_SYS_NAND_U_BOOT_SIZE (1024 << 10) #endif /* * CPLD */ -#define CONFIG_SYS_CPLD_BASE 0x7fb00000 -#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE +#define CFG_SYS_CPLD_BASE 0x7fb00000 +#define CPLD_BASE_PHYS CFG_SYS_CPLD_BASE -#define CONFIG_SYS_CPLD_CSPR_EXT (0x0) -#define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ +#define CFG_SYS_CPLD_CSPR_EXT (0x0) +#define CFG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ CSPR_PORT_SIZE_8 | \ CSPR_MSEL_GPCM | \ CSPR_V) -#define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024) -#define CONFIG_SYS_CPLD_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ +#define CFG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024) +#define CFG_SYS_CPLD_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ CSOR_NOR_NOR_MODE_AVD_NOR | \ CSOR_NOR_TRHZ_80) /* CPLD Timing parameters for IFC GPCM */ -#define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ +#define CFG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ FTIM0_GPCM_TEADC(0xf) | \ FTIM0_GPCM_TEAHC(0xf)) -#define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ +#define CFG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ FTIM1_GPCM_TRAD(0x3f)) -#define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ +#define CFG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ FTIM2_GPCM_TCH(0xf) | \ FTIM2_GPCM_TWP(0xff)) -#define CONFIG_SYS_CPLD_FTIM3 0x0 +#define CFG_SYS_CPLD_FTIM3 0x0 /* IFC Timing Params */ #ifdef CONFIG_TFABOOT -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 - -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 + +#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 #else #ifdef CONFIG_NAND_BOOT -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 - -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 + +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 #else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 - -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 + +#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 #endif #endif -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_CPLD_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_CPLD_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_CPLD_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_CPLD_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_CPLD_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_CPLD_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_CPLD_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_CPLD_FTIM3 /* * Environment diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index 7e1a724387e..4ed5481c3e7 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -32,17 +32,15 @@ /* Link Definitions */ #define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000 #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_BLOCK2_BASE 0x880000000ULL #define CPU_RELEASE_ADDR secondary_boot_addr /* Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_serial_clock()) +#define CFG_SYS_NS16550_CLK (get_serial_clock()) /* SD boot SPL */ #ifdef CONFIG_SD_BOOT @@ -59,30 +57,23 @@ /* NAND SPL */ #ifdef CONFIG_NAND_BOOT -#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE +#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE #endif /* GPIO */ /* I2C */ -/* SATA */ -#ifndef SPL_NO_SATA -#define CONFIG_SYS_SATA AHCI_BASE_ADDR -#endif - /* FMan ucode */ #ifndef SPL_NO_FMAN -#define CONFIG_SYS_DPAA_FMAN #ifdef CONFIG_SYS_DPAA_FMAN -#define CONFIG_SYS_FM_MURAM_SIZE 0x60000 +#define CFG_SYS_FM_MURAM_SIZE 0x60000 #endif #endif /* Miscellaneous configurable options */ -#define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 #define BOOT_TARGET_DEVICES(func) \ diff --git a/include/configs/ls1046afrwy.h b/include/configs/ls1046afrwy.h index 48408f28583..1759d25f3a3 100644 --- a/include/configs/ls1046afrwy.h +++ b/include/configs/ls1046afrwy.h @@ -8,22 +8,22 @@ #include "ls1046a_common.h" -#define CONFIG_SYS_UBOOT_BASE 0x40100000 +#define CFG_SYS_UBOOT_BASE 0x40100000 /* * NAND Flash Definitions */ -#define CONFIG_SYS_NAND_BASE 0x7e800000 -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#define CFG_SYS_NAND_BASE 0x7e800000 +#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE -#define CONFIG_SYS_NAND_CSPR_EXT (0x0) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ +#define CFG_SYS_NAND_CSPR_EXT (0x0) +#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_NAND \ | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ +#define CFG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) +#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ @@ -31,31 +31,31 @@ | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \ | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ +#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ FTIM0_NAND_TWP(0x18) | \ FTIM0_NAND_TWCHT(0x7) | \ FTIM0_NAND_TWH(0xa)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ +#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ FTIM1_NAND_TWBE(0x39) | \ FTIM1_NAND_TRR(0xe) | \ FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ +#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ FTIM2_NAND_TREH(0xa) | \ FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 +#define CFG_SYS_NAND_FTIM3 0x0 -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #define CONFIG_MTD_NAND_VERIFY_WRITE /* IFC Timing Params */ -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 /* EEPROM */ #define I2C_RETIMER_ADDR 0x18 @@ -66,9 +66,8 @@ #define I2C_MUX_CH_RTC 0x1 /* Channel 0*/ /* RTC */ -#define RTC -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 0 I2C bus 0*/ -#define CONFIG_SYS_RTC_BUS_NUM 0 +#define CFG_SYS_I2C_RTC_ADDR 0x51 /* Channel 0 I2C bus 0*/ +#define CFG_SYS_RTC_BUS_NUM 0 /* * Environment diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h index 037d462b5df..553ae841cab 100644 --- a/include/configs/ls1046aqds.h +++ b/include/configs/ls1046aqds.h @@ -33,14 +33,14 @@ /* IFC */ #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) /* - * CONFIG_SYS_FLASH_BASE has the final address (core view) - * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) - * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address + * CFG_SYS_FLASH_BASE has the final address (core view) + * CFG_SYS_FLASH_BASE_PHYS has the final address (IFC view) + * CFG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address * CONFIG_TEXT_BASE is linked to 0x60000000 for booting */ -#define CONFIG_SYS_FLASH_BASE 0x60000000 -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 +#define CFG_SYS_FLASH_BASE 0x60000000 +#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE +#define CFG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 #ifdef CONFIG_MTD_NOR_FLASH #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ @@ -58,54 +58,54 @@ * IFC Definitions */ #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ +#define CFG_SYS_NOR0_CSPR_EXT (0x0) +#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR1_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ +#define CFG_SYS_NOR1_CSPR_EXT (0x0) +#define CFG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS \ + 0x8000000) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) +#define CFG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) -#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ +#define CFG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ CSOR_NOR_TRHZ_80) -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ +#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ FTIM0_NOR_TEADC(0x5) | \ FTIM0_NOR_TAVDS(0x6) | \ FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ +#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ FTIM1_NOR_TRAD_NOR(0x1a) | \ FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \ +#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \ FTIM2_NOR_TCH(0x8) | \ FTIM2_NOR_TWPH(0xe) | \ FTIM2_NOR_TWP(0x1c)) -#define CONFIG_SYS_NOR_FTIM3 0 +#define CFG_SYS_NOR_FTIM3 0 -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ - CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} +#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS, \ + CFG_SYS_FLASH_BASE_PHYS + 0x8000000} -#define CONFIG_SYS_WRITE_SWAPPED_DATA +#define CFG_SYS_WRITE_SWAPPED_DATA /* * NAND Flash Definitions */ -#define CONFIG_SYS_NAND_BASE 0x7e800000 -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#define CFG_SYS_NAND_BASE 0x7e800000 +#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE -#define CONFIG_SYS_NAND_CSPR_EXT (0x0) +#define CFG_SYS_NAND_CSPR_EXT (0x0) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ +#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_NAND \ | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ +#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024) +#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \ | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ @@ -113,25 +113,25 @@ | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ +#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ FTIM0_NAND_TWP(0x18) | \ FTIM0_NAND_TWCHT(0x7) | \ FTIM0_NAND_TWH(0xa)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ +#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ FTIM1_NAND_TWBE(0x39) | \ FTIM1_NAND_TRR(0xe) | \ FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ +#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ FTIM2_NAND_TREH(0xa) | \ FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 +#define CFG_SYS_NAND_FTIM3 0x0 -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #define CONFIG_MTD_NAND_VERIFY_WRITE #endif #ifdef CONFIG_NAND_BOOT -#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) +#define CFG_SYS_NAND_U_BOOT_SIZE (768 << 10) #endif #if defined(CONFIG_TFABOOT) || \ @@ -145,7 +145,7 @@ #ifdef CONFIG_FSL_QIXIS #define QIXIS_BASE 0x7fb00000 #define QIXIS_BASE_PHYS QIXIS_BASE -#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define CFG_SYS_I2C_FPGA_ADDR 0x66 #define QIXIS_LBMAP_SWITCH 6 #define QIXIS_LBMAP_MASK 0x0f #define QIXIS_LBMAP_SHIFT 0 @@ -163,130 +163,130 @@ #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 -#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) -#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ +#define CFG_SYS_FPGA_CSPR_EXT (0x0) +#define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ CSPR_PORT_SIZE_8 | \ CSPR_MSEL_GPCM | \ CSPR_V) -#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) -#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ +#define CFG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) +#define CFG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ CSOR_NOR_NOR_MODE_AVD_NOR | \ CSOR_NOR_TRHZ_80) /* * QIXIS Timing parameters for IFC GPCM */ -#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \ +#define CFG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \ FTIM0_GPCM_TEADC(0x20) | \ FTIM0_GPCM_TEAHC(0x10)) -#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \ +#define CFG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \ FTIM1_GPCM_TRAD(0x1f)) -#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \ +#define CFG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \ FTIM2_GPCM_TCH(0x8) | \ FTIM2_GPCM_TWP(0xf0)) -#define CONFIG_SYS_FPGA_FTIM3 0x0 +#define CFG_SYS_FPGA_FTIM3 0x0 #endif #ifdef CONFIG_TFABOOT -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 -#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 -#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 -#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR1_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT +#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR +#define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK +#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR +#define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0 +#define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1 +#define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2 +#define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3 #else #ifdef CONFIG_NAND_BOOT -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 -#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 -#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 -#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NOR1_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NOR1_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT +#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR +#define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK +#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR +#define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0 +#define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1 +#define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2 +#define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3 #else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 -#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 -#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 -#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR1_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT +#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR +#define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK +#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR +#define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0 +#define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1 +#define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2 +#define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3 #endif #endif diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h index 769349336af..f3904e7b3f7 100644 --- a/include/configs/ls1046ardb.h +++ b/include/configs/ls1046ardb.h @@ -16,19 +16,19 @@ #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #if defined(CONFIG_QSPI_BOOT) -#define CONFIG_SYS_UBOOT_BASE 0x40100000 +#define CFG_SYS_UBOOT_BASE 0x40100000 #endif -#define CONFIG_SYS_NAND_BASE 0x7e800000 -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#define CFG_SYS_NAND_BASE 0x7e800000 +#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE -#define CONFIG_SYS_NAND_CSPR_EXT (0x0) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ +#define CFG_SYS_NAND_CSPR_EXT (0x0) +#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_NAND \ | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ +#define CFG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) +#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \ | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ @@ -36,65 +36,65 @@ | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ +#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ FTIM0_NAND_TWP(0x18) | \ FTIM0_NAND_TWCHT(0x7) | \ FTIM0_NAND_TWH(0xa)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ +#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ FTIM1_NAND_TWBE(0x39) | \ FTIM1_NAND_TRR(0xe) | \ FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ +#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ FTIM2_NAND_TREH(0xa) | \ FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 +#define CFG_SYS_NAND_FTIM3 0x0 -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #define CONFIG_MTD_NAND_VERIFY_WRITE /* * CPLD */ -#define CONFIG_SYS_CPLD_BASE 0x7fb00000 -#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE +#define CFG_SYS_CPLD_BASE 0x7fb00000 +#define CPLD_BASE_PHYS CFG_SYS_CPLD_BASE -#define CONFIG_SYS_CPLD_CSPR_EXT (0x0) -#define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ +#define CFG_SYS_CPLD_CSPR_EXT (0x0) +#define CFG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ CSPR_PORT_SIZE_8 | \ CSPR_MSEL_GPCM | \ CSPR_V) -#define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024) -#define CONFIG_SYS_CPLD_CSOR CSOR_NOR_ADM_SHIFT(16) +#define CFG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024) +#define CFG_SYS_CPLD_CSOR CSOR_NOR_ADM_SHIFT(16) /* CPLD Timing parameters for IFC GPCM */ -#define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ +#define CFG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ FTIM0_GPCM_TEADC(0x0e) | \ FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ +#define CFG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ FTIM1_GPCM_TRAD(0x3f)) -#define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ +#define CFG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ FTIM2_GPCM_TCH(0xf) | \ FTIM2_GPCM_TWP(0x3E)) -#define CONFIG_SYS_CPLD_FTIM3 0x0 +#define CFG_SYS_CPLD_FTIM3 0x0 /* IFC Timing Params */ -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 - -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 + +#define CFG_SYS_CSPR2_EXT CFG_SYS_CPLD_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_CPLD_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_CPLD_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_CPLD_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_CPLD_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_CPLD_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_CPLD_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_CPLD_FTIM3 /* EEPROM */ #define I2C_RETIMER_ADDR 0x18 diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h index 73e4ac3e3d4..57429d4bbe3 100644 --- a/include/configs/ls1088a_common.h +++ b/include/configs/ls1088a_common.h @@ -30,10 +30,10 @@ #define CFG_SYS_FSL_QSPI_BASE 0x20000000 #define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL /* * SMP Definitinos */ @@ -45,9 +45,7 @@ /* Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2) +#define CFG_SYS_NS16550_CLK (get_bus_freq(0) / 2) /* * During booting, IFC is mapped at the region of 0x30000000. @@ -66,18 +64,18 @@ * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet) * * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation. - * CONFIG_SYS_FLASH_BASE has the final address (core view) - * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) - * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address + * CFG_SYS_FLASH_BASE has the final address (core view) + * CFG_SYS_FLASH_BASE_PHYS has the final address (IFC view) + * CFG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address * CONFIG_TEXT_BASE is linked to 0x30000000 for booting */ -#define CONFIG_SYS_FLASH_BASE 0x580000000ULL -#define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000 -#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 +#define CFG_SYS_FLASH_BASE 0x580000000ULL +#define CFG_SYS_FLASH_BASE_PHYS 0x80000000 +#define CFG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 -#define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000 -#define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000 +#define CFG_SYS_FLASH1_BASE_PHYS 0xC0000000 +#define CFG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000 #ifndef __ASSEMBLY__ unsigned long long get_qixis_addr(void); @@ -88,18 +86,18 @@ unsigned long long get_qixis_addr(void); #define QIXIS_BASE_PHYS_EARLY 0xC000000 -#define CONFIG_SYS_NAND_BASE 0x530000000ULL -#define CONFIG_SYS_NAND_BASE_PHYS 0x30000000 +#define CFG_SYS_NAND_BASE 0x530000000ULL +#define CFG_SYS_NAND_BASE_PHYS 0x30000000 /* MC firmware */ /* TODO Actual DPL max length needs to be confirmed with the MC FW team */ -#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 -#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 -#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 -#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 -#define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000 -#define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000 +#define CFG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 +#define CFG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 +#define CFG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 +#define CFG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 +#define CFG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000 +#define CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000 /* * Carve out a DDR region which will not be used by u-boot/Linux @@ -109,14 +107,13 @@ unsigned long long get_qixis_addr(void); */ #if defined(CONFIG_FSL_MC_ENET) -#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024) +#define CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024) #endif /* Miscellaneous configurable options */ /* Physical Memory Map */ -#define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 #ifndef SPL_NO_ENV diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h index d50b76b89ae..a35045d640f 100644 --- a/include/configs/ls1088aqds.h +++ b/include/configs/ls1088aqds.h @@ -22,64 +22,61 @@ * IFC Definitions */ #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) -#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) +#define CFG_SYS_NOR0_CSPR_EXT (0x0) +#define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) +#define CFG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) -#define CONFIG_SYS_NOR0_CSPR \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ +#define CFG_SYS_NOR0_CSPR \ + (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR0_CSPR_EARLY \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ +#define CFG_SYS_NOR0_CSPR_EARLY \ + (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS_EARLY) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR1_CSPR \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \ +#define CFG_SYS_NOR1_CSPR \ + (CSPR_PHYS_ADDR(CFG_SYS_FLASH1_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR1_CSPR_EARLY \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \ +#define CFG_SYS_NOR1_CSPR_EARLY \ + (CSPR_PHYS_ADDR(CFG_SYS_FLASH1_BASE_PHYS_EARLY) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ +#define CFG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) +#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ FTIM0_NOR_TEADC(0x5) | \ FTIM0_NOR_TAVDS(0x6) | \ FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ +#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ FTIM1_NOR_TRAD_NOR(0x1a) | \ FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \ +#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \ FTIM2_NOR_TCH(0x8) | \ FTIM2_NOR_TWPH(0xe) | \ FTIM2_NOR_TWP(0x1c)) -#define CONFIG_SYS_NOR_FTIM3 0x04000000 -#define CONFIG_SYS_IFC_CCR 0x01000000 +#define CFG_SYS_NOR_FTIM3 0x04000000 +#define CFG_SYS_IFC_CCR 0x01000000 #ifndef SYS_NO_FLASH #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ - CONFIG_SYS_FLASH_BASE + 0x40000000} +#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE,\ + CFG_SYS_FLASH_BASE + 0x40000000} #endif #endif -#define CONFIG_SYS_NAND_MAX_ECCPOS 256 -#define CONFIG_SYS_NAND_MAX_OOBFREE 2 - -#define CONFIG_SYS_NAND_CSPR_EXT (0x0) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ +#define CFG_SYS_NAND_CSPR_EXT (0x0) +#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \ | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ | CSPR_MSEL_NAND /* MSEL = NAND */ \ | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) +#define CFG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ +#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ @@ -88,23 +85,23 @@ | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ /* ONFI NAND Flash mode0 Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ +#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ FTIM0_NAND_TWP(0x18) | \ FTIM0_NAND_TWCHT(0x07) | \ FTIM0_NAND_TWH(0x0a)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ +#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ FTIM1_NAND_TWBE(0x39) | \ FTIM1_NAND_TRR(0x0e) | \ FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ +#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ FTIM2_NAND_TREH(0x0a) | \ FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 +#define CFG_SYS_NAND_FTIM3 0x0 -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #define CONFIG_MTD_NAND_VERIFY_WRITE -#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define CFG_SYS_I2C_FPGA_ADDR 0x66 #define QIXIS_LBMAP_SWITCH 6 #define QIXIS_QMAP_MASK 0xe0 #define QIXIS_QMAP_SHIFT 5 @@ -130,8 +127,8 @@ #define QIXIS_SDID_MASK 0x07 #define QIXIS_ESDHC_NO_ADAPTER 0x7 -#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) -#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ +#define CFG_SYS_FPGA_CSPR_EXT (0x0) +#define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) @@ -142,9 +139,9 @@ #define SYS_FPGA_AMASK IFC_AMASK(64 * 1024) #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0) +#define CFG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0) #else -#define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(12) +#define CFG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(12) #endif /* QIXIS Timing parameters*/ #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ @@ -158,102 +155,102 @@ #define SYS_FPGA_CS_FTIM3 0x0 #ifdef CONFIG_TFABOOT -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY -#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY -#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY -#define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL -#define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0 -#define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1 -#define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2 -#define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR_EARLY +#define CFG_SYS_CSPR0_FINAL CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR_EARLY +#define CFG_SYS_CSPR1_FINAL CFG_SYS_NOR1_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK_EARLY +#define CFG_SYS_AMASK1_FINAL CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT +#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR +#define CFG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL +#define CFG_SYS_AMASK3 SYS_FPGA_AMASK +#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR +#define CFG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0 +#define CFG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1 +#define CFG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2 +#define CFG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3 #else #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL -#define CONFIG_SYS_AMASK2 SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_FPGA_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_FPGA_CSPR +#define CFG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL +#define CFG_SYS_AMASK2 SYS_FPGA_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_FPGA_CSOR +#define CFG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0 +#define CFG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1 +#define CFG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2 +#define CFG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3 #else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY -#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY -#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY -#define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL -#define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0 -#define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1 -#define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2 -#define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR_EARLY +#define CFG_SYS_CSPR0_FINAL CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR_EARLY +#define CFG_SYS_CSPR1_FINAL CFG_SYS_NOR1_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK_EARLY +#define CFG_SYS_AMASK1_FINAL CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT +#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR +#define CFG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL +#define CFG_SYS_AMASK3 SYS_FPGA_AMASK +#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR +#define CFG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0 +#define CFG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1 +#define CFG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2 +#define CFG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3 #endif #endif -#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 +#define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 /* * I2C bus multiplexer @@ -283,8 +280,7 @@ /* * RTC configuration */ -#define RTC -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ +#define CFG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ #ifdef CONFIG_FSL_DSPI #if !defined(CONFIG_TFABOOT) && \ diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h index 4edf40b0b72..7bc4fc6a665 100644 --- a/include/configs/ls1088ardb.h +++ b/include/configs/ls1088ardb.h @@ -20,50 +20,47 @@ #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) -#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64 * 1024 * 1024) +#define CFG_SYS_NOR0_CSPR_EXT (0x0) +#define CFG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) +#define CFG_SYS_NOR_AMASK_EARLY IFC_AMASK(64 * 1024 * 1024) -#define CONFIG_SYS_NOR0_CSPR \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ +#define CFG_SYS_NOR0_CSPR \ + (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR0_CSPR_EARLY \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ +#define CFG_SYS_NOR0_CSPR_EARLY \ + (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS_EARLY) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(6) -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ +#define CFG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(6) +#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ FTIM0_NOR_TEADC(0x1) | \ FTIM0_NOR_TEAHC(0x1)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ +#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ FTIM1_NOR_TRAD_NOR(0x1)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \ +#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \ FTIM2_NOR_TCH(0x0) | \ FTIM2_NOR_TWP(0x1)) -#define CONFIG_SYS_NOR_FTIM3 0x04000000 -#define CONFIG_SYS_IFC_CCR 0x01000000 +#define CFG_SYS_NOR_FTIM3 0x04000000 +#define CFG_SYS_IFC_CCR 0x01000000 #ifndef SYS_NO_FLASH #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } +#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE } #endif #endif -#define CONFIG_SYS_NAND_MAX_ECCPOS 256 -#define CONFIG_SYS_NAND_MAX_OOBFREE 2 - -#define CONFIG_SYS_NAND_CSPR_EXT (0x0) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ +#define CFG_SYS_NAND_CSPR_EXT (0x0) +#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \ | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ | CSPR_MSEL_NAND /* MSEL = NAND */ \ | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) +#define CFG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ +#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ @@ -72,23 +69,23 @@ | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ /* ONFI NAND Flash mode0 Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ +#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ FTIM0_NAND_TWP(0x18) | \ FTIM0_NAND_TWCHT(0x07) | \ FTIM0_NAND_TWH(0x0a)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ +#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ FTIM1_NAND_TWBE(0x39) | \ FTIM1_NAND_TRR(0x0e) | \ FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ +#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ FTIM2_NAND_TREH(0x0a) | \ FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 +#define CFG_SYS_NAND_FTIM3 0x0 -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #define CONFIG_MTD_NAND_VERIFY_WRITE -#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define CFG_SYS_I2C_FPGA_ADDR 0x66 #define QIXIS_BRDCFG4_OFFSET 0x54 #define QIXIS_LBMAP_SWITCH 2 #define QIXIS_QMAP_MASK 0xe0 @@ -110,8 +107,8 @@ #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 #define QIXIS_RST_FORCE_MEM 0x01 -#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) -#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ +#define CFG_SYS_FPGA_CSPR_EXT (0x0) +#define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) @@ -120,8 +117,8 @@ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64*1024) -#define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0) +#define CFG_SYS_FPGA_AMASK IFC_AMASK(64*1024) +#define CFG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0) /* QIXIS Timing parameters*/ #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ FTIM0_GPCM_TEADC(0x0e) | \ @@ -135,36 +132,36 @@ #if defined(CONFIG_TFABOOT) || \ defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL -#define CONFIG_SYS_AMASK2 CONFIG_SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_FPGA_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_FPGA_CSPR +#define CFG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL +#define CFG_SYS_AMASK2 CFG_SYS_FPGA_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_FPGA_CSOR +#define CFG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0 +#define CFG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1 +#define CFG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2 +#define CFG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3 #else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY -#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR_EARLY +#define CFG_SYS_CSPR0_FINAL CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 #endif -#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 +#define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 #define I2C_MUX_CH_VOL_MONITOR 0xA /* Voltage monitor on channel 2*/ @@ -189,13 +186,10 @@ #define I2C_MUX_CH_DEFAULT 0x8 #define I2C_MUX_CH5 0xD -#ifndef SPL_NO_RTC /* * RTC configuration */ -#define RTC -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ -#endif +#define CFG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ #ifndef SPL_NO_ENV /* Initial environment variables */ diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 53a3af1baac..e82456fd814 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -17,10 +17,10 @@ /* Link Definitions */ #define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL /* * SMP Definitinos @@ -37,9 +37,7 @@ /* I2C */ /* Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_serial_clock()) +#define CFG_SYS_NS16550_CLK (get_serial_clock()) /* * During booting, IFC is mapped at the region of 0x30000000. @@ -58,18 +56,18 @@ * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet) * * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation. - * CONFIG_SYS_FLASH_BASE has the final address (core view) - * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) - * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address + * CFG_SYS_FLASH_BASE has the final address (core view) + * CFG_SYS_FLASH_BASE_PHYS has the final address (IFC view) + * CFG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address * CONFIG_TEXT_BASE is linked to 0x30000000 for booting */ -#define CONFIG_SYS_FLASH_BASE 0x580000000ULL -#define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000 -#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 +#define CFG_SYS_FLASH_BASE 0x580000000ULL +#define CFG_SYS_FLASH_BASE_PHYS 0x80000000 +#define CFG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 -#define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000 -#define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000 +#define CFG_SYS_FLASH1_BASE_PHYS 0xC0000000 +#define CFG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000 #ifndef __ASSEMBLY__ unsigned long long get_qixis_addr(void); @@ -81,18 +79,18 @@ unsigned long long get_qixis_addr(void); #define QIXIS_SDID_MASK 0x07 #define QIXIS_ESDHC_NO_ADAPTER 0x7 -#define CONFIG_SYS_NAND_BASE 0x530000000ULL -#define CONFIG_SYS_NAND_BASE_PHYS 0x30000000 +#define CFG_SYS_NAND_BASE 0x530000000ULL +#define CFG_SYS_NAND_BASE_PHYS 0x30000000 /* MC firmware */ /* TODO Actual DPL max length needs to be confirmed with the MC FW team */ -#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 -#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 -#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 -#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 +#define CFG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 +#define CFG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 +#define CFG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 +#define CFG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 /* For LS2085A */ -#define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000 -#define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000 +#define CFG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000 +#define CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000 /* * Carve out a DDR region which will not be used by u-boot/Linux @@ -101,7 +99,7 @@ unsigned long long get_qixis_addr(void); * 512MB aligned, so the min size to hide is 512MB. */ #ifdef CONFIG_FSL_MC_ENET -#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024) +#define CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024) #endif /* Miscellaneous configurable options */ @@ -109,7 +107,6 @@ unsigned long long get_qixis_addr(void); /* Physical Memory Map */ /* fixme: these need to be checked against the board */ -#define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 /* Initial environment variables */ @@ -129,8 +126,8 @@ unsigned long long get_qixis_addr(void); " 0x580e00000 \0" #ifdef CONFIG_NAND_BOOT -#define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000 -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST +#define CFG_SYS_NAND_U_BOOT_DST 0x80400000 +#define CFG_SYS_NAND_U_BOOT_START CFG_SYS_NAND_U_BOOT_DST #endif #include <asm/arch/soc.h> diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 1fa4aa3734d..924d4057d93 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -10,10 +10,10 @@ #include "ls2080a_common.h" #ifdef CONFIG_FSL_QSPI -#define CONFIG_SYS_I2C_IFDR_DIV 0x7e +#define CFG_SYS_I2C_IFDR_DIV 0x7e #endif -#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define CFG_SYS_I2C_FPGA_ADDR 0x66 #define COUNTER_FREQUENCY_REAL (get_board_sys_clk()/4) #define CONFIG_MEM_INIT_VALUE 0xdeadbeef @@ -25,62 +25,59 @@ #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */ #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 -#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) -#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) +#define CFG_SYS_NOR0_CSPR_EXT (0x0) +#define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) +#define CFG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) -#define CONFIG_SYS_NOR0_CSPR \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ +#define CFG_SYS_NOR0_CSPR \ + (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR0_CSPR_EARLY \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ +#define CFG_SYS_NOR0_CSPR_EARLY \ + (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS_EARLY) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR1_CSPR \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \ +#define CFG_SYS_NOR1_CSPR \ + (CSPR_PHYS_ADDR(CFG_SYS_FLASH1_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR1_CSPR_EARLY \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \ +#define CFG_SYS_NOR1_CSPR_EARLY \ + (CSPR_PHYS_ADDR(CFG_SYS_FLASH1_BASE_PHYS_EARLY) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ +#define CFG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) +#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ FTIM0_NOR_TEADC(0x5) | \ FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ +#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ FTIM1_NOR_TRAD_NOR(0x1a) |\ FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ +#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ FTIM2_NOR_TCH(0x4) | \ FTIM2_NOR_TWPH(0x0E) | \ FTIM2_NOR_TWP(0x1c)) -#define CONFIG_SYS_NOR_FTIM3 0x04000000 -#define CONFIG_SYS_IFC_CCR 0x01000000 +#define CFG_SYS_NOR_FTIM3 0x04000000 +#define CFG_SYS_IFC_CCR 0x01000000 #ifdef CONFIG_MTD_NOR_FLASH #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ - CONFIG_SYS_FLASH_BASE + 0x40000000} +#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE,\ + CFG_SYS_FLASH_BASE + 0x40000000} #endif -#define CONFIG_SYS_NAND_MAX_ECCPOS 256 -#define CONFIG_SYS_NAND_MAX_OOBFREE 2 - -#define CONFIG_SYS_NAND_CSPR_EXT (0x0) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ +#define CFG_SYS_NAND_CSPR_EXT (0x0) +#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \ | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ | CSPR_MSEL_NAND /* MSEL = NAND */ \ | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) +#define CFG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ +#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ @@ -89,20 +86,20 @@ | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ /* ONFI NAND Flash mode0 Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ +#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ FTIM0_NAND_TWP(0x18) | \ FTIM0_NAND_TWCHT(0x07) | \ FTIM0_NAND_TWH(0x0a)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ +#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ FTIM1_NAND_TWBE(0x39) | \ FTIM1_NAND_TRR(0x0e) | \ FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ +#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ FTIM2_NAND_TREH(0x0a) | \ FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 +#define CFG_SYS_NAND_FTIM3 0x0 -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #define CONFIG_MTD_NAND_VERIFY_WRITE #define QIXIS_LBMAP_SWITCH 0x06 @@ -122,92 +119,92 @@ #define QIXIS_RCW_SRC_QSPI 0x62 #define QIXIS_RST_FORCE_MEM 0x01 -#define CONFIG_SYS_CSPR3_EXT (0x0) -#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ +#define CFG_SYS_CSPR3_EXT (0x0) +#define CFG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ +#define CFG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) -#define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12) +#define CFG_SYS_AMASK3 IFC_AMASK(64*1024) +#define CFG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12) /* QIXIS Timing parameters for IFC CS3 */ -#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ +#define CFG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ FTIM0_GPCM_TEADC(0x0e) | \ FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ +#define CFG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ FTIM1_GPCM_TRAD(0x3f)) -#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ +#define CFG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ FTIM2_GPCM_TCH(0xf) | \ FTIM2_GPCM_TWP(0x3E)) -#define CONFIG_SYS_CS3_FTIM3 0x0 +#define CFG_SYS_CS3_FTIM3 0x0 #if defined(CONFIG_SPL) #if defined(CONFIG_NAND_BOOT) -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR_EARLY -#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR_EARLY -#define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK_EARLY -#define CONFIG_SYS_AMASK2_FINAL CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 - -#define CONFIG_SYS_NAND_U_BOOT_SIZE (640 * 1024) +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR0_CSPR_EARLY +#define CFG_SYS_CSPR1_FINAL CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NOR1_CSPR_EARLY +#define CFG_SYS_CSPR2_FINAL CFG_SYS_NOR1_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK_EARLY +#define CFG_SYS_AMASK2_FINAL CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 + +#define CFG_SYS_NAND_U_BOOT_SIZE (640 * 1024) #endif #else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY -#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY -#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY -#define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR_EARLY +#define CFG_SYS_CSPR0_FINAL CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR_EARLY +#define CFG_SYS_CSPR1_FINAL CFG_SYS_NOR1_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK_EARLY +#define CFG_SYS_AMASK1_FINAL CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 #endif -#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 +#define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 /* * I2C @@ -230,9 +227,7 @@ /* * RTC configuration */ -#define RTC -#define CONFIG_RTC_DS3231 1 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CFG_SYS_I2C_RTC_ADDR 0x68 /* Initial environment variables */ #undef CONFIG_EXTRA_ENV_SETTINGS diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index e1c66c5dcc0..c50b6030680 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -32,52 +32,49 @@ #if !defined(CONFIG_FSL_QSPI) || defined(CONFIG_TFABOOT) -#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) -#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) +#define CFG_SYS_NOR0_CSPR_EXT (0x0) +#define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) +#define CFG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) -#define CONFIG_SYS_NOR0_CSPR \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ +#define CFG_SYS_NOR0_CSPR \ + (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR0_CSPR_EARLY \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ +#define CFG_SYS_NOR0_CSPR_EARLY \ + (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS_EARLY) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ +#define CFG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) +#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ FTIM0_NOR_TEADC(0x5) | \ FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ +#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ FTIM1_NOR_TRAD_NOR(0x1a) |\ FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ +#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ FTIM2_NOR_TCH(0x4) | \ FTIM2_NOR_TWPH(0x0E) | \ FTIM2_NOR_TWP(0x1c)) -#define CONFIG_SYS_NOR_FTIM3 0x04000000 -#define CONFIG_SYS_IFC_CCR 0x01000000 +#define CFG_SYS_NOR_FTIM3 0x04000000 +#define CFG_SYS_IFC_CCR 0x01000000 #ifdef CONFIG_MTD_NOR_FLASH #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ - CONFIG_SYS_FLASH_BASE + 0x40000000} +#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE,\ + CFG_SYS_FLASH_BASE + 0x40000000} #endif -#define CONFIG_SYS_NAND_MAX_ECCPOS 256 -#define CONFIG_SYS_NAND_MAX_OOBFREE 2 - -#define CONFIG_SYS_NAND_CSPR_EXT (0x0) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ +#define CFG_SYS_NAND_CSPR_EXT (0x0) +#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \ | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ | CSPR_MSEL_NAND /* MSEL = NAND */ \ | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) +#define CFG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ +#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ @@ -86,20 +83,20 @@ | CSOR_NAND_PB(128)) /* Pages Per Block 128*/ /* ONFI NAND Flash mode0 Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x0e) | \ +#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x0e) | \ FTIM0_NAND_TWP(0x30) | \ FTIM0_NAND_TWCHT(0x0e) | \ FTIM0_NAND_TWH(0x14)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x64) | \ +#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x64) | \ FTIM1_NAND_TWBE(0xab) | \ FTIM1_NAND_TRR(0x1c) | \ FTIM1_NAND_TRP(0x30)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x1e) | \ +#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x1e) | \ FTIM2_NAND_TREH(0x14) | \ FTIM2_NAND_TWHRE(0x3c)) -#define CONFIG_SYS_NAND_FTIM3 0x0 +#define CFG_SYS_NAND_FTIM3 0x0 -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #define CONFIG_MTD_NAND_VERIFY_WRITE #define QIXIS_LBMAP_SWITCH 0x06 @@ -116,70 +113,70 @@ #define QIXIS_RCW_SRC_NAND 0x119 #define QIXIS_RST_FORCE_MEM 0x01 -#define CONFIG_SYS_CSPR3_EXT (0x0) -#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ +#define CFG_SYS_CSPR3_EXT (0x0) +#define CFG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ +#define CFG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) -#define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12) +#define CFG_SYS_AMASK3 IFC_AMASK(64*1024) +#define CFG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12) /* QIXIS Timing parameters for IFC CS3 */ -#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ +#define CFG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ FTIM0_GPCM_TEADC(0x0e) | \ FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ +#define CFG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ FTIM1_GPCM_TRAD(0x3f)) -#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ +#define CFG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ FTIM2_GPCM_TCH(0xf) | \ FTIM2_GPCM_TWP(0x3E)) -#define CONFIG_SYS_CS3_FTIM3 0x0 +#define CFG_SYS_CS3_FTIM3 0x0 #if defined(CONFIG_SPL) && defined(CONFIG_MTD_RAW_NAND) -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR_EARLY -#define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 - -#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024) +#define CFG_SYS_CSPR2_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NOR0_CSPR_EARLY +#define CFG_SYS_CSPR2_FINAL CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 + +#define CFG_SYS_NAND_U_BOOT_SIZE (512 * 1024) #else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY -#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR_EARLY +#define CFG_SYS_CSPR0_FINAL CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 #endif #endif -#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 +#define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 #ifdef CONFIG_TARGET_LS2081ARDB #define QIXIS_QMAP_MASK 0x07 @@ -200,7 +197,7 @@ * I2C */ #ifdef CONFIG_TARGET_LS2081ARDB -#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define CFG_SYS_I2C_FPGA_ADDR 0x66 #endif #define I2C_MUX_PCA_ADDR 0x75 #define I2C_MUX_PCA_ADDR_PRI 0x75 /* Primary Mux*/ @@ -213,12 +210,10 @@ /* * RTC configuration */ -#define RTC #ifdef CONFIG_TARGET_LS2081ARDB -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 +#define CFG_SYS_I2C_RTC_ADDR 0x51 #else -#define CONFIG_RTC_DS3231 1 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CFG_SYS_I2C_RTC_ADDR 0x68 #endif #define BOOT_TARGET_DEVICES(func) \ diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index 8b2b7479c11..a469c83fa4e 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -10,15 +10,15 @@ #include <asm/arch/config.h> #include <asm/arch/soc.h> -#define CONFIG_SYS_FLASH_BASE 0x20000000 +#define CFG_SYS_FLASH_BASE 0x20000000 /* DDR */ #define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 -#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL -#define CONFIG_SYS_SDRAM_SIZE 0x200000000UL -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL +#define CFG_SYS_SDRAM_SIZE 0x200000000UL +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 @@ -42,22 +42,22 @@ /* Serial Port */ #define CONFIG_PL011_CLOCK (get_bus_freq(0) / 4) -#define CONFIG_SYS_SERIAL0 0x21c0000 -#define CONFIG_SYS_SERIAL1 0x21d0000 -#define CONFIG_SYS_SERIAL2 0x21e0000 -#define CONFIG_SYS_SERIAL3 0x21f0000 +#define CFG_SYS_SERIAL0 0x21c0000 +#define CFG_SYS_SERIAL1 0x21d0000 +#define CFG_SYS_SERIAL2 0x21e0000 +#define CFG_SYS_SERIAL3 0x21f0000 /*below might needs to be removed*/ -#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \ - (void *)CONFIG_SYS_SERIAL1, \ - (void *)CONFIG_SYS_SERIAL2, \ - (void *)CONFIG_SYS_SERIAL3 } +#define CONFIG_PL01x_PORTS {(void *)CFG_SYS_SERIAL0, \ + (void *)CFG_SYS_SERIAL1, \ + (void *)CFG_SYS_SERIAL2, \ + (void *)CFG_SYS_SERIAL3 } /* MC firmware */ -#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 -#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 -#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 -#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 -#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 +#define CFG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 +#define CFG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 +#define CFG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 +#define CFG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 +#define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 /* * Carve out a DDR region which will not be used by u-boot/Linux @@ -66,7 +66,7 @@ * 512MB aligned, so the min size to hide is 512MB. */ #ifdef CONFIG_FSL_MC_ENET -#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (256UL * 1024 * 1024) +#define CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (256UL * 1024 * 1024) #endif /* I2C bus multiplexer */ @@ -74,17 +74,15 @@ #define I2C_MUX_CH_DEFAULT 0x8 /* RTC */ -#define RTC -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ +#define CFG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ /* Qixis */ -#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define CFG_SYS_I2C_FPGA_ADDR 0x66 /* USB */ #define COUNTER_FREQUENCY_REAL (get_board_sys_clk() / 4) -#define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 /* Initial environment variables */ diff --git a/include/configs/lx2160aqds.h b/include/configs/lx2160aqds.h index 4e8a9048596..9f891064bd5 100644 --- a/include/configs/lx2160aqds.h +++ b/include/configs/lx2160aqds.h @@ -9,7 +9,7 @@ #include "lx2160a_common.h" /* RTC */ -#define CONFIG_SYS_RTC_BUS_NUM 0 +#define CFG_SYS_RTC_BUS_NUM 0 /* MAC/PHY configuration */ diff --git a/include/configs/lx2160ardb.h b/include/configs/lx2160ardb.h index bb9239cc599..58c0ff36571 100644 --- a/include/configs/lx2160ardb.h +++ b/include/configs/lx2160ardb.h @@ -9,7 +9,7 @@ #include "lx2160a_common.h" /* RTC */ -#define CONFIG_SYS_RTC_BUS_NUM 4 +#define CFG_SYS_RTC_BUS_NUM 4 /* EMC2305 */ #define I2C_MUX_CH_EMC2305 0x09 diff --git a/include/configs/lx2162aqds.h b/include/configs/lx2162aqds.h index b70abb013f4..157688ef7d7 100644 --- a/include/configs/lx2162aqds.h +++ b/include/configs/lx2162aqds.h @@ -11,7 +11,7 @@ /* USB */ /* RTC */ -#define CONFIG_SYS_RTC_BUS_NUM 0 +#define CFG_SYS_RTC_BUS_NUM 0 /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index a20b41bdf07..66591390d90 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -20,9 +20,9 @@ #define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) #define PHYS_SDRAM_SIZE (gd->ram_size) -#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) -#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) -#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) +#define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1) +#define CFG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) +#define CFG_SYS_INIT_RAM_SIZE (IRAM_SIZE) /* * U-Boot general configurations @@ -44,10 +44,10 @@ * NAND */ #ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR_AXI +#define CFG_SYS_NAND_BASE NFC_BASE_ADDR_AXI #define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI #define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR -#define CONFIG_SYS_NAND_LARGEPAGE +#define CFG_SYS_NAND_LARGEPAGE #define CONFIG_MXC_NAND_HWECC #endif @@ -58,13 +58,13 @@ #define CONFIG_FEC_MXC_PHYADDR 0x0 #endif -#define CONFIG_SYS_RTC_BUS_NUM 1 /* I2C2 */ +#define CFG_SYS_RTC_BUS_NUM 1 /* I2C2 */ /* * RTC */ #ifdef CONFIG_CMD_DATE -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CFG_SYS_I2C_RTC_ADDR 0x68 #endif /* @@ -77,21 +77,11 @@ #endif /* LVDS display */ -#define CONFIG_SYS_LDB_CLOCK 33260000 -#define CONFIG_IMX_VIDEO_SKIP - -/* IIM Fuses */ -#define CONFIG_FSL_IIM +#define CFG_SYS_LDB_CLOCK 33260000 /* Watchdog */ /* - * NAND SPL - */ - -#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) - -/* * Extra Environments */ #define CONFIG_HOSTNAME "m53menlo" diff --git a/include/configs/malta.h b/include/configs/malta.h index 30c2e41eec5..65f4b05649b 100644 --- a/include/configs/malta.h +++ b/include/configs/malta.h @@ -22,26 +22,25 @@ */ #ifdef CONFIG_64BIT -# define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000 +# define CFG_SYS_SDRAM_BASE 0xffffffff80000000 #else -# define CONFIG_SYS_SDRAM_BASE 0x80000000 +# define CFG_SYS_SDRAM_BASE 0x80000000 #endif -#define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 MiB */ +#define CFG_SYS_SDRAM_SIZE 0x10000000 /* 256 MiB */ -#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 +#define CFG_SYS_INIT_SP_OFFSET 0x400000 /* * Serial driver */ -#define CONFIG_SYS_NS16550_PORT_MAPPED /* * Flash configuration */ #ifdef CONFIG_64BIT -# define CONFIG_SYS_FLASH_BASE 0xffffffffbe000000 +# define CFG_SYS_FLASH_BASE 0xffffffffbe000000 #else -# define CONFIG_SYS_FLASH_BASE 0xbe000000 +# define CFG_SYS_FLASH_BASE 0xbe000000 #endif /* diff --git a/include/configs/maxbcm.h b/include/configs/maxbcm.h index db84302231a..5ad945b5589 100644 --- a/include/configs/maxbcm.h +++ b/include/configs/maxbcm.h @@ -47,6 +47,6 @@ */ /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ -#define CONFIG_SYS_SDRAM_SIZE SZ_1G +#define CFG_SYS_SDRAM_SIZE SZ_1G #endif /* _CONFIG_DB_MV7846MP_GP_H */ diff --git a/include/configs/mccmon6.h b/include/configs/mccmon6.h index 69ca7c52753..7c401a2cfd6 100644 --- a/include/configs/mccmon6.h +++ b/include/configs/mccmon6.h @@ -9,9 +9,7 @@ #include "mx6_common.h" -#include "imx6_spl.h" - -#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + 0x80000) +#define CFG_SYS_UBOOT_BASE (CFG_SYS_FLASH_BASE + 0x80000) /* * Below defines are set but NOT really used since we by @@ -26,12 +24,12 @@ #define CFG_SYS_FSL_ESDHC_ADDR 0 /* NOR 16-bit mode */ -#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR +#define CFG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR #define CONFIG_FLASH_VERIFY /* NOR Flash MTD */ -#define CONFIG_SYS_FLASH_BANKS_LIST { (CONFIG_SYS_FLASH_BASE) } -#define CONFIG_SYS_FLASH_BANKS_SIZES { (32 * SZ_1M) } +#define CFG_SYS_FLASH_BANKS_LIST { (CFG_SYS_FLASH_BASE) } +#define CFG_SYS_FLASH_BANKS_SIZES { (32 * SZ_1M) } /* Ethernet Configuration */ #define CONFIG_FEC_MXC_PHYADDR 1 @@ -118,7 +116,7 @@ "nor_img_addr=0x11000000\0" \ "nor_img_file=core-image-lwn-mccmon6.nor\0" \ "emmc_img_file=core-image-lwn-mccmon6.ext4\0" \ - "nor_bank_start=" __stringify(CONFIG_SYS_FLASH_BASE) "\0" \ + "nor_bank_start=" __stringify(CFG_SYS_FLASH_BASE) "\0" \ "nor_img_size=0x02000000\0" \ "factory_script_file=factory.scr\0" \ "factory_load_script=" \ @@ -216,9 +214,9 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* Environment organization */ diff --git a/include/configs/medcom-wide.h b/include/configs/medcom-wide.h index b90a84da8ad..a8d8d8b09e0 100644 --- a/include/configs/medcom-wide.h +++ b/include/configs/medcom-wide.h @@ -16,7 +16,7 @@ /* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */ -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE /* NAND support */ diff --git a/include/configs/meerkat96.h b/include/configs/meerkat96.h index c6ce8837474..9e480fe0558 100644 --- a/include/configs/meerkat96.h +++ b/include/configs/meerkat96.h @@ -17,9 +17,9 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* Environment configs */ diff --git a/include/configs/meesc.h b/include/configs/meesc.h index 9f913fad168..d190e4b5039 100644 --- a/include/configs/meesc.h +++ b/include/configs/meesc.h @@ -28,8 +28,8 @@ */ /* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* 32.768 kHz crystal */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 16000000/* 16.0 MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* 32.768 kHz crystal */ +#define CFG_SYS_AT91_MAIN_CLOCK 16000000/* 16.0 MHz crystal */ /* Misc CPU related */ @@ -44,20 +44,19 @@ #define PHYS_SDRAM ATMEL_BASE_CS1 /* 0x20000000 */ #define PHYS_SDRAM_SIZE 0x02000000 /* 32 MByte */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_SIZE +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_SIZE PHYS_SDRAM_SIZE -#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM0 -#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024) +#define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM0 +#define CFG_SYS_INIT_RAM_SIZE (16 * 1024) /* NAND flash */ #ifdef CONFIG_CMD_NAND -# define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 /* 0x40000000 */ -# define CONFIG_SYS_NAND_DBW_8 -# define CONFIG_SYS_NAND_MASK_ALE (1 << 21) -# define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -# define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15) -# define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(22) +# define CFG_SYS_NAND_BASE ATMEL_BASE_CS3 /* 0x40000000 */ +# define CFG_SYS_NAND_MASK_ALE (1 << 21) +# define CFG_SYS_NAND_MASK_CLE (1 << 22) +# define CFG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15) +# define CFG_SYS_NAND_READY_PIN GPIO_PIN_PA(22) #endif /* hw-controller addresses */ diff --git a/include/configs/meson64.h b/include/configs/meson64.h index 726f33c26c2..6331b7615db 100644 --- a/include/configs/meson64.h +++ b/include/configs/meson64.h @@ -36,7 +36,7 @@ #define STDIN_CFG "serial" #endif -#define CONFIG_SYS_SDRAM_BASE 0 +#define CFG_SYS_SDRAM_BASE 0 /* ROM USB boot support, auto-execute boot.scr at scriptaddr */ #define BOOTENV_DEV_ROMUSB(devtypeu, devtypel, instance) \ diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 139b5bca108..edd2466caa9 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -13,7 +13,7 @@ /* uart */ /* The following table includes the supported baudrates */ -# define CONFIG_SYS_BAUDRATE_TABLE \ +# define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} #define CONFIG_HOSTNAME "microblaze-generic" @@ -95,6 +95,6 @@ /* SPL part */ -#define CONFIG_SYS_UBOOT_BASE CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE #endif /* __CONFIG_H */ diff --git a/include/configs/microchip_mpfs_icicle.h b/include/configs/microchip_mpfs_icicle.h index 4c7cfac8af7..3def93d61e8 100644 --- a/include/configs/microchip_mpfs_icicle.h +++ b/include/configs/microchip_mpfs_icicle.h @@ -9,7 +9,7 @@ #include <linux/sizes.h> -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 diff --git a/include/configs/msc_sm2s_imx8mp.h b/include/configs/msc_sm2s_imx8mp.h index bd35378800b..cfe926c0a14 100644 --- a/include/configs/msc_sm2s_imx8mp.h +++ b/include/configs/msc_sm2s_imx8mp.h @@ -14,7 +14,7 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h> -#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) +#define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #if defined(CONFIG_CMD_NET) #define CONFIG_FEC_MXC_PHYADDR 1 @@ -46,10 +46,10 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x80000 -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ #define PHYS_SDRAM_2 0xc0000000 diff --git a/include/configs/mt7620.h b/include/configs/mt7620.h index c76e1fcaed9..d5bd4926348 100644 --- a/include/configs/mt7620.h +++ b/include/configs/mt7620.h @@ -8,15 +8,15 @@ #ifndef __CONFIG_MT7620_H #define __CONFIG_MT7620_H -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 +#define CFG_SYS_INIT_SP_OFFSET 0x400000 /* SPL */ -#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE /* Dummy value */ -#define CONFIG_SYS_UBOOT_BASE 0 +#define CFG_SYS_UBOOT_BASE 0 #endif /* __CONFIG_MT7620_H */ diff --git a/include/configs/mt7621.h b/include/configs/mt7621.h index 9b1ba3655e8..7c8c67f4469 100644 --- a/include/configs/mt7621.h +++ b/include/configs/mt7621.h @@ -8,12 +8,12 @@ #ifndef __CONFIG_MT7621_H #define __CONFIG_MT7621_H -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_VERY_BIG_RAM #define CONFIG_MAX_MEM_MAPPED 0x1c000000 -#define CONFIG_SYS_INIT_SP_OFFSET 0x800000 +#define CFG_SYS_INIT_SP_OFFSET 0x800000 /* MMC */ #define MMC_SUPPORTS_TUNING @@ -22,17 +22,15 @@ /* Serial SPL */ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) -#define CONFIG_SYS_NS16550_MEM32 -#define CONFIG_SYS_NS16550_CLK 50000000 -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#define CONFIG_SYS_NS16550_COM1 0xbe000c00 +#define CFG_SYS_NS16550_CLK 50000000 +#define CFG_SYS_NS16550_COM1 0xbe000c00 #endif /* Serial common */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ +#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ 230400, 460800, 921600 } /* Dummy value */ -#define CONFIG_SYS_UBOOT_BASE 0 +#define CFG_SYS_UBOOT_BASE 0 #endif /* __CONFIG_MT7621_H */ diff --git a/include/configs/mt7622.h b/include/configs/mt7622.h index fd8e30acf59..8c297266d8b 100644 --- a/include/configs/mt7622.h +++ b/include/configs/mt7622.h @@ -10,12 +10,12 @@ #define __MT7622_H /* Uboot definition */ -#define CONFIG_SYS_UBOOT_BASE CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE /* SPL -> Uboot */ -#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE /* DRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 /* Ethernet */ #define CONFIG_IPADDR 192.168.1.1 diff --git a/include/configs/mt7623.h b/include/configs/mt7623.h index 73093f94d2b..39a7ba76633 100644 --- a/include/configs/mt7623.h +++ b/include/configs/mt7623.h @@ -21,7 +21,7 @@ #define MMC_SUPPORTS_TUNING /* DRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 /* This is needed for kernel booting */ #define FDT_HIGH "0xac000000" diff --git a/include/configs/mt7628.h b/include/configs/mt7628.h index 43527017d84..9df2715fc7d 100644 --- a/include/configs/mt7628.h +++ b/include/configs/mt7628.h @@ -8,27 +8,25 @@ #ifndef __CONFIG_MT7628_H #define __CONFIG_MT7628_H -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_INIT_SP_OFFSET 0x80000 +#define CFG_SYS_INIT_SP_OFFSET 0x80000 /* Serial SPL */ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) -#define CONFIG_SYS_NS16550_MEM32 -#define CONFIG_SYS_NS16550_CLK 40000000 -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#define CONFIG_SYS_NS16550_COM1 0xb0000c00 +#define CFG_SYS_NS16550_CLK 40000000 +#define CFG_SYS_NS16550_COM1 0xb0000c00 #endif /* Serial common */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ +#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ 230400, 460800, 921600 } /* SPL */ -#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE /* Dummy value */ -#define CONFIG_SYS_UBOOT_BASE 0 +#define CFG_SYS_UBOOT_BASE 0 #endif /* __CONFIG_MT7628_H */ diff --git a/include/configs/mt7629.h b/include/configs/mt7629.h index 668dc3c4f74..bfa44aacc72 100644 --- a/include/configs/mt7629.h +++ b/include/configs/mt7629.h @@ -18,14 +18,14 @@ /* Defines for SPL */ #define CONFIG_SPI_ADDR 0x30000000 -#define CONFIG_SYS_UBOOT_BASE (CONFIG_SPI_ADDR + CONFIG_SPL_PAD_TO) +#define CFG_SYS_UBOOT_BASE (CONFIG_SPI_ADDR + CONFIG_SPL_PAD_TO) /* SPL -> Uboot */ /* UBoot -> Kernel */ /* DRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 /* Ethernet */ #define CONFIG_IPADDR 192.168.1.1 diff --git a/include/configs/mt7981.h b/include/configs/mt7981.h index 9f26b0ba7bb..14c885ec55c 100644 --- a/include/configs/mt7981.h +++ b/include/configs/mt7981.h @@ -10,12 +10,12 @@ #define __MT7981_H /* Uboot definition */ -#define CONFIG_SYS_UBOOT_BASE CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE /* SPL -> Uboot */ -#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE /* DRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #endif diff --git a/include/configs/mt7986.h b/include/configs/mt7986.h index 4fbd57a573d..0c41af1fc32 100644 --- a/include/configs/mt7986.h +++ b/include/configs/mt7986.h @@ -10,12 +10,12 @@ #define __MT7986_H /* Uboot definition */ -#define CONFIG_SYS_UBOOT_BASE CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE /* SPL -> Uboot */ -#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE /* DRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #endif diff --git a/include/configs/mt8183.h b/include/configs/mt8183.h index c93d70ddf1a..3da7619d78d 100644 --- a/include/configs/mt8183.h +++ b/include/configs/mt8183.h @@ -12,11 +12,8 @@ #include <linux/sizes.h> -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#define CONFIG_SYS_NS16550_MEM32 -#define CONFIG_SYS_NS16550_COM1 0x11005200 -#define CONFIG_SYS_NS16550_CLK 26000000 +#define CFG_SYS_NS16550_COM1 0x11005200 +#define CFG_SYS_NS16550_CLK 26000000 /* Environment settings */ #include <config_distro_bootcmd.h> diff --git a/include/configs/mt8512.h b/include/configs/mt8512.h index d15941660ab..3a35527da10 100644 --- a/include/configs/mt8512.h +++ b/include/configs/mt8512.h @@ -10,7 +10,7 @@ #define __MT8512_H /* Uboot definition */ -#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE #define ENV_BOOT_READ_IMAGE \ "boot_rd_img=mmc dev 0" \ diff --git a/include/configs/mt8516.h b/include/configs/mt8516.h index 7228f3e4288..0f7981a5661 100644 --- a/include/configs/mt8516.h +++ b/include/configs/mt8516.h @@ -12,11 +12,8 @@ #include <linux/sizes.h> -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#define CONFIG_SYS_NS16550_MEM32 -#define CONFIG_SYS_NS16550_COM1 0x11005000 -#define CONFIG_SYS_NS16550_CLK 26000000 +#define CFG_SYS_NS16550_COM1 0x11005000 +#define CFG_SYS_NS16550_CLK 26000000 /* Environment settings */ #include <config_distro_bootcmd.h> diff --git a/include/configs/mt8518.h b/include/configs/mt8518.h index 7cabbef9288..8a8bc85ca70 100644 --- a/include/configs/mt8518.h +++ b/include/configs/mt8518.h @@ -10,8 +10,8 @@ #define __MT8518_H /* DRAM definition */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_SDRAM_SIZE 0x20000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_SIZE 0x20000000 /* Uboot definition */ diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h index 6d4fff3820c..fa275d61d18 100644 --- a/include/configs/mv-common.h +++ b/include/configs/mv-common.h @@ -27,20 +27,18 @@ */ /* additions for new ARM relocation support */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 /* * NS16550 Configuration */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK +#define CFG_SYS_NS16550_CLK CFG_SYS_TCLK #if !defined(CONFIG_DM_SERIAL) -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE +#define CFG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE #endif -#if defined(CONFIG_ARMADA_38X) && !defined(CONFIG_SYS_BAUDRATE_TABLE) -#define CONFIG_SYS_BAUDRATE_TABLE { 300, 600, 1200, 1800, 2400, 4800, \ +#if defined(CONFIG_ARMADA_38X) && !defined(CFG_SYS_BAUDRATE_TABLE) +#define CFG_SYS_BAUDRATE_TABLE { 300, 600, 1200, 1800, 2400, 4800, \ 9600, 19200, 38400, 57600, 115200, \ 230400, 460800, 500000, 576000, \ 921600, 1000000, 1152000, 1500000, \ diff --git a/include/configs/mvebu_alleycat-5.h b/include/configs/mvebu_alleycat-5.h index 41bdfae6c31..5c9620371e3 100644 --- a/include/configs/mvebu_alleycat-5.h +++ b/include/configs/mvebu_alleycat-5.h @@ -9,9 +9,9 @@ #include <asm/arch/soc.h> /* additions for new ARM relocation support */ -#define CONFIG_SYS_SDRAM_BASE 0x200000000 +#define CFG_SYS_SDRAM_BASE 0x200000000 -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ +#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ 115200, 230400, 460800, 921600 } /* Default Env vars */ @@ -37,6 +37,6 @@ /* * High Level Configuration Options (easy to change) */ -#define CONFIG_SYS_TCLK 325000000 +#define CFG_SYS_TCLK 325000000 #endif /* _CONFIG_MVEBU_ALLEYCAY_5_H */ diff --git a/include/configs/mvebu_armada-37xx.h b/include/configs/mvebu_armada-37xx.h index 6d3cb99b2df..9bfc48c52d9 100644 --- a/include/configs/mvebu_armada-37xx.h +++ b/include/configs/mvebu_armada-37xx.h @@ -13,9 +13,9 @@ */ /* additions for new ARM relocation support */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_BAUDRATE_TABLE { 300, 600, 1200, 1800, 2400, 4800, \ +#define CFG_SYS_BAUDRATE_TABLE { 300, 600, 1200, 1800, 2400, 4800, \ 9600, 19200, 38400, 57600, 115200, \ 230400, 460800, 500000, 576000, \ 921600, 1000000, 1152000, 1500000, \ diff --git a/include/configs/mvebu_armada-8k.h b/include/configs/mvebu_armada-8k.h index 5debd9117c6..beac3ae6496 100644 --- a/include/configs/mvebu_armada-8k.h +++ b/include/configs/mvebu_armada-8k.h @@ -9,14 +9,14 @@ /* * High Level Configuration Options (easy to change) */ -#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ +#define CFG_SYS_TCLK 250000000 /* 250MHz */ /* additions for new ARM relocation support */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 /* auto boot */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ +#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ 115200, 230400, 460800, 921600 } /* diff --git a/include/configs/mx23_olinuxino.h b/include/configs/mx23_olinuxino.h index dd303a17d61..aa3d7a1a3fc 100644 --- a/include/configs/mx23_olinuxino.h +++ b/include/configs/mx23_olinuxino.h @@ -10,7 +10,7 @@ /* Memory configuration */ #define PHYS_SDRAM_1 0x40000000 /* Base address */ #define PHYS_SDRAM_1_SIZE 0x08000000 /* Max 128 MB RAM */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 /* Status LED */ diff --git a/include/configs/mx23evk.h b/include/configs/mx23evk.h index 4c0531212ed..f597cdb3056 100644 --- a/include/configs/mx23evk.h +++ b/include/configs/mx23evk.h @@ -13,7 +13,7 @@ /* Memory configuration */ #define PHYS_SDRAM_1 0x40000000 /* Base address */ #define PHYS_SDRAM_1_SIZE 0x08000000 /* Max 128 MB RAM */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 /* Extra Environments */ #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index 140f5e98c52..c740d853327 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -13,15 +13,10 @@ /* Memory configuration */ #define PHYS_SDRAM_1 0x40000000 /* Base address */ #define PHYS_SDRAM_1_SIZE 0x40000000 /* Max 1 GB RAM */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 /* UBI and NAND partitioning */ -/* RTC */ -#ifdef CONFIG_CMD_DATE -#define CONFIG_RTC_MXS -#endif - /* Extra Environment */ #define CONFIG_EXTRA_ENV_SETTINGS \ "ubifs_file=filesystem.ubifs\0" \ diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index 95afb350ec3..ddd37b3936f 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -17,19 +17,15 @@ /* * Hardware drivers */ -#define CONFIG_FSL_IIM #define CONFIG_MXC_UART_BASE UART1_BASE /* PMIC Controller */ -#define CONFIG_POWER_SPI -#define CONFIG_POWER_FSL #define CONFIG_FSL_PMIC_BUS 0 #define CONFIG_FSL_PMIC_CS 0 #define CONFIG_FSL_PMIC_CLK 2500000 #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) #define CONFIG_FSL_PMIC_BITLEN 32 -#define CONFIG_RTC_MC13XXX /* * MMC Configs @@ -112,13 +108,13 @@ #define PHYS_SDRAM_1 CSD0_BASE_ADDR #define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) -#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) -#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) -#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) +#define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1) +#define CFG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) +#define CFG_SYS_INIT_RAM_SIZE (IRAM_SIZE) -#define CONFIG_SYS_DDR_CLKSEL 0 -#define CONFIG_SYS_CLKTL_CBCDR 0x59E35100 -#define CONFIG_SYS_MAIN_PWR_ON +#define CFG_SYS_DDR_CLKSEL 0 +#define CFG_SYS_CLKTL_CBCDR 0x59E35100 +#define CFG_SYS_MAIN_PWR_ON /*----------------------------------------------------------------------- * environment organization diff --git a/include/configs/mx53cx9020.h b/include/configs/mx53cx9020.h index 77835639720..cd806cb698e 100644 --- a/include/configs/mx53cx9020.h +++ b/include/configs/mx53cx9020.h @@ -60,13 +60,10 @@ #define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) #define PHYS_SDRAM_SIZE (gd->ram_size) -#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) -#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) -#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) +#define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1) +#define CFG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) +#define CFG_SYS_INIT_RAM_SIZE (IRAM_SIZE) /* environment organization */ -/* Framebuffer and LCD */ -#define CONFIG_IMX_VIDEO_SKIP - #endif /* __CONFIG_H */ diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index 3c9b2ad58ee..d0107fcc8cb 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -22,9 +22,7 @@ #define CONFIG_MXC_USB_FLAGS 0 /* PMIC Controller */ -#define CONFIG_POWER_FSL -#define CONFIG_POWER_FSL_MC13892 -#define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR 0x48 +#define CFG_SYS_DIALOG_PMIC_I2C_ADDR 0x48 #define CFG_SYS_FSL_PMIC_I2C_ADDR 0x8 /* Command definition */ @@ -95,9 +93,9 @@ #define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) #define PHYS_SDRAM_SIZE (gd->ram_size) -#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) -#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) -#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) +#define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1) +#define CFG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) +#define CFG_SYS_INIT_RAM_SIZE (IRAM_SIZE) /* Framebuffer and LCD */ diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h index b26613a2ea8..9464d6e44ae 100644 --- a/include/configs/mx53ppd.h +++ b/include/configs/mx53ppd.h @@ -87,7 +87,7 @@ /* Miscellaneous configurable options */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */ +#define CFG_SYS_BOOTMAPSZ (256 << 20) /* 256M */ /* Physical Memory Map */ #define PHYS_SDRAM_1 CSD0_BASE_ADDR @@ -96,17 +96,10 @@ #define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) #define PHYS_SDRAM_SIZE (gd->ram_size) -#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) -#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) -#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) +#define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1) +#define CFG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) +#define CFG_SYS_INIT_RAM_SIZE (IRAM_SIZE) /* FLASH and environment organization */ -#define CONFIG_FSL_IIM - -/* Backlight Control */ -#define CONFIG_IMX6_PWM_PER_CLK 66666000 - -#define CONFIG_IMX_VIDEO_SKIP - #endif /* __CONFIG_H */ diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index 43145567544..245530aa640 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -12,7 +12,7 @@ #define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */ #else #ifndef CONFIG_SYS_L2CACHE_OFF -#define CONFIG_SYS_PL310_BASE L2_PL310_BASE +#define CFG_SYS_PL310_BASE L2_PL310_BASE #endif #endif diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h index bc90b9563ad..f7f209c20b5 100644 --- a/include/configs/mx6cuboxi.h +++ b/include/configs/mx6cuboxi.h @@ -11,15 +11,9 @@ #include "mx6_common.h" -#include "imx6_spl.h" - /* MMC Configs */ #define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR -/* Framebuffer */ -#define CONFIG_IMX_HDMI -#define CONFIG_IMX_VIDEO_SKIP - /* USB */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) @@ -87,9 +81,9 @@ #include <config_distro_bootcmd.h> /* Physical Memory Map */ -#define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* Environment organization */ diff --git a/include/configs/mx6memcal.h b/include/configs/mx6memcal.h index ad53f17d671..f6d3b2eeb9c 100644 --- a/include/configs/mx6memcal.h +++ b/include/configs/mx6memcal.h @@ -11,7 +11,6 @@ /* SPL */ #include "mx6_common.h" -#include "imx6_spl.h" #ifdef CONFIG_SERIAL_CONSOLE_UART1 #if defined(CONFIG_MX6SL) @@ -28,9 +27,9 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE #define CONFIG_MXC_USB_PORTSC PORT_PTS_UTMI diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index bc9fab12909..6294fd1e2c4 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -139,16 +139,12 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* Environment organization */ -/* Framebuffer */ -#define CONFIG_IMX_HDMI -#define CONFIG_IMX_VIDEO_SKIP - #define CONFIG_USBD_HS #endif /* __MX6QSABRE_COMMON_CONFIG_H */ diff --git a/include/configs/mx6sabreauto.h b/include/configs/mx6sabreauto.h index 61570b7af53..888da7ce365 100644 --- a/include/configs/mx6sabreauto.h +++ b/include/configs/mx6sabreauto.h @@ -8,10 +8,6 @@ #ifndef __MX6SABREAUTO_CONFIG_H #define __MX6SABREAUTO_CONFIG_H -#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - #define CONFIG_MXC_UART_BASE UART4_BASE #define CONSOLE_DEV "ttymxc3" @@ -19,8 +15,7 @@ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_PCA953X -#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} } +#define CFG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} } #include "mx6sabre_common.h" @@ -30,18 +25,17 @@ #endif #ifdef CONFIG_MTD_NOR_FLASH -#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR +#define CFG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR #endif #define CFG_SYS_FSL_USDHC_NUM 2 /* NAND stuff */ -#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CFG_SYS_NAND_BASE 0x40000000 /* DMA stuff, needed for GPMI/MXS NAND support */ /* PMIC */ -#define CONFIG_POWER_PFUZE100 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 #endif /* __MX6SABREAUTO_CONFIG_H */ diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h index 49cd1512dc5..78a554d0ccb 100644 --- a/include/configs/mx6sabresd.h +++ b/include/configs/mx6sabresd.h @@ -8,10 +8,6 @@ #ifndef __MX6SABRESD_CONFIG_H #define __MX6SABRESD_CONFIG_H -#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - #define CONFIG_MXC_UART_BASE UART1_BASE #define CONSOLE_DEV "ttymxc0" @@ -29,7 +25,6 @@ #endif /* PMIC */ -#define CONFIG_POWER_PFUZE100 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 /* USB Configs */ diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index 26b97bd3f2e..358d9f47c0f 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -10,10 +10,6 @@ #include "mx6_common.h" -#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - #define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR /* MMC Configs */ @@ -86,9 +82,9 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* Environment organization */ diff --git a/include/configs/mx6sllevk.h b/include/configs/mx6sllevk.h index 44a5eeff198..8731f6a3e4a 100644 --- a/include/configs/mx6sllevk.h +++ b/include/configs/mx6sllevk.h @@ -82,9 +82,9 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define PHYS_SDRAM_SIZE SZ_2G -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* Environment organization */ @@ -92,8 +92,6 @@ #define CFG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR #define CFG_SYS_FSL_USDHC_NUM 3 -#define CONFIG_IOMUX_LPSR - /* USB Configs */ #ifdef CONFIG_CMD_USB #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h index 0d9764e3b4c..0dd40563c29 100644 --- a/include/configs/mx6sxsabreauto.h +++ b/include/configs/mx6sxsabreauto.h @@ -78,15 +78,15 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* MMC Configuration */ #define CFG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR /* NAND stuff */ -#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CFG_SYS_NAND_BASE 0x40000000 /* DMA stuff, needed for GPMI/MXS NAND support */ diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index 83779f09bfc..6f5dffe4fbb 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -12,10 +12,6 @@ #include "mx6_common.h" -#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - #define CONFIG_MXC_UART_BASE UART1_BASE #ifdef CONFIG_IMX_BOOTAUX @@ -110,9 +106,9 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* MMC Configuration */ #define CFG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index d0e3d3f0284..cb1019bd56a 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -15,9 +15,6 @@ #define is_mx6ul_9x9_evk() CONFIG_IS_ENABLED(TARGET_MX6UL_9X9_EVK) -/* SPL options */ -#include "imx6_spl.h" - #define CONFIG_MXC_UART_BASE UART1_BASE /* MMC Configs */ @@ -111,9 +108,9 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* environment organization */ diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h index 604923ec2b7..0e986093f35 100644 --- a/include/configs/mx6ullevk.h +++ b/include/configs/mx6ullevk.h @@ -102,14 +102,12 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* environment organization */ -#define CONFIG_IOMUX_LPSR - #ifdef CONFIG_CMD_NET #define CONFIG_FEC_ENET_DEV 1 #endif diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h index 4704276a74d..d5af6990107 100644 --- a/include/configs/mx7_common.h +++ b/include/configs/mx7_common.h @@ -17,9 +17,6 @@ #define CONFIG_MXC_GPT_HCLK #define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */ -/* Enable iomux-lpsr support */ -#define CONFIG_IOMUX_LPSR - /* Miscellaneous configurable options */ /* UART */ diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index 2a97d2fac46..6c165521f7a 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -81,9 +81,9 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* environment organization */ @@ -93,7 +93,7 @@ */ #ifdef CONFIG_NAND_MXS /* NAND stuff */ -#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CFG_SYS_NAND_BASE 0x40000000 /* DMA stuff, needed for GPMI/MXS NAND support */ #endif diff --git a/include/configs/mx7ulp_com.h b/include/configs/mx7ulp_com.h index 62e8e629911..85922fa436c 100644 --- a/include/configs/mx7ulp_com.h +++ b/include/configs/mx7ulp_com.h @@ -18,7 +18,7 @@ /* Using ULP WDOG for reset */ #define WDOG_BASE_ADDR WDG1_RBASE -#define CONFIG_SYS_HZ_CLOCK 1000000 /* Fixed at 1MHz from TSTMR */ +#define CFG_SYS_HZ_CLOCK 1000000 /* Fixed at 1MHz from TSTMR */ /* UART */ #define LPUART_BASE LPUART4_RBASE @@ -26,7 +26,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM 0x60000000 -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_EXTRA_ENV_SETTINGS \ "image=zImage\0" \ @@ -48,8 +48,8 @@ "bootz ${loadaddr} - ${fdt_addr}; " \ "fi;\0" \ -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE SZ_256K +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE SZ_256K #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #endif /* __CONFIG_H */ diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h index e93824928b3..99e01896c71 100644 --- a/include/configs/mx7ulp_evk.h +++ b/include/configs/mx7ulp_evk.h @@ -15,7 +15,7 @@ /* Using ULP WDOG for reset */ #define WDOG_BASE_ADDR WDG1_RBASE -#define CONFIG_SYS_HZ_CLOCK 1000000 /* Fixed at 1Mhz from TSTMR */ +#define CFG_SYS_HZ_CLOCK 1000000 /* Fixed at 1Mhz from TSTMR */ /* UART */ #define LPUART_BASE LPUART4_RBASE @@ -26,7 +26,7 @@ #define PHYS_SDRAM 0x60000000 #define PHYS_SDRAM_SIZE SZ_1G -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ @@ -92,7 +92,7 @@ "bootz; " \ "fi;\0" \ -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE SZ_256K +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE SZ_256K #endif /* __CONFIG_H */ diff --git a/include/configs/mxs.h b/include/configs/mxs.h index e8610386f04..30f27e7f0c1 100644 --- a/include/configs/mxs.h +++ b/include/configs/mxs.h @@ -46,11 +46,11 @@ /* Memory sizes */ /* OCRAM at 0x0 ; 32kB on MX23 ; 128kB on MX28 */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x00000000 +#define CFG_SYS_INIT_RAM_ADDR 0x00000000 #if defined(CONFIG_MX23) -#define CONFIG_SYS_INIT_RAM_SIZE (32 * 1024) +#define CFG_SYS_INIT_RAM_SIZE (32 * 1024) #elif defined(CONFIG_MX28) -#define CONFIG_SYS_INIT_RAM_SIZE (128 * 1024) +#define CFG_SYS_INIT_RAM_SIZE (128 * 1024) #endif /* Point initial SP in SRAM so SPL can use it too. */ @@ -83,12 +83,7 @@ /* NAND */ #ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_NAND_BASE 0x60000000 -#endif - -/* OCOTP */ -#ifdef CONFIG_CMD_FUSE -#define CONFIG_MXS_OCOTP +#define CFG_SYS_NAND_BASE 0x60000000 #endif /* SPI */ diff --git a/include/configs/mys_6ulx.h b/include/configs/mys_6ulx.h index a777305ec76..a32fcd57f8f 100644 --- a/include/configs/mys_6ulx.h +++ b/include/configs/mys_6ulx.h @@ -10,9 +10,6 @@ #include <linux/sizes.h> #include "mx6_common.h" -/* SPL options */ -#include "imx6_spl.h" - #define CFG_SYS_FSL_USDHC_NUM 1 /* Console configs */ @@ -25,12 +22,12 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define PHYS_SDRAM_SIZE SZ_256M -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* NAND */ -#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CFG_SYS_NAND_BASE 0x40000000 /* USB Configs */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index ec5339d930a..5020b3bb71d 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -26,10 +26,6 @@ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -/* Framebuffer and LCD */ -#define CONFIG_IMX_HDMI -#define CONFIG_IMX_VIDEO_SKIP - #ifdef CONFIG_CMD_MMC #define DISTRO_BOOT_DEV_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1) #else @@ -90,9 +86,9 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* Environment organization */ diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index 99a020c3c71..caaa9ed86b3 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -40,24 +40,14 @@ */ #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK +#define CFG_SYS_NS16550_CLK V_NS16550_CLK /* * select serial console configuration */ -#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 +#define CFG_SYS_NS16550_COM3 OMAP34XX_UART3 -#define CONFIG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, 115200 } - -/* USB device configuration */ -#define CONFIG_USB_DEVICE -#define CONFIG_USB_TTY -#define CONFIG_USBD_VENDORID 0x0421 -#define CONFIG_USBD_PRODUCTID_CDCACM 0x01c8 -#define CONFIG_USBD_PRODUCTID_GSERIAL 0x01c8 -#define CONFIG_USBD_MANUFACTURER "Nokia" -#define CONFIG_USBD_PRODUCT_NAME "N900 (U-Boot)" +#define CFG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, 115200 } #define GPIO_SLIDE 71 @@ -65,7 +55,7 @@ * Board ONENAND Info. */ -#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP +#define CFG_SYS_ONENAND_BASE ONENAND_MAP /* Environment information */ #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -151,7 +141,7 @@ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). * This rate is divided by a local divisor. */ -#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) +#define CFG_SYS_TIMERBASE (OMAP34XX_GPT2) /* * Physical Memory Map @@ -162,16 +152,16 @@ * FLASH and environment organization */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 -#define CONFIG_SYS_INIT_RAM_SIZE 0x800 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_INIT_RAM_ADDR 0x4020f800 +#define CFG_SYS_INIT_RAM_SIZE 0x800 /* * Attached kernel image */ #define SDRAM_SIZE 0x10000000 /* 256 MB */ -#define SDRAM_END (CONFIG_SYS_SDRAM_BASE + SDRAM_SIZE) +#define SDRAM_END (CFG_SYS_SDRAM_BASE + SDRAM_SIZE) #define IMAGE_MAXSIZE 0x1FF800 /* 2 MB - 2 kB */ #define KERNEL_OFFSET 0x40000 /* 256 kB */ diff --git a/include/configs/novena.h b/include/configs/novena.h index f2a04ca6185..4e46dfc526c 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -30,12 +30,9 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -/* SPL */ -#include "imx6_spl.h" /* common IMX6 SPL configuration */ +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* I2C */ #define CONFIG_I2C_MULTI_BUS @@ -53,7 +50,6 @@ #endif /* PMIC */ -#define CONFIG_POWER_PFUZE100 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 /* UART */ @@ -67,10 +63,6 @@ #define CONFIG_USBD_HS #endif -/* Video output */ -#define CONFIG_IMX_HDMI -#define CONFIG_IMX_VIDEO_SKIP - /* Extra U-Boot environment. */ #define CONFIG_EXTRA_ENV_SETTINGS \ "fdt_high=0xffffffff\0" \ diff --git a/include/configs/npi_imx6ull.h b/include/configs/npi_imx6ull.h index ccc203f5f24..09c4ddb6646 100644 --- a/include/configs/npi_imx6ull.h +++ b/include/configs/npi_imx6ull.h @@ -10,9 +10,6 @@ #include <linux/sizes.h> #include "mx6_common.h" -/* SPL options */ -#include "imx6_spl.h" - #define CFG_SYS_FSL_USDHC_NUM 1 /* Console configs */ @@ -26,12 +23,12 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* NAND */ -#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CFG_SYS_NAND_BASE 0x40000000 /* USB Configs */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) diff --git a/include/configs/nsim.h b/include/configs/nsim.h index d469ef83c24..013a3491a39 100644 --- a/include/configs/nsim.h +++ b/include/configs/nsim.h @@ -12,9 +12,9 @@ * Memory configuration */ -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SDRAM_SIZE SZ_256M +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_SIZE SZ_256M /* * Console configuration diff --git a/include/configs/nyan-big.h b/include/configs/nyan-big.h index c59e1032439..baa452156ec 100644 --- a/include/configs/nyan-big.h +++ b/include/configs/nyan-big.h @@ -16,7 +16,7 @@ /* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTA -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE /* SPI */ #define CONFIG_SPI_FLASH_SIZE (4 << 20) diff --git a/include/configs/o4-imx6ull-nano.h b/include/configs/o4-imx6ull-nano.h index 00f7d871271..ea1edab9fc1 100644 --- a/include/configs/o4-imx6ull-nano.h +++ b/include/configs/o4-imx6ull-nano.h @@ -7,9 +7,9 @@ #include "mx6_common.h" #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE #if IS_ENABLED(CONFIG_CMD_USB) # define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) diff --git a/include/configs/octeon_common.h b/include/configs/octeon_common.h index 0fa7490e7de..c0ea9e852dc 100644 --- a/include/configs/octeon_common.h +++ b/include/configs/octeon_common.h @@ -8,12 +8,12 @@ #define __OCTEON_COMMON_H__ #if defined(CONFIG_RAM_OCTEON) -#define CONFIG_SYS_INIT_SP_OFFSET 0x20180000 +#define CFG_SYS_INIT_SP_OFFSET 0x20180000 #else /* No DDR init -> run in L2 cache with limited resources */ -#define CONFIG_SYS_INIT_SP_OFFSET 0x00180000 +#define CFG_SYS_INIT_SP_OFFSET 0x00180000 #endif -#define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000 +#define CFG_SYS_SDRAM_BASE 0xffffffff80000000 #endif /* __OCTEON_COMMON_H__ */ diff --git a/include/configs/octeontx2_common.h b/include/configs/octeontx2_common.h index ab1eb787e70..03d1a8e7b5f 100644 --- a/include/configs/octeontx2_common.h +++ b/include/configs/octeontx2_common.h @@ -10,7 +10,7 @@ /** Maximum size of image supported for bootm (and bootable FIT images) */ /** Memory base address */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_TEXT_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_TEXT_BASE /** Stack starting address */ diff --git a/include/configs/octeontx_common.h b/include/configs/octeontx_common.h index 38f99ab2167..58275ccffa0 100644 --- a/include/configs/octeontx_common.h +++ b/include/configs/octeontx_common.h @@ -36,7 +36,7 @@ /** Maximum size of image supported for bootm (and bootable FIT images) */ /** Memory base address */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_TEXT_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_TEXT_BASE /** Stack starting address */ diff --git a/include/configs/odroid.h b/include/configs/odroid.h index babd3ca9631..f252b349437 100644 --- a/include/configs/odroid.h +++ b/include/configs/odroid.h @@ -14,12 +14,12 @@ #include <configs/exynos4-common.h> #ifndef CONFIG_SYS_L2CACHE_OFF -#define CONFIG_SYS_PL310_BASE 0x10502000 +#define CFG_SYS_PL310_BASE 0x10502000 #endif -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE #include <linux/sizes.h> @@ -143,10 +143,4 @@ "kernel_addr_r=0x41000000\0" \ BOOTENV -/* - * Supported Odroid boards: X3, U3 - * TODO: Add Odroid X support - */ -#define CONFIG_MISC_COMMON - #endif /* __CONFIG_H */ diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h index 15646297423..5bbe7aadcb2 100644 --- a/include/configs/odroid_xu3.h +++ b/include/configs/odroid_xu3.h @@ -10,7 +10,7 @@ #include <configs/exynos5420-common.h> #include <configs/exynos5-common.h> -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define TZPC_BASE_OFFSET 0x10000 @@ -57,7 +57,6 @@ "params.bin raw 0x1880 0x20\0" /* Enable: board/samsung/common/misc.c to use set_dfu_alt_info() */ -#define CONFIG_MISC_COMMON #define CONFIG_SET_DFU_ALT_BUF_LEN (SZ_1K) /* Set soc_rev, soc_id, board_rev, board_name, fdtfile */ diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index d46ca337d5f..f4e23bbb0f3 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -20,11 +20,11 @@ /* NAND */ #if defined(CONFIG_MTD_RAW_NAND) -#define CONFIG_SYS_FLASH_BASE NAND_BASE -#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ +#define CFG_SYS_FLASH_BASE NAND_BASE +#define CFG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ 10, 11, 12, 13} -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CFG_SYS_NAND_ECCSIZE 512 +#define CFG_SYS_NAND_ECCBYTES 3 /* NAND: SPL falcon mode configs */ #endif /* CONFIG_MTD_RAW_NAND */ diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index 77629d7fc1e..8bb8521f1c1 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -25,11 +25,11 @@ /* NAND */ #if defined(CONFIG_MTD_RAW_NAND) -#define CONFIG_SYS_FLASH_BASE NAND_BASE -#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ +#define CFG_SYS_FLASH_BASE NAND_BASE +#define CFG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ 10, 11, 12, 13} -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CFG_SYS_NAND_ECCSIZE 512 +#define CFG_SYS_NAND_ECCBYTES 3 #endif /* CONFIG_MTD_RAW_NAND */ #define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \ diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h index 97f47ea5b71..a6b5e55b541 100644 --- a/include/configs/omap3_igep00x0.h +++ b/include/configs/omap3_igep00x0.h @@ -66,18 +66,18 @@ BOOTENV /* OneNAND config */ -#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP -#define CONFIG_SYS_ONENAND_BLOCK_SIZE (128*1024) +#define CFG_SYS_ONENAND_BASE ONENAND_MAP +#define CFG_SYS_ONENAND_BLOCK_SIZE (128*1024) /* NAND config */ -#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ +#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 10, 11, 12, 13, 14, 15, 16, 17, \ 18, 19, 20, 21, 22, 23, 24, 25, \ 26, 27, 28, 29, 30, 31, 32, 33, \ 34, 35, 36, 37, 38, 39, 40, 41, \ 42, 43, 44, 45, 46, 47, 48, 49, \ 50, 51, 52, 53, 54, 55, 56, 57, } -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 14 +#define CFG_SYS_NAND_ECCSIZE 512 +#define CFG_SYS_NAND_ECCBYTES 14 #endif /* __IGEP00X0_H */ diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index 442a3cad220..38955377510 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -17,17 +17,15 @@ /* Board NAND Info. */ #ifdef CONFIG_MTD_RAW_NAND /* NAND devices */ -#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \ +#define CFG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \ 13, 14, 16, 17, 18, 19, 20, 21, 22, \ 23, 24, 25, 26, 27, 28, 30, 31, 32, \ 33, 34, 35, 36, 37, 38, 39, 40, 41, \ 42, 44, 45, 46, 47, 48, 49, 50, 51, \ 52, 53, 54, 55, 56} -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 13 -#define CONFIG_SYS_NAND_MAX_OOBFREE 2 -#define CONFIG_SYS_NAND_MAX_ECCPOS 56 +#define CFG_SYS_NAND_ECCSIZE 512 +#define CFG_SYS_NAND_ECCBYTES 13 #endif /* Environment information */ @@ -146,9 +144,9 @@ /* **** PISMO SUPPORT *** */ #if defined(CONFIG_CMD_NAND) -#define CONFIG_SYS_FLASH_BASE 0x10000000 +#define CFG_SYS_FLASH_BASE 0x10000000 #endif -#define CONFIG_SYS_FLASH_SIZE 0x4000000 +#define CFG_SYS_FLASH_SIZE 0x4000000 #endif /* __CONFIG_H */ diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h index cce5556fe26..d7fa2d43914 100644 --- a/include/configs/omap5_uevm.h +++ b/include/configs/omap5_uevm.h @@ -28,7 +28,7 @@ #include <configs/ti_omap5_common.h> -#define CONFIG_SYS_NS16550_COM3 UART3_BASE +#define CFG_SYS_NS16550_COM3 UART3_BASE /* MMC ENV related defines */ @@ -36,9 +36,8 @@ #define CONFIG_HSMMC2_8BIT /* Required support for the TCA642X GPIO we have on the uEVM */ -#define CONFIG_TCA642X -#define CONFIG_SYS_I2C_TCA642X_BUS_NUM 4 -#define CONFIG_SYS_I2C_TCA642X_ADDR 0x22 +#define CFG_SYS_I2C_TCA642X_BUS_NUM 4 +#define CFG_SYS_I2C_TCA642X_ADDR 0x22 /* Enabled commands */ diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h index 41039302415..788a1113868 100644 --- a/include/configs/omapl138_lcdk.h +++ b/include/configs/omapl138_lcdk.h @@ -17,9 +17,9 @@ /* * SoC Configuration */ -#define CONFIG_SYS_OSCIN_FREQ 24000000 -#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE -#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) +#define CFG_SYS_OSCIN_FREQ 24000000 +#define CFG_SYS_TIMERBASE DAVINCI_TIMER0_BASE +#define CFG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) /* * Memory Info @@ -32,7 +32,7 @@ /* memtest will be run on 16MB */ -#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ +#define CFG_SYS_DA850_SYSCFG_SUSPSRC ( \ DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ DAVINCI_SYSCFG_SUSPSRC_SPI1 | \ DAVINCI_SYSCFG_SUSPSRC_UART2 | \ @@ -44,17 +44,17 @@ */ /* Requires CONFIG_SYS_DA850_PLL0_POSTDIV=0, set in Kconfig */ -#define CONFIG_SYS_DA850_PLL0_PLLM 18 -#define CONFIG_SYS_DA850_PLL1_PLLM 21 +#define CFG_SYS_DA850_PLL0_PLLM 18 +#define CFG_SYS_DA850_PLL1_PLLM 21 /* * DDR2 memory configuration */ -#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ +#define CFG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ DV_DDR_PHY_EXT_STRBEN | \ (0x5 << DV_DDR_PHY_RD_LATENCY_SHIFT)) -#define CONFIG_SYS_DA850_DDR2_SDBCR ( \ +#define CFG_SYS_DA850_DDR2_SDBCR ( \ (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \ (1 << DV_DDR_SDCR_DDREN_SHIFT) | \ (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ @@ -64,9 +64,9 @@ (2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */ -#define CONFIG_SYS_DA850_DDR2_SDBCR2 0 +#define CFG_SYS_DA850_DDR2_SDBCR2 0 -#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \ +#define CFG_SYS_DA850_DDR2_SDTIMR ( \ (19 << DV_DDR_SDTMR1_RFC_SHIFT) | \ (1 << DV_DDR_SDTMR1_RP_SHIFT) | \ (1 << DV_DDR_SDTMR1_RCD_SHIFT) | \ @@ -76,7 +76,7 @@ (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ (1 << DV_DDR_SDTMR1_WTR_SHIFT)) -#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \ +#define CFG_SYS_DA850_DDR2_SDTIMR2 ( \ (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ (2 << DV_DDR_SDTMR2_XP_SHIFT) | \ (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ @@ -85,48 +85,41 @@ (1 << DV_DDR_SDTMR2_RTP_SHIFT) | \ (2 << DV_DDR_SDTMR2_CKE_SHIFT)) -#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000492 -#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30 +#define CFG_SYS_DA850_DDR2_SDRCR 0x00000492 +#define CFG_SYS_DA850_DDR2_PBBPR 0x30 /* * Serial Driver info */ -#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) +#define CFG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) -#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE -#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) +#define CFG_SYS_SPI_BASE DAVINCI_SPI1_BASE +#define CFG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) /* * I2C Configuration */ -#define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20 +#define CFG_SYS_I2C_EXPANDER_ADDR 0x20 /* * Flash & Environment */ #ifdef CONFIG_MTD_RAW_NAND -#define CONFIG_SYS_NAND_PAGE_2K -#define CONFIG_SYS_NAND_CS 3 -#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE -#define CONFIG_SYS_NAND_MASK_CLE 0x10 -#define CONFIG_SYS_NAND_MASK_ALE 0x8 -#undef CONFIG_SYS_NAND_HW_ECC -#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST +#define CFG_SYS_NAND_CS 3 +#define CFG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE +#define CFG_SYS_NAND_MASK_CLE 0x10 +#define CFG_SYS_NAND_MASK_ALE 0x8 #define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC -#define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K -#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000 -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST -#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \ - CONFIG_SYS_NAND_U_BOOT_SIZE - \ - CONFIG_SYS_MALLOC_LEN - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_NAND_ECCPOS { \ +#define CFG_SYS_NAND_U_BOOT_SIZE SZ_512K +#define CFG_SYS_NAND_U_BOOT_DST 0xc1080000 +#define CFG_SYS_NAND_U_BOOT_START CFG_SYS_NAND_U_BOOT_DST +#define CFG_SYS_NAND_ECCPOS { \ 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \ 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \ 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ 54, 55, 56, 57, 58, 59, 60, 61, 62, 63 } -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 10 +#define CFG_SYS_NAND_ECCSIZE 512 +#define CFG_SYS_NAND_ECCBYTES 10 #endif /* @@ -161,7 +154,7 @@ /* defines for SPL */ /* additions for new relocation code, must added to all boards */ -#define CONFIG_SYS_SDRAM_BASE 0xc0000000 +#define CFG_SYS_SDRAM_BASE 0xc0000000 #include <asm/arch/hardware.h> diff --git a/include/configs/openpiton-riscv64.h b/include/configs/openpiton-riscv64.h index 3ff8187b5df..5b097e9fef2 100644 --- a/include/configs/openpiton-riscv64.h +++ b/include/configs/openpiton-riscv64.h @@ -14,7 +14,7 @@ #include <linux/sizes.h> /* Environment options */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 /* --------------------------------------------------------------------- * Board boot configuration diff --git a/include/configs/opos6uldev.h b/include/configs/opos6uldev.h index 3e551e13aa6..e42a736136b 100644 --- a/include/configs/opos6uldev.h +++ b/include/configs/opos6uldev.h @@ -10,17 +10,13 @@ #include "mx6_common.h" -#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - /* Miscellaneous configurable options */ #define CONFIG_STANDALONE_LOAD_ADDR CONFIG_SYS_LOAD_ADDR /* Physical Memory Map */ -#define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* USB */ #ifdef CONFIG_USB_EHCI_MX6 diff --git a/include/configs/origen.h b/include/configs/origen.h index 36aaa7c14fb..6633d541a31 100644 --- a/include/configs/origen.h +++ b/include/configs/origen.h @@ -11,8 +11,8 @@ #include <configs/exynos4-common.h> /* ORIGEN has 4 bank of DRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ /* Power Down Modes */ diff --git a/include/configs/owl-common.h b/include/configs/owl-common.h index b0233b96b06..8d0311cfb3b 100644 --- a/include/configs/owl-common.h +++ b/include/configs/owl-common.h @@ -11,7 +11,7 @@ #define _OWL_COMMON_CONFIG_H_ /* SDRAM Definitions */ -#define CONFIG_SYS_SDRAM_BASE 0x0 +#define CFG_SYS_SDRAM_BASE 0x0 /* Some commands use this as the default load address */ diff --git a/include/configs/p1_p2_bootsrc.h b/include/configs/p1_p2_bootsrc.h index d155e553e20..c96deda61d7 100644 --- a/include/configs/p1_p2_bootsrc.h +++ b/include/configs/p1_p2_bootsrc.h @@ -7,11 +7,11 @@ #include <linux/stringify.h> -#if !defined(CONFIG_SYS_SPD_BUS_NUM) || !defined(CONFIG_SYS_I2C_PCA9557_ADDR) -#error "CONFIG_SYS_SPD_BUS_NUM and CONFIG_SYS_I2C_PCA9557_ADDR are required" +#if !defined(CONFIG_SYS_SPD_BUS_NUM) || !defined(CFG_SYS_I2C_PCA9557_ADDR) +#error "CONFIG_SYS_SPD_BUS_NUM and CFG_SYS_I2C_PCA9557_ADDR are required" #endif -#define __BOOTSRC_CMD(src, msk) i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 src 1; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 msk 1 +#define __BOOTSRC_CMD(src, msk) i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CFG_SYS_I2C_PCA9557_ADDR 1 src 1; i2c mw CFG_SYS_I2C_PCA9557_ADDR 3 msk 1 #define __VAR_CMD(var, cmd) __stringify(var=cmd\0) #define __VAR_CMD_RST(var, cmd) __VAR_CMD(var, cmd; reset) diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 778bf5112af..9738e9fa9cb 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -13,7 +13,6 @@ #include <linux/stringify.h> #if defined(CONFIG_TARGET_P1020RDB_PC) -#define CONFIG_VSC7385_ENET #define CONFIG_SLIC #define __SW_BOOT_MASK 0x03 #define __SW_BOOT_NOR 0x5c @@ -43,7 +42,6 @@ * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off */ #if defined(CONFIG_TARGET_P1020RDB_PD) -#define CONFIG_VSC7385_ENET #define CONFIG_SLIC #define __SW_BOOT_MASK 0x03 #define __SW_BOOT_NOR 0x64 @@ -63,7 +61,6 @@ #endif #if defined(CONFIG_TARGET_P2020RDB) -#define CONFIG_VSC7385_ENET #define __SW_BOOT_MASK 0x03 #define __SW_BOOT_NOR 0xc8 #define __SW_BOOT_SPI 0x28 @@ -83,28 +80,28 @@ #endif #ifdef CONFIG_SDCARD -#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_MMC_U_BOOT_DST CONFIG_TEXT_BASE -#define CONFIG_SYS_MMC_U_BOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10) +#define CFG_SYS_MMC_U_BOOT_DST CONFIG_TEXT_BASE +#define CFG_SYS_MMC_U_BOOT_START CONFIG_TEXT_BASE #ifdef CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR -#define CONFIG_SYS_MMC_U_BOOT_OFFS (CONFIG_SPL_PAD_TO - CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA*512) +#define CFG_SYS_MMC_U_BOOT_OFFS (CONFIG_SPL_PAD_TO - CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA*512) #else -#define CONFIG_SYS_MMC_U_BOOT_OFFS CONFIG_SPL_PAD_TO +#define CFG_SYS_MMC_U_BOOT_OFFS CONFIG_SPL_PAD_TO #endif #elif defined(CONFIG_SPIFLASH) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST CONFIG_TEXT_BASE -#define CONFIG_SYS_SPI_FLASH_U_BOOT_START CONFIG_TEXT_BASE -#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS CONFIG_SPL_PAD_TO +#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) +#define CFG_SYS_SPI_FLASH_U_BOOT_DST CONFIG_TEXT_BASE +#define CFG_SYS_SPI_FLASH_U_BOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_SPI_FLASH_U_BOOT_OFFS CONFIG_SPL_PAD_TO #elif defined(CONFIG_MTD_RAW_NAND) #ifdef CONFIG_TPL_BUILD -#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) -#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) +#define CFG_SYS_NAND_U_BOOT_SIZE (832 << 10) +#define CFG_SYS_NAND_U_BOOT_DST (0x11000000) +#define CFG_SYS_NAND_U_BOOT_START (0x11000000) #elif defined(CONFIG_SPL_BUILD) -#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 -#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 +#define CFG_SYS_NAND_U_BOOT_SIZE (128 << 10) +#define CFG_SYS_NAND_U_BOOT_DST 0xf8f80000 +#define CFG_SYS_NAND_U_BOOT_START 0xf8f80000 #endif /* not CONFIG_TPL_BUILD */ #endif @@ -112,58 +109,57 @@ #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc #endif -#define CONFIG_HWCONFIG /* * These can be toggled for performance analysis, otherwise use default. */ #define CONFIG_L2_CACHE -#define CONFIG_SYS_CCSRBAR 0xffe00000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR +#define CFG_SYS_CCSRBAR 0xffe00000 +#define CFG_SYS_CCSRBAR_PHYS_LOW CFG_SYS_CCSRBAR /* DDR Setup */ #define SPD_EEPROM_ADDRESS 0x52 #if defined(CONFIG_TARGET_P1020RDB_PD) -#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G +#define CFG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G #else -#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G +#define CFG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G #endif -#define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_SIZE (1u << (CFG_SYS_SDRAM_SIZE_LAW - 19)) +#define CFG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE /* Default settings for DDR3 */ #ifndef CONFIG_TARGET_P2020RDB -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 -#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 -#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f -#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 -#define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 - -#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 -#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 -#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 - -#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 -#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608 -#define CONFIG_SYS_DDR_SR_CNTR 0x00000000 -#define CONFIG_SYS_DDR_RCW_1 0x00000000 -#define CONFIG_SYS_DDR_RCW_2 0x00000000 -#define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ -#define CONFIG_SYS_DDR_CONTROL_2 0x04401050 -#define CONFIG_SYS_DDR_TIMING_4 0x00220001 -#define CONFIG_SYS_DDR_TIMING_5 0x03402400 - -#define CONFIG_SYS_DDR_TIMING_3 0x00020000 -#define CONFIG_SYS_DDR_TIMING_0 0x00330004 -#define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846 -#define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF -#define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 -#define CONFIG_SYS_DDR_MODE_1 0x40461520 -#define CONFIG_SYS_DDR_MODE_2 0x8000c000 -#define CONFIG_SYS_DDR_INTERVAL 0x0C300000 +#define CFG_SYS_DDR_CS0_BNDS 0x0000003f +#define CFG_SYS_DDR_CS0_CONFIG 0x80014302 +#define CFG_SYS_DDR_CS0_CONFIG_2 0x00000000 +#define CFG_SYS_DDR_CS1_BNDS 0x0040007f +#define CFG_SYS_DDR_CS1_CONFIG 0x80014302 +#define CFG_SYS_DDR_CS1_CONFIG_2 0x00000000 + +#define CFG_SYS_DDR_INIT_ADDR 0x00000000 +#define CFG_SYS_DDR_INIT_EXT_ADDR 0x00000000 +#define CFG_SYS_DDR_MODE_CONTROL 0x00000000 + +#define CFG_SYS_DDR_ZQ_CONTROL 0x89080600 +#define CFG_SYS_DDR_WRLVL_CONTROL 0x8655A608 +#define CFG_SYS_DDR_SR_CNTR 0x00000000 +#define CFG_SYS_DDR_RCW_1 0x00000000 +#define CFG_SYS_DDR_RCW_2 0x00000000 +#define CFG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ +#define CFG_SYS_DDR_CONTROL_2 0x04401050 +#define CFG_SYS_DDR_TIMING_4 0x00220001 +#define CFG_SYS_DDR_TIMING_5 0x03402400 + +#define CFG_SYS_DDR_TIMING_3 0x00020000 +#define CFG_SYS_DDR_TIMING_0 0x00330004 +#define CFG_SYS_DDR_TIMING_1 0x6f6B4846 +#define CFG_SYS_DDR_TIMING_2 0x0FA8C8CF +#define CFG_SYS_DDR_CLK_CTRL 0x03000000 +#define CFG_SYS_DDR_MODE_1 0x40461520 +#define CFG_SYS_DDR_MODE_2 0x8000c000 +#define CFG_SYS_DDR_INTERVAL 0x0C300000 #endif /* @@ -186,43 +182,43 @@ * Local Bus Definitions */ #if defined(CONFIG_TARGET_P1020RDB_PD) -#define CONFIG_SYS_FLASH_BASE 0xec000000 +#define CFG_SYS_FLASH_BASE 0xec000000 #else -#define CONFIG_SYS_FLASH_BASE 0xef000000 +#define CFG_SYS_FLASH_BASE 0xef000000 #endif #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) +#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE) #else -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE #endif -#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ +#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) \ | BR_PS_16 | BR_V) #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} +#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS} #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ /* Nand Flash */ #ifdef CONFIG_NAND_FSL_ELBC -#define CONFIG_SYS_NAND_BASE 0xff800000 +#define CFG_SYS_NAND_BASE 0xff800000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull +#define CFG_SYS_NAND_BASE_PHYS 0xfff800000ull #else -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE #endif -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } -#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ +#define CFG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ | BR_V) /* valid */ #if defined(CONFIG_TARGET_P1020RDB_PD) -#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \ +#define CFG_SYS_NAND_OR_PRELIM (OR_AM_32KB \ | OR_FCM_PGS /* Large Page*/ \ | OR_FCM_CSCT \ | OR_FCM_CST \ @@ -231,7 +227,7 @@ | OR_FCM_TRLX \ | OR_FCM_EHTR) #else -#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \ +#define CFG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \ | OR_FCM_CSCT \ | OR_FCM_CST \ | OR_FCM_CHT \ @@ -241,50 +237,44 @@ #endif #endif /* CONFIG_NAND_FSL_ELBC */ -#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ +#define CFG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR +#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR /* The assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#define CFG_SYS_INIT_RAM_ADDR_PHYS \ + ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CFG_SYS_INIT_RAM_ADDR_PHYS_LOW) #else /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS +#define CFG_SYS_INIT_RAM_ADDR_PHYS CFG_SYS_INIT_RAM_ADDR +#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 +#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR_PHYS #endif /* Size of used area in RAM */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 +#define CFG_SYS_INIT_RAM_SIZE 0x00004000 -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_CPLD_BASE 0xffa00000 +#define CFG_SYS_CPLD_BASE 0xffa00000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull +#define CFG_SYS_CPLD_BASE_PHYS 0xfffa00000ull #else -#define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE +#define CFG_SYS_CPLD_BASE_PHYS CFG_SYS_CPLD_BASE #endif /* CPLD config size: 1Mb */ /* Vsc7385 switch */ #ifdef CONFIG_VSC7385_ENET #define __VSCFW_ADDR "vscfw_addr=ef000000\0" -#define CONFIG_SYS_VSC7385_BASE 0xffb00000 +#define CFG_SYS_VSC7385_BASE 0xffb00000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull +#define CFG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull #else -#define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE +#define CFG_SYS_VSC7385_BASE_PHYS CFG_SYS_VSC7385_BASE #endif -#define CONFIG_SYS_VSC7385_BR_PRELIM \ - (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V) -#define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \ - OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \ - OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) - /* The size of the VSC7385 firmware image */ #define CONFIG_VSC7385_IMAGE_SIZE 8192 #endif @@ -298,18 +288,18 @@ */ #if defined(CONFIG_SPL_BUILD) #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) -#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 -#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) +#define CFG_SYS_INIT_L2_ADDR 0xf8f80000 +#define CFG_SYS_INIT_L2_ADDR_PHYS CFG_SYS_INIT_L2_ADDR +#define CFG_SYS_INIT_L2_END (CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) #elif defined(CONFIG_MTD_RAW_NAND) #ifdef CONFIG_TPL_BUILD -#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 -#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) +#define CFG_SYS_INIT_L2_ADDR 0xf8f80000 +#define CFG_SYS_INIT_L2_ADDR_PHYS CFG_SYS_INIT_L2_ADDR +#define CFG_SYS_INIT_L2_END (CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) #else -#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 -#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) +#define CFG_SYS_INIT_L2_ADDR 0xf8f80000 +#define CFG_SYS_INIT_L2_ADDR_PHYS CFG_SYS_INIT_L2_ADDR +#define CFG_SYS_INIT_L2_END (CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) #endif /* CONFIG_TPL_BUILD */ #endif #endif @@ -319,31 +309,25 @@ * shorted - index 1 */ #undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) -#if defined(CONFIG_SPL_BUILD) && CONFIG_IS_ENABLED(INIT_MINIMAL) -#define CONFIG_NS16550_MIN_FUNCTIONS -#endif +#define CFG_SYS_NS16550_CLK get_bus_freq(0) -#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) +#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x4500) +#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x4600) /* I2C */ #if !CONFIG_IS_ENABLED(DM_I2C) -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } +#define CFG_SYS_I2C_NOPROBES { {0, 0x29} } #endif /* * I2C2 EEPROM */ -#define CONFIG_RTC_PT7C4338 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 -#define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 +#define CFG_SYS_I2C_RTC_ADDR 0x68 +#define CFG_SYS_I2C_PCA9557_ADDR 0x18 /* enable read and write access to EEPROM */ @@ -354,31 +338,31 @@ */ /* controller 2, direct to uli, tgtid 2, Base address 9000 */ -#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#define CFG_SYS_PCIE2_MEM_VIRT 0xa0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#define CFG_SYS_PCIE2_MEM_PHYS 0xc20000000ull #else -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 +#define CFG_SYS_PCIE2_MEM_PHYS 0xa0000000 #endif -#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 +#define CFG_SYS_PCIE2_IO_VIRT 0xffc10000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull +#define CFG_SYS_PCIE2_IO_PHYS 0xfffc10000ull #else -#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 +#define CFG_SYS_PCIE2_IO_PHYS 0xffc10000 #endif /* controller 1, Slot 2, tgtid 1, Base address a000 */ -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull #else -#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 +#define CFG_SYS_PCIE1_MEM_PHYS 0x80000000 #endif -#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 +#define CFG_SYS_PCIE1_IO_VIRT 0xffc00000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull +#define CFG_SYS_PCIE1_IO_PHYS 0xfffc00000ull #else -#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 +#define CFG_SYS_PCIE1_IO_PHYS 0xffc00000 #endif #endif /* CONFIG_PCI */ @@ -408,7 +392,7 @@ */ #if defined(CONFIG_MTD_RAW_NAND) #ifdef CONFIG_TPL_BUILD -#define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) +#define SPL_ENV_ADDR (CFG_SYS_INIT_L2_ADDR + (160 << 10)) #endif #endif @@ -429,7 +413,7 @@ * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ +#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ /* * Environment Configuration diff --git a/include/configs/paz00.h b/include/configs/paz00.h index c12f4d0937d..a945f4e9b28 100644 --- a/include/configs/paz00.h +++ b/include/configs/paz00.h @@ -17,7 +17,7 @@ /* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTA -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE /* Environment in eMMC, at the end of 2nd "boot sector" */ diff --git a/include/configs/pcl063.h b/include/configs/pcl063.h index dea87122ebc..2a1660bf188 100644 --- a/include/configs/pcl063.h +++ b/include/configs/pcl063.h @@ -11,9 +11,6 @@ #include <linux/sizes.h> #include "mx6_common.h" -/* SPL options */ -#include "imx6_spl.h" - /* * There is a bug in some i.MX6UL processors that results in the initial * portion of OCRAM being unavailable when booting from (at least) an SD @@ -37,12 +34,12 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define PHYS_SDRAM_SIZE SZ_256M -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* NAND */ -#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CFG_SYS_NAND_BASE 0x40000000 /* USB Configs */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) diff --git a/include/configs/pcl063_ull.h b/include/configs/pcl063_ull.h index 2bdae8afa8c..4421e740d9e 100644 --- a/include/configs/pcl063_ull.h +++ b/include/configs/pcl063_ull.h @@ -13,9 +13,6 @@ #include <linux/stringify.h> #include "mx6_common.h" -/* SPL options */ -#include "imx6_spl.h" - #define CFG_SYS_FSL_USDHC_NUM 2 /* Environment settings */ @@ -39,12 +36,12 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define PHYS_SDRAM_SIZE SZ_256M -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* NAND */ -#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CFG_SYS_NAND_BASE 0x40000000 /* USB Configs */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h index a04a03a7e18..5c2ff5d02ee 100644 --- a/include/configs/pcm052.h +++ b/include/configs/pcm052.h @@ -118,9 +118,9 @@ #define PHYS_SDRAM (0x80000000) #define PHYS_SDRAM_SIZE (CONFIG_PCM052_DDR_SIZE * SZ_1M) -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* environment organization */ diff --git a/include/configs/pcm058.h b/include/configs/pcm058.h index 01190904cf6..3674e4cddae 100644 --- a/include/configs/pcm058.h +++ b/include/configs/pcm058.h @@ -6,10 +6,6 @@ #ifndef __PCM058_CONFIG_H #define __PCM058_CONFIG_H -#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - #include "mx6_common.h" #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) @@ -19,9 +15,9 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* Environment organization */ #define ENV_MMC \ diff --git a/include/configs/pdu001.h b/include/configs/pdu001.h index ed3201aa3c4..71807837673 100644 --- a/include/configs/pdu001.h +++ b/include/configs/pdu001.h @@ -50,11 +50,11 @@ "\0" /* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_COM1 UART0_BASE -#define CONFIG_SYS_NS16550_COM2 UART1_BASE -#define CONFIG_SYS_NS16550_COM3 UART2_BASE -#define CONFIG_SYS_NS16550_COM4 UART3_BASE -#define CONFIG_SYS_NS16550_COM5 UART4_BASE -#define CONFIG_SYS_NS16550_COM6 UART5_BASE +#define CFG_SYS_NS16550_COM1 UART0_BASE +#define CFG_SYS_NS16550_COM2 UART1_BASE +#define CFG_SYS_NS16550_COM3 UART2_BASE +#define CFG_SYS_NS16550_COM4 UART3_BASE +#define CFG_SYS_NS16550_COM5 UART4_BASE +#define CFG_SYS_NS16550_COM6 UART5_BASE #endif /* ! __CONFIG_PDU001_H */ diff --git a/include/configs/peach-pi.h b/include/configs/peach-pi.h index 7a8d3c63d44..fb6eb572cfa 100644 --- a/include/configs/peach-pi.h +++ b/include/configs/peach-pi.h @@ -20,9 +20,7 @@ #include <configs/exynos5-dt-common.h> #include <configs/exynos5-common.h> -#define CONFIG_SYS_SDRAM_BASE 0x20000000 - -#define CONFIG_POWER_TPS65090_EC +#define CFG_SYS_SDRAM_BASE 0x20000000 /* DRAM Memory Banks */ #define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h index 2c749ac2143..09c6b4f8dd5 100644 --- a/include/configs/peach-pit.h +++ b/include/configs/peach-pit.h @@ -20,7 +20,7 @@ #include <configs/exynos5-dt-common.h> #include <configs/exynos5-common.h> -#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_BASE 0x20000000 /* DRAM Memory Banks */ #define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ diff --git a/include/configs/pg-wcom-expu1.h b/include/configs/pg-wcom-expu1.h index e08d9414129..1b72739d143 100644 --- a/include/configs/pg-wcom-expu1.h +++ b/include/configs/pg-wcom-expu1.h @@ -13,23 +13,23 @@ #define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1" /* CLIPS FPGA Definitions */ -#define CONFIG_SYS_CSPR3_EXT (0x00) -#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CLIPS_BASE) | \ +#define CFG_SYS_CSPR3_EXT (0x00) +#define CFG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CLIPS_BASE) | \ CSPR_PORT_SIZE_8 | \ CSPR_MSEL_GPCM | \ CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) -#define CONFIG_SYS_CSOR3 (CSOR_GPCM_ADM_SHIFT(0x4) | \ +#define CFG_SYS_AMASK3 IFC_AMASK(64 * 1024) +#define CFG_SYS_CSOR3 (CSOR_GPCM_ADM_SHIFT(0x4) | \ CSOR_GPCM_TRHZ_40) -#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \ +#define CFG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \ FTIM0_GPCM_TEADC(0x7) | \ FTIM0_GPCM_TEAHC(0x2)) -#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x2) | \ +#define CFG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x2) | \ FTIM1_GPCM_TRAD(0x12)) -#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x3) | \ +#define CFG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x3) | \ FTIM2_GPCM_TCH(0x1) | \ FTIM2_GPCM_TWP(0x12)) -#define CONFIG_SYS_CS3_FTIM3 0x04000000 +#define CFG_SYS_CS3_FTIM3 0x04000000 /* PRST */ #define WCOM_CLIPS_RST 0 diff --git a/include/configs/pg-wcom-seli8.h b/include/configs/pg-wcom-seli8.h index 9a7669c940b..e4bcae5bb5e 100644 --- a/include/configs/pg-wcom-seli8.h +++ b/include/configs/pg-wcom-seli8.h @@ -12,23 +12,23 @@ #define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1" /* PAXK FPGA Definitions */ -#define CONFIG_SYS_CSPR3_EXT (0x00) -#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_PAX_BASE) | \ +#define CFG_SYS_CSPR3_EXT (0x00) +#define CFG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_PAX_BASE) | \ CSPR_PORT_SIZE_8 | \ CSPR_MSEL_GPCM | \ CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) -#define CONFIG_SYS_CSOR3 (CSOR_GPCM_ADM_SHIFT(0x4) | \ +#define CFG_SYS_AMASK3 IFC_AMASK(64 * 1024) +#define CFG_SYS_CSOR3 (CSOR_GPCM_ADM_SHIFT(0x4) | \ CSOR_GPCM_TRHZ_40) -#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \ +#define CFG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \ FTIM0_GPCM_TEADC(0x7) | \ FTIM0_GPCM_TEAHC(0x2)) -#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x2) | \ +#define CFG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x2) | \ FTIM1_GPCM_TRAD(0x12)) -#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x3) | \ +#define CFG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x3) | \ FTIM2_GPCM_TCH(0x1) | \ FTIM2_GPCM_TWP(0x12)) -#define CONFIG_SYS_CS3_FTIM3 0x04000000 +#define CFG_SYS_CS3_FTIM3 0x04000000 /* PRST */ #define KM_LIU_RST 0 diff --git a/include/configs/phycore_am335x_r2.h b/include/configs/phycore_am335x_r2.h index f69d8adb91c..f922491637d 100644 --- a/include/configs/phycore_am335x_r2.h +++ b/include/configs/phycore_am335x_r2.h @@ -79,12 +79,10 @@ #define V_OSCK 25000000 /* Clock output from T2 */ #define V_SCLK V_OSCK -#define CONFIG_POWER_TPS65910 - #ifdef CONFIG_MTD_RAW_NAND /* NAND: device related configs */ /* NAND: driver related configs */ -#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ +#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 10, 11, 12, 13, 14, 15, 16, 17, \ 18, 19, 20, 21, 22, 23, 24, 25, \ 26, 27, 28, 29, 30, 31, 32, 33, \ @@ -92,15 +90,9 @@ 42, 43, 44, 45, 46, 47, 48, 49, \ 50, 51, 52, 53, 54, 55, 56, 57, } -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 14 +#define CFG_SYS_NAND_ECCSIZE 512 +#define CFG_SYS_NAND_ECCBYTES 14 #endif /* !CONFIG_MTD_RAW_NAND */ -/* CPU */ - -#ifdef CONFIG_SPI_BOOT -#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 -#endif - #endif /* ! __CONFIG_PHYCORE_AM335x_R2_H */ diff --git a/include/configs/phycore_imx8mm.h b/include/configs/phycore_imx8mm.h index c98393b7c75..7f73117ac1c 100644 --- a/include/configs/phycore_imx8mm.h +++ b/include/configs/phycore_imx8mm.h @@ -11,7 +11,7 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h> -#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD @@ -60,11 +60,11 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE SZ_512K +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE SZ_512K -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */ diff --git a/include/configs/phycore_imx8mp.h b/include/configs/phycore_imx8mp.h index 49cd9d4b3c6..11a833bb127 100644 --- a/include/configs/phycore_imx8mp.h +++ b/include/configs/phycore_imx8mp.h @@ -10,7 +10,7 @@ #include <linux/sizes.h> #include <asm/arch/imx-regs.h> -#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD @@ -59,11 +59,11 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE SZ_512K +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE SZ_512K -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h index 4ea16d6115a..3cc2a693cee 100644 --- a/include/configs/pic32mzdask.h +++ b/include/configs/pic32mzdask.h @@ -18,12 +18,12 @@ * Memory Layout */ /* Initial RAM for temporary stack, global data */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 -#define CONFIG_SYS_INIT_RAM_ADDR \ - (CONFIG_SYS_SRAM_BASE + CONFIG_SYS_SRAM_SIZE - CONFIG_SYS_INIT_RAM_SIZE) +#define CFG_SYS_INIT_RAM_SIZE 0x10000 +#define CFG_SYS_INIT_RAM_ADDR \ + (CONFIG_SYS_SRAM_BASE + CONFIG_SYS_SRAM_SIZE - CFG_SYS_INIT_RAM_SIZE) /* SDRAM Configuration (for final code, data, stack, heap) */ -#define CONFIG_SYS_SDRAM_BASE 0x88000000 +#define CFG_SYS_SDRAM_BASE 0x88000000 /* Memory Test */ diff --git a/include/configs/pico-imx6.h b/include/configs/pico-imx6.h index 687133b9bdd..6d7873daa0a 100644 --- a/include/configs/pico-imx6.h +++ b/include/configs/pico-imx6.h @@ -10,14 +10,6 @@ #include "mx6_common.h" -#include "imx6_spl.h" - -#ifdef CONFIG_SPL_OS_BOOT -/* Falcon Mode */ - -/* Falcon Mode - MMC support: args@1MB kernel@2MB */ -#endif - #define CONFIG_MXC_UART_BASE UART1_BASE /* MMC Configuration */ @@ -99,17 +91,13 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* Environment organization */ /* Ethernet Configuration */ #define CONFIG_FEC_MXC_PHYADDR 1 -/* Framebuffer */ -#define CONFIG_IMX_HDMI -#define CONFIG_IMX_VIDEO_SKIP - #endif /* __CONFIG_H * */ diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h index d4f58b6a7b0..8af8883fad6 100644 --- a/include/configs/pico-imx6ul.h +++ b/include/configs/pico-imx6ul.h @@ -12,13 +12,6 @@ #include <linux/sizes.h> #include "mx6_common.h" #include <asm/mach-imx/gpio.h> -#include "imx6_spl.h" - -#ifdef CONFIG_SPL_OS_BOOT -/* Falcon Mode */ - -/* Falcon Mode - MMC support: args@1MB kernel@2MB */ -#endif /* Network support */ @@ -98,9 +91,9 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE #ifdef CONFIG_VIDEO #define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index 159bf4c68ca..83907b06ebb 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -10,14 +10,6 @@ #include "mx7_common.h" -#include "imx7_spl.h" - -#ifdef CONFIG_SPL_OS_BOOT -/* Falcon Mode */ - -/* Falcon Mode - MMC support: args@1MB kernel@2MB */ -#endif - #define CONFIG_MXC_UART_BASE UART5_IPS_BASE_ADDR /* MMC Config */ @@ -101,12 +93,11 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* PMIC */ -#define CONFIG_POWER_PFUZE3000 #define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 /* FLASH and environment organization */ diff --git a/include/configs/pico-imx8mq.h b/include/configs/pico-imx8mq.h index 17af19d49dc..f9301a5524b 100644 --- a/include/configs/pico-imx8mq.h +++ b/include/configs/pico-imx8mq.h @@ -63,11 +63,11 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x80000 -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2 GiB DDR */ diff --git a/include/configs/plutux.h b/include/configs/plutux.h index 09f0ed9b9a1..99db59c489e 100644 --- a/include/configs/plutux.h +++ b/include/configs/plutux.h @@ -16,7 +16,7 @@ /* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */ -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE /* NAND support */ diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h index 278f1b5cc62..a233fb8ed74 100644 --- a/include/configs/pm9261.h +++ b/include/configs/pm9261.h @@ -22,47 +22,47 @@ #define MASTER_PLL_DIV 15 #define MASTER_PLL_MUL 162 #define MAIN_PLL_DIV 2 -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 +#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ +#define CFG_SYS_AT91_MAIN_CLOCK 18432000 /* clocks */ /* CKGR_MOR - enable main osc. */ -#define CONFIG_SYS_MOR_VAL \ +#define CFG_SYS_MOR_VAL \ (AT91_PMC_MOR_MOSCEN | \ (255 << 8)) /* Main Oscillator Start-up Time */ -#define CONFIG_SYS_PLLAR_VAL \ +#define CFG_SYS_PLLAR_VAL \ (AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \ AT91_PMC_PLLXR_OUT(3) | \ ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) /* PCK/2 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR1_VAL \ +#define CFG_SYS_MCKR1_VAL \ (AT91_PMC_MCKR_CSS_SLOW | \ AT91_PMC_MCKR_PRES_1 | \ AT91_PMC_MCKR_MDIV_2) /* PCK/2 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR2_VAL \ +#define CFG_SYS_MCKR2_VAL \ (AT91_PMC_MCKR_CSS_PLLA | \ AT91_PMC_MCKR_PRES_1 | \ AT91_PMC_MCKR_MDIV_2) /* define PDC[31:16] as DATA[31:16] */ -#define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000 +#define CFG_SYS_PIOC_PDR_VAL1 0xFFFF0000 /* no pull-up for D[31:16] */ -#define CONFIG_SYS_PIOC_PPUDR_VAL 0xFFFF0000 +#define CFG_SYS_PIOC_PPUDR_VAL 0xFFFF0000 /* EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */ -#define CONFIG_SYS_MATRIX_EBICSA_VAL \ +#define CFG_SYS_MATRIX_EBICSA_VAL \ (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_EBI_CS1A) /* SDRAM */ /* SDRAMC_MR Mode register */ -#define CONFIG_SYS_SDRC_MR_VAL1 AT91_SDRAMC_MODE_NORMAL +#define CFG_SYS_SDRC_MR_VAL1 AT91_SDRAMC_MODE_NORMAL /* SDRAMC_TR - Refresh Timer register */ -#define CONFIG_SYS_SDRC_TR_VAL1 0x13C +#define CFG_SYS_SDRC_TR_VAL1 0x13C /* SDRAMC_CR - Configuration register*/ -#define CONFIG_SYS_SDRC_CR_VAL \ +#define CFG_SYS_SDRC_CR_VAL \ (AT91_SDRAMC_NC_9 | \ AT91_SDRAMC_NR_13 | \ AT91_SDRAMC_NB_4 | \ @@ -76,49 +76,49 @@ (1 << 28)) /* Exit Self Refresh to Active Delay */ /* Memory Device Register -> SDRAM */ -#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM -#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE -#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH -#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR -#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL -#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ -#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM +#define CFG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE +#define CFG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH +#define CFG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR +#define CFG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL +#define CFG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ +#define CFG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ -#define CONFIG_SYS_SMC0_SETUP0_VAL \ +#define CFG_SYS_SMC0_SETUP0_VAL \ (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) -#define CONFIG_SYS_SMC0_PULSE0_VAL \ +#define CFG_SYS_SMC0_PULSE0_VAL \ (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) -#define CONFIG_SYS_SMC0_CYCLE0_VAL \ +#define CFG_SYS_SMC0_CYCLE0_VAL \ (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) -#define CONFIG_SYS_SMC0_MODE0_VAL \ +#define CFG_SYS_SMC0_MODE0_VAL \ (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ AT91_SMC_MODE_DBW_16 | \ AT91_SMC_MODE_TDF | \ AT91_SMC_MODE_TDF_CYCLE(6)) /* user reset enable */ -#define CONFIG_SYS_RSTC_RMR_VAL \ +#define CFG_SYS_RSTC_RMR_VAL \ (AT91_RSTC_KEY | \ AT91_RSTC_CR_PROCRST | \ AT91_RSTC_MR_ERSTL(1) | \ AT91_RSTC_MR_ERSTL(2)) /* Disable Watchdog */ -#define CONFIG_SYS_WDTC_WDMR_VAL \ +#define CFG_SYS_WDTC_WDMR_VAL \ (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ AT91_WDT_MR_WDV(0xfff) | \ AT91_WDT_MR_WDDIS | \ @@ -129,21 +129,20 @@ #define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ /* NAND flash */ -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_DBW_8 1 +#define CFG_SYS_NAND_BASE 0x40000000 /* our ALE is AD22 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 22) +#define CFG_SYS_NAND_MASK_ALE (1 << 22) /* our CLE is AD21 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 21) -#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14) -#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(16) +#define CFG_SYS_NAND_MASK_CLE (1 << 21) +#define CFG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14) +#define CFG_SYS_NAND_READY_PIN GPIO_PIN_PA(16) /* NOR flash */ #define PHYS_FLASH_1 0x10000000 -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CFG_SYS_FLASH_BASE PHYS_FLASH_1 /* USB */ -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 +#define CFG_SYS_USB_OHCI_REGS_BASE 0x00500000 #define CONFIG_EXTRA_ENV_SETTINGS \ "partition=nand0,0\0" \ @@ -161,6 +160,6 @@ "flashboot=run ramargs;run addip;bootm 0x10050000\0" \ "" -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #endif diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h index 7c23206a300..9fd897958a4 100644 --- a/include/configs/pm9263.h +++ b/include/configs/pm9263.h @@ -22,14 +22,14 @@ #define MASTER_PLL_DIV 6 #define MASTER_PLL_MUL 65 #define MAIN_PLL_DIV 2 /* 2 or 4 */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ +#define CFG_SYS_AT91_MAIN_CLOCK 18432000 +#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ /* clocks */ -#define CONFIG_SYS_MOR_VAL \ +#define CFG_SYS_MOR_VAL \ (AT91_PMC_MOR_MOSCEN | \ (255 << 8)) /* Main Oscillator Start-up Time */ -#define CONFIG_SYS_PLLAR_VAL \ +#define CFG_SYS_PLLAR_VAL \ (AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \ AT91_PMC_PLLXR_OUT(3) | \ AT91_PMC_PLLXR_PLLCOUNT(0x3f) | /* PLL Counter */\ @@ -38,43 +38,43 @@ #if (MAIN_PLL_DIV == 2) /* PCK/2 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR1_VAL \ +#define CFG_SYS_MCKR1_VAL \ (AT91_PMC_MCKR_CSS_SLOW | \ AT91_PMC_MCKR_PRES_1 | \ AT91_PMC_MCKR_MDIV_2) /* PCK/2 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR2_VAL \ +#define CFG_SYS_MCKR2_VAL \ (AT91_PMC_MCKR_CSS_PLLA | \ AT91_PMC_MCKR_PRES_1 | \ AT91_PMC_MCKR_MDIV_2) #else /* PCK/4 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR1_VAL \ +#define CFG_SYS_MCKR1_VAL \ (AT91_PMC_MCKR_CSS_SLOW | \ AT91_PMC_MCKR_PRES_1 | \ AT91_PMC_MCKR_MDIV_4) /* PCK/4 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR2_VAL \ +#define CFG_SYS_MCKR2_VAL \ (AT91_PMC_MCKR_CSS_PLLA | \ AT91_PMC_MCKR_PRES_1 | \ AT91_PMC_MCKR_MDIV_4) #endif /* define PDC[31:16] as DATA[31:16] */ -#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 +#define CFG_SYS_PIOD_PDR_VAL1 0xFFFF0000 /* no pull-up for D[31:16] */ -#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 +#define CFG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ -#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \ +#define CFG_SYS_MATRIX_EBI0CSA_VAL \ (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \ AT91_MATRIX_CSA_EBI_CS1A) /* SDRAM */ /* SDRAMC_MR Mode register */ -#define CONFIG_SYS_SDRC_MR_VAL1 0 +#define CFG_SYS_SDRC_MR_VAL1 0 /* SDRAMC_TR - Refresh Timer register */ -#define CONFIG_SYS_SDRC_TR_VAL1 0x3AA +#define CFG_SYS_SDRC_TR_VAL1 0x3AA /* SDRAMC_CR - Configuration register*/ -#define CONFIG_SYS_SDRC_CR_VAL \ +#define CFG_SYS_SDRC_CR_VAL \ (AT91_SDRAMC_NC_9 | \ AT91_SDRAMC_NR_13 | \ AT91_SDRAMC_NB_4 | \ @@ -88,49 +88,49 @@ (8 << 28)) /* tXSR - Exit Self Refresh to Active Delay */ /* Memory Device Register -> SDRAM */ -#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM -#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE -#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH -#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR -#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL -#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ -#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM +#define CFG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE +#define CFG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH +#define CFG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR +#define CFG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL +#define CFG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ +#define CFG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ -#define CONFIG_SYS_SMC0_SETUP0_VAL \ +#define CFG_SYS_SMC0_SETUP0_VAL \ (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) -#define CONFIG_SYS_SMC0_PULSE0_VAL \ +#define CFG_SYS_SMC0_PULSE0_VAL \ (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) -#define CONFIG_SYS_SMC0_CYCLE0_VAL \ +#define CFG_SYS_SMC0_CYCLE0_VAL \ (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) -#define CONFIG_SYS_SMC0_MODE0_VAL \ +#define CFG_SYS_SMC0_MODE0_VAL \ (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ AT91_SMC_MODE_DBW_16 | \ AT91_SMC_MODE_TDF | \ AT91_SMC_MODE_TDF_CYCLE(6)) /* user reset enable */ -#define CONFIG_SYS_RSTC_RMR_VAL \ +#define CFG_SYS_RSTC_RMR_VAL \ (AT91_RSTC_KEY | \ AT91_RSTC_CR_PROCRST | \ AT91_RSTC_MR_ERSTL(1) | \ AT91_RSTC_MR_ERSTL(2)) /* Disable Watchdog */ -#define CONFIG_SYS_WDTC_WDMR_VAL \ +#define CFG_SYS_WDTC_WDMR_VAL \ (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ AT91_WDT_MR_WDV(0xfff) | \ AT91_WDT_MR_WDDIS | \ @@ -142,18 +142,17 @@ /* NOR flash, if populated */ #define PHYS_FLASH_1 0x10000000 -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CFG_SYS_FLASH_BASE PHYS_FLASH_1 /* NAND flash */ #ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_DBW_8 1 +#define CFG_SYS_NAND_BASE 0x40000000 /* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +#define CFG_SYS_NAND_MASK_ALE (1 << 21) /* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15) -#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PB(30) +#define CFG_SYS_NAND_MASK_CLE (1 << 22) +#define CFG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15) +#define CFG_SYS_NAND_READY_PIN GPIO_PIN_PB(30) #endif @@ -167,7 +166,7 @@ AT91_MATRIX_SCFG_SLOT_CYCLE(255)) /* USB */ -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ +#define CFG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ #define CONFIG_EXTRA_ENV_SETTINGS \ "partition=nand0,0\0" \ @@ -185,6 +184,6 @@ "flashboot=run ramargs;run addip;bootm 0x10050000\0" \ "" -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #endif diff --git a/include/configs/pm9g45.h b/include/configs/pm9g45.h index 35fd5256836..686411eee2e 100644 --- a/include/configs/pm9g45.h +++ b/include/configs/pm9g45.h @@ -16,23 +16,22 @@ #define __CONFIG_H /* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 +#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x70000000 -#define CONFIG_SYS_SDRAM_SIZE 0x08000000 +#define CFG_SYS_SDRAM_BASE 0x70000000 +#define CFG_SYS_SDRAM_SIZE 0x08000000 /* NAND flash */ #ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 -#define CONFIG_SYS_NAND_DBW_8 +#define CFG_SYS_NAND_BASE ATMEL_BASE_CS3 /* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE BIT(21) +#define CFG_SYS_NAND_MASK_ALE BIT(21) /* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE BIT(22) -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD3 +#define CFG_SYS_NAND_MASK_CLE BIT(22) +#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 +#define CFG_SYS_NAND_READY_PIN AT91_PIN_PD3 #endif #ifdef CONFIG_NAND_BOOT @@ -45,18 +44,18 @@ #ifdef CONFIG_SD_BOOT #elif CONFIG_NAND_BOOT -#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000 +#define CFG_SYS_NAND_U_BOOT_SIZE 0x80000 -#define CONFIG_SYS_NAND_ECCSIZE 256 -#define CONFIG_SYS_NAND_ECCBYTES 3 -#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ +#define CFG_SYS_NAND_ECCSIZE 256 +#define CFG_SYS_NAND_ECCBYTES 3 +#define CFG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ 48, 49, 50, 51, 52, 53, 54, 55, \ 56, 57, 58, 59, 60, 61, 62, 63, } #endif -#define CONFIG_SYS_MASTER_CLOCK 132096000 -#define CONFIG_SYS_AT91_PLLA 0x20c73f03 -#define CONFIG_SYS_MCKR 0x1301 -#define CONFIG_SYS_MCKR_CSS 0x1302 +#define CFG_SYS_MASTER_CLOCK 132096000 +#define CFG_SYS_AT91_PLLA 0x20c73f03 +#define CFG_SYS_MCKR 0x1301 +#define CFG_SYS_MCKR_CSS 0x1302 #endif diff --git a/include/configs/poleg.h b/include/configs/poleg.h index 05253d59efd..518d7a3639c 100644 --- a/include/configs/poleg.h +++ b/include/configs/poleg.h @@ -7,11 +7,11 @@ #define __CONFIG_POLEG_H #ifndef CONFIG_SYS_L2CACHE_OFF -#define CONFIG_SYS_PL310_BASE 0xF03FC000 /* L2 - Cache Regs Base (4k Space)*/ +#define CFG_SYS_PL310_BASE 0xF03FC000 /* L2 - Cache Regs Base (4k Space)*/ #endif -#define CONFIG_SYS_BOOTMAPSZ (0x30 << 20) -#define CONFIG_SYS_SDRAM_BASE 0x0 +#define CFG_SYS_BOOTMAPSZ (0x30 << 20) +#define CFG_SYS_SDRAM_BASE 0x0 /* Default environemnt variables */ #define CONFIG_SERVERIP 192.168.0.1 diff --git a/include/configs/pomelo.h b/include/configs/pomelo.h index 2e206542f8d..1c11685f49e 100644 --- a/include/configs/pomelo.h +++ b/include/configs/pomelo.h @@ -9,7 +9,7 @@ #define __POMELO_CONFIG_H__ /* SDRAM Bank #1 start address */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 /* SIZE of malloc pool */ diff --git a/include/configs/presidio_asic.h b/include/configs/presidio_asic.h index ebf5467ef41..2b25c31b1d8 100644 --- a/include/configs/presidio_asic.h +++ b/include/configs/presidio_asic.h @@ -9,8 +9,8 @@ #define __PRESIDIO_ASIC_H /* Generic Timer Definitions */ -#define CONFIG_SYS_TIMER_RATE 25000000 -#define CONFIG_SYS_TIMER_COUNTER 0xf4321008 +#define CFG_SYS_TIMER_RATE 25000000 +#define CFG_SYS_TIMER_COUNTER 0xf4321008 /* note: arch/arm/cpu/armv8/start.S which references GICD_BASE/GICC_BASE * does not yet support DT. Thus define it here. @@ -18,7 +18,7 @@ #define GICD_BASE 0xf7011000 #define GICC_BASE 0xf7012000 -#define CONFIG_SYS_TIMER_BASE 0xf4321000 +#define CFG_SYS_TIMER_BASE 0xf4321000 /* Use external clock source */ #define PRESIDIO_APB_CLK 125000000 @@ -26,17 +26,17 @@ /* Cortina Serial Configuration */ #define CORTINA_UART_CLOCK (PRESIDIO_APB_CLK) -#define CORTINA_SERIAL_PORTS {(void *)CONFIG_SYS_SERIAL0, \ - (void *)CONFIG_SYS_SERIAL1} +#define CORTINA_SERIAL_PORTS {(void *)CFG_SYS_SERIAL0, \ + (void *)CFG_SYS_SERIAL1} -#define CONFIG_SYS_SERIAL0 PER_UART0_CFG -#define CONFIG_SYS_SERIAL1 PER_UART1_CFG +#define CFG_SYS_SERIAL0 PER_UART0_CFG +#define CFG_SYS_SERIAL1 PER_UART1_CFG /* SDRAM Bank #1 */ #define DDR_BASE 0x00000000 #define PHYS_SDRAM_1 DDR_BASE #define PHYS_SDRAM_1_SIZE 0x80000000 /* 2GB */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 /* Console I/O Buffer Size */ @@ -58,8 +58,8 @@ /* nand driver parameters */ #ifdef CONFIG_TARGET_PRESIDIO_ASIC - #define CONFIG_SYS_NAND_BASE CONFIG_SYS_FLASH_BASE - #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } + #define CFG_SYS_NAND_BASE CFG_SYS_FLASH_BASE + #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #endif #endif /* __PRESIDIO_ASIC_H */ diff --git a/include/configs/px30_common.h b/include/configs/px30_common.h index 49d1878ebdd..99376155b49 100644 --- a/include/configs/px30_common.h +++ b/include/configs/px30_common.h @@ -8,15 +8,13 @@ #include "rockchip-common.h" -#define CONFIG_SYS_NS16550_MEM32 - /* FIXME: ff020000 is pmu_mem (10k), while ff0e0000 is regular int_mem */ #define CONFIG_IRAM_BASE 0xff020000 #define GICD_BASE 0xff131000 #define GICC_BASE 0xff132000 -#define CONFIG_SYS_SDRAM_BASE 0 +#define CFG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xff000000 #define SDRAM_BANK_SIZE (2UL << 30) diff --git a/include/configs/qcs404-evb.h b/include/configs/qcs404-evb.h index 58020ae95b1..c41bb341d82 100644 --- a/include/configs/qcs404-evb.h +++ b/include/configs/qcs404-evb.h @@ -11,7 +11,7 @@ #include <linux/sizes.h> #include <asm/arch/sysmap-qcs404.h> -#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 } +#define CFG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 } #define CONFIG_EXTRA_ENV_SETTINGS \ "bootm_size=0x5000000\0" \ diff --git a/include/configs/qemu-arm.h b/include/configs/qemu-arm.h index 535762ecb24..a67af73fd56 100644 --- a/include/configs/qemu-arm.h +++ b/include/configs/qemu-arm.h @@ -10,7 +10,7 @@ /* Physical memory map */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 /* GUIDs for capsule updatable firmware images */ #define QEMU_ARM_UBOOT_IMAGE_GUID \ diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h index 9fc51fdfd76..30a9eae8523 100644 --- a/include/configs/qemu-ppce500.h +++ b/include/configs/qemu-ppce500.h @@ -12,42 +12,37 @@ /* Needed to fill the ccsrbar pointer */ /* Virtual address to CCSRBAR */ -#define CONFIG_SYS_CCSRBAR 0xe0000000 +#define CFG_SYS_CCSRBAR 0xe0000000 /* Physical address should be a function call */ #ifndef __ASSEMBLY__ extern unsigned long long get_phys_ccsrbar_addr_early(void); -#define CONFIG_SYS_CCSRBAR_PHYS_HIGH (get_phys_ccsrbar_addr_early() >> 32) -#define CONFIG_SYS_CCSRBAR_PHYS_LOW get_phys_ccsrbar_addr_early() +#define CFG_SYS_CCSRBAR_PHYS_HIGH (get_phys_ccsrbar_addr_early() >> 32) +#define CFG_SYS_CCSRBAR_PHYS_LOW get_phys_ccsrbar_addr_early() #else -#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR +#define CFG_SYS_CCSRBAR_PHYS_HIGH 0x0 +#define CFG_SYS_CCSRBAR_PHYS_LOW CFG_SYS_CCSRBAR #endif /* Virtual address to a temporary map if we need it (max 128MB) */ -#define CONFIG_SYS_TMPVIRT 0xe8000000 +#define CFG_SYS_TMPVIRT 0xe8000000 /* * DDR Setup */ #define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE -#define CONFIG_HWCONFIG - -#define CONFIG_SYS_INIT_RAM_ADDR 0x00100000 -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0x0 -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0x00100000 +#define CFG_SYS_INIT_RAM_ADDR 0x00100000 +#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0x0 +#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0x00100000 /* The assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 - -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CFG_SYS_INIT_RAM_ADDR_PHYS \ + ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CFG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#define CFG_SYS_INIT_RAM_SIZE 0x00004000 -/* RTC */ -#define CONFIG_RTC_PT7C4338 +#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /* * Miscellaneous configurable options @@ -58,7 +53,7 @@ extern unsigned long long get_phys_ccsrbar_addr_early(void); * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ /* * Environment Configuration diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h index d81e5d6c862..72f35cc0542 100644 --- a/include/configs/qemu-riscv.h +++ b/include/configs/qemu-riscv.h @@ -8,7 +8,7 @@ #include <linux/sizes.h> -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 diff --git a/include/configs/r2dplus.h b/include/configs/r2dplus.h index ac39e11a99e..bad74cc620d 100644 --- a/include/configs/r2dplus.h +++ b/include/configs/r2dplus.h @@ -6,21 +6,16 @@ /* SCIF */ /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x8C000000 -#define CONFIG_SYS_SDRAM_SIZE 0x04000000 +#define CFG_SYS_SDRAM_BASE 0x8C000000 +#define CFG_SYS_SDRAM_SIZE 0x04000000 /* Address of u-boot image in Flash */ -#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) +#define CFG_SYS_BOOTMAPSZ (8 * 1024 * 1024) /* * NOR Flash ( Spantion S29GL256P ) */ -#define CONFIG_SYS_FLASH_BASE (0xA0000000) -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } - -/* - * SuperH Clock setting - */ -#define CONFIG_SYS_PLL_SETTLING_TIME 100/* in us */ +#define CFG_SYS_FLASH_BASE (0xA0000000) +#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE } #endif /* __CONFIG_H */ diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h index 3a38e0656de..291c2a43d4d 100644 --- a/include/configs/rcar-gen2-common.h +++ b/include/configs/rcar-gen2-common.h @@ -10,20 +10,14 @@ #include <asm/arch/rmobile.h> -#ifndef CONFIG_PINCTRL_PFC -#define CONFIG_SH_GPIO_PFC -#endif - /* console */ -#define CONFIG_SYS_BAUDRATE_TABLE { 38400, 115200 } +#define CFG_SYS_BAUDRATE_TABLE { 38400, 115200 } -#define CONFIG_SYS_SDRAM_BASE (RCAR_GEN2_SDRAM_BASE) -#define CONFIG_SYS_SDRAM_SIZE (RCAR_GEN2_UBOOT_SDRAM_SIZE) +#define CFG_SYS_SDRAM_BASE (RCAR_GEN2_SDRAM_BASE) +#define CFG_SYS_SDRAM_SIZE (RCAR_GEN2_UBOOT_SDRAM_SIZE) /* Timer */ -#define CONFIG_TMU_TIMER -#define CONFIG_SYS_TIMER_COUNTS_DOWN -#define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */ -#define CONFIG_SYS_TIMER_RATE (get_board_sys_clk() / 8) +#define CFG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */ +#define CFG_SYS_TIMER_RATE (get_board_sys_clk() / 8) #endif /* __RCAR_GEN2_COMMON_H */ diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h index 7432cffb5a5..e9cbd253824 100644 --- a/include/configs/rcar-gen3-common.h +++ b/include/configs/rcar-gen3-common.h @@ -18,7 +18,7 @@ #define GICC_BASE 0xF1020000 /* console */ -#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400 } +#define CFG_SYS_BAUDRATE_TABLE { 115200, 38400 } /* PHY needs a longer autoneg timeout */ #define PHY_ANEG_TIMEOUT 20000 @@ -26,8 +26,8 @@ /* MEMORY */ #define DRAM_RSV_SIZE 0x08000000 -#define CONFIG_SYS_SDRAM_BASE (0x40000000 + DRAM_RSV_SIZE) -#define CONFIG_SYS_SDRAM_SIZE (0x80000000u - DRAM_RSV_SIZE) +#define CFG_SYS_SDRAM_BASE (0x40000000 + DRAM_RSV_SIZE) +#define CFG_SYS_SDRAM_SIZE (0x80000000u - DRAM_RSV_SIZE) #define CONFIG_VERY_BIG_RAM #define CONFIG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE) diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h index 6616396777a..a4cae697181 100644 --- a/include/configs/rk3036_common.h +++ b/include/configs/rk3036_common.h @@ -8,9 +8,9 @@ #include <asm/arch-rockchip/hardware.h> #include "rockchip-common.h" -#define CONFIG_SYS_HZ_CLOCK 24000000 +#define CFG_SYS_HZ_CLOCK 24000000 -#define CONFIG_SYS_SDRAM_BASE 0x60000000 +#define CFG_SYS_SDRAM_BASE 0x60000000 #define SDRAM_BANK_SIZE (512UL << 20UL) #define SDRAM_MAX_SIZE (CONFIG_NR_DRAM_BANKS * SDRAM_BANK_SIZE) diff --git a/include/configs/rk3066_common.h b/include/configs/rk3066_common.h index 9297184bded..99c86edeaa4 100644 --- a/include/configs/rk3066_common.h +++ b/include/configs/rk3066_common.h @@ -11,7 +11,7 @@ #define CONFIG_IRAM_BASE 0x10080000 -#define CONFIG_SYS_SDRAM_BASE 0x60000000 +#define CFG_SYS_SDRAM_BASE 0x60000000 #define SDRAM_BANK_SIZE (1024UL << 20UL) #define SDRAM_MAX_SIZE CONFIG_NR_DRAM_BANKS * SDRAM_BANK_SIZE diff --git a/include/configs/rk3128_common.h b/include/configs/rk3128_common.h index 12d4bc65d7e..302546630ac 100644 --- a/include/configs/rk3128_common.h +++ b/include/configs/rk3128_common.h @@ -8,13 +8,13 @@ #include "rockchip-common.h" -#define CONFIG_SYS_HZ_CLOCK 24000000 +#define CFG_SYS_HZ_CLOCK 24000000 #define CONFIG_IRAM_BASE 0x10080000 /* RAW SD card / eMMC locations. */ -#define CONFIG_SYS_SDRAM_BASE 0x60000000 +#define CFG_SYS_SDRAM_BASE 0x60000000 #define SDRAM_MAX_SIZE 0x80000000 /* usb mass storage */ diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h index 6fe1b2d9a2e..334fb3affa5 100644 --- a/include/configs/rk3188_common.h +++ b/include/configs/rk3188_common.h @@ -13,7 +13,7 @@ /* spl size 32kb sram - 2kb bootrom */ -#define CONFIG_SYS_SDRAM_BASE 0x60000000 +#define CFG_SYS_SDRAM_BASE 0x60000000 #define SDRAM_BANK_SIZE (2UL << 30) #define SDRAM_MAX_SIZE 0x80000000 diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h index 4fb86b69a8e..58ad62afe16 100644 --- a/include/configs/rk322x_common.h +++ b/include/configs/rk322x_common.h @@ -8,11 +8,11 @@ #include <asm/arch-rockchip/hardware.h> #include "rockchip-common.h" -#define CONFIG_SYS_HZ_CLOCK 24000000 +#define CFG_SYS_HZ_CLOCK 24000000 #define CONFIG_IRAM_BASE 0x10080000 -#define CONFIG_SYS_SDRAM_BASE 0x60000000 +#define CFG_SYS_SDRAM_BASE 0x60000000 #define SDRAM_BANK_SIZE (512UL << 20UL) #define SDRAM_MAX_SIZE 0x80000000 diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index 81f16edbad6..6b55c57dd77 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -9,13 +9,13 @@ #include <asm/arch-rockchip/hardware.h> #include "rockchip-common.h" -#define CONFIG_SYS_HZ_CLOCK 24000000 +#define CFG_SYS_HZ_CLOCK 24000000 #define CONFIG_IRAM_BASE 0xff700000 /* RAW SD card / eMMC locations. */ -#define CONFIG_SYS_SDRAM_BASE 0 +#define CFG_SYS_SDRAM_BASE 0 #define SDRAM_BANK_SIZE (2UL << 30) #define SDRAM_MAX_SIZE 0xfe000000 diff --git a/include/configs/rk3308_common.h b/include/configs/rk3308_common.h index 200b34b35ba..4b510b13991 100644 --- a/include/configs/rk3308_common.h +++ b/include/configs/rk3308_common.h @@ -8,11 +8,9 @@ #include "rockchip-common.h" -#define CONFIG_SYS_NS16550_MEM32 - #define CONFIG_IRAM_BASE 0xfff80000 -#define CONFIG_SYS_SDRAM_BASE 0 +#define CFG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xff000000 #define SDRAM_BANK_SIZE (2UL << 30) diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h index 1e214e4ebe1..132b7d0fe9b 100644 --- a/include/configs/rk3328_common.h +++ b/include/configs/rk3328_common.h @@ -11,7 +11,7 @@ #define CONFIG_IRAM_BASE 0xff090000 /* FAT sd card locations. */ -#define CONFIG_SYS_SDRAM_BASE 0 +#define CFG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xff000000 #define ENV_MEM_LAYOUT_SETTINGS \ diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h index 37e0c1d936c..92cdc1a51fb 100644 --- a/include/configs/rk3368_common.h +++ b/include/configs/rk3368_common.h @@ -11,7 +11,7 @@ #include <asm/arch-rockchip/hardware.h> #include <linux/sizes.h> -#define CONFIG_SYS_SDRAM_BASE 0 +#define CFG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xff000000 #define CONFIG_IRAM_BASE 0xff8c0000 diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index 2f9aee58197..78f624d31ca 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -21,7 +21,7 @@ /* RAW SD card / eMMC locations. */ /* FAT sd card locations. */ -#define CONFIG_SYS_SDRAM_BASE 0 +#define CFG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xf8000000 #ifndef CONFIG_SPL_BUILD diff --git a/include/configs/rk3568_common.h b/include/configs/rk3568_common.h index 15e81523402..d43dc2580e4 100644 --- a/include/configs/rk3568_common.h +++ b/include/configs/rk3568_common.h @@ -10,7 +10,7 @@ #define CONFIG_IRAM_BASE 0xfdcc0000 -#define CONFIG_SYS_SDRAM_BASE 0 +#define CFG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xf0000000 #define ENV_MEM_LAYOUT_SETTINGS \ diff --git a/include/configs/rockchip-common.h b/include/configs/rockchip-common.h index 4c964cc3770..1f6b82f2d02 100644 --- a/include/configs/rockchip-common.h +++ b/include/configs/rockchip-common.h @@ -7,8 +7,6 @@ #define _ROCKCHIP_COMMON_H_ #include <linux/sizes.h> -#define CONFIG_SYS_NS16550_MEM32 - /* ((CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - 64) * 512) */ #ifndef CONFIG_SPL_BUILD diff --git a/include/configs/rpi.h b/include/configs/rpi.h index cd8fe8b518b..e3549275138 100644 --- a/include/configs/rpi.h +++ b/include/configs/rpi.h @@ -17,21 +17,21 @@ /* Use SoC timer for AArch32, but architected timer for AArch64 */ #ifndef CONFIG_ARM64 -#define CONFIG_SYS_TIMER_RATE 1000000 -#define CONFIG_SYS_TIMER_COUNTER \ +#define CFG_SYS_TIMER_RATE 1000000 +#define CFG_SYS_TIMER_COUNTER \ (&((struct bcm2835_timer_regs *)BCM2835_TIMER_PHYSADDR)->clo) #endif /* Memory layout */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_UBOOT_BASE CONFIG_TEXT_BASE +#define CFG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE /* * The board really has 256M. However, the VC (VideoCore co-processor) shares * the RAM, and uses a configurable portion at the top. We tell U-Boot that a * smaller amount of RAM is present in order to avoid stomping on the area * the VC uses. */ -#define CONFIG_SYS_SDRAM_SIZE SZ_128M +#define CFG_SYS_SDRAM_SIZE SZ_128M /* Devices */ /* LCD */ diff --git a/include/configs/rv1108_common.h b/include/configs/rv1108_common.h index 83c3167f38d..84a5ae6965d 100644 --- a/include/configs/rv1108_common.h +++ b/include/configs/rv1108_common.h @@ -10,12 +10,12 @@ #define CONFIG_IRAM_BASE 0x10080000 -#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000) +#define CFG_SYS_TIMER_RATE (24 * 1000 * 1000) /* TIMER1,initialized by ddr initialize code */ -#define CONFIG_SYS_TIMER_BASE 0x10350020 -#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) +#define CFG_SYS_TIMER_BASE 0x10350020 +#define CFG_SYS_TIMER_COUNTER (CFG_SYS_TIMER_BASE + 8) -#define CONFIG_SYS_SDRAM_BASE 0x60000000 +#define CFG_SYS_SDRAM_BASE 0x60000000 /* rockchip ohci host driver */ diff --git a/include/configs/s5p4418_nanopi2.h b/include/configs/s5p4418_nanopi2.h index ae94f0ecc56..e071d4da5e8 100644 --- a/include/configs/s5p4418_nanopi2.h +++ b/include/configs/s5p4418_nanopi2.h @@ -18,7 +18,7 @@ /*----------------------------------------------------------------------- * System memory Configuration */ -#define CONFIG_SYS_SDRAM_BASE 0x71000000 +#define CFG_SYS_SDRAM_BASE 0x71000000 /* * "(0x40000000 - CONFIG_SYS_RESERVE_MEM_SIZE)" has been used in @@ -55,7 +55,7 @@ * Starting kernel ... * ... */ -#define CONFIG_SYS_SDRAM_SIZE (0xb0000000 - CONFIG_SYS_SDRAM_BASE) +#define CFG_SYS_SDRAM_SIZE (0xb0000000 - CFG_SYS_SDRAM_BASE) #define BMP_LOAD_ADDR 0x78000000 diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index de4510aa434..fdade1ee66f 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -14,7 +14,7 @@ #include <asm/arch/cpu.h> /* get chip and board defs */ /* DRAM Base */ -#define CONFIG_SYS_SDRAM_BASE 0x30000000 +#define CFG_SYS_SDRAM_BASE 0x30000000 /* Text Base */ @@ -61,8 +61,6 @@ #define COMMON_BOOT "${console} ${meminfo} ${mtdparts}" -#define CONFIG_MISC_COMMON - #define CONFIG_EXTRA_ENV_SETTINGS \ "updateb=" \ "onenand erase 0x0 0x100000;" \ @@ -114,7 +112,7 @@ "dfu_alt_info=" CONFIG_DFU_ALT "\0" /* Goni has 3 banks of DRAM, but swap the bank */ -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* OneDRAM Bank #0 */ +#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE /* OneDRAM Bank #0 */ #define PHYS_SDRAM_1_SIZE (80 << 20) /* 80 MB in Bank #0 */ #define PHYS_SDRAM_2 0x40000000 /* mDDR DMC1 Bank #1 */ #define PHYS_SDRAM_2_SIZE (256 << 20) /* 256 MB in Bank #1 */ @@ -124,6 +122,6 @@ /* FLASH and environment organization */ #define CONFIG_MMC_DEFAULT_DEV 0 -#define CONFIG_SYS_ONENAND_BASE 0xB0000000 +#define CFG_SYS_ONENAND_BASE 0xB0000000 #endif /* __CONFIG_H */ diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index 668b52600e8..80d3fc9258c 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -14,8 +14,8 @@ /* Keep L2 Cache Disabled */ /* Universal has 2 banks of DRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ @@ -87,7 +87,7 @@ "mmcrootpart=3\0" \ "opts=always_resume=1" -#define CONFIG_SYS_ONENAND_BASE 0x0C000000 +#define CFG_SYS_ONENAND_BASE 0x0C000000 #ifndef __ASSEMBLY__ void universal_spi_scl(int bit); @@ -95,9 +95,6 @@ void universal_spi_sda(int bit); int universal_spi_read(void); #endif -/* Common misc for Samsung */ -#define CONFIG_MISC_COMMON - /* Download menu - definitions for check keys */ #ifndef __ASSEMBLY__ diff --git a/include/configs/salvator-x.h b/include/configs/salvator-x.h index 41e52546ed3..2e422cd241e 100644 --- a/include/configs/salvator-x.h +++ b/include/configs/salvator-x.h @@ -14,7 +14,7 @@ /* Environment in eMMC, at the end of 2nd "boot sector" */ #define CONFIG_FLASH_SHOW_PROGRESS 45 -#define CONFIG_SYS_FLASH_BANKS_LIST { 0x08000000 } -#define CONFIG_SYS_WRITE_SWAPPED_DATA +#define CFG_SYS_FLASH_BANKS_LIST { 0x08000000 } +#define CFG_SYS_WRITE_SWAPPED_DATA #endif /* __SALVATOR_X_H */ diff --git a/include/configs/sam9x60_curiosity.h b/include/configs/sam9x60_curiosity.h index afb1e3d0f10..f44ce909b91 100644 --- a/include/configs/sam9x60_curiosity.h +++ b/include/configs/sam9x60_curiosity.h @@ -10,14 +10,14 @@ #ifndef __CONFIG_H__ #define __CONFIG_H__ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* 24 MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 +#define CFG_SYS_AT91_MAIN_CLOCK 24000000 /* 24 MHz crystal */ #define CONFIG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID 0 /* ignored in arm */ /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x8000000 /* 128 MB */ +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE 0x8000000 /* 128 MB */ #endif diff --git a/include/configs/sam9x60ek.h b/include/configs/sam9x60ek.h index 70c6ec5b65c..27b39ebf417 100644 --- a/include/configs/sam9x60ek.h +++ b/include/configs/sam9x60ek.h @@ -11,8 +11,8 @@ #define __CONFIG_H__ /* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* 24 MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 +#define CFG_SYS_AT91_MAIN_CLOCK 24000000 /* 24 MHz crystal */ #define CONFIG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID 0 /* ignored in arm */ @@ -23,16 +23,16 @@ */ /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 megs */ +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE 0x10000000 /* 256 megs */ /* NAND flash */ #ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_MASK_ALE BIT(21) -#define CONFIG_SYS_NAND_MASK_CLE BIT(22) -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5 +#define CFG_SYS_NAND_BASE 0x40000000 +#define CFG_SYS_NAND_MASK_ALE BIT(21) +#define CFG_SYS_NAND_MASK_CLE BIT(22) +#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4 +#define CFG_SYS_NAND_READY_PIN AT91_PIN_PD5 #endif #endif diff --git a/include/configs/sama5d27_som1_ek.h b/include/configs/sama5d27_som1_ek.h index 79f354d2e6c..d62146e7797 100644 --- a/include/configs/sama5d27_som1_ek.h +++ b/include/configs/sama5d27_som1_ek.h @@ -11,8 +11,8 @@ #include "at91-sama5_common.h" -#undef CONFIG_SYS_AT91_MAIN_CLOCK -#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ +#undef CFG_SYS_AT91_MAIN_CLOCK +#define CFG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ /* SPL */ diff --git a/include/configs/sama5d27_wlsom1_ek.h b/include/configs/sama5d27_wlsom1_ek.h index de6c92ed7d4..1979cb366e5 100644 --- a/include/configs/sama5d27_wlsom1_ek.h +++ b/include/configs/sama5d27_wlsom1_ek.h @@ -12,12 +12,12 @@ #include "at91-sama5_common.h" -#undef CONFIG_SYS_AT91_MAIN_CLOCK -#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ +#undef CFG_SYS_AT91_MAIN_CLOCK +#define CFG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x10000000 +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE 0x10000000 /* SPL */ diff --git a/include/configs/sama5d2_icp.h b/include/configs/sama5d2_icp.h index ebdb39273ef..a072b21dfb8 100644 --- a/include/configs/sama5d2_icp.h +++ b/include/configs/sama5d2_icp.h @@ -11,12 +11,12 @@ #include "at91-sama5_common.h" -#undef CONFIG_SYS_AT91_MAIN_CLOCK -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ +#undef CFG_SYS_AT91_MAIN_CLOCK +#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x20000000 +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE 0x20000000 #ifdef CONFIG_SD_BOOT /* u-boot env in sd/mmc card */ diff --git a/include/configs/sama5d2_ptc_ek.h b/include/configs/sama5d2_ptc_ek.h index 9281c7ccc40..bf3c92bdf39 100644 --- a/include/configs/sama5d2_ptc_ek.h +++ b/include/configs/sama5d2_ptc_ek.h @@ -12,20 +12,20 @@ #include "at91-sama5_common.h" -#undef CONFIG_SYS_AT91_MAIN_CLOCK -#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ +#undef CFG_SYS_AT91_MAIN_CLOCK +#define CFG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x20000000 +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE 0x20000000 /* NAND Flash */ #ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 +#define CFG_SYS_NAND_BASE ATMEL_BASE_CS3 /* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE BIT(21) +#define CFG_SYS_NAND_MASK_ALE BIT(21) /* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE BIT(22) +#define CFG_SYS_NAND_MASK_CLE BIT(22) #endif #endif /* __CONFIG_H */ diff --git a/include/configs/sama5d3_xplained.h b/include/configs/sama5d3_xplained.h index eed688d6b3e..4b13a101170 100644 --- a/include/configs/sama5d3_xplained.h +++ b/include/configs/sama5d3_xplained.h @@ -24,16 +24,16 @@ #define ATMEL_PMC_UHP (1 << 6) /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x10000000 +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE 0x10000000 /* NAND flash */ #ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_NAND_BASE 0x60000000 +#define CFG_SYS_NAND_BASE 0x60000000 /* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +#define CFG_SYS_NAND_MASK_ALE (1 << 21) /* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CFG_SYS_NAND_MASK_CLE (1 << 22) #endif /* SPL */ diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h index b05fa59d722..4f579ad9c56 100644 --- a/include/configs/sama5d3xek.h +++ b/include/configs/sama5d3xek.h @@ -27,22 +27,22 @@ /* NOR flash */ #ifdef CONFIG_MTD_NOR_FLASH -#define CONFIG_SYS_FLASH_BASE 0x10000000 +#define CFG_SYS_FLASH_BASE 0x10000000 #endif /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x20000000 +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE 0x20000000 /* SerialFlash */ /* NAND flash */ #ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_NAND_BASE 0x60000000 +#define CFG_SYS_NAND_BASE 0x60000000 /* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +#define CFG_SYS_NAND_MASK_ALE (1 << 21) /* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CFG_SYS_NAND_MASK_CLE (1 << 22) #endif /* SPL */ diff --git a/include/configs/sama5d4_xplained.h b/include/configs/sama5d4_xplained.h index c4552c26975..084cb4def66 100644 --- a/include/configs/sama5d4_xplained.h +++ b/include/configs/sama5d4_xplained.h @@ -12,16 +12,16 @@ #include "at91-sama5_common.h" /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x20000000 +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE 0x20000000 /* NAND flash */ #ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_NAND_BASE 0x80000000 +#define CFG_SYS_NAND_BASE 0x80000000 /* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +#define CFG_SYS_NAND_MASK_ALE (1 << 21) /* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CFG_SYS_NAND_MASK_CLE (1 << 22) #endif /* SPL */ diff --git a/include/configs/sama5d4ek.h b/include/configs/sama5d4ek.h index d7199921ba3..cbc1c0f4651 100644 --- a/include/configs/sama5d4ek.h +++ b/include/configs/sama5d4ek.h @@ -12,16 +12,16 @@ #include "at91-sama5_common.h" /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x20000000 +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE 0x20000000 /* NAND flash */ #ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_NAND_BASE 0x80000000 +#define CFG_SYS_NAND_BASE 0x80000000 /* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +#define CFG_SYS_NAND_MASK_ALE (1 << 21) /* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CFG_SYS_NAND_MASK_CLE (1 << 22) #endif /* SPL */ diff --git a/include/configs/sama7g5ek.h b/include/configs/sama7g5ek.h index 3f905bf2d77..59f13edbc85 100644 --- a/include/configs/sama7g5ek.h +++ b/include/configs/sama7g5ek.h @@ -9,10 +9,10 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 +#define CFG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x60000000 -#define CONFIG_SYS_SDRAM_SIZE 0x20000000 +#define CFG_SYS_SDRAM_BASE 0x60000000 +#define CFG_SYS_SDRAM_SIZE 0x20000000 #endif diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index 0dcb2ebc316..8d9af7f088d 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -6,22 +6,16 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_IO_TRACE - #define CONFIG_MALLOC_F_ADDR 0x0010000 /* Size of our emulated memory */ #define SB_CONCAT(x, y) x ## y #define SB_TO_UL(s) SB_CONCAT(s, UL) -#define CONFIG_SYS_SDRAM_BASE 0 -#define CONFIG_SYS_SDRAM_SIZE \ +#define CFG_SYS_SDRAM_BASE 0 +#define CFG_SYS_SDRAM_SIZE \ (SB_TO_UL(CONFIG_SANDBOX_RAM_SIZE_MB) << 20) -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ +#define CFG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 115200} -#ifndef SANDBOX_NO_SDL -#define CONFIG_SANDBOX_SDL -#endif - #endif diff --git a/include/configs/sdm845.h b/include/configs/sdm845.h index af5fe27e68b..f7cdd5a1956 100644 --- a/include/configs/sdm845.h +++ b/include/configs/sdm845.h @@ -11,7 +11,7 @@ #include <linux/sizes.h> #include <asm/arch/sysmap-sdm845.h> -#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 } +#define CFG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 } #define CONFIG_EXTRA_ENV_SETTINGS \ "bootm_size=0x4000000\0" \ diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index c7f03a1e754..f272fe9bf8f 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -9,12 +9,6 @@ #include <linux/sizes.h> -/* LP0 suspend / resume */ -#define CONFIG_TEGRA_LP0 -#define CONFIG_TEGRA_PMU -#define CONFIG_TPS6586X_POWER -#define CONFIG_TEGRA_CLOCK_SCALING - #include "tegra20-common.h" /* High-level configuration options */ @@ -22,7 +16,7 @@ /* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTD -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE /* Environment in eMMC, at the end of 2nd "boot sector" */ diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index 87da5e4232c..5a001716fb0 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -33,22 +33,21 @@ /* Physical Memory Map */ #define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */ -#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_DRAM_1 /* Platform/Board specific defs */ -#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ +#define CFG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ /* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_CLK (48000000) -#define CONFIG_SYS_NS16550_COM1 0x44e09000 -#define CONFIG_SYS_NS16550_COM4 0x481a6000 +#define CFG_SYS_NS16550_CLK (48000000) +#define CFG_SYS_NS16550_COM1 0x44e09000 +#define CFG_SYS_NS16550_COM4 0x481a6000 /* I2C Configuration */ /* Defines for SPL */ -#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ +#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 10, 11, 12, 13, 14, 15, 16, 17, \ 18, 19, 20, 21, 22, 23, 24, 25, \ 26, 27, 28, 29, 30, 31, 32, 33, \ @@ -56,14 +55,10 @@ 42, 43, 44, 45, 46, 47, 48, 49, \ 50, 51, 52, 53, 54, 55, 56, 57, } -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 14 +#define CFG_SYS_NAND_ECCSIZE 512 +#define CFG_SYS_NAND_ECCBYTES 14 -#define CONFIG_SYS_NAND_ECCSTEPS 4 -#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \ - CONFIG_SYS_NAND_ECCSTEPS) - -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE /* * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM @@ -365,7 +360,7 @@ */ -#define CONFIG_SYS_NAND_BASE (0x08000000) /* physical address */ +#define CFG_SYS_NAND_BASE (0x08000000) /* physical address */ /* to access nand at */ /* CS0 */ #endif diff --git a/include/configs/sifive-unleashed.h b/include/configs/sifive-unleashed.h index 2e5592cf94d..5ad2124bdda 100644 --- a/include/configs/sifive-unleashed.h +++ b/include/configs/sifive-unleashed.h @@ -11,7 +11,7 @@ #include <linux/sizes.h> -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 diff --git a/include/configs/sifive-unmatched.h b/include/configs/sifive-unmatched.h index 85fab927195..f4b1a16019e 100644 --- a/include/configs/sifive-unmatched.h +++ b/include/configs/sifive-unmatched.h @@ -11,7 +11,7 @@ #include <linux/sizes.h> -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 diff --git a/include/configs/sipeed-maix.h b/include/configs/sipeed-maix.h index 7159fc35d52..974531ea0d8 100644 --- a/include/configs/sipeed-maix.h +++ b/include/configs/sipeed-maix.h @@ -8,8 +8,8 @@ #include <linux/sizes.h> -#define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_SDRAM_SIZE SZ_8M +#define CFG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_SIZE SZ_8M #ifndef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h index a77215d19be..b988b96e58d 100644 --- a/include/configs/smartweb.h +++ b/include/configs/smartweb.h @@ -36,8 +36,8 @@ */ /* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ +#define CFG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432MHz crystal */ /* misc settings */ @@ -45,8 +45,8 @@ * SDRAM: 1 bank, 64 MB, base address 0x20000000 * Already initialized before u-boot gets started. */ -#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 -#define CONFIG_SYS_SDRAM_SIZE (64 * SZ_1M) +#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1 +#define CFG_SYS_SDRAM_SIZE (64 * SZ_1M) /* * Perform a SDRAM Memtest from the start of SDRAM @@ -54,21 +54,16 @@ */ /* NAND flash settings */ -#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 -#define CONFIG_SYS_NAND_DBW_8 -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13 +#define CFG_SYS_NAND_BASE ATMEL_BASE_CS3 +#define CFG_SYS_NAND_MASK_ALE (1 << 21) +#define CFG_SYS_NAND_MASK_CLE (1 << 22) +#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 +#define CFG_SYS_NAND_READY_PIN AT91_PIN_PC13 /* serial console */ #define CONFIG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID ATMEL_ID_SYS -/* USB DFU support */ - -#define CONFIG_USB_GADGET_AT91 - /* DFU class support */ #define DFU_MANIFEST_POLL_TIMEOUT 25000 @@ -88,28 +83,26 @@ * leaving the correct space for initial global data structure above that * address while providing maximum stack area below. */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 +#define CFG_SYS_INIT_RAM_SIZE 0x1000 +#define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 /* Defines for SPL */ -#define CONFIG_SYS_NAND_ENABLE_PIN_SPL (2*32 + 14) -#define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE +#define CFG_SYS_NAND_U_BOOT_SIZE SZ_512K +#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE -#define CONFIG_SYS_NAND_SIZE (SZ_256M) -#define CONFIG_SYS_NAND_ECCSIZE 256 -#define CONFIG_SYS_NAND_ECCBYTES 3 -#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ +#define CFG_SYS_NAND_ECCSIZE 256 +#define CFG_SYS_NAND_ECCBYTES 3 +#define CFG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ 48, 49, 50, 51, 52, 53, 54, 55, \ 56, 57, 58, 59, 60, 61, 62, 63, } -#define CONFIG_SYS_MASTER_CLOCK (198656000/2) +#define CFG_SYS_MASTER_CLOCK (198656000/2) #define AT91_PLL_LOCK_TIMEOUT 1000000 -#define CONFIG_SYS_AT91_PLLA 0x2060bf09 -#define CONFIG_SYS_MCKR 0x100 -#define CONFIG_SYS_MCKR_CSS (0x02 | CONFIG_SYS_MCKR) -#define CONFIG_SYS_AT91_PLLB 0x10483f0e +#define CFG_SYS_AT91_PLLA 0x2060bf09 +#define CFG_SYS_MCKR 0x100 +#define CFG_SYS_MCKR_CSS (0x02 | CFG_SYS_MCKR) +#define CFG_SYS_AT91_PLLB 0x10483f0e #endif /* __CONFIG_H */ diff --git a/include/configs/smdk5420.h b/include/configs/smdk5420.h index 12c2e1f6159..0392530c0ad 100644 --- a/include/configs/smdk5420.h +++ b/include/configs/smdk5420.h @@ -14,7 +14,7 @@ #define CONFIG_SMDK5420 /* which is in a SMDK5420 */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_BASE 0x20000000 /* DRAM Memory Banks */ #define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h index ba562b23780..ffa1a1fcb0e 100644 --- a/include/configs/smdkc100.h +++ b/include/configs/smdkc100.h @@ -16,7 +16,7 @@ /* input clock of PLL: SMDKC100 has 12MHz input clock */ /* DRAM Base */ -#define CONFIG_SYS_SDRAM_BASE 0x30000000 +#define CFG_SYS_SDRAM_BASE 0x30000000 /* Text Base */ @@ -77,7 +77,7 @@ */ /* SMDKC100 has 1 banks of DRAM, we use only one in U-Boot */ -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE /* SDRAM Bank #1 */ #define PHYS_SDRAM_1_SIZE (128 << 20) /* 0x8000000, 128 MB Bank #1 */ /*----------------------------------------------------------------------- @@ -88,7 +88,7 @@ * Boot configuration */ -#define CONFIG_SYS_ONENAND_BASE 0xE7100000 +#define CFG_SYS_ONENAND_BASE 0xE7100000 /* * Ethernet Contoller driver diff --git a/include/configs/smdkv310.h b/include/configs/smdkv310.h index 0b1f0c5f54c..af0c8200fc2 100644 --- a/include/configs/smdkv310.h +++ b/include/configs/smdkv310.h @@ -11,7 +11,7 @@ #include "exynos4-common.h" /* High Level Configuration Options */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 /* Handling Sleep Mode*/ #define S5P_CHECK_SLEEP 0x00000BAD @@ -23,13 +23,13 @@ /* SMDKV310 has 4 bank of DRAM */ #define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) +#define PHYS_SDRAM_2 (CFG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) #define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_3 (CFG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_4 (CFG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE /* FLASH and environment organization */ diff --git a/include/configs/smegw01.h b/include/configs/smegw01.h index faa13c65216..14f9cf56028 100644 --- a/include/configs/smegw01.h +++ b/include/configs/smegw01.h @@ -38,8 +38,8 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE #endif diff --git a/include/configs/snapper9g45.h b/include/configs/snapper9g45.h index c56fb378312..b7aa49ce435 100644 --- a/include/configs/snapper9g45.h +++ b/include/configs/snapper9g45.h @@ -15,27 +15,25 @@ #include <linux/sizes.h> /* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 +#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* CPU */ /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS6 -#define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024) /* 64MB */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM +#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS6 +#define CFG_SYS_SDRAM_SIZE (128 * 1024 * 1024) /* 64MB */ +#define CFG_SYS_INIT_RAM_SIZE 0x1000 +#define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM /* Mem test settings */ /* NAND Flash */ -#define CONFIG_SYS_NAND_ECC_BASE ATMEL_BASE_ECC -#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 -#define CONFIG_SYS_NAND_DBW_8 -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* AD21 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* AD22 */ -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8 +#define CFG_SYS_NAND_BASE ATMEL_BASE_CS3 +#define CFG_SYS_NAND_MASK_ALE (1 << 21) /* AD21 */ +#define CFG_SYS_NAND_MASK_CLE (1 << 22) /* AD22 */ +#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 +#define CFG_SYS_NAND_READY_PIN AT91_PIN_PC8 /* UARTs/Serial console */ diff --git a/include/configs/sniper.h b/include/configs/sniper.h index 0187fca5f0d..afca7e18e9b 100644 --- a/include/configs/sniper.h +++ b/include/configs/sniper.h @@ -15,7 +15,7 @@ * Clocks */ -#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 +#define CFG_SYS_TIMERBASE OMAP34XX_GPT2 #define V_NS16550_CLK 48000000 #define V_OSCK 26000000 @@ -32,7 +32,7 @@ * Memory */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 /* * I2C @@ -52,15 +52,10 @@ * Serial */ -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#endif - -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK -#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 +#define CFG_SYS_NS16550_CLK V_NS16550_CLK +#define CFG_SYS_NS16550_COM3 OMAP34XX_UART3 -#define CONFIG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, \ +#define CFG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, \ 115200 } /* diff --git a/include/configs/socfpga_arria10_socdk.h b/include/configs/socfpga_arria10_socdk.h index f712928d3c8..35c777b774e 100644 --- a/include/configs/socfpga_arria10_socdk.h +++ b/include/configs/socfpga_arria10_socdk.h @@ -18,8 +18,7 @@ /* * Serial / UART configurations */ -#define CONFIG_SYS_NS16550_MEM32 -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} +#define CFG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} /* * L4 OSC1 Timer 0 diff --git a/include/configs/socfpga_arria5_secu1.h b/include/configs/socfpga_arria5_secu1.h index 261ae56c1dc..29b4b22b398 100644 --- a/include/configs/socfpga_arria5_secu1.h +++ b/include/configs/socfpga_arria5_secu1.h @@ -10,7 +10,7 @@ #include <linux/stringify.h> /* Eternal oscillator */ -#define CONFIG_SYS_TIMER_RATE 40000000 +#define CFG_SYS_TIMER_RATE 40000000 /* Memory configurations */ #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512MiB on SECU1 */ @@ -21,7 +21,7 @@ * the last two bytes of the 128 bytes large NVRAM in the * RTC which begin at address 0x20 */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CFG_SYS_I2C_RTC_ADDR 0x68 /* Environment settings */ diff --git a/include/configs/socfpga_chameleonv3.h b/include/configs/socfpga_chameleonv3.h index 75d2081fac8..aa13878177e 100644 --- a/include/configs/socfpga_chameleonv3.h +++ b/include/configs/socfpga_chameleonv3.h @@ -17,8 +17,7 @@ /* * Serial / UART configurations */ -#define CONFIG_SYS_NS16550_MEM32 -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} +#define CFG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} #define CONFIG_EXTRA_ENV_SETTINGS \ "autoload=no\0" \ diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 704a7141d7e..bbbdea6664c 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -12,12 +12,12 @@ */ #define PHYS_SDRAM_1 0x0 #if defined(CONFIG_TARGET_SOCFPGA_GEN5) -#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 -#define CONFIG_SYS_INIT_RAM_SIZE SOCFPGA_PHYS_OCRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR 0xFFFF0000 +#define CFG_SYS_INIT_RAM_SIZE SOCFPGA_PHYS_OCRAM_SIZE #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) -#define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000 +#define CFG_SYS_INIT_RAM_ADDR 0xFFE00000 /* SPL memory allocation configuration, this is for FAT implementation */ -#define CONFIG_SYS_INIT_RAM_SIZE (SOCFPGA_PHYS_OCRAM_SIZE - \ +#define CFG_SYS_INIT_RAM_SIZE (SOCFPGA_PHYS_OCRAM_SIZE - \ CONFIG_SYS_SPL_MALLOC_SIZE) #endif @@ -27,9 +27,9 @@ * at this address to not overwrite the bootcounter by checking, if the * bootcounter address is located in the internal SRAM. */ -#if ((CONFIG_SYS_BOOTCOUNT_ADDR > CONFIG_SYS_INIT_RAM_ADDR) && \ - (CONFIG_SYS_BOOTCOUNT_ADDR < (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE))) +#if ((CONFIG_SYS_BOOTCOUNT_ADDR > CFG_SYS_INIT_RAM_ADDR) && \ + (CONFIG_SYS_BOOTCOUNT_ADDR < (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE))) #endif /* @@ -38,7 +38,7 @@ * in U-Boot pre-reloc is higher than in SPL. */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 /* * U-Boot general configurations @@ -48,17 +48,16 @@ /* * Cache */ -#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS +#define CFG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS /* * L4 OSC1 Timer 0 */ #ifndef CONFIG_TIMER -#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS -#define CONFIG_SYS_TIMER_COUNTS_DOWN -#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) -#ifndef CONFIG_SYS_TIMER_RATE -#define CONFIG_SYS_TIMER_RATE 25000000 +#define CFG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS +#define CFG_SYS_TIMER_COUNTER (CFG_SYS_TIMERBASE + 0x4) +#ifndef CFG_SYS_TIMER_RATE +#define CFG_SYS_TIMER_RATE 25000000 #endif #endif @@ -71,8 +70,8 @@ * NAND Support */ #ifdef CONFIG_NAND_DENALI -#define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS -#define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS +#define CFG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS +#define CFG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS #endif /* diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index 86cc3771ba5..47089f312d2 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -26,8 +26,8 @@ /* * U-Boot run time memory configurations */ -#define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x40000 +#define CFG_SYS_INIT_RAM_ADDR 0xFFE00000 +#define CFG_SYS_INIT_RAM_SIZE 0x40000 /* * U-Boot environment configurations @@ -70,13 +70,12 @@ */ #define PHYS_SDRAM_1 0x0 #define PHYS_SDRAM_1_SIZE (1 * 1024 * 1024 * 1024) -#define CONFIG_SYS_SDRAM_BASE 0 +#define CFG_SYS_SDRAM_BASE 0 /* * Serial / UART configurations */ -#define CONFIG_SYS_NS16550_CLK 100000000 -#define CONFIG_SYS_NS16550_MEM32 +#define CFG_SYS_NS16550_CLK 100000000 /* * SDMMC configurations diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 3c978f5ee4e..95393d3ab25 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -42,20 +42,19 @@ */ #define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ +#define CFG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ -#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ +#undef CFG_SYS_DRAM_TEST /* memory test, takes time */ -#define CONFIG_SYS_CCSRBAR 0xE0000000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR +#define CFG_SYS_CCSRBAR 0xE0000000 +#define CFG_SYS_CCSRBAR_PHYS_LOW CFG_SYS_CCSRBAR /* DDR Setup */ -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE #define CONFIG_VERY_BIG_RAM /* I2C addresses of SPD EEPROMs */ @@ -63,58 +62,54 @@ /* Hardcoded values, to use instead of SPD */ -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 -#define CONFIG_SYS_DDR_TIMING_0 0x00260802 -#define CONFIG_SYS_DDR_TIMING_1 0x3935D322 -#define CONFIG_SYS_DDR_TIMING_2 0x14904CC8 -#define CONFIG_SYS_DDR_MODE 0x00480432 -#define CONFIG_SYS_DDR_INTERVAL 0x030C0100 -#define CONFIG_SYS_DDR_CONFIG_2 0x04400000 -#define CONFIG_SYS_DDR_CONFIG 0xC3008000 -#define CONFIG_SYS_DDR_CLK_CONTROL 0x03800000 -#define CONFIG_SYS_SDRAM_SIZE 256 /* in Megs */ +#define CFG_SYS_DDR_CS0_BNDS 0x0000000f +#define CFG_SYS_DDR_CS0_CONFIG 0x80010102 +#define CFG_SYS_DDR_TIMING_0 0x00260802 +#define CFG_SYS_DDR_TIMING_1 0x3935D322 +#define CFG_SYS_DDR_TIMING_2 0x14904CC8 +#define CFG_SYS_DDR_MODE 0x00480432 +#define CFG_SYS_DDR_INTERVAL 0x030C0100 +#define CFG_SYS_DDR_CONFIG_2 0x04400000 +#define CFG_SYS_DDR_CONFIG 0xC3008000 +#define CFG_SYS_DDR_CLK_CONTROL 0x03800000 +#define CFG_SYS_SDRAM_SIZE 256 /* in Megs */ /* * Flash on the LocalBus */ -#define CONFIG_SYS_FLASH0 0xFE000000 -#define CONFIG_SYS_FLASH1 0xFC000000 -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 } +#define CFG_SYS_FLASH0 0xFE000000 +#define CFG_SYS_FLASH1 0xFC000000 +#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH1, CFG_SYS_FLASH0 } -#define CONFIG_SYS_LBC_FLASH_BASE CONFIG_SYS_FLASH1 /* Localbus flash start */ -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_LBC_FLASH_BASE /* start of FLASH */ +#define CFG_SYS_LBC_FLASH_BASE CFG_SYS_FLASH1 /* Localbus flash start */ +#define CFG_SYS_FLASH_BASE CFG_SYS_LBC_FLASH_BASE /* start of FLASH */ -#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ -#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ -#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/ +#define CFG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ +#define CFG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ +#define CFG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ +#define CFG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/ -#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size used area in RAM*/ +#define CFG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ +#define CFG_SYS_INIT_RAM_SIZE 0x4000 /* Size used area in RAM*/ -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /* FPGA and NAND */ -#define CONFIG_SYS_FPGA_BASE 0xc0000000 -#define CONFIG_SYS_FPGA_SIZE 0x00100000 /* 1 MB */ +#define CFG_SYS_FPGA_BASE 0xc0000000 +#define CFG_SYS_FPGA_SIZE 0x00100000 /* 1 MB */ -#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_FPGA_BASE + 0x70) +#define CFG_SYS_NAND_BASE (CFG_SYS_FPGA_BASE + 0x70) /* LIME GDC */ -#define CONFIG_SYS_LIME_BASE 0xc8000000 +#define CFG_SYS_LIME_BASE 0xc8000000 /* * General PCI * Memory space is mapped 1-1. */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE -#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_BASE 0xE2000000 -#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE -#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */ +#define CFG_SYS_PCI1_MEM_PHYS 0x80000000 +#define CFG_SYS_PCI1_IO_PHYS 0xE2000000 #define CONFIG_TSEC1 1 #define CONFIG_TSEC1_NAME "TSEC0" @@ -141,7 +136,7 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CFG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/somlabs_visionsom_6ull.h b/include/configs/somlabs_visionsom_6ull.h index 49672dfe7c3..de0f48b79a1 100644 --- a/include/configs/somlabs_visionsom_6ull.h +++ b/include/configs/somlabs_visionsom_6ull.h @@ -13,10 +13,6 @@ #include "mx6_common.h" #include <asm/mach-imx/gpio.h> -/* SPL options */ -#include "imx6_spl.h" - - /* MMC Configs */ #ifdef CONFIG_FSL_USDHC #define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR @@ -57,9 +53,9 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* environment organization */ diff --git a/include/configs/stemmy.h b/include/configs/stemmy.h index 3c70856fc70..a5987c5e17a 100644 --- a/include/configs/stemmy.h +++ b/include/configs/stemmy.h @@ -15,7 +15,7 @@ */ /* FIXME: This should be loaded from device tree... */ -#define CONFIG_SYS_PL310_BASE 0xa0412000 +#define CFG_SYS_PL310_BASE 0xa0412000 /* Linux does not boot if FDT / initrd is loaded to end of RAM */ #define BOOT_ENV \ diff --git a/include/configs/stih410-b2260.h b/include/configs/stih410-b2260.h index 1e966a23227..9294d57ca84 100644 --- a/include/configs/stih410-b2260.h +++ b/include/configs/stih410-b2260.h @@ -11,10 +11,10 @@ /* ram memory-related information */ #define PHYS_SDRAM_1 0x40000000 -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define PHYS_SDRAM_1_SIZE 0x3E000000 -#define CONFIG_SYS_HZ_CLOCK 750000000 /* 750 MHz */ +#define CFG_SYS_HZ_CLOCK 750000000 /* 750 MHz */ /* Environment */ @@ -22,7 +22,7 @@ * For booting Linux, use the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ SZ_256M +#define CFG_SYS_BOOTMAPSZ SZ_256M #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ diff --git a/include/configs/stm32f429-discovery.h b/include/configs/stm32f429-discovery.h index 51f69010b17..afd7d50428b 100644 --- a/include/configs/stm32f429-discovery.h +++ b/include/configs/stm32f429-discovery.h @@ -7,13 +7,13 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_FLASH_BASE 0x08000000 +#define CFG_SYS_FLASH_BASE 0x08000000 /* * Configuration of the external SDRAM memory */ -#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ +#define CFG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ #define CONFIG_EXTRA_ENV_SETTINGS \ "bootargs_romfs=uclinux.physaddr=0x08180000 root=/dev/mtdblock0\0" \ diff --git a/include/configs/stm32f429-evaluation.h b/include/configs/stm32f429-evaluation.h index 221b7abe1ad..c8aad47966f 100644 --- a/include/configs/stm32f429-evaluation.h +++ b/include/configs/stm32f429-evaluation.h @@ -10,15 +10,15 @@ #include <linux/sizes.h> /* For booting Linux, use the first 16MB of memory */ -#define CONFIG_SYS_BOOTMAPSZ SZ_16M +#define CFG_SYS_BOOTMAPSZ SZ_16M -#define CONFIG_SYS_FLASH_BASE 0x08000000 +#define CFG_SYS_FLASH_BASE 0x08000000 /* * Configuration of the external SDRAM memory */ -#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ +#define CFG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) diff --git a/include/configs/stm32f469-discovery.h b/include/configs/stm32f469-discovery.h index 55e70ce9250..573a6b17956 100644 --- a/include/configs/stm32f469-discovery.h +++ b/include/configs/stm32f469-discovery.h @@ -10,15 +10,15 @@ #include <linux/sizes.h> /* For booting Linux, use the first 12MB of memory */ -#define CONFIG_SYS_BOOTMAPSZ SZ_8M + SZ_4M +#define CFG_SYS_BOOTMAPSZ SZ_8M + SZ_4M -#define CONFIG_SYS_FLASH_BASE 0x08000000 +#define CFG_SYS_FLASH_BASE 0x08000000 /* * Configuration of the external SDRAM memory */ -#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ +#define CFG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h index c7d6d9368a2..14e883a3589 100644 --- a/include/configs/stm32f746-disco.h +++ b/include/configs/stm32f746-disco.h @@ -10,15 +10,15 @@ #include <linux/sizes.h> /* For booting Linux, use the first 6MB of memory */ -#define CONFIG_SYS_BOOTMAPSZ SZ_4M + SZ_2M +#define CFG_SYS_BOOTMAPSZ SZ_4M + SZ_2M -#define CONFIG_SYS_FLASH_BASE 0x08000000 +#define CFG_SYS_FLASH_BASE 0x08000000 /* * Configuration of the external SDRAM memory */ -#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ +#define CFG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) @@ -33,7 +33,7 @@ "ramdisk_addr_r=0xC0438000\0" \ BOOTENV -#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + \ +#define CFG_SYS_UBOOT_BASE (CFG_SYS_FLASH_BASE + \ CONFIG_SPL_PAD_TO) /* For splashcreen */ diff --git a/include/configs/stm32h743-disco.h b/include/configs/stm32h743-disco.h index f959fcf26f3..67e6a3a19d2 100644 --- a/include/configs/stm32h743-disco.h +++ b/include/configs/stm32h743-disco.h @@ -11,11 +11,11 @@ #include <linux/sizes.h> /* For booting Linux, use the first 16MB of memory */ -#define CONFIG_SYS_BOOTMAPSZ SZ_16M +#define CFG_SYS_BOOTMAPSZ SZ_16M -#define CONFIG_SYS_FLASH_BASE 0x08000000 +#define CFG_SYS_FLASH_BASE 0x08000000 -#define CONFIG_SYS_HZ_CLOCK 1000000 +#define CFG_SYS_HZ_CLOCK 1000000 #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) diff --git a/include/configs/stm32h743-eval.h b/include/configs/stm32h743-eval.h index c8688e9ca7b..4786eb001bc 100644 --- a/include/configs/stm32h743-eval.h +++ b/include/configs/stm32h743-eval.h @@ -11,11 +11,11 @@ #include <linux/sizes.h> /* For booting Linux, use the first 16MB of memory */ -#define CONFIG_SYS_BOOTMAPSZ SZ_16M +#define CFG_SYS_BOOTMAPSZ SZ_16M -#define CONFIG_SYS_FLASH_BASE 0x08000000 +#define CFG_SYS_FLASH_BASE 0x08000000 -#define CONFIG_SYS_HZ_CLOCK 1000000 +#define CFG_SYS_HZ_CLOCK 1000000 #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) diff --git a/include/configs/stm32h750-art-pi.h b/include/configs/stm32h750-art-pi.h index f7fa8c51d8e..e667fe6f6ac 100644 --- a/include/configs/stm32h750-art-pi.h +++ b/include/configs/stm32h750-art-pi.h @@ -11,11 +11,11 @@ #include <linux/sizes.h> /* For booting Linux, use the first 16MB of memory */ -#define CONFIG_SYS_BOOTMAPSZ (SZ_16M + SZ_8M) +#define CFG_SYS_BOOTMAPSZ (SZ_16M + SZ_8M) -#define CONFIG_SYS_FLASH_BASE 0x90000000 +#define CFG_SYS_FLASH_BASE 0x90000000 -#define CONFIG_SYS_HZ_CLOCK 1000000 +#define CFG_SYS_HZ_CLOCK 1000000 #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) diff --git a/include/configs/stm32mp13_common.h b/include/configs/stm32mp13_common.h index 07a5bfc8a86..c259a616133 100644 --- a/include/configs/stm32mp13_common.h +++ b/include/configs/stm32mp13_common.h @@ -13,13 +13,13 @@ /* * Configuration of the external SRAM memory used by U-Boot */ -#define CONFIG_SYS_SDRAM_BASE STM32_DDR_BASE +#define CFG_SYS_SDRAM_BASE STM32_DDR_BASE /* * For booting Linux, use the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ SZ_256M +#define CFG_SYS_BOOTMAPSZ SZ_256M /* NAND support */ diff --git a/include/configs/stm32mp13_st_common.h b/include/configs/stm32mp13_st_common.h index c51022b40d2..ad8126f6103 100644 --- a/include/configs/stm32mp13_st_common.h +++ b/include/configs/stm32mp13_st_common.h @@ -15,7 +15,7 @@ #include <configs/stm32mp13_common.h> /* uart with on-board st-link */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ +#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ 230400, 460800, 921600, \ 1000000, 2000000, 4000000} diff --git a/include/configs/stm32mp15_common.h b/include/configs/stm32mp15_common.h index b809f9322ad..c9cfadd9ce0 100644 --- a/include/configs/stm32mp15_common.h +++ b/include/configs/stm32mp15_common.h @@ -13,13 +13,13 @@ /* * Configuration of the external SRAM memory used by U-Boot */ -#define CONFIG_SYS_SDRAM_BASE STM32_DDR_BASE +#define CFG_SYS_SDRAM_BASE STM32_DDR_BASE /* * For booting Linux, use the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ SZ_256M +#define CFG_SYS_BOOTMAPSZ SZ_256M /* NAND support */ diff --git a/include/configs/stm32mp15_st_common.h b/include/configs/stm32mp15_st_common.h index 6bdc286cfca..38b5aa7319c 100644 --- a/include/configs/stm32mp15_st_common.h +++ b/include/configs/stm32mp15_st_common.h @@ -14,7 +14,7 @@ #include <configs/stm32mp15_common.h> /* uart with on-board st-link */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ +#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ 230400, 460800, 921600, \ 1000000, 2000000 } diff --git a/include/configs/stmark2.h b/include/configs/stmark2.h index ba49075ce06..faff8d6ed6d 100644 --- a/include/configs/stmark2.h +++ b/include/configs/stmark2.h @@ -10,7 +10,7 @@ #define CONFIG_HOSTNAME "stmark2" -#define CONFIG_SYS_UART_PORT 0 +#define CFG_SYS_UART_PORT 0 #define LDS_BOARD_TEXT \ board/sysam/stmark2/sbf_dram_init.o (.text*) @@ -34,34 +34,34 @@ "sf write ${loadaddr} 0x00800000 ${filesize}\0" \ "" -#define CONFIG_SYS_SBFHDR_SIZE 0x7 +#define CFG_SYS_SBFHDR_SIZE 0x7 /* Input, PCI, Flexbus, and VCO */ #define CONFIG_PRAM 2048 /* 2048 KB */ -#define CONFIG_SYS_MBAR 0xFC000000 +#define CFG_SYS_MBAR 0xFC000000 /* * Definitions for initial stack pointer and data area (in internal SRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 +#define CFG_SYS_INIT_RAM_ADDR 0x80000000 /* End of used area in internal SRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 -#define CONFIG_SYS_INIT_RAM_CTRL 0x221 -#define CONFIG_SYS_INIT_SP_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \ +#define CFG_SYS_INIT_RAM_SIZE 0x10000 +#define CFG_SYS_INIT_RAM_CTRL 0x221 +#define CFG_SYS_INIT_SP_OFFSET ((CFG_SYS_INIT_RAM_SIZE - \ GENERATED_GBL_DATA_SIZE) - 32) -#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) +#define CFG_SYS_SBFHDR_DATA_OFFSET (CFG_SYS_INIT_RAM_SIZE - 32) /* * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */ +#define CFG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */ -#define CONFIG_SYS_DRAM_TEST +#define CFG_SYS_DRAM_TEST #if defined(CONFIG_CF_SBF) #define CONFIG_SERIAL_BOOT @@ -75,30 +75,30 @@ * the maximum mapped by the Linux kernel during initialization ?? */ /* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \ - (CONFIG_SYS_SDRAM_SIZE << 20)) +#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + \ + (CFG_SYS_SDRAM_SIZE << 20)) /* Configuration for environment * Environment is embedded in u-boot in the second sector of the flash */ /* Cache Configuration */ -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) -#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) -#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ +#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 4) +#define CFG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) +#define CFG_SYS_DCACHE_INV (CF_CACR_DCINVA) +#define CFG_SYS_CACHE_ACR2 (CFG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ +#define CFG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ CF_CACR_ICINVA | CF_CACR_EUSP) -#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ +#define CFG_SYS_CACHE_DCACR ((CFG_SYS_CACHE_ICACR | \ CF_CACR_DEC | CF_CACR_DDCM_P | \ CF_CACR_DCINVA) & ~CF_CACR_ICINVA) -#define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 12) +#define CACR_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 12) #endif /* __STMARK2_CONFIG_H */ diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h index 567aa1ffe43..7eadb6d421e 100644 --- a/include/configs/stv0991.h +++ b/include/configs/stv0991.h @@ -6,18 +6,18 @@ #ifndef __CONFIG_STV0991_H #define __CONFIG_STV0991_H -#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH +#define CFG_SYS_EXCEPTION_VECTORS_HIGH /* ram memory-related information */ #define PHYS_SDRAM_1 0x00000000 -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define PHYS_SDRAM_1_SIZE 0x00198000 /* user interface */ /* MISC */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 -#define CONFIG_SYS_INIT_RAM_ADDR 0x00190000 +#define CFG_SYS_INIT_RAM_SIZE 0x8000 +#define CFG_SYS_INIT_RAM_ADDR 0x00190000 /* U-Boot Load Address */ /* Misc configuration */ diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 720768629d6..1677aafad03 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -16,21 +16,19 @@ #include <linux/stringify.h> /* Serial & console */ -#define CONFIG_SYS_NS16550_SERIAL /* ns16550 reg in the low bits of cpu reg */ #ifdef CONFIG_MACH_SUNIV /* suniv doesn't have apb2 and uart is connected to apb1 */ -#define CONFIG_SYS_NS16550_CLK 100000000 +#define CFG_SYS_NS16550_CLK 100000000 #else -#define CONFIG_SYS_NS16550_CLK 24000000 +#define CFG_SYS_NS16550_CLK 24000000 #endif #ifndef CONFIG_DM_SERIAL -# define CONFIG_SYS_NS16550_REG_SIZE -4 -# define CONFIG_SYS_NS16550_COM1 SUNXI_UART0_BASE -# define CONFIG_SYS_NS16550_COM2 SUNXI_UART1_BASE -# define CONFIG_SYS_NS16550_COM3 SUNXI_UART2_BASE -# define CONFIG_SYS_NS16550_COM4 SUNXI_UART3_BASE -# define CONFIG_SYS_NS16550_COM5 SUNXI_R_UART_BASE +# define CFG_SYS_NS16550_COM1 SUNXI_UART0_BASE +# define CFG_SYS_NS16550_COM2 SUNXI_UART1_BASE +# define CFG_SYS_NS16550_COM3 SUNXI_UART2_BASE +# define CFG_SYS_NS16550_COM4 SUNXI_UART3_BASE +# define CFG_SYS_NS16550_COM5 SUNXI_R_UART_BASE #endif /* CPU */ @@ -44,13 +42,13 @@ */ #ifdef CONFIG_MACH_SUN9I #define SDRAM_OFFSET(x) 0x2##x -#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_BASE 0x20000000 #elif defined(CONFIG_MACH_SUNIV) #define SDRAM_OFFSET(x) 0x8##x -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #else #define SDRAM_OFFSET(x) 0x4##x -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 /* V3s do not have enough memory to place code at 0x4a000000 */ #endif @@ -64,17 +62,13 @@ * is known yet. * H6 has SRAM A1 at 0x00020000. */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SUNXI_SRAM_ADDRESS +#define CFG_SYS_INIT_RAM_ADDR CONFIG_SUNXI_SRAM_ADDRESS /* FIXME: this may be larger on some SoCs */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */ +#define CFG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */ -#define PHYS_SDRAM_0 CONFIG_SYS_SDRAM_BASE +#define PHYS_SDRAM_0 CFG_SYS_SDRAM_BASE #define PHYS_SDRAM_0_SIZE 0x80000000 /* 2 GiB */ -#ifdef CONFIG_NAND_SUNXI -#define CONFIG_SYS_NAND_MAX_ECCPOS 1664 -#endif - /* mmc config */ #define CONFIG_MMC_SUNXI_SLOT 0 diff --git a/include/configs/synquacer.h b/include/configs/synquacer.h index 63d897d090a..69926890010 100644 --- a/include/configs/synquacer.h +++ b/include/configs/synquacer.h @@ -6,12 +6,12 @@ #define __CONFIG_H /* Timers for fasp(TIMCLK) */ -#define CONFIG_SYS_TIMERBASE 0x31080000 /* AP Timer 1 (ARM-SP804) */ +#define CFG_SYS_TIMERBASE 0x31080000 /* AP Timer 1 (ARM-SP804) */ /* * SDRAM (for initialize) */ -#define CONFIG_SYS_SDRAM_BASE (0x80000000) /* Start address of DDR3 */ +#define CFG_SYS_SDRAM_BASE (0x80000000) /* Start address of DDR3 */ #define PHYS_SDRAM_SIZE (0x7c000000) /* Default size (2GB - Secure memory) */ #define CONFIG_VERY_BIG_RAM /* SynQuacer supports up to 64GB */ @@ -28,7 +28,7 @@ */ /* RTC */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 +#define CFG_SYS_I2C_RTC_ADDR 0x51 /* Serial (pl011) */ #define UART_CLK (62500000) @@ -36,8 +36,8 @@ #define CONFIG_PL01x_PORTS {(void *)(0x2a400000)} /* Support MTD */ -#define CONFIG_SYS_FLASH_BASE (0x08000000) -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} +#define CFG_SYS_FLASH_BASE (0x08000000) +#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE} /* Since U-Boot 64bit PCIe support is limited, disable 64bit MMIO support */ diff --git a/include/configs/taurus.h b/include/configs/taurus.h index 45780d9a4ea..30f84255820 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -29,8 +29,8 @@ */ /* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* main clock xtal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ +#define CFG_SYS_AT91_MAIN_CLOCK 18432000 /* main clock xtal */ /* Misc CPU related */ @@ -41,32 +41,27 @@ * SDRAM: 1 bank, min 32, max 128 MB * Initialized before u-boot gets started. */ -#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 -#define CONFIG_SYS_SDRAM_SIZE (128 * SZ_1M) +#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1 +#define CFG_SYS_SDRAM_SIZE (128 * SZ_1M) /* * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM, * leaving the correct space for initial global data structure above * that address while providing maximum stack area below. */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 +#define CFG_SYS_INIT_RAM_SIZE 0x1000 +#define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 /* NAND flash */ #ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 -#define CONFIG_SYS_NAND_DBW_8 -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13 +#define CFG_SYS_NAND_BASE ATMEL_BASE_CS3 +#define CFG_SYS_NAND_MASK_ALE (1 << 21) +#define CFG_SYS_NAND_MASK_CLE (1 << 22) +#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 +#define CFG_SYS_NAND_READY_PIN AT91_PIN_PC13 #endif #if defined(CONFIG_BOARD_TAURUS) -/* USB DFU support */ - -#define CONFIG_USB_GADGET_AT91 - /* DFU class support */ #define DFU_MANIFEST_POLL_TIMEOUT 25000 #endif @@ -127,23 +122,21 @@ /* Defines for SPL */ -#define CONFIG_SYS_NAND_ENABLE_PIN_SPL (2*32 + 14) -#define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE +#define CFG_SYS_NAND_U_BOOT_SIZE SZ_512K +#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE -#define CONFIG_SYS_NAND_SIZE (256 * SZ_1M) -#define CONFIG_SYS_NAND_ECCSIZE 256 -#define CONFIG_SYS_NAND_ECCBYTES 3 -#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ +#define CFG_SYS_NAND_ECCSIZE 256 +#define CFG_SYS_NAND_ECCBYTES 3 +#define CFG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ 48, 49, 50, 51, 52, 53, 54, 55, \ 56, 57, 58, 59, 60, 61, 62, 63, } -#define CONFIG_SYS_MASTER_CLOCK 132096000 +#define CFG_SYS_MASTER_CLOCK 132096000 #define AT91_PLL_LOCK_TIMEOUT 1000000 -#define CONFIG_SYS_AT91_PLLA 0x202A3F01 -#define CONFIG_SYS_MCKR 0x1300 -#define CONFIG_SYS_MCKR_CSS (0x02 | CONFIG_SYS_MCKR) -#define CONFIG_SYS_AT91_PLLB 0x10193F05 +#define CFG_SYS_AT91_PLLA 0x202A3F01 +#define CFG_SYS_MCKR 0x1300 +#define CFG_SYS_MCKR_CSS (0x02 | CFG_SYS_MCKR) +#define CFG_SYS_AT91_PLLB 0x10193F05 #endif diff --git a/include/configs/tb100.h b/include/configs/tb100.h index 16bdc39b750..1318f5e5ee4 100644 --- a/include/configs/tb100.h +++ b/include/configs/tb100.h @@ -12,15 +12,14 @@ * Memory configuration */ -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SDRAM_SIZE SZ_128M +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_SIZE SZ_128M /* * UART configuration */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_CLK 166666666 +#define CFG_SYS_NS16550_CLK 166666666 /* * Even though the board houses Realtek RTL8211E PHY diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h index 7f197851d0a..fcc96749422 100644 --- a/include/configs/tbs2910.h +++ b/include/configs/tbs2910.h @@ -13,16 +13,12 @@ /* General configuration */ /* Physical Memory Map */ -#define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR +#define CFG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_BOOTMAPSZ 0x10000000 - -/* Framebuffer */ -#define CONFIG_IMX_HDMI -#define CONFIG_IMX_VIDEO_SKIP +#define CFG_SYS_BOOTMAPSZ 0x10000000 /* PCI */ #ifdef CONFIG_CMD_PCI diff --git a/include/configs/tec-ng.h b/include/configs/tec-ng.h index f8e741ab6fc..09879663701 100644 --- a/include/configs/tec-ng.h +++ b/include/configs/tec-ng.h @@ -14,7 +14,7 @@ /* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTD -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE /* Environment in eMMC, at the end of 2nd "boot sector" */ diff --git a/include/configs/tec.h b/include/configs/tec.h index 2377b47e054..ddf753da4a9 100644 --- a/include/configs/tec.h +++ b/include/configs/tec.h @@ -16,7 +16,7 @@ /* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */ -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE /* NAND support */ diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index 2915db7f8bf..66cf7ae5847 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -17,8 +17,8 @@ /* Use the Tegra US timer on ARMv7, but the architected timer on ARMv8. */ #ifndef CONFIG_ARM64 -#define CONFIG_SYS_TIMER_RATE 1000000 -#define CONFIG_SYS_TIMER_COUNTER NV_PA_TMRUS_BASE +#define CFG_SYS_TIMER_RATE 1000000 +#define CFG_SYS_TIMER_COUNTER NV_PA_TMRUS_BASE #endif /* Environment */ @@ -26,7 +26,7 @@ /* * NS16550 Configuration */ -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK +#define CFG_SYS_NS16550_CLK V_NS16550_CLK #ifdef CONFIG_ARM64 #define FDTFILE "nvidia/" CONFIG_DEFAULT_DEVICE_TREE ".dtb" @@ -40,13 +40,13 @@ #define PHYS_SDRAM_1 NV_PA_SDRC_CS0 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */ +#define CFG_SYS_BOOTMAPSZ (256 << 20) /* 256M */ #ifndef CONFIG_ARM64 -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN +#define CFG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE +#define CFG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN /* Defines for SPL */ #endif diff --git a/include/configs/ten64.h b/include/configs/ten64.h index 04772c9e4ef..57724719a9d 100644 --- a/include/configs/ten64.h +++ b/include/configs/ten64.h @@ -10,7 +10,7 @@ #include "ls1088a_common.h" -#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 +#define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd" #define SD_BOOTCOMMAND "run distro_bootcmd" diff --git a/include/configs/theadorable-x86-dfi-bt700.h b/include/configs/theadorable-x86-dfi-bt700.h index bb3186e2192..663a49e7b6c 100644 --- a/include/configs/theadorable-x86-dfi-bt700.h +++ b/include/configs/theadorable-x86-dfi-bt700.h @@ -13,7 +13,6 @@ #include <configs/x86-common.h> /* Use BayTrail internal HS UART which is memory-mapped */ -#undef CONFIG_SYS_NS16550_PORT_MAPPED /* Set the board specific parameters */ #define DEF_ENV_TFTPDIR "theadorable-x86-dfi" diff --git a/include/configs/theadorable.h b/include/configs/theadorable.h index 655fcb0011b..76b496303f3 100644 --- a/include/configs/theadorable.h +++ b/include/configs/theadorable.h @@ -68,6 +68,6 @@ /* Defines for SPL */ /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ -#define CONFIG_SYS_SDRAM_SIZE SZ_2G +#define CFG_SYS_SDRAM_SIZE SZ_2G #endif /* _CONFIG_THEADORABLE_H */ diff --git a/include/configs/thunderx_88xx.h b/include/configs/thunderx_88xx.h index cf2efdbe230..7becf1eb7cb 100644 --- a/include/configs/thunderx_88xx.h +++ b/include/configs/thunderx_88xx.h @@ -8,12 +8,12 @@ #define MEM_BASE 0x00500000 -#define CONFIG_SYS_LOWMEM_BASE MEM_BASE +#define CFG_SYS_LOWMEM_BASE MEM_BASE /* Link Definitions */ /* SMP Spin Table Definitions */ -#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) +#define CPU_RELEASE_ADDR (CFG_SYS_SDRAM_BASE + 0x7fff0) /* PL011 Serial Configuration */ @@ -22,15 +22,15 @@ /* Generic Interrupt Controller Definitions */ #define GICD_BASE (0x801000000000) #define GICR_BASE (0x801000002000) -#define CONFIG_SYS_SERIAL0 0x87e024000000 -#define CONFIG_SYS_SERIAL1 0x87e025000000 +#define CFG_SYS_SERIAL0 0x87e024000000 +#define CFG_SYS_SERIAL1 0x87e025000000 /* Miscellaneous configurable options */ /* Physical Memory Map */ #define PHYS_SDRAM_1 (MEM_BASE) /* SDRAM Bank #1 */ #define PHYS_SDRAM_1_SIZE (0x80000000-MEM_BASE) /* 2048 MB */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 /* Initial environment variables */ #define UBOOT_IMG_HEAD_SIZE 0x40 diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h index 97166e010f7..03849adb5ab 100644 --- a/include/configs/ti814x_evm.h +++ b/include/configs/ti814x_evm.h @@ -69,25 +69,21 @@ #define PHYS_DRAM_1_SIZE 0x20000000 /* 512MB */ #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1024MB */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 /** * Platform/Board specific defs */ -#define CONFIG_SYS_TIMERBASE 0x4802E000 +#define CFG_SYS_TIMERBASE 0x4802E000 /* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK (48000000) -#define CONFIG_SYS_NS16550_COM1 0x48020000 /* Base EVM has UART0 */ +#define CFG_SYS_NS16550_CLK (48000000) +#define CFG_SYS_NS16550_COM1 0x48020000 /* Base EVM has UART0 */ /* CPU */ /* Defines for SPL */ -#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 - /* * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM * 64 bytes before this address should be set aside for u-boot.img's diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h index 82add65ec0d..7b04292d218 100644 --- a/include/configs/ti816x_evm.h +++ b/include/configs/ti816x_evm.h @@ -20,20 +20,18 @@ #define V_SCLK (V_OSCK >> 1) #define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2048MB */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 /** * Platform/Board specific defs */ -#define CONFIG_SYS_TIMERBASE 0x4802E000 +#define CFG_SYS_TIMERBASE 0x4802E000 /* * NS16550 Configuration */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK (48000000) -#define CONFIG_SYS_NS16550_COM1 0x48024000 /* Base EVM has UART2 */ +#define CFG_SYS_NS16550_CLK (48000000) +#define CFG_SYS_NS16550_COM1 0x48024000 /* Base EVM has UART2 */ /* allow overwriting serial config and ethaddr */ @@ -42,13 +40,13 @@ * GPMC NAND block. We support 1 device and the physical address to * access CS0 at is 0x8000000. */ -#define CONFIG_SYS_NAND_BASE 0x8000000 +#define CFG_SYS_NAND_BASE 0x8000000 /* NAND: SPL related configs */ /* NAND: device related configs */ /* NAND: driver related configs */ -#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ +#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 10, 11, 12, 13, 14, 15, 16, 17, \ 18, 19, 20, 21, 22, 23, 24, 25, \ 26, 27, 28, 29, 30, 31, 32, 33, \ @@ -56,8 +54,8 @@ 42, 43, 44, 45, 46, 47, 48, 49, \ 50, 51, 52, 53, 54, 55, 56, 57, } -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 14 +#define CFG_SYS_NAND_ECCSIZE 512 +#define CFG_SYS_NAND_ECCBYTES 14 /* SPL */ /* Defines for SPL */ diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h index 5d5df6b1019..ed17b429209 100644 --- a/include/configs/ti_am335x_common.h +++ b/include/configs/ti_am335x_common.h @@ -12,18 +12,12 @@ #define __CONFIG_TI_AM335X_COMMON_H__ #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ -#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ +#define CFG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ #include <asm/arch/omap.h> /* NS16550 Configuration */ -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_NS16550_SERIAL -#ifndef CONFIG_DM_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#endif -#endif -#define CONFIG_SYS_NS16550_CLK 48000000 +#define CFG_SYS_NS16550_CLK 48000000 /* * SPL related defines. The Public RAM memory map the ROM defines the diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index 05536c3eedc..d54c208ef66 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -64,7 +64,7 @@ * initial stack pointer in our SRAM. Otherwise, we can define * CONFIG_NR_DRAM_BANKS before including this file. */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 /* If DM_I2C, enable non-DM I2C support */ @@ -123,7 +123,7 @@ /* General parts of the framework, required. */ #ifdef CONFIG_MTD_RAW_NAND -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE #endif #endif /* !CONFIG_NOR_BOOT */ diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index 6c01ab813e5..ea45bba409c 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -14,7 +14,7 @@ /* SoC Configuration */ /* Memory Configuration */ -#define CONFIG_SYS_LPAE_SDRAM_BASE 0x800000000 +#define CFG_SYS_LPAE_SDRAM_BASE 0x800000000 #define CONFIG_MAX_RAM_BANK_SIZE (2 << 30) /* 2GB */ #ifdef CONFIG_SYS_MALLOC_F_LEN @@ -34,23 +34,17 @@ #define KEYSTONE_SRAM_SCRATCH_SPACE_END (TI_SRAM_SCRATCH_BOARD_EEPROM_END) /* UART Configuration */ -#define CONFIG_SYS_NS16550_MEM32 -#define CONFIG_SYS_NS16550_COM1 KS2_UART0_BASE -#define CONFIG_SYS_NS16550_COM2 KS2_UART1_BASE +#define CFG_SYS_NS16550_COM1 KS2_UART0_BASE +#define CFG_SYS_NS16550_COM2 KS2_UART1_BASE #ifndef CONFIG_SOC_K2G -#define CONFIG_SYS_NS16550_CLK ks_clk_get_rate(KS2_CLK1_6) +#define CFG_SYS_NS16550_CLK ks_clk_get_rate(KS2_CLK1_6) #else -#define CONFIG_SYS_NS16550_CLK ks_clk_get_rate(uart_pll_clk) / 2 +#define CFG_SYS_NS16550_CLK ks_clk_get_rate(uart_pll_clk) / 2 #endif /* SPI Configuration */ -#define CONFIG_SYS_SPI_CLK ks_clk_get_rate(KS2_CLK1_6) - -/* Network Configuration */ -#define CONFIG_SYS_SGMII_REFCLK_MHZ 312 -#define CONFIG_SYS_SGMII_LINERATE_MHZ 1250 -#define CONFIG_SYS_SGMII_RATESCALE 2 +#define CFG_SYS_SPI_CLK ks_clk_get_rate(KS2_CLK1_6) /* Keystone net */ #define CONFIG_KSNET_MAC_ID_BASE KS2_MAC_ID_BASE_ADDR @@ -62,13 +56,12 @@ /* EEPROM definitions */ /* NAND Configuration */ -#define CONFIG_SYS_NAND_MASK_CLE 0x4000 -#define CONFIG_SYS_NAND_MASK_ALE 0x2000 -#define CONFIG_SYS_NAND_CS 2 +#define CFG_SYS_NAND_MASK_CLE 0x4000 +#define CFG_SYS_NAND_MASK_ALE 0x2000 +#define CFG_SYS_NAND_CS 2 -#define CONFIG_SYS_NAND_LARGEPAGE -#define CONFIG_SYS_NAND_BASE_LIST { 0x30000000, } -#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE +#define CFG_SYS_NAND_LARGEPAGE +#define CFG_SYS_NAND_BASE_LIST { 0x30000000, } #define DFU_ALT_INFO_MMC \ "dfu_alt_info_mmc=" \ @@ -183,9 +176,9 @@ #include <asm/arch/hardware.h> #include <asm/arch/clock.h> #ifndef CONFIG_SOC_K2G -#define CONFIG_SYS_HZ_CLOCK ks_clk_get_rate(KS2_CLK1_6) +#define CFG_SYS_HZ_CLOCK ks_clk_get_rate(KS2_CLK1_6) #else -#define CONFIG_SYS_HZ_CLOCK get_external_clk(sys_clk) +#define CFG_SYS_HZ_CLOCK get_external_clk(sys_clk) #endif #endif /* __CONFIG_KS2_EVM_H */ diff --git a/include/configs/ti_armv7_omap.h b/include/configs/ti_armv7_omap.h index 44706c7733a..d34042af468 100644 --- a/include/configs/ti_armv7_omap.h +++ b/include/configs/ti_armv7_omap.h @@ -16,8 +16,8 @@ * access CS0 at is 0x8000000. */ #ifdef CONFIG_MTD_RAW_NAND -#ifndef CONFIG_SYS_NAND_BASE -#define CONFIG_SYS_NAND_BASE 0x8000000 +#ifndef CFG_SYS_NAND_BASE +#define CFG_SYS_NAND_BASE 0x8000000 #endif #endif diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h index 47f3c813b33..36a05b6896e 100644 --- a/include/configs/ti_omap3_common.h +++ b/include/configs/ti_omap3_common.h @@ -26,19 +26,15 @@ /* NS16550 Configuration */ #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK -#if !defined(CONFIG_DM_SERIAL) -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#endif /* !CONFIG_DM_SERIAL */ -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ +#define CFG_SYS_NS16550_CLK V_NS16550_CLK +#define CFG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ 115200} /* Select serial console configuration */ #ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 -#define CONFIG_SYS_NS16550_COM2 OMAP34XX_UART2 -#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 +#define CFG_SYS_NS16550_COM1 OMAP34XX_UART1 +#define CFG_SYS_NS16550_COM2 OMAP34XX_UART2 +#define CFG_SYS_NS16550_COM3 OMAP34XX_UART3 #endif /* Physical Memory Map */ @@ -50,12 +46,12 @@ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). * This rate is divided by a local divisor. */ -#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) +#define CFG_SYS_TIMERBASE (OMAP34XX_GPT2) /* SPL */ #ifdef CONFIG_MTD_RAW_NAND -#define CONFIG_SYS_NAND_BASE 0x30000000 +#define CFG_SYS_NAND_BASE 0x30000000 #endif /* Now bring in the rest of the common code. */ diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h index 0568946fc82..64ec59d78eb 100644 --- a/include/configs/ti_omap4_common.h +++ b/include/configs/ti_omap4_common.h @@ -12,7 +12,7 @@ #define __CONFIG_TI_OMAP4_COMMON_H #ifndef CONFIG_SYS_L2CACHE_OFF -#define CONFIG_SYS_PL310_BASE 0x48242000 +#define CFG_SYS_PL310_BASE 0x48242000 #endif /* Get CPU defs */ @@ -20,23 +20,18 @@ #include <asm/arch/omap.h> /* Use General purpose timer 1 */ -#define CONFIG_SYS_TIMERBASE GPT2_BASE +#define CFG_SYS_TIMERBASE GPT2_BASE #include <configs/ti_armv7_omap.h> /* * Hardware drivers */ -#define CONFIG_SYS_NS16550_CLK 48000000 +#define CFG_SYS_NS16550_CLK 48000000 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL) -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_COM3 UART3_BASE +#define CFG_SYS_NS16550_COM3 UART3_BASE #endif -/* TWL6030 */ -#define CONFIG_TWL6030_POWER 1 - /* * Environment setup */ diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index 24bbf9e7c2c..37ab2e44672 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -17,7 +17,7 @@ #define __CONFIG_TI_OMAP5_COMMON_H /* Use General purpose timer 1 */ -#define CONFIG_SYS_TIMERBASE GPT2_BASE +#define CFG_SYS_TIMERBASE GPT2_BASE #include <linux/stringify.h> @@ -29,11 +29,7 @@ /* * Hardware drivers */ -#define CONFIG_SYS_NS16550_CLK 48000000 -#if !defined(CONFIG_DM_SERIAL) -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#endif +#define CFG_SYS_NS16550_CLK 48000000 /* * Environment setup diff --git a/include/configs/total_compute.h b/include/configs/total_compute.h index ab6cd063321..0f28690612a 100644 --- a/include/configs/total_compute.h +++ b/include/configs/total_compute.h @@ -23,7 +23,7 @@ /* Top 48MB reserved for secure world use */ #define DRAM_SEC_SIZE 0x03000000 #define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define PHYS_SDRAM_2 0x8080000000 #define PHYS_SDRAM_2_SIZE 0x180000000 @@ -41,6 +41,6 @@ * Else boot FIT image. */ -#define CONFIG_SYS_FLASH_BASE 0x0C000000 +#define CFG_SYS_FLASH_BASE 0x0C000000 #endif /* __TOTAL_COMPUTE_H */ diff --git a/include/configs/tplink_wdr4300.h b/include/configs/tplink_wdr4300.h index b14726ad234..24943c8dcfb 100644 --- a/include/configs/tplink_wdr4300.h +++ b/include/configs/tplink_wdr4300.h @@ -6,15 +6,15 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_SDRAM_BASE 0xa0000000 +#define CFG_SYS_SDRAM_BASE 0xa0000000 -#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 +#define CFG_SYS_INIT_RAM_ADDR 0xbd000000 +#define CFG_SYS_INIT_RAM_SIZE 0x8000 /* * Serial Port */ -#define CONFIG_SYS_NS16550_CLK 40000000 +#define CFG_SYS_NS16550_CLK 40000000 /* * Command diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index 2c589158952..7a1ad9544a3 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -11,13 +11,6 @@ #include <linux/kconfig.h> #include <linux/stringify.h> -/* SPL */ -/* #if defined(CONFIG_SPL_BUILD) */ -/* common IMX6 SPL configuration */ -#include "imx6_spl.h" - -/* #endif */ - /* place code in last 4 MiB of RAM */ #include "mx6_common.h" @@ -38,7 +31,6 @@ #define CONFIG_I2C_MULTI_BUS #if !defined(CONFIG_DM_PMIC) -#define CONFIG_POWER_PFUZE100 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 #define TQMA6_PFUZE100_I2C_BUS 2 #endif @@ -275,9 +267,9 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* * All the defines above are for the TQMa6 SoM diff --git a/include/configs/tqma6_wru4.h b/include/configs/tqma6_wru4.h index 999130600cc..4d8839b6e60 100644 --- a/include/configs/tqma6_wru4.h +++ b/include/configs/tqma6_wru4.h @@ -16,11 +16,9 @@ /* Watchdog */ /* Config on-board RTC */ -#define CONFIG_RTC_DS1337 -#define CONFIG_SYS_RTC_BUS_NUM 2 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CFG_SYS_RTC_BUS_NUM 2 +#define CFG_SYS_I2C_RTC_ADDR 0x68 /* Turn off RTC square-wave output to save battery */ -#define CONFIG_RTC_DS1337_NOOSC /* LED */ diff --git a/include/configs/trats.h b/include/configs/trats.h index ca318687783..ec18842bbe8 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -12,12 +12,12 @@ #include <configs/exynos4-common.h> #ifndef CONFIG_SYS_L2CACHE_OFF -#define CONFIG_SYS_PL310_BASE 0x10502000 +#define CFG_SYS_PL310_BASE 0x10502000 #endif /* TRATS has 4 banks of DRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ /* Tizen - partitions definitions */ @@ -125,9 +125,6 @@ /* GPT */ -/* Common misc for Samsung */ -#define CONFIG_MISC_COMMON - /* Download menu - definitions for check keys */ #ifndef __ASSEMBLY__ diff --git a/include/configs/trats2.h b/include/configs/trats2.h index f324ea7ebeb..0aa331e3935 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -13,12 +13,12 @@ #include <configs/exynos4-common.h> #ifndef CONFIG_SYS_L2CACHE_OFF -#define CONFIG_SYS_PL310_BASE 0x10502000 +#define CFG_SYS_PL310_BASE 0x10502000 #endif /* TRATS2 has 4 banks of DRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ /* Tizen - partitions definitions */ @@ -115,9 +115,6 @@ /* GPT */ -/* Common misc for Samsung */ -#define CONFIG_MISC_COMMON - /* Download menu - definitions for check keys */ #ifndef __ASSEMBLY__ diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h index b562d44a13b..e4cbc7da843 100644 --- a/include/configs/trimslice.h +++ b/include/configs/trimslice.h @@ -16,7 +16,7 @@ /* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTA #define CONFIG_TEGRA_UARTA_GPU -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE /* SPI */ diff --git a/include/configs/turris_mox.h b/include/configs/turris_mox.h index f549f9f7ad0..fdb420ed874 100644 --- a/include/configs/turris_mox.h +++ b/include/configs/turris_mox.h @@ -8,8 +8,8 @@ #ifndef _CONFIG_TURRIS_MOX_H #define _CONFIG_TURRIS_MOX_H -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_BAUDRATE_TABLE { 300, 600, 1200, 1800, 2400, 4800, \ +#define CFG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_BAUDRATE_TABLE { 300, 600, 1200, 1800, 2400, 4800, \ 9600, 19200, 38400, 57600, 115200, \ 230400, 460800, 500000, 576000, \ 921600, 1000000, 1152000, 1500000, \ diff --git a/include/configs/udoo.h b/include/configs/udoo.h index 8af5151c503..fac8c1eeb4e 100644 --- a/include/configs/udoo.h +++ b/include/configs/udoo.h @@ -10,8 +10,6 @@ #include "mx6_common.h" -#include "imx6_spl.h" - #define CONFIG_MXC_UART_BASE UART2_BASE /* MMC Configuration */ @@ -51,9 +49,9 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* Environment organization */ diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h index 093e2e8dae7..d4c92233aca 100644 --- a/include/configs/udoo_neo.h +++ b/include/configs/udoo_neo.h @@ -12,8 +12,6 @@ #include "mx6_common.h" -#include "imx6_spl.h" - /* MMC Configuration */ #define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR @@ -59,12 +57,11 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* PMIC */ -#define CONFIG_POWER_PFUZE3000 #define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 #define PFUZE3000_I2C_BUS 0 diff --git a/include/configs/ulcb.h b/include/configs/ulcb.h index a977271c1e6..ab199bc726a 100644 --- a/include/configs/ulcb.h +++ b/include/configs/ulcb.h @@ -14,7 +14,7 @@ /* Environment in eMMC, at the end of 2nd "boot sector" */ #define CONFIG_FLASH_SHOW_PROGRESS 45 -#define CONFIG_SYS_FLASH_BANKS_LIST { 0x08000000 } -#define CONFIG_SYS_WRITE_SWAPPED_DATA +#define CFG_SYS_FLASH_BANKS_LIST { 0x08000000 } +#define CFG_SYS_WRITE_SWAPPED_DATA #endif /* __ULCB_H */ diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 32b47db346f..8cd81f1cddd 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -37,11 +37,11 @@ #if !defined(CONFIG_ARM64) /* Time clock 1MHz */ -#define CONFIG_SYS_TIMER_RATE 1000000 +#define CFG_SYS_TIMER_RATE 1000000 #endif -#define CONFIG_SYS_NAND_REGS_BASE 0x68100000 -#define CONFIG_SYS_NAND_DATA_BASE 0x68000000 +#define CFG_SYS_NAND_REGS_BASE 0x68100000 +#define CFG_SYS_NAND_DATA_BASE 0x68000000 /* * Network Configuration @@ -162,11 +162,11 @@ LINUXBOOT_ENV_SETTINGS \ BOOTENV -#define CONFIG_SYS_BOOTMAPSZ 0x20000000 +#define CFG_SYS_BOOTMAPSZ 0x20000000 /* only for SPL */ /* subtract sizeof(struct legacy_img_hdr) */ -#define CONFIG_SYS_UBOOT_BASE (0x130000 - 0x40) +#define CFG_SYS_UBOOT_BASE (0x130000 - 0x40) #endif /* __CONFIG_UNIPHIER_H__ */ diff --git a/include/configs/usb_a9263.h b/include/configs/usb_a9263.h index 44eaeda432a..657dbadd339 100644 --- a/include/configs/usb_a9263.h +++ b/include/configs/usb_a9263.h @@ -17,29 +17,29 @@ #include <asm/hardware.h> /* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 +#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* * Hardware drivers */ /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 -#define CONFIG_SYS_SDRAM_SIZE 0x04000000 +#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1 +#define CFG_SYS_SDRAM_SIZE 0x04000000 -#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024) -#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 +#define CFG_SYS_INIT_RAM_SIZE (16 * 1024) +#define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 /* NAND flash */ #ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 +#define CFG_SYS_NAND_BASE ATMEL_BASE_CS3 /* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +#define CFG_SYS_NAND_MASK_ALE (1 << 21) /* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15) -#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(22) +#define CFG_SYS_NAND_MASK_CLE (1 << 22) +#define CFG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15) +#define CFG_SYS_NAND_READY_PIN GPIO_PIN_PA(22) #endif /* bootstrap + u-boot + env + linux in dataflash on CS0 */ diff --git a/include/configs/usbarmory.h b/include/configs/usbarmory.h index c381934f31a..a2bc3cd23a5 100644 --- a/include/configs/usbarmory.h +++ b/include/configs/usbarmory.h @@ -27,9 +27,6 @@ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -/* Fuse */ -#define CONFIG_FSL_IIM - /* Linux boot */ #define CONFIG_HOSTNAME "usbarmory" @@ -60,8 +57,8 @@ #define PHYS_SDRAM CSD0_BASE_ADDR #define PHYS_SDRAM_SIZE (gd->ram_size) -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE #endif /* __CONFIG_H */ diff --git a/include/configs/vcoreiii.h b/include/configs/vcoreiii.h index 02ddc6fb6e0..b03159805c1 100644 --- a/include/configs/vcoreiii.h +++ b/include/configs/vcoreiii.h @@ -10,17 +10,17 @@ /* Onboard devices */ -#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 +#define CFG_SYS_INIT_SP_OFFSET 0x400000 -#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_MIPS_TIMER_FREQ +#define CFG_SYS_NS16550_CLK CONFIG_SYS_MIPS_TIMER_FREQ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #if defined(CONFIG_DDRTYPE_H5TQ1G63BFA) || defined(CONFIG_DDRTYPE_MT47H128M8HQ) -#define CONFIG_SYS_SDRAM_SIZE (128 * SZ_1M) +#define CFG_SYS_SDRAM_SIZE (128 * SZ_1M) #elif defined(CONFIG_DDRTYPE_MT41J128M16HA) || defined(CONFIG_DDRTYPE_MT41K128M16JT) -#define CONFIG_SYS_SDRAM_SIZE (256 * SZ_1M) +#define CFG_SYS_SDRAM_SIZE (256 * SZ_1M) #elif defined(CONFIG_DDRTYPE_H5TQ4G63MFR) || defined(CONFIG_DDRTYPE_MT41K256M16) -#define CONFIG_SYS_SDRAM_SIZE (512 * SZ_1M) +#define CFG_SYS_SDRAM_SIZE (512 * SZ_1M) #else #error Unknown DDR size - please add! #endif diff --git a/include/configs/venice2.h b/include/configs/venice2.h index 03aa7adcc0d..b2dc04a975a 100644 --- a/include/configs/venice2.h +++ b/include/configs/venice2.h @@ -16,7 +16,7 @@ /* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTA -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE /* Environment in eMMC, at the end of 2nd "boot sector" */ diff --git a/include/configs/ventana.h b/include/configs/ventana.h index 0bd5a1e8522..f7a507768ec 100644 --- a/include/configs/ventana.h +++ b/include/configs/ventana.h @@ -15,7 +15,7 @@ /* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTD -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE /* Environment in eMMC, at the end of 2nd "boot sector" */ diff --git a/include/configs/verdin-imx8mm.h b/include/configs/verdin-imx8mm.h index f513dade6aa..18ac6b2b089 100644 --- a/include/configs/verdin-imx8mm.h +++ b/include/configs/verdin-imx8mm.h @@ -9,7 +9,7 @@ #include <asm/arch/imx-regs.h> #include <linux/sizes.h> -#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD @@ -53,14 +53,14 @@ "${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x2 " \ "${blkcnt}; fi\0" -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE SZ_2M +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE SZ_2M #if defined(CONFIG_ENV_IS_IN_MMC) /* Environment in eMMC, before config block at the end of 1st "boot sector" */ #endif -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 /* SDRAM configuration */ #define PHYS_SDRAM 0x40000000 diff --git a/include/configs/verdin-imx8mp.h b/include/configs/verdin-imx8mp.h index fea4329d23c..88839a6e561 100644 --- a/include/configs/verdin-imx8mp.h +++ b/include/configs/verdin-imx8mp.h @@ -9,7 +9,7 @@ #include <asm/arch/imx-regs.h> #include <linux/sizes.h> -#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD @@ -65,11 +65,11 @@ "${blkcnt} / 0x200; mmc dev 2 1; mmc write ${loadaddr} 0x0 " \ "${blkcnt}; fi\0" -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE SZ_512K +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE SZ_512K /* i.MX 8M Plus supports max. 8GB memory in two albeit concecutive banks */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE (SZ_2G + SZ_1G) #define PHYS_SDRAM_2 0x100000000 diff --git a/include/configs/vexpress_aemv8.h b/include/configs/vexpress_aemv8.h index 0c11b6b3331..30c1f5025b0 100644 --- a/include/configs/vexpress_aemv8.h +++ b/include/configs/vexpress_aemv8.h @@ -96,7 +96,7 @@ /* Top 16MB reserved for secure world use */ #define DRAM_SEC_SIZE 0x01000000 #define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO #define PHYS_SDRAM_2 (0x880000000) @@ -254,9 +254,9 @@ BOOTENV #ifdef CONFIG_TARGET_VEXPRESS64_JUNO -#define CONFIG_SYS_FLASH_BASE 0x08000000 +#define CFG_SYS_FLASH_BASE 0x08000000 #else -#define CONFIG_SYS_FLASH_BASE (V2M_PA_BASE + 0x0C000000) +#define CFG_SYS_FLASH_BASE (V2M_PA_BASE + 0x0C000000) #endif #endif /* __VEXPRESS_AEMV8_H */ diff --git a/include/configs/vexpress_common.h b/include/configs/vexpress_common.h index 5d773060d82..e8b6acf8b8f 100644 --- a/include/configs/vexpress_common.h +++ b/include/configs/vexpress_common.h @@ -112,17 +112,16 @@ #define SCTL_BASE V2M_SYSCTL #define VEXPRESS_FLASHPROG_FLVPPEN (1 << 0) -#define CONFIG_SYS_TIMER_RATE 1000000 -#define CONFIG_SYS_TIMER_COUNTER (V2M_TIMER01 + 0x4) -#define CONFIG_SYS_TIMER_COUNTS_DOWN +#define CFG_SYS_TIMER_RATE 1000000 +#define CFG_SYS_TIMER_COUNTER (V2M_TIMER01 + 0x4) /* PL011 Serial Configuration */ #define CONFIG_PL011_CLOCK 24000000 -#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \ - (void *)CONFIG_SYS_SERIAL1} +#define CONFIG_PL01x_PORTS {(void *)CFG_SYS_SERIAL0, \ + (void *)CFG_SYS_SERIAL1} -#define CONFIG_SYS_SERIAL0 V2M_UART0 -#define CONFIG_SYS_SERIAL1 V2M_UART1 +#define CFG_SYS_SERIAL0 V2M_UART0 +#define CFG_SYS_SERIAL1 V2M_UART1 /* Miscellaneous configurable options */ #define LINUX_BOOT_PARAM_ADDR (V2M_BASE + 0x2000) @@ -135,8 +134,8 @@ #define PHYS_SDRAM_2_SIZE 0x20000000 /* 512 MB */ /* additions for new relocation code */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_INIT_RAM_SIZE 0x1000 /* Basic environment settings */ #define BOOT_TARGET_DEVICES(func) \ @@ -165,7 +164,7 @@ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" /* FLASH and environment organization */ -#define CONFIG_SYS_FLASH_SIZE 0x04000000 +#define CFG_SYS_FLASH_SIZE 0x04000000 /* Timeout values in ticks */ @@ -178,6 +177,6 @@ */ /* Store environment at top of flash */ -#define CONFIG_SYS_FLASH_BANKS_LIST { V2M_NOR0, V2M_NOR1 } +#define CFG_SYS_FLASH_BANKS_LIST { V2M_NOR0, V2M_NOR1 } #endif /* VEXPRESS_COMMON_H */ diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h index 7e3d3473b44..14e6b2bac91 100644 --- a/include/configs/vf610twr.h +++ b/include/configs/vf610twr.h @@ -14,7 +14,7 @@ /* NAND support */ #ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR +#define CFG_SYS_NAND_BASE NFC_BASE_ADDR /* Dynamic MTD partition support */ #endif @@ -123,8 +123,8 @@ #define PHYS_SDRAM (0x80000000) #define PHYS_SDRAM_SIZE (128 * 1024 * 1024) -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE #endif diff --git a/include/configs/vinco.h b/include/configs/vinco.h index a1572967618..9f72bdde816 100644 --- a/include/configs/vinco.h +++ b/include/configs/vinco.h @@ -21,17 +21,17 @@ #define CONFIG_USART_ID 30 /* Timer */ -#define CONFIG_SYS_TIMER_COUNTER 0xfc06863c +#define CFG_SYS_TIMER_COUNTER 0xfc06863c /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x4000000 +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE 0x4000000 /* MMC */ #ifdef CONFIG_CMD_MMC #define ATMEL_BASE_MMCI 0xfc000000 -#define CONFIG_SYS_MMC_CLK_OD 500000 +#define CFG_SYS_MMC_CLK_OD 500000 /* For generating MMC partitions */ diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h index a4484fd3f8c..1a71b300fc5 100644 --- a/include/configs/vining_2000.h +++ b/include/configs/vining_2000.h @@ -10,10 +10,6 @@ #include "mx6_common.h" -#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ func(MMC, mmc, 1) \ @@ -27,15 +23,14 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* MMC Configuration */ #define CFG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR /* PMIC */ -#define CONFIG_POWER_PFUZE100 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 /* Network */ diff --git a/include/configs/vocore2.h b/include/configs/vocore2.h index 6f36d6964b9..43050d61c37 100644 --- a/include/configs/vocore2.h +++ b/include/configs/vocore2.h @@ -7,22 +7,20 @@ #define __VOCORE2_CONFIG_H__ /* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 +#define CFG_SYS_INIT_SP_OFFSET 0x400000 /* SPL */ -#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE /* Dummy value */ -#define CONFIG_SYS_UBOOT_BASE 0 +#define CFG_SYS_UBOOT_BASE 0 /* Serial SPL */ -#define CONFIG_SYS_NS16550_MEM32 -#define CONFIG_SYS_NS16550_CLK 40000000 -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#define CONFIG_SYS_NS16550_COM3 0xb0000e00 +#define CFG_SYS_NS16550_CLK 40000000 +#define CFG_SYS_NS16550_COM3 0xb0000e00 /* RAM */ diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index 91c1f4b3b51..6923009d459 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -10,8 +10,6 @@ #include "mx6_common.h" -#include "imx6_spl.h" - #define CONFIG_MXC_UART_BASE UART1_BASE /* MMC Configuration */ @@ -22,10 +20,6 @@ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -/* Framebuffer */ -#define CONFIG_IMX_HDMI -#define CONFIG_IMX_VIDEO_SKIP - #define CONFIG_EXTRA_ENV_SETTINGS \ "console=ttymxc0\0" \ "splashpos=m,m\0" \ @@ -91,9 +85,9 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* Environment organization */ diff --git a/include/configs/warp7.h b/include/configs/warp7.h index a4b12dc55ed..56c90aa1032 100644 --- a/include/configs/warp7.h +++ b/include/configs/warp7.h @@ -84,9 +84,9 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* environment organization */ diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h index a7c805c2d6f..010da1531ff 100644 --- a/include/configs/work_92105.h +++ b/include/configs/work_92105.h @@ -16,10 +16,8 @@ /* * Memory configurations */ -#define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE -#define CONFIG_SYS_SDRAM_SIZE SZ_128M - -#define CONFIG_RTC_DS1374 +#define CFG_SYS_SDRAM_BASE EMC_DYCS0_BASE +#define CFG_SYS_SDRAM_SIZE SZ_128M /* * U-Boot General Configurations @@ -42,8 +40,8 @@ */ /* driver configuration */ -#define CONFIG_SYS_MAX_NAND_CHIPS 1 -#define CONFIG_SYS_NAND_BASE MLC_NAND_BASE +#define CFG_SYS_MAX_NAND_CHIPS 1 +#define CFG_SYS_NAND_BASE MLC_NAND_BASE /* * GPIO @@ -63,8 +61,8 @@ /* SPL will use serial */ /* SPL will load U-Boot from NAND offset 0x40000 */ /* U-Boot will be 0x40000 bytes, loaded and run at CONFIG_TEXT_BASE */ -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE +#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE /* * Include SoC specific configuration diff --git a/include/configs/x530.h b/include/configs/x530.h index 0add626e81a..dee87cb7732 100644 --- a/include/configs/x530.h +++ b/include/configs/x530.h @@ -13,11 +13,9 @@ /* * NS16550 Configuration */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK +#define CFG_SYS_NS16550_CLK CFG_SYS_TCLK #if !defined(CONFIG_DM_SERIAL) -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE +#define CFG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE #endif /* diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index 8e22d6e5d87..3e17b53dde2 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -21,7 +21,6 @@ /*----------------------------------------------------------------------- * Serial Configuration */ -#define CONFIG_SYS_NS16550_PORT_MAPPED /* * Miscellaneous configurable options @@ -31,7 +30,7 @@ * CPU Features */ -#define CONFIG_SYS_STACK_SIZE (32 * 1024) +#define CFG_SYS_STACK_SIZE (32 * 1024) /*----------------------------------------------------------------------- * Environment configuration diff --git a/include/configs/xea.h b/include/configs/xea.h index 19ccf633c40..b432ab2dc8e 100644 --- a/include/configs/xea.h +++ b/include/configs/xea.h @@ -16,14 +16,14 @@ /* SPL */ -#define CONFIG_SYS_SPI_KERNEL_OFFS SZ_1M -#define CONFIG_SYS_SPI_ARGS_OFFS SZ_512K -#define CONFIG_SYS_SPI_ARGS_SIZE SZ_32K +#define CFG_SYS_SPI_KERNEL_OFFS SZ_1M +#define CFG_SYS_SPI_ARGS_OFFS SZ_512K +#define CFG_SYS_SPI_ARGS_SIZE SZ_32K /* Memory configuration */ #define PHYS_SDRAM_1 0x40000000 /* Base address */ #define PHYS_SDRAM_1_SIZE 0x10000000 /* Max 256 MB RAM */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 /* Extra Environment */ #define CONFIG_HOSTNAME "xea" diff --git a/include/configs/xenguest_arm64.h b/include/configs/xenguest_arm64.h index 364dae0cd93..612436aeb48 100644 --- a/include/configs/xenguest_arm64.h +++ b/include/configs/xenguest_arm64.h @@ -11,7 +11,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS -#undef CONFIG_SYS_SDRAM_BASE +#undef CFG_SYS_SDRAM_BASE #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/xilinx_versal.h b/include/configs/xilinx_versal.h index 8caf5394ed4..ee3130ed327 100644 --- a/include/configs/xilinx_versal.h +++ b/include/configs/xilinx_versal.h @@ -15,7 +15,7 @@ #define GICR_BASE 0xF9080000 /* Serial setup */ -#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ { 4800, 9600, 19200, 38400, 57600, 115200 } /* GUID for capsule updatable firmware image */ diff --git a/include/configs/xilinx_versal_net.h b/include/configs/xilinx_versal_net.h index 0ccd38b7e69..7d77189693e 100644 --- a/include/configs/xilinx_versal_net.h +++ b/include/configs/xilinx_versal_net.h @@ -20,7 +20,7 @@ #define GICR_BASE 0xF9060000 /* Serial setup */ -#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ { 4800, 9600, 19200, 38400, 57600, 115200 } #if defined(CONFIG_CMD_DFU) diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 60f007a10fc..efe241df97e 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -15,7 +15,7 @@ #define GICC_BASE 0xF9020000 /* Serial setup */ -#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ { 4800, 9600, 19200, 38400, 57600, 115200 } /* GUIDs for capsule updatable firmware images */ @@ -192,9 +192,9 @@ #endif #if defined(CONFIG_SPL_SPI_FLASH_SUPPORT) -# define CONFIG_SYS_SPI_KERNEL_OFFS 0x80000 -# define CONFIG_SYS_SPI_ARGS_OFFS 0xa0000 -# define CONFIG_SYS_SPI_ARGS_SIZE 0xa0000 +# define CFG_SYS_SPI_KERNEL_OFFS 0x80000 +# define CFG_SYS_SPI_ARGS_OFFS 0xa0000 +# define CFG_SYS_SPI_ARGS_SIZE 0xa0000 #endif /* u-boot is like dtb */ diff --git a/include/configs/xilinx_zynqmp_mini_nand.h b/include/configs/xilinx_zynqmp_mini_nand.h index d2c0e91b32e..1b6e26ee396 100644 --- a/include/configs/xilinx_zynqmp_mini_nand.h +++ b/include/configs/xilinx_zynqmp_mini_nand.h @@ -12,7 +12,7 @@ #include <configs/xilinx_zynqmp_mini.h> -#define CONFIG_SYS_SDRAM_SIZE 0x1000000 -#define CONFIG_SYS_SDRAM_BASE 0x0 +#define CFG_SYS_SDRAM_SIZE 0x1000000 +#define CFG_SYS_SDRAM_BASE 0x0 #endif /* __CONFIG_ZYNQMP_MINI_NAND_H */ diff --git a/include/configs/xilinx_zynqmp_r5.h b/include/configs/xilinx_zynqmp_r5.h index b6bc402a7e9..3a7b7e03d6a 100644 --- a/include/configs/xilinx_zynqmp_r5.h +++ b/include/configs/xilinx_zynqmp_r5.h @@ -10,13 +10,13 @@ /* Serial drivers */ /* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} /* Boot configuration */ -#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 +#define CFG_SYS_INIT_RAM_ADDR 0xFFFF0000 +#define CFG_SYS_INIT_RAM_SIZE 0x1000 /* Extend size of kernel image for uncompression */ diff --git a/include/configs/xpress.h b/include/configs/xpress.h index fc8ec3204b1..3e604894ad4 100644 --- a/include/configs/xpress.h +++ b/include/configs/xpress.h @@ -10,9 +10,6 @@ #include "mx6_common.h" #include <asm/mach-imx/gpio.h> -/* SPL options */ -#include "imx6_spl.h" - #define CONFIG_MXC_UART_BASE MX6UL_UART7_BASE_ADDR /* MMC Configs */ @@ -24,9 +21,9 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define PHYS_SDRAM_SIZE (128 << 20) -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* Environment is in stored in the eMMC boot partition */ diff --git a/include/configs/xtfpga.h b/include/configs/xtfpga.h index 58d01f4bb42..9201dac7abc 100644 --- a/include/configs/xtfpga.h +++ b/include/configs/xtfpga.h @@ -21,12 +21,12 @@ /*===================*/ #if XCHAL_HAVE_PTP_MMU -#define CONFIG_SYS_MEMORY_BASE \ +#define CFG_SYS_MEMORY_BASE \ (XCHAL_VECBASE_RESET_VADDR - XCHAL_VECBASE_RESET_PADDR) -#define CONFIG_SYS_IO_BASE 0xf0000000 +#define CFG_SYS_IO_BASE 0xf0000000 #else -#define CONFIG_SYS_MEMORY_BASE 0x60000000 -#define CONFIG_SYS_IO_BASE 0x90000000 +#define CFG_SYS_MEMORY_BASE 0x60000000 +#define CFG_SYS_IO_BASE 0x90000000 #define CONFIG_MAX_MEM_MAPPED 0x10000000 #endif @@ -42,12 +42,12 @@ */ #if XCHAL_HAVE_PTP_MMU || CONFIG_BOARD_SDRAM_SIZE < 0x10000000 -#define CONFIG_SYS_SDRAM_SIZE CONFIG_BOARD_SDRAM_SIZE +#define CFG_SYS_SDRAM_SIZE CONFIG_BOARD_SDRAM_SIZE #else -#define CONFIG_SYS_SDRAM_SIZE 0x10000000 +#define CFG_SYS_SDRAM_SIZE 0x10000000 #endif -#define CONFIG_SYS_SDRAM_BASE MEMADDR(0x00000000) +#define CFG_SYS_SDRAM_BASE MEMADDR(0x00000000) /* Lx60 can only map 128kb memory (instead of 256kb) when running under OCD */ @@ -70,12 +70,12 @@ #endif #if defined(CONFIG_MAX_MEM_MAPPED) && \ - CONFIG_MAX_MEM_MAPPED < CONFIG_SYS_SDRAM_SIZE + CONFIG_MAX_MEM_MAPPED < CFG_SYS_SDRAM_SIZE #define XTENSA_SYS_TEXT_ADDR \ (MEMADDR(CONFIG_MAX_MEM_MAPPED) - CONFIG_SYS_MONITOR_LEN) #else #define XTENSA_SYS_TEXT_ADDR \ - (MEMADDR(CONFIG_SYS_SDRAM_SIZE) - CONFIG_SYS_MONITOR_LEN) + (MEMADDR(CFG_SYS_SDRAM_SIZE) - CONFIG_SYS_MONITOR_LEN) #endif /*==============================*/ @@ -100,16 +100,16 @@ */ /* FPGA core clock frequency in Hz (also input to UART) */ -#define CONFIG_SYS_FPGAREG_FREQ IOADDR(0x0D020004) /* CPU clock frequency*/ +#define CFG_SYS_FPGAREG_FREQ IOADDR(0x0D020004) /* CPU clock frequency*/ /* * DIP switch (left=sw1=lsb=bit0, right=sw8=msb=bit7; off=0, on=1): * Bits 0..5 set the lower 6 bits of the default ethernet MAC. * Bit 6 is reserved for future use by Tensilica. - * Bit 7 maps the first 128KB of ROM address space at CONFIG_SYS_ROM_BASE to + * Bit 7 maps the first 128KB of ROM address space at CFG_SYS_ROM_BASE to * the base of flash * (when on/1) or to the base of RAM (when off/0). */ -#define CONFIG_SYS_FPGAREG_DIPSW IOADDR(0x0D02000C) +#define CFG_SYS_FPGAREG_DIPSW IOADDR(0x0D02000C) #define FPGAREG_MAC_SHIFT 0 /* Ethernet MAC bits 0..5 */ #define FPGAREG_MAC_WIDTH 6 #define FPGAREG_MAC_MASK 0x3f @@ -120,44 +120,42 @@ #define FPGAREG_BOOT_FLASH (1<<FPGAREG_BOOT_SHIFT) /* Force hard reset of board by writing a code to this register */ -#define CONFIG_SYS_FPGAREG_RESET IOADDR(0x0D020010) /* Reset board .. */ -#define CONFIG_SYS_FPGAREG_RESET_CODE 0x0000DEAD /* by writing this code */ +#define CFG_SYS_FPGAREG_RESET IOADDR(0x0D020010) /* Reset board .. */ +#define CFG_SYS_FPGAREG_RESET_CODE 0x0000DEAD /* by writing this code */ /*====================*/ /* Serial Driver Info */ /*====================*/ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_COM1 IOADDR(0x0D050020) /* Base address */ +#define CFG_SYS_NS16550_COM1 IOADDR(0x0D050020) /* Base address */ /* Input clk to NS16550 (in Hz; the SYS_CLK_FREQ is in kHz) */ -#define CONFIG_SYS_NS16550_CLK get_board_sys_clk() +#define CFG_SYS_NS16550_CLK get_board_sys_clk() /*======================*/ /* Ethernet Driver Info */ /*======================*/ #define CONFIG_ETHBASE 00:50:C2:13:6f:00 -#define CONFIG_SYS_ETHOC_BASE IOADDR(0x0d030000) -#define CONFIG_SYS_ETHOC_BUFFER_ADDR IOADDR(0x0D800000) +#define CFG_SYS_ETHOC_BASE IOADDR(0x0d030000) +#define CFG_SYS_ETHOC_BUFFER_ADDR IOADDR(0x0D800000) /*=====================*/ /* Flash & Environment */ /*=====================*/ #ifdef CONFIG_XTFPGA_LX60 -# define CONFIG_SYS_FLASH_SIZE 0x0040000 /* 4MB */ -# define CONFIG_SYS_FLASH_PARMSECT_SZ 0x2000 /* param size 8KB */ -# define CONFIG_SYS_FLASH_BASE IOADDR(0x08000000) +# define CFG_SYS_FLASH_SIZE 0x0040000 /* 4MB */ +# define CFG_SYS_FLASH_PARMSECT_SZ 0x2000 /* param size 8KB */ +# define CFG_SYS_FLASH_BASE IOADDR(0x08000000) #elif defined(CONFIG_XTFPGA_KC705) -# define CONFIG_SYS_FLASH_SIZE 0x8000000 /* 128MB */ -# define CONFIG_SYS_FLASH_PARMSECT_SZ 0x8000 /* param size 32KB */ -# define CONFIG_SYS_FLASH_BASE IOADDR(0x00000000) +# define CFG_SYS_FLASH_SIZE 0x8000000 /* 128MB */ +# define CFG_SYS_FLASH_PARMSECT_SZ 0x8000 /* param size 32KB */ +# define CFG_SYS_FLASH_BASE IOADDR(0x00000000) #else -# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* 16MB */ -# define CONFIG_SYS_FLASH_PARMSECT_SZ 0x8000 /* param size 32KB */ -# define CONFIG_SYS_FLASH_BASE IOADDR(0x08000000) +# define CFG_SYS_FLASH_SIZE 0x1000000 /* 16MB */ +# define CFG_SYS_FLASH_PARMSECT_SZ 0x8000 /* param size 32KB */ +# define CFG_SYS_FLASH_BASE IOADDR(0x08000000) #endif /* diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 6574cf92e26..b8c142fed37 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -11,13 +11,12 @@ /* Cache options */ #ifndef CONFIG_SYS_L2CACHE_OFF -# define CONFIG_SYS_PL310_BASE 0xf8f02000 +# define CFG_SYS_PL310_BASE 0xf8f02000 #endif #define ZYNQ_SCUTIMER_BASEADDR 0xF8F00600 -#define CONFIG_SYS_TIMERBASE ZYNQ_SCUTIMER_BASEADDR -#define CONFIG_SYS_TIMER_COUNTS_DOWN -#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) +#define CFG_SYS_TIMERBASE ZYNQ_SCUTIMER_BASEADDR +#define CFG_SYS_TIMER_COUNTER (CFG_SYS_TIMERBASE + 0x4) /* GUIDs for capsule updatable firmware images */ #define XILINX_BOOT_IMAGE_GUID \ @@ -30,7 +29,7 @@ /* Serial drivers */ /* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} /* Ethernet driver */ @@ -189,8 +188,8 @@ /* Miscellaneous configurable options */ -#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 +#define CFG_SYS_INIT_RAM_ADDR 0xFFFF0000 +#define CFG_SYS_INIT_RAM_SIZE 0x2000 /* Extend size of kernel image for uncompression */ @@ -201,10 +200,10 @@ /* qspi mode is working fine */ #ifdef CONFIG_ZYNQ_QSPI -#define CONFIG_SYS_SPI_ARGS_OFFS 0x200000 -#define CONFIG_SYS_SPI_ARGS_SIZE 0x80000 -#define CONFIG_SYS_SPI_KERNEL_OFFS (CONFIG_SYS_SPI_ARGS_OFFS + \ - CONFIG_SYS_SPI_ARGS_SIZE) +#define CFG_SYS_SPI_ARGS_OFFS 0x200000 +#define CFG_SYS_SPI_ARGS_SIZE 0x80000 +#define CFG_SYS_SPI_KERNEL_OFFS (CFG_SYS_SPI_ARGS_OFFS + \ + CFG_SYS_SPI_ARGS_SIZE) #endif /* SP location before relocation, must use scratch RAM */ diff --git a/include/configs/zynq_cse.h b/include/configs/zynq_cse.h index cb982c2e74f..ac6e8c4ff86 100644 --- a/include/configs/zynq_cse.h +++ b/include/configs/zynq_cse.h @@ -14,9 +14,9 @@ /* Undef unneeded configs */ #undef CONFIG_EXTRA_ENV_SETTINGS -#undef CONFIG_SYS_INIT_RAM_ADDR -#undef CONFIG_SYS_INIT_RAM_SIZE -#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFDE000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 +#undef CFG_SYS_INIT_RAM_ADDR +#undef CFG_SYS_INIT_RAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR 0xFFFDE000 +#define CFG_SYS_INIT_RAM_SIZE 0x1000 #endif /* __CONFIG_ZYNQ_CSE_H */ diff --git a/include/dm/platform_data/lpc32xx_hsuart.h b/include/dm/platform_data/lpc32xx_hsuart.h deleted file mode 100644 index 6f41e0e734a..00000000000 --- a/include/dm/platform_data/lpc32xx_hsuart.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2015 Vladimir Zapolskiy <vz@mleia.com> - */ - -#ifndef _LPC32XX_HSUART_PLAT_H -#define _LPC32XX_HSUART_PLAT_H - -/** - * struct lpc32xx_hsuart_plat - NXP LPC32xx HSUART platform data - * - * @base: Base register address - */ -struct lpc32xx_hsuart_plat { - unsigned long base; -}; - -#endif diff --git a/include/e500.h b/include/e500.h index 255f46bf1e5..9f68a834c2f 100644 --- a/include/e500.h +++ b/include/e500.h @@ -19,7 +19,7 @@ typedef struct unsigned long freq_localbus; unsigned long freq_qe; #ifdef CONFIG_SYS_DPAA_FMAN - unsigned long freq_fman[CONFIG_SYS_NUM_FMAN]; + unsigned long freq_fman[CFG_SYS_NUM_FMAN]; #endif #ifdef CONFIG_SYS_DPAA_QBMAN unsigned long freq_qman; diff --git a/include/fm_eth.h b/include/fm_eth.h index 7475b515073..aeb640925ee 100644 --- a/include/fm_eth.h +++ b/include/fm_eth.h @@ -56,7 +56,7 @@ enum fm_eth_type { #define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR (CFG_SYS_FSL_FM1_ADDR + 0xfc000) #endif #define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CFG_SYS_FSL_FM1_ADDR + 0xfd000) -#if (CONFIG_SYS_NUM_FMAN == 2) +#if (CFG_SYS_NUM_FMAN == 2) #define CONFIG_SYS_FM2_DTSEC_MDIO_ADDR (CFG_SYS_FSL_FM2_ADDR + 0xfc000) #define CONFIG_SYS_FM2_TGEC_MDIO_ADDR (CFG_SYS_FSL_FM2_ADDR + 0xfd000) #endif @@ -102,7 +102,7 @@ enum fm_eth_type { offsetof(struct ccsr_fman, memac[n-1]),\ } #else -#if (CONFIG_SYS_NUM_FMAN == 2) +#if (CFG_SYS_NUM_FMAN == 2) #define FM_TGEC_INFO_INITIALIZER(idx, n) \ { \ FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM2_TGEC_MDIO_ADDR) \ @@ -131,7 +131,7 @@ enum fm_eth_type { #endif #endif -#if (CONFIG_SYS_NUM_FM1_10GEC >= 3) +#if (CFG_SYS_NUM_FM1_10GEC >= 3) #define FM_TGEC_INFO_INITIALIZER2(idx, n) \ { \ FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \ diff --git a/include/fsl-mc/fsl_mc.h b/include/fsl-mc/fsl_mc.h index 07a46a4a1b0..c701dc1084b 100644 --- a/include/fsl-mc/fsl_mc.h +++ b/include/fsl-mc/fsl_mc.h @@ -66,7 +66,7 @@ int get_mc_boot_status(void); int get_dpl_apply_status(void); int is_lazy_dpl_addr_valid(void); void fdt_fixup_mc_ddr(u64 *base, u64 *size); -#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET +#ifdef CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET int get_aiop_apply_status(void); #endif u64 mc_get_dram_addr(void); diff --git a/include/fsl_ifc.h b/include/fsl_ifc.h index 9f243cd9457..de1e70a6d0b 100644 --- a/include/fsl_ifc.h +++ b/include/fsl_ifc.h @@ -801,7 +801,7 @@ void init_final_memctl_regs(void); #define IFC_RREGS_64KOFFSET (64*1024) #define IFC_FCM_BASE_ADDR \ - ((struct fsl_ifc_fcm *)CONFIG_SYS_IFC_ADDR) + ((struct fsl_ifc_fcm *)CFG_SYS_IFC_ADDR) #define get_ifc_cspr_ext(i) \ (ifc_in32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr_ext)) diff --git a/include/i2c.h b/include/i2c.h index e0ee94e5504..51390f8fd84 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -633,19 +633,19 @@ void i2c_early_init_f(void); */ #define I2C_RXTX_LEN 128 /* maximum tx/rx buffer length */ -#if !defined(CONFIG_SYS_I2C_MAX_HOPS) +#if !defined(CFG_SYS_I2C_MAX_HOPS) /* no muxes used bus = i2c adapters */ #define CONFIG_SYS_I2C_DIRECT_BUS 1 -#define CONFIG_SYS_I2C_MAX_HOPS 0 -#define CONFIG_SYS_NUM_I2C_BUSES ll_entry_count(struct i2c_adapter, i2c) +#define CFG_SYS_I2C_MAX_HOPS 0 +#define CFG_SYS_NUM_I2C_BUSES ll_entry_count(struct i2c_adapter, i2c) #else /* we use i2c muxes */ #undef CONFIG_SYS_I2C_DIRECT_BUS #endif /* define the I2C bus number for RTC and DTT if not already done */ -#if !defined(CONFIG_SYS_RTC_BUS_NUM) -#define CONFIG_SYS_RTC_BUS_NUM 0 +#if !defined(CFG_SYS_RTC_BUS_NUM) +#define CFG_SYS_RTC_BUS_NUM 0 #endif struct i2c_adapter { @@ -705,7 +705,7 @@ struct i2c_next_hop { struct i2c_bus_hose { int adapter; - struct i2c_next_hop next_hop[CONFIG_SYS_I2C_MAX_HOPS]; + struct i2c_next_hop next_hop[CFG_SYS_I2C_MAX_HOPS]; }; #define I2C_NULL_HOP {{-1, ""}, 0, 0} extern struct i2c_bus_hose i2c_bus[]; @@ -931,12 +931,12 @@ unsigned int i2c_get_bus_speed(void); * completely to new multibus support. */ #if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || defined(CONFIG_I2C_MULTI_BUS) -# if !defined(CONFIG_SYS_MAX_I2C_BUS) -# define CONFIG_SYS_MAX_I2C_BUS 2 +# if !defined(CFG_SYS_MAX_I2C_BUS) +# define CFG_SYS_MAX_I2C_BUS 2 # endif # define I2C_MULTI_BUS 1 #else -# define CONFIG_SYS_MAX_I2C_BUS 1 +# define CFG_SYS_MAX_I2C_BUS 1 # define I2C_MULTI_BUS 0 #endif diff --git a/include/init.h b/include/init.h index d40d11f33d2..699dc2482c0 100644 --- a/include/init.h +++ b/include/init.h @@ -90,8 +90,8 @@ int dram_init(void); * * If this is not provided, a default implementation will try to set up a * single bank. It will do this if CONFIG_NR_DRAM_BANKS and - * CONFIG_SYS_SDRAM_BASE are set. The bank will have a start address of - * CONFIG_SYS_SDRAM_BASE and the size will be determined by a call to + * CFG_SYS_SDRAM_BASE are set. The bank will have a start address of + * CFG_SYS_SDRAM_BASE and the size will be determined by a call to * get_effective_memsize(). * * Return: 0 if OK, -ve on error diff --git a/include/mpc85xx.h b/include/mpc85xx.h index 053b68a10a4..636734dd3c6 100644 --- a/include/mpc85xx.h +++ b/include/mpc85xx.h @@ -26,38 +26,38 @@ * Define default values for some CCSR macros to make header files cleaner* * * To completely disable CCSR relocation in a board header file, define - * CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS - * to a value that is the same as CONFIG_SYS_CCSRBAR. + * CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE. This will force CFG_SYS_CCSRBAR_PHYS + * to a value that is the same as CFG_SYS_CCSRBAR. */ -#ifdef CONFIG_SYS_CCSRBAR_PHYS -#error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly. Use \ -CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead." +#ifdef CFG_SYS_CCSRBAR_PHYS +#error "Do not define CFG_SYS_CCSRBAR_PHYS directly. Use \ +CFG_SYS_CCSRBAR_PHYS_LOW and/or CFG_SYS_CCSRBAR_PHYS_HIGH instead." #endif #if CONFIG_IS_ENABLED(SYS_CCSR_DO_NOT_RELOCATE) -#undef CONFIG_SYS_CCSRBAR_PHYS_HIGH -#undef CONFIG_SYS_CCSRBAR_PHYS_LOW -#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 +#undef CFG_SYS_CCSRBAR_PHYS_HIGH +#undef CFG_SYS_CCSRBAR_PHYS_LOW +#define CFG_SYS_CCSRBAR_PHYS_HIGH 0 #endif -#ifndef CONFIG_SYS_CCSRBAR -#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT +#ifndef CFG_SYS_CCSRBAR +#define CFG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT #endif -#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH +#ifndef CFG_SYS_CCSRBAR_PHYS_HIGH #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf +#define CFG_SYS_CCSRBAR_PHYS_HIGH 0xf #else -#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 +#define CFG_SYS_CCSRBAR_PHYS_HIGH 0 #endif #endif -#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT +#ifndef CFG_SYS_CCSRBAR_PHYS_LOW +#define CFG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT #endif -#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \ - CONFIG_SYS_CCSRBAR_PHYS_LOW) +#define CFG_SYS_CCSRBAR_PHYS ((CFG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \ + CFG_SYS_CCSRBAR_PHYS_LOW) #endif /* __MPC85xx_H__ */ diff --git a/include/mpc86xx.h b/include/mpc86xx.h index 9fe47480325..ea8d17d557e 100644 --- a/include/mpc86xx.h +++ b/include/mpc86xx.h @@ -16,9 +16,9 @@ * platform register addresses */ -#define GUTS_SVR (CONFIG_SYS_CCSRBAR + 0xE00A4) -#define MCM_ABCR (CONFIG_SYS_CCSRBAR + 0x01000) -#define MCM_DBCR (CONFIG_SYS_CCSRBAR + 0x01008) +#define GUTS_SVR (CFG_SYS_CCSRBAR + 0xE00A4) +#define MCM_ABCR (CFG_SYS_CCSRBAR + 0x01000) +#define MCM_DBCR (CFG_SYS_CCSRBAR + 0x01008) /* * l2cr values. Look in config_<BOARD>.h for the actual setup diff --git a/include/mtd/cfi_flash.h b/include/mtd/cfi_flash.h index 1321da19102..52cd1c4dbc4 100644 --- a/include/mtd/cfi_flash.h +++ b/include/mtd/cfi_flash.h @@ -147,8 +147,8 @@ struct cfi_pri_hdr { u8 minor_version; } __attribute__((packed)); -#ifndef CONFIG_SYS_FLASH_BANKS_LIST -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } +#ifndef CFG_SYS_FLASH_BANKS_LIST +#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE } #endif /* diff --git a/include/mvebu_mmc.h b/include/mvebu_mmc.h index e75c3fa3289..0f6f5c23dee 100644 --- a/include/mvebu_mmc.h +++ b/include/mvebu_mmc.h @@ -21,7 +21,7 @@ #define MVEBU_MMC_CLOCKRATE_MAX 50000000 #define MVEBU_MMC_BASE_DIV_MAX 0x7ff -#define MVEBU_MMC_BASE_FAST_CLOCK CONFIG_SYS_TCLK +#define MVEBU_MMC_BASE_FAST_CLOCK CFG_SYS_TCLK #define MVEBU_MMC_BASE_FAST_CLK_100 100000000 #define MVEBU_MMC_BASE_FAST_CLK_200 200000000 diff --git a/include/ns16550.h b/include/ns16550.h index 3d9002d9f15..0ee5c4d6de7 100644 --- a/include/ns16550.h +++ b/include/ns16550.h @@ -26,7 +26,7 @@ #include <linux/types.h> -#ifdef CONFIG_DM_SERIAL +#if defined(CONFIG_DM_SERIAL) && !defined(CONFIG_SYS_NS16550_REG_SIZE) /* * For driver model we always use one byte per register, and sort out the * differences in the driver diff --git a/include/post.h b/include/post.h index ec03556e917..e68d5c89020 100644 --- a/include/post.h +++ b/include/post.h @@ -16,7 +16,7 @@ #if defined(CONFIG_POST) -#ifndef CONFIG_POST_EXTERNAL_WORD_FUNCS +#ifndef CFG_POST_EXTERNAL_WORD_FUNCS #ifdef CONFIG_SYS_POST_WORD_ADDR #define _POST_WORD_ADDR CONFIG_SYS_POST_WORD_ADDR #else @@ -51,7 +51,7 @@ static inline void post_word_store (ulong value) extern ulong post_word_load(void); extern void post_word_store(ulong value); -#endif /* CONFIG_POST_EXTERNAL_WORD_FUNCS */ +#endif /* CFG_POST_EXTERNAL_WORD_FUNCS */ #endif /* defined (CONFIG_POST) */ #endif /* __ASSEMBLY__ */ @@ -142,7 +142,7 @@ extern int memory_post_test(int flags); #define CONFIG_SYS_POST_RTC 0x00000001 #define CONFIG_SYS_POST_WATCHDOG 0x00000002 -#define CONFIG_SYS_POST_MEMORY 0x00000004 +#define CFG_SYS_POST_MEMORY 0x00000004 #define CONFIG_SYS_POST_CPU 0x00000008 #define CONFIG_SYS_POST_I2C 0x00000010 #define CONFIG_SYS_POST_CACHE 0x00000020 @@ -163,7 +163,7 @@ extern int memory_post_test(int flags); #define CONFIG_SYS_POST_CODEC 0x00200000 #define CONFIG_SYS_POST_COPROC 0x00400000 #define CONFIG_SYS_POST_FLASH 0x00800000 -#define CONFIG_SYS_POST_MEM_REGIONS 0x01000000 +#define CFG_SYS_POST_MEM_REGIONS 0x01000000 #endif /* CONFIG_POST */ diff --git a/include/serial.h b/include/serial.h index fe01bcfadb9..f4d7dc58a9e 100644 --- a/include/serial.h +++ b/include/serial.h @@ -14,7 +14,7 @@ struct serial_device { int (*tstc)(void); void (*putc)(const char c); void (*puts)(const char *s); -#if CONFIG_POST & CONFIG_SYS_POST_UART +#if CFG_POST & CONFIG_SYS_POST_UART void (*loop)(int); #endif struct serial_device *next; @@ -242,7 +242,7 @@ struct dm_serial_ops { * @return 0 if OK, -ve on error */ int (*clear)(struct udevice *dev); -#if CONFIG_POST & CONFIG_SYS_POST_UART +#if CFG_POST & CONFIG_SYS_POST_UART /** * loop() - Control serial device loopback mode * diff --git a/include/spl.h b/include/spl.h index 3eb27de6166..fb8c279d726 100644 --- a/include/spl.h +++ b/include/spl.h @@ -470,7 +470,7 @@ void spl_set_bd(void); * spl_set_header_raw_uboot() - Set up a standard SPL image structure * * This sets up the given spl_image which the standard values obtained from - * config options: CONFIG_SYS_MONITOR_LEN, CONFIG_SYS_UBOOT_START, + * config options: CONFIG_SYS_MONITOR_LEN, CFG_SYS_UBOOT_START, * CONFIG_TEXT_BASE. * * @spl_image: Image description to set up diff --git a/include/system-constants.h b/include/system-constants.h index 83b41b384f3..0d6b71b35a0 100644 --- a/include/system-constants.h +++ b/include/system-constants.h @@ -12,10 +12,10 @@ #define SYS_INIT_SP_ADDR CONFIG_CUSTOM_SYS_INIT_SP_ADDR #else #ifdef CONFIG_MIPS -#define SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET) +#define SYS_INIT_SP_ADDR (CFG_SYS_SDRAM_BASE + CFG_SYS_INIT_SP_OFFSET) #else #define SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) + (CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #endif #endif diff --git a/include/tca642x.h b/include/tca642x.h index bda86c1ed88..c0a3cef5bd5 100644 --- a/include/tca642x.h +++ b/include/tca642x.h @@ -41,13 +41,13 @@ enum { #define TCA642X_DIR_IN 1 /* Default to an address that hopefully won't corrupt other i2c devices */ -#ifndef CONFIG_SYS_I2C_TCA642X_ADDR -#define CONFIG_SYS_I2C_TCA642X_ADDR (~0) +#ifndef CFG_SYS_I2C_TCA642X_ADDR +#define CFG_SYS_I2C_TCA642X_ADDR (~0) #endif /* Default to an address that hopefully won't corrupt other i2c devices */ -#ifndef CONFIG_SYS_I2C_TCA642X_BUS_NUM -#define CONFIG_SYS_I2C_TCA642X_BUS_NUM (0) +#ifndef CFG_SYS_I2C_TCA642X_BUS_NUM +#define CFG_SYS_I2C_TCA642X_BUS_NUM (0) #endif struct tca642x_bank_info { diff --git a/include/tsec.h b/include/tsec.h index 72f34851ad1..de279b21171 100644 --- a/include/tsec.h +++ b/include/tsec.h @@ -124,8 +124,8 @@ #define RCTRL_PROM 0x00000008 -#ifndef CONFIG_SYS_TBIPA_VALUE -# define CONFIG_SYS_TBIPA_VALUE 0x1f +#ifndef CFG_SYS_TBIPA_VALUE +# define CFG_SYS_TBIPA_VALUE 0x1f #endif #define MRBLR_INIT_SETTINGS PKTSIZE_ALIGN |