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2019-04-09test: fs: disable the metadata checksums on ext4 filesystemsJean-Jacques Hiblot
If the metadata checksums are enabled, all write operations will fail. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-04-09fs: ext4: cache extent dataStephen Warren
When a file contains extents, U-Boot currently reads extent-related data for each block in the file, even if that data is located in the same block each time. This significantly slows down loading of files that use extents. Implement a very dumb cache to prevent repeatedly reading the same block. Files with extents now load as fast as files without. Note: There are many cases where read_allocated_block() is called. This patch only addresses one of those places; all others still read redundant data in any case they did before. This is a minimal patch to fix the load command; other cases aren't fixed. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2019-04-09Merge branch 'master' of git://git.denx.de/u-boot-ubiTom Rini
2019-04-09Merge tag 'u-boot-atmel-2019.07-a' of git://git.denx.de/u-boot-atmelTom Rini
First set of u-boot-atmel features and fixes for 2019.07 cycle
2019-04-09net: macb: Add small delay after link establishmentStefan Roese
I've noticed that the first ethernet packet after PHY link establishment is not tranferred correctly most of the time on my AT91SAM9G25 board. Here I usually see a timeout of a few seconds, which is quite annoying. Adding a small delay (10ms in this case) after the link establishment helps to solve this problem. With this patch applied, this timeout on the first packet is not seen any more. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Wenyou Yang <wenyou.yang@atmel.com> Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-04-09pinctrl: at91: add slewrate support for SAM9X60Claudiu Beznea
Add slew rate support for SAM9X60 pin controller. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2019-04-09pinctrl: at91: add compatibles for SAM9X60 pin controllerClaudiu Beznea
Add compatibles for SAM9X60 pin controller. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2019-04-09pinctrl: at91: add drive strength support for SAM9X60Claudiu Beznea
Add drive strength support for SAM9X60 pin controller. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2019-04-09pinctrl: at91: add option to use drive strength bitsClaudiu Beznea
SAM9X60 uses high and low drive strengths. To implement this, in at91_pinctrl_mux_ops::set_drivestrength we need bit numbers of drive strengths (1 for low, 2 for high), thus change the code to allow the usage of drive strength bit numbers. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2019-04-09arm: at91: Add gardena-gateway-at91sam supportStefan Roese
The GARDENA smart Gateway boards are equipped with an Atmel / Microchip AT91SAM9G25 SoC and with 128 MiB of RAM and 256 MiB of NAND storage. This patch adds support for this board including SPL support. Therefore the AT91Boostrap is not needed on this platform any more. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Andreas Bießmann <andreas@biessmann.org> Cc: Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2019-04-09arm: at91: at91sam9x5.dtsi: Add watchdog handleStefan Roese
This makes it possible to reference the watchdog DT node via "&watchdog" from board dts files. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Andreas Bießmann <andreas@biessmann.org> Cc: Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2019-04-09arm: at91: siemens: Add support to generate combined SPL+U-Boot imageStefan Roese
This patch adds the necessary defines to the Siemens AT91SAM based boards (smartweb, corvus and taurus) to generate the combined binary image with SPL and main U-Boot image combined (u-boot-with-spl.bin). Signed-off-by: Stefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Andreas Bießmann <andreas@biessmann.org> Cc: Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by: Heiko Schocher <hs@denx.de> Tested on the taurus board: Tested-by: Heiko Schocher <hs@denx.de>
2019-04-09Makefile: Add Kconfig option CONFIG_SPL_IMAGE to select the SPL binaryStefan Roese
This patch adds the CONFIG_SPL_IMAGE option to select the SPL image that shall be used to generate the combined SPL + U-Boot image. The default value is the current value "spl/u-boot-spl.bin". This patch also sets CONFIG_SPL_IMAGE to "spl/boot.bin" for AT91 targets which use SPL NAND support (boot from NAND). For these build targets the combined image "u-boot-with-spl.bin" is now automatically generated and can be programmed into NAND as one single image (vs. SPL image and U-Boot as 2 separate images). Signed-off-by: Stefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Andreas Bießmann <andreas@biessmann.org> Cc: Eugen Hristev <eugen.hristev@microchip.com>
2019-04-09Makefile.spl: Move generated AT91SAM NAND image boot.bin to spl directoryStefan Roese
This patch moves the AT91SAM NAND booting SPL image "boot.bin" which includes the ECC values from the root directory into the spl directory, where all SPL related images are located. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Andreas Bießmann <andreas@biessmann.org> Cc: Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by: Heiko Schocher <hs@denx.de> Tested on the taurus board: Tested-by: Heiko Schocher <hs@denx.de>
2019-04-09arm: at91: arm926ejs/u-boot-spl.lds: Add _image_binary_end to SPL ldsStefan Roese
This patch adds _image_binary_end to the SPL linker script. This will be used be the upcoming GARDENA AT91SAM based platform, which uses DT in SPL and configures CONFIGURE_SPL_SEPARATE_BSS. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Andreas Bießmann <andreas@biessmann.org> Cc: Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2019-04-09arm: at91: Enable watchdog supportStefan Roese
This patch enables and starts the watchdog on the AT91 platform if configured. The WD timeout value is read in the AT91 WD device driver from the DT, using the "timeout-sec" DT property. If not provided in the DT, the default value of 2 seconds is used. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Andreas Bießmann <andreas@biessmann.org> Cc: Eugen Hristev <eugen.hristev@microchip.com>
2019-04-09arm: at91: Remove CONFIG_AT91_HW_WDT_TIMEOUTStefan Roese
This patch removes the CONFIG_AT91_HW_WDT_TIMEOUT as its not needed any more. The WD timeout value can be provided via the "timeout-sec" DT property. If not provided this way, the default value of 2 seconds will be used. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Andreas Bießmann <andreas@biessmann.org> Cc: Eugen Hristev <eugen.hristev@microchip.com>
2019-04-09watchdog: at91sam9_wdt: Fix WDT setup in at91_wdt_start()Stefan Roese
This patch fixes the timer register setup in at91_wdt_start() to correctly configure the register again. The input timeout value is now in milli-seconds instead of seconds with the new watchdog API. Make sure to take this into account and only use a max timeout value of 16 seconds as appropriate for this SoC. Also the check against a lower timeout value than 0 is removed. This check makes no sense, as the timeout value is unsigned. Signed-off-by: Stefan Roese <sr@denx.de> Reported-by: Heiko Schocher <hs@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Andreas Bießmann <andreas@biessmann.org> Cc: Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by: Heiko Schocher <hs@denx.de> Tested on the taurus board: Tested-by: Heiko Schocher <hs@denx.de>
2019-04-09watchdog: Handle SPL build with watchdog disabledStefan Roese
This patch adds some checks, so that the watchdog can be enabled in main U-Boot proper but can be disabled in SPL. This will be used by some AT91SAM based boards, which might enable the watchdog in the main U-Boot proper and not in SPL. It will be enabled in SPL by default there, so no need to configure it there. This approach saves some space in SPL. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Andreas Bießmann <andreas@biessmann.org> Cc: Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by: Heiko Schocher <hs@denx.de> Tested on the taurus board: Tested-by: Heiko Schocher <hs@denx.de>
2019-04-09serial: atmel_usart: Use fixed clock value in SPL version with DM_SERIALStefan Roese
This patch adds an alterative SPL version of atmel_serial_enable_clk(). This enables the usage of this driver without full clock support (in drivers and DT nodes). This saves some space in the SPL image. Please note that this fixed clock support is only added to the SPL code in the DM_SERIAL part of this file. All boards not using SPL & DM_SERIAL should not be affected. This patch also introduces CONFIG_SPL_UART_CLOCK for the fixed UART input clock. It defaults to 132096000 for ARCH_AT91 but can be set to a different value if needed. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Andreas Bießmann <andreas@biessmann.org> Cc: Eugen Hristev <eugen.hristev@microchip.com>
2019-04-09arm: at91: spl_at91.c: Call spl_early_init() if OF_CONTROL is enabledStefan Roese
This patch adds a call to spl_early_init() to board_init_f() which is needed when CONFIG_SPL_OF_CONTROL is configured. This is necessary for the early SPL setup including the DTB setup for later usage. Please note that this call might also be needed for non SPL_OF_CONTROL board, like the smartweb target. But smartweb fails to build with this call because its binary grows too big. So I disabled it for these kind of targets for now. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Andreas Bießmann <andreas@biessmann.org> Cc: Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by: Heiko Schocher <hs@denx.de> Tested on the taurus board: Tested-by: Heiko Schocher <hs@denx.de>
2019-04-09arm: at91: Makefile: Compile lowlevel_init only when really necessaryStefan Roese
Make sure that lowlevel_init is not compiled when CONFIG_SKIP_LOWLEVEL_INIT_ONLY is configured. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Andreas Bießmann <andreas@biessmann.org> Cc: Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by: Heiko Schocher <hs@denx.de> Tested on the taurus board: Tested-by: Heiko Schocher <hs@denx.de>
2019-04-09board: pm9g45: Migrate to CONFIG_DMIlko Iliev
Migrate the following options to CONFIG_DM: CONFIG_DM_GPIO CONFIG_DM_MMC CONFIG_DM_ETH CONFIG_DM_SERIAL CONFIG_DM_USB Signed-off-by: Ilko Iliev <iliev@ronetix.at>
2019-04-09ARM: at91: sama5d2: Wrap cpu detection to fix macb driverAlexander Dahl
When introducing the SAMA5D27 SoCs, the SAMA5D2 series got an additional chip id. The check if the cpu is sama5d2 was changed from a preprocessor definition (inlining a call to 'get_chip_id()') to a C function, probably to not call get_chip_id twice? That however broke a check in the macb ethernet driver. That driver is more generic and also used for other platforms. I suppose this solution was implemented to use it in 'gem_is_gigabit_capable()', without having to stricly depend on the at91 platform: #ifndef cpu_is_sama5d2 #define cpu_is_sama5d2() 0 #endif That only works as long as cpu_is_sama5d2 is a preprocessor definition. (The same is still true for sama5d4 by the way.) So this is a straight forward fix for the workaround. The not working check on the SAMA5D2 CPU lead to an issue on a custom board with a LAN8720A ethernet phy connected to the SoC: => dhcp ethernet@f8008000: PHY present at 1 ethernet@f8008000: Starting autonegotiation... ethernet@f8008000: Autonegotiation complete ethernet@f8008000: link up, 1000Mbps full-duplex (lpa: 0xffff) BOOTP broadcast 1 BOOTP broadcast 2 BOOTP broadcast 3 BOOTP broadcast 4 BOOTP broadcast 5 BOOTP broadcast 6 BOOTP broadcast 7 BOOTP broadcast 8 BOOTP broadcast 9 BOOTP broadcast 10 BOOTP broadcast 11 BOOTP broadcast 12 BOOTP broadcast 13 BOOTP broadcast 14 BOOTP broadcast 15 BOOTP broadcast 16 BOOTP broadcast 17 Retry time exceeded; starting again Notice the wrong reported link speed, although both SoC and phy only support 100 MBit/s! The real issue on reliably detecting the features of that cadence ethernet mac IP block, is probably more complicated, though. Fixes: 245cbc583d ("ARM: at91: Get the Chip ID of SAMA5D2 SiP") Signed-off-by: Alexander Dahl <ada@thorsis.com>
2019-04-09mtd: ubi, ubifs debug: Use pr_debug instead of pr_critEran Matityahu
Before printk.h was introduced and MTDDEBUG was removed, pr_crit() was calling MTDDEBUG(), which was since then replaced by the current pr_debug(). pr_debug is more appropriate here. Signed-off-by: Eran Matityahu <eran.m@variscite.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2019-04-09mtd: ubi debug: Remove the pid print from ubi_assertEran Matityahu
Add a new definition for ubi_assert and keep the original one in an ifndef __UBOOT__. Signed-off-by: Eran Matityahu <eran.m@variscite.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2019-04-08Merge tag 'efi-2019-07-rc1' of git://git.denx.de/u-boot-efiTom Rini
Pull request for UEFI sub-system for v2019.07-rc1 The patch series adds support for the BootNext and BootCurrent variables. The rest is mostly bug fixes. With the bug fixes in place it becomes possible to use the EFI Shell `edit` command. A new unit test is supplied to check the image base and size fields of the loaded image protocol. An inline check when freeing memory from the pool safeguards against double frees.
2019-04-08Merge git://git.denx.de/u-boot-riscvTom Rini
- RISC-V arch support SMP. - Support Andestech's PLIC and PLMT. - qemu, fu54e, ae350 boards enable SMP by default. - Fix CONFIG_DEFAULT_DEVICE_TREE failure.
2019-04-08Prepare v2019.04Tom Rini
Signed-off-by: Tom Rini <trini@konsulko.com>
2019-04-08arm: sunxi: Enable DM_MMC on required SoCsJagan Teki
Enabling DM_MMC is forcing CONFIG_BLK=y so if any board which uses SCSI must need to enable DM_SCSI otherwise SCSI reads on that particular target making invalid reading to the disk drive. Allwinner platform do support SCSI on A10, A20 and R40 SoC's out of these only A10 have DM_SCSI enabled. So enabling DM_MMC on A20, R40 would eventually end-up with scsi disk read failures like [1] So, enable DM_MMC in all places of respective SoC's instead of enabling them globally to Allwinner platform. Now, DM_MMC is enabled in Allwinner SoC's except A20 and R40. [1] https://lists.denx.de/pipermail/u-boot/2019-April/364057.html Reported-by: Pablo Sebastián Greco <pgreco@centosproject.org> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-04-08Merge tag 'fixes-for-2019.04-rc4' of git://git.denx.de/u-boot-stagingTom Rini
- i.MX8QXP-MEK ethernet fix
2019-04-08dts: imx8qxp-mek: Add PHY post reset delayAndrejs Cainikovs
PHY cannot be detected unless we wait about 150 ms. Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@netmodule.com> Reviewed-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-04-08net: dm: fec: Support phy-reset-post-delay propertyAndrejs Cainikovs
As per Linux kernel DT binding doc: - phy-reset-post-delay : Post reset delay in milliseconds. If present then a delay of phy-reset-post-delay milliseconds will be observed after the phy-reset-gpios has been toggled. Can be omitted thus no delay is observed. Delay is in range of 1ms to 1000ms. Other delays are invalid. Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@netmodule.com> Reviewed-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Lukasz Majewski <lukma@denx.de>
2019-04-08watchdog: Move watchdog_dev to data section (BSS may not be cleared)Stefan Roese
This patch moves all instances of static "watchdog_dev" declarations to the "data" section. This may be needed, as the BSS may not be cleared in the early U-Boot phase, where watchdog_reset() is already beeing called. This may result in incorrect pointer access, as the check to "!watchdog_dev" in watchdog_reset() may not be true and the function may continue to run. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: "Marek Behún" <marek.behun@nic.cz> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Tested-by: Michal Simek <michal.simek@xilinx.com> (on zcu100) Reviewed-by: Michal Simek <michal.simek@xilinx.com>
2019-04-08riscv: dts: fix CONFIG_DEFAULT_DEVICE_TREE failureRick Chen
It occurs since commit 27cb7300ffda ("Ensure device tree DTS is compiled"). More details can refer to 89c2b5c02049aea746b1edee0b4e1d8519dec2f4 ARM: fix arch/arm/dts/Makefile Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-04-08riscv: ae350: enable SMPRick Chen
Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-04-08riscv: dts: ae350 support SMPRick Chen
Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-04-08riscv: ax25: Andes specific cache shall only support in M-modeRick Chen
Limit the cache configuration only can be supported in M mode. It can not be manipulated in S mode. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-04-08riscv: ax25: Add platform-specific Kconfig optionsRick Chen
Add ax25 RISC-V platform-specific Kconfig options, to include CPU and timer drivers. Also disable ATCPIT100 SoC timer and replace by PLMT. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-04-08riscv: Add a SYSCON driver for Andestech's PLMTRick Chen
The platform-Level Machine Timer (PLMT) block holds memory-mapped mtime register associated with timer tick. This driver implements the riscv_get_time() which is required by the generic RISC-V timer driver. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-04-08riscv: Add a SYSCON driver for Andestech's PLICRick Chen
The Platform-Level Interrupt Controller (PLIC) block holds memory-mapped claim and pending registers associated with software interrupt. It is required for handling IPI. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-04-08riscv: qemu: enable SMPLukas Auer
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-04-08riscv: fu540: enable SMPLukas Auer
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-04-08riscv: hang if relocation of secondary harts failsLukas Auer
Print an error message and hang if smp_call_function() returns an error, indicating that relocation of the secondary harts has failed. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2019-04-08riscv: do not rely on hart ID passed by previous boot stageLukas Auer
RISC-V U-Boot expects the hart ID to be passed to it via register a0 by the previous boot stage. Machine mode firmware such as BBL and OpenSBI do this when starting their payload (U-Boot) in supervisor mode. If U-Boot is running in machine mode, this task must be handled by the boot ROM. Explicitly populate register a0 with the hart ID from the mhartid CSR to avoid possible problems on RISC-V processors with a boot ROM that does not handle this task. Suggested-by: Rick Chen <rick@andestech.com> Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com> Tested-by: Rick Chen <rick@andestech.com>
2019-04-08riscv: boot images passed to bootm on all hartsLukas Auer
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-04-08riscv: add support for multi-hart systemsLukas Auer
On RISC-V, all harts boot independently. To be able to run on a multi-hart system, U-Boot must be extended with the functionality to manage all harts in the system. All harts entering U-Boot are registered in the available_harts mask stored in global data. A hart lottery system as used in the Linux kernel selects the hart U-Boot runs on. All other harts are halted. U-Boot can delegate functions to them using smp_call_function(). Every hart has a valid pointer to the global data structure and a 8KiB stack by default. The stack size is set with CONFIG_STACK_SIZE_SHIFT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-04-08riscv: save hart ID in register tp instead of s0Lukas Auer
The hart ID passed by the previous boot stage is currently stored in register s0. If we divert the control flow inside a function, which is required as part of multi-hart support, the function epilog may not be called, clobbering register s0. Save the hart ID in the unallocatable register tp instead to protect the hart ID. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2019-04-08riscv: delay initialization of caches and debug UARTLukas Auer
Move the initialization of the caches and the debug UART until after board_init_f_init_reserve. This is in preparation for SMP support, where code prior to this point will be executed by all harts. This ensures that initialization will only be performed once on the main hart running U-Boot. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-04-08riscv: implement IPI platform functions using SBILukas Auer
The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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