Age | Commit message (Collapse) | Author |
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1. Set dpgdck0_2_en to 0 when required freq is lower than 300Mhz.
2. When dpgdck0_2_en is 0, the formula to calculate output freq
will be changed to 2 * freq * [].
Signed-off-by: Terry Lv <r65388@freescale.com>
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In mx35, when testing TVIN, the screen will flick.
We find that flickers will get better when using ESDCTL_0x82226080
against ESDCTL_0x82228080 for register SCDCTL0.
The origin value ESDCTL_0x82228080 in lowlevel_init.S will be called in
external boot which will reduce the bandwidth.
Signed-off-by: Terry Lv <r65388@freescale.com>
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mx53 evk mmu wrong mapped two csd slots.
Actually evk only has one slot.
Signed-off-by: Terry Lv <r65388@freescale.com>
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Change fastboot code for that fastboot uses mmc command to access card.
Thus the code need to be modified to new mmc command.
Signed-off-by: Terry Lv <r65388@freescale.com>
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This patch will enhance mmc command.
1. Add erase command.
2. Abandon dev_no in mmc command. User need to switch slot with "mmc
dev" command.
3. Add mmc part switch command. Enhance partition switch support.
4. Add mmc bootpart. Boot partition support is more flexible.
Signed-off-by: Terry Lv <r65388@freescale.com>
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Trivial change to remove build warnings.
Signed-off-by: Terry Lv <r65388@freescale.com>
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Modifications on config files.
1. Remove CONFIG_BOOT_PARTITION_ACCESS.
2. Change all mmc read command in default env configs.
Signed-off-by: Terry Lv <r65388@freescale.com>
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MX53 SMD hangs if reset many times with lower possibility.
If doing I2C access in early time, I2C may cause system hangs.
So moving I2C access to late phase to make system hang issue disappear.
QA Test result: QA raised 6 full rounds of CTS one-round test
Totally ran for 6 rounds about 27 hours, reboot for 56*6=336 times,
no reboot failure occurred.
Signed-off-by: Wayne Zou <b36644@freescale.com>
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to fix we should amend systemrev in uboot, add new board RevB for it
Signed-off-by: Robin Gong <B38343@freescale.com>
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1. As customer required, we change to use rom plugins for mx53 boards.
Tested pass with latest mfg tools.
2. Update DDR3 script based on MX53_TO2_DDR3_LCB_SMD_ARDb_v2.inc.
Got from
http://compass.freescale.net/livelink/livelink?func=ll
&objId=221058910&objAction=browse&viewType=1.
3. Fix a tiny build error in mx53_smd.c.
This error will happen when building mx53_smd_mfg.
Signed-off-by: Terry Lv <r65388@freescale.com>
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remove printf() because serial interface is not ready in board_init()
Signed-off-by: Wayne Zou <b36644@freescale.com>
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Init clocks, phy and pll for sata.
Signed-off-by: Terry Lv <r65388@freescale.com>
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Kernel stops at USB driver initialization if suspending,
resuming and resetting the board.
It's because VUSB_2V5 voltage is disabled after suspend.
Need to re-enable it mannually into U-boot
Signed-off-by: Lily Zhang <r58066@freescale.com>
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1. ENET don't need to enable ENET pll clock;
2. Enable cpu debug clock in case of using JTAG;
3. Clean up some debug info during bring up.
Signed-off-by: Anson Huang <b20788@freescale.com>
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when board boots up, during the iMX53 SOC does DA9053 Read/Write
operation, it writes slave address and wait for ACK . Instead of ACK
PMIC sends NAK. A workaround fix is provided as a part of retries to
fix I2C NAK for very first access.
Signed-off-by: Wayne Zou <b36644@freescale.com>
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set Ripley AUX input current limit to 950mA and
set charge termination current to 400mA
Signed-off-by: Wayne Zou <b36644@freescale.com>
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Default boot up with the 7' LCD on.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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We should disabel some clocks in uboot to save
power, or when we download from enet to boot up
kernel, the power consumption could be up 800mA@5V,
may damage the chip.
After apply it, we can save more then 200mA@5V.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Change env size to 8K and change gpmi nand env offset to 2M.
This will reduce boot time and fix gpmi nand env problem.
Signed-off-by: Terry Lv <r65388@freescale.com>
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update Ripley USB and AUX/DC charger settings for pcba revB board
Signed-off-by: Wayne Zou <b36644@freescale.com>
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Add DC-IN power supply support for revB board when booting from EMMC.
set both AUX&USB current limit to 1.5A for Ripley 2.1 only
Change CC current to 950mA
Signed-off-by: Wayne Zou <b36644@freescale.com>
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Update DDR DCD configuration
Open all the clocks during boot
Change CV voltage to 4.2V
Signed-off-by: Weihua Zou <wayne.zou@freescale.com>
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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to avoid ipu starvation issue.
1. enable IPU AXI cache in uboot
2. set Qos to 7 for IPU to highest priority in uboot.
3. set AXI id to 0 for high priority IDMA channel in linux.
Signed-off-by: Jason Chen <b02280@freescale.com>
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In mx51 configuration, CONFIG_BOOT_PARTITION_ACCESS is not defined.
This cause build error to fastboot.c
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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Add new machine type for pcba.
Add UART, I2C, SD/MMC, PMIC, DDR initial support.
Add MFG tool support.
Add support for MC34708 on revB pcba board.
Update VDDGP setting on MC34708 PMIC for revB board.
Close unused clock, for fastboot it will enable usb_phy
usb_oh3 clock by itself, still need to verify this work
or not when revB bootup.
Signed-off-by: Wayne Zou <b36644@freescale.com>
Signed-off-by: Lily Zhang <r58066@freescale.com>
Signed-off-by: Jason Liu <r64343@freescale.com>
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uboot image cannot be burned to boot partition for eMMC 4.3. This
patch will fix it.
Signed-off-by: Sammy He <r62914@freescale.com>
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Enable auto self-refresh of MMDC to save power
when memory idle.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Change DCDC_3V15's GPIO setting for REV-D.
Signed-off-by: Anson Huang <b20788@freescale.com>
(cherry picked from commit 28a8e166c6a8fa001325f88ef06e5a81f6ed82a9)
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This patch is used to support watchdog timeout in SMD RevA, RevB
board.
1. Revert "ENGR00143469 mx53 smd: pull down GPIO_9 to reset the
board".
2. Force warm reset as cold reset.
Signed-off-by: Lily Zhang <r58066@freescale.com>
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Updated mx53 ddr3 script according to MX53_TO2_DDR3_LCB_SMD_ARDb_v1.inc
from Michael J Kjar on July 8, 2011:
-change ESDREF[REF_SEL]=01 (for 32KHz), from incorrect setting of 00 (64KHz)
-change DDR3 MR0 write to "setmem /32 0x63fd901c = 0x052080b0" from
"0x092080b0". This chagned write recovery from 8 clocks to 6 clocks
(in line with ESDCFG1[tWR])
Signed-off-by: Lily Zhang <r58066@freescale.com>
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Use simple enviroment to implement the default boot command.
The original one is too complex, and not readable.
For MX51BBG, only SD card boot env is supportd by default.
For MX53SMD, only eMMC boot env is supportd by default.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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Drop NAND/SPI boot support.
Enable fastboot.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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update default cmdline to align with Document.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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ROM requires DCD table instead of plugin to initialize DRAM if emmc fastboot
mode is to be used. Therefore, switched the DRAM script from plugin to
DCD table. The DCD table created is based on the following RVD script:
Arik_init_DDR3_528MHz_002.inc found at
http://compass.freescale.net/livelink/livelink?func=ll&objId=222928845
When fastboot mode is used by ROM, the MMC_BOOT register of USDHC does not
get reset when RSTA bit is set by uboot driver. Therefore, need to write 0
to it manually during driver init. This brings USDHC out of fastboot mode,
allowing normal communication with emmc to proceed in uboot.
Changed comments for DLL delay to be more accurate.
Signed-off-by: Anish Trivedi <anish@freescale.com>
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New bit definitions in USDHC.
Added is_usdhc variable to fsl_esdhc_cfg to distinguish between ESDHC
and USDHC.
Enabled DDR mode support in USDHC.
Created a config to customize target delay for DDR mode.
Modified USDHC pad settings to make DDR mode work for all emmcs at 50 MHz.
Signed-off-by: Anish Trivedi <anish@freescale.com>
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Make sure the PLL workaround is done only for PLL1.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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In precode, PHY forced to work at 100M even connect to
1G switch.
In this commit, let PHY auto negotiate it working speed. Enet tx
work at store-and-forward mode.
BTW, AR8031 take quite a long time, about 1.6s from negotiation to link up.
we have to wait and then set ENET correctly.
Signed-off-by: Zeng Zhaoming <b32542@freescale.com>
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Add ENET and AR8031 PHY support to uboot.
To make it works on sabreauto, need do following changes:
1. rework phy to output 125M clock from CLK_25M signal,
and the 125M clock input to SoC as reference clock to generate
RGMII_TXC clock.
2. Enable TXC delay in PHY debug register.
3. set ENET working in RMII mode.
4. set ENET working at 1000M or 100M/10M.
5. set ENET TX fifo to maximum to avoid underrun error.
6. force AR8031 PHY working at 100M
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Zeng Zhaoming <b32542@freescale.com>
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Use 528M DDR script
Disable L2 cache because rom enable L2 cache when use plug-in
Fix usdhc pad settings
Remove mac address hardcode
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Richard Zhu <r65037@freescale.com>
Signed-off-by: Terry Lv <r65388@freescale.com>
Signed-off-by: Anish Trivedi <anish@freescale.com>
Signed-off-by: Jason Liu <r64343@freescale.com>
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Apply the following SW workaround to fix the PLL unlock issue.
1.Move all the clock sources which are currently running
on PLL1 from PLL1 to PLL2
2.Clear AREN bit in PLL1 (to avoid restart during MFN change)
3.Program the PLL1 to the next settings:
a. MFI = 8
b. MFD = 179
c. MFN = 180
d. PLM = 1
4.Manually restart the PLL1
5.Wait to PLL1 to lock
6.Reprogram the PLL1 to the next settings:
a. MFI = 60, others keep same
7.Load the MFN
8.Wait for LDREQ and delay ~4.6us
9.Switch the clocks which were previously moved from PLL1 to PLL2 back to PLL1
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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PLL1 workaround to prevent it from losing lock:
(1) Disable AREN bit to avoid PLL1 restart during MFN change
(2) set PLL1 to ~864Mhz with MFI = 8, MFN = 180, MFD = 179, PDF = 0
(3) Manual restart PLL1
(4) Wait PLL1 lock
(5) Set PLL1 to 800Mhz with only change MFN to 60, others keep
(6) Set LDREQ bit to load new MFN
(7) Poll on LDREQ bit for MFN update to be completed
(8) Delay at least 4 us to avoid PLL1 instability window
(9) Switch ARM back to PLL1
Signed-off-by: Anish Trivedi <anish@freescale.com>
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After reseting in stop mode, the VUSB_2V5 voltage is disable by pmic.
It needs to be enable manually in u-boot.
Signed-off-by: Wayne Zou <b36644@freescale.com>
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Not all peripherals are mapped in MMU.
Thus we add those missed mapped area.
Signed-off-by: Terry Lv <r65388@freescale.com>
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Change VCC from 1.35V to 1.3V QS Ripley board
Signed-off-by: Wayne Zou <b36644@freescale.com>
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Change the recovery boot for MX53_SMD to emmc 's device 1.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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Enable NAND gpio, recovery mode detect after boot from spi nor.
Change default env for loading kernel and uramdisk from NAND,
disabling elcdif lcd driver to support EPDC eink panel as default.
Enable recovery mode support and NAND/UBI/UBIFS command.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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Nand oobsize is wrong in some nand chips.
Signed-off-by: Terry Lv <r65388@freescale.com>
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For clk command always make console output mess characters,
here we reinitilize it after clock is changed.
Signed-off-by: Terry Lv <r65388@freescale.com>
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Add mc34708 pmic support on loco/Ripley board
Signed-off-by: Zou Weihua -wayne zou <b36644@freescale.com>
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Change the default environment setting as sd boot for mx53
loco, mx53 smd and mx53 ard boards.
Signed-off-by: Lily Zhang <r58066@freescale.com>
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