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2021-05-16arm64: mvebu: a8k: align memory regionsjinghua
1. RAM: base address 0x0 size 2Gbytes 2. MMIO: base address 0xf0000000 size 1Gbytes Signed-off-by: Ofir Fedida <ofedida@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2021-05-16spi: kirkwood: prevent limiting speed to 0Grzegorz Jaszczyk
After commit 1fe929ed497bcc8975be8d37383ebafd22b99dd2 ("spi: kirkwood: prevent configuring speed exceeding max controller freq") the spi frequency could be set to 0 on platform where spi-max-frequency is not defined (e.g. on armada-388-gp). Prevent limiting speed in mentioned cases. Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Tested-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-by: Marcin Wojtas <marcin@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2021-05-16spi: kirkwood: prevent configuring speed exceeding max controller freqMarcin Wojtas
This patch adds a limitation in the kirkwood_spi driver set_speed hook, which prevents setting too high transfer speed. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: Kostya Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2021-05-16spi: kirkwood: support extended baud ratesKen Ma
The Armada SoC family implementation of this SPI hardware module has extended the configuration register to allow for a wider range of SPI clock rates. Specifically the Serial Baud Rate Pre-selection bits in the SPI Interface Configuration Register now also use bits 6 and 7 as well. Modify the baud rate calculation to handle these differences for the Armada case. Potentially a baud rate can be setup using a number of different pre-scalar and scalar combinations. This code tries all possible pre-scalar divisors (8 in total) to try and find the most accurate set. Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2021-05-16mvebu: x530: Reduce SPL image sizeStefan Roese
Currently, building U-Boot for x530 fails since the SPL image is too big. This patch reduces the SPL size by changing the following Kconfig options: Enable CONFIG_SPL_TINY_MEMSET Disable CONFIG_SPI_FLASH_BAR By disabling CONFIG_SPI_FLASH_BAR, the tiny SPI NOR framework can be used. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Cc: Pratyush Yadav <p.yadav@ti.com> Cc: Tom Rini <trini@konsulko.com> Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Acked-by: Pratyush Yadav <p.yadav@ti.com>
2021-05-15configs: Resync with savedefconfigTom Rini
Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
2021-05-14Merge https://source.denx.de/u-boot/custodians/u-boot-shTom Rini
2021-05-14Merge tag 'u-boot-amlogic-20210514' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-amlogic - dts: add missing -u-boot.dtsi to enable HDMI on Beelink GTKing/King-Pro - usb: dwc3-meson-g12a: skip phy on -ENODATA aswell - net: dwmac_meson8b: do not set TX delay in TXID & RXID - net: designware: meson8b: add g12a compatible
2021-05-14Merge https://source.denx.de/u-boot/custodians/u-boot-riscvTom Rini
2021-05-14net: designware: meson8b: add g12a compatibleNeil Armstrong
Add support for the Meson G12A dwmac glue compatible needed after Linux 5.12 sync. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-05-14net: dwmac_meson8b: do not set TX delay in TXID & RXIDNeil Armstrong
When the PHY interface is set as TXID & RXID, the delays should be taken from DT, but first they should not be hardcoded since the PHY driver will set them. Fixes: 798424e857 ("net: designware: add Amlogic Meson8b & later glue driver") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-05-14usb: dwc3-meson-g12a: skip phy on -ENODATA aswellNeil Armstrong
If the PHY isn't specified in the DT, -ENODATA means it should be skipped, handle it like -ENOENT. With that, devices without USB3 supported can have USB working (Odroid-HC4). Fixes: adb049abf7 ("usb: dwc3: Add Meson G12A USB Glue") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-05-14ARM: dts: add missing -u-boot.dtsi to enable HDMI on Beelink GTKing/King-ProNeil Armstrong
This lacks the right u-boot specific DT include to make HDMI work. Reported-by: B1oHazard <ty3uk@mail.ua> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-05-14Revert "riscv: cpu: fu740: clear feature disable CSR"Bin Meng
This reverts commit bc8bbb77f74f21582b3bfd790334397757f88575. This commit breaks U-Boot booting on SiFive Unleashed board, as there is no such CSR on U54 core. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-05-14pwm: sifive: make set_config() and set_enable() work properlyVincent Chen
The pwm_sifive_set_config() and pwm_sifive_set_enable() cannot work properly due to the wrong implementations. It will cause the u-boot PWM command to not work as expected. The bugs will be resolved in this patch. Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
2021-05-14riscv: Don't reserve AI ram in k210 dtsSean Anderson
It is no longer necessary to disallow ai ram, since it is enabled by the sram driver. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2021-05-14riscv: k210: Use AI as the parent clock of aisram, not PLL1Sean Anderson
Testing showed that disabling AI while leaving PLL1 enabled disabled the aisram. This suggests that AI is a more appropriate clock for that ram bank. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2021-05-14riscv: k210: Rename airam to aisramSean Anderson
This is more consistent with the naming of other ram banks, and matches what Linux is doing. Reported-by: Damien Le Moal <Damien.LeMoal@wdc.com> Signed-off-by: Sean Anderson <seanga2@gmail.com>
2021-05-14riscv: Enable AI ram on K210Sean Anderson
We just need to initialize all the clocks pre-reloc. The clock driver creates a bunch of devices, so we need to increase the pre-reloc malloc arena. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2021-05-14riscv: Enable some devices pre-relocationSean Anderson
These devices are necessary for the clock driver, which is required by the sram driver, to run pre-relocation. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2021-05-14clk: Add support for the k210 clock driver pre-relocationSean Anderson
Variables which had previously been stored in .bss are moved to .data. In addition, probed needs to be reset when the clock driver is re-bound post-relocation. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2021-05-14clk: k210: Move the clint clock to under aclkSean Anderson
No other (real) clocks have the cpu clock as their parent; instead they are children of aclk. Move the clint clock under aclk to match them. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2021-05-14clk: k210: Remove k210_register_pllSean Anderson
This simplifies the PLL creation process, since we don't have to pass all the parameters individually. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2021-05-14clk: k210: Fix PLL enable always getting takenSean Anderson
This conditional always evaluated as false, regardless of the value of reg. Fix it so that it properly tests the bits in the PLL register. Also test PLL_EN, now that we set it. Reported-by: Damien Le Moal <Damien.LeMoal@wdc.com> Signed-off-by: Sean Anderson <seanga2@gmail.com>
2021-05-14clk: k210: Fix PLLs not being enabledSean Anderson
After starting or setting the rate of a PLL, the enable bit must be set. This fixes a bug where the AI ram would not be accessible, because it requires PLL1 to be running. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Damien Le Moal <damien.lemoal@wdc.com>
2021-05-14clk: Warn on failure to assign rateSean Anderson
If the user/dev explicitly requests a clock be assigned a certain rate, then we should warn them if we can't do it. This makes it clear if the clock is running at the default rate. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2021-05-14MAINTAINERS: Add a co-maintainer for RISC-VRick Chen
Add Leo as co-maintainer for RISC-V. Signed-off-by: Rick Chen <rick@andestech.com>
2021-05-13Merge branch '2021-05-13-extension-board-detection-and-DT-overlay-application'Tom Rini
- Improve support for various forms of extension boards and add DT overlay application support.
2021-05-13am335x: add support for cape detect functionalityKory Maincent
Update the Kconfig and the board file to make the am335x board compatible with cape detection. Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
2021-05-13arm: am335x: add support for i2c2 busKory Maincent
The am335x from BeagleBone use i2c EEPROM to detect capes. The memory is wired to i2c bus 2 therefore it need to be enabled. Add i2c2 clock, pinmux description and pinmux enable function. Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
2021-05-13configs: CHIP: add support for DIP detect functionalityKory Maincent
This commit enables using the extension board detection mechanism on CHIP boards Signed-off-by: Kory Maincent <kory.maincent@bootlin.com> Acked-by: Maxime Ripard <maxime@cerno.tech> Acked-by: Andre Przywara <andre.przywara@arm.com>
2021-05-13arm: sunxi: add support for DIP detection to CHIP boardKory Maincent
Add the extension_board_scan specific function to scan the information of the EEPROM on one-wire and fill the extension struct. Add the Kconfig symbol to enable the needs to detect DIPs. Signed-off-by: Kory Maincent <kory.maincent@bootlin.com> Reviewed-by: Maxime Ripard <maxime@cerno.tech> Acked-by: Andre Przywara <andre.przywara@arm.com>
2021-05-13w1: replace dt detection by automatic detectionKory Maincent
This patch changes the functioning of the detection of w1 devices. The old way was a comparison between detected w1 and the ones described in the device tree. Now it will just look for the driver matching the family id of the w1 detected. The patch is inspired from Maxime Ripard code. Signed-off-by: Kory Maincent <kory.maincent@bootlin.com> Reviewed-by: Maxime Ripard <maxime@cerno.tech>
2021-05-13am57xx: add support for cape detect functionalityKory Maincent
This commit enables using the extension board detection mechanism on AM57xx based platforms. Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
2021-05-13ti/common: add support for extension_scan_board functionKory Maincent
The BeagleBone platforms all use a common mechanism to discover and identify extension boards (called "capes"): each extension board has an I2C-connected EEPROM describing itself. This patch implements a generic extension_scan_board() feature that can be used by all BeagleBone platforms to read those I2C EEPROMs and fill in the list of "extension" structures. Following commits will enable this common logic on two BeagleBone platforms. Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
2021-05-13pytest: add sandbox test for "extension" commandKory Maincent
This commit extends the sandbox to implement a dummy extension_board_scan() function and enables the extension command in the sandbox configuration. It then adds a test that checks the proper functionality of the extension command by applying two Device Tree overlays to the sandbox Device Tree. Signed-off-by: Kory Maincent <kory.maincent@bootlin.com> [trini: Limit to running on sandbox] Signed-off-by: Tom Rini <trini@konsulko.com>
2021-05-13cmd: add support for a new "extension" commandKory Maincent
This patch adds a new "extension" command, which aims at detecting extension boards connected to the hardware platform, and apply the Device Tree overlays that describe the hardware present on those extension boards. In order to enable this mechanism, board-specific code must implement the extension_board_scan() function that fills in a linked list of "struct extension", each describing one extension board. In addition, the board-specific code must select the SUPPORT_EXTENSION_SCAN Kconfig boolean. Based on this: - "extension scan" makes the generic code call the board-specific extension_board_scan() function to retrieve the list of detected extension boards. - "extension list" allows to list the detected extension boards. - "extension apply <number>|all" allows to apply the Device Tree overlay(s) corresponding to one, or all, extension boards The latter requires two environment variables to exist and set one variable to run: - extension_overlay_addr: the RAM address where to load the Device Tree overlays - extension_overlay_cmd: the U-Boot command to load one overlay. Indeed, the location and mechanism to load DT overlays is very setup specific. - extension_overlay_name: set by the command: the name of the DT which will be load during the execution. When calling the command described in the extension_overlay_cmd variable, the variable extension_overlay_name will be defined. So a typical extension_overlay_cmd will look like this: extension_overlay_cmd=load mmc 0:1 $extension_overlay_addr /boot/$extension_overlay_name Here is an example on how to use it: => run loadfdt => fdt addr $fdtaddr => setenv extension_overlay_addr 0x1000 => setenv extension_overlay_cmd 'load mmc 0:1 ${extension_overlay_addr} /boot/${extension_overlay_name}' => extension scan Found 1 extension board(s). => extension apply 0 519 bytes read in 3 ms (168.9 KiB/s) Signed-off-by: Kory Maincent <kory.maincent@bootlin.com> Reviewed-by: Maxime Ripard <maxime@cerno.tech>
2021-05-13fdt_support: move fdt_valid from cmd_fdt.c to fdt_support.cKory Maincent
Move the fdt_valid function to fdt_support. This changes allow to be able to test the validity of a devicetree in other c files. Update code syntax. Signed-off-by: Kory Maincent <kory.maincent@bootlin.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Maxime Ripard <maxime@cerno.tech>
2021-05-12ARM: renesas: Scrub duplicate memory nodes from DT on Gen3Marek Vasut
Scrub duplicate /memory@* node entries here. Some R-Car DTs might contain multiple /memory@* nodes, however fdt_fixup_memory_banks() either generates single /memory node or updates the first /memory node. Any remaining memory nodes are thus potential duplicates. However, it is not possible to delete all the memory nodes right away, since some of those might not be DRAM memory nodes, but some sort of other memory. Thus, delete only the memory nodes which are in the R-Car3 DBSC ranges. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-05-12ARM: rmobile: Add missing rcar-common/common.c to Beacon RZG2M kitMarek Vasut
The rcar-common/common.c contains various common board functions shared by all R-Car and RZG boards. This board is not compiling the file in, so add it. This way, part of the board code can be de-duplicated too. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Adam Ford <aford173@gmail.com>
2021-05-12Merge tag 'ti-v2021.07-rc3' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-ti - Initial support for AM64 EVM and SK - K3 DDR driver unification for J7 and AM64 platforms. - Minor fixes for TI clock driver
2021-05-12ARM: dts: k3-am642-sk: Add ethernet related DT nodesVignesh Raghavendra
Add CPSW related nodes for AM642 SK. There are two CPSW ports on the board but U-Boot supports only the first port. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-12ARM: dts: k3-am64-main: Add CPSW DT nodesVignesh Raghavendra
AM64 as CPSW3G IP with 2 external ports. Add DT entries for the same (based on kernel DT). Disable second port as its by default set to ICSS usage on EVM. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-12net: ti: am65-cpsw-nuss: Add a new compatible for AM64Vignesh Raghavendra
Add a new compatible to support AM64 SoC Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-12net: ti: am65-cpsw-nuss: Don't cache disabled port IDVignesh Raghavendra
Currently driver may end up caching disabled port ID as active interface. Fix this by bailing out earlier in case port is marked disabled in the DT. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-12net: ti: am65-cpsw-nuss: Prepare to support non primary ext portVignesh Raghavendra
CPSW NUSS IP on K3 SoCs can have more than one external port (upto 8) Therefore increase AM65_CPSW_CPSWNU_MAX_PORTS to 9 (8 ext + 1 Root port) as preparation to allow any one of the 8 ports to be used as ethernet interface in U-Boot. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-12dma: ti: k3-udma: Add BCDMA and PKTDMA supportVignesh Raghavendra
Sync BCDMA and PKTDMA support from Kernel for AM64 SoC Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-12dma: ti: k3-psil-am64: Add AM64 PSIL endpoint dataVignesh Raghavendra
Add AM64 SoC specific channel mapping and endpoint data. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-12dma: ti: k3-psil: Extend PSIL EP data extension for AM64Vignesh Raghavendra
Extend PSIL EP data to include AM64 DMA specific information Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-12dma: ti: k3-psil-am654: Drop unused PSIL EP static dataVignesh Raghavendra
ICSSG Ethernet driver uses two src threads per port (one per slice). Similarly CPSW uses one src thread. Drop PSIL EP static data for other src threads in order to reduce R5 SPL footprint. This makes AM65x board bootable again. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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