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2023-04-24include: Enable video related global data variable and splash at SPLNikhil M Jain
To include video related global data variables and splash functions at SPL and u-boot proper, use CONFIG_IS_ENABLED. Replace CONFIG_CMD_BMP with CONFIG_BMP to enable splash_display function at u-boot proper and SPL. Signed-off-by: Nikhil M Jain <n-jain1@ti.com> Reviewed-by: Devarsh Thakkar <devarsht@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-04-24common: Enable splash functions at SPLNikhil M Jain
To support splash screen at both u-boot proper and SPL use CONFIG_IS_ENABLED and CONFIG_VAL to check for video related Kconfigs at respective stages. Replace CONFIG_CMD_BMP with CONFIG_BMP to enable splash_display function at u-boot proper and SPL. Signed-off-by: Nikhil M Jain <n-jain1@ti.com> Reviewed-by: Devarsh Thakkar <devarsht@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-04-24drivers: video: Enable necessary video functions at SPLNikhil M Jain
To support video driver at SPL use CONFIG_IS_ENABLED and CONFIG_VAL, which checks for stage specific configs and thus enables video support at respective stage. Signed-off-by: Nikhil M Jain <n-jain1@ti.com> Reviewed-by: Devarsh Thakkar <devarsht@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2023-04-24common: Makefile: Rule to compile bmp.cNikhil M Jain
Add rule to compile bmp.c at SPL and u-boot proper when CONFIG_SPL_BMP and CONFIG_BMP are defined. Signed-off-by: Nikhil M Jain <n-jain1@ti.com> Reviewed-by: Devarsh Thakkar <devarsht@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2023-04-24cmd: bmp: Split bmp commands and functionsNikhil M Jain
To enable splash screen at SPL, need to compile cmd/bmp.c which also includes bmp commands, since SPL doesn't use commands split bmp.c into common/bmp.c which includes all bmp functions and cmd/bmp.c which only contains bmp commands. Add function delclaration for bmp_info in video.h. Signed-off-by: Nikhil M Jain <n-jain1@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-04-24common: Kconfig: Add BMP configsNikhil M Jain
Add CONFIG_BMP and CONFIG_SPL_BMP which enable displaying bmp images at u-boot proper and SPL. Signed-off-by: Nikhil M Jain <n-jain1@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
2023-04-24common: Makefile: Add rule to compile splash and splash_source at SPLNikhil M Jain
To enable splash screen and loading bmp from boot media, add rules to compile splash.c and splash_source.c at SPL stage only when CONFIG_SPL_SPLASH_SCREEN and CONFIG_SPL_SPLASH_SOURCE are defined. Signed-off-by: Nikhil M Jain <n-jain1@ti.com> Reviewed-by: Devarsh Thakkar <devarsht@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-04-24drivers: video: tidss: Makefile: Add condition to compile TIDSS at SPLNikhil M Jain
To enable TIDSS driver only at SPL stage add rule to compile the TIDSS video driver. CONFIG_$(SPL_)VIDEO_TIDSS will compile tidss_drv, at SPL only if CONFIG_SPL_VIDEO_TIDSS is defined and at u-boot proper if CONFIG_VIDEO_TIDSS is defined. Signed-off-by: Nikhil M Jain <n-jain1@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-04-24drivers: video: Makefile: Rule to compile necessary video driver filesNikhil M Jain
To enable video driver at SPL, need to compile video-uclass, vidconsole-uclass, backlight-uclass, panel-uclass, simple-panel, add rules to compile them at SPL and u-boot proper. To support splash_display at SPL, need to compile video-bmp, add rule to compile at SPL and u-boot proper. Signed-off-by: Nikhil M Jain <n-jain1@ti.com> Reviewed-by: Devarsh Thakkar <devarsht@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2023-04-24drivers: Makefile: Add rule to compile video driverNikhil M Jain
Compile video driver at SPL using CONFIG_SPL_VIDEO. Signed-off-by: Nikhil M Jain <n-jain1@ti.com> Reviewed-by: Devarsh Thakkar <devarsht@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> # qemu-x86_64
2023-04-24drivers: video: tidss: Kconfig: Configs to enable TIDSS at SPLNikhil M Jain
To enable tidss display driver only at SPL stage, add necessary config, CONFIG_SPL_VIDEO_TIDSS. Signed-off-by: Nikhil M Jain <n-jain1@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
2023-04-24drivers: video: Kconfig: Add configs for enabling video at SPLNikhil M Jain
Add Kconfigs which enable the video driver and splash screen at SPL stage only and not at u-boot proper. The existing Kconfigs from u-boot proper were not used to make SPL splash screen independent to them. Signed-off-by: Nikhil M Jain <n-jain1@ti.com> Reviewed-by: Devarsh Thakkar <devarsht@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2023-04-23patman: Declare the future Series memorySimon Glass
This member is used in series.MakeCcFile() so should be declared in the Series class. Add a declaration to silence the warning. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-04-23Merge tag 'u-boot-rockchip-20230421' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-rockchip - Add rk3588 evb support; - Update pinctrl for rk3568 and rk3588; - Update rk3288 dts; - Update mmc support for rk3568 and rk3588; - Add rng support for rk3588; - Add DSI support for rk3568; - Some other misc fixes in dts, config, driver;
2023-04-22Merge tag 'efi-2023-07-rc1-2' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-efi Pull request for efi-2023-07-rc1-2 Documentation: * Describe Python coding style UEFI: * Enable tests for authenticated capsules on the sandbox * Fix pylint warnings * Correct struct efi_hii_keyboard_layout definition
2023-04-22Merge https://source.denx.de/u-boot/custodians/u-boot-riscvTom Rini
* Add StarFive VisionFive v2 Board support * Support CONFIG_REMAKE_ELF * Code cleanups for RISC-V architecture
2023-04-22Merge https://source.denx.de/u-boot/custodians/u-boot-watchdogTom Rini
- watchdog: arm_smc_wdt: add watchdog support (Lionel) - watchdog: ftwdt010: return a previously deleted driver now ported to DM (Sergei) - watchdog: Add a watchdog driver for Raspberry Pi boards (Etienne)
2023-04-22Merge tag 'u-boot-stm32-20230419' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-stm configs: _ Add usb_pgood_delay for ST boards _ increase malloc size for pre-reloc for stm32mp15 _ Set CONFIG_USB_HUB_DEBOUNCE_TIMEOUT=2s for stm32mp15 dts: _ Add QSPI support on STM32MP13x SoC family _ Add FMC support on STM32MP13x SoC family drivers/machine: _ pinctrl_stm32: Add slew rate support for stm32_pinctrl_get_pin_muxing() _ spi: stm32_qspi: Remove useless struct stm32_qspi_flash _ rawnand: stm32_fmc2: remove unsupported EDO mode _ stm32mp: fix various array bounds checks
2023-04-22Merge tag 'u-boot-nand-20230422' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-nand-flash Pull request for u-boot-nand-20230422 Replaces a patch by Linus Walleij merged with pull request u-boot-nand-20230417, with a newer version that contains fixes for tests run by Tom Rini.
2023-04-22mtd: rawnand: nand_base: Handle algorithm selectionLinus Walleij
For BRCMNAND with 1-bit BCH ECC (BCH-1) such as used on the D-Link DIR-885L and DIR-890L routers, we need to explicitly select the ECC like this in the device tree: nand-ecc-algo = "bch"; nand-ecc-strength = <1>; nand-ecc-step-size = <512>; This is handled by the Linux kernel but U-Boot core does not respect this. Fix it up by parsing the algorithm and preserve the behaviour using this property to select software BCH as far as possible. Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Acked-by: William Zhang <william.zhang@broadcom.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Tested-by: Tom Rini <trini@konsulko.com> [am335x_evm] Link: https://lore.kernel.org/all/20230407134008.1939717-3-linus.walleij@linaro.org/ Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-04-22Revert "mtd: rawnand: nand_base: Handle algorithm selection"Dario Binacchi
It will be replaced by a more recent version which contains fixes for tests run by Tom Rini. This reverts commit ff33d3c87c2a1ab576607c2f67a9cb7690a4e7ca. Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-04-21configs: rockchip: radxa-cm3-io: drop CONFIG_USB_DWC3_GENERICFUKAUMI Naoki
it's not used by rk35xx Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
2023-04-21arm: dts: rockchip: radxa-cm3-io, rock-3a: enable regulators for usbFUKAUMI Naoki
enable regulators for usb host function Signed-off-by: FUKAUMI Naoki <naoki@radxa.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21configs: rockchip: radxa-cm3-io, rock-3a: enable commands for i2c/pmic/regulatorFUKAUMI Naoki
enable commands for i2c/pmic/regulator and relevant configs. also drop configs for unused regulators. Signed-off-by: FUKAUMI Naoki <naoki@radxa.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21configs: rockchip: rock-3a: make usb host workFUKAUMI Naoki
add support for USB host function on ROCK 3A Signed-off-by: FUKAUMI Naoki <naoki@radxa.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21mmc: rockchip_sdhci: Limit number of blocks read in a single commandJonas Karlman
Using DMA to load TF-A into SRAM fails when booting from eMMC on RK3588. ## Checking hash(es) for Image atf-3 ... sha256 error! Bad hash value for 'hash' hash node in 'atf-3' image node spl_load_simple_fit: can't load image loadables index 2 (ret = -1) mmc_load_image_raw_sector: mmc block read error Fix this by using PIO mode in SPL and limit the number of blocks used in a single read command to avoid triggering Data End Bit Error interrupt. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21mmc: sdhci: Allow disabling of SDMA in SPLPeter Geis
Rockchip emmc devices have a similar issue to Rockchip dwmmc devices, where performing DMA to SRAM later causes issues with suspend/resume. Allow us to toggle SDMA in SPL for sdhci similar to ADMA support, so we can ensure DMA is not used when loading the SRAM code. Signed-off-by: Peter Geis <pgwipeout@gmail.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> [jonas@kwiboo.se: add Kconfig default value and fix ADMA typo] Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
2023-04-21clk: rockchip: rk3588: Add limited TMCLK_EMMC clock supportJonas Karlman
The device tree sdhci node reference the TMCLK_EMMC clock, add limited support this clock to rk3588 cru driver. Fixes probe of sdhci driver. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21rockchip: rk3588-rock-5b: Include eMMC node in SPL dtbJonas Karlman
Add sdhci node to SPL and u-boot,spl-boot-order. Also add more supported mmc modes and pinctrl. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21mmc: rockchip_sdhci: Add support for RK3588Jonas Karlman
Add support for RK3588 to the rockchip sdhci driver. Use driver data to handle differences between RK3568 and RK3588: - Set "Receive original clock source is auto gating" for RK3588. - Set "Receive clock source is no-inverted" only on RK3568 and "Transmit clock source is invertion of original clock input" for RK3588. - Use different txclk_tapnum for HS400 modes on RK3588. - Configure the CMDOUT reg for HS400 modes for RK3588. This is based on the mainline linux and vendor kernel driver and have successfully been tested with rock5b-rk3588_defconfig and CONFIG_MMC_HS200_SUPPORT=y CONFIG_MMC_HS400_SUPPORT=y CONFIG_MMC_HS400_ES_SUPPORT=y CONFIG_MMC_SPEED_MODE_SET=y using the following command to switch mode and then read 512 MiB of data from eMMC into memory, => mmc dev 0 0 <mode> && mmc info && mmc read 10000000 2000 10000 for each of the modes below. 0 = MMC legacy 1 = MMC High Speed (26MHz) 3 = MMC High Speed (52MHz) 4 = MMC DDR52 (52MHz) 10 = HS200 (200MHz) 11 = HS400 (200MHz) 12 = HS400ES (200MHz) Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21rockchip: rk3568-rock-3a: Enable support for more eMMC modesJonas Karlman
Add supported mmc modes to rk3568-rock-3a device tree. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21mmc: rockchip_sdhci: Fix HS400 and HS400ES mode on RK3568Jonas Karlman
Adjust tap number for transmit clock, tap number and delay number for strobe input to fix HS400 modes on RK3568. New values have been picked from vendor kernel and u-boot and have successfully been tested with rock-3a-rk3568_defconfig and CONFIG_MMC_HS200_SUPPORT=y CONFIG_MMC_HS400_SUPPORT=y CONFIG_MMC_HS400_ES_SUPPORT=y CONFIG_MMC_SPEED_MODE_SET=y using the following command to switch mode and then read 512 MiB of data from eMMC into memory, => mmc dev 0 0 <mode> && mmc info && mmc read 10000000 2000 10000 for each of the modes below. 0 = MMC legacy 1 = MMC High Speed (26MHz) 3 = MMC High Speed (52MHz) 4 = MMC DDR52 (52MHz) 10 = HS200 (200MHz) 11 = HS400 (200MHz) 12 = HS400ES (200MHz) Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21mmc: rockchip_sdhci: Rearrange and simplify used regs and flagsJonas Karlman
This rearrange and remove duplicate defines to make the code cleaner. There is no need to read vendor area1 and use an offset each time, it is easier and clearer to just use the reg offset defined in TRM, same as the other vendor regs. This also removes use of the misspelled const for the RK3588 CMDOUT reg, it will be re-added when support for RK3588 is introduced. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21mmc: rockchip_sdhci: Remove empty get_phy and set_enhanced_strobe opsJonas Karlman
Remove empty implementations of get_phy and set_enhanced_strobe ops. Change driver set_enhanced_strobe to return 0 in order to allow missing implementation of the ops. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21mmc: rockchip_sdhci: Update speed mode controls in set_ios_postJonas Karlman
Refactor set_ios_post ops to correctly set UHS Speed Select field values according to TRM. Also set or unset Enhanced Strobe Enable bit and eMMC Card present bit in set_ios_post, the Enhanced Strobe Enable bit was never unset after switching to HS400ES mode. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21mmc: rockchip_sdhci: Refactor execute tuning error handlingJonas Karlman
Check return value from mmc_send_cmd and clear HOST_CONTROL2 when there is an error. Also skip enable of interrupt signaling and remove a delay, a delay is already happening in sdhci_send_command. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21mmc: rockchip_sdhci: Use set_clock and config_dll sdhci_opsJonas Karlman
Change to configure clock and DLL in set_clock and config_dll ops instead of in the set_ios_post ops. With this change the output clock is turned off while configuring DLL parameters, according to the design recommendations. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21mmc: rockchip_sdhci: Add set_clock and config_dll sdhci_opsJonas Karlman
Add support for the set_clock and config_dll sdhci_ops. Use of these ops will allow configuration of DLL while the output clock is disabled. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21mmc: rockchip_sdhci: Remove unneeded emmc_phy_initJonas Karlman
Remove the unneeded emmc_phy_init now that the no-inverter flag is handled correctly after commit 2321a991bbb5 ("rockchip: sdhci: rk3568: bypass DLL when clk <= 52 MHz"). Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21mmc: rockchip_sdhci: Fix use of device private dataJonas Karlman
The device private data is misused in rockchip_sdhci_of_to_plat and rockchip_sdhci_execute_tuning. In these functions dev_get_priv is assigned to struct sdhci_host: struct sdhci_host *host = dev_get_priv(dev); Instead, the sdhci host should refer to host in struct rockchip_sdhc: struct rockchip_sdhc *priv = dev_get_priv(dev); struct sdhci_host *host = &priv->host; Because host is the first member in struct rockchip_sdhc this is not a real problem, lets fix it anyway and also use priv name consistently. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21mmc: sdhci: Set UHS Mode Select field for UHS SDR25 modeJonas Karlman
Set correct UHS Mode Select field value for UHS SDR25 (50MHz) mode. Fixes: d1c0a2200afb ("mmc: sdhci: Add support for HOST_CONTROL2 and setting UHS timings") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21mmc: sdhci: Fix HISPD bit handling for MMC HS 52MHz modeJonas Karlman
Set High Speed Enable bit for MMC High Speed (52MHz) mode. Fixes: f12341a95295 ("mmc: sdhci: Fix HISPD bit handling") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21ARM: dts: rockchip: rk3588s-u-boot: Add rng nodeChris Morgan
Add a node for the trng found on RK3588 SoCs. Changes in V3: - Added Reviewed-By tag. Changes in V2: - None Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Sughosh Ganu <sughosh.ganu@linaro.org>
2023-04-21rockchip: rng: add trngv1 for rk3588Chris Morgan
This adds support for the TRNG found in the RK3588 SoC to the rockchip_rng driver so that it can be used for things such as seeding randomness to Linux. Changes in V3: - Moved notes from commit to cover letter. - Added Reviewed-By tag. Changes in V2: - Modified Kconfig to note that the Rockchip RNG driver supports all versions of the hardware (v1, v2, and the trng in the rk3588). Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com> Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21clk: rockchip: rk3568: Add dummy I2S1_MCLKOUT_TX clock supportJonas Karlman
A RK3568 device tree pmic node can reference the I2S1_MCLKOUT_TX clock in assigned-clocks, add dummy support to set parent of this clock to the rk3568 cru driver. Fixes probe of pmic driver and missing regulators on affected boards, rk3568-evb and rk3568-rock-3a. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21pinctrl: rockchip: Fix IO mux selection on RK3568Jonas Karlman
IO mux selection is not working correctly for all pins. Sync mux route data from linux to add any missing and update wrong trigger pins to fix this. Also apply the pull-up fix needed for GPIO0 D3-D6. Fixes: 1977d746aa54 ("rockchip: rk3568: add rk3568 pinctrl driver") Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
2023-04-21rockchip: rk3588: Sync sdmmc node from linux-nextJonas Karlman
Sync the sdmmc node from linux-next, include required nodes in SPL and imply Kconfig options required for functional sdmmc clk in SPL and U-Boot proper. This make it possible for both SPL and U-Boot proper to configure sdmmc clocks. In SPL, before TF-A is loaded, scru regs is configured, in U-Boot proper a SCMI message is sent to TF-A. Fixes: 95c8656b72dc ("ARM: dts: rockchip: rk3588s-u-boot: Add sdmmc node") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21rockchip: rk3588: Add support for sdmmc clocks in SPLJonas Karlman
Booting from sdmmc on RK3588 currently works because of a workaround in the device tree, clocks are reordered so that the driver use ciu-sample instead of ciu, and the BootRom initializes sdmmc clocks before SPL is loaded into DRAM. The sdmmc clocks are normally controlled by TF-A using SCMI. However, there is a need to control these clocks in SPL, before TF-A has started. This adds a rk3588_scru driver to control the sdmmc clocks in SPL before TF-A has started, using scru regs. It also adds a small glue driver to bind the scmi clock node to the rk3588_scru driver in SPL. Fixes: 7a474df74023 ("clk: rockchip: Add rk3588 clk support") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21clk: scmi: Add Kconfig option for SPLJonas Karlman
Building U-Boot SPL with CLK_SCMI and SCMI_FIRMWARE Kconfig options enabled and SPL_FIRMWARE disabled result in the following error. drivers/clk/clk_scmi.o: in function `scmi_clk_gate': drivers/clk/clk_scmi.c:84: undefined reference to `devm_scmi_process_msg' drivers/clk/clk_scmi.c:88: undefined reference to `scmi_to_linux_errno' drivers/clk/clk_scmi.o: in function `scmi_clk_get_rate': drivers/clk/clk_scmi.c:113: undefined reference to `devm_scmi_process_msg' drivers/clk/clk_scmi.c:117: undefined reference to `scmi_to_linux_errno' drivers/clk/clk_scmi.o: in function `scmi_clk_set_rate': drivers/clk/clk_scmi.c:139: undefined reference to `devm_scmi_process_msg' drivers/clk/clk_scmi.c:143: undefined reference to `scmi_to_linux_errno' drivers/clk/clk_scmi.o: in function `scmi_clk_probe': drivers/clk/clk_scmi.c:157: undefined reference to `devm_scmi_of_get_channel' make[1]: *** [scripts/Makefile.spl:527: spl/u-boot-spl] Error 1 make: *** [Makefile:2043: spl/u-boot-spl] Error 2 Add Kconfig option so that CLK_SCMI can be disabled in SPL to fix this. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21rockchip: rk35xx: Enable fdtoverlay and kernel compressionJonas Karlman
Add fdtoverlay_addr_r, kernel_comp_addr_r and imply use of OF_LIBFDT_OVERLAY on RK3568 and RK3588 to support fdtoverlay and kernel compression. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Simon Glass <sjg@chromium.org>
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