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2023-02-28ram: rockchip: Add rk3588 ddr driver supportJagan Teki
Add ddr driver for rk3588 to get the ram capacity. Co-developed-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28clk: rockchip: pll: Add pll_rk3588 type for rk3588Jagan Teki
Add RK3588 pll set and get rate clock support. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28clk: rockchip: Add rk3588 clk supportJagan Teki
Add clock driver support for Rockchip RK3588 SoC. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28dt-bindings: clk: Add dt-binding header for RK3588Jagan Teki
Add the dt-bindings header for the Rockchip RK3588, that gets shared between the clock controller and the clock references in the dts. commit <f204a60e545c> ("dt-bindings: clock: add rk3588 clock definitions") Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28arm: rockchip: Add grf header for rk3588Jagan Teki
Add GRF header for Rockchip RK3588. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28arm: rockchip: Add cru header for rk3588Jagan Teki
Add clock and reset unit header include for rk3588. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28rockchip: mkimage: Add rk3588 supportJagan Teki
Add support for rk3588 package header in mkimage tool. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28evb-rk3568: Update MAINTAINERS and documentationChris Morgan
Update the MAINTAINERS file to include the devicetree for the rk3568-evb1-v10 board. Also update Rockchip board docs to include information on building RK3568 based devices. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28arm64: dts: rockchip: add gpio-ranges property to gpio nodesChris Morgan
Add gpio-ranges property to GPIO nodes so that the bank ID can be correctly derived for each GPIO bank. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28rockchip: rk3568: enable automatic power savingsChris Morgan
It enables automatic clock gating on idle, disables the eDP phy by default, and sets the core pvtpll ring length. It is reported this lowers the temperature on at least one SoC by 7C. Signed-off-by: Peter Geis <pgwipeout@gmail.com> Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28rockchip: rk3568: add boot device detectionChris Morgan
Enable spl to detect which device it was booted from. Signed-off-by: Peter Geis <pgwipeout@gmail.com> Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28arm64: dts: rockchip: Sync rk356x from Linux mainChris Morgan
Sync rk3566 and rk3568 from the mainline Linux kernel (6.2-rc2 as of this writing). Note that this will rename the rk3568-evb to rk3568-evb1-v10. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28dts: rockchip: px30: add gpio-ranges property to gpio nodesChris Morgan
Add the gpio-ranges property to each GPIO node for use in deriving the correct bank ID. Note that invoking "gpio status -a" no longer causes the board to hit a "Synchronous Abort". Fixes: 537b1a277479 ("rockchip: add px30 devicetrees") Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28gpio: gpio-rockchip: parse gpio-ranges for bank idChris Morgan
Use the new devicetree property of gpio-ranges to determine the GPIO bank ID. Preserve the "old" way of doing things too, so that boards can be migrated and tested gradually (I only have a 3566 and 3326 to test). Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28rk3566: radxa-cm3: Enable USB2.0, USB3.0 supportManoj Sai
=> usb start starting USB... Bus usb@fd000000: Register 2000140 NbrPorts 2 Starting the controller USB XHCI 1.10 Bus usb@fd800000: USB EHCI 1.00 scanning bus usb@fd000000 for devices... cannot reset port 1!? 2 USB Device(s) found scanning bus usb@fd800000 for devices... 4 USB Device(s) found scanning usb for storage devices... 2 Storage Device(s) found => usb tree USB device tree: 1 Hub (5 Gb/s, 0mA) | U-Boot XHCI Host Controller | +-2 Mass Storage (5 Gb/s, 224mA) SanDisk Dual Drive 04019c9b2e1a58f24ee318c3c123aa5 1 Hub (480 Mb/s, 0mA) | u-boot EHCI Host Controller | +-2 Hub (480 Mb/s, 100mA) | USB 2.0 Hub | +-3 Mass Storage (480 Mb/s, 500mA) | JetFlash Mass Storage Device 19M7I4ZQFTSC08SU | +-4 Human Interface (12 Mb/s, 98mA) Logitech USB Receiver Co-developed-by: Suniel Mahesh <sunil@amarulasolutions.com> Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com> Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28rockchip: rk3568: Select DM_REGULATOR_FIXEDManoj Sai
Select the DM_REGULATOR_FIXED on RK3568 platform. Co-developed-by: Suniel Mahesh <sunil@amarulasolutions.com> Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com> Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28rockchip: rk3568: add rk3568 pinctrl driverJagan Teki
Add driver supporting pin multiplexing on rk3568 platform. Co-developed-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com> Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com> Co-developed-by: Jianqun Xu <jay.xu@rock-chips.com> Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28arm64: dts: rk356x-u-boot: Drop combphy1 assigned-clocks/ratesJagan Teki
combphy1 is failing to probe due to unhandled assigned-clocks and assigned-clocks-rates. => usb start starting USB... Bus usb@fd000000: Failed to get PHY1 for usb@fd000000 Port not available. Bus usb@fd800000: USB EHCI 1.00 There is no real requirement for them in U-Boot to handle, hence mark them as deleted-properties for the probe to success Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28drivers: phy: add naneng combphy for rk3568Jagan Teki
RK3568 has three combo phys, and PCIe/USB3/SATA/QSGMII controllers share one pipe interface for each combo phy, here is the diagram of the complex connection. +----------------+ | | +------+ | USB3 OTG CTRL0 |---->| | | | | | +------------+ +----------------+ | PIPE | | | | MUX |---->| Combo PHY0 | +----------------+ | | | | | | | | +------------+ | SATA CTRL0 |---->| | | | +------+ +----------------+ +----------------+ | | +------+ | USB3 HOST CTRL1|---->| | | | | | +------------+ +----------------+ | PIPE | | | | MUX |---->| Combo PHY1 | +----------------+ | | | | | |---->| | +------------+ | SATA CTRL1 | -->| | | | | +------+ +----------------+ | | +----------------+ | | | | +------+ | QSGMII CTRL |---->| | | | | | +------------+ +----------------+ | PIPE | | | | MUX |---->| Combo PHY2 | +----------------+ | | | | | |---->| | +------------+ | SATA CTRL2 | -->| | | | | +------+ +----------------+ | | +----------------+ | | | | | PCIe2 1-Lane |--- | | +----------------+ Co-developed-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com> Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com> Co-developed-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28phy: rockchip-inno-usb2: Add USB2 PHY for rk3568Manoj Sai
RK3568 has two USB 2.0 PHYs, and each PHY has two ports, the OTG port of PHY0 support OTG mode with charging detection function, they are similar to previous Rockchip SoCs. However, there are three different designs for RK3568 USB 2.0 PHY. 1. RK3568 uses independent USB GRF module for each USB 2.0 PHY. 2. RK3568 accesses the registers of USB 2.0 PHY IP directly by APB. 3. The two ports of USB 2.0 PHY share one interrupt. This patch only PHY1 with necessary attributes required to function USBPHY1 on U-Boot. Co-developed-by: Ren Jianing <jianing.ren@rock-chips.com> Signed-off-by: Ren Jianing <jianing.ren@rock-chips.com> Co-developed-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28phy: rockchip: inno-usb2: Add support #address_cells = 2Jagan Teki
New Rockchip devices have the usb phy nodes as standalone devices. These nodes have register nodes with #address_cells = 2, but only use 32 bit addresses. Adjust the driver to check if the returned address is "0", and adjust the index in that case. Derived and adjusted the similar change from linux-next with below commit <9c19c531dc98> ("phy: phy-rockchip-inno-usb2: support #address_cells = 2") Co-developed-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com> Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28board: rockchip: Add Radxa Compute Module 3 IO BoardJagan Teki
Radxa Compute Module 3(CM3) IO board an application board from Radxa and is compatible with Raspberry Pi CM4 IO form factor. Radxa CM3 needs to mount on top of this IO board in order to create complete Radxa CM3 IO board platform. Add support for Radxa CM3 IO Board defconfig and -u-boot.dtsi Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2023-02-28arm64: dts: rockchip: rk3566: Add Radxa Compute Module 3 IOJagan Teki
Radxa Compute Module 3(CM3) IO board an application board from Radxa and is compatible with Raspberry Pi CM4 IO form factor. Specification: - 1x HDMI, - 2x MIPI DSI - 2x MIPI CSI2 - 1x eDP - 1x PCIe card - 2x SATA - 2x USB 2.0 Host - 1x USB 3.0 - 1x USB 2.0 OTG - Phone jack - microSD slot - 40-pin GPIO expansion header - 12V DC Radxa CM3 needs to mount on top of this IO board in order to create complete Radxa CM3 IO board platform. linux-next commit for the same, commit <8f19828844f2> ("arm64: dts: rockchip: Fix compatible for Radxa CM3") Add support for Radxa CM3 IO Board. Co-developed-by: FUKAUMI Naoki <naoki@radxa.com> Signed-off-by: FUKAUMI Naoki <naoki@radxa.com> Co-developed-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com> Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28arm64: dts: rockchip: rk3566: Add Radxa Compute Module 3Jagan Teki
Radxa Compute Module 3(CM3) is one of the modules from a series System On Module based on the Radxa ROCK 3 series and is compatible with Raspberry Pi CM4 pinout and form factor. Specification: - Rockchip RK3566 - up to 8GB LPDDR4 - up to 128GB high performance eMMC - Optional wireless LAN, 2.4GHz and 5.0GHz IEEE 802.11b/g/n/ac wireless, BT 5.0, BLE with onboard and external antenna. - Gigabit Ethernet PHY Radxa CM3 needs to mount on top of this IO board in order to create complete Radxa CM3 IO board platform. Since Radxa CM3 is compatible with Raspberry Pi CM4 pinout so it is possible to mount Radxa CM3 on top of the Rasberry Pi CM4 IO board. linux-next commit for the same, commit <8f19828844f2> ("arm64: dts: rockchip: Fix compatible for Radxa CM3") Add support for Radxa CM3. Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Co-developed-by: FUKAUMI Naoki <naoki@radxa.com> Signed-off-by: FUKAUMI Naoki <naoki@radxa.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2023-02-28dt-bindings: rockchip: Sync rockchip, vop2.h from LinuxJagan Teki
Sync rockchip,vop2.h from linux-next, and the last commit is commit <604be85547ce> ("drm/rockchip: Add VOP2 driver") Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2023-02-28rockchip: rk3568: Move DM_RESET in arch kconfigJagan Teki
Like other rockchip SoCs, DM_RESET is useful across rk3568 platform. Select it from arch kconfig. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28board: edgeble: Fix neural-compute-module-2 board nameJagan Teki
The board should be RV1126-NEU2 instead RV1126-ECM0. Fix the wrong name. Fixes: b8f1ca954013 ("board: rockchip: Add Edgeble Neu2 IO Board") Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28include: rk3328: Add default env for compressed kernel imagesChristopher Obbard
Add default memory addresses for kernel_comp_addr_r and kernel_comp_size to enable booting from a compressed kernel image. This area is temporarily used to decompress the kernel image on-the-fly. Signed-off-by: Christopher Obbard <chris.obbard@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28arm64: dts: rockchip: rk3308: Add Radxa ROCK Pi S supportAkash Gajjar
Add Radxa ROCK 3 Model A support. sync rk3308-rock-pi-s.dts from Linux 6.2.0-rc7. ROCK Pi S is RK3308 based SBC from radxa.com. ROCK Pi S has a, - 256MB/512MB DDR3 RAM - SD, NAND flash (optional on board 1/2/4/8Gb) - 100MB ethernet, PoE (optional) - Onboard 802.11 b/g/n wifi + Bluetooth 4.0 Module - USB2.0 Type-A HOST x1 - USB3.0 Type-C OTG x1 - 26-pin expansion header - USB Type-C DC 5V Power Supply Linux commit commit for the same, <2e04c25b1320> ("arm64: dts: rockchip: add ROCK Pi S DTS support") Signed-off-by: Akash Gajjar <gajjar04akash@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28arm64: dts: rockchip: rk3568: Add Radxa ROCK 3 Model A board supportAkash Gajjar
Add Radxa ROCK 3 Model A support. sync rk3568-rock-3a.dts from Linux 6.2.0-rc7 Board Specifications - Rockchip RK3568 - 2/4/8GB LPDDR4 3200MT/s - eMMC socket, SD card slot - GbE LAN - PCIe 3.0/2.0 - M.2 Connector - 3.5mm Audio jack with mic - HDMI 2.0, MIPI DSI/CSI - USB 3.0 Host/OTG, USB 2.0 Host - 40-pin GPIO expansion ports - USB Type C PD 2.0, 9V/2A, 12V/2A, 15V/2A, 20V/2A Refer Linux commit <22a442e6586c> ("arm64: dts: rockchip: add basic dts for the radxa rock3 model a") Signed-off-by: Akash Gajjar <gajjar04akash@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28binman: Mark mkimage entry missing when its subnodes is missingJonas Karlman
Using the mkimage entry with the multiple-data-files prop and having a missing external blob result in an unexpected ValueError exception using the --allow-missing flag. ValueError: Filename 'missing.bin' not found in input path (...) Fix this by using _pathname that is resolved by ObtainContents for blob entries, ObtainContents also handles allow missing for external blobs. Mark mkimage entry as missing and return without running mkimage when missing entries is reported by CheckMissing. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28rockchip: mkimage: Update init size limit for RK3568Jonas Karlman
The current init size limit of 76KiB is too big to fit in the 64KiB SRAM on RK3568, sync init size limit from vendor u-boot to fix this. Set init size limit to 60KiB (-16KiB) for RK3568. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28rockchip: mkimage: Update init size limit for RK3328Jonas Karlman
Latest vendor TPL for RK3328 has grown past the current init size limit of 28KiB, sync the init size limit from vendor u-boot to fix this. Set init size limit to 30KiB (+2KiB) for RK3328. This makes it possible to use latest vendor TPL on RK3328 without getting a size limit error running the mkimage command. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28Revert "board: rockchip: Fix binman_init failure on EVB-RK3568"Jonas Karlman
An external TPL binary is now expected to be provided using ROCKCHIP_TPL when building RK3568 targets. This reverts commit 31500e7bcfaca08ab7c2879f502a6cf852410244. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28rockchip: Use an external TPL binary on RK3568Jonas Karlman
Rockchip SoCs typically use U-Boot TPL to initialize DRAM, then jumps back to BootRom to load next stage, U-Boot SPL, into DRAM. BootRom then jumps to U-Boot SPL to continue the normal boot flow. However, there is no support to initialize DRAM on RK35xx SoCs using U-Boot TPL and instead an external TPL binary must be used to generate a bootable u-boot-rockchip.bin image. Add CONFIG_ROCKCHIP_EXTERNAL_TPL to indicate that an external TPL should be used. Build U-Boot with ROCKCHIP_TPL=/path/to/ddr.bin to generate a bootable u-boot-rockchip.bin image for RK3568. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Eugen Hristev <eugen.hristev@collabora.com>
2023-02-28binman: Add support for a rockchip-tpl entryJonas Karlman
The rockchip-tpl entry can be used when an external TPL binary should be used instead of the normal U-Boot TPL. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Eugen Hristev <eugen.hristev@collabora.com>
2023-02-28rockchip: dts: rk3328: fix sdram paramsJonas Karlman
The rk3328 sdram driver read sdram parameters from the devicetree into a struct rk3328_sdram_params using dev_read_u32_array. After commit 5ab30c3176bf ("ram: rockchip: Update ddr pctl regs for px30") changed the size of struct ddr_pctl_regs, a member of struct rk3328_sdram_params, U-Boot TPL can no longer initialize DRAM on RK3328. Add ten u32 to the sdram parameter array in devicetree to align with this size change. This fixes DRAM initialization on RK3328. Fixes: 5ab30c3176bf ("ram: rockchip: Update ddr pctl regs for px30") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # roc-rk3328-cc
2023-02-28rockchip: sdram: add dram bank with usable memory beyond 4GBJonas Karlman
Add a second dram bank of usable memory beyond the blob of space for peripheral near 4GB. Any memory that exists beyond the 4GB mark is added to the second bank. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28rockchip: sdram: add basic support for sdram reg info version 3Jonas Karlman
Newer DRAM initialization blobs from vendor can encode sdram info in a new version 3 format. The new format makes use of more bits in sys_reg3 compared to the version 2 format. Add basic support for detecting the version 3 format and decoding the high bits used for ddrtype. This fixes decode of sdram size on my RK3568 boards that have LPDDR4X. Details on the new format was deciphered from vendor u-boot commit [1]. [1] https://github.com/rockchip-linux/u-boot/commit/c69667e0e2bf4290ab1f408fcde58b8806ac266b Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28rockchip: ringneck: fix SDRAM init failQuentin Schulz
CONFIG_RAM_PX30_DDR4 got renamed to CONFIG_RAM_ROCKCHIP_DDR4 in commit 26f92be07e2a ("ram: rockchip: Add common ddr type configs"). Since both patchsets were merged unbeknownst to the other, the conflict wasn't detected while testing each patchset individually and could only be observed after a merge to master branch. Fixes: c925be73a0a8 ("rockchip: add support for PX30 Ringneck SoM on Haikou Devkit") Cc: Quentin Schulz <foss+uboot@0leil.net> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28mmc: rockchip_dw_mmc: fix DDR52 8-bit mode handlingJohn Keeping
The RK3288 TRM states that, for 8-bit DDR modes: The CLKDIV register should always be programmed with a value higher than zero (0); that is, a clock divider should always be used for 8-bit DDR mode. In Linux, the driver applies this logic for all SoCs using the driver and does not distinguish RK3288, so presumably this requirement is the same for all other Rockchip SoCs using this IP. Add the necessary code to double the clock frequency when 8-bit DDR is selected. The dw_mmc core already handles setting CLKDIV correctly given the input clock and desired bus clock. Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2023-02-28arm: dts: rockchip: rk3399: nanopi-r4s: Provide smbios sysinfoChristian Kohlschütter
Provide human-readable manufacturer and product names for the FriendlyELEC NanoPi R4S. Enable CONFIG_SYSINFO and CONFIG_SYSINFO_SMBIOS by default. Signed-off-by: Christian Kohlschütter <christian@kohlschutter.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-27Prepare v2023.04-rc3v2023.04-rc3Tom Rini
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-02-27configs: Resync with savedefconfigTom Rini
Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
2023-02-23Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-tegraTom Rini
2023-02-23Merge branch '2023-02-23-assorted-fixes'Tom Rini
- btrfs bugfix, silence a bunch of gcc-12.2 linker warnings finally, relax one of the trace test time requirements (so CI doesn't fail due to test being slightly slow, but still correct), and correct env on MMC and checking for where GPT can be
2023-02-23ARM: tegra20: implement BCT patchingSvyatoslav Ryhel
This function allows updating bootloader from u-boot on production devices without need in host PC. Be aware! It works only with re-crypt BCT. Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20 Signed-off-by: Ramin Khonsari <raminterex@yahoo.com> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23ARM: tegra30: implement BCT patchingRamin Khonsari
This function allows updating bootloader from u-boot on production devices without need in host PC. Be aware! It works only with re-crypted BCT. Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30 Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30 Signed-off-by: Ramin Khonsari <raminterex@yahoo.com> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23ARM: tegra: crypto: extend crypto functionalSvyatoslav Ryhel
Add support for encryption, decryption and signinig with non-zero key saving backward compatibility. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23ARM: tegra: expose crypto module for all Tegra SoCsSvyatoslav Ryhel
Move crypto module from T20 only into common Tegra dir. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Signed-off-by: Tom <twarren@nvidia.com>
generated by cgit v1.2.3 (git 2.0.4) at 2025-10-28 20:22:29 +0000