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Now that we have a damage tracking API, let's populate damage done by
UEFI payloads when they BLT data onto the screen.
Signed-off-by: Alexander Graf <agraf@csgraf.de>
Reported-by: Da Xue <da@libre.computer>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
[Alper: Add struct comment for new member]
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Link: https://lore.kernel.org/u-boot/20230821135111.3558478-10-alpernebiyasak@gmail.com/
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Let's report the video damage when we draw a bitmap on the screen. This
way we can later lazily flush only relevant regions to hardware.
Signed-off-by: Alexander Graf <agraf@csgraf.de>
Reported-by: Da Xue <da@libre.computer>
Reviewed-by: Simon Glass <sjg@chromium.org>
Link: https://lore.kernel.org/u-boot/20230821135111.3558478-9-alpernebiyasak@gmail.com/
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With VIDEO_DAMAGE, the video uclass tracks updated regions of the frame
buffer in order to avoid unnecessary work during a video sync. Enable
the config in sandbox and add a test for it, by printing strings at a
few locations and checking the tracked region.
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Adjust test avoid temporary failures in this patch:
Signed-off-by: Simon Glass <sjg@chromium.org>
Link: https://lore.kernel.org/u-boot/20230821135111.3558478-8-alpernebiyasak@gmail.com/
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Now that we have a damage tracking API, let's populate damage done by
vidconsole drivers. We try to declare as little memory as damaged as
possible.
Signed-off-by: Alexander Graf <agraf@csgraf.de>
Reported-by: Da Xue <da@libre.computer>
[Alper: Rebase for met->baseline, fontdata->height/width, make rotated
console_putc_xy() damages pass tests, edit patch message]
Co-developed-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Link: https://lore.kernel.org/u-boot/20230821135111.3558478-7-alpernebiyasak@gmail.com/
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Let's report the video damage when we fill parts of the screen. This
way we can later lazily flush only relevant regions to hardware.
Signed-off-by: Alexander Graf <agraf@csgraf.de>
Reported-by: Da Xue <da@libre.computer>
[Alper: Move from video_clear() to video_fill(), video_fill_part()]
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Link: https://lore.kernel.org/u-boot/20230821135111.3558478-6-alpernebiyasak@gmail.com/
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We are going to introduce image damage tracking to fasten up screen
refresh on large displays. This patch adds damage tracking for up to
one rectangle of the screen which is typically enough to hold blt or
text print updates. Callers into this API and a reduced dcache flush
code path will follow in later patches.
Signed-off-by: Alexander Graf <agraf@csgraf.de>
Reported-by: Da Xue <da@libre.computer>
[Alper: Use xstart/yend, document new fields, return void from
video_damage(), declare priv, drop headers, use IS_ENABLED()]
Co-developed-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Link: https://lore.kernel.org/u-boot/20230821135111.3558478-5-alpernebiyasak@gmail.com/
Reviewed-by: Simon Glass <sjg@chromium.org>
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With VIDEO_COPY enabled, only the modified parts of the frame buffer are
intended to be copied to the hardware. Add a test that checks this, by
overwriting contents we prepared without telling the video uclass and
then checking if the overwritten contents have been redrawn on the next
sync.
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Link: https://lore.kernel.org/u-boot/20230821135111.3558478-4-alpernebiyasak@gmail.com/
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The video tests have a helper function to generate a pseudo-digest of
frame buffer contents, but it only does so for the main one. There is
another check that the copy frame buffer is the same as that. But
neither is enough to test if only the modified regions are copied to the
copy frame buffer, since we will want the two to be different in very
specific ways.
Add a boolean argument to the existing helper function to indicate which
frame buffer we want to inspect, and update the existing callers.
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Link: https://lore.kernel.org/u-boot/20230821135111.3558478-3-alpernebiyasak@gmail.com/
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While checking frame buffer contents, the video tests also check if the
copy frame buffer contents match the main frame buffer. To test if only
the modified regions are updated after a sync, we will need to create
situations where the two are mismatched. Split this check into another
function that we can skip calling, since we won't want it to error on
those mismatched cases.
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Link: https://lore.kernel.org/u-boot/20230821135111.3558478-2-alpernebiyasak@gmail.com/
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It's currently possible to make the bootloader crash on calling
clk_set_rate caused by the loop in clk_clean_rate_cache.
The loop assume that every child of the clock node are also clock
device but this is not always the case. For example it's common for a
clock to bind to a reset device or also expose a syscon if the clock
register map is also used to apply special configuration.
In such case, on accessing a device as a clock, the bootloader crash. To
correctly handle this, check if the child device is actually a clock and
ignore otherwise.
Fixes: 6b7fd3128f71 ("clk: fix set_rate to clean up cached rates for the hierarchy")
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
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CONFIG_SYS_NONCACHED_MEMORY is defined as hex, not bool. It should be
replaced with CONFIG_SYS_HAS_NONCACHED_MEMORY when switched from #ifdef to
CONFIG_IS_ENABLED().
Fixes: 6c171f7a184 (common: board: make initcalls static)
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@codethink.co.uk> # rock5b
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
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SST(sst26wf016) flashes have multiple erase block sizes, including
8 KB, 32 KB, and 64 KB. Since a 64 KB sector erase cannot be performed
on all blocks, the 4 KB sector erase command should be used instead.
Enabling the SPI_FLASH_USE_4K_SECTORS configuration allows the use of
4 KB sector erases, but it may increase the erase operation time for large
memory flashes.
This reverts commit 34cd4a72fb2d113e2754c0d643618a8e3fa549ab
MEMORY ORGANIZATION:
The SST26WF016B/016BA SQI memory array is organized
in uniform, 4 KByte erasable sectors with the following
erasable blocks: eight 8 KByte parameter, two
32 KByte overlay, and thirty 64 KByte overlay blocks.
See Figure 3-1.
Top of Memory Block
┌──────────┐
│ 8 KByte │
├──────────┤
│ 8 KByte │
├──────────┤
│ 8 KByte │
├──────────┤
│ 8 KByte │
├──────────┤
│ 32 KByte │
├──────────┤
│ 64 KByte │
├──────────┤
│ 64 KByte │
├──────────┤
│ 64 KByte │
├──────────┤
│ 32 KByte │
├──────────┤
│ 8 KByte │
├──────────┤
│ 8 KByte │
├──────────┤
│ 8 KByte │
├──────────┤
│ 8 KByte │
└──────────┘
Bottom of Memory Block
┌────────────────────────────────┐
│ 64 KByte │
├────────────────────────────────┤
│ 64 KByte │
└────────────────────────────────┘
Expanded View:
┌──────┐ ┌──────┐ ┌──────┐ ┌──────┐
│ 4 KB │ │ 4 KB │ │ 4 KB │ │ 4 KB │
├──────┤ ├──────┤ ├──────┤ ├──────┤
│ . . . (continues) . . . │
└──────┘ └──────┘ └──────┘ └──────┘
2 Sectors for 8 KByte blocks
8 Sectors for 32 KByte blocks
16 Sectors for 64 KByte blocks
Link: https://ww1.microchip.com/downloads/en/DeviceDoc/20005013D.pdf
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
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QSPI driver performs chip select operation before every read/write
access. During this operation, driver needs to enable and disable
the QSPI controller. This may cause data loss if there is inadvertent
halting of any ongoing read/write operation. To avoid this scenario,
waiting for the QSPI status to be idle before next read/write
operation is implemented.
Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
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Takahiro Kuwano <Takahiro.Kuwano@infineon.com> says:
Those are 3.0V, 256Mb/2Gb NOR Flash devices with Octal interface.
Same fanctionalities with 1.8V version that are already supported.
Link: https://lore.kernel.org/r/cover.1743575001.git.Takahiro.Kuwano@infineon.com
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Infineon S28HL02GT is 3.0V, 2Gb Flash device with Octal interface.
It has the same functionalities with S28HS02GT.
Link: https://www.infineon.com/dgdl/Infineon-S28HS02GT_S28HS04GT_S28HL02GT_S28HL04GT_2Gb_4Gb_SEMPER_Flash_Octal_interface_1.8V_3.0V-DataSheet-v01_00-EN.pdf?fileId=8ac78c8c7e7124d1017f0631e33714d9
Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
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Infineon S28HL256T is 3.0V, 256Mb Flash device with Octal interface.
It has the same functionalities with S28HS256T.
Link:https://www.infineon.com/dgdl/Infineon-S28HS256T_S28HL256T_256Mb_SEMPER_Flash_Octal_interface_1_8V_3-DataSheet-v02_00-EN.pdf?fileId=8ac78c8c8fc2dd9c018fc66787aa0657
Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
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At the moment a mixture of ifdef(CONFIG_IS_ENABLED) and
CONFIG_IS_ENABLED(SPI_FLASH_BAR) is used in the spi-nor framework.
This leads to misbehaviour in the SPL as there is no Kconfig option
CONFIG_SPL_SPI_FLASH_BAR. This commit standardizes the use of
CONFIG_SPI_FLASH to get SPLs that load U-Boot proper from the
SPI flash to work again.
Fixes: 9bb02f7 (mtd: spi-nor: Fix the spi_nor_read() when config SPI_STACKED_PARALLEL is enabled)
Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com>
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Since the opcode SPINOR_OP_CHIP_ERASE (0xc7) is not supported
for the mt35xu01g/2g flashes, the NO_CHIP_ERASE flag has been added
to enable sector erase functionality instead.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
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This adds the vexpress_fvp and vexpress_fvp_bloblist platforms to the
list of platforms we test via emulator in CI. In order to do this we
need to first have our container runtime have TF-A builds for the
vexpress_fvp platform, both with and without transfer list support as
well as installing "telnet" so that we can access console. In the CI
files we check for the existence of /opt/tf-a/${TEST_PY_BD} and if
found, copy bl1.bin and fip.bin to /tmp and set the variables so that we
can later run FVP to run.
Note that we currently disable the hostfs (semihosting) tests as they
trigger a bug in FVP. This has been reported upstream, and can be
enabled when fixed.
Reviewed-by: Harrison Mutai <harrison.mutai@arm.com>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
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Signed-off-by: Tom Rini <trini@konsulko.com>
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The mtd partition offset must be calculated first as it will be
referenced when calculating the mtd partition size.
Change-Id: Iccfd101b0a9597ac240c25670da638a82af28980
Fixes: 1ca97ee9039 (mtd: mtdpart: Support MTD_SIZE_REMAINING with unallocated memory area)
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Reported-by: Francesco Dolcini <francesco@dolcini.it>
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getopt_long() expects a NULL-terminated list of structures. The current
list in mkimage does not have a zero-filled structure at the end, which
can cause getopt_long() to walk past the end of the array when passing
an unknown option, causing a segmentation fault.
As a reproducer, the following command causes a segmentation fault
(tested in Debian 12):
mkimage --foobar
Signed-off-by: Carlos López <carlos.lopezr4096@gmail.com>
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The LMB memory region attributes flags are used to specify the
behaviour of the memory regions with respect to allocations -- for
e.g. it is allowed to re-allocate a memory region already reserved
with the LMB_NONE flag. The flags use values with different bit
positions through the BIT() macro. Move the LMB_NOMAP value to bit
position 1, and also move the other flags accordingly. Using bit
position 0 for LMB_NOMAP results in the logic in
lmb_print_region_flags() to break, which prints an incorrect value for
the regions with LMB_NOMAP atribute.
Fixes: 3d56c06551d ("lmb: Move enum lmb_flags to a u32")
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
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fix the following typos
- from "categorys" to "categories"
- from "indivdually" to "individually"
Signed-off-by: Aristo Chen <aristo.chen@canonical.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
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As this driver needs to use the special sandbox <asm/malloc.h> header
rather than normal malloc, it must be careful of the includes it brings
in. It does not need <spi.h> for anything, so drop it.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
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Currently, the phy_config() API is invoked by the driver only once since it
has been probed. While this works in general, it doesn't allow the driver
to bring the PHY back to its default reset state. As a result, the driver
might not be able to recover the PHY from a bad state. To address this,
move phy_config() into the driver's start callback (am65_cpsw_start()).
Apart from providing the means to recover the PHY in the event of failure,
the implementation is in line with the idea of "reset and configure" that
is already followed by am65_cpsw_start() when it comes to programming the
CPSW MAC.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
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Mark Kettenis <kettenis@openbsd.org> says:
This is a collection of improvements for the Apple RTKit code
that we have been carrying downstream for some time now.
Link: https://lore.kernel.org/r/20250420115808.94272-1-kettenis@openbsd.org
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The new OSLog region in MTP (firmware 13.3+) persists on handoff to
Linux. To avoid having to come up with some weird DART handoff or DAPF
tricks, let's just steal some of the coprocessor's dedicated SRAM. This
keeps it happy and Linux doesn't need any special handoff then.
Signed-off-by: Hector Martin <marcan@marcan.st>
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
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To be used for special-case oslog support in rtkit-helper.
Signed-off-by: Hector Martin <marcan@marcan.st>
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
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This will work for u-boot itself, but needs a special workaround in the
MTP driver for Linux handoff to work.
Signed-off-by: Hector Martin <marcan@marcan.st>
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
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This driver handles the MTP ASC coprocessor, which does not need any
special handling on the RTKit side and communicates out-of-band.
Signed-off-by: Hector Martin <marcan@marcan.st>
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
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For devices without specific buffer methods, just assume we can give
them raw memory pointers when they request a buffer.
Signed-off-by: Hector Martin <marcan@marcan.st>
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
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This is required for MTP to work properly
Signed-off-by: Hector Martin <marcan@marcan.st>
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
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https://gitlab.denx.de/u-boot/custodians/u-boot-imx
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/25974
- Fix power-domain ref counting regression.
- Fix i.MX8MP USB clock regression.
- Fix i.MX8MM osc_32k regression in SPL.
- Finish converting clock-osc-24 back to osc_24 on i.MX.
- Several imx8mp capricorn updates.
- Update Stefano Babic's email address.
- Fix fsl_qspi bug by moving AHB read buffer config after LUT.
- Fix verdin imx95 sku 0089 pid4.
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This series from Raymond Mao <raymond.mao@linaro.org> fixes some cases
of passing the device tree to U-Boot via standard passage and then
ensures that we set the environment variable of the device tree
correctly in this case.
Link: https://lore.kernel.org/r/20250331224011.2734284-1-raymond.mao@linaro.org
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We have improvements to the reliability of H6 and H616 DRAM
initialisation, hopefully avoiding those occasional size misdetections
many people reported before.
Also there is some modernisation of the USB PHY code, to use DT provided
regulators and GPIOs, instead of relying on this being badly duplicated
in Kconfig. This also happens to fix broken USB operations for older
boards (using the A20 SoCs, for instance), which were clashing over
grabbing some GPIOs, leading to a driver bailout. There is also some
rework of the H6/H616 SPL clock code, to prepare it for being reused by
the upcoming Allwinner A523 support. This drops the usage of C structs
to model MMIO register frames, and replaces them by using an addition of
the base address with a macro defined offset. Also in preparation for
A523 there is one fix and one addition for the FEL code, to prepare for
the GICv3 interrupt controller that the new SoC uses. And since this is
a simple fix, and was ready, there is also the watchdog driver for that
new SoC. Finally tossing in an easy fix to some H616 defconfig files to
enable eMMC.
I also use the opportunity to enable proper page table protection
(observing read-only and no-execute attributes), support for which the
arm64 port recently gained. I didn't spot any issues on my arm64 board
tests, but it can be easily disabled or backed out again in case any
issues arise.
Full support for the two new SoC series (A133 and A523) we are working
on is not quite ready yet, but might follow still a bit later if
progress permits.
CI passed, and boot-tested on at least one board with a H616, H6, A64,
H3, A20, T113s.
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With the SPL clock code and the DRAM init routine we converted all users
of the H6 class "struct sunxi_prcm_reg" over to use #define'd register
offsets now.
Drop the whole definition of this struct now, since it's not needed
anymore, for all H6 and H616 boards.
This removes the entire fragile and questionable definition, and allows
new SoCs to share the code more easily.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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The Allwinner H6 and H616 DRAM initialisation code uses a complex C
struct, modelling the PRCM clock register frame. For those SoCs, this
struct contains 20 registers, but the DRAM code only uses two of them.
Since we want to get rid of this struct, drop the usage of the struct in
the H6 and H616 DRAM code, by using #define'd register names and their
offset, and then adding those names to the base pointer.
This removes one more user of the PRCM clock register struct.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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U-Boot drivers often revert to using C structures for modelling hardware
register frames. This creates some problems:
- A "struct" is a C language construct to group several variables
together. The details of the layout of this struct are partly subject
to the compiler's discretion (padding and alignment).
- The "packed" attribute would force a certain layout, but we are not
using it.
- The actual source of information from the data sheet is the register
offset. Here we create an artificial struct, carefully tuning the
layout (with a lot of reserved members) to match that offset. To help
with correctness, we put the desired information as a *comment*,
though this is purely for the human reader, and has no effect on the
generated layout. This sounds all very backwards.
- Using a struct suggests we can assign a pointer and then access the
register content via the members. But this is not the case, instead
every MMIO register access must go through specific accessor functions,
to meet the ordering and access size guarantees the hardware requires.
- We share those structs in code shared across multiple SoC families,
though most SoCs define their own version of the struct. Members must
match in their name, across every SoC, otherwise compilation will fail.
We work around this with even more #ifdefs in the shared code.
- Some SoCs have an *almost* identical layout, but differ in a few
registers. This requires hard to maintain #ifdef's in the struct
definition.
- Some of the register frames are huge: the H6 CCU device defines 127
registers. We use 15 of them. Still the whole frame would need to be
described, which is very tedious, but for no reason.
- Adding a new SoC often forces people to decide whether to share an
existing struct, or to create a new copy. For some cases (say like 80%
similarity) this works out badly either way.
The Linux kernel heavily frowns upon those register structs, and instead
uses a much simpler solution: #define REG_NAME <offset>
This easily maps to the actual information from the data sheet, and can
much simpler be shared across multiple SoCs, as it allows to have all
SoC versions visible, so we can use C "if" statements instead of #ifdef's.
Also it requires to just define the registers we need, and we can use
alternative locations for some registers much more easily.
Drop the usage of "struct sunxi_prcm_reg" in the H6 SPL clock code, by
defining the respective register names and their offsets, then adding
them to the base pointer.
We cannot drop the struct definition quite yet, as it's also used in
other drivers, still.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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With the SPL clock code, the MMC driver, and the DRAM init routine we
converted all users of the H6 class "struct sunxi_ccm_reg" over to use
#define'd register offsets now.
Drop the whole definition of this struct now, since it's not needed
anymore, for all H6 and H616 boards.
This removes the entire fragile and questionable definition, and allows
new SoCs to share the code more easily.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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The Allwinner H6 DRAM initialisation code uses a complex C struct,
modelling the clock device's register frame. For this SoC, the struct
contains 127 registers, but the DRAM code only uses four of them.
Since we want to get rid of this struct, drop the usage of the struct in
the H6 DRAM code, by using #define'd register names and their offset, and
then adding those names to the base pointer.
This removes one more user of the clock register struct.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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The Allwinner H616 DRAM initialisation code uses a complex C struct,
modelling the clock device's register frame. For this SoC, the struct
contains 127 registers, but the DRAM code only uses four of them.
Since we want to get rid of this struct, drop the usage of the struct in
the H616 DRAM code, by using #define'd register names and their offset,
and then adding those names to the base pointer.
This removes one more user of the clock register struct.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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The Allwinner MMC code uses a complex C struct, modelling the clock
device's register frame. We rely on sharing the member names across all
Allwinner SoCs, which is fragile.
Drop the usage of the struct in the MMC code, by using #define'd
register names and their offset, and then adding those names to the base
pointer. This requires to define those offsets for all SoCs, but since we
only use between four and six clock registers in the MMC code, this is
easily done.
This removes one common user of the clock register struct.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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U-Boot drivers often revert to using C structures for modelling hardware
register frames. This creates some problems:
- A "struct" is a C language construct to group several variables
together. The details of the layout of this struct are partly subject
to the compiler's discretion (padding and alignment).
- The "packed" attribute would force a certain layout, but we are not
using it.
- The actual source of information from the data sheet is the register
offset. Here we create an artificial struct, carefully tuning the
layout (with a lot of reserved members) to match that offset. To help
with correctness, we put the desired information as a *comment*,
though this is purely for the human reader, and has no effect on the
generated layout. This sounds all very backwards.
- Using a struct suggests we can assign a pointer and then access the
register content via the members. But this is not the case, instead
every MMIO register access must go through specific accessor functions,
to meet the ordering and access size guarantees the hardware requires.
- We share those structs in code shared across multiple SoC families,
though most SoCs define their own version of the struct. Members must
match in their name, across every SoC, otherwise compilation will fail.
We work around this with even more #ifdefs in the shared code.
- Some SoCs have an *almost* identical layout, but differ in a few
registers. This requires hard to maintain #ifdef's in the struct
definition.
- Some of the register frames are huge: the H6 CCU device defines 127
registers. We use 15 of them. Still the whole frame would need to be
described, which is very tedious, but for no reason.
- Adding a new SoC often forces people to decide whether to share an
existing struct, or to create a new copy. For some cases (say like 80%
similarity) this works out badly either way.
The Linux kernel heavily frowns upon those register structs, and instead
uses a much simpler solution: #define REG_NAME <offset>
This easily maps to the actual information from the data sheet, and can
much simpler be shared across multiple SoCs, as it allows to have all
SoC versions visible, so we can use C "if" statements instead of #ifdef's.
Also it requires to just define the registers we need, and we can use
alternative locations for some registers much more easily.
Drop the usage of "struct sunxi_ccm_reg" in the H6 SPL clock code, by
defining the respective register names and their offsets, then adding
them to the base pointer.
We cannot drop the struct definition quite yet, as it's also used in
other drivers, still.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Thanks for Jernej's JTAG debugging effort, it turns out that the BROM
expects SP_IRQ to be saved and restored, when we want to enter back into
FEL after the SPL's AArch64 stint.
Save and restore SP_IRQ as part of the FEL state handling. The banked
MRS/MSR access to SP_IRQ, without actually being in IRQ mode, was
introduced with the ARMv7 virtualisation extensions. The Arm Cortex-A8
cores used in the A10/A13s or older F1C100s SoCs would not support that,
but this code here is purely in the ARMv8/AArch64 code path, so it's
safe to use unconditionally.
Reported-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
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To be able to return to the BootROM FEL USB debug code, we must restore
the core's state as accurately as possible after the SPL has been run.
Since the BootROM runs in AArch32, but the SPL uses AArch64, this requires
a core reset, which clears the core's state.
So far we were saving and restoring the required registers like SCTLR
and VBAR, but could ignore the interrupt controller's state (GICC), since
that lives in MMIO registers, unaffected by a core reset.
Newer Allwinner SoCs now feature a GICv3 interrupt controller, which keeps
some GIC state in architected system registers, and those are cleared
when we switch back to AArch32.
To enable FEL operation on the Allwinner A523 SoC,
Add AArch32 assembly code to save and restore the ICC_PMR and ICC_IGRPEN1
system registers. The other GICv3 sysregs are either not relevant for the
BROM operation, or haven't been changed from their reset defaults by the
BROM anyway.
This enables FEL operation on the Allwinner A523 family of SoCs.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
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The Allwinner A523 SoC moved the watchdog into a separate MMIO frame,
and also shifted the registers a bit: the control, config, and mode
register are located four bytes earlier.
Add the new compatible string, and connect it to the new struct
describing the new register layout.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Stefan Roese <sr@denx.de>
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Now that the USB PHY driver uses the device tree to get the VBUS detect
and USB ID GPIOs, these Kconfig symbols are unused. Remove them from
their Kconfig definition, and also from all defconfig files.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
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So far Allwinner boards controlled the USB OTG ID detection via the
respective GPIO pin specified in Kconfig, as a string. All boards should
have the same GPIO already specified in the devicetree, in the
usb0_id_det-gpios property.
Convert the usage of the Kconfig configured GPIO over to query that
information from the devicetree, then use the existing DM GPIO
infrastructure to request the GPIO.
Only PHY0 supports USB-OTG, so limit the GPIO request to that PHY, to
avoid claiming it multiple times.
This removes the need to name that GPIO in the defconfig file.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
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So far Allwinner boards controlled the USB VBUS detection via the
respective GPIO pin specified in Kconfig, as a string. All boards should
have the same GPIO already specified in the devicetree, in the
usb0_vbus_det-gpios property.
Convert the usage of the Kconfig configured GPIO over to query that
information from the devicetree, then use the existing DM GPIO
infrastructure to request the GPIO.
Only PHY0 supports USB-OTG, so limit the GPIO request to that PHY, to
avoid claiming it multiple times.
This removes the need to name that GPIO in the defconfig file.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
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