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2023-01-16Merge tag 'u-boot-rockchip-20230117' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-rockchip - Add support for rv1126 soc and rv1126 neu2 io board; - Add support for rk3399 pine64 pinephone pro board; - dts sync from linux for rk3399 and px30; - Add support for PX30 Ringneck SoM board;
2023-01-16rockchip: add support for PX30 Ringneck SoM on Haikou DevkitQuentin Schulz
The PX30-µQ7 (Ringneck) is a system-on-module featuring the Rockchip PX30 in a micro Qseven-compatible form-factor. PX30-µQ7 features: * CPU: quad-core Cortex-A35 * DRAM: 2GB dual-channel * eMMC: onboard eMMC * SD/MMC * TI DP83825I 10/100Mbps PHY * USB: * USB2.0 dual role port * 3x USB2.0 host via onboard USB2.0 hub * Display: MIPI-DSI * Camera: MIPI-CSI * onboard 2.4GHz WiFi + Bluetooth module * Companion Controller: on-board additional microcontroller (STM32 Cortex-M0 or ATtiny): * RTC * fan controller * CAN (only STM32) The non-U-Boot DTS files are imported from Linux v6.2-rc2. Cc: Quentin Schulz <foss+uboot@0leil.net> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
2023-01-16arm64: dts: rockchip: sync px30 DTSI with Linux kernel v6.1Quentin Schulz
Sync the px30 dtsi from Linux kernel v6.1. Cc: Quentin Schulz <foss+uboot@0leil.net> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
2023-01-16rockchip: px30: insert u-boot, spl-boot-device into U-Boot device treeQuentin Schulz
It is possible to boot U-Boot proper from a different storage medium than the one used by the BOOTROM to load the SPL. This information is stored in the u-boot,spl-boot-device Device Tree property and is accessible from U-Boot proper so that it has knowledge at runtime where it was loaded from. Let's add support for this feature for px30. Cc: Quentin Schulz <foss+uboot@0leil.net> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
2023-01-16rockchip: px30: list possible SPL boot devicesQuentin Schulz
BOOTROM sets a bit in a CPU register so that the software can know from where the first stage bootloader was booted. One use case for this is to specify the default loading medium for U-Boot proper to match the one used by the BOOTROM to load the SPL (same-as-spl in u-boot,spl-boot-order). Let's create the mapping between BOOTROM value and Device Tree node names for MMC devices. Cc: Quentin Schulz <foss+uboot@0leil.net> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
2023-01-16rockchip: px30: fix CFG_IRAM_BASEQuentin Schulz
The IRAM on PX30 (or Int_MEM in datasheet) starts at 0xff0e0000 and not 0xff020000 as rightfully stated in the FIXME comment. Let's fix it so that BROM_BOOTSOURCE_ID_ADDR points to the correct address for PX30. Fixes: 46281a76bee3 ("rockchip: add core px30 headers") Cc: Quentin Schulz <foss+uboot@0leil.net> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
2023-01-16rockchip: px30: fix possibly unused grf and cru variablesQuentin Schulz
The grf and cru are only used when no UART base is provided by the user (defaults to UART2) or for UART1, UART3 and UART5 to be used for the debug UART. Therefore, let's surround those variable definitions with the proper checks. This wasn't an issue before support for UART0 was added, because all cases were using cru and grf. UART0 only uses pmucru so there's a need to not define those variables anymore. Fixes: d0af506625ff ("rockchip: px30: support debug uart on UART0") Cc: Quentin Schulz <foss+uboot@0leil.net> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16rockchip: Add initial support for the PINE64 Pinephone ProPeter Robinson
The Pinephone Pro is another device by PINE64. It's closely related to the Pinebook Pro of which this initial support is derived from. Specification: - A variant of the Rockchip RK3399 - A 6 inch 720*1440 DSI display - Front and rear cameras - Type-C interface with alt mode display (DP 1.2) and PD charging - 4GB LPDDR4 RAM - 128GB eMMC - mSD card slot - An AP6255 module for 802.11ac WiFi and Bluetooth 5 - Quectel EG25-G 4G/LTE modem Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-16arm64: dts: rk3399: Add upstream Pinephone Pro dtsPeter Robinson
Initial support for the PinePhone Pro has now landed upstream in Linux 6.1 RC1 so sync the dts from 6.2-rc1 for initial support. Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
2023-01-16board: rockchip: Add Edgeble Neu2 IO BoardJagan Teki
Neural Compute Module 2(Neu2) IO board is an industrial form factor IO board from Edgeble AI. General features: - microSD slot - MIPI DSI connector - 2x USB Host - 1x USB OTG - Ethernet - mini PCIe - Onboard PoE - RS485, RS232, CAN - Micro Phone array - Speaker - RTC battery slot - 40-pin expansion Neu2 needs to mount on top of this IO board in order to create complete Edgeble Neural Compute Module 2(Neu2) IO platform. Add support for it. Signed-off-by: Jagan Teki <jagan@edgeble.ai>
2023-01-16ARM: dts: rockchip: Add rv1126-u-boot.dtsiJagan Teki
Add u-boot,dm-spl and u-boot,dm-pre-reloc related properties for Rockchip RV1126 SoC. Both eMMC and SD boot are tested in Edgeble Neu2 SoM. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16ARM: dts: rockchip: rv1126: Add Edgeble Neural Compute Module 2(Neu2) IOJagan Teki
Neural Compute Module 2(Neu2) IO board is an industrial form factor evaluation board from Edgeble AI. General features: - microSD slot - MIPI DSI connector - 2x USB Host - 1x USB OTG - Ethernet - mini PCIe - Onboard PoE - RS485, RS232, CAN - Micro Phone array - Speaker - RTC battery slot - 40-pin expansion Neu2 needs to mount on top of this IO board in order to create complete Edgeble Neural Compute Module 2(Neu2) IO platform. Add support for it. Signed-off-by: Jagan Teki <jagan@edgeble.ai>
2023-01-16ARM: dts: rockchip: rv1126: Add Edgeble Neural Compute Module 2(Neu2)Jagan Teki
Neural Compute Module 2(Neu2) is a 96boards SoM-CB compute module based on Rockchip RV1126 from Edgeble AI. General features: - Rockchip RV1126 - 2/4GB LPDDR4 - 8/16/32GB eMMC - 2x MIPI CSI2 FPC connector - Fn-link 8223A-SR WiFi/BT Industrial grade (-40 °C to +85 °C) version of the same class of module called Neu2k powered with Rockchip RV1126K. Neu2 needs to mount on top of Edgeble IO boards for creating complete platform solutions. Add support for it. Signed-off-by: Jagan Teki <jagan@edgeble.ai>
2023-01-16rockchip: mkimage: Add rv1126 supportJagan Teki
Add support for rv1126 package header in mkimage tool. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16arm: rockchip: rv1126: Set dram area unsecure for SPLJagan Teki
Unsecure the dram area so that MMC, USB, and SFC controllers can able to read data from dram. Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16arm: rockchip: Add RV1126 arch core supportJagan Teki
Rockchip RV1126 is a high-performance vision processor SoC for IPC/CVR, especially for AI related application. Add arch core support for it. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Change-Id: I22fde40ec375e3c6aba39808abf252edc45d4b04
2023-01-16ARM: dts: rockchip: Add Rockchip RV1126 SoCJagan Teki
RV1126 is a high-performance vision processor SoC for IPC/CVR, especially for AI related application. It is based on quad-core ARM Cortex-A7 32-bit core which integrates NEON and FPU. There is a 32KB I-cache and 32KB D-cache for each core and 512KB unified L2 cache. It has build-in NPU supports INT8/INT16 hybrid operation and computing power is up to 2.0TOPs. This patch add basic core dtsi support. Signed-off-by: Jon Lin <jon.lin@rock-chips.com> Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
2023-01-16ARM: dts: rockchip: Add Rockchip RV1126 pinctrlJagan Teki
Add pinctrl definitions for Rockchip RV1126. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16arm: rockchip: Add grf header for rv1126Jagan Teki
Add GRF header for Rockchip RV1126. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16dt-bindings: power: Add power-domain header for rv1126Jagan Teki
Add power-domain header for RV1126 SoC from description in TRM. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16clk: rockchip: Add rv1126 clk supportJagan Teki
Add clock driver support for Rockchip RV1126 SoC. Signed-off-by: Joseph Chen <chenjh@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16dt-bindings: clk: Add dt-binding header for RV1126Jagan Teki
Add the dt-bindings header for the Rockchip RV1126, that gets shared between the clock controller and the clock references in the dts. Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16arch: rockchip: Add cru header for rv1126Jagan Teki
Add clock and reset unit header include for rv1126. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16pinctrl: rockchip: Add rv1126 supportJagan Teki
Add pinctrl driver for Rockchip RV1126. Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16pinctrl: rockchip: Add pinctrl route typesJagan Teki
Some pins in rockchip are routed via Top GRF and PMU GRF instead of direct regmap. Add support to handle all these routing paths so that the SoC pinctrl drivers will use them accordingly. Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16ram: rockchip: Add rv1126 lpddr4 supportJagan Teki
Add LPDDR4 detection timings and support for RV1126. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16ram: rockchip: rv1126: Control ddr init prints via DEBUGJagan Teki
Control the ddr init print messages via RAM_ROCKCHIP_DEBUG instead of printing by default. This gives an option to configs to enable these prints or not. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16ram: rockchip: Add rv1126 ddr driver supportJagan Teki
Add DDR driver for Rockchip RV1126 SoC. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16ram: rockchip: Add rv1126 ddr loader paramsJagan Teki
Add DDR loader parameters for Rockchip RV1126 SoC. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16ram: rockchip: Add rv1126 ddr3 supportJagan Teki
Add DDR3 detection timings for Rockchip RV1126 SoC. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16ram: rockchip: Update ddr pctl regs for px30Jagan Teki
Add full ddr pctl registers and bit masks for px30. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16ram: rockchip: Compute ddr capacity based on grf splitJagan Teki
DDR chip capacity is computed based on GRF split in some Rockchip SoC's like PX30 and RV1126. Add split argument in ddr print info so-that the respective ddr driver will pass the grf split. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16ram: rockchip: Add common ddr type configsJagan Teki
We have common ddr types in rockchip or in general. So use the common ddr type names instead of per Rockchip SoC to avoid confusion. The respective ddr type names will use on the associated ddr SoC driver as these drivers are built per SoC at a time. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16ram: Mark ram-uclass depend on TPL_DM or SPL_DMJagan Teki
ram-uclass is building irrespective of whether TPL_DM or SPL_DM is enabled. So control the ram uclass build based on TPL/SPL_DM. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16configs: roc-pc-rk3399: Enable rockchip efuse supportChristopher Obbard
Enable efuse support which allows reading of the cpuid#, serial# and also generates a unique mac address from the board's serial. Signed-off-by: Christopher Obbard <chris.obbard@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16rockchip: mkimage: make RC4 key constJohn Keeping
This is read-only data, so mark it as such. Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16rc4: mark key as constJohn Keeping
Key data is never written so the parameter can be const, which allows putting fixed keys in .rodata. Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16rockchip: puma-rk3399: sync DTS with Linux kernel next-20221114Quentin Schulz
This synchronizes the Device Trees related to Puma RK3399 SoM with Linux kernel next-20221114 to include two important changes pertaining to eMMC and SD card instability. Cc: Quentin Schulz <foss+uboot@0leil.net> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16rockchip: clk: add watchdog clock to px30_clk_enableQuentin Schulz
Add the PCLK_WDT_NS clock to px30_clk_enable so that the watchdog driver can probe since it wants to enable this clock. Cc: Quentin Schulz <foss+uboot@0leil.net> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16rockchip: px30: make watchdog and tsadc trigger a first global resetQuentin Schulz
By default, the PX30 is configured for watchdog and tsadc to trigger a second global reset which is a more permissive reset than first global reset. From TRM part 1 "2.3 System Reset Solution": glb_srstn_1 will reset the all logic, and glb_srstn_2 will reset the all logic except GRF, SGRF and all GPIOs. This enforces that the watchdog and tsadc trigger glb_srstn_1 as similarly done for RK3399 in U-Boot (in SDRAM driver for some reason?), TF-A and Coreboot. Cc: Quentin Schulz <foss+uboot@0leil.net> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-15Merge https://source.denx.de/u-boot/custodians/u-boot-shTom Rini
2023-01-15Merge https://source.denx.de/u-boot/custodians/u-boot-usbTom Rini
2023-01-14usb: gadget: dwc2_udc_otg: implement pullup()Mattijs Korpershoek
Pullup is used by the usb framework in order to do software-controlled usb_gadget_connect() and usb_gadget_disconnect(). Implement pullup() for dwc2 using the SOFT_DISCONNECT bit in the dctl register: * when pullup is on, clear SOFT_DISCONNECT * when pullup is off, set SOFT_DISCONNECT This is especially useful when a gadget disconnection is initiated but no board_usb_cleanup() is called. Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2023-01-14usb: gadget: fastboot: detach usb just before rebootingDario Binacchi
The patch fixes the following error when updating a BSH SMM S2 board: 3:72>Start Cmd:FB[-t 8000]: ucmd nand write ${loadaddr} nanddtb ${filesize} 3:72>Okay (0.023s) 3:72>Start Cmd:FB: reboot 3:72>Fail Bulk(R):LIBUSB_ERROR_IO(0s) The "fastboot reboot" command detaches the USB when it still needs to be used. So let's detach the USB just before the reset. CC: Mattijs Korpershoek <mkorpershoek@baylibre.com> Fixes: 5f7e01e9d5d800 ("usb: gadget: fastboot: detach usb on reboot commands") Suggested-by: Michael Trimarchi <michael@amarulasolutions.com> Co-developed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-01-14usb: hub: allow to increase HUB_DEBOUNCE_TIMEOUTPatrick Delaunay
Add a new CONFIG_USB_HUB_DEBOUNCE_TIMEOUT to increase the HUB_DEBOUNCE_TIMEOUT value, for example to 2s because some usb device needs around 1.5s or more to make the hub port status to be connected steadily after being powered off and powered on. This 2s value is aligned with Linux driver and avoids to configure "usb_pgood_delay" as a workaround for connection timeout on some USB device; normally the env variable "usb_pgood_delay" is used to delay the first query after power ON and thus the device answer, but this variable not used to increase the connection timeout delay. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-01-14configs: r8a77980: Condor: Enable MMC support by defaultAndrey Dolnikov
This enables MMC support, which is available on Condor board, by default. Signed-off-by: Andrey Dolnikov <andrey.dolnikov@cogentembedded.com> Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
2023-01-14ARM: renesas: condor: switch eMMC bus to 1V8Hai Pham
The eMMC card has two supplies, VCC and VCCQ. The VCC supplies the NAND array and the VCCQ supplies the bus. On Condor, the VCC is connected to 3.3V rail, while the VCCQ is connected to 1.8V rail. Adjust the pinmux to match the bus, which is always operating in 1.8V mode. Based on Linux commit 69efe4bbeda50745 ("arm64: dts: renesas: condor: Switch eMMC bus to 1V8") from Wolfram Sang Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
2023-01-14ARM: dts: renesas: condor: Enable SPI NOR fast-readMarek Vasut
This board requires SPI NOR fast-read, otherwise the SPI NOR access returns corrupted data. Enable the fast-read explicitly in DT as it has been disabled in the MTD subsystem by commit d008190920 ("mtd: spi-nor: Mask out fast read if not requested in DT") Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2023-01-14ARM: renesas: ulcb: Set CONFIG_TEXT_BASE=0x0 on R-Car Gen3 ULCBMarek Vasut
Since R-Car Gen3 already enables position independent build, also set CONFIG_TEXT_BASE=0x0 to finalize the switch. This is possible since 534f0fbd65 ("arm64: Fix relocation of env_addr if POSITION_INDEPENDENT=y") fixed current env_get_char() crash with CONFIG_TEXT_BASE=0x0 . This change permits us to start U-Boot from any location in DRAM instead of specific TEXT_BASE. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2023-01-14ARM: renesas: condor: Set CONFIG_TEXT_BASE=0x0 on R-Car Gen3 CondorMarek Vasut
Since R-Car Gen3 already enables position independent build, also set CONFIG_TEXT_BASE=0x0 to finalize the switch. This is possible since 534f0fbd65 ("arm64: Fix relocation of env_addr if POSITION_INDEPENDENT=y") fixed current env_get_char() crash with CONFIG_TEXT_BASE=0x0 . This change permits us to start U-Boot from any location in DRAM instead of specific TEXT_BASE. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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