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2021-07-06Merge branch '2021-07-06-platform-updates'Tom Rini
- mpc8379erdb DM_USB, DM_PCI and DM_ETH support. - Drop PCI support from the integrator family of boards - Add synquacer support - Assorted lpc32xx updates and improvements - snapdragon (and related) fixes, Broadcom iproc update
2021-07-06serial: serial_msm: Ensure BAM/single character mode are disabledStephan Gerhold
At the moment, the U-Boot serial_msm driver does not initialize the UART_DM_DMEN register with the required value. Usually this does not cause any problems, because there is Qualcomm's LK bootloader running before U-Boot which initializes the register with the correct value. It's important that this register is initialized correctly, because the U-Boot driver does not make use of the BAM/DMA or single character mode functionality of the UART controller. A different bootloader before U-Boot might initialize the register differently. For example, on DragonBoard 410c U-Boot can also be installed to the "aboot" partition (replacing LK entirely). In this case U-Boot is loaded directly by SBL, which seems to use the single-character mode for some reason. In single character mode there is always just one char in the FIFO, instead of the 4 characters expected by msm_serial_fetch(). It also causes issues with "earlycon" later in the Linux kernel, which tries to output 4 chars at once, but only the first char will be written. This causes early UART log in Linux to be corrupted like this: [ 00ano:ameoi .Q1B[ 00ac _idaM00080oo'ahani-lcle._20). 15NdNii 5 SPMSJ20:U2 [ 00rkoolmsamel [ 00Fw ]elamletopsioble [ 00ore instead of [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd030] [ 0.000000] Machine model: Qualcomm Technologies, Inc. APQ 8016 SBC [ 0.000000] earlycon: msm_serial_dm0 at MMIO 0x00000000078b0000 (options '') [ 0.000000] printk: bootconsole [msm_serial_dm0] enabled Make sure to initialize UART_DM_DMEN correctly to fix this issue when loading U-Boot directly after SBL (instead of through LK). There is no functional difference when loading U-Boot through LK since LK also initializes UART_DM_DMEN to 0x0. [1] [1]: https://git.linaro.org/landing-teams/working/qualcomm/lk.git/tree/platform/msm_shared/uart_dm.c?h=dragonboard410c-LA.BR.1.2.7-03810-8x16.0-linaro3#n203 Cc: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-07-06arm: dts: db410c: Add missing cd-gpios for SD card detectionStephan Gerhold
It looks like SD card detection is broken at the moment for DB410c. The eMMC is detected correctly, but the SD card is not. This is probably similar to the issue fixed in commit 850514740358 ("mmc: msm_sdhci: Use mmc_of_parse for setting host_caps") for eMMC, except that the SD card does not have a property like "non-removable" that skips the card detection. The SDHCI on DB410c cannot detect itself if a SD card is inserted, so add the necessary cd-gpios to make SD card detection work again. While at it, fix the #gpio-cells for the soc_gpios to avoid DTC warnings - the soc_gpios are actually already used with two cells for the gpio-leds so this was just wrong all the time. Cc: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-07-06arm: snapdragon: Fix typo in clk_bcr_update()Sheep Sun
Fix typo in clock-snapdragon.c Signed-off-by: Sheep Sun <sunxiaoyang2003@gmail.com>
2021-07-06arm: snapdragon: Use correct GICC register on APQ8016Sheep Sun
The GICC register used by u-boot is 0x0a20c000, which is actually a GICC for WCNSS, the WLAN processor. U-boot runs on the Application Processor, therefore it should use APCS GICC instead. Hence, correct it with APCS GICC register address. Signed-off-by: Sheep Sun <sunxiaoyang2003@gmail.com>
2021-07-06lpc32xx: ea-lpc3250devkitv2: enable i2c (DM)Trevor Woerner
Enable a DMed i2c driver for the ea-lpc3250devkitv2 board. Include some sample commands/output for testing. Signed-off-by: Trevor Woerner <twoerner@gmail.com>
2021-07-06Kconfig: convert CONFIG_SYS_I2C_LPC32XXTrevor Woerner
Convert the CONFIG_SYS_I2C_LPC32XX configuration symbol from an include directive to a Kconfig value. Signed-off-by: Trevor Woerner <twoerner@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-07-06lpc32xx: i2c: finish DM/OF codeTrevor Woerner
Add the of_match/compatible string to the lpc32xx i2c driver so it works correctly with device-tree. Signed-off-by: Trevor Woerner <twoerner@gmail.com>
2021-07-06lpc32xx: i2c: fix base addressTrevor Woerner
The lpc32xx driver was not obtaining the per-device base address correctly from the device tree. Fix the FIXME in order to get the correct base address. Signed-off-by: Trevor Woerner <twoerner@gmail.com>
2021-07-06lpc32xx: i2c: remove unused defineTrevor Woerner
The LPC32XX_I2C_STAT_DRMI is not used anywhere so remove it. Signed-off-by: Trevor Woerner <twoerner@gmail.com>
2021-07-06arm: lpc32xx: add EA LPC3250 DevKitv2 board supportTrevor Woerner
Add basic support for running U-Boot on the Embedded Artists LPC3250 Developer's Kit v2 board by launching U-Boot from the board's s1l loader (which comes pre-installed on the board). Signed-off-by: Trevor Woerner <twoerner@gmail.com>
2021-07-06lpc32xx: import device tree from LinuxTrevor Woerner
Import the dtsi, dts, and clock binding files for the lpc32xx ea3250 board directly and unmodified from the latest Linux kernel. Signed-off-by: Trevor Woerner <twoerner@gmail.com>
2021-07-06lpc32xx: Kconfig: switch to CONFIG_CONS_INDEXTrevor Woerner
There's nothing special or unique to the lpc32xx that requires its own config parameter for specifying the console uart index. Therefore instead of using the lpc32xx-specific CONFIG_SYS_LPC32XX_UART include parameter, use the already-available CONFIG_CONS_INDEX from Kconfig. Signed-off-by: Trevor Woerner <twoerner@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-07-06configs: synquacer: Enable EFI capsule update supportMasami Hiramatsu
Enable EFI capsule update support. With the EFI capsule update, you can update U-Boot, TF-A and OP-TEE. TF-A and OP-TEE are usually combined as a FIP binary, but if the binary is bigger than 480KB, you have to modify FIP header, split the OP-TEE and stores the OP-TEE binary in the different place. This configuration supports both cases. Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-07-06doc: qemu: arm64: Fix the documentation of capsule updateMasami Hiramatsu
Since the EDK2 GenerateCapsule script is out of date and it doesn't generate the supported version capsule file, the document should refer the mkeficapsule in tools. Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-07-06board: synquacer: Add DeveloperBox 96boards EE supportMasami Hiramatsu
Add the DeveloperBox 96boards EE support. This board is also known as Socionext SynQuacer E-Series. It contians one "SC2A11" SoC, which has 24-cores of arm Cortex-A53, and 4 DDR3 slots, 3 PCIe slots (1 4x port and 2 1x ports which are expanded via PCIe bridge chip), 2 USB 3.0 ports and 2 USB 2.0 ports, 2 SATA ports and 1 GbE, 64MB NOR flash and 8GB eMMC on standard MicroATX Form Factor. For more information, see this page; https://www.96boards.org/product/developerbox/ Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-07-06ARM: dts: synquacer: Add device trees for DeveloperBoxMasami Hiramatsu
Add device trees for 96boards EE DeveloperBox and basement SynQuacer SoC dtsi. These files are imported from EDK2 commit 83d38b0b4c0f240d4488c600bbe87cea391f3922 as-is (except for the changes #include path and some macros). And add U-Boot specific changes in synquacer-sc2a11-developerbox-u-boot.dtsi Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-07-06i2c: synquacer: SNI Synquacer I2C controllerJassi Brar
Add driver for class of I2C controllers found on Socionext Synquacer platform. Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2021-07-06spi: synquacer: Add HSSPI SPI controller driver for SynQuacerJassi Brar
This is a driver for the HSSPI SPI controller on SynQuacer SoC. The HSSPI has command sequence mode (memory mapped) and direct mode (FIFO access). The driver will operate it under the direct mode. And before booting OS, it switch back to the command sequence mode since that is compatible with default EDK2 behavior. Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org> Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-07-06mmc: synquacer: Add SynQuacer F_SDH30 SDHCI driverJassi Brar
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org> Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-07-06pci: synquacer: Add SynQuacer ECAM based PCIe driverMasami Hiramatsu
Add ECAM based SynQuacer PCIe RC driver. This driver configures the PCIe RC and filter out a ghost pcie config. Since the Linux kernel expects "socionext,synquacer-pcie-ecam" device is configured by firmware (EDK2), it doesn't re-configure in the kernel. So as same as EDK2, U-Boot needs to configure it before boot the kernel. Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-07-06gpio: Introduce CONFIG_GPIO_EXTRA_HEADER to cleanup #ifdefsMasami Hiramatsu
Since some SoCs and boards do not hae extra asm/arch/gpio.h, introduce CONFIG_GPIO_EXTRA_HEADER instead of adding !define(CONFIG_ARCH_XXXX) in asm/gpio.h. Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-07-06dm: pci: Skip setting VGA bridge bits if parent device is the host busMasami Hiramatsu
Commit bbbcb5262839 ("dm: pci: Enable VGA address forwarding on bridges") sets the VGA bridge bits by checking pplat->class, but if the parent device is the pci host bus device, it can be skipped. Moreover, it shouldn't access the pplat because the parent has different plat data. Without this fix, "pci enum" command cause a synchronous abort. pci_auto_config_devices: start PCI Autoconfig: Bus Memory region: [78000000-7fffffff], Physical Memory [78000000-7fffffffx] PCI Autoconfig: Bus I/O region: [0-ffff], Physical Memory [77f00000-77f0ffffx] pci_auto_config_devices: device pci_6:0.0 PCI Autoconfig: BAR 0, Mem, size=0x1000000, address=0x78000000 bus_lower=0x79000000 PCI Autoconfig: BAR 1, Mem, size=0x8000000, No room in resource, avail start=79000000 / size=8000000, need=8000000 PCI: Failed autoconfig bar 14 PCI Autoconfig: BAR 2, I/O, size=0x4, address=0x1000 bus_lower=0x1004 PCI Autoconfig: BAR 3, Mem, size=0x2000000, address=0x7a000000 bus_lower=0x7c000000 PCI Autoconfig: BAR 4, I/O, size=0x80, address=0x1080 bus_lower=0x1100 PCI Autoconfig: ROM, size=0x80000, address=0x7c000000 bus_lower=0x7c080000 "Synchronous Abort" handler, esr 0x96000006 elr: 00000000e002bd28 lr : 00000000e002bce8 (reloc) elr: 00000000fff6fd28 lr : 00000000fff6fce8 x0 : 0000000000001041 x1 : 000000000000003e x2 : 00000000ffb0f8c8 x3 : 0000000000000001 x4 : 0000000000000080 x5 : 0000000000000000 x6 : 00000000fff718fc x7 : 000000000000000f x8 : 00000000ffb0f238 x9 : 0000000000000008 x10: 0000000000000000 x11: 0000000000000010 x12: 0000000000000006 x13: 000000000001869f x14: 00000000ffb0fcd0 x15: 0000000000000020 x16: 00000000fff71cc4 x17: 0000000000000000 x18: 00000000ffb13d90 x19: 00000000ffb14320 x20: 0000000000000000 x21: 00000000ffb14090 x22: 00000000ffb0f8c8 x23: 0000000000000001 x24: 00000000ffb14c10 x25: 0000000000000000 x26: 0000000000000000 x27: 0000000000000000 x28: 00000000ffb14c70 x29: 00000000ffb0f830 Code: 52800843 52800061 52800e00 97ffcf65 (b9400280) Resetting CPU ... Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-07-06ata: ahci-pci: Use scsi_ops to initialize opsMasami Hiramatsu
Without this fix, scsi-scan will cause a synchronous abort when accessing ops->scan. Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-07-06arm: iproc: Add higher speed configurationsChris Packham
Add support for 1.3GHz, 1.35GHz and 1.4GHz parts. This is based on equivalent code in Broadcom's LDK 5.0.6. Signed-off-by: Chris Packham <judge.packham@gmail.com>
2021-07-06ARM: integrator: Drop PCI supportLinus Walleij
We didn't convert the Integrator to use DM for PCI in time, and we don't use it either so let's just drop PCI support from the Integrator. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2021-07-06mpc8379erdb: enable DM_USB DM_PCI DM_ETHSinan Akman
Signed-off-by: Sinan Akman <sinan@writeme.com>
2021-07-06Merge https://source.denx.de/u-boot/custodians/u-boot-riscvTom Rini
2021-07-06Merge branch 'network_master' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-net
2021-07-06board: sifive: support spl multi-dtb on unmatched boardZong Li
There are two revisions of unmatched board with different DDR timing, we'd like to support multi-dtb mechanism in SPL, then it selects the right DTB at runtime according to PCB revision in I2C EEPROM. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-07-06riscv: dts: add dts for unmatched rev1Zong Li
The difference between unmatched rev3 and rev1 is DDR timing, the rev3 uses 1866 MT/s for 16GiB, and rev1 uses 2133 MT/s for 8GiB. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-07-06board: sifive: Add an interface to get PCB revisionZong Li
There are different DDR parameter settings for different board revisions. Add a new interface to get the PCB revision to determine which DT should be selected at runtime. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-07-06riscv: sifive: fu740: Support i2c in splZong Li
Enable SPL_I2C_SUPPORT for fu740, and add 'u-boot,dm-spl' property in i2c node. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-07-06riscv: sifive: fu740: kconfig: Enable support for Opencores I2C controllerZong Li
Enable the Opencores I2C controller on FU740 Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-07-06board: sifive: unmatched: add initial support for a platform ID EEPROMZong Li
Add initial support for the PCB description EEPROM for SiFive HiFive Unmatched boards. This implementation is refactored based on Paul Walmsley's porting and adopt the suggestions from David Abdurachmanov. Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com> Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-07-06mmc: openpiton: add piton_mmc driverTianrui Wei
This commit adds support to piton_mmc driver for OpenPiton-riscv64 This driver has many things set as preconfigured because the hardware automatically configures most of the settings during startup. Signed-off-by: Tianrui Wei <tianrui-wei@outlook.com> Signed-off-by: Jonathan Balkind <jbalkind@ucsb.edu> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-07-06board: riscv: add openpiton-riscv64 SoC supportTianrui Wei
This patch adds openpiton-riscv64 SOC support. In particular, this board supports a standard bootflow through zsbl->u-boot SPL-> opensbi->u-boot proper->Linux. There are separate defconfigs for building u-boot SPL and u-boot proper Signed-off-by: Tianrui Wei <tianrui-wei@outlook.com> Signed-off-by: Jonathan Balkind <jbalkind@ucsb.edu> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-07-06riscv: sifive: Set default fdtfile namesDimitri John Ledkov
Set default fdtfile names for unleashed and unmatched boards, as used in the upstream Linux kernel. This allows sysboot command to find and load appropriate dtb for the matching kernel from universal stock Ubuntu RISC-V rootfs images based on fdtdir setting in extlinux.conf. Signed-off-by: Dimitri John Ledkov <dimitri.ledkov@canonical.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> cc: Paul Walmsley <paul.walmsley@sifive.com> cc: Palmer Dabbelt <palmer@dabbelt.com> cc: Anup Patel <anup.patel@wdc.com> cc: Atish Patra <atish.patra@wdc.com> cc: Pragnesh Patel <pragnesh.patel@sifive.com> cc: Green Wan <green.wan@sifive.com>
2021-07-06drivers: clk: sifive: fu740-prci: replace 'pciaux' with 'pcieaux'Green Wan
Replace 'pciaux' with 'pcieaux', including name string and function prefix. The old name string, 'pciaux', might cause an error if PCIe driver is changed to use clk_get_by_name() with 'pcieaux' to get clock. Signed-off-by: Green Wan <green.wan@sifive.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-07-06net: dwc_eth_qos: cosmetic: remove unused define EQOS_DESCRIPTOR_ALIGNPatrick Delaunay
Remove the define EQOS_DESCRIPTOR_ALIGN unused since the commit 6f1e668d964e ("net: dwc_eth_qos: Pad descriptors to cacheline size") Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-07-06board: sl28: add DSA support for variant 2Michael Walle
Now that u-boot gained DSA support, and it is already enabled for the kontron_sl28 board, add the last missing piece and enable the corresponding devices it in the device tree. Signed-off-by: Michael Walle <michael@walle.cc>
2021-07-06net: enetc: propagate the return code from phy_startup() to eth_ops::startVladimir Oltean
Make sure that errors in the PHY driver .startup() method, such as no link, are propagated and not ignored. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-07-06net: enetc: force the RGMII MAC speed/duplex instead of using in-band signalingVladimir Oltean
The RGMII spec supports optional in-band status reporting for the speed and duplex negotiated on the copper side, and the ENETC driver enables this feature by default. However, this does not work when the PHY does not implement the in-band reporting, or when there is a MAC-to-MAC connection described using a fixed-link. In that case, it would be better to disable the feature in the ENETC MAC and always force the speed and duplex to the values that were negotiated and retrieved over MDIO once the autoneg is finished. Since this works always, we just do it unconditionally and drop the in-band code. Note that because we need to wait for the autoneg to complete, we need to move enetc_setup_mac_iface() after phy_startup() returns, and then pass the phydev pointer all the way to enetc_init_rgmii(). The same considerations have led to a similar Linux driver patch as well: https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git/commit/?id=c76a97218dcbb2cb7cec1404ace43ef96c87d874 Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-07-06net: enetc: require a PHY device when probingVladimir Oltean
Given that even a fixed-link has an associated phy_device, there is no reason to operate in a mode when dm_eth_phy_connect fails. Remove the driver checks for a NULL priv->phy and just return -ENODEV when that happens. Copyright updated according to corporate requirements. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-07-06arm: dts: ls1028a: disable enetc-2 by defaultVladimir Oltean
The enetc-2 port is used as DSA master (connected back-to-back to mscc_felix_port4). Since the convention is to not enable ports in the common SoC dtsi unless they are used on the board, then enable enetc-2 only when mscc_felix_port4 itself is enabled. All existing device trees appear to adhere to this rule, so disable enetc-2 in the SoC dtsi. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-07-06arm: dts: ls1028a: declare the fixed-link speeds for the internal ENETC portsVladimir Oltean
To comply with the device tree bindings expectations for an Ethernet controller, as well as to simplify the driver code, declare fixed-link nodes for the internal ENETC ports (attached to the mscc_felix switch). Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-07-06arm: dts: ls1028a: enable internal RGMII delays for the LS1028A-QDS AR8035 PHYVladimir Oltean
There are no PCB trace delays on this board, so the PHY needs to enable its internal ones in order to have a proper electrical connection to the enetc MAC. Fixes: b32e9a757837 ("arm: dts: ls1028a updates for network interfaces") Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-07-06arm: dts: ls1028a: enable the switch CPU port for the LS1028A-QDSVladimir Oltean
Due to an upstream change, the ls1028a.dtsi bindings for the mscc_felix switch got accepted with all ports disabled by default and with no link to the DSA master - this needs to be done on a per board basis. Note that enetc-2 is not currently disabled in the ls1028a.dtsi, but presumably at some point it might become. Explicitly enable it in the QDS device trees anyway, to proactively avoid issues when that happens. Fixes: a7fdac7e2a2a ("arm: dts: ls1028a: define QDS networking protocol combinations") Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-07-06net: smc911x: Determine bus width at runtimeAndre Przywara
The SMC911x Ethernet MACs can be integrated using a 16 or 32-bit bus. The driver needs to know about this choice, which is the reason for us having a Kconfig symbol for that. Now this bus width is already described using a devicetree property, and since the driver is DM compliant and is using the DT now, we should query this at runtime. We leave the Kconfig choice around, in case the DT is missing this property. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-07-06net: smc911x: Drop redundant CONFIG_SMC911X_16_BIT Kconfig symbolAndre Przywara
The SMC911x Ethernet driver needs to know which accessor functions it can use to access the MMIO registers. For that reason we have a Kconfig choice between 16 and 32-bit bus width. Since it's only those two options that we (and the Linux kernel) support, and there does not seem to be any evidence of another bus width anywhere, limit the Kconfig construct to a simple symbol. This simplifies the code and allows a later rework to be much easier. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-07 05:19:54 +0000