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2021-05-14Merge https://source.denx.de/u-boot/custodians/u-boot-riscvTom Rini
2021-05-14Revert "riscv: cpu: fu740: clear feature disable CSR"Bin Meng
This reverts commit bc8bbb77f74f21582b3bfd790334397757f88575. This commit breaks U-Boot booting on SiFive Unleashed board, as there is no such CSR on U54 core. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-05-14pwm: sifive: make set_config() and set_enable() work properlyVincent Chen
The pwm_sifive_set_config() and pwm_sifive_set_enable() cannot work properly due to the wrong implementations. It will cause the u-boot PWM command to not work as expected. The bugs will be resolved in this patch. Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
2021-05-14riscv: Don't reserve AI ram in k210 dtsSean Anderson
It is no longer necessary to disallow ai ram, since it is enabled by the sram driver. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2021-05-14riscv: k210: Use AI as the parent clock of aisram, not PLL1Sean Anderson
Testing showed that disabling AI while leaving PLL1 enabled disabled the aisram. This suggests that AI is a more appropriate clock for that ram bank. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2021-05-14riscv: k210: Rename airam to aisramSean Anderson
This is more consistent with the naming of other ram banks, and matches what Linux is doing. Reported-by: Damien Le Moal <Damien.LeMoal@wdc.com> Signed-off-by: Sean Anderson <seanga2@gmail.com>
2021-05-14riscv: Enable AI ram on K210Sean Anderson
We just need to initialize all the clocks pre-reloc. The clock driver creates a bunch of devices, so we need to increase the pre-reloc malloc arena. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2021-05-14riscv: Enable some devices pre-relocationSean Anderson
These devices are necessary for the clock driver, which is required by the sram driver, to run pre-relocation. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2021-05-14clk: Add support for the k210 clock driver pre-relocationSean Anderson
Variables which had previously been stored in .bss are moved to .data. In addition, probed needs to be reset when the clock driver is re-bound post-relocation. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2021-05-14clk: k210: Move the clint clock to under aclkSean Anderson
No other (real) clocks have the cpu clock as their parent; instead they are children of aclk. Move the clint clock under aclk to match them. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2021-05-14clk: k210: Remove k210_register_pllSean Anderson
This simplifies the PLL creation process, since we don't have to pass all the parameters individually. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2021-05-14clk: k210: Fix PLL enable always getting takenSean Anderson
This conditional always evaluated as false, regardless of the value of reg. Fix it so that it properly tests the bits in the PLL register. Also test PLL_EN, now that we set it. Reported-by: Damien Le Moal <Damien.LeMoal@wdc.com> Signed-off-by: Sean Anderson <seanga2@gmail.com>
2021-05-14clk: k210: Fix PLLs not being enabledSean Anderson
After starting or setting the rate of a PLL, the enable bit must be set. This fixes a bug where the AI ram would not be accessible, because it requires PLL1 to be running. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Damien Le Moal <damien.lemoal@wdc.com>
2021-05-14clk: Warn on failure to assign rateSean Anderson
If the user/dev explicitly requests a clock be assigned a certain rate, then we should warn them if we can't do it. This makes it clear if the clock is running at the default rate. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2021-05-14MAINTAINERS: Add a co-maintainer for RISC-VRick Chen
Add Leo as co-maintainer for RISC-V. Signed-off-by: Rick Chen <rick@andestech.com>
2021-05-13Merge branch '2021-05-13-extension-board-detection-and-DT-overlay-application'Tom Rini
- Improve support for various forms of extension boards and add DT overlay application support.
2021-05-13am335x: add support for cape detect functionalityKory Maincent
Update the Kconfig and the board file to make the am335x board compatible with cape detection. Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
2021-05-13arm: am335x: add support for i2c2 busKory Maincent
The am335x from BeagleBone use i2c EEPROM to detect capes. The memory is wired to i2c bus 2 therefore it need to be enabled. Add i2c2 clock, pinmux description and pinmux enable function. Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
2021-05-13configs: CHIP: add support for DIP detect functionalityKory Maincent
This commit enables using the extension board detection mechanism on CHIP boards Signed-off-by: Kory Maincent <kory.maincent@bootlin.com> Acked-by: Maxime Ripard <maxime@cerno.tech> Acked-by: Andre Przywara <andre.przywara@arm.com>
2021-05-13arm: sunxi: add support for DIP detection to CHIP boardKory Maincent
Add the extension_board_scan specific function to scan the information of the EEPROM on one-wire and fill the extension struct. Add the Kconfig symbol to enable the needs to detect DIPs. Signed-off-by: Kory Maincent <kory.maincent@bootlin.com> Reviewed-by: Maxime Ripard <maxime@cerno.tech> Acked-by: Andre Przywara <andre.przywara@arm.com>
2021-05-13w1: replace dt detection by automatic detectionKory Maincent
This patch changes the functioning of the detection of w1 devices. The old way was a comparison between detected w1 and the ones described in the device tree. Now it will just look for the driver matching the family id of the w1 detected. The patch is inspired from Maxime Ripard code. Signed-off-by: Kory Maincent <kory.maincent@bootlin.com> Reviewed-by: Maxime Ripard <maxime@cerno.tech>
2021-05-13am57xx: add support for cape detect functionalityKory Maincent
This commit enables using the extension board detection mechanism on AM57xx based platforms. Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
2021-05-13ti/common: add support for extension_scan_board functionKory Maincent
The BeagleBone platforms all use a common mechanism to discover and identify extension boards (called "capes"): each extension board has an I2C-connected EEPROM describing itself. This patch implements a generic extension_scan_board() feature that can be used by all BeagleBone platforms to read those I2C EEPROMs and fill in the list of "extension" structures. Following commits will enable this common logic on two BeagleBone platforms. Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
2021-05-13pytest: add sandbox test for "extension" commandKory Maincent
This commit extends the sandbox to implement a dummy extension_board_scan() function and enables the extension command in the sandbox configuration. It then adds a test that checks the proper functionality of the extension command by applying two Device Tree overlays to the sandbox Device Tree. Signed-off-by: Kory Maincent <kory.maincent@bootlin.com> [trini: Limit to running on sandbox] Signed-off-by: Tom Rini <trini@konsulko.com>
2021-05-13cmd: add support for a new "extension" commandKory Maincent
This patch adds a new "extension" command, which aims at detecting extension boards connected to the hardware platform, and apply the Device Tree overlays that describe the hardware present on those extension boards. In order to enable this mechanism, board-specific code must implement the extension_board_scan() function that fills in a linked list of "struct extension", each describing one extension board. In addition, the board-specific code must select the SUPPORT_EXTENSION_SCAN Kconfig boolean. Based on this: - "extension scan" makes the generic code call the board-specific extension_board_scan() function to retrieve the list of detected extension boards. - "extension list" allows to list the detected extension boards. - "extension apply <number>|all" allows to apply the Device Tree overlay(s) corresponding to one, or all, extension boards The latter requires two environment variables to exist and set one variable to run: - extension_overlay_addr: the RAM address where to load the Device Tree overlays - extension_overlay_cmd: the U-Boot command to load one overlay. Indeed, the location and mechanism to load DT overlays is very setup specific. - extension_overlay_name: set by the command: the name of the DT which will be load during the execution. When calling the command described in the extension_overlay_cmd variable, the variable extension_overlay_name will be defined. So a typical extension_overlay_cmd will look like this: extension_overlay_cmd=load mmc 0:1 $extension_overlay_addr /boot/$extension_overlay_name Here is an example on how to use it: => run loadfdt => fdt addr $fdtaddr => setenv extension_overlay_addr 0x1000 => setenv extension_overlay_cmd 'load mmc 0:1 ${extension_overlay_addr} /boot/${extension_overlay_name}' => extension scan Found 1 extension board(s). => extension apply 0 519 bytes read in 3 ms (168.9 KiB/s) Signed-off-by: Kory Maincent <kory.maincent@bootlin.com> Reviewed-by: Maxime Ripard <maxime@cerno.tech>
2021-05-13fdt_support: move fdt_valid from cmd_fdt.c to fdt_support.cKory Maincent
Move the fdt_valid function to fdt_support. This changes allow to be able to test the validity of a devicetree in other c files. Update code syntax. Signed-off-by: Kory Maincent <kory.maincent@bootlin.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Maxime Ripard <maxime@cerno.tech>
2021-05-12Merge tag 'ti-v2021.07-rc3' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-ti - Initial support for AM64 EVM and SK - K3 DDR driver unification for J7 and AM64 platforms. - Minor fixes for TI clock driver
2021-05-12ARM: dts: k3-am642-sk: Add ethernet related DT nodesVignesh Raghavendra
Add CPSW related nodes for AM642 SK. There are two CPSW ports on the board but U-Boot supports only the first port. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-12ARM: dts: k3-am64-main: Add CPSW DT nodesVignesh Raghavendra
AM64 as CPSW3G IP with 2 external ports. Add DT entries for the same (based on kernel DT). Disable second port as its by default set to ICSS usage on EVM. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-12net: ti: am65-cpsw-nuss: Add a new compatible for AM64Vignesh Raghavendra
Add a new compatible to support AM64 SoC Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-12net: ti: am65-cpsw-nuss: Don't cache disabled port IDVignesh Raghavendra
Currently driver may end up caching disabled port ID as active interface. Fix this by bailing out earlier in case port is marked disabled in the DT. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-12net: ti: am65-cpsw-nuss: Prepare to support non primary ext portVignesh Raghavendra
CPSW NUSS IP on K3 SoCs can have more than one external port (upto 8) Therefore increase AM65_CPSW_CPSWNU_MAX_PORTS to 9 (8 ext + 1 Root port) as preparation to allow any one of the 8 ports to be used as ethernet interface in U-Boot. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-12dma: ti: k3-udma: Add BCDMA and PKTDMA supportVignesh Raghavendra
Sync BCDMA and PKTDMA support from Kernel for AM64 SoC Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-12dma: ti: k3-psil-am64: Add AM64 PSIL endpoint dataVignesh Raghavendra
Add AM64 SoC specific channel mapping and endpoint data. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-12dma: ti: k3-psil: Extend PSIL EP data extension for AM64Vignesh Raghavendra
Extend PSIL EP data to include AM64 DMA specific information Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-12dma: ti: k3-psil-am654: Drop unused PSIL EP static dataVignesh Raghavendra
ICSSG Ethernet driver uses two src threads per port (one per slice). Similarly CPSW uses one src thread. Drop PSIL EP static data for other src threads in order to reduce R5 SPL footprint. This makes AM65x board bootable again. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-12soc: ti: k3-navss-ringacc: Remove unused ring modesVignesh Raghavendra
With AM64x supporting only K3_NAV_RINGACC_RING_MODE_RING or the exposed ring mode, all other K3 SoCs have also been moved to this common baseline. Therefore drop other modes such as K3_NAV_RINGACC_RING_MODE_MESSAGE (and proxy) to save on SPL footprint. There is a saving of ~800 bytes with this change for am65x_evm_r5_defconfig. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
2021-05-12soc: ti: k3-navss-ringacc: Add AM64 ringacc supportVignesh Raghavendra
AM64 dual mode rings are modeled as pair of Rings objects which has common configuration and memory buffer, but separate real-time control register sets for each direction mem2dev (forward) and dev2mem (reverse). AM64 rings must be requested only using k3_ringacc_request_rings_pair(), and forward ring must always be initialized/configured. After this any other Ringacc APIs can be used without any callers changes. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-12firmware: ti_sci: Update ti_sci_cmd_rm_udmap_tx_ch_cfg() API to the latestVignesh Raghavendra
Update struct ti_sci_msg_rm_udmap_tx_ch_cfg_req to latest ABI to support AM64x BCDMA Block copy channels. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-12board: ti: am64x: Parse MAC address from board EEPROMVignesh Raghavendra
Parse MAC addresses from EEPROM and set them in the env. This is needed to get MAC address for additional ethernet ports on the EVM. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-12configs: am64x_evm_a53: Enable support for building multiple dtbsLokesh Vutla
Enable all relevant configs for building multiple dtbs into a single fit image and load the right dtb for next stage. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-05-12configs: am64x_evm_a53: Enable support for reading eepromLokesh Vutla
Enable relevant configs for reading eeprom data and updating env variables. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-05-12configs: am64x_evm_a53: Enable configs for printing cpuinfoLokesh Vutla
Enable all relevant configs for printing CPU info. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-05-12configs: am64x_evm_r5: Enable support for building multiple device treesLokesh Vutla
Enable defconfigs for building multiple device trees into a single FIT image. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-05-12configs: am64x_evm_r5: Enable checks for spl and stack sizesLokesh Vutla
Enable relevant configs that checks for the size of image and stack: BSS: 4KB Initial MALLOC: 512KB Initial Stack: 8K SPL Image size can be: ~960KB Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-05-12arm: dts: am642-r5-sk: Add r5 specific dtsLokesh Vutla
Add R5 specific dts for AM64 SK Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
2021-05-12arm: dts: am642-sk: Add initial sk dtsLokesh Vutla
AM642 StarterKit (SK) board is a low cost, small form factor board designed for TI’s AM642 SoC. It supports the following interfaces: * 2 GB LPDDR4 RAM * x2 Gigabit Ethernet interfaces capable of working in switch and MAC mode * x1 USB 3.0 Type-A port * x1 UHS-1 capable µSD card slot * 2.4/5 GHz WLAN + Bluetooth 4.2 through WL1837 * 512 Mbit OSPI flash * x2 UART through UART-USB bridge * XDS110 for onboard JTAG debug using USB * Temperature sensors, user push buttons and LEDs * 40-pin Raspberry Pi compatible GPIO header * 24-pin header for peripherals in MCU island (I2C, UART, SPI, IO) * 54-pin header for Programmable Realtime Unit (PRU) IO pins * Interface for remote automation. Includes: * power measurement and reset control * boot mode change Add basic support for AM642 SK. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-05-12arm: dts: am642-evm: Add I2C nodesLokesh Vutla
Add I2C nodes for AM64 and enable pinmux for i2c0 for reading eeprom data. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-05-12arm: dts: k3-am642-r5-evm: Do not use power-domains for I2CLokesh Vutla
I2C EEPROM will be probed before SYSFW is available. So drop the power-domains property for I2C. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-05-12arm: dts: k3-am64-evm: Make chip id available before pre-relocLokesh Vutla
Chipid will be needed for SoC detection for all stages of U-Boot. So make it u-boot,dm-spl Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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