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2020-10-21Merge tag 'efi-2021-01-rc1-2' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-efi Pull request for UEFI sub-system for efi-2021-01-rc1 (2) A use after free in the UEFI network stack is fixed.
2020-10-21Revert "Fix data abort caused by mis-aligning FIT data"Marek Vasut
This reverts commit eb39d8ba5f0d1468b01b89a2a464d18612d3ea76. The commit breaks booting of fitImage by SPL, the system simply hangs. This is because on arm32, the fitImage and all of its content can be aligned to 4 bytes and U-Boot expects just that. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Reuben Dowle <reuben.dowle@4rf.com> Cc: Tom Rini <trini@konsulko.com> Signed-off-by: Marek Vasut <marex@denx.de>
2020-10-20Merge https://gitlab.denx.de/u-boot/custodians/u-boot-shTom Rini
- Assorted R-Car Gen3 updates
2020-10-20Merge https://gitlab.denx.de/u-boot/custodians/u-boot-usbTom Rini
- MediaTek USB host support
2020-10-20pinctrl: renesas: pfc-r8a77990: Sync PFC tables with Linux 5.9Lad Prabhakar
Sync the R8A77990 SoC PFC tables with Linux 5.9 , commit bbf5c979011a. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
2020-10-20clk: renesas: Import R8A774C0 clock tables from Linux 5.9Lad Prabhakar
Import RZ/G2E (R8A774C0) clock tables from Linux 5.9 commit bbf5c979011a ("Linux 5.9"). Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
2020-10-20clk: renesas: Add R8A774E1 clock tablesBiju Das
This sync's the RZ/G2H clock tables with mainline linux 5.9 commit bbf5c979011a ("Linux 5.9"). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-10-20clk: renesas: Add R8A774B1 clock tablesBiju Das
This sync's the RZ/G2N clock tables with mainline linux 5.9 commit bbf5c979011a ("Linux 5.9"). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-10-20arm: dts: r8a774c0: Import DTS from Linux 5.9Lad Prabhakar
Import R8A774C0 (RZ/G2E) SoC DTSI and headers from Linux 5.9 commit bbf5c979011a ("Linux 5.9"). Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
2020-10-20arm: renesas: Add config option for R8A774C0 SoCLad Prabhakar
Add config support for RZ/G2E (a.k.a R8A774C0) SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
2020-10-20arm: renesas: Add config option for R8A774E1 SoCBiju Das
Add config support for RZ/G2H(a.k.a R8A774E1) SoC. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-10-20arm: renesas: Add config option for R8A774B1 SoCBiju Das
Add config support for RZ/G2N(a.k.a R8A774B1) SoC. Also fixed the alignment issue on R8A774A1 config. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-10-20clk: renesas: r8a774a1-cpg-mssr: Add R8A774A1 RPC clockBiju Das
Add RPC entry into the R8A774A1 clock driver tables. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-10-20spi: renesas_rpc_spi: Add R-Car Gen3 and RZ/G2 fallback compatibility stringBiju Das
Add fallback compatibility string for R-Car Gen3 and RZ/G2. Also sorted the compatible string as per SoC ID. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
2020-10-20MAINTAINERS: add USB driver to ARM MEDIATEKChunfeng Yun
Add MediaTek USB3 Dual-Role controller driver to ARM MEDIATEK, and add myself as a maintainer for it. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-10-20configs: mt8512: enable fastboot and USB host related configsChunfeng Yun
Enable mtu3, xhci, tphy drivers. Device mode: enable fastboot; Host mode: enable USB, FAT commands, and fixed regulator, mass storage drivers; Due to device mode is enabled by default, comment out the host mode config here. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-10-20arm: dts: mt8512: add usb related nodesChunfeng Yun
Add usb, usb phy, and fixed regulators nodes Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Acked-by: Bin Meng <bmeng.cn@gmail.com>
2020-10-20usb: gadget: Add bcdDevice for the MTU3 USB Gadget ControllerChunfeng Yun
Add an entry in usb_gadget_controller_number() for the MTU3 gadget controller. It is used to bind the USB Ethernet driver. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-10-20usb: add MediaTek USB3 DRD driverChunfeng Yun
This patch adds support for the MediaTek USB3 DRD controller, its host side is based on xHCI, this driver supports device mode and host mode. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Acked-by: Bin Meng <bmeng.cn@gmail.com>
2020-10-20usb: common: add define of usb_speed_string()Chunfeng Yun
There is only declaration of usb_speed_string(), but no definition, so add it to avoid build error when call it. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-10-20usb: add USB_SPEED_SUPER_PLUSChunfeng Yun
Add enum USB_SPEED_SUPER_PLUS for USB3.1 Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-10-20dt-bindings: usb: mtu3: add bindings for MediaTek USB3 DRDChunfeng Yun
Add dt-binding for MediaTek USB3 DRD Driver which it's ported from the Linux kernel DTS binding: Documentation/devicetree/bindings/usb/mediatek,mtu3.txt Commit ID: 34d0545978b6 ("dt-bindings: usb: mtu3: fix typo of DMA clock name") Due to Dual-Role switch is not supported in Uboot, some properties are removed or changed. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-10-20dt-binding: usb: add bindings for some common propertiesChunfeng Yun
Add bindings for common properties, include maximum-speed, dr_mode and phy_type Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-10-20usb: musb-new: Fix typo in caution messageNaoki Hayama
%s/Occured/Occurred/ Signed-off-by: Naoki Hayama <naoki.hayama@lineo.co.jp>
2020-10-20usb: dwc2: Fix control OUT transfer issueChance.Yang
In buffer DMA mode, gadget should re-configure EP 0 to received SETUP packets when doeptsiz.xfersize is equal to a setup packet size(8 bytes) and EP 0 is in WAIT_FOR_SETUP state. Since EP 0 is not enabled in WAIT_FOR_SETUP state, SETUP packets is NOT received from RxFifo and wriiten to the external memory. Signed-off-by: Chance.Yang <chance.yang@vatics.com>
2020-10-20usb: xhci: avoid type conversion of void *Heinrich Schuchardt
void * can be assigned to any pointer variable. Avoid unnecessary conversions. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-10-19efi_loader: fix use after free in receive pathPatrick Wildt
With DM enabled the ethernet code will receive a packet, call the push method that's set by the EFI network implementation and then free the packet. Unfortunately the push methods only sets a flag that the packet needs to be handled, but the code that provides the packet to an EFI application runs after the packet has already been freed. To rectify this issue, adjust the push method to accept the packet and store it in a temporary buffer. The EFI application then gets the data copied from that buffer. This way the packet is cached until is is needed. The DM Ethernet stack tries to receive 32 packets at once, thus we better allocate as many buffers as the stack. Signed-off-by: Patrick Wildt <patrick@blueri.se> Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-10-19net: add a define for the number of packets received as batchPatrick Wildt
With a define for the magic number of packets received as batch we can make sure that the EFI network stack caches the same amount of packets. Signed-off-by: Patrick Wildt <patrick@blueri.se> Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-10-19Merge tag 'u-boot-atmel-2021.01-b' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-atmel Second set of u-boot-atmel features for 2021.01 cycle: This feature set brings the rework of the clock tree for sam9x60 SoC. This makes the clock tree fully compatible with Common Clock Framework and allows full clock configuration in U-Boot. This means that the sam9x60 boards can boot now using U-Boot. This also includes the definitions for sam9x60 SiPs and a divisor fix for the clock on sama7g5 SoC.
2020-10-19clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristicsEugen Hristev
This SoC has the 5th divisor for the mck0 master clock. Adapt the characteristics accordingly. Reported-by: Mihai Sain <mihai.sain@microchip.com> Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-19clk: at91: clk-master: add 5th divisor for mck masterEugen Hristev
clk-master can have 5 divisors with a field width of 3 bits on some products. Change the mask and number of divisors accordingly. Reported-by: Mihai Sain <mihai.sain@microchip.com> Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-19ARM: at91: Add chip ID for SAM9X60 SiPNicolas Ferre
SAM9X60 SiP (System in Package) are added for SoC identification. Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
2020-10-19ARM: dts: sam9x60: use alphabetical orderClaudiu Beznea
Use alphabetical order for entries in sam9x60ek-u-boot.dtsi Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-19configs: sam9x60ek: update defconfigs for CCFClaudiu Beznea
Update defconfigs for using common clock framework compatible clocks. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-19ARM: dts: sam9x60: use CCF compatibles for PMCClaudiu Beznea
Use CCF compatible for PMC. With this, the board/SoC will be able to boot. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-19ARM: dts: sam9x60: use slow clock CCF compatible bindingsClaudiu Beznea
Use slow clock CCF compatible DT bindings. This will not break the above functionality as the SoC is not booting with current PMC bindings. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-19ARM: dts: sam9x60: use u-boot,dm-pre-relocClaudiu Beznea
Use u-boot,dm-pre-reloc for slow xtal and main xtal. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-19ARM: dts: sam9x60ek: add clock frequencies to board fileClaudiu Beznea
Slow Xtal and Main Xtal are board specific. Add their proper frequency to board file. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-19clk: at91: sam9x60: add support compatible with CCFClaudiu Beznea
Add SAM9X60 clock support compatible with CCF. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-19board: atmel: sam9x60ek: add SYS_MALLOC_F_LEN to SYS_INIT_SP_ADDRClaudiu Beznea
Heap base address is computed based on SYS_INIT_SP_ADDR by subtracting the SYS_MALLOC_F_LEN value in board_init_f_init_reserve(). Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-18Merge tag 'video-for-2021.01' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-video - add dw-mipi-dsi phy timings and Tx escape clock configuration - fix pwm backlight duty cycle calculation - migrate CONFIG_VIDEO_BMP_* and CONFIG_BMP_* to Kconfig
2020-10-18configs: migrate CONFIG_BMP_16/24/32BPP to defconfigsPatrick Delaunay
Done with: ./tools/moveconfig.py BMP_16BPP BMP_24BPP BMP_32BPP Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-18configs: migrate CONFIG_VIDEO_BMP_RLE8 to defconfigsPatrick Delaunay
Done with: ./tools/moveconfig.py VIDEO_BMP_RLE8 Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-18configs: migrate CONFIG_VIDEO_BMP_GZIP to defconfigsPatrick Delaunay
Done with: ./tools/moveconfig.py VIDEO_BMP_GZIP The 3 suspicious migration because CMD_BMP and SPLASH_SCREEN are not activated in these defconfigs: - trats_defconfig - s5pc210_universal_defconfig - trats2_defconfig Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-18video: backlight: fix pwm's duty cycle calculationDario Binacchi
For levels equal to the maximum value, the duty cycle must be equal to the period. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-18video: backlight: fix pwm data structure descriptionDario Binacchi
The description of the 'max_level' field was incorrectly assigned to the 'min_level' field. Signed-off-by: Dario Binacchi <dariobin@libero.it>
2020-10-18video: dw-mipi-dsi: permit configuring the escape clock rateNeil Armstrong
The Amlogic D-PHY in the Amlogic AXG SoC Family does support a frequency higher than 10MHz for the TX Escape Clock, thus make the target rate configurable. This is based on the Linux commit [1] and adapted to the U-Boot driver. [1] a328ca7e4af3 ("drm/bridge: dw-mipi-dsi: permit configuring the escape clock rate") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-10-18video: dw-mipi-dsi: driver-specific configuration of phy timingsNeil Armstrong
The timing values for dw-dsi are often dependent on the used display and according to Philippe Cornu will most likely also depend on the used phy technology in the soc-specific implementation. To solve this and allow specific implementations to define them as needed add a new get_timing callback to phy_ops and call this from the dphy_timing function to retrieve the necessary values for the specific mode. This is based on the Linux commit [1] and adapted to the U-Boot driver. [1] 25ed8aeb9c39 ("drm/bridge/synopsys: dsi: driver-specific configuration of phy timings") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-10-17test: Fix sandbox tests failing to buildSean Anderson
syslog_test.h is in test/log/, not include/ Fixes: 52d3df7fef ("log: Allow LOG_DEBUG to always enable log output") Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-16Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvellTom Rini
- Fix Octeon SPI driver for Octeon TX2 - Fix and enhance Octeon watchdog driver - Misc minor enhancements to Octeon TX/TX2
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-06 12:30:15 +0000