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2023-05-18rockchip: rk3588-rock-5b: Add bootph prop to pinctrl for uart2 and sdhciJonas Karlman
Enable pinctrl for sdhci in SPL to support loading of FIT image from SD and eMMC storage when booting from SPI NOR flash. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-18rockchip: rk3588-rock-5b: Update defconfigJonas Karlman
Update defconfig for rk3588-rock-5b with new defaults. Remove the SPL_ROCKCHIP_BACK_TO_BROM=y option, SPL is expected to load next stage from a FIT image and then jump to next stage not back to BootRom. Extend SPL_MAX_SIZE to 0x40000, SPL is loaded to 0x0 and TF-A is loaded to 0x40000, use the space in between as SPL_MAX_SIZE. Add config option to include useful gpio cmd. Remove the CONFIG_NET_RANDOM_ETHADDR=y option, ethaddr and eth1addr is set based on cpuid read from OTP. Add CONFIG_SYS_NS16550_MEM32=y to use 32bit access of serial register. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-18rockchip: rk3588-evb: Update defconfigJonas Karlman
Update defconfig for rk3588-evb with new defaults. Add CONFIG_SPL_FIT_SIGNATURE=y to let SPL verify an auto generated hash of FIT images. This help indicate if there is an issue loading any of the images to DRAM or SRAM. Extend SPL_MAX_SIZE to 0x40000, SPL is loaded to 0x0 and TF-A is loaded to 0x40000, use the space in between as SPL_MAX_SIZE. Add config options to include useful gpio and regulator cmd. Remove the CONFIG_NET_RANDOM_ETHADDR=y option, ethaddr and eth1addr is set based on cpuid read from OTP. Remove CONFIG_DEBUG_UART_ANNOUNCE=y to remove debug messages. Add CONFIG_SYS_NS16550_MEM32=y to use 32bit access of serial register. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-18rockchip: rk3588: Select DM_RESET and DM_REGULATOR_FIXED in arch KconfigJonas Karlman
Like other Rockchip SoCs, DM_RESET and DM_REGULATOR_FIXED is useful across RK3588 platform. Select them from arch Kconfig. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-18rockchip: rk3568-rock-3a: Enable boot from SPI NOR flashJonas Karlman
Add sfc and flash node to device tree and config options to enable support for booting from SPI NOR flash on Radxa ROCK 3 Model A. Unlike prior generation SoCs the BootRom in RK3568 can read all data and look for idbloader at 0x8000, same as on SD and eMMC. Use the rksd format and modify the mkimage offset to generate a bootable u-boot-rockchip-spi.bin that can be written to 0x0 of SPI NOR flash. The FIT image is loaded from 0x60000. => sf probe SF: Detected mx25u12835f with page size 256 Bytes, erase size 4 KiB, total 16 MiB => load mmc 1:1 10000000 u-boot-rockchip-spi.bin 1384448 bytes read in 119 ms (11.1 MiB/s) => sf update $fileaddr 0 $filesize device 0 offset 0x0, size 0x152000 1179648 bytes written, 204800 bytes skipped in 9.901s, speed 143185 B/s Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-18rockchip: rk3568-rock-3a: Use pinctrl for sdmmc and sdhci in SPLJonas Karlman
Enable pinctrl for sdmmc and sdhci in SPL to support loading of FIT image from SD and eMMC storage when booting from SPI NOR flash. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-18rockchip: rk3568-rock-3a: Update defconfigJonas Karlman
Update defconfig for rk3568-rock-3a with new defaults. Remove the SPL_ROCKCHIP_BACK_TO_BROM=y option, SPL is expected to load next stage from a FIT image and then jump to next stage not back to BootRom. Add CONFIG_SPL_FIT_SIGNATURE=y to let SPL verify an auto generated hash of FIT images. This help indicate if there is an issue loading any of the images to DRAM or SRAM. Extend SPL_MAX_SIZE to 0x40000, SPL is loaded to 0x0 and TF-A is loaded to 0x40000, use the space in between as SPL_MAX_SIZE. Add config option to include useful gpio cmd. Remove the CONFIG_NET_RANDOM_ETHADDR=y option, ethaddr and eth1addr is set based on cpuid read from OTP. Filter out assigned-clock props with CONFIG_OF_SPL_REMOVE_PROPS, U-Boot proper will read and configure assigned-clock props. Remove the CONFIG_SPL_PMIC_RK8XX=y option, the pmic is not used in SPL. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-18rockchip: rk3568-evb: Update defconfigJonas Karlman
Update defconfig for rk3568-evb with new defaults. Remove the SPL_ROCKCHIP_BACK_TO_BROM=y option, SPL is expected to load next stage from a FIT image and then jump to next stage not back to BootRom. Add CONFIG_SPL_FIT_SIGNATURE=y to let SPL verify an auto generated hash of FIT images. This help indicate if there is an issue loading any of the images to DRAM or SRAM. Extend SPL_MAX_SIZE to 0x40000, SPL is loaded to 0x0 and TF-A is loaded to 0x40000, use the space in between as SPL_MAX_SIZE. Add config options to include useful gpio, i2c, pmic and regulator cmd. Remove the CONFIG_NET_RANDOM_ETHADDR=y option, ethaddr and eth1addr is set based on cpuid read from OTP. Filter out assigned-clock props with CONFIG_OF_SPL_REMOVE_PROPS, U-Boot proper will read and configure assigned-clock props. Add config options to enable support for the RK809 PMIC. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-18rockchip: rk3566-radxa-cm3-io: Use pinctrl for sdmmc and sdhci in SPLJonas Karlman
Enable pinctrl for sdmmc and sdhci in SPL to support loading of FIT image from SD and eMMC storage when booting from SPI NOR flash. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-18rockchip: rk3566-radxa-cm3-io: Update defconfigJonas Karlman
Update defconfig for rk3566-radxa-cm3-io with new defaults. Also add missing supported mmc modes to sdhci node. Remove the SPL_ROCKCHIP_BACK_TO_BROM=y option, SPL is expected to load next stage from a FIT image and then jump to next stage not back to BootRom. Add CONFIG_SPL_FIT_SIGNATURE=y to let SPL verify an auto generated hash of FIT images. This help indicate if there is an issue loading any of the images to DRAM or SRAM. Extend SPL_MAX_SIZE to 0x40000, SPL is loaded to 0x0 and TF-A is loaded to 0x40000, use the space in between as SPL_MAX_SIZE. Add config option to include useful gpio cmd. Remove the CONFIG_NET_RANDOM_ETHADDR=y option, ethaddr and eth1addr is set based on cpuid read from OTP. Filter out assigned-clock props with CONFIG_OF_SPL_REMOVE_PROPS, U-Boot proper will read and configure assigned-clock props. Add CONFIG_SYS_NS16550_MEM32=y to use 32bit access of serial register. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-18rockchip: rk356x-u-boot: Add xin24m clock node to SPLJonas Karlman
Add bootph-all prop to xin24m clock node, it is referenced by cru node. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-18spi: rockchip_sfc: Use linux rockchip,sfc-no-dma propJonas Karlman
Use the same prop as linux to control the use of fifo or dma mode. Also add a u-boot,spl-sfc-no-dma prop to control the same in SPL. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-18configs: rock5b-rk3588: add PCI drivers and commandEugen Hristev
Add drivers for PCIe , phy, and command. Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-18ARM: dts: rockchip: rock5b: enable pcie2x1l2 and associated combphyChristopher Obbard
Enable the PCIe 2x1l 2 device and associated combphy. On this bus, the Rock5B has an Ethernet transceiver connected. Signed-off-by: Christopher Obbard <chris.obbard@collabora.com> [eugen.hristev@collabora.com: minor tweaks] Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> [jonas@kwiboo.se: add PCIe pins] Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-18ARM: dts: rockchip: rk3588s-u-boot: add pcie2x1l2 with PHYJoseph Chen
Add the node for PCIe 2x1l 2 device together with the corresponding combphy. Signed-off-by: Joseph Chen <chenjh@rock-chips.com> [eugen.hristev@collabora.com: moved to -u-boot.dtsi, minor adaptations] Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> [jonas@kwiboo.se: adapt to kernel node] Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-18rockchip: rockpro64: Build u-boot-rockchip-spi.binJonas Karlman
Enable CONFIG_ROCKCHIP_SPI_IMAGE to build u-boot-rockchip-spi.bin. Define CONFIG_SYS_SPI_U_BOOT_OFFS to write u-boot.itb at the expected offset. Enable CONFIG_LTO to reduce size of SPL so that the mkimage output fit before the 0x60000 offset in u-boot-rockchip-spi.bin. => sf probe SF: Detected gd25q128 with page size 256 Bytes, erase size 4 KiB, total 16 MiB => load mmc 1:1 10000000 u-boot-rockchip-spi.bin 1442304 bytes read in 27 ms (50.9 MiB/s) => sf update $fileaddr 0 $filesize device 0 offset 0x0, size 0x160200 1421824 bytes written, 20480 bytes skipped in 9.501s, speed 155432 B/s Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-18rockchip: rock-pi-4: Use SDMA to boost eMMC performanceJonas Karlman
Enable the use of SDMA mode to boost eMMC performance on ROCK Pi 4. Also add missing flags to indicate the supported MMC modes. Using mmc read command to read 32 MiB data shows following improvement: => time mmc read 10000000 2000 10000 Before: time: 3.178 seconds After: time: 0.402 seconds This also enables CONFIG_SPL_FIT_SIGNATURE option to help discover any possible future issue with loading TF-A into DRAM/SRAM. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-18rockchip: rockpro64: Use SDMA to boost eMMC performanceJonas Karlman
Enable the use of SDMA mode to boost eMMC performance on RockPro64. Also add missing flags to indicate the supported MMC modes. Using mmc read command to read 32 MiB data shows following improvement: => time mmc read 10000000 2000 10000 Before: time: 3.178 seconds After: time: 0.402 seconds This also enables CONFIG_SPL_FIT_SIGNATURE option to help discover any possible future issue with loading TF-A into DRAM/SRAM. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-18mmc: rockchip_sdhci: Disable DMA mode using a device tree propertyJonas Karlman
Loading part of TF-A into SRAM from eMMC using DMA fails on RK3399 similar to other Rockchip SoCs. Checksum validation fails with: ## Checking hash(es) for Image atf-2 ... sha256 error! Bad hash value for 'hash' hash node in 'atf-2' image node spl_load_simple_fit: can't load image loadables index 1 (ret = -1) mmc_load_image_raw_sector: mmc block read error SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ### Add a device tree property, u-boot,spl-fifo-mode, to control when the rockchip_sdhci driver should disable the use of DMA and fallback on PIO mode. Same device tree property is used by the rockchip_dw_mmc driver. In commit 2cc6cde647e2 ("mmc: rockchip_sdhci: Limit number of blocks read in a single command") the DMA mode was disabled using a CONFIG option on RK3588. Revert that and instead disable DMA using the device tree property for all RK3588 boards, also apply similar workaround for all RK3399 boards. Fixes: 2cc6cde647e2 ("mmc: rockchip_sdhci: Limit number of blocks read in a single command") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Quentin Schulz <foss+uboot@0leil.net> # RK3399 Puma, RK3588 Tiger
2023-05-18mmc: rockchip_sdhci: Skip blocks read workaround on RK3399Jonas Karlman
The workaround to limit number of blocks to read in a single command should only be applied to RK3568 and RK3588. Change to be more strict when to apply the workaround. Fixes: 2cc6cde647e2 ("mmc: rockchip_sdhci: Limit number of blocks read in a single command") Suggested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Quentin Schulz <foss+uboot@0leil.net> # RK3399 Puma, RK3588 Tiger
2023-05-17phy: rockchip: naneng-combphy: Support rk3588Jon Lin
Add support for rk3588 phy variant. The PHY clock is fixed at 100MHz. Signed-off-by: Jon Lin <jon.lin@rock-chips.com> [kever.yang@rock-chips.com: update pcie pll parameters] Co-developed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> [eugen.hristev@collabora.com: squashed, tidy up] Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-17phy: rockchip: naneng-combphy: Add support for multiple resetsEugen Hristev
Some variants of the PHY have more than just one reset. To cover all cases, request the rests in bulk rather than just the reset at index 0. Co-developed-by: Ren Jianing <jianing.ren@rock-chips.com> Signed-off-by: Ren Jianing <jianing.ren@rock-chips.com> Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-17pci: pcie_dw_rockchip: Support max_link_speed dts propertyJon Lin
Add support for max_link_speed specified in the PCI DT binding. Signed-off-by: Jon Lin <jon.lin@rock-chips.com> [eugen.hristev@collabora.com: port to latest API, set default correctly, align to 80 chars] Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> [jonas@kwiboo.se: switch to dev_read_u32_default] Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-17pci: pcie_dw_rockchip: Add rk3588 compatibleJon Lin
Add compatible for RK3588 SoC. Signed-off-by: Jon Lin <jon.lin@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-17reset: rockchip: implement rk3588 lookup tableEugen Hristev
The current DT bindings for the rk3588 clock use a different ID than the one that is supposed to be written to the hardware registers. Thus, we cannot use directly the id provided in the phandle, but rather use a lookup table to correctly setup the hardware. This approach has been implemented already in Linux, by commit : f1c506d152ff ("clk: rockchip: add clock controller for the RK3588") Hence, implement a similar approach using the lookup table, and adapt the existing reset driver to work with SoCs using lookup table. The file rst-rk3588.c has been copied as much as possible from Linux. Adapt the clk rk3588 driver as well to bind the reset driver with the lookup table. Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
2023-05-17configs: rockchip: rock5b-rk3588: add pinctrl to SPLEugen Hristev
Add pinctrl driver in SPL. Do not remove pinctrl properties for SPL dtb. Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-17ARM: dts: rk3588-rock-5b-u-boot: add bootph-all to pinctrl for sdmmcEugen Hristev
To be able to initialize the pinctrl correctly at SPL level and read u-boot proper from SD-Card, the pinctrl must be initialized. Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-17phy: Keep balance of counts when ops is missingJonas Karlman
Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Fixes: 226fce6108fe ("phy: Track power-on and init counts in uclass") Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
2023-05-17phy: rockchip-inno-usb2: add initial support for rk3588 PHYEugen Hristev
Add initial support for the rk3588 PHY variant. The lookup for the host-port reg inside the struct now does a do {} while() instead of a while() {} in order to allow a first check for reg == 0. Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Co-developed-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
2023-05-17phy: remove phy-supply related codeEugen Hristev
phy-supply is now handled at uclass level. Remove it from the drivers that implement it at the driver level. Acked-by: Neil Armstrong <neil.armstrong@linaro.org> Suggested-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
2023-05-17phy: add support for phy-supplyEugen Hristev
Some phys require a phy-supply property that is a phandle to a regulator that needs to be enabled for phy operations. Implement basic supply lookup, enable and disabling, if DM_REGULATOR is available. Reviewed-by: Kever Yang <kever.yang@rock-chips.com> [jonas@kwiboo.se: use regulator_set_enable_if_allowed and disable if power_on ops fails] Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
2023-05-17configs: rockchip: rock5b-rk3588: enable USB and regulatorsEugen Hristev
Enable USB command, USB drivers, PHY and regulators, for USB host operations. Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
2023-05-17ARM: dts: rockchip: rk3588-rock-5b-u-boot: add USB 2.0 hostEugen Hristev
Add USB 2.0 host nodes and PHYs. Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Co-developed-by: William Wu <william.wu@rock-chips.com> Signed-off-by: William Wu <william.wu@rock-chips.com> Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
2023-05-16Merge tag 'efi-2023-07-rc3' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-efi Pull request efi-2023-07-rc3 Documentation: * update the description of signature algorithms UEFI: * fix unaligned access to GUID in HII database protocol * fix launching EFI binaries loaded via semihosting * fix filling of file path in loaded image protocol for non-block devices
2023-05-16Merge branch '2023-05-15-assorted-bugfixes'Tom Rini
- Merge in a long-standing fix for some exynos platforms, correct a Kconfig description, fix some env issues, fix an issue in devfdt_get_addr_size_index_ptr and look for "panel-timings" not "panel-timing" per upstream binding.
2023-05-16Merge tag 'xilinx-for-v2023.07-rc3' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2023.07-rc3 .mailmap - Fix Xilinx IDs ZynqMP: - Fix R5 split boot mode - DT fixes - sync with Linux Xilinx: - Enable virtio and RNG support - Enable ADI ethernet phy SPI/Zynq: - Fix dummy byte calculation
2023-05-15environment: ti: rproc: fix remoteproc environment variablesManorit Chawdhry
During refactor this seemed to have been missed. Fixes: 65dbb128fb45 ("include: environment: ti: Use .env for environment variables") Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-05-15core: fdtaddr: use map_sysmem() as cast for the return (part 2)Johan Jonker
For the devfdt_get_addr_size_index_ptr() function use map_sysmem() function as cast for the return for use in sandbox. Signed-off-by: Johan Jonker <jbx6244@gmail.com>
2023-05-15drivers: core: ofnode: fix typo in panel timing decodeRaphael Gallais-Pou
In case where a single timing resolution is implemented in the device-tree, the property is named "panel-timing", as specify in Linux kernel binding file: Documentation/devicetree/bindings/display/panel/panel-common.yaml # Display Timings panel-timing: description: Most display panels are restricted to a single resolution and require specific display timings. The panel-timing subnode expresses those timings. $ref: panel-timing.yaml# display-timings: description: Some display panels support several resolutions with different timings. The display-timings bindings supports specifying several timings and optionally specifying which is the native mode. $ref: display-timings.yaml# Fixes: 0347cc773270 ("drivers: core: ofnode: Add panel timing decode.") Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-05-15envtools lack extra settings since commit 86b9c3e4e4 ("env: Allow U-Boot ↵Christophe Leroy
scripts to be placed in After converting my targets from CFG_EXTRA_ENV_SETTINGS to CONFIG_EXTRA_ENV_TEXT as suggested by Tom, I discovered that fw_setenv doesn't set the entire defaut environment anymore. I tried to fix it with the below patch, but it fails qemu-x86 CI test, see https://source.denx.de/u-boot/custodians/u-boot-mpc8xx/-/pipelines/16326 That's the only CI test that fails AFAICS. Could you help with a solution ? This needs to be fixed. Thanks Christophe ---- >8 ---- From: Christophe Leroy <christophe.leroy@csgroup.eu> Subject: [RFC PATCH] envtools: Fix default environment After converting some targets from CFG_EXTRA_ENV_SETTINGS to CONFIG_EXTRA_ENV_TEXT, default environment embedded in fw_env tool missed all extra settings. Commit 86b9c3e4e4 ("env: Allow U-Boot scripts to be placed in a .env file") restricted the inclusion of the content of that file to builds without USE_HOSTCC. But as mentionned in commit 79fc0c5f49 ("tools/env: cross-compile fw_printenv without setting HOSTCC"), HOSTCC and USE_HOSTCC are kept for code re-use. Remove the restricting so that settings included in a .env file are also added to fw_env tool. Fixes: 86b9c3e4e4 ("env: Allow U-Boot scripts to be placed in a .env file") Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
2023-05-15samsung: common: do not reset if cros-ec uclass is missingHenrik Grimler
Otherwise non-ChromeOS samsung devices, like the odroid boards, are stuck in a bootloop if CONFIG_CROS_EC is not enabled: <...> MMC: SAMSUNG SDHCI: 2, EXYNOS DWMMC: 0 Loading Environment from MMC... *** Warning - bad CRC, using default environment cros-ec communications failure -96 Please reset with Power+Refresh Cannot init cros-ec device resetting ... Issue started after commit e44d7e73fe0d ("dm: core: Switch uclass_*_device_err to use uclass_*_device_check"). Signed-off-by: Henrik Grimler <henrik@grimler.se> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
2023-05-15Revert "mmc: s5p_sdhci: unset the SDHCI_QUIRK_BROKEN_R1B"Henrik Grimler
This reverts commit a034ec06ff1d558bbe11d5ee05edbb4de3ee2215. Commit 4a3ea75de4c5 ("Revert "mmc: sdhci: set to INT_DATA_END when there are data"") reverted the alternative fix that was added for Exynos 4 devices, causing an error when trying to boot from an sdcard: <...> Loading Environment from MMC... sdhci_send_command: Timeout for status update! mmc fail to send stop cmd <...> Re-add the quirk to allow booting from sdcards again. Signed-off-by: Henrik Grimler <henrik@grimler.se>
2023-05-15video: tweak CONFIG_SPL_VIDEO descriptionJohn Keeping
Make it clear that this is the SPL option to avoid potential confusion when the description for CONFIG_SPL_VIDEO is the same as that for CONFIG_VIDEO. Signed-off-by: John Keeping <john@metanate.com>
2023-05-15Merge https://source.denx.de/u-boot/custodians/u-boot-cfi-flashTom Rini
- cfi: respect reg address length (Nuno)
2023-05-15mtd: cfi: respect reg address lengthNuno Sá
flash_get_size() will get the flash size from the device itself and go through all erase regions to read protection status. However, the device mappable region (eg: devicetree reg property) might be lower than the device full size which means that the above cycle will result in a data bus exception. This change fixes it by reading the 'addr_size' during probe() and also use that as one possible upper limit. Signed-off-by: Nuno Sá <nuno.sa@analog.com>
2023-05-15.mailmap: Map all Xilinx users mail ids to AMDAlgapally Santosh Sagar
The mail ids of all the current Xilinx users are to be mapped to AMD following the merger with AMD. The mailmap file is updated accordingly. The ids of Marek Behún and Michal Simek are taken as reference. Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20230426060104.10412-3-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-05-15.mailmap: Sort the mailmap ids in dictionary orderAlgapally Santosh Sagar
The mailmap ids are not arranged in the dictionary order. So, sort the mailmap ids in the dictionary order. Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20230426060104.10412-2-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-05-15Revert "spi: zynq_qspi: Use dummy buswidth in dummy byte calculation"Stefan Herbrechtsmeier
This reverts commit e09784728689de7949d4cdd559a9590e0bfcc702. The commit wrongly divides the dummy bytes by dummy bus width to calculate the dummy bytes. The framework already converts the dummy cycles to the number of bytes and the controller use the SPI flash command to determine the dummy cycles via the address width. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Acked-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20230427065355.7413-1-stefan.herbrechtsmeier-oss@weidmueller.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-05-15arm64: versal: Enable ADIN ethernet phyAshok Reddy Soma
Versal VEK280 board has Analog Devices ethernet phy. So, enable CONFIG_PHY_ADIN config in Versal defconfig. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20230420085645.21260-3-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-05-15arm64: zynqmp: Enable ADIN ethernet phyAshok Reddy Soma
Some of the Kria SOM and ZynqMP boards are using Analog Devices ethernet phy. So, enable CONFIG_PHY_ADIN for all ZynqMP platforms. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20230420085645.21260-2-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
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