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2021-01-20efi_selftest: don't compile dtbdump if GENERATE_ACPI_TABLEHeinrich Schuchardt
If we are using ACPI tables instead of a device tree, we don't need the dtbdump.efi test tool. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-01-20efi_selftest: ask before overwriting in dtbdump.efiHeinrich Schuchardt
Before overwriting an existing file ask the user. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-01-20efi_loader: remove EFI_UNICODE_COLLATION_PROTOCOLHeinrich Schuchardt
In EFI 1.10 a version of the Unicode collation protocol using ISO 639-2 language codes existed. This protocol is not part of the UEFI specification any longer. It was however required to run the UEFI Self Certification Test (SCT) II, version 2.6, 2017. So we implemented it for the sole purpose of running the SCT. As the SCT does not need the protocol anymore it is time for removal. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-01-20efi_loader: EFI_DEVICE_PATH_UTILITIES_PROTOCOL configurableHeinrich Schuchardt
Allow the EFI_DEVICE_PATH_UTILITIES_PROTOCOL to be disabled via configuration. On systems that are very tight on U-Boot image size we may want to disable the protocol. As it is required to run the UEFI Shell enable it by default. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-01-20efi_loader: make EFI_DT_FIXUP_PROTOCOL configurableHeinrich Schuchardt
Allow EFI_DT_FIXUP_PROTOCOL to be disabled via configuration. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-01-20efi_loader: fixup protocol, avoid forward declarationHeinrich Schuchardt
Avoid a forward declaration. Add a missing function description. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-01-20efi_loader: make the UEFI boot manager configurableHeinrich Schuchardt
Some boards are very tight on the binary size. Booting via UEFI is possible without using the boot manager. Provide a configuration option to make the boot manager available. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-01-19efi_loader: move load options to new moduleHeinrich Schuchardt
Move all load options related functions to a new module. So that they can be compiled independently. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-01-19Merge branch '2021-01-18-assorted-platform-updates'Tom Rini
- Assorted MediaTek, AST2x00 updates - Assorted driver fixes for various platforms - Keymile platform updates - Add pwm command, mp5416 pmic driver
2021-01-18dts: mt7622: use accurate clock source fot mtk_timerWeijie Gao
The input system clock for mt7622 timer is 10MHz and can be retrieved through the clk driver. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2021-01-18timer: mtk_timer: initialize the timer before useWeijie Gao
The timer being used by this driver may have already been used by first stage bootloader (e.g. ATF/preloader), and it's settings may differ from what this driver is going to use. This may cause issues, such as inaccurate timer frequency due to incorrect clock divider. This patch adds the initialization code to avoid them. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2021-01-18pinctrl: mediatek: correct error handlingHeinrich Schuchardt
If no GPIO controller is found, the return value should not depend on a random value on the stack. Initialize variable ret. The problem was indicated by cppcheck. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Acked-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
2021-01-18mtd: remove drivers/mtd/mw_eeprom.cHeinrich Schuchardt
drivers/mtd/mw_eeprom.c contains code that never worked. mw_eeprom_write() and mw_eeprom_read() have incorrect loop conditions: while (len <= 2) { CONFIG_MW_EEPROM is not set anywhere. So let's simply drop the module. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-01-18drivers: qe: avoid double free()Heinrich Schuchardt
Avoid calling free(addr) twice if the device for ucode is not found. The problem was indicated by cppcheck. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-01-18mmc: fsl_esdhc_spl: remove superfluous free()Heinrich Schuchardt
Freeing a buffer before calling hang() is superfluous. Removing the call reduces the SPL size. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-01-18doc: board: freescale: advise to use newer atf and firmwareAndrey Zhizhikin
Update branch and version information of ATF and DDR firmware files to point to latest releases provided by NXP. This is especially critical for imx8mp evk, as the ATF support for that SoC is only available in latest releases. Align all SoCs from imx8m family to use identical revisions of ATF and DDR firmware. Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2021-01-18dma: bcm6348: incorrect buffer allocationHeinrich Schuchardt
Calling calloc() for 0 members does not make any sense. Setting ch_priv->busy_desc = NULL for ch_priv->desc_cnt > 0 is equally unreasonable. The current code will lead to a NULL dereference in bcm6348_iudma_enable(). The assignments for ch_priv->busy_desc are obviously swapped. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-01-18cmd: Add a pwm commandPragnesh Patel
Add the command "pwm" for controlling the pwm channels. This command provides pwm invert/config/enable/disable functionalities via PWM uclass drivers Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-18power: pmic: add driver for Monolithic Power mp5416Tim Harvey
This adds basic register access and child regulator binding for the Monolithic MP5416 Power Management IC which integrates four DC/DC switching converters and five LDO regulators. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2021-01-18configs: aspeed: Add defconfig for AST2600 EVBChia-Wei, Wang
Add the default configuration for the AST2600 EVB. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2021-01-18aspeed: Add AST2600 platform supportChia-Wei, Wang
Add low level platform initialization for the AST2600 SoC. The 2-stage booting with U-Boot SPL are leveraged to support different booting mode. However, currently the patch supports only the booting from memory-mapped SPI flash. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2021-01-18ARM: dts: aspeed: Add AST2600 SoC supportChia-Wei, Wang
AST2600 is the 7th generation of Aspeed SoC designated for Interated Remote Management Processor. AST2600 has significant performance improvement by integrating 1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the controllers are also improved with more features and better performance than preceding AST24xx/AST25xx. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2021-01-18reset: aspeed: Add AST2600 reset supportChia-Wei, Wang
Add controller reset support through the System Control Unit (SCU) of AST2600 SoC. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2021-01-18wdt: aspeed: Add AST2600 watchdog supportChia-Wei, Wang
AST2600 has 8 watchdog timers including 8 sets of 32-bit decrement counters, based on 1MHz clock. A 64-bit reset mask is also supported to specify which controllers should be reset by the WDT reset. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2021-01-18ram: aspeed: Add AST2600 DRAM control supportDylan Hung
AST2600 supports DDR4 SDRAM with maximum speed DDR4-1600. The DDR4 DRAM types including 128MbX16 (2Gb), 256MbX16 (4Gb), 512MbX16 (8Gb), 1GbX16 (16Gb), and 1GbX8 TwinDie (16Gb) are supported. Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com> Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2021-01-18clk: aspeed: Add AST2600 clock supportRyan Chen
This patch adds the clock control driver for the AST2600 SoC. Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
2021-01-18board: presidio: Add Parallel NAND supportKate Liu
Set environment for Nand flash (U-boot 2020.04): - add nand flash in the device tree - add new default configuration file for G3 using parallel Nand - set nand parameters in presidio_asic.h Signed-off-by: Kate Liu <kate.liu@cortina-access.com> Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.com> CC: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2021-01-18mtd: rawnand: cortina_nand: Add Cortina CAxxxx SoC supportKate Liu
Add Cortina Access parallel Nand support for CAxxxx SOCs Signed-off-by: Kate Liu <kate.liu@cortina-access.com> Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.com> CC: Tom Rini <trini@konsulko.com> CC: Scott Wood <oss@buserror.net> Reviewed-by: Tom Rini <trini@konsulko.com>
2021-01-18km/arm: cleanup defconfig filesHolger Brunck
Disable some unneeded config options and adapt the ident string. CC: Stefan Roese <sr@denx.de> Signed-off-by: Holger Brunck <holger.brunck@hitachi-powergrids.com> Reviewed-by: Stefan Roese <sr@denx.de>
2021-01-18km/kirkwood: enable USB support and the host controller driverHolger Brunck
Our kirkwood device embeds a USB host controller that is now used on some boards. This enables the support of USB and the corresponding driver. Signed-off-by: Holger Brunck <holger.brunck@hitachi-powergrids.com> CC: Stefan Roese <sr@denx.de> Reviewed-by: Stefan Roese <sr@denx.de>
2021-01-18mmc: Only retrieve cd pin when GPIO is enabledHarm Berntsen
The driver only needs to retrieve the pin for the ACPI info. The driver itself works without depending on GPIO. Signed-off-by: Harm Berntsen <harm.berntsen@nedap.com> CC: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-18acpi: Add missing ARM acpi_table headerHarm Berntsen
The pci_mmc.c driver can generate ACPI info and therefore includes asm/acpi_table.h by proxy. This file does not exist for the ARM architecture and thus code compilation failed when using this driver on ARM. Signed-off-by: Harm Berntsen <harm.berntsen@nedap.com> CC: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-18gpio: do not include <asm/arch/gpio.h> on ARCH_QEMUHarm Berntsen
As no gpio.h is defined for this architecture, to avoid compilation failure, do not include <asm/arch/gpio.h> for QEMU. Signed-off-by: Harm Berntsen <harm.berntsen@nedap.com>
2021-01-18clk: mediatek: Add MT8183 clock driverFabien Parent
Add the topckgen, apmixedsys and infracfg clock driver for the MT8183 SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com>
2021-01-18tools: mtk_image: add support for booting ARM64 imagesFabien Parent
mkimage is only able to package aarch32 binaries. Add support for AArch64 images. One can create a ARM64 image using the following command line: mkimage -T mtk_image -a 0x201000 -e 0x201000 -n "media=emmc;arm64=1" -d bl2.bin bl2.img Signed-off-by: Fabien Parent <fparent@baylibre.com>
2021-01-18configs: pumpkin: enable fastbootFabien Parent
Enable fastboot commands for mt8516 pumpkin board. Signed-off-by: Fabien Parent <fparent@baylibre.com>
2021-01-18configs: pumpkin: enable USB gadgetFabien Parent
Enable USB gadget on pumpkin. This requires to also enable BOARD_LATE_INIT since the init is done in board_late_init function. Signed-off-by: Fabien Parent <fparent@baylibre.com>
2021-01-18board: mediatek: pumpkin: initialize usb deviceFabien Parent
Initialize USB device on pumpkin if it is enabled in the config. Signed-off-by: Fabien Parent <fparent@baylibre.com>
2021-01-18arm: dts: mt8516-pumpkin: enable usb portFabien Parent
Enable the USB port for MT8516 Pumpkin Board. Signed-off-by: Fabien Parent <fparent@baylibre.com>
2021-01-18arm: dts: mt8516: add support for USBFabien Parent
Add support for USB on mt8516 based SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com>
2021-01-18Merge https://gitlab.denx.de/u-boot/custodians/u-boot-shTom Rini
- R-Car pinctrl updates
2021-01-18Merge https://gitlab.denx.de/u-boot/custodians/u-boot-riscvTom Rini
- Update qemu-riscv.rst build instructions. - Add support for SPI on Kendryte K210. - Add Microchip PolarFire SoC Icicle Kit support. - Add support for an early timer. - Select TIMER_EARLY to avoid infinite recursion for Trace.
2021-01-18Merge tag 'doc-2021-04-rc1' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-efi Pull request for documentation tag doc-2021-04-rc1 * document man-page base command * move README.fdt-overlays to HTML documentation * add synopsis for pstore command
2021-01-18Merge branch '2021-01-16-assorted-improvements'Tom Rini
- Assorted testing improvements and fixes - Assorted code cleanups
2021-01-18ARM: dts: renesas: Remove leading 0x from rpc nodeLad Prabhakar
Remove the leading "0x" from rpc node to fix the below dtc warning: Warning (simple_bus_reg): Node /soc/rpc@0xee200000 simple-bus unit address format error, expected "ee200000" Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2021-01-18pinctrl: renesas: Implement get_pin_muxing() callbackLad Prabhakar
Implement get_pin_muxing() callback so that pinmux status command can be used on Renesas platforms. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
2021-01-18pinctrl: renesas: Make sure the pin type is updated after setting the MUXLad Prabhakar
By default on startup all the pin types are configured to PINMUX_TYPE_NONE (in sh_pfc_map_pins()), when pin is set as GPIO the pin type is updated to PINMUX_TYPE_GPIO. But the type is not updated when the pin is set as a function in sh_pfc_pinctrl_pin_set() or sh_pfc_pinctrl_group_set() calls (these calls only set the MUX if the pin type is PINMUX_TYPE_NONE ie unused). So with the current implementation pin functionality could be overwritten silently, for example if the same pin is added for SPI and serial. This patch makes sure of updating pin type after every successful call to sh_pfc_config_mux() and thus fixing from pin functionality to be overwritten. Also a warning message is printed if the current pin is being overwritten before abort. This also avoids pin re-muxing to same type that is for example from command line device is asked to re-probe/select (mmc dev x) we return early with success in this case as the pin is already muxed. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
2021-01-18doc: board: Add Microchip MPFS Icicle Kit docPadmarao Begari
This doc describes the procedure to build, flash and boot Linux using U-boot on Microchip MPFS Icicle Kit. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2021-01-18riscv: Add Microchip MPFS Icicle Kit supportPadmarao Begari
This patch adds Microchip MPFS Icicle Kit support. For now, only NS16550 Serial, Microchip clock, Cadence eMMC and MACB drivers are enabled. The Microchip MPFS Icicle defconfig by default builds U-Boot for S-Mode because U-Boot on Microchip PolarFire SoC will run in S-Mode as payload of HSS + OpenSBI. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com>
2021-01-18riscv: dts: Add device tree for Microchip Icicle KitPadmarao Begari
Add device tree for Microchip PolarFire SoC Icicle Kit. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
generated by cgit v1.2.3 (git 2.0.4) at 2025-11-05 17:07:54 +0000