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2024-12-07lib: hashtable: Prevent recursive calling of callback functionsChristoph Niedermaier
In case there are two variables which each implement env callback that performs env_set() on the other variable, the callbacks will call each other recursively until the stack runs out. Prevent such a recursion from happening. Example which triggers this behavior: static int on_foo(...) { env_set("bar", 0); ... } static int on_bar(...) { env_set("foo", 0); ... } U_BOOT_ENV_CALLBACK(foo, on_foo); U_BOOT_ENV_CALLBACK(bar, on_bar); Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com> Suggested-by: Marek Vasut <marex@denx.de>
2024-12-07arm64: imx8mp: Read values from M24C32-D write-lockable page on DHCOM i.MX8MPChristoph Niedermaier
The new i.MX8M Plus DHCOM rev.200 is populated with M24C32-D EEPROM that contains an additional write-lockable page called ID page, which is populated with a structure containing ethernet MAC addresses, DH item number and DH serial number. Because the write-lockable page is not present on rev.100 i.MX8MP DHCOM SoM, test whether EEPROM ID page exists by setting up the i2c driver. There may be multiple EEPROMs with an ID page on this platform, always use the first one. The evaluation of the EEPROM ID page is done in two steps. First, the content is read and checked. This is done to cache the content of the EEPROM ID page. Second, the content is extracted from the EEPROM buffer by requesting it. For the ethernet MAC address the i.MX8M Plus DHCOM currently supports parsing address from multiple sources in the following priority order: 1) U-Boot environment 'ethaddr'/'eth1addr' environment variable 2) SoC OTP fuses 3) On-SoM EEPROM Add support for parsing the content of this new EEPROM ID page and place it between 2) and 3) on the priority list. The new entry is 2.5) On-SoM EEPROM write-lockable page. Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com> Reviewed-by: Marek Vasut <marex@denx.de>
2024-12-07arm64: dts: imx8mp: Add aliases for the access to the EEPROM ID page nodeChristoph Niedermaier
The new i.MX8M Plus DHCOM rev.200 is populated with M24C32-D EEPROM that contains an additional write-lockable page called ID page. Add aliases eeprom0wl and eeprom1wl for the access to the EEPROM ID page node. Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com> Reviewed-by: Marek Vasut <marex@denx.de>
2024-12-07imx: Support i.MX91 11x11 EVK boardPeng Fan
Add i.MX91 11x11 EVK Board support. - Four ddr scripts included w/o inline ecc feature. - SDHC/NETWORK/I2C/UART supported - PCA9451 supported, default nominal drive mode - Documentation added. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2024-12-07arm64: dts: add NXP i.MX91 device treePeng Fan
Add the i.MX91 device tree from [1]. These files could be synced to linux upstream after [1] merged to linux source tree. [1] https://lore.kernel.org/all/20241120094945.3032663-1-pengfei.li_1@nxp.com/ Signed-off-by: Peng Fan <peng.fan@nxp.com>
2024-12-07pinctrl: imx93: support i.MX91Peng Fan
Reuse i.MX93 pinctrl driver for i.MX91, because i.MX91 follows same design as i.MX93 in IOMUXC controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2024-12-07ddr: imx: Add new rates for i.MX91Ye Li
iMX91 reuses iMX93 controller and PHY, but with lower speed, so add new DDR rates for i.MX91. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2024-12-07clk: imx: clk-fracn-gppll: Add new PLL rateYe Li
Add new rates to integer and frac PLL to support iMX91 Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2024-12-07clk: imx93: support i.MX91Peng Fan
i.MX91 is a derived from i.MX93, and most clocks could be reused from i.MX93. Also Update imx93-clock.h to sync with linux next. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2024-12-07imx: Add iMX91 supportPeng Fan
iMX91 is reduced part from iMX93 with part number: i.MX9131/11/01 It removed A55_1, M33, MIPI DSI, LVDS, etc. i.MX9131: - Support 2.4GT/s DDR and HWFFC at 1.2GT/s i.MX9121: - A55 at 800Mhz and DDR at 1600MTS, with low drive mode. i.MX9111: - Support 1.6GT/s DDR and HWFFC at 800MT/s i.MX9101: - Support 800Mhz ARM clock - Support 1.6GT/s DDR and HWFFC at 800MT/s - No parallel display, eQOS, flexcan Updated Clock/Container/CPU and etc for i.MX91 Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2024-12-07imx93: Update 9x9 part fuses checkingYe Li
According to iMX93 fuse burn plan, all 9x9 parts will have USB2, ENET1 (FEC), LVDS1, CSI1 and DSI1 disabled. The codes missed ENET1 fuse when detecting 9x9. Although it still can detect 9x9 correctly, we add the ENET1 fuse to the check to be more accurate. Fixes: 58da865e27f ("imx9: add i.MX93 variants support") Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2024-12-07imx9: gpio: include types.h headerPeng Fan
Include types.h header for u32, following Linux Coding Style to include necessary headers. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2024-12-07imx9: trdc: correct DEBUG usagePeng Fan
Replace '#if DEBUG' with '#ifdef DEBUG', otherwise '#define DEBUG 1' should be used and conflict with '#define DEBUG' in include/log.h Fixes: 5fda95fb944 ("imx: imx9: Add TRDC driver for TRDC init") Signed-off-by: Peng Fan <peng.fan@nxp.com>
2024-12-07gpio: imx_rgpio2p: Move 8ulp_data to data sectionPeng Fan
have_dual_base is set to false, so the 8ulp_data will be put in BSS section which conflicts with the area of u-boot.dtb which padded just after u-boot-nodtb.bin. So move 8ulp_data to data section to avoid its content being corrupted by dtb. Fixes: 51cfa66f2c4 ("gpio: imx_rgpio2p: support one address") Signed-off-by: Peng Fan <peng.fan@nxp.com>
2024-12-07board: phytec: phycore_imx8mm: Add RAUC boot logic to environmentYunus Bas
Add RAUC boot logic to the environment. Signed-off-by: Yunus Bas <y.bas@phytec.de>
2024-12-07phycore_imx8mm: Move default bootcmd to board envYunus Bas
Move the default bootcmd from the defconfig to the board environment. Signed-off-by: Yunus Bas <y.bas@phytec.de>
2024-12-07phycore_imx8mm: Switch to using env text filesYunus Bas
Move the environment into the board directory and convert header to a txt file. In addition, this patch also applies following changes: - Change default nfsroot path to /srv/nfs due to compliance with Linux FHS 3.0. - Rename specific variables as stated in the bootstd documentation. Renamed variables: fdt_addr => fdt_addr_r fdt_file => fdtfile Signed-off-by: Yunus Bas <y.bas@phytec.de>
2024-12-06Merge patch series "board: ti: k3-am65: covert last board to OF_UPSTREAM"Tom Rini
Bryan Brattlof <bb@ti.com> says: Hello Everyone! This small series converts TI's AM65x reference board to use CONFIG_OF_UPSTREAM and removes the unused device tree files from arch/arm/dts. Because it's the last board using a AM65x without enabling OF_UPSTREAM it allows us to also remove all the SoC FDT files as well and keep a single version of the SoC's DT files in the dts/upstream directory going forward. Link: https://lore.kernel.org/r/20241121-am65x-v1-0-fe87aff1b5fc@ti.com
2024-12-06arm: dts: k3-am65: remove unsused am65x SoC fdt filesBryan Brattlof
With all boards using TI's AM65x having enabled CONFIG_OF_UPSTREAM cleanup the unused SoC fdt files. Signed-off-by: Bryan Brattlof <bb@ti.com>
2024-12-06arm: dts: k3-am654: cleanup unused board filesBryan Brattlof
With the reference board now using CONFIG_OF_UPSTREAM these board files are unused. Remove them Signed-off-by: Bryan Brattlof <bb@ti.com>
2024-12-06board: ti: am65x: migrate to OF_UPSTREAMBryan Brattlof
Rather than rely on manual updates from the arch/arm/dts directory, enable CONFIG_OF_UPSTREAM to receive automatic device tree updates for the am65x reference board. Signed-off-by: Bryan Brattlof <bb@ti.com>
2024-12-06Merge patch series "PLL Sequencing update"Tom Rini
Manorit Chawdhry <m-chawdhry@ti.com> says: It has done a re-write of the full driver and the commits aren't split to keep the bisectability intact. Boot Logs: https://gist.github.com/manorit2001/1eaba109d722715a233244da693133d3 Link: https://lore.kernel.org/r/20241121-b4-upstream-pll-fix-v1-0-904f618897a7@ti.com
2024-12-06clk: ti: clk-k3-pll: Add additional robustness steps to the PLL sequenceManorit Chawdhry
Based on the recommendation from HW team make modifications to the sequence for more robustness. - Unlock the PLL registers - Enable external bypass - Disable the PLL - Program pllm and pllf - Program Ref divider - Enable other PLL controls like DSM_EN, DAC_EN,etc - Enable calibration if available - Enable PLL - Wait for PLL lock and Calibration lock - Remove external bypass Re-write the full sequence from scratch as the previous sequence was way off and keep it in a single commit for bisectability. Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2024-12-06clk: ti: clk-k3-pll: Change variable name reg to baseManorit Chawdhry
base is more appropriate for the usage as the variable stores the base address and seems more accurate w.r.t reg. Change reg to base. Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2024-12-06arm: dts: k3-*-r5: Remove clocks from mcu_timer0Manorit Chawdhry
Updated PLL driver sequencing requires us to use udelay in the PLL driver as there is no poll bit to get the status of operations. tick-timer(mcu_timer0/main_timer0) setting up the clocks for itself is something that won't work as the PLL driver will be using udelay and PLLs are configured during clock probe which would end up in a recursive probe. tick-timer being used by K3 devices are configured by ROM and we really don't need to configure any of the clocks. Remove the clock dependency from R5 stage as we don't need to setup clocks for it. Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2024-12-06env: Switch the callback static list to KconfigChristoph Niedermaier
Switch the callback static list from the board configuration variable CFG_ENV_CALLBACK_LIST_STATIC to Kconfig CONFIG_ENV_CALLBACK_LIST_STATIC. Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com> Reviewed-by: Marek Vasut <marex@denx.de>
2024-12-06ram: k3-ddrss: drop debug() in timing-sensitive sequenceThéo Lebrun
Those debug() calls might be useful, but beware. They can cause the DDR controller to hang if we do not run the sequence quickly enough. They usually are not an issue with upstream U-Boot and the default DDR config, but they have become troublesome with custom DDR configs. Drop those debug() statements that shouldn't be present in time-sensitive code, to avoid anyone else falling into the trap. Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
2024-12-06Merge patch series "led: update LED boot/activity to new property ↵Tom Rini
implementation" Christian Marangi <ansuelsmth@gmail.com> says: This series is split in 2 part. While adapting the LED boot and activity code to the new property accepted by Rob in dt-schema repository, a big BUG was discovered. The reason wasn't clear at start and took me some days to figure it out. This was triggered by adding a new phandle in the test.dts to introduce test for the new OPs. This single addition caused the sandbox CI test to fail in the dm_test_ofnode_phandle_ot test. This doesn't make sense as reverting the change made the CI test to correctly finish. Also moving the uboot node down after the first phandle (in test.dts the gpio one) also made the CI test to correctly finish. A little bit of searching and debugging made me realize the parse phandle OPs didn't support other.dts at all and they were still referencing phandle index from test.dts. (more info in the related commit) In short the test was broken all along and was working by pure luck. The first 4 patch address and fix the problem for good. The other 4 patch expand and address the property change for LED boot/activity. Posting in a single series as changes are trivial and just to speedup review process. (and also because the second part depends on the first) All CI tested with azure pipeline. Link: https://lore.kernel.org/r/20241110115054.2555-1-ansuelsmth@gmail.com
2024-12-06test: dm: Update test for LED activity and bootChristian Marangi
Update test for LED activity and boot to follow new implementation with property set to the LED node phandle. Also update a copy-paste error in the function name for the activity tests and actually enable the test with the DM_TEST macro. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2024-12-06led: update LED boot/activity to new property implementationChristian Marangi
Update LED boot/activity to reference by phandle instead of label and add to period property the "-ms" suffix. This is a followup request by dt-schema maintainers that required LED node to be referenced by a phandle to the node instead of indirectly by the LED label and for timevalue to have a suffix. While at it generalize the LED node label parsing since the logic is common for generic LED bind and LED activity/boot. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-12-06test: dm: Add test for ofnode options phandle helperChristian Marangi
Add test for ofnode options phandle helper and add new property in the sandbox test dts. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2024-12-06dm: core: implement phandle ofnode_options helperChristian Marangi
Implement ofnode_options phandle helper to get an ofnode from a phandle option in /options/u-boot. This helper can be useful since new DT yaml usually require to link a phandle of a node instead of referencing it by name or other indirect way. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2024-12-06test: dm: Expand dm_test_ofnode_phandle(_ot) with new ofnode/tree_parse_phandleChristian Marangi
Expand dm_test_ofnode_phandle(_ot) with new ofnode/tree_parse_phandle() op. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2024-12-06dm: core: implement ofnode/tree_parse_phandle() helperChristian Marangi
Implement ofnode/tree_parse_phandle() helper as an equivalent of of_parse_phandle to handle simple single value phandle. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2024-12-06test: dm: fix broken dm_test_ofnode_phandle_ot and get_by_phandle_otChristian Marangi
Fix broken dm_test_ofnode_phandle_ot test. They never actually worked and were passing test by pure luck by having the same phandle index of test.dts that coincicentally had #gpio-cells in the same index node. It was sufficient to add a phandle to test.dts to make the test fail. To correctly test these feature, make use oif the new OPs oftree to parse phandle. For consistency with the dm_test_ofnode_phandle, rework the test and other.dts to use the same property with the other- prefix to every node. Also fix dm_test_ofnode_get_by_phandle_ot by making it more robust and renaming the phandle property to other-phandle. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2024-12-06dm: core: implement oftree variant of parse_phandle OPsChristian Marangi
Implement oftree variant of parse_phandle OPs. There is currently a very hidden and laten BUG with parse_phandle OPs that doesn't permit the support of multiple DTS in a system. One usage example if sandbox with the usage of other.dts The BUG is only present on live scenario where of_... OPs are used and it's not present when fdt... OPs are used. This is caused by an assumption made in __of_parse_phandle_with_args, with the of_find_node_by_phandle call that pass the first arg as NULL. This makes of_find_node_by_phandle use the default root node of the system and doesn't permit the usage of alternative tree. This is correct for normal system and also for the linux kernel where it's assumed a single device tree. It's problematic if other device tree needs to be used. To fix this, introduce __of_root_parse_phandle_with_args to define a root device tree for of_find_node_by_phandle. Introduce all the variant OPs for this and in ofnode, the oftree OPs following how it's done for other OPs with similar task. For FDT scenario, ofnode_from_fdtdec_phandle_args is reworked to accept a new variable, node and noffset_to_ofnode is used instead of offset_to_ofnode. This is required to support multiple FDB blob to calculate the correct of_offset of the ofnode. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2024-12-04Merge patch series "Add OPP_LOW support for J7200"Tom Rini
Aniket Limaye <a-limaye@ti.com> says: This series adds OPP_LOW spec data in k3_avs driver and enables a config option to select the OPP_LOW performance point. J7200 SOC supports OPP_LOW and OPP_NOM as two Operating Performance Points as per (7.5 Operating Performance Points) section in the Datasheet [0]. - A72SS/MSMC at 2 GHz/1GHz operation must use OPP_NOM. - A72SS/MSMC at 1 GHz/500 MHz operation can use OPP_NOM or OPP_LOW voltage (though OPP_LOW voltage is recommended to reduce power consumption). The actual OPP voltage for the device is read from the efuse and updated in k3_avs_probe(). The default j7200 devicetree and k3_avs driver set OPP_NOM spec frequency and voltage. In the board init file, if K3_OPP_LOW config is enabled, Check if OPP_LOW AVS voltage read from efuse is valid and update frequency (A72 and MSMC) and voltage (VDD_CPU) as per the OPP_LOW spec. [0]: https://www.ti.com/lit/gpn/dra821u (J7200 Datasheet) Test logs: https://gist.github.com/aniket-l/328ad93ed60c2419ed7be9f85e6b6075 - With series applied on master and CONFIG_K3_OPP_LOW enabled in j7200_evm_r5_defconfig - Logs shown with and without efuse register programmed for OPP_0 (Errors out if OPP_0 not found, programs OPP_LOW spec if found) - Voltage update verified using 'i2c md 0x4c 0xe' in u-boot - Frequency update verified using 'k3conf clock dump' in linux Link: https://lore.kernel.org/r/20241119003617.1871183-1-a-limaye@ti.com
2024-12-04configs: j7200_evm_r5_defconfig: Define K3_OPP_LOWReid Tonking
Define new CONFIG_K3_OPP_LOW under arm/mach-k3/r5/Kconfig and add default value to j7200_evm_r5_defconfig Signed-off-by: Reid Tonking <reidt@ti.com> Signed-off-by: Aniket Limaye <a-limaye@ti.com>
2024-12-04arm: mach-k3: j721e-init.c: Add support for CONFIG_K3_OPP_LOWAniket Limaye
The default j7200 devicetree and k3_avs driver set 2GHz/1GHz frequency for A72/MSMC clks and the OPP_NOM voltage. J7200 SOCs may support OPP_LOW Operating Performance Point: 1GHz/500MHz clks for A72/MSMC and OPP_LOW AVS voltage read from efuse. Hence, add a config check in board_init_f() to select OPP_LOW specs: - Check if OPP_LOW AVS voltage read from efuse is valid. - Use the device IDs and clock IDs (TISCI docs [0]) to find the A72 and MSMC clock frequencies in the devicetree. - Fixup the clock frequencies in devicetree as per OPP_LOW spec. k3_avs driver programs the OPP_LOW AVS voltage for VDD_CPU through k3_avs_notify_freq() callback from clk_k3. [0]: https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/j7200/clocks.html Signed-off-by: Aniket Limaye <a-limaye@ti.com> Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>
2024-12-04misc: k3_avs: Check validity of efuse voltage dataReid Tonking
k3_avs driver checks opp_ids when probing and overwrites the voltage values in vd_data for the respective board. The new k3_avs_check_opp() can be called from board files to check the efuse data and returns 0 if valid. Also add the same check in k3_avs_program_voltage() to error out if the efuse data was not valid. Signed-off-by: Reid Tonking <reidt@ti.com> Signed-off-by: Aniket Limaye <a-limaye@ti.com> Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>
2024-12-04misc: k3_avs: Add OPP_LOW voltage and frequency to vd_dataReid Tonking
J7200 SOC supports OPP_LOW and OPP_NOM as two Operating Performance Points as per (7.5 Operating Performance Points) section in the Datasheet [0]. - A72SS/MSMC at 2 GHz/1GHz operation must use OPP_NOM. - A72SS/MSMC at 1 GHz/500 MHz operation can use OPP_NOM or OPP_LOW voltage (though OPP_LOW voltage is recommended to reduce power consumption). Add OPP_LOW frequency->voltage entry to vd_data. The actual OPP voltage for the device is read from the efuse and updated in k3_avs_probe(). OPP_NOM corresponds to OPP_1 and OPP_LOW to OPP_0 efuse register fields, as described in the Datasheet [0] The register offsets and fields are described in the TRM (5.2.6.1.5 WKUP_VTM_VD_OPPVID_j Register) [1]. [0]: https://www.ti.com/lit/gpn/dra821u (J7200 Datasheet) [1]: https://www.ti.com/lit/pdf/spruiu1 (J7200 TRM) Signed-off-by: Reid Tonking <reidt@ti.com> Signed-off-by: Aniket Limaye <a-limaye@ti.com>
2024-12-04arm: dts: k3-j7200-r5-common: Add msmc clk to a72 nodeReid Tonking
The j7200 SOC has a single DDR controller and hence no need for configuring the MSMC interleaver. Hence we do not have an explicit node for MSMC in j7200 DT, unlike j721s2/j784s4. Also, MSMC clk id is described under A72SS0_CORE0 Device in TISCI documentation [0]. Considering the above, define the MSMC clk in the a72 node. [0]: https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/j7200/clocks.html#clocks-for-a72ss0-core0-device Signed-off-by: Reid Tonking <reidt@ti.com> Signed-off-by: Aniket Limaye <a-limaye@ti.com> Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>
2024-12-04Merge patch series "Enable AVS support for AM68, AM69 and J784S4"Tom Rini
Neha Malcom Francis <n-francis@ti.com> says: This series adds AVS support for AM68 SK, AM69 SK and J784S4 EVM. Boot logs: https://gist.github.com/nehamalcom/db5dbf98357ebac46f648c24ad1a17e2 Link: https://lore.kernel.org/r/20241118105714.1973573-1-n-francis@ti.com
2024-12-04configs: am68_sk_r5: Add AVS ConfigsUdit Kumar
Add AVS and PMIC regulator configs Signed-off-by: Udit Kumar <u-kumar1@ti.com> Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>
2024-12-04configs: j784s4_evm_r5_defconfig: Enable AVSNeha Malcom Francis
Enable AVS support on J784S4 along with regulator. Signed-off-by: Neha Malcom Francis <n-francis@ti.com> Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>
2024-12-04arch: arm: mach-k3: j784s4_init: Probe AVS driverNeha Malcom Francis
Probe the AVS driver to set the AVS voltage. Signed-off-by: Neha Malcom Francis <n-francis@ti.com> Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>
2024-12-04arm: dts: k3-am68-sk-r5-base-board: Add VTM node to R5 stageNeha Malcom Francis
Add the VTM node to the R5 boot stage so that AVS is correctly configured for AM68 SK. Signed-off-by: Neha Malcom Francis <n-francis@ti.com> Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>
2024-12-04arm: dts: k3-j784s4-r5: Add VTM node to R5 stageNeha Malcom Francis
Add VTM node to R5 boot stage so that AVS gets correctly configured for J784S4 EVM and AM69 SK. Signed-off-by: Neha Malcom Francis <n-francis@ti.com> Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>
2024-12-04arm: dts: k3-am68: Enable OSPI bootUdit Kumar
Enable OSPI node to allow OSPI boot on AM68 Signed-off-by: Udit Kumar <u-kumar1@ti.com>
2024-12-04dm: gpio: Return error when pull up/down is requested but set_flags ops is ↵Zixun LI
not implmentated Currently in _dm_gpio_set_flags() when set_flags ops is not implemented direction_output()/_input() is used, but pull up/down is not supported by these ops. Signed-off-by: Zixun LI <admin@hifiphile.com>
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