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Calibration values were calculated using the NXP tool
I.MX6ULL_DDR3_Script_Aid_V0.01.xlsx
Signed-off-by: Wolfgang Birkner <wolfgang.birkner@bshg.com>
Signed-off-by: Simon Holesch <simon.holesch@bshg.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
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When using SPL on i.mx6 we frequently notice some DDR initialization
mismatches between the SPL code and the non-SPL code.
As the non-SPL code have been tested for long time and proves to be
reliable, let's configure the DDR in the exact same way as the non-SPL
case.
The idea is simple: just use the DCD table and write directly to the DDR
registers.
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
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Now that the UART driver can enable the required clocks, remove
the hard-coded clock enable.
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Tested-by: Fabio Estevam <festevam@gmail.com>
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Now that the UART driver can enable the required clocks, remove
the hard-coded clock enable.
Co-developed-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
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The commit dda454e933c6 ("serial: mxc: Support bulk enabling clocks")
breaks the booting of the BSH SMM S2 board. The analysis of the issue
revealed memory allocation failures during the registration of UART4
clocks as well as other peripherals. Increasing SYS_MALLOC_F_LEN to
0x10000 fixed the issue.
Dropping this option allows it to be set to the default value of
CONFIG_SYS_MALLOC_F_LEN, which is set by default to 0x10000 on
i.MX8M platforms.
Co-developed-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
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Commit 2a00d73d081a ("spl: mmc: Try to clean up raw-mode options") breaks
the boot of the BSH SMM S2 board. Add options to load U-Boot from raw NAND
sector.
Fixes: 2a00d73d081a ("spl: mmc: Try to clean up raw-mode options")
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
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Commit 2a00d73d081a ("spl: mmc: Try to clean up raw-mode options") breaks
the boot of the BSH SMM S2 board. As stated in the dropped comment, "Some
boards use this value even though MMC is not enabled in SPL, for example
imx8mn_bsh_smm_s2".
Support load of the U-Boot image from raw NAND sector.
Fixes: 2a00d73d081a ("spl: mmc: Try to clean up raw-mode options")
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
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Commit 2a00d73d081a ("spl: mmc: Try to clean up raw-mode options") breaks
the boot of the BSH SMM S2 board. As stated in the commit itself, "Some
boards use this value even though MMC is not enabled in SPL, for example
imx8mn_bsh_smm_s2".
Support load of the U-Boot image from raw NAND sector. This is equivalent
to load from MMC raw sector.
Fixes: 2a00d73d081a ("spl: mmc: Try to clean up raw-mode options")
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
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Migrate to OF_UPSTREAM for phyCORE-i.MX93 since board can use upstream
Linux kernel device-tree for phyBOARD-Segin-i.MX93.
Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Wadim Egorov <w.egorov@phytec.de>
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commit 68dcbdd594d4 ("ARM: imx: Add weak default reset_cpu()")
introduced a regression that 'reset' command unable to reset
imx6ulz based BSH module's modules in the u-boot.
BSH module's imx6, imx6ulz-bsh-smm-m2.dts
Fixes: 68dcbdd594d4 ("ARM: imx: Add weak default reset_cpu()")
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
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Add the configuration that allow to reset the board from reset
cmd
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
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The node is specified on the parent architecture u-boot.dtsi
file
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
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Standardize on using the IS_ENABLED macro.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
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The function arch_spl_mmc_get_uboot_raw_sector() was never compiled,
even when the option CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION was
enabled. So rename the macro SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION to
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION.
Fixes: 2a00d73d081a ("spl: mmc: Try to clean up raw-mode options")
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
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https://source.denx.de/u-boot/custodians/u-boot-mmc
CI: https://source.denx.de/u-boot/custodians/u-boot-mmc/-/pipelines/26241
- Fix mmc cv1800b build without MMC_SUPPORTS_TUNING
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That's how it looks like without CONFIG_MMC_SUPPORTS_TUNING before the
patch:
aarch64-buildroot-linux-gnu-ld.bfd: drivers/mmc/cv1800b_sdhci.o: in function `cv1800b_execute_tuning':
drivers/mmc/cv1800b_sdhci.c:47:(.text.cv1800b_execute_tuning+0x50): undefined reference to `mmc_send_tuning'
Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request efi-2025-07-rc3-2
Documentation:
* Add test/py/requirements.txt to documentation
* Use globing for selecting pytest files
UEFI:
* Provide a function to disable ANSI output during tests
Other:
* test: allow multiple config options in buildconfigspec
* test: allow testing with NET_LWIP=y
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Adjust network tests to run with CONFIG_NET_LWIP=y.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
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In some cases we have alternative configuration options that supply the
same functionality, e.g CONFIG_NET and CONFIG_NET_LWIP.
Allow to specify all of them as arguments for buildconfigspec() and execute
the text if any of these is fulfilled, e.g.
@pytest.mark.buildconfigspec('net', 'net_lwip')
Update the documentation.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
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After the original series was merged, Quentin noted that we could handle
adding additional tests more easily by using the glob feature. Do so.
Suggested-by: Quentin Schulz <quentin.schulz@cherry.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
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As noted by Quentin, in CI we should be at least versioning the pytest
that we install. To avoid problems later, go with the whole requirements
file being used. Furthermore, our documentation building for readthedocs
must also have pytest so install the requirements file there as well.
Reported-by: Quentin Schulz <quentin.schulz@cherry.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
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We don't want ANSI escape-sequences written in tests since it is a pain
to check the output with ut_assert_nextline() et al.
Provide a way to tests to request that these characters not be sent.
Add a proper function comment while we are here, to encourage others.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
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https://source.denx.de/u-boot/custodians/u-boot-watchdog
CI: https://dev.azure.com/sr0718/u-boot/_build/results?buildId=393&view=results
- make cyclic_(un)register idempotent
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https://source.denx.de/u-boot/custodians/u-boot-marvell
CI: https://dev.azure.com/sr0718/u-boot/_build/results?buildId=392&view=results
- mvebu_espressobin_ultra-88f3720_defconfig: enable hwrng
- kirkwood: Convert to DM_SERIAL for Kirkwood boards
- kirkwood: Convert to DM_SERIAL for Synology DS109 board
- cmd: tlv_eeprom: return after successful read from EEPROM
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Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
Reviewed-by: Stefan Roese <sr@denx.de>
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Now that cyclic_unregister() is safe to call on a not-registered
cyclic_info, we can make cyclic_register() behave like the mod_timer()
and hrtimer_start() APIs in linux, in that they don't distinguish
between whether the timer was already enabled or not; from the point
of the call it is, with whatever timeout/period is set in that most
recent call.
This avoids users of the cyclic API from separately keeping track of
whether their callback is already registered or not, and even if they
know it is, can be used for changing the period (and/or the callback
function) without first doing unregister().
See also this recent'ish message from kernel maintainer Thomas
Gleixner on that API design for timer frameworks:
https://lore.kernel.org/lkml/87ikn6sibi.ffs@tglx/
First of all the question is whether add() and mod() are really
valuable distinctions. I'm not convinced at all. Back then, when we
introduced hrtimers, we came to the conclusion that hrtimer_start()
is sufficient.
Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
Reviewed-by: Stefan Roese <sr@denx.de>
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Make cyclic_unregister() safe to call with an already unregistered, or
possibly never registered, struct cyclic_info. This is similar to how
the various timer APIs in the linux kernel work (they all allow
calling delete/cancel/... on an inactive timer object).
This means callers don't have to separately keep track of whether
their cyclic callback is registered or not, and avoids them trying to
peek into the struct cyclic_info for that information - which leads to
somewhat ugly code as it would have to be guarded by ifdef
CONFIG_CYCLIC.
Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
Reviewed-by: Stefan Roese <sr@denx.de>
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Commit f6eff35b8c19 ("cmd: tlv_eeprom: handle -ENODEV error from
read_eeprom function") removed the needed 'return 0' after a successful
read. As a result, the usage message is shown when 'tlv_eeprom read' is
successfully called.
Let's fix it by adding the needed 'return 0'.
Signed-off-by: Martin Schiller <ms@dev.tdt.de>
Reviewed-by: Stefan Roese <sr@denx.de>
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Remove DS109 board reset_misc() function. U-Boot generic reset is enough.
Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
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Enable DM_SERIAL for Marvell Kirkwood Synology DS109.
Note that this patch depends on:
https://patchwork.ozlabs.org/project/uboot/patch/20250505220853.23679-1-mibodhi@gmail.com/
Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
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Enable DM_SERIAL for Marvell Kirkwood boards that have not been converted.
Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefan Roese <sr@denx.de>
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This device has a hardware random number generator. Linux can
use this feature to randomize the location of the kernel in
memory for better security. However, that functionality is only
available if the bootloader firmware provides it. Enable support
for it in the default configuration for this device.
Signed-off-by: Benjamin Schneider <ben@bens.haus>
Reviewed-by: Stefan Roese <sr@denx.de>
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https://gitlab.denx.de/u-boot/custodians/u-boot-imx
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/26116
- Add imxrt1170 support to the fspi SPI driver.
- Enable PCI early on imx95_evk.
- Fix fsl_enetc imdio register calculation.
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Enable PCI early as the NETC device is an PCI ECAM device.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Alice Guo <alice.guo@nxp.com>
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With commit cc4e8af2c552, fsl_enetc register accessors have been split to
handle different register offsets on different SoCs. However, for
internal MDIO register calculation, only ENETC_PM_IMDIO_BASE was fixed
without adding the SoC specific MAC register offset.
As a result, the network support for the Kontron SMARC-sAL28 and
probably other boards based on the LS1028A CPU is broken.
Add the SoC specific MAC register offset to calculation of imdio.priv to
fix this.
Fixes: cc4e8af2c552 ("net: fsl_enetc: Split register accessors")
Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com>
Signed-off-by: Heiko Thiery <heiko.thiery@gmail.com>
Reviewed-by: Michael Walle <mwalle@kernel.org>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Tested-by: Vladimir Oltean <vladimir.oltean@nxp.com> # LS1028A
Tested-by: Tim Harvey <tharvey@gateworks.com> # imx95_19x19_evk
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Alice Guo <alice.guo@nxp.com>
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Signed-off-by: Jonathan Currier <dullfire@yahoo.com>
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On 32-bit systems, e.g. i.mxrt-1170 fdt_addr_t may only be 32-bit.
Cast to a "long long" for garbage avoidance.
Signed-off-by: Jonathan Currier <dullfire@yahoo.com>
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Signed-off-by: Jonathan Currier <dullfire@yahoo.com>
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Add the device specific driver data, and the clock configuration.
Signed-off-by: Jonathan Currier <dullfire@yahoo.com>
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The flexspi on different SoCs may have different number of LUTs.
So involve lut_num in nxp_fspi_devtype_data to make distinguish.
This patch prepare for the adding of imx8ulp.
Fixes: ef89fd56bdfc ("arm64: dts: imx8ulp: add flexspi node")
Cc: stable@kernel.org
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://patch.msgid.link/20240905094338.1986871-3-haibo.chen@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
(Picked from linux 190b7e2efb1ed8435fc7431d9c7a2447d05d5066)
Signed-off-by: Jonathan Currier <dullfire@yahoo.com>
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Signed-off-by: Tom Rini <trini@konsulko.com>
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Resync all defconfig files using qconfig.py
Signed-off-by: Tom Rini <trini@konsulko.com>
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The commit ac30d90f3367 ("clk: Ensure the parent clocks are enabled
while reparenting") add a call to clk_enable() for the parent clock.
For clock drivers that do not implement the enable() ops, like most
Rockchip clock drivers, this now cause the set_parent() ops to never
be called when CLK_CCF=n (default for Rockchip).
clk_enable() typically return -ENOSYS when the enable() ops is not
implemented by the clock driver, with CLK_CCF=y clk_enable() instead
return 0 when the enable() ops is unimplemented.
Change to ignore -ENOSYS from the newly introduced clk_enable() call to
fix this regression and restore the old behavior of set_parent() ops
being called regardless of if enable() ops is implemented or not.
Fixes: ac30d90f3367 ("clk: Ensure the parent clocks are enabled while reparenting")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Tested-by: Dang Huynh <danct12@riseup.net>
Acked-by: Miquel Raynal <miquel.raynal@bootlin.com>
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https://source.denx.de/u-boot/custodians/u-boot-efi
Pull-request efi-2025-07-rc3
CI:
* https://source.denx.de/u-boot/custodians/u-boot-efi/-/pipelines/26146
Documentation:
* Improve the pytest documentation
* u-boot-test-reset: mention power cycling
* describe u-boot-test-release
* correct link to QEMU
* describe that RISC-V supports semihosting
UEFI:
* link libggc via PLATFORM_LIBGCC to EFI binaries
* allow suppressing ANSI output in dtbdump.efi
* test/py/test_efi_fit: test fdt and initrd
# -----BEGIN PGP SIGNATURE-----
#
# iQIzBAABCAAdFiEEK7wKXt3/btL6/yA+hO4vgnE3U0sFAmggj+IACgkQhO4vgnE3
# U0sjTBAAkWySSBNFoj12AyjO2h4kJecxiJJxyoMYTcsr3xdgV0WTPQFaWcSBqTsL
# NgKq5KFNe+ywUdDIqU1VLOTcQf298hofRrcp5Gfhv+syZaRCorCSoSJI6ZveZ5Bi
# 9N2pPvhEVrlFBF2XannJ5ilYtLAbiqIvVFmdLmFwRPbODv/gfEkSudSy0Za7t1tM
# c7RoRegpXziY4Y1XPfr3MpXgKpUQkOPnvXKUwtHhL055X/1Ggg87dzPg1fiU+DiQ
# AGAgvGD/KF/ym4aWQ3jWyji8Kxc5BLsurv083it7JAmL82wqNbU9j5cx3mS/f2Le
# uL7YWv1GANbq+MoBC5O3nkB+yUtHSLylFC3KKFiehmKhc/JO+Uj3cJY/Q/25+lxs
# aahG3C/5xgBTgM6YEqJfSqKYQVFsC2V/a7gWAFlX7OidYXm6oDBu4TeAHmAtBgcj
# pz0AVCYMWyhKE+zb+4U2mlKEQ8bJpFdC2Q+pTMciGAM3YyztotJ1yoM4IndDrh4q
# ScrIpXHSqWLlZfev+NnJDw1UKLWEJIMeXh0uzfpaT5M0cLEDeHTOSX9Fp3ZPj9Af
# +T3nNWSXWlOW0wc6C5igj4p0UiGSbHMMPOa54f/D0gdl/UkPZ1YPBYVBa/eX1yBy
# NlaJziLCmLqyWpYIVhaigKDtGWfgjoHGaABfyuSIj/HxmIHhD5w=
# =NbGi
# -----END PGP SIGNATURE-----
# gpg: Signature made Sun 11 May 2025 05:54:10 AM CST
# gpg: using RSA key 2BBC0A5EDDFF6ED2FAFF203E84EE2F827137534B
# gpg: Can't check signature: No public key
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Add tests to check initrd and dtb loading
Signed-off-by: Adriano Cordova <adriano.cordova@canonical.com>
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Imitate in dtbdump what initrddump does for color,
newlines and input handling. The output parsing in
the CI is strict and with the current output the CI
is not recongnizing the prompt '=>'.
Signed-off-by: Adriano Cordova <adriano.cordova@canonical.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
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Link .efi applications using libgcc
Signed-off-by: Adriano Cordova <adriano.cordova@canonical.com>
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Mention that RISC-V supports semihosting.
Update the link to ARM's semihosting documentation
Update SPDX identifier to current format.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
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%s/hhttps:/https:/
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
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Add this test to the documentation. No changes to the test itself were
required.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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