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Change type of ulong env_get_bootm_low() to phys_addr_t env_get_bootm_low().
The PPC/LS systems already treat env_get_bootm_low() result as phys_addr_t,
while the function itself still returns ulong. This is potentially dangerous
on 64bit systems, where ulong might not be large enough to hold the content
of "bootm_low" environment variable. Fix it by using phys_addr_t, similar to
what env_get_bootm_size() does, which returns phys_size_t .
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reported-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
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According to README CFG_SYS_BOOTMAPSZ section, in case both "bootm_low" and
"bootm_size" variables are defined, "bootm_mapsize" variable is not defined
and CFG_SYS_BOOTMAPSZ macro is not defined, all data for the Linux kernel
must be between "bootm_low" and "bootm_low" + "bootm_size".
Currently, for systems with DRAM between 0x4000_0000..0x7fff_ffff and with
e.g. bootm_low=0x60000000 and bootm_size=0x10000000, the code will attempt
to reserve memory from 0x4000_0000..0x4fff_ffff, which is incorrect. This
is because "bootm_low" is not taken into consideration correctly.
The last parameter of lmb_alloc_base() is the maximum physical address of
the to be reserved LMB area. Currently this is the start of DRAM bank that
is considered for LMB area reservation + min(DRAM bank size, bootm_size).
In case bootm_low is set to non-zero, this maximum physical address has to
be shifted upward, to min(DRAM bank start + size, bootm_low + bootm_size),
otherwise the reserved memory may be below bootm_low address.
In case of multiple DRAM banks, the current change reserves top part of
the first bank, and reserves the rest of memory in the follow up banks.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
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Bryan Brattlof <bb@ti.com> says:
Hello Again Everyone!
The AM62Px is an extension of the existing Sitara AM62x low-cost family
of application processors built for Automotive and Linux Application
development. Scalable Arm Cortex-A53 performance and embedded features,
such as: multi high-definition display support, 3D-graphics
acceleration, 4K video acceleration, and extensive peripherals make the
AM62Px well-suited for a broad range of automation and industrial
application, including automotive digital instrumentation, automotive
displays, industrial HMI, and more.
Some highlights of AM62P SoC are:
* Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster.
Dual/Single core variants are provided in the same package to allow HW
compatible designs.
* One Device manager Cortex-R5F for system power and resource
management, and one Cortex-R5F for Functional Safety or
general-purpose usage.
* One 3D GPU up to 50 GLFOPS
* H.264/H.265 Video Encode/Decode.
* Display support: 3x display support over OLDI/LVDS (1x OLDI-DL, 1x or
2x OLDI-SL), DSI, or DPI. Up to 3840x1080 @ 60fps resolution
* Integrated Giga-bit Ethernet switch supporting up to a total of two
external ports (TSN capable).
* 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3xMMC and SD, GPMC for
NAND/FPGA connection, OSPI memory controller, 3xMcASP for audio,
1xCSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other peripherals.
* Dedicated Centralized Hardware Security Module with support for secure
boot, debug security and crypto acceleration and trusted execution
environment.
* One 32-bit DDR Subsystem that supports LPDDR4, DDR4 memory types.
* Multiple low power modes support, ex: Deep sleep, Standby, MCU-only,
enabling battery powered system design.
For those interested, more details about this SoC can be found in the
Technical Reference Manual here: https://www.ti.com/lit/pdf/spruj83
Proof-of-Life: https://paste.sr.ht/~bryanb/af2ac108a9362549aa326f182e87918d52bf2d71
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The SPDX ID format usese a single space used after the
'SPDX-License-Identifier:'. Fix all files that use any other white-space
character other than a single space.
Signed-off-by: Bryan Brattlof <bb@ti.com>
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Introduce basic documentation for the am62p family of SoCs.
Signed-off-by: Bryan Brattlof <bb@ti.com>
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Introduce the initial configs needed to support the am62px SoC family
Signed-off-by: Bryan Brattlof <bb@ti.com>
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Include the U-Boot device tree files needed to boot the board.
Signed-off-by: Bryan Brattlof <bb@ti.com>
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Add PSIL data for the AM62P and the J722S SoC family. The PSIL mapping
for the J722S is the same except for the extra instances of the CSI-RX.
So let's reuse the same file for both the AM62P and J722S.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
[bb@ti.com: rebased to U-Boot v2024.01]
Signed-off-by: Bryan Brattlof <bb@ti.com>
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Include the static DMA channel data for ti_sci
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
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Introduce the basic files needed to support the am62px family of SoCs
Co-developed-by: Hari Nagalla <hnagalla@ti.com>
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
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Introduce the basic functions and definitions needed to properly
initialize TI's am62p family of SoCs
Signed-off-by: Bryan Brattlof <bb@ti.com>
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Currently, for the K3 generation of SoCs, there are more SoCs that
utilize the split firmware approach than the combined DMSC firmware.
Invert the logic to avoid adding more and more SoCs to this list.
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Acked-by: Andrew Davis <afd@ti.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
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The am62px family of SoCs uses the same DDR controller as found on the
am62ax family. Enable this option when building for the am62px family
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
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Include the clock and lpsc tree files needed for the wkup spl to
initialize the proper PLLs and power domains to boot the SoC.
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
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Cleanup this list and standardize on using the IS_ENABLED macro for the
power domain data list.
Reviewed-by: Igor Opaniuk <igor.opaniuk@foundries.io>
Signed-off-by: Bryan Brattlof <bb@ti.com>
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Include the part number for TI's am62px family of SoCs so we can
properly identify it during boot
Reviewed-by: Igor Opaniuk <igor.opaniuk@foundries.io>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
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Prepare v2024.04-rc4
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Signed-off-by: Tom Rini <trini@konsulko.com>
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https://gitlab.denx.de/u-boot/custodians/u-boot-imx
- Use TF-A on imx8mp_beacon to fix boot regression.
- Use latest 6.8 dts for imx8mp_beacon.
- Fix the RAM initialization for phycore_imx8mp PCL-070 rev 1.
- Describe the 0087 i.mx8m mini product variant in tdx-cfg-block.
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Rsync all defconfig files using moveconfig.py
Signed-off-by: Tom Rini <trini@konsulko.com>
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The device tree has evolved over time, so re-sync. This also
partial reverts one change on the PCIe, because U-Boot doesn't
have a proper driver. However, since the clock is configured
to generate a 100MHz reference clock by default, a proper driver
isn't really necessary.
Signed-off-by: Adam Ford <aford173@gmail.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
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Add new product id 0087 Verdin iMX8M Mini Quad 2GB IT.
Signed-off-by: Joao Paulo Goncalves <joao.goncalves@toradex.com>
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When the board was originally added, it enabled some features which
allowed it to bypass Trusted Firmware, but as the feature set of
Linux grew and more features became available, the U-Boot config
options which bypassed TF-A caused issues, so it needs to return
to the standard operating mode of using TF-A or the system no
longer boots.
Fixes: ab53bd43dbde ("arm64: imx: Add support for imx8mp-beacon-kit")
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
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We need to differ between PCL-070 and PCM-070. PCL-070 supports 2GHz RAM
timings from pcb rev 1 or newer. PCM-070 supports 2GHz RAM timings from
pcb rev 3 or newer.
Signed-off-by: Benjamin Hahn <B.Hahn@phytec.de>
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Add a function that gets the som_type from the EEPROM.
Add an enum for the som_type.
Signed-off-by: Benjamin Hahn <B.Hahn@phytec.de>
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- Singular quirk DT property rename.
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In case the PHY is fully described in DT, use PHY MDIO address
from DT directly instead of always using auto-detection. This
also fixes the behavior of 'mdio list' in such DT setup, which
now prints the PHY connected to the MAC correctly.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
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- Add phytec am64x platform, update am65-cpsw and a few other assorted
fixes.
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Drop old implementation and use hash_command() instead, as
how it's currently done for crc32 and sha1sum cmds.
Test:
=> md5sum 0x60000000 0x200
md5 for 60000000 ... 600001ff ==> e6bbbe95f5b41996f4a9b9af7bbd4050
Signed-off-by: Igor Opaniuk <igor.opaniuk@gmail.com>
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Return value of a function 'malloc_cache_aligned'
is dereferenced at autoboot.c:207 without checking for NULL,
but it is usually checked for this function.
Found by RASU JSC.
Signed-off-by: Maks Mishin <maks.mishinFZ@gmail.com>
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It is found that when DM is enabled, only generic init function is
called in .probe(). Baudrate is never honored. Add a function call
to .setbrg() when probing so that we can update the baudrate of the
serial device.
Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
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Add a new Kconfig symbol MDIO_TI_CPSW for the CPSW MDIO
driver and build it with proper DM support if enabled.
If MDIO_TI_CPSW is not enabled then we continue to
behave like before.
Clean up MDIO custom handling in am65-cpsw and use
dm_eth_phy_connect() to get the PHY.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Tested-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
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Some platforms have bus level Reset controlled
by a GPIO line. If available then handle bus reset
via GPIO.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
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Add documentation for PHYTEC phyCORE-AM64x SoM.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
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Add support for PHYTEC phyCORE-AM64x SoM.
Supported features:
- 2GB DDR4 RAM
- eMMC Flash
- external uSD
- OSPI NOR Flash
- debug UART
Product page SoM: https://www.phytec.com/product/phycore-am64x
Device trees were taken from Linux v6.8-rc2.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
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If mixed rsa and ecdsa keys are specified in dtsi, an rsa key can be sent
into the ecdsa verify. Without the ecdsa,curve property, this function will
crash due to lack of checking the null pointer return.
Signed-off-by: Bob Wolff <bob.wolff68@gmail.com>
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Andrew Davis <afd@ti.com> says:
Explanation for this series is mostly in [4/6]. First 3
patches should be safe to take independent of the last 3.
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The current address of TF-A in DRAM is just below the 512MB address line.
This means if the DRAM in a system is 512MB then TF-A is right at the
end of memory which is often reused, for instance U-Boot relocates itself
here. If a system has less than 512MB then that system wouldn't work at
all as TF-A would fail to load.
To avoid the issues above, move TF-A to the start of DRAM, which doesn't
change from system to system.
As TF-A is position independent, this has no dependency on TF-A. We
also fixup DT as needed when TF-A address is moved, so this change also
has no dependency on Linux and is fully forward/backward compatible.
Signed-off-by: Andrew Davis <afd@ti.com>
Acked-by: Bryan Brattlof <bb@ti.com>
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The address we load TFA and OP-TEE to is configurable by
CONFIG_K3_{ATF,OPTEE}_LOAD_ADDR, but the DT nodes reserving this memory
are static. Fix that by updating this node when the loaded address
does not match the address in DT.
Signed-off-by: Andrew Davis <afd@ti.com>
Acked-by: Bryan Brattlof <bb@ti.com>
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The address we load TF-A and OP-TEE to is configurable by Kconfig
CONFIG_K3_{ATF,OPTEE}_LOAD_ADDR, but the DT nodes reserving this memory
are often statically defined. As these binaries are dynamically loadable,
and in the case of OP-TEE may not even be loaded at all, hard-coding these
addresses is not a hardware description, but rather a configuration.
If the address that U-Boot loaded TF-A or OP-TEE does not match the
address in hard-coded in DT, then fix that node address. This also handles
the case when no reserved memory for these is provided by DT, which is
more correct as explained above.
Add this fixup function, and enable it for AM62.
Signed-off-by: Andrew Davis <afd@ti.com>
Acked-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
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The fixups provided by ft_system_setup() are applicable for all AM62 based
boards. Select this at the target selection level for all AM62 boards and
remove it from any specific defconfig.
Signed-off-by: Andrew Davis <afd@ti.com>
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Much like we have for ATF, OP-TEE has a standard address that we load
it too and run it from. Add a Kconfig item for this to remove some
hard-coding and allow this address to be more easily changed.
Signed-off-by: Andrew Davis <afd@ti.com>
Acked-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
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There is a default ATF load address that is used for devices that have
ATF running in SRAM. For AM62 and AM62a, ATF runs from DRAM. Instead
of having to override the address in every defconfig, make add a
default for these ATF in DRAM devices.
Signed-off-by: Andrew Davis <afd@ti.com>
Acked-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
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Allow boards that use ti_spl_template to not use optee part in
configuration.
Vendor can have module with 256 Mb of memory and they try to optimize
the available memory just using the essential components.
This change allow to remove tee from configuration without binman
fail.
configurations {
default = "conf-0";
conf-0 {
description = "k3-am62_ccm_m3";
firmware = "atf";
loadables = "dm", "spl";
fdt = "fdt-0";
};
};
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
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Jonathan Humphreys <j-humphreys@ti.com> says:
This series enables OSPI storage and boot.
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The phy calibration pattern partition isn't needed as the Cadence driver isn't
calibrating the phys.
Signed-off-by: Jonathan Humphreys <j-humphreys@ti.com>
Fixes: 58d61fb5a77e ("arm: dts: k3-j721e-sk: Add initial A72 specific dts support")
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Add boot ROM XSPI bootmode, and set to BOOT_DEVICE_SPI if detected.
Signed-off-by: Jonathan Humphreys <j-humphreys@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
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Set config values to enable OSPI functionality.
Signed-off-by: Jonathan Humphreys <j-humphreys@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
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Jonathan Humphreys <j-humphreys@ti.com> says:
This series enables OSPI support for AM64x by setting the proper configs, and DT
entries for SPL.
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Add bootph DT tags to enable OSPI in SPL.
Set OSPI regs for R5 SPL to address OSPI's boot region.
Signed-off-by: Jonathan Humphreys <j-humphreys@ti.com>
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