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2023-03-10ARM: dts: renesas: Enable sysinfo on R-Car D3 DraakTam Nguyen
Enable support for sysinfo on R-Car D3 Draak board. The sysinfo is used e.g. to access and decode board-specific information and then in turn used by board-info to print those information. Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> [Marek: Drop compatible from I2C node, this is in r8a77995.dtsi already. Drop status = "okay" from EEPROM node. Add dts: tag. Fix Kconfig EEPROM address to be 0x50 and match the DT, sync config.]
2023-03-10ARM: dts: renesas: Enable sysinfo on R-Car V3H Condor/Condor-ITam Nguyen
Add new sysinfo IDs for R-Car V3H Condor/Condor-I . Enable support for sysinfo on R-Car V3H Condor/Condor-I. The sysinfo is used e.g. to access and decode board-specific information and then in turn used by board-info to print those information. Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> [Marek: Drop compatible from I2C node, this is in r8a77980.dtsi already. Drop status = "okay" from EEPROM node. Add dts: tag. Update the commit message, note the new sysinfo IDs. Fix Kconfig EEPROM address to be 0x50 and match the DT, sync config.]
2023-03-10sysinfo: rcar3: Fix Draak and Eagle board codeTam Nguyen
Correct the board code ID based on the hardware documentation Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-03-10pinctrl: renesas: Drop non-existent PFC info table entriesMarek Vasut
Remove PFC info table entries which are never instantiated, since there are no drivers for those. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-03-10clk: renesas: Always select DM_RESET to prevent inobvious failure of ↵Marek Vasut
rst_gen3 subdriver The CLK_RCAR_GEN3 registers two subdrivers, clk_gen3 and rst_gen3. The former depends on the clock framework, which is always enabled in this context of clock framework driver, while the later depends on reset framework which may not always be enabled. Ensure the reset framework is also always enabled to prevent inobvious early boot time bind failure of the CPG driver, which leads to system showing no activity and is difficult to debug. Note that one possible approach to debug this is to use CONFIG_DEBUG_UART and add debug printascii()s into the drivers/clk/renesas/clk-rcar-gen3.c . Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-03-10mmc: renesas-sdhi: Add proper probe error fail pathMarek Vasut
In case one of the calls in probe fail, trigger a fail path and undo all the steps done in probe until the point of failure. The current implementation failed to stop controller clock and free claimed clock, so fix that. Furthermore, print return code in error prints for easier debugging. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-03-10mmc: renesas-sdhi: Always configure default SDnH clock rate to 800 MHzMarek Vasut
The prior stage bootloader might have left the SDnCKCR register in completely arbitrary state before passing control to U-Boot, which includes the register being populated with incorrect values. Currently the SDHI driver will attempt to use clock framework to configure SDn clock, which may fail in case SDnCKCR contains invalid values for the SDnH clock, because the clock framework would not be able to determine SDnH clock rate and would get -EINVAL instead, which in turn would not allow the clock framework to determine the correct SDn clock divider ratio. This failure occurs specifically in case SDnCKCR reads back 0x209 . Correct the problem by first setting default SDnH clock rate to 800 MHz, thus assuring the SDnCKCR SDnH bits are correct, and only afterward set up the SDn clock rate to default 200 MHz. Note that the SDHI driver may reconfigure SDnH clock later based on IOS settings obtained from the attached card, the 800 MHz set up here is only the default value. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-03-06Merge https://source.denx.de/u-boot/custodians/u-boot-marvellTom Rini
- mvebu: Use 4K sector for Thecus N2350 SPI flash (Tony)
2023-03-06arm: mvebu: Use 4K sector for Thecus N2350 SPI flashTony Dinh
Since the SPI flash chip mx25l3205d on this board has 4K-sector capability, enable it for the envs. Signed-off-by: Tony Dinh <mibodhi@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
2023-03-01Merge tag 'dm-pull-29feb23' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-dm minor sandbox fixes a37xx fix Add camel-case tool, since the conversion will take a while
2023-03-01tools: binman: minor formatting fix in docsRalph Siemsen
This should fix a rendering oddity when viewing the docs online at https://u-boot.readthedocs.io/en/latest/develop/package/binman.html Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-03-01sandbox: fix building with CONFIG_SPL_TIMER=yHeinrich Schuchardt
Building sandbox_defconfig with CONFIG_SPL_TIMER=y results in an error include/dm/platdata.h:63:33: error: static assertion failed: "Cannot use U_BOOT_DRVINFO with of-platdata. Please use devicetree instead" Add a missing condition in the sandbox driver. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-03-01MAINTAINERS: assign sandbox drivers to SANDBOXHeinrich Schuchardt
Drivers should have a maintainer. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-03-01sandbox: allow building sandbox_spl with CONFIG_DEBUGHeinrich Schuchardt
Building sandbox_spl with CONFIG_DEBUG leads to errors due to missing symbols: /usr/bin/ld: common/spl/spl_fit.o: in function `spl_fit_upload_fpga': common/spl/spl_fit.c:595: undefined reference to `fpga_load' /usr/bin/ld: test/test-main.o: in function `dm_test_post_run': test/test-main.c:124: undefined reference to `crc8' /usr/bin/ld: test/test-main.o: in function `dm_test_pre_run': test/test-main.c:95: undefined reference to `crc8' collect2: error: ld returned 1 exit status This is due to -Og not eliminating unused functions. Add FPGA and CRC8 support to the defconfig. Sandbox tests for SPL_FPGA and CRC8 should be created. So enabling these setting is advised anyway. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-03-01arm64: a37xx: pinctrl: probe after bindingRobert Marko
Currently, pinctrl drivers are getting probed during post-bind, however that is being reverted, and on A37XX pinctrl driver is the one that registers the GPIO driver during the probe. So, if the pinctrl driver doesn't get probed GPIO-s won't get registered and thus they cannot be used. This is a problem on the Methode eDPU as it just uses SB pins as GPIO-s and without them being registered networking won't work as it only has one SFP slot and the TX disable GPIO is on the SB controller. So, lets just add a flag only to A37XX driver to probe after binding in order for the GPIO driver to always get registered. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-03-01sandbox: Correctly define BITS_PER_LONGMichal Suchanek
SANDBOX_BITS_PER_LONG is the number of bits in long on the sandbox platform. Signed-off-by: Michal Suchanek <msuchanek@suse.de>
2023-03-01RFC: tools: Add a camel-case conversion scriptSimon Glass
This is only for posterity, since once the conversion is done, the script is of no use. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-03-01Merge tag 'u-boot-at91-fixes-2023.04-a' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-at91 First set of u-boot-at91 fixes for the 2023.04 cycle: This fixes set include one clock index fix for sama7g5 and two board configuration alignments for pm9g45.
2023-02-28Merge tag 'u-boot-rockchip-20230228' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-rockchip Please pull the updates for rockchip platform: - Add support for rk3588 soc; - Add rk3588 Edgeble Neu6 board and Radxa ROCK5B board; - Add rk3308 Radxa ROCK Pi S board; - Add rk3568 Radxa ROCK 3 board, - Add rk3566 Radxa Compute Module 3 board; - Add support for sdram reg info version 3 - Refactor rockchip OTP/eFuse driver and add more soc support; - Add external TPL support for binman; binman support for mkimage ignore missing entry is based on [1]; [1] https://patchwork.ozlabs.org/project/uboot/patch/20230219220158.4160763-7-jonas@kwiboo.se/
2023-02-28board: rock5b-rk3588: add memory gaps into kernel's DTBEugen Hristev
RK3588 has two memory gaps when using 16 GiB DRAM size: [0x3fc000000 , 0x3fc500000] and [0x3fff00000 , 0x3ffffffff] If the kernel is agnostic to these gaps, accessing the area causes a SError panic. Hence, add reserved memory areas in kernel's DTB before booting. Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28board: rockchip: add Radxa ROCK5B Rk3588 boardEugen Hristev
ROCK 5B is a Rockchip RK3588 based SBC (Single Board Computer) by Radxa. There are tree variants depending on the DRAM size : 4G, 8G and 16G. Specification: Rockchip Rk3588 SoC 4x ARM Cortex-A76, 4x ARM Cortex-A55 4/8/16GB memory LPDDR4x Mali G610MC4 GPU MIPI CSI 2 multiple lanes connector eMMC module connector uSD slot (up to 128GB) 2x USB 2.0, 2x USB 3.0 2x HDMI output, 1x HDMI input Ethernet port 40-pin IO header including UART, SPI, I2C and 5V DC power in USB PD over USB Type-C Size: 85mm x 54mm Kernel commits: a1d3281450ab ("arm64: dts: rockchip: Add rock-5b board") 6fb13f888f2a ("arm64: dts: rockchip: Update sdhci alias for rock-5b") Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28clk: rockchip: rk3568: add more supported clk rates for sdmmc and emmcVasily Khoruzhick
SDHCI driver may attempt to set 26MHz clock, but clk_rk3568 will return error in this case. Apparently, SDHCI silently ignores the error and as a result eMMC initialization fails. Add 25 MHz and 26 MHz clk rates for sdmmc and emmc on rk3568 to fix that. Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28rockchip: rk3588: Read cpuid from otpJonas Karlman
Read cpuid from otp and set ethaddr for RK3588. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28rockchip: rk3568: Read cpuid from otpJonas Karlman
The cpuid on RK3568 is located at 0xa instead of 0x7 as all other SoCs. Add and use a CFG_CPUID_OFFSET to define this offset. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28rockchip: misc: Set eth1addr mac addressJonas Karlman
Set eth1addr in addition to ethaddr. Also allow fdt fixup of ethernet mac addresses when CMD_NET is disabled. Set ethaddr and eth1addr based on HASH and SHA256 options. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28rockchip: efuse: Add support for RK3036Jonas Karlman
Add support for rk3036 compatible. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28rockchip: efuse: Add support for RK3128Jonas Karlman
Add support for rk3128 compatible. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28rockchip: efuse: Add support for RK3328Jonas Karlman
Add support for rk3328 compatible. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28rockchip: efuse: Add support for RK3288 and moreJonas Karlman
Add support for rk3066a, rk3188, rk322x and rk3288 compatible. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28rockchip: efuse: Refactor to use driver data and opsJonas Karlman
Refactor the driver to use driver data and ops to simplify handling of SoCs that require a unique read op. Move handling of the aligned bounce buffer to main read op in order to keep the SoC unique read op simple. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28rockchip: otp: Add dump_otp debug commandJonas Karlman
Add a simple debug command to dump the content of the otp. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28rockchip: otp: Add support for RK3588Jonas Karlman
Add support for rk3588 compatible. Adjust offset using driver data in main read op. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28rockchip: otp: Add support for RK3568Jonas Karlman
Add support for rk3568 compatible. Handle allocation of an aligned bounce buffer in main read op in order to keep the SoC unique read op simple. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28rockchip: otp: Refactor to use driver data and opsJonas Karlman
Refactor the driver to use driver data and ops to simplify handling of SoCs that require a unique read op. Use readl_poll_sleep_timeout instead of a custom poll loop, and add validation of input parameter to main read op. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28board: rockchip: Add Edgeble Neural Compute Module 6Jagan Teki
Neural Compute Module 6(Neu2) is a 96boards SoM-CB compute module based on Rockchip RK3588 from Edgeble AI. General features: - Rockchip RK3588 - up to 32GB LPDDR4x - up to 128GB eMMC - 2x MIPI CSI2 FPC On module WiFi6/BT5 is available in the following Neu6 variants. Neural Compute Module 6(Neu6) IO board is an industrial form factor ready-to-use IO board from Edgeble AI. IO board offers plenty of peripherals and connectivity options and this patch enables basic eMMC and UART which is enough to successfully boot Linux. Neu6 needs to mount on top of this IO board in order to create a complete Edgeble Neural Compute Module 6(Neu6) IO platform. Boot log for the record, DDR Version V1.08 20220617 LPDDR4X, 2112MHz channel[0] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB channel[1] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB channel[2] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB channel[3] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB Manufacturer ID:0x6 CH0 RX Vref:31.7%, TX Vref:21.8%,21.8% CH1 RX Vref:30.7%, TX Vref:22.8%,23.8% CH2 RX Vref:30.7%, TX Vref:22.8%,22.8% CH3 RX Vref:30.7%, TX Vref:21.8%,21.8% change to F1: 528MHz change to F2: 1068MHz change to F3: 1560MHz change to F0: 2112MHz out U-Boot SPL 2023.01-00952-g1d1785a516-dirty (Jan 30 2023 - 19:53:55 +0530) Trying to boot from MMC1 INFO: Preloader serial: 2 NOTICE: BL31: v2.3():v2.3-391-g856309329:derrick.huang NOTICE: BL31: Built : 14:15:50, Jul 18 2022 INFO: ext 32k is not valid INFO: GICv3 without legacy support detected. INFO: ARM GICv3 driver initialized in EL3 INFO: system boots from cpu-hwid-0 INFO: idle_st=0x21fff, pd_st=0x11fff9, repair_st=0xfff70001 INFO: dfs DDR fsp_params[0].freq_mhz= 2112MHz INFO: dfs DDR fsp_params[1].freq_mhz= 528MHz INFO: dfs DDR fsp_params[2].freq_mhz= 1068MHz INFO: dfs DDR fsp_params[3].freq_mhz= 1560MHz INFO: BL31: Initialising Exception Handling Framework INFO: BL31: Initializing runtime services WARNING: No OPTEE provided by BL2 boot loader, Booting device without OPTEE initialization. SMC`s destined for OPTEE will return SMC_UNK ERROR: Error initializing runtime service opteed_fast INFO: BL31: Preparing for EL3 exit to normal world INFO: Entry point address = 0xa00000 INFO: SPSR = 0x3c9 U-Boot 2023.01-00952-g1d1785a516-dirty (Jan 30 2023 - 19:53:55 +0530) Model: Edgeble Neu6A IO Board DRAM: 7.5 GiB (effective 3.7 GiB) Core: 71 devices, 15 uclasses, devicetree: separate MMC: mmc@fe2c0000: 0 Loading Environment from nowhere... OK In: serial@feb50000 Out: serial@feb50000 Err: serial@feb50000 Model: Edgeble Neu6A IO Board Net: No ethernet found. Hit any key to stop autoboot: 0 => Add support for Edgeble Neu6 Model A IO Board. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28ARM: dts: rockchip: rk3588s-u-boot: Add sdmmc nodeJagan Teki
Booting from SDMMC is one of the fast and easy booting methods for initial support of any SoC to upstream more features.  This patch is trying to add the sdmmc node for rk3588 and added as u-boot specific node in -u-boot.dtsi as upstream Linux is not supporting yet. As soon as Linux supports it, a sync of the Linux device tree would eventually drop this node.  Clock properties as added according to the rockchip mmc driver but the actual definition might add scmi clocks into 0 and 1 indexes. This is due to scmi clock are not supporting in upstream U-Boot. Properly addition of scmi clock would eventually follow sdmmc clock definition of Linux once they upstreamed. Signed-off-by: Jagan Teki <jagan@edgeble.ai>
2023-02-28ARM: dts: rockchip: Add rk3588-u-boot.dtsiJagan Teki
Add u-boot,dm-spl and u-boot,dm-pre-reloc related properties for Rockchip RK3588 SoC to boot the SPL. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28arm: rockchip: Add RK3588 arch core supportJagan Teki
The Rockchip RK3588 is a ARM-based SoC with quad-core Cortex-A76 and quad-core Cortex-A55 including NEON and GPU, 6TOPS NPU, Mali-G610 MP4, HDMI Out, HDMI In, DP, eDP, MIPI DSI, MIPI CSI2, LPDDR4/4X/5, eMMC5.1, SD3.0/MMC4.5, USB OTG 3.0, Type-C, USB 2.0, PCIe 3.0, SATA 3, Ethernet, SDIO3.0 I2C, UART, SPI, GPIO and PWM. Add arch core support for it. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28arm64: dts: rockchip: rk3588: Add Edgeble Neu6 Model A IOJagan Teki
Neural Compute Module 6(Neu6) IO board is an industrial form factor ready-to-use IO board from Edgeble AI. IO board offers plenty of peripherals and connectivity options and this patch enables basic eMMC and UART which is enough to successfully boot Linux. Neu6 needs to mount on top of this IO board in order to create a complete Edgeble Neural Compute Module 6(Neu6) IO platform. commit <a5079a534554> ("arm64: dts: rockchip: rk3588: Add Edgeble Neu6 Model A IO") Add support for Edgeble Neu6 Model A IO Board. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28arm64: dts: rockchip: rk3588: Add Edgeble Neu6 Model A SoMJagan Teki
Neural Compute Module 6(Neu2) is a 96boards SoM-CB compute module based on Rockchip RK3588 from Edgeble AI. General features: - Rockchip RK3588 - up to 32GB LPDDR4x - up to 128GB eMMC - 2x MIPI CSI2 FPC On module WiFi6/BT5 is available in the following Neu6 variants. Neu6 needs to mount on top of associated Edgeble IO boards for creating complete platform solutions. Enable eMMC for now to boot Linux successfully. commit <3d9a2f7e7c5e> ("arm64: dts: rockchip: rk3588: Add Edgeble Neu6 Model A SoM") Add support for Edgeble Neu6 Model A SoM. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28arm64: dts: rockchip: Add base DT for rk3588 SoCJagan Teki
This initial version supports CPU, dma, interrupts, timers, UART and SDHCI (everything necessary to boot Linux on this system on chip) as well as Ethernet, I2C, PWM and SPI. The DT is split into rk3588 and rk3588s, which is a reduced version (i.e. with less peripherals) of the former. commit <9fb232e9911f> (" arm64: dts: rockchip: Add base DT for rk3588 SoC") commit <d68a97d501f8> ("arm64: dts: rockchip: Add rk3588 pinctrl data") Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28arm: rockchip: Add ioc header for rk3588Jagan Teki
Add IOC unit header include for rk3588. Signed-off-by: Steven Liu <steven.liu@rock-chips.com> Signed-off-by: Joseph Chen <chenjh@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28dt-bindings: reset: add rk3588 reset definitionsJagan Teki
Add reset ID defines for rk3588. commit <0a8eb7dae617> ("dt-bindings: reset: add rk3588 reset definitions") Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28dt-bindings: power: Add power-domain header for rk3588Jagan Teki
Add power-domain header for RK3588 SoC from description in TRM. commit <67944950c2d0> ("dt-bindings: power: add power-domain header for rk3588") Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28ram: rockchip: Add rk3588 ddr driver supportJagan Teki
Add ddr driver for rk3588 to get the ram capacity. Co-developed-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28clk: rockchip: pll: Add pll_rk3588 type for rk3588Jagan Teki
Add RK3588 pll set and get rate clock support. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28clk: rockchip: Add rk3588 clk supportJagan Teki
Add clock driver support for Rockchip RK3588 SoC. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28dt-bindings: clk: Add dt-binding header for RK3588Jagan Teki
Add the dt-bindings header for the Rockchip RK3588, that gets shared between the clock controller and the clock references in the dts. commit <f204a60e545c> ("dt-bindings: clock: add rk3588 clock definitions") Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28arm: rockchip: Add grf header for rk3588Jagan Teki
Add GRF header for Rockchip RK3588. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28arm: rockchip: Add cru header for rk3588Jagan Teki
Add clock and reset unit header include for rk3588. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
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