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2023-05-11x86: Tidy up availability of string functionsSimon Glass
For now, just enable the fast-but-large string functions in 32-boot U-Boot proper only. Avoid using them in SPL. We cannot use then in 64-bit builds since we only have 32-bit assembly. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org>
2023-05-11x86: Support debug UART in 64-bit modeSimon Glass
The debug UART is already set up in SPL, so there is no need to do anything here. We must provide the (empty) function though. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11x86: samus: Drop EFI_LOADERSimon Glass
This adds a lot of code so that it cannot be built with the binary blobs. It is not used on this board. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11x86: ivybridge: Ensure LPC is available for GPIO baseSimon Glass
The bd82x6x_get_gpio_base() does not work if the LPC is not set up. Probe it early to avoid this problem. In chromebook_link64 this problem shows up as an inability to read the GPIO straps for the memory type. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11sf: Rename spi-nor-tiny functionsSimon Glass
The 'tiny' SPI nor functions have the same name as their big brothers, which can be confusing. Use different names so it is clear which version is in the image. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11sf: Guard against zero erasesizeSimon Glass
With tiny SPI flash the erasesize is 0 which can cause a divide-by-zero error. Check for this and return a proper error instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11binman: Support writing symbols for ucode etypesSimon Glass
Allow symbol writing in these cases so that U-Boot can find the position and size of U-Boot at runtime. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11dm: Emit the arch_cpu_init_dm() even only before relocationSimon Glass
The original function was only called once, before relocation. The new one is called again after relocation. This was not the intent of the original call. Fix this by renaming and updating the calling logic. With this, chromebook_link64 makes it through SPL. Fixes: 7fe32b3442f0 ("event: Convert arch_cpu_init_dm() to use events") Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11coreboot: Enable ms commandSimon Glass
This is useful when looking for tables in memory. Enable it for coreboot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11x86: nvme: coreboot: Enable NVMeSimon Glass
Enable support for NVMe storage devices. Update the driver to enable the bus master bit, since coreboot does not do that automatically. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11nvme: Enable PCI bus masteringSimon Glass
U-Boot sets up devices ready for use, but coreboot does not. Enable this so that NVMe works OK from coreboot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11x86: coreboot: Show unimplemented sysinfo tagsSimon Glass
Sometimes coreboot adds new tags that U-Boot does not know about. These are silently ignored, but it is useful to at least know what we are missing. Add a way to collect this information. For Brya it shows: Unimpl. 38 41 37 34 42 40 These are: LB_TAG_PLATFORM_BLOB_VERSION LB_TAG_ACPI_CNVS LB_TAG_FMAP LB_TAG_VBOOT_WORKBUF LB_TAG_TYPE_C_INFO LB_TAG_BOARD_CONFIG Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11x86: coreboot: Log function names and line numbersSimon Glass
Turn these options on to make it easier to debug things. Also enable dhrystone so we can get some measure of performance. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11x86: coreboot: Scan PCI after relocationSimon Glass
Enable this so that PCI devices can be used correctly without needing to do a manual scan. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11x86: coreboot: Document how to enable the debug UARTSimon Glass
This is not obvious so add a little note about how it works. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11x86: coreboot: Use a memory-mapped UARTSimon Glass
This is much more common on modern hardware, so default to using it. This does not affect the normal UART, but does allow the debug UART to work, since it uses serial_out_shift(), etc. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11pci: coreboot: Don't read regions when bootingSimon Glass
When U-Boot is the second-stage bootloader, PCI is already set up. We cannot read the regions from the device tree. There is no point anyway, since PCI devices have already been allocated according to the regions and it is not safe for U-Boot to make any changes. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Fixes: f2ebaaa9f38d ("pci: Handle failed calloc in decode_regions()") Tested-by: Christian Gmeiner <christian.gmeiner@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11x86: Allow locating the UART from ACPI tablesSimon Glass
When coreboot does not pass a UART in its sysinfo struct, there is no easy way to find it out. Since coreboot does not actually init the serial device when serial is disabled, it is not possible to make it add this information to the sysinfo table. Add a way to obtain this information from the DBG2 ACPI table, which is normally set up by coreboot. For now this only supports a memory-mapped 16550-style UART. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11x86: coreboot: Collect the address of the ACPI tablesSimon Glass
At present any ACPI tables created by prior-stage firmware are ignored. It is useful to be able to view these in U-Boot. Pick this up from the sysinfo tables and display it with the cbsysinfo command. This allows the 'acpi list' command to work when booting from coreboot. Adjust the global_data condition so that acpi_start is available even if table-generation is disabled. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11acpi: Move the table-finding functions into the libarySimon Glass
This is useful for other features. Move the function into library code so it can be used outside just the 'acpi' command. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11acpi: Create a new Kconfig for ACPISimon Glass
We have several Kconfig options for ACPI, but all relate to specific functions, such as generating tables and AML code. Add a new option which controls including basic ACPI library code, including the lib/acpi directory. This will allow us to add functions which are available even if table generation is not supported. Adjust the command to avoid a build error when ACPIGEN is not enabled. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11input: Flush the keyboard buffer before resetting itSimon Glass
If U-Boot is not the first-stage bootloader the keyboard may already be set up. Make sure to flush any data before trying to reset it. This avoids a long timeout / hang. Add some comments and a log category while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11x86: Adjust search range for sysinfo tableSimon Glass
Avoid searching starting at 0 since this memory may not be available, e.g. if protection against NULL-pointer access is enabled. The table cannot be there anyway, since the first 1KB of memory was originally used for the interrupt table and coreboot avoids it. Start at 0x400 instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11mtrr: Don't show an invalid CPU numberSimon Glass
When U-Boot did not do the MP init, we don't get an actual CPU number here. Skip printing it in that case. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-09Merge tag 'u-boot-rockchip-20230509' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-rockchip - Rockchip NFC driver update and dev addr pointer api update; - use standard dr_mode for usb driver; - rock pi boards dts update; - Add rk3566 Anbernic boards; - Misc fixes for drivers;
2023-05-09clk: rockchip: rk3588: add hardcoded assigned clocks valuesEugen Hristev
The CRU is being probed with a default set of assigned clocks, which are not implemented in the driver at all. Hence, when clk_set_defaults is called, it fails with ENOENT. This would not be a problem, as the CRU still handles all the required clocks, and the assigned clocks are default configs which are preprogrammed or not required for Uboot operations. However, the rockchip reset driver is being bound by the same DT node as CRU, as the reset driver has no DT node. But, when probing the reset node, it will call again the clk_set_defaults for the CRU node, and failing because of missing those specific clocks in the rk3588 clock driver. To avoid this, simply implement a basic set/get that will just return success and the default corresponding rate for the required assigned clocks. As those clocks were not supported in Uboot, not required for Uboot operations, there is no need to do any different kind of initialization. Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-09rockchip: handle peripheral as well as otg dr_modeJohn Keeping
The OTG port is identified by inspecting the "dr_mode" property which is expected to be "otg" for this port. But it will work just as well as a device controller when dr_mode is set to "peripheral", which may be required if the mode detection pin is not set up correctly and the device controller needs to be programmed to override this. Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-09rockchip: use standard dr_mode parsing functionJohn Keeping
Instead of duplicating the string values here, use usb_get_dr_mode() to handle the property lookup and converting the values to an enum. This is implemented with a switch in preparation for the next patch which adds extra handling for peripheral mode. Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-09arm: dts: rockchip: rock-3a: drop u-boot,spl-boot-orderFUKAUMI Naoki
use common one defined in rk356x-u-boot.dtsi. Signed-off-by: FUKAUMI Naoki <naoki@radxa.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-09arm: dts: rk356x: Makefile: sortFUKAUMI Naoki
sort alphanumerically. Signed-off-by: FUKAUMI Naoki <naoki@radxa.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-09doc: rockchip: update list of Radxa ROCK (Pi) 4 boardsFUKAUMI Naoki
add Radxa ROCK (Pi) 4 variants. Signed-off-by: FUKAUMI Naoki <naoki@radxa.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-09configs: rockchip: add Radxa ROCK 4C+FUKAUMI Naoki
add defconfig for Radxa ROCK 4C+. Signed-off-by: FUKAUMI Naoki <naoki@radxa.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-09arm: dts: rockchip: add Radxa ROCK 4C+FUKAUMI Naoki
Linux commit 246450344dad arm64: dts: rockchip: rk3399: Radxa ROCK 4C+ Add support for Radxa ROCK 4C+ SBC. Key differences of 4C+ compared to previous ROCK Pi 4. - Rockchip RK3399-T SoC - DP from 4C replaced with micro HDMI 2K@60fps - 4-lane MIPI DSI with 1920*1080 - RK817 Audio codec Also, an official naming convention from Radxa mention to remove Pi from board name, so this 4C+ is named as Radxa ROCK 4C+ not Radxa ROCK Pi 4C+. Signed-off-by: Stephen Chen <stephen@radxa.com> Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: FUKAUMI Naoki <naoki@radxa.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-09configs: rockchip: rock-pi-4: use dtb for ROCK Pi 4A instead of 4BFUKAUMI Naoki
rk3399-rock-pi-4a.dtb is enough for Radxa ROCK Pi 4A/B/A+/B+ and ROCK 4SE. Signed-off-by: FUKAUMI Naoki <naoki@radxa.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-09arm: dts: rockchip: rock-pi-4: sync with Linux 6.3FUKAUMI Naoki
sync dts{,i} files for Radxa ROCK Pi 4 series with Linux 6.3. because rk3399-rock-pi-4a.dts is enough for ROCK Pi 4A/B/A+/B+ and ROCK 4SE, delete dts{,i} for ROCK Pi 4B. Signed-off-by: FUKAUMI Naoki <naoki@radxa.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-09rockchip: rk3328: Add support for FriendlyARM NanoPi R2CTianling Shen
The NanoPi R2C is a minor variant of NanoPi R2S with the on-board NIC chip changed from rtl8211e to yt8521s, and otherwise identical to R2S. The device tree is taken from the kernel linux-next branch: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=004589ff9df5b75672a78b6c3c4cba93202b14c9 Signed-off-by: Tianling Shen <cnsztl@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-09reset: reset-rockchip: fix trivial line spacing alignmentEugen Hristev
Fix line spacing aligment in bind function Fixes: 760188c1aa5b ("rockchip: reset: support a (common) rockchip reset drivers") Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-09clk: rockchip: correct trivial typo in debug messageEugen Hristev
s/faile/failed in debug message Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-09pci: pcie_dw_rockchip: release resources on failing probeEugen Hristev
Implement a resource release mechanism on failing probe. Without this, a strange situation can happen e.g. when init port fails, or attempting to get the PHY fails, because the gpios have been requested first, and if the user tries to do 'pci enum' again, the driver will fail with 'can't find reset gpios' even if the gpios are there, just because they were blocked by a previous probe attempt. It is only natural to release the acquired resources if the probe fails, just for consistency if nothing else. This way on subsequent probe attempts, the user will get the same error message, and not something different that doesn't make sense. Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-08Prepare v2023.07-rc2v2023.07-rc2Tom Rini
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-05-08configs: Resync with savedefconfigTom Rini
Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
2023-05-08board: ti: am64x: Add support for AM64B SKJudith Mendez
The AM64x SR2.0 SK board uses "AM64B-SKEVM" as the EEPROM identifier. This board is similar to the AM64x SKEVM except that it has a new PMIC that will be enabled in the future and consequently could use a different device tree file in the future. For now we treat the board same as an AM64x SK. Signed-off-by: Judith Mendez <jm@ti.com> Acked-by: Andrew Davis <afd@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-05-08common: spl: spl: Remove video driver before u-boot properNikhil M Jain
Add method to remove video driver before loading u-boot proper. When bootstage changes from SPL to u-boot proper, noo method is called to remove video driver, and at u-boot proper if video driver is not enabled, the video driver starts displaying garbage on the screen, because there is no reserved space for video and the frame buffer gets u-boot proper data written. Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
2023-05-08board: ti: am62x: evm: Add necessary functions to call splash screenNikhil M Jain
To enable splash screen on AM62x at a53 SPL setup DRAM, set page table, enable cache to allow copying of bmp image to frame buffer and display it using splash_display. Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
2023-05-08board: ti: am62x: am62x: Change splashimage and splashsourceNikhil M Jain
Change splashimage which is bmp image loadaddr to 0x80200000 since stack is situated at 0x80477660 as splash framework requires bmp image to be present above stack. Change splashsource to sf to support loading bmp image from ospi flash memory. Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
2023-05-08configs: am62x_evm_a53_defconfig: Changes in memory to support SPL splash screenNikhil M Jain
To enable splash at A53 SPL, need to do memory map changes which involves locate stack above malloc and have enough space to load bmp image above stack. To load a 1920X1200 image a minimum of 8.8MB space is needed, to support it move malloc down to 0x80b80000 from 0x80480000 and bss to 0x80c80000 to have 1MB buffer between malloc and BSS. Observed SPL size 195KB, CONFIG_SPL_SIZE_LIMIT set to 256KB. Observed stack size 1904Bytes, CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK set to 2KB. CONFIG_SPL_SYS_REPORT_STACK_F_USAGE config sets stack above the malloc and reports for stack overflow. Memory map at A53 SPL before splash screen 0x80000000+---------------------+ | Empty 512 KB | | | 0x80080000+---------------------+ | Text Base | | 352 KB | | | 0x800D8000+---------------------+ | | | | | Empty 3.6MB | | | | | 0x80477660+---------------------+ | Stack 2 KB | 0x80477e60+---------------------+ | GD 416 Bytes | 0x80478000+---------------------+ | Malloc 352 KB | | | 0x80480000+---------------------+ | | | | | | | | | Empty 5.5 MB | | | | | | | | | 0x80a00000+---------------------+ | | | BSS 512 KB | | | 0x80a80000+---------------------+ | | | | | | | | | Empty 5.5 MB | | | | | | | | | 0x81000000+---------------------+FIT Image load address New memory map with splash screen at SPL 0x80000000+---------------------+ | Empty 512 KB | | | 0x80080000+---------------------+ | Text Base | | 352 KB | | | 0x800D8000+---------------------+ | Empty 1.1MB | | | 0x80200000+---------------------+ | | | | | | | BMP Image Load | | | | 9.4 MB | | | | | | | | | | | | | 0x80b77660+---------------------+ | Stack 2KB | 0x80b77e60+---------------------+ | GD 416 Bytes | 0x80b78000+---------------------+ | | | Malloc 352KB | 0x80b80000+---------------------+ | | | Empty 1 MB | | | 0x80c80000+---------------------+ | BSS 512 KB | | | 0x80d00000+---------------------+ | | | | | Empty 3.0 MB | | | | | | | 0x81000000+---------------------+FIT Image load addressi Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
2023-05-08btrfs: fix offset when reading compressed extentsDominique Martinet
btrfs_read_extent_reg correctly computed the extent offset in the BTRFS_COMPRESS_NONE case, but did not account for the 'offset - key.offset' part correctly in the compressed case, making the function read incorrect data. In the case I examined, the last 4k of a file was corrupted and contained data from a few blocks prior, e.g. reading a 10k file with a single extent: btrfs_file_read() -> btrfs_read_extent_reg (aligned part loop, until 8k) -> read_and_truncate_page -> btrfs_read_extent_reg (re-reads the last extent from 8k to the end, incorrectly reading the first 2k of data) This can be reproduced as follow: $ truncate -s 200M btr $ mount btr -o compress /mnt $ pat() { dd if=/dev/zero bs=1M count=$1 iflag=count_bytes status=none | tr '\0' "\\$2"; } $ { pat 4K 1; pat 4K 2; pat 2K 3; } > /mnt/file $ sync $ filefrag -v /mnt/file File size of /mnt/file is 10240 (3 blocks of 4096 bytes) ext: logical_offset: physical_offset: length: expected: flags: 0: 0.. 2: 3328.. 3330: 3: last,encoded,eof $ umount /mnt Then in u-boot: => load scsi 0 2000000 file 10240 bytes read in 3 ms (3.3 MiB/s) => md 2001ff0 02001ff0: 02020202 02020202 02020202 02020202 ................ 02002000: 01010101 01010101 01010101 01010101 ................ 02002010: 01010101 01010101 01010101 01010101 ................ (02002000 onwards should contain '03' pattern but went back to 01, start of the extent) After patch, data is read properly: => md 2001ff0 02001ff0: 02020202 02020202 02020202 02020202 ................ 02002000: 03030303 03030303 03030303 03030303 ................ 02002010: 03030303 03030303 03030303 03030303 ................ Note that the code previously (before commit e3427184f38a ("fs: btrfs: Implement btrfs_file_read()")) did not split that read in two, so this is a regression even if the previous code might not have been handling offsets correctly either (something that booted now fails to boot) Fixes: a26a6bedafcf ("fs: btrfs: Introduce btrfs_read_extent_inline() and btrfs_read_extent_reg()") Signed-off-by: Dominique Martinet <dominique.martinet@atmark-techno.com> Reviewed-by: Qu Wenruo <wqu@suse.com>
2023-05-08Merge https://source.denx.de/u-boot/custodians/u-boot-marvellTom Rini
- cmd: tlv_eeprom: Misc cleanups & improvements (Josua)
2023-05-08cmd: tlv_eeprom: enable 'dev' subcommand before 'read'Josua Mayer
Move the handler for "tlv_eeprom dev X" command to the beginning of do_tlv_eeprom, to allow using it before issuing a "read" command for currently selected eeprom. Also remove the check if eeprom exists, since that can only work after the first execution of read_eeprom triggered device lookup. Instead accept values up to the defined array size (MAX_TLV_DEVICES). Signed-off-by: Josua Mayer <josua@solid-run.com> Reviewed-by: Stefan Roese <sr@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Baruch Siach <baruch@tkos.co.il> Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
2023-05-08cmd: tlv_eeprom: handle -ENODEV error from read_eeprom functionJosua Mayer
When tlv eeprom does not exist, return error code instead of quietly making up tlv structure in memory. Signed-off-by: Josua Mayer <josua@solid-run.com> Reviewed-by: Stefan Roese <sr@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Baruch Siach <baruch@tkos.co.il> Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
generated by cgit v1.2.3 (git 2.0.4) at 2025-11-02 20:53:18 +0000