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2021-09-17clk: ti: k3: Update driver to account for divider flagsSuman Anna
The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-09-17clk: ti: k3-pll: Change DIV_CTRL programming to read-modify-writeDave Gerlach
There are three different divider values in the DIV_CTRL register controlled by the k3-pll driver. Currently the ti_pll_clk_set_rate function writes the entire register when programming plld, even though plld only resides in the lower 6 bits. Change the plld programming to read-modify-write to only affect the relevant bits for plld and to preserve the other two divider values present in the upper 16 bits, otherwise they will always get set to zero when programming plld. Fixes: 0aa2930ca192 ("clk: add support for TI K3 SoC PLL") Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-09-17arm: mach-k3: Add note to auto-generated filesDave Gerlach
Add a note to the automatically generated clk-data and dev-data files for j721e and j7200 to indicate that they are in fact auto-generated and should not be hand edited. Also adjust TI URL to use https instead of http and also add an empty line before first header inclusion. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-09-17arm: mach-k3: j7200: Fix clk-data parenting for postdiv PLL clocksSuman Anna
The TI K3 Fractional PLLs use two programmable POSTDIV1 and POSTDIV2 divisors to generate the final FOUTPOSTDIV clock. These are in sequence with POSTDIV2 following the POSTDIV1 clock. The current J7200 clock data has the POSTDIV2 clock as the parent for the POSTDIV1 clock, which is opposite of the actual implementation. Fix the data by simply adjusting the register bit-shifts. The Main PLL1 POSTDIV clocks were also defined incorrectly using Main PLL0 register values, fix these as well. Fixes: 277729eaf373 ("arm: mach-k3: Add platform data for j721e and j7200") Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-09-17arm: mach-k3: j721e: Fix clk-data parenting for postdiv PLL clocksSuman Anna
The TI K3 Fractional PLLs use two programmable POSTDIV1 and POSTDIV2 divisors to generate the final FOUTPOSTDIV clock. These are in sequence with POSTDIV2 following the POSTDIV1 clock. The current J721E clock data has the POSTDIV2 clock as the parent for the POSTDIV1 clock, which is opposite of the actual implementation. Fix the data by simply adjusting the register bit-shifts. The Main PLL1 POSTDIV clocks were also defined incorrectly using Main PLL0 register values, fix these as well. Fixes: 277729eaf373 ("arm: mach-k3: Add platform data for j721e and j7200") Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-09-17arm: mach-k3: common: Add a release_resources_for_core_shutdown() stubSuman Anna
Add a weak release_resources_for_core_shutdown() stub implementation that can be overridden by actual implementation if a SoC supports that function. Signed-off-by: Suman Anna <s-anna@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com>
2021-09-17firmware: ti_sci: Include linux/err.h in ti_sci_protocol.hSuman Anna
The common TI SCI header file uses some macros from err.h and these get exercised when CONFIG_TI_SCI_PROTOCOL is not defined. Include the linux/err.h header file in this header file directly rather than relying on source files to include it to eliminate any potential build errors. While at this, reorder the existing header file include to the beginning of the file. Signed-off-by: Suman Anna <s-anna@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com>
2021-09-17MAINTAINERS: POWERPC MPC8XX: Update email addressChristophe Leroy
Our email addresses have changed from @c-s.fr to @csgroup.eu Update entry in MAINTAINERS Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
2021-09-15Merge branch 'rpi-next' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-raspberrypi Ivan's patch fixes a kernel warning when booting RPi2, as the firmware already provides a frambebuffer node. Marek's patch fixes random crashes on 32 bit RPi4 with newer firmware. My SMBIOS patchesfixes an issue that show up with e4f8e543f1 ("smbios: Drop the unused Kconfig options"). Basically the SMBIOS table broke and wasn't readable anymore.
2021-09-15rpi: Conditionally add simple-framebuffer nodeIvan T. Ivanov
It appears that RPi firmware has already added framebuffer node under /chosen, at least on RPi 2 versions. So check for this and don't add duplicate node. Signed-off-by: Ivan T. Ivanov <iivanov@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2021-09-15ARM: bcm283x: change the virtual address of the XHCI PCI device baseMarek Szyprowski
Move the XHCI PCI device base up in the virtual address space. This fixes initialization failure observed with newer Raspberry Pi firmware, later than 63b1922311 ("firmware: arm_loader: Update armstubs with those from PR 117). It looks that chosing 0xff800000 as the XHCI PCI device base conflicts with the updated ARM/VideoCore firmware. This also requires to reduce the size of the mapped PCI device region from 8MiB to 4MiB to fit into 32bit address space. This is still enough for the XHCI PCI device. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Nicolas Saenz Julienne <nsaenz@kernel.org> Tested-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2021-09-15configs: rpi: Enable SMBIOS sysinfo driverMatthias Brugger
Enable this driver to allow U-Boot to get SMBIOS table information from a device tree node. Signed-off-by: Matthias Brugger <mbrugger@suse.com> Acked-by: Fabian Vogt <fvogt@suse.com>
2021-09-15arm: dts: bcm283x: Add minimal smbios informationMatthias Brugger
At present SMBIOS tables are empty, which breaks some use-cases that rely on that. Add some minimal information to fulfill this. Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2021-09-14Prepare v2021.10-rc4v2021.10-rc4Tom Rini
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-09-14configs: Resync with savedefconfigTom Rini
Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
2021-09-14image: Avoid erroneous double byte-swap in CRC valueAlexandru Gagniuc
The hash algorithm selection was streamlined in commit 92055e138f28 ("image: Drop if/elseif hash selection in calculate_hash()"). Said commit kept the call to cpu_to_uimage() to convert the CRC to big endian format. This would have been correct when calling crc32_wd(). However, the ->hash_func_ws member of crc32 points to crc32_wd_buf(), which already converts the CRC to big endian. On a little endian host, doing both conversions results in a little-endian CRC. This is incorrect. To remedy this, simply drop the call to cpu_to_uimage(), thus only doing the byte-order conversion once. Fixes: 92055e138f28 ("image: Drop if/elseif hash selection in calculate_hash()") Tested-by: Tom Rini <trini@konsulko.com> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2021-09-14Merge branch '2021-09-14-assorted-fixes'Tom Rini
- Assorted bugfixes
2021-09-14image: rsa: Move padding_algos to linker listsAlexandru Gagniuc
We are not guaranteed to have the padding_pkcs_15_verify symbol since commit 92c960bc1d ("lib: rsa: Remove #ifdefs from rsa.h"), and commit 61416fe9df ("Kconfig: FIT_SIGNATURE should not select RSA_VERIFY") The padding_algos only make sense with RSA verification, which can now be disabled in lieu of ECDSA. In fact this will lead to build failures because of the missing symbol mentioned earlier. To resolve this, move the padding_algos to a linker list, with declarations moved to rsa_verify.c. This is consistent with commit 6909edb4ce ("image: rsa: Move verification algorithm to a linker list") One could argue that the added #ifdef USE_HOSTCC is ugly, and should be hidden within the U_BOOT_PADDING_ALGO() macro. However, this would be inconsistent with the "cryptos" list. This logic for was not previously explored: Without knowledge of the U_BOOT_PADDING_ALGO() macro, its use is similar to something being declared. However, should #ifndef USE_HOSTCC be part of the macro, it would not be obvious that it behaves differently on host code and target code. Having the #ifndef outside the macro makes this obvious. Also, the #ifdef is not always necessary. For example ecda-verify makes use of U_BOOT_CRYPTO_ALGO() without any accompanying #ifdefs. The fundamental issue is a lack of separation of host and target code in rsa_verify. Therefore, the declaration of a padding algo with the external #ifdef is more readable and consistent. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2021-09-14pinctrl: fix typoYuan Fang
fix typo in pinctrl Kconfig file to avoid git commit failure on some commit hooks check. Signed-off-by: Yuan Fang <fangyuanseu@gmail.com>
2021-09-14lib: fix typos in KconfigOleksandr Suvorov
There are trivial typos in the Kconfig file. Fixed them. Also, fixed grammar in the descriptions with typos. Fixes: d56b4b1974 ("configs: Migrate RBTREE, LZO, CMD_MTDPARTS, CMD_UBI and CMD_UBIFS") Fixes: 7264f2928b ("spl: fit: Eanble GZIP support for image decompression") Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-09-14lib/rsa: don't use NULL as key_idHeinrich Schuchardt
If keydir is not provided but name is we want to use name as key_id. But with the current coding name is only used on its own if it is NULL and keydir is provided which never occurs. Fixes: 824ee745fbca ("lib/rsa: Use the 'keyfile' argument from mkimage") Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-09-13Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxiTom Rini
- a fix for U-Boot 2021.10 to bring back MMC boot on older boards.
2021-09-14sunxi: mmc: A20: Fix MMC optimisationAndre Przywara
Some SoCs (as seen on A20) seem to misreport the MMC FIFO level if the FIFO is completely full: the level size reads as zero, but the FIFO_FULL bit is set. We won't do a single iteration of the read loop in this case, so will be stuck forever. Check for this situation and use a safe minimal FIFO size instead when we hit this case. This fixes MMC boot on A20 devices after the MMC FIFO optimisation (9faae5457f52). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-09-13Merge branch '2021-09-09-finish-pre-DM_PCI-removal'Tom Rini
- Finish removing the non-DM_PCI legacy code.
2021-09-13pci: Drop DM_PCISimon Glass
This option has not effect now. Drop it, using PCI instead where needed. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-13pci: Drop PCI_INDIRECT_BRIDGESimon Glass
This does not work with driver model so can be removed. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-13net: Drop DM_PCI check from designware driverSimon Glass
We don't need this check anymore since when PCI is enabled, driver model is always used. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-13pci: acpi: Drop DM_PCI check from ahciSimon Glass
We don't need these checks anymore since when PCI is enabled, driver model is always used. Drop them. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-13pci: Drop DM_PCI check from fdtdecSimon Glass
We don't need this check anymore since when PCI is enabled, driver model is always used. Sadly this doesn't work with nds32 for some reason to do with the toolchain. Add a work-around for that. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-13pci: Drop old code from header fileSimon Glass
We don't need this code anymore since when PCI is enabled, driver model is always used. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-13ppc: Remove UCP1020 boardSimon Glass
This board has not been converted to CONFIG_DM_PCI by the deadline. Remove it. Note that we have to add CONFIG_SPIFLASH to scripts/config_whitelist.txt because it's not really migrated at this point. Acked-by: Michael Durrant <mdurrant@arcturusnetworks.com> Acked-by: Oleksandr Zhadan <oleks@arcturusnetworks.com> Acked-by: Oleksandr Zhadan and Michael Durrant <arcsupport@arcturusnetworks.com> Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Handle CONFIG_SPIFLASH differently and delete Kconfig file] Signed-off-by: Tom Rini <trini@konsulko.com>
2021-09-13Merge tag 'mmc-2021-9-13' of https://source.denx.de/u-boot/custodians/u-boot-mmcTom Rini
Support using mmc command for enumerating mmc card in a given mode Fix device_remove in mmc Fix switch issue with send_status disabled Drop 1ms delay in fsl_esdhc command sending Revert "mmc: sdhci: set to INT_DATA_END when there are data"
2021-09-13mmc: fsl_esdhc: remove 1ms sleep in esdhc_send_cmd_common()Michael Walle
Since the beginning of this driver which was initially for the MPC8379 and MPC8536 SoCs, there is this spurious 1ms delay. According to the comment it should actually be only 8 clock cycles. Esp. during EFI block transfers, this 1ms add up to a significant delay and slows down EFI boot. I couldn't find any mention in the MPC8536 that there should be a delay of 8 clock cycles between commands. The SD card specification mentions that the clock has to be left enabled for 8 cycles after a command or response. But I don't see how this delay will help with this. Go ahead and just remove it. If there will ever be any regression we can introduce a compile time flag, but for now I'd like to keep it simple. In the split off imx driver this delay was also removed in commit 9098682200e6 ("mmc: fsl_esdhc_imx: remove the 1ms delay before sending command"). Signed-off-by: Michael Walle <michael@walle.cc>
2021-09-12Merge tag 'efi-2021-10-rc4-2' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-efi Pull request for efi-2021-10-rc4-2 Documentation: * improve documentation of U-Boot for /config DT node * integrate bloblist documentation UEFI: * correct usage of EFI_CALL() * code tidy up
2021-09-11Merge branch '2021-09-10-assorted-TI-updates'Tom Rini
- A number of TI platform bugfixes
2021-09-11efi_loader: simplify efi_watchdog_timer_notify()Heinrich Schuchardt
We can call do_reset() directly without invoking the UEFI API. This decreases the code size. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-09-11efi_loader: eliminate EFI_CALL() in nvedit_efi.cHeinrich Schuchardt
Reduce the code size by avoiding using the external UEFI API and using our internal functions instead. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-09-11efi_loader: Remove incorrect calls of EFI_CALL in TCG2Ilias Apalodimas
There is two unneeded EFI_CALL references in tcg2_measure_pe_image(). The first one in efi_search_protocol() and the second on in the device path calculation. The second isn't even a function we should be calling, but a pointer assignment, which happens to work with the existing macro. While at it switch the malloc call to a calloc, remove the unnecessary cast and get rid of an unneeded if statement before copying the device path Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-09-11efi_loader: require CONFIG_BLKHeinrich Schuchardt
The move to driver model should by now be completed. To be able to remove pre-driver model code from our block IO code require CONFIG_BLK=y for UEFI support. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-09-11efi_loader: boot_service_capability_min should be capitalizedMasahisa Kojima
boot_service_capability_min is constant, it should be capitalized. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-09-11doc: Complete the list of available runtime-config optionsSimon Glass
The current list is missing a few items. Add them. Reviewed-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-09-11doc: Tidy up the bindings for the config/ nodeSimon Glass
Sort these and add a type so it is clear how to set the value. Add a note about usage to the top. Correct the 'no-keyboard' binding which is missing a prefix. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-09-11bloblist: Move to rST formatSimon Glass
Move this documentation to the new format. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2021-09-11doc: board: toradex: fix file namesOleksandr Suvorov
Fix the documentation file names: s/apalix/apalis/. Fixes: e98ea49a0e ("toradex: MAINTAINERS: entries for new reST docs") Fixes: 3730106cf0 ("doc: board: apalis-imx8x: add documentation") Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io> Reviewed-by: Igor Opaniuk <igor.opaniuk@foundries.io> Acked-by: Francesco Dolcini <francesco.dolcini@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-09-10configs: j72*_evm: Define the buffer sizes for dfuAswath Govindraju
On J721e R5 SPL, dfu buffer for loading sysfw.itb image gets allocated before DRAM gets initialized. So, the buffer gets allocated in MCU L3 RAM. The current buffer size to be allocated is 256KB and the available total heap memory is 0x70000 (448KB). This leads to NOMEM errors during allocation. In other cases when constraints such as above are not present fix the size of buffers to the sector size in OSPI for proper functioning. Also, if CONFIG_SYS_DFU_DATA_BUF_SIZE is defined and CONFIG_SYS_DFU_MAX_FILE_SIZE is not defined then the max file size for dfu transfer is defined as CONFIG_SYS_DFU_DATA_BUF_SIZE. Fix these by setting appropriate buffer sizes in their respective defconfig files and defining the max file size as 8 MB which is the default dfu buffer size. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2021-09-10environment: ti: k3_dfu: Increase the size allocated for bootloader images ↵Aswath Govindraju
in dfu_alt_info_ram The size of u-boot.img is above 1MB and that of tispl.bin is close to 1MB, in case of j721e. Therefore, increase the sizes allocated for tispl.bin and u-boot.img to 2 MB and 4 MB respectively, in dfu_alt_info_ram environment variable. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2021-09-10arm: dts: k3-j721e-r5-*.dts: Fix clock-names property in the usb0 instanceAswath Govindraju
In the cdns3 usb driver, the clock name looked for is ref. Therefore, fix the clock-names property in usb0 instance for proper initialization of cdns3 usb gadget driver. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2021-09-10ARM: dts: Fix node status to "okay" on TI boardsRoger Quadros
As per Device Tree Specification [1], the status parameter of nodes can be "okay", "disabled", etc. "ok" is not a valid parameter. U-boot Driver Model does not recognize status="ok" either and treats the node as disabled. [1] https://github.com/devicetree-org/devicetree-specification/releases/tag/v0.3 Signed-off-by: Roger Quadros <rogerq@kernel.org> Reviewed-by: Nishanth Menon <nm@ti.com>
2021-09-10tools: k3_fit_atf: Fix DM binary FIT load addressesSuman Anna
The DM binary runs on the MCU R5F Core0 after R5 SPL on J721E and J7200 SoCs. The binary is built alongside the TFA, OPTEE and A72 SPL binaries and included in the tispl.bin FIT image. The R5 SPL loads the DM binary at 0xA0000000 address, based on the value used in the FIT image build script. The DM binary though is an ELF image and not a regular binary file, and so is processed further to load the actual program segments using the U-Boot's standard ELF loader library. The DM binary does leverage a certain portion of DDR for its program segments, and typically reserves 16 MB of DDR at 0xA0000000 with the 1st MB used for IPC between Linux and the remote processor, and remaining memory for firmware segments. This can cause an incomplete loading of the program segments if the DM binary is larger than 1 MB, due to overlap of the initial loaded binary and the actual program segments. Fix this by using the address 0x89000000, which matches the current "addr_mcur5f0_0load" env variable used by R5 SPL before the DM firmware inclusion into the tispl.bin. Fixes: df5363a67f35 ("tools: k3_fit_atf: add DM binary to the FIT image") Signed-off-by: Suman Anna <s-anna@ti.com>
2021-09-10arm: dts: k3-am642-evm-u-boot: Add u-boot, dm-spl tag in the pinmux node of mmc1Aswath Govindraju
Add u-boot,dm-spl tag in the pinmux device tree node, required for MMCSD1 subsystem. Fixes: b6059ddc45b9 ("arm: dts: k3-am642: Add r5 specific dt support") Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
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