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This adds the early A523 clock setup code, for the basic peripheral PLL
and the basic bus clocks (APB/AHB). This is quite close to the existing
H6 and H616 clock code, so this shares the same file. A few bits and bobs
are different, though, so filter for the A523 in a few occasions.
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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The cpu_sunxi_ncat2.h header file contains addresses of some peripherals
that are needed for the SPL, for chips that belong to the "NCAT2"
generation.
The Allwinner A523 is a member of this group, but a few addresses
differ, and we need a few more addresses, for playing with the core
reset, for instance.
Add the new addresses needed for the A523 and guard existing definitions
that conflict with that new chip.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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The X-Powers AXP323 is very close sibling to the AXP313A, only that it
adds support for dual-phasing the first two DC/DC converters.
We do not really care about this particular feature, so just add the new
compatible string and tie it to the existing AXP313A support code.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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The Allwinner A523 SoC has a slightly changed mod clock, where the P
factor, formerly a shift value, is now a second divider value.
Also the input clock is not PLL_PERIPH0 (600MHz) anymore, but
PLL_PERIPH0_400M (for MMC0/1), so adjust the input rate calculation
accordingly. MMC2 has a different set of parents, so the input clock
is 800 MHz there.
Adjust for all of this.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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The new DT pinctrl binding would allow us to read the pinmux values from
the DT, but it is actually easier to just continue with hardcoding the
mux values in the driver, and matching them against the "function" name.
Add the values for the primary and secondary pin controller on the A523.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Add a clock driver for the PRCM clock controller on the Allwinner A523
family of SoCs, often also used with an "r" prefix or suffix.
This just describes the clock gates and reset lines for the few devices
that we would need, most prominently the R_I2C device for the PMIC.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Add a clock driver for the main clock controller on the Allwinner A523
family of SoCs.
As usual, this just describes the clock gates and reset lines for the
few device that U-Boot cares about: USB, Ethernet, MMC, I2C, SPI.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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The watchdog in the Allwinner A523 SoC differs a bit from the one in the
previous SoCs: it lives in a separate register frame, so no longer
inside some timer device, and it manages to shuffle around some
registers a bit. But it also conveniently adds a direct reset
functionality, so we don't need to use a dummy timeout period.
Avoid introducing a new MMIO register frame C struct, but just define
the one needed register offset as a macro. Then just trigger this new
direct reset functionality in the A523 specific reset_cpu()
implementation.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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The Allwinner A523 features 8 CPU cores, organised in two clusters, both
driven by separate PLLs. Also there is the DSU PLL, which clocks the
hardware that connects the cores to the rest of the system.
And while the PLL registers itself are very similar, they are located in
a separate register frame, outside the main CCU, and also the register
controlling the CPU clock source (mux) is different.
Provide a separate function that reparents the two clusters and the DSU,
while their PLLs are programmed. For the actual PLL programming, we rely
on the existing shared routine.
The selection between the new A523 routine and the existing code is made
with C if statements, but since the choice is effectively made at compile
time already, the compiler optimises away the other code paths, leaving
just the one required function in.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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When we program the CPU PLL, we need to switch the CPU clock source away
from the PLL temporarily, then switch it back, once the PLL has
stabilised.
The CPU CLK register will be different on the A523, so move the current
code into a separate function, to allow using a different version of
that later for the A523.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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The SPL initial clock setup code for the Allwinner H6 and H616 SoCs uses
a simple CPU PLL setup routine, which programs all register bits at once,
then waits for the LOCK bit to clear.
The manual suggests to follow a certain procedure for bringing up any
PLLs, which involves several register writes, one at a time, and some
delays. Also the H616 and the new A523 require some tiny changes in this
sequence, and the different SoCs also feature some extra bits here and
there, which we should not just clear.
So factor out the PLL setup routine, and make it follow the manual's
suggestion. This will read the PLL register at the beginning, then tweak
the bits we need to manipulate, and writes the register several times on
the way. This allows to cover the specific bits for different SoCs.
Besides improving the reliability of the PLL setup, this helps with the
A523, which requires *three* CPU PLLs to be programmed.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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The Allwinner PLLs share most of their control bits, they differ mostly
in the factors and dividers.
Drop the PLL specific definition of those common bits, and use one
shared macro, for all PLLs.
This requires changing the users in the SPL clock and DRAM code.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request efi-2025-10-rc1
CI: https://source.denx.de/u-boot/custodians/u-boot-efi/-/pipelines/27176
Documentation:
* update FIT signature testing instructions
* describe defconfigs for AM69-SK
UEFI:
* provide unit test for system table pointer
* efi_realloc() must check efi_alloc() return value
* correct EFI_DEBUG_TABLE_ENTRY_SIZE
* avoid NULL dereference in ESRT creation tests
* add missing check in FMP.GetImageInfo()
* rename lib/efi to lib/efi_client
* rename CONFIG_EFI to CONFIG_EFI_CLIENT
* create a new CONFIG_EFI
* update maintainers for EFI_CLIENT
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Update the FIT signature testing instructions to use the pytest suite instead of
the old vboot_test.sh script.
Signed-off-by: Enric Balletbo i Serra <eballetbo@kernel.org>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
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The UEFI 2.11 specification, chapter 23.1.3 requires
EFI_FIRMWARE_MANAGEMENT_PROTOCOL.GetImageInfo() to return
EFI_INVALID_PARAMETER if *ImageInfoSize is not too small
and ImageInfo is NULL.
Fixes: f27c20148511 ("efi_loader: add firmware management protocol for FIT image")
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
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The code foresees that parameters descriptor_size and descriptor_count
might be NULL and then dereferences them without further check.
The size check must take into account the descriptor count.
ImageInfo might be NULL. In this case we must not dereference it.
Fixes: 4ac6041c3cbf ("efi: ESRT creation tests")
Addresses-Coverity-ID: CID 569497: Null pointer dereferences (FORWARD_NULL)
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
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With the current code we allocate to little memory when adding entries to
the EFI_DEBUG_INFO_TABLE and we fail to correctly move entries when an
entry is removed.
EFI_DEBUG_TABLE_ENTRY_SIZE must be the size of an entry in the
EFI_DEBUG_INFO_TABLE, not the size of a pointer.
Fixes: 146546138af5 ("efi: add EFI_DEBUG_IMAGE_INFO for debug")
Addresses-Coverity-ID: CID 569498: Code maintainability issues (SIZEOF_MISMATCH)
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
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Avoid copying to NULL if out of memory.
Fixes: 3c08df58cc43 ("lib: efi_loader: efi_memory.c: add efi_realloc() for realloc memory")
Addresses-Coverity-ID: 569499: Null pointer dereferences (NULL_RETURNS)
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
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Enhance the debug support unit test.
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
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The J784S4 and AM69 Platforms page only details the defconfigs for
J784S4.
Mention the ones needed for AM69-SK as well, to guide users on how to
build for that board.
Signed-off-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
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The 'EFI PAYLOAD' entry really refers to the EFI loader and EFI APP
refers to the app and the payload.
Rename 'EFI PAYLOAD' to 'EFI LOADER' and 'EFI APP' to 'EFI CLIENT'
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
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Create a Kconfig which indicates that EFI functionality is in use,
either as a client (EFI app / stub) or provider (EFI loader). This will
make it easier to share code between these two parts of U-Boot
Signed-off-by: Simon Glass <sjg@chromium.org>
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The generic name 'EFI' would be more useful for common EFI features. At
present it just refers to the EFI app and stub, which is confusing.
Rename it to EFI_CLIENT
Signed-off-by: Simon Glass <sjg@chromium.org>
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This directory was created when U-Boot gained the ability to run as an
EFI app in 2015. Since then the EFI-loader feature has been added.
The code in lib/efi is not actually used by the loader, so the name is
confusing.
Rename the directory to efi_client to indicate that it includes files
just for U-Boot being a client of EFI, i.e. the EFI app and stub.
Signed-off-by: Simon Glass <sjg@chromium.org>
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- Update to Ubuntu "Jammy" 20250714 tag
- Update to current Dockerfile which brings us QEMU 10.0.2 and newer
coreboot and pulls in lz4 via the non-legacy package name.
Signed-off-by: Tom Rini <trini@konsulko.com>
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This series from myself brings CI up to using QEMU 10.0.2 for platforms.
We need to disable one test for now while a report to upstream QEMU is
resolved and also need to now update coreboot in order to be able to
build a version of it non-interactively (source locations have changed).
Link: https://lore.kernel.org/r/20250716001539.2483390-1-trini@konsulko.com
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At this point there's problems rebuilding coreboot-24.08 without manual
intervention. Let us upgrade to a newer version.
Signed-off-by: Tom Rini <trini@konsulko.com>
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As QEMU 10.0.2 is the current release, update to that so that we can
update other features within CI.
Signed-off-by: Tom Rini <trini@konsulko.com>
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Changes in upstream QEMU have lead to this specific configuration of the
sifive_unleashed platform not working in QEMU. Until this can be
root caused and resolved, disable this test for now.
Link: https://gitlab.com/qemu-project/qemu/-/issues/2945
Signed-off-by: Tom Rini <trini@konsulko.com>
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- Enhanced e850-96 support
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Now that USB is enabled on the E850-96 board, DFU and fastboot tools are
functional and can be used to flash images to eMMC. Update the E850-96
documentation accordingly and describe flashing to User Data Area and
Boot HW Partition of eMMC using fastboot and DFU tools.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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Make it possible to update E850-96 firmware binaries using EFI Capsule
Update mechanism. For example, to update the U-Boot binary, the capsule
file can be generated like this:
$ ./tools/mkeficapsule --index 4 \
--guid 629578c3-ffb3-4a89-ac0c-611840727779 \
u-boot.bin capsule4.bin
The resulting 'capsule4.bin' should be copied to ESP partition (in
/boot/efi/EFI/UpdateCapsule/ directory). Then after reboot U-Boot will
update the 'bootloader' area in eMMC Boot Partition A (boot0) and remove
the capsule file, by EFI boot manager executed as a part of Standard
Boot:
Applying capsule capsule4.bin succeeded.
Reboot after firmware update.
The kernel will also expose the ESRT table information via SysFS in
/sys/firmware/efi/esrt/entries.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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Now that USB phy and dwc3 glue layer was added for Exynos850, USB gadget
is functional on E850-96 board. Enable next features to make it useful:
- Exynos850 USB PHY driver (needed for all USB functions)
- dwc3 generic driver
- USB gadget
- CONFIG_DM_USB_GADGET: needed for DWC3 glue layer to instantiate the
peripheral driver, i.e. dwc3_generic_peripheral_probe()
- USB VID and PID
- DFU
- Fastboot (including flashing to eMMC boot partitions)
As all Exynos firmware binaries (including U-Boot) are contained in eMMC
boot partition A (mmc0boot0), because that's where Boot ROM code jumps,
it might be useful to be able to flash that area with fastboot. Other
more fine grained choices for updating the firmware would be DFU and EFI
Capsule Update mechanism.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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"fastboot flash" tries to malloc 8 MiB buffer after receiving data over
USB and trying to write it to eMMC. Right now only 8.12 MiB malloc is
available for E850-96 overall, which leads to this issue:
Malloc failed for: CHUNK_TYPE_RAW
Fix it by increasing malloc pool size from 8.12 MiB up to 32 MiB, like
it's done in many other boards using fastboot.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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Matches downstream Android-Q partition table created by flashing the
modified gpt.img [1], with added ESP partition (EFI System Partition).
It's an A/B slotted Android partition table, so it's possible to boot
Android from this table using Android GBL EFI app. Tested using
AOSP/main images for E850-96 with booting via GBL app.
[1] https://gitlab.com/Linaro/96boards/e850-96/tools/gpt/-/blob/master/gpt_layout_uboot_q_ab
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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Add 'dfu_alt_info' environment variable which contains:
- Linux eMMC partitions ('esp' and 'rootfs')
- eMMC Boot Partition A layout, where all the firmware reside
It makes it possible to update the bootloader (U-Boot). All sizes in
'dfu_alt_info' are given in 512B blocks (LBA). eMMC size is 58.2 GiB.
The eMMC Boot Partition A (mmc0boot0) layout looks like this:
boot0 partition (4 MiB)
0x0 +----------------------------------+
| fwbl1 (12 KiB) |
0x18 +----------------------------------+
| epbl (76 KiB) |
0xb0 +----------------------------------+
| bl2 (256 KiB) |
0x2b0 +----------------------------------+
| dram_train (16 KiB) |
0x2d0 +----------------------------------+
| ect_test (50 KiB) |
0x334 +----------------------------------+
| acpm_test (130 KiB) |
0x438 +----------------------------------+
| bootloader (2 MiB) |
0x1438 +----------------------------------+
| el3_mon (256 KiB) |
0x1638 +----------------------------------+
where U-Boot should be flashed into 'bootloader' partition. So U-Boot
binary size should be 2 MiB or less. The whole boot0 partition is 4 MiB,
but only 2.8 MiB is currently used.
With this change, the U-Boot binary can be updated on eMMC like this:
=> dfu 0 mmc 0
$ dfu-util -D u-boot.bin -a bootloader
Looking at E850-96 booting diagram at [1,2], it's easy to see how these
binaries are being executed in the same order they are placed in
mmc0boot0 area. E.g. fwbl1 is definitely BL1 (software part of Boot
ROM). So it's obvious the ROM code just reads the binary from eMMC at
0x0 offset into RAM (SRAM?) and executes it.
All mentioned images can be found at [3], as stated in E850-96 U-Boot
documentation. 'dram_train', 'ect_test' and 'acpm_test' areas should be
ignored -- they are not flashed with real images.
[1] doc/board/samsung/e850-96.rst
[2] https://docs.u-boot.org/en/latest/board/samsung/e850-96.html
[3] https://gitlab.com/Linaro/96boards/e850-96/images/-/tree/master/images
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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Setup "serial#" environment variable from the chip ID. The chip ID is
read from Exynos850 SoC OTP (One Time Programmable) memory, which acts
like an EEPROM and contains unique SoC ID. This "serial#" variable is
further used for "fastboot devices" serial number, etc.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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The only thing needed from DWC3 glue layer for Exynos850 is to enable
USB clocks. The generic glue layer driver already does that. Add
Exynos850 dwc3 compatible string to enable support for this chip.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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Add DM driver for Exynos USB PHY controllers. For now it only supports
Exynos850 SoC. Only UTMI+ (USB 2.0) PHY interface is implemented, as
Exynos850 doesn't support USB 3.0. Only two clocks are used for this
controller:
- phy: bus clock, used for PHY registers access
- ref: PHY reference clock (OSCCLK)
Ported from Linux kernel: drivers/phy/samsung/phy-exynos5-usbdrd.c
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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https://gitlab.denx.de/u-boot/custodians/u-boot-imx
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/27149
- Add support for the NXP imx93 frdm board.
- imx93_evk and phycore-imx93 cleanups.
- Convert imx6dl-sielaff to OF_UPSTREAM and fix serial download mode boot.
- Fix crash in imx power-domain.
- Migrate Phytec imx8mm boards to standard boot.
- Fix smatch warnings.
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Neha Malcom Francis <n-francis@ti.com> says:
This series implements a driver for the BIST (Built-In Self Test) module
for K3 devices. The BIST driver must ideally support triggering of BIST
tests, both PBIST (Memory BIST) and LBIST (Logic BIST) on a core. Both
tests are destructive in nature. Please see links [1] and [2] for
further information regarding the two.
At boot up, BIST is executed by hardware for the MCU domain
automatically as part of HW POST. So BIST has been checked only for the
MCU domain when U-Boot comes up in the usual U-Boot to Linux boot flow.
To facilitate the use-case where some safe firmware is intended to be
run on a safe core, it is best to have triggered the BIST tests on that
core. As an example, we take triggering the BIST tests on the MAIN R52_x
cores. The triggering patch is kept as DONOTMERGE.
The general procedure for triggering BIST on a core is:
1. Power on the core under test following a sequence
2. Trigger the BIST test
3. Reset the core under test following a sequence
BIST tests are triggered from A72 SPL where the DM (Device Manager
firmware that handles power management) is already up and can perform
these power sequences for us.
Boot logs (with LOG_DEBUG and CONFIG_K3_BIST enabled) and DT node kept (already
merged to ti-k3-dts-next [3]):
https://gist.github.com/nehamalcom/3fed504d038b54e3e05ba3874d73d603
[1] https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/latest/exports/docs/sdl/sdl_docs/userguide/j721e/modules/pbist.html#introduction
[2] https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/latest/exports/docs/sdl/sdl_docs/userguide/j721e/modules/lbist.html#introduction
[3] https://lore.kernel.org/all/175205725858.918402.3771835070085533874.b4-ty@ti.com/
Link: https://lore.kernel.org/r/20250716062156.2564297-1-n-francis@ti.com
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The load address for the R5's SPL is defined in Kconfig by
SPL_TEXT_BASE. Rather than hard coding the load address which could
lead to hard to debug issues if this value is changed, just use the
SPL_TEXT_BASE value.
Reviewed-by: Andrew Davis <afd@ti.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
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The uart11 reg address was a copy of the value for uart10.
Update it to the correct value.
Signed-off-by: Rebecca Cran <rebecca@os.amperecomputing.com>
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Smatch reported a possible buffer overflow in exfat_set_label but it
turns out that this code is unused so just guard the function with
'#ifndef __UBOOT__' as well as exfat_get_label that is also unused and
the helper static find_label.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
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Instead of strcpy which is unbounded use strlcpy to ensure that the
receiving buffer cannot be overflowed.
This issue found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
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Commit 86acdce2ba88 ("common: add config for board_init() call")
introduced CONFIG_BOARD_INIT option. This option can be disabled for the
boards where board_init() function is not needed. Remove empty
board_init() calls for all boards where it's possible, and disable
CONFIG_BOARD_INIT in all related defconfigs.
This cleanup was made semi-automatically using these scripts: [1].
No functional change, but the binary size for the modified boards is
reduced a bit.
[1] https://github.com/joe-skb7/uboot-convert-scripts/tree/master/remove-board-init
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Tested-by: Adam Ford <aford173@gmail.com> #imx8mm_beacon
Tested-by: Bryan Brattlof <bb@ti.com>
Acked-by: Peng Fan <peng.fan@nxp.com> #NXP boards
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Trigger all tests of PBIST and LBIST using appropriate calls to set the
core under test (MAIN R5 2_0) to it's required state.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
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Add a driver for the BIST module that support triggering of both PBIST
(Memory BIST) and LBIST (Logic BIST) tests. Also expose the relevant
operations and functions that would be required for an end user to
trigger the tests.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
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uclass_find_next_device always returns 0, so instead make it a void and
update calling sites.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
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https://source.denx.de/u-boot/custodians/u-boot-microblaze
AMD/Xilinx/FPGA changes for v2025.10-rc1 v2
zynqmp:
- Generate fit-dtb.blob all the time
- Simplify power-domain driver bind
zynqmp_mini:
- Remove PSCI_RESET
fpga:
- Improve user feedback in case of FPGA bitstream load failure
misc:
- Fix kernel-doc in gpio zynq and axi_mrmac
spi:
- Revert fix in STIG mode
[trini: Remove CONFIG_FPGA_VERSALPL=y from sandbox due to
sandbox+clang+asan test problem]
Signed-off-by: Tom Rini <trini@konsulko.com>
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