summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2021-09-21configs: sama5d2: add qspi config for QSPI1Mihai Sain
Add new config for storing environment from QSPI1. Signed-off-by: Mihai Sain <mihai.sain@microchip.com> [eugen.hristev@microchip.com: cleanup and add MAINTAINERS entry] Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2021-09-21ARM: dts: at91: sama5d2: fix dtc warning for ohci and ehciEugen Hristev
Fixed the following DTC build warning (reproducible with W=1) arch/arm/dts/at91-sama5d2_icp.dtb: Warning (unit_address_format): /ahb/ohci@00400000: unit name should not have leading 0s arch/arm/dts/at91-sama5d2_icp.dtb: Warning (unit_address_format): /ahb/ehci@00500000: unit name should not have leading 0s Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by: Alexander Dahl <ada@thorsis.com>
2021-09-21ARM: dts: at91: sama5d2_icp: cosmetic arrangement of the nodesEugen Hristev
Reorder the nodes following the kernel rules: nodes in a range are sorted by ascending bus address, and when referenced by phandle, are ordered alphabetically. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2021-09-21ARM: dts: at91: sama5d2_icp: add QSPI1 deviceMihai Sain
Add support for sst26vf064b 64Mbit qspi-flash that is present on sama5d2_icp board. Signed-off-by: Mihai Sain <mihai.sain@microchip.com> [eugen.hristev@microchip.com: move u-boot properties to sama5d2_icp-u-boot.dtsi] Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2021-09-21board: sama5d2_xplained: Modify load addressesClément Léger
When using OP-TEE, address range [0x20000000 - 0x22000000] is reserved. This modification allows to have a system which always work even when OP-TEE is present. Signed-off-by: Clément Léger <clement.leger@bootlin.com>
2021-09-21board: sama5d2_xplained: Get dram size and base from device treeClément Léger
In order to make it more flexible and allow modifying the base address of DRAM without recompiling U-Boot, use memory node from device tree with fdtdec functions. Signed-off-by: Clément Léger <clement.leger@bootlin.com>
2021-09-21ARM: dts: at91: sama5d2_xplained: Add memory node in devicetreeClément Léger
sama5d2_xplained DRAM detection code will be modified to use device tree instead of hardcoded addresses. In order to prepare that, add the memory node to at91-sama5d2_xplained.dts. Signed-off-by: Clément Léger <clement.leger@bootlin.com>
2021-09-21board: sama5d27_som1_ek: Modify load addressesClément Léger
When using OP-TEE, address range [0x20000000 - 0x22000000] is reserved. This modification allows to have a system which always work even when OP-TEE is present. Signed-off-by: Clément Léger <clement.leger@bootlin.com>
2021-09-21board: sama5d27_som1_ek: Get dram size and base from device treeClément Léger
In order to make it more flexible and allow modifying the base address of DRAM without recompiling U-Boot, use memory node from device tree with fdtdec functions. Signed-off-by: Clément Léger <clement.leger@bootlin.com>
2021-09-21ARM: mach-at91: armv7: fix multiple cpu_reset definition when enabling SYSRESETClément Léger
When SYSRESET is enabled, cpu_reset function is also defined in sysreset-uclass.c which lead to multiple definitions of this function since reset.c is build unconditionally. Add a check in Makefile to build this file only if SYSRESET isn't enabled. SYSRESET can be enabled when building SYSRESET_PSCI for instance on this platform. Signed-off-by: Clément Léger <clement.leger@bootlin.com>
2021-09-21configs: gardena-smart-gateway-at91sam: Adjust to production valuesReto Schneider
This commit updates the default config with the values that will be used soon on the Atmel / Microchip AT91SAM9G25 based GARDENA smart gateway. Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com> Reviewed-by: Stefan Roese <sr@denx.de>
2021-09-21configs: sam9x60ek: enable CONFIG_CPUClaudiu Beznea
Enable CONFIG_CPU for SAM9X60EK configs. Reported-by: Eugen Hristev <eugen.hristev@microchip.com> Fixes: a64862284f65 ("clk: at91: sam9x60: add support compatible with CCF") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2021-09-21ARM: dts: at91: sam9x60: add bindings for CPUClaudiu Beznea
Add bindings for CPU. This will allow displaying correctly the crystal, CPU and master clock. Reported-by: Eugen Hristev <eugen.hristev@microchip.com> Fixes: a64862284f65 ("clk: at91: sam9x60: add support compatible with CCF") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2021-09-21cpu: at91: add compatible for ARM9260EJ-SClaudiu Beznea
The crystal, CPU and master clock were not displayed correctly on SAM9X60 after adding CCF clock support. Add compatible for ARM926EJ-S to fix this. Reported-by: Eugen Hristev <eugen.hristev@microchip.com> Fixes: a64862284f65 ("clk: at91: sam9x60: add support compatible with CCF") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2021-09-21clk: at91: clk-master: split master clock in pres and dividerClaudiu Beznea
Split master clock in 2 controlling block: one for prescaler one for divider. This will allow referencing correctly the CPU clock and master clock in device trees. Reported-by: Eugen Hristev <eugen.hristev@microchip.com> Fixes: a64862284f65 ("clk: at91: sam9x60: add support compatible with CCF") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2021-09-21ARM: at91: Add chip ID of SAMA5D29Hari Prasath
Add SAMA5D29 SoC for identification during the boot up. Signed-off-by: Hari Prasath <Hari.PrasathGE@microchip.com>
2021-09-16scripts/config_whitelist.txt: Fix after mergingTom Rini
CONFIG_SPIFLASH is manually re-added as it is not a new symbol, but now only exists in CONFIG_SYS_EXTRA_OPTIONS. Signed-off-by: Tom Rini <trini@konsulko.com>
2021-09-16pci: Fix mismerge with v2021.10-rc4Tom Rini
With legacy PCI code removed and thus DM_PCI also removed, a few places did not get correctly updated with the merge to next and thus broke. Remove now extraneous dependencies on DM_PCI. Signed-off-by: Tom Rini <trini@konsulko.com>
2021-09-16Merge tag 'v2021.10-rc4' into nextTom Rini
Prepare v2021.10-rc4 Signed-off-by: Tom Rini <trini@konsulko.com> # gpg: Signature made Tue 14 Sep 2021 06:58:32 PM EDT # gpg: using RSA key 1A3C7F70E08FAB1707809BBF147C39FF9634B72C # gpg: Good signature from "Thomas Rini <trini@konsulko.com>" [ultimate] # Conflicts: # board/Arcturus/ucp1020/spl.c # cmd/mvebu/Kconfig # common/Kconfig.boot # common/image-fit.c # configs/UCP1020_defconfig # configs/sifive_unmatched_defconfig # drivers/pci/Kconfig # include/configs/UCP1020.h # include/configs/sifive-unmatched.h # lib/Makefile # scripts/config_whitelist.txt
2021-09-14Prepare v2021.10-rc4v2021.10-rc4Tom Rini
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-09-14configs: Resync with savedefconfigTom Rini
Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
2021-09-14image: Avoid erroneous double byte-swap in CRC valueAlexandru Gagniuc
The hash algorithm selection was streamlined in commit 92055e138f28 ("image: Drop if/elseif hash selection in calculate_hash()"). Said commit kept the call to cpu_to_uimage() to convert the CRC to big endian format. This would have been correct when calling crc32_wd(). However, the ->hash_func_ws member of crc32 points to crc32_wd_buf(), which already converts the CRC to big endian. On a little endian host, doing both conversions results in a little-endian CRC. This is incorrect. To remedy this, simply drop the call to cpu_to_uimage(), thus only doing the byte-order conversion once. Fixes: 92055e138f28 ("image: Drop if/elseif hash selection in calculate_hash()") Tested-by: Tom Rini <trini@konsulko.com> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2021-09-14Merge branch '2021-09-14-assorted-fixes'Tom Rini
- Assorted bugfixes
2021-09-14image: rsa: Move padding_algos to linker listsAlexandru Gagniuc
We are not guaranteed to have the padding_pkcs_15_verify symbol since commit 92c960bc1d ("lib: rsa: Remove #ifdefs from rsa.h"), and commit 61416fe9df ("Kconfig: FIT_SIGNATURE should not select RSA_VERIFY") The padding_algos only make sense with RSA verification, which can now be disabled in lieu of ECDSA. In fact this will lead to build failures because of the missing symbol mentioned earlier. To resolve this, move the padding_algos to a linker list, with declarations moved to rsa_verify.c. This is consistent with commit 6909edb4ce ("image: rsa: Move verification algorithm to a linker list") One could argue that the added #ifdef USE_HOSTCC is ugly, and should be hidden within the U_BOOT_PADDING_ALGO() macro. However, this would be inconsistent with the "cryptos" list. This logic for was not previously explored: Without knowledge of the U_BOOT_PADDING_ALGO() macro, its use is similar to something being declared. However, should #ifndef USE_HOSTCC be part of the macro, it would not be obvious that it behaves differently on host code and target code. Having the #ifndef outside the macro makes this obvious. Also, the #ifdef is not always necessary. For example ecda-verify makes use of U_BOOT_CRYPTO_ALGO() without any accompanying #ifdefs. The fundamental issue is a lack of separation of host and target code in rsa_verify. Therefore, the declaration of a padding algo with the external #ifdef is more readable and consistent. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2021-09-14pinctrl: fix typoYuan Fang
fix typo in pinctrl Kconfig file to avoid git commit failure on some commit hooks check. Signed-off-by: Yuan Fang <fangyuanseu@gmail.com>
2021-09-14lib: fix typos in KconfigOleksandr Suvorov
There are trivial typos in the Kconfig file. Fixed them. Also, fixed grammar in the descriptions with typos. Fixes: d56b4b1974 ("configs: Migrate RBTREE, LZO, CMD_MTDPARTS, CMD_UBI and CMD_UBIFS") Fixes: 7264f2928b ("spl: fit: Eanble GZIP support for image decompression") Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-09-14lib/rsa: don't use NULL as key_idHeinrich Schuchardt
If keydir is not provided but name is we want to use name as key_id. But with the current coding name is only used on its own if it is NULL and keydir is provided which never occurs. Fixes: 824ee745fbca ("lib/rsa: Use the 'keyfile' argument from mkimage") Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-09-13Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxiTom Rini
- a fix for U-Boot 2021.10 to bring back MMC boot on older boards.
2021-09-14sunxi: mmc: A20: Fix MMC optimisationAndre Przywara
Some SoCs (as seen on A20) seem to misreport the MMC FIFO level if the FIFO is completely full: the level size reads as zero, but the FIFO_FULL bit is set. We won't do a single iteration of the read loop in this case, so will be stuck forever. Check for this situation and use a safe minimal FIFO size instead when we hit this case. This fixes MMC boot on A20 devices after the MMC FIFO optimisation (9faae5457f52). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-09-13Merge branch '2021-09-09-finish-pre-DM_PCI-removal'Tom Rini
- Finish removing the non-DM_PCI legacy code.
2021-09-13pci: Drop DM_PCISimon Glass
This option has not effect now. Drop it, using PCI instead where needed. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-13pci: Drop PCI_INDIRECT_BRIDGESimon Glass
This does not work with driver model so can be removed. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-13net: Drop DM_PCI check from designware driverSimon Glass
We don't need this check anymore since when PCI is enabled, driver model is always used. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-13pci: acpi: Drop DM_PCI check from ahciSimon Glass
We don't need these checks anymore since when PCI is enabled, driver model is always used. Drop them. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-13pci: Drop DM_PCI check from fdtdecSimon Glass
We don't need this check anymore since when PCI is enabled, driver model is always used. Sadly this doesn't work with nds32 for some reason to do with the toolchain. Add a work-around for that. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-13pci: Drop old code from header fileSimon Glass
We don't need this code anymore since when PCI is enabled, driver model is always used. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-13ppc: Remove UCP1020 boardSimon Glass
This board has not been converted to CONFIG_DM_PCI by the deadline. Remove it. Note that we have to add CONFIG_SPIFLASH to scripts/config_whitelist.txt because it's not really migrated at this point. Acked-by: Michael Durrant <mdurrant@arcturusnetworks.com> Acked-by: Oleksandr Zhadan <oleks@arcturusnetworks.com> Acked-by: Oleksandr Zhadan and Michael Durrant <arcsupport@arcturusnetworks.com> Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Handle CONFIG_SPIFLASH differently and delete Kconfig file] Signed-off-by: Tom Rini <trini@konsulko.com>
2021-09-13Merge tag 'mmc-2021-9-13' of https://source.denx.de/u-boot/custodians/u-boot-mmcTom Rini
Support using mmc command for enumerating mmc card in a given mode Fix device_remove in mmc Fix switch issue with send_status disabled Drop 1ms delay in fsl_esdhc command sending Revert "mmc: sdhci: set to INT_DATA_END when there are data"
2021-09-13mmc: fsl_esdhc: remove 1ms sleep in esdhc_send_cmd_common()Michael Walle
Since the beginning of this driver which was initially for the MPC8379 and MPC8536 SoCs, there is this spurious 1ms delay. According to the comment it should actually be only 8 clock cycles. Esp. during EFI block transfers, this 1ms add up to a significant delay and slows down EFI boot. I couldn't find any mention in the MPC8536 that there should be a delay of 8 clock cycles between commands. The SD card specification mentions that the clock has to be left enabled for 8 cycles after a command or response. But I don't see how this delay will help with this. Go ahead and just remove it. If there will ever be any regression we can introduce a compile time flag, but for now I'd like to keep it simple. In the split off imx driver this delay was also removed in commit 9098682200e6 ("mmc: fsl_esdhc_imx: remove the 1ms delay before sending command"). Signed-off-by: Michael Walle <michael@walle.cc>
2021-09-12Merge tag 'efi-2021-10-rc4-2' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-efi Pull request for efi-2021-10-rc4-2 Documentation: * improve documentation of U-Boot for /config DT node * integrate bloblist documentation UEFI: * correct usage of EFI_CALL() * code tidy up
2021-09-11Merge branch '2021-09-11-update-docker-container' into nextTom Rini
- Update to latest Docker container images for CI. This includes QEMU 6.1.0 and support for SiFive Unleashed being tested.
2021-09-11CI: Update to latest container imagesTom Rini
- Current Ubuntu/Focal tag - QEMU 6.1.0 - genimage tool added Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2021-09-11azure/gitlab: Add tests for SiFive Unleashed boardBin Meng
This adds CI tests for SiFive Unleashed board. QEMU supports booting exact the same images as used on the real hardware out of the box, that U-Boot SPL loads U-Boot proper from either an SD card or the SPI NOR flash, hence we can easily set up CI to cover these 2 boot flows of SiFive Unleashed board. With this, now we can have regression testing of mmc-spi-slot and sifive spi drivers, as well as mmc and spi-nor subsystems. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2021-09-11riscv: sifive: unleashed: Add genimage config filesBin Meng
This adds genimage [1] config files for generating SD card and spi-nor images, which can be programmed to an SD card or SPI flash and boot from there. The same images will be used for U-Boot CI testing for this board. [1] https://github.com/pengutronix/genimage Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2021-09-11tools: docker: Build and install genimageBin Meng
genimage [1] is a tool to create flash/disk images. This is required by some targets, e.g.: sifive_unleashed, to generate sdcard or spi-nor images for real hardware, as well as U-Boot CI testing. [1] https://github.com/pengutronix/genimage Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2021-09-11tools: docker: Bump up QEMU version to 6.1.0Bin Meng
At present U-Boot CI testing is still using QEMU 4.2.0 which is pretty old. Let's bump up to QEMU 6.1.0. ninja-build is added as the prerequisite required by QEMU 6.1.0. Note there is a bug in QEMU 6.1.0 Xilinx Zynq UART emulation codes. A quick fix [1] was posted on QEMU mailing list but it it too late for 6.1.0 release. Let's manually apply the bug fix on top of the v6.1.0 release tag at the time being. [1] http://patchwork.ozlabs.org/project/qemu-devel/patch/20210823020813.25192-2-bmeng.cn@gmail.com/ Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2021-09-11Dockerfile: Update to latest "focal" tagTom Rini
Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2021-09-11Merge branch '2021-09-10-assorted-TI-updates'Tom Rini
- A number of TI platform bugfixes
2021-09-11efi_loader: simplify efi_watchdog_timer_notify()Heinrich Schuchardt
We can call do_reset() directly without invoking the UEFI API. This decreases the code size. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-09-11efi_loader: eliminate EFI_CALL() in nvedit_efi.cHeinrich Schuchardt
Reduce the code size by avoiding using the external UEFI API and using our internal functions instead. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-06 11:50:04 +0000