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2024-09-20arm64: zynqmp: Fix status property for m-a2197 boardsMichal Simek
Status property should be missing or okay or disabled but not just disable. dt-validate is reporting it too. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/bbf62f5911fcb356d1467b3979b4ff3c485124ad.1726219714.git.michal.simek@amd.com
2024-09-20board: xilinx: Remove conditional check for MicroblazePadmarao Begari
U-Boot is not picking boot.scr script address from device tree rather it's using default address for Microblaze platform, and it's picking for other platforms. Remove conditional check for Microblaze platform, so that u-boot pick up boot.scr script address for all platforms from device tree. Signed-off-by: Padmarao Begari <padmarao.begari@amd.com> Link: https://lore.kernel.org/r/20240913093231.2343528-1-padmarao.begari@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2024-09-20arm64: zynqmp: Define only one revision in zcu106-rev1.0Michal Simek
zcu106 rev1.0 is sw compatible with revA but only one revision should be listed in compatible string that's why remove revA and keep only rev1.0. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/c5214b1a01032b88a394104a57624e0d91a22f29.1726221517.git.michal.simek@amd.com
2024-09-20mmc: zynq_sdhci: Remove device_is_compatible() functionPadmarao Begari
There are lot of device_is_compatible() present in the driver. Remove them and replace with a variables "SDHCI_COMPATIBLE_SDHCI_89A" and "SDHCI_COMPATIBLE_VERSAL_NET_EMMC" with match data. This change saves the space and reduce the execution time. Signed-off-by: Padmarao Begari <padmarao.begari@amd.com> Link: https://lore.kernel.org/r/20240913093157.2343476-1-padmarao.begari@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2024-09-20net: gem: Remove undocumented is-internal-pcspma dt flagMichal Simek
Generic understanding/consideration is that phy-mode as sgmi means that the internal PCS(Physical Coding Sublayer) should be enabled by default. Xilinx GEM implementation allows configuration GEM (gmii mode) + PL PCS PMA (sgmii mode, Physical Medum Attachment) but in this case phy-mode should be setup as gmii. The reason for this assumption is that phy-mode should be described based on GEM configuration not based on mode coming out of PHY. Also Linux kernel automatically setting up PCSSEL bit when phy mode is sgmii without a need to specified additional DT propety. All our DTSes with sgmii phy mode have this flag enabled that's why there is no need/reason to just duplicate information. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/2ecdbcc4ce692e2f8b3e7054a2abab35f6c03a69.1726213052.git.michal.simek@amd.com
2024-09-20xilinx: Enable SIMPLE_PM_BUSMichal Simek
Enable simple-pm-bus driver to handle case where axi bus coming between PS (fixed) part to PL (programmable) part has own clock or power domain. That's why enable driver to be ready for this configuration. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/b9f4bb85be502616edf3be2b79e52a0e2c03e821.1725349691.git.michal.simek@amd.com
2024-09-20arm64: zynqmp: Remove overlays and add new dtb entries for ZynqMPPrasad Kummari
Remove device tree overlay (DTBO) entries for the ZynqMP target from the Makefile. Add new device tree binaries (DTBs) for the zynqmp-sm-k24-revA and zynqmp-smk-k24-revA configurations. Signed-off-by: Prasad Kummari <prasad.kummari@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/20240906070808.1045991-3-prasad.kummari@amd.com
2024-09-20kbuild: cherry-pick kbuild fdtoverlay changes from linuxPrasad Kummari
Linux commits: 15d16d6dadf6 kbuild: Add generic rule to apply fdtoverlay 44f87191d105 kbuild: parameterize the .o part of suffix-search The Linux commit 15d16d6dadf6 adds a generic rule in Makefile.lib to automatically apply fdtoverlay, so that each platform doesn't need to include a complex rule. This also automatically appends DTC_FLAGS_foo_base += -@ to all base files The platform's Makefile only needs to have this now: foo-dtbs := foo_base.dtb foo_overlay1.dtbo foo_overlay2.dtbo dtb-y := foo.dtb Signed-off-by: Prasad Kummari <prasad.kummari@amd.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/20240906070808.1045991-2-prasad.kummari@amd.com
2024-09-20arm64: zynqmp: Add missing vc7_xin fixed clock to sc-vpk180-revAMichal Simek
Add missing vc7_xin fixed clock as clock input for some clock generators. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/4904f5e0aab8a0b0c2fcc1912be493d4185e6173.1725881047.git.michal.simek@amd.com
2024-09-20arm: zynqmp: Enable non-invasive CCI-400 PMU debugSean Anderson
Set NIDEN, enabling non-invasive debug for the CCI-400 PMU. Otherwise, the PMU is effectively disabled. Signed-off-by: Sean Anderson <sean.anderson@linux.dev> Reviewed-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/20240905171833.325548-3-sean.anderson@linux.dev Signed-off-by: Michal Simek <michal.simek@amd.com>
2024-09-20zynqmp: Disable secure access for boot devicesSean Anderson
Boot devices (QSPI, MMC, NAND, and Ethernet) use secure access for DMA by default. As this causes problems when using the SMMU [1], configure them for normal access instead. [1] https://support.xilinx.com/s/article/72164 Signed-off-by: Sean Anderson <sean.anderson@linux.dev> Link: https://lore.kernel.org/r/20240905171833.325548-2-sean.anderson@linux.dev Signed-off-by: Michal Simek <michal.simek@amd.com>
2024-09-20arm64: zynqmp: Add u-boot command to boot into recovery imagePrasad Kummari
To boot into the firmware recovery tool, the user currently needs to press a button on the board while powering the system up. To simplify this process, a U-Boot command was added to allow booting directly into the recovery tool. For example: ZynqMP> zynqmp reboot <multiboot offset in hex> Co-develop-by: Prasad Kummari <prasad.kummari@amd.com> Signed-off-by: Prasad Kummari <prasad.kummari@amd.com> Co-develop-by: Michal Simek <michal.simek@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/20240827115529.2931334-1-prasad.kummari@amd.com
2024-09-20xilinx: versal-net: fix no previous prototype for function warning.Prasad Kummari
Included the SPI header to resolve the no previous prototypes for function. Removed unused mode variable. sparse warnings warning: no previous prototype for 'spi_get_env_dev' [-Wmissing-prototypes] warning: variable 'mode' set but not used [-Wunused-but-set-variable] Signed-off-by: Prasad Kummari <prasad.kummari@amd.com> Link: https://lore.kernel.org/r/20240905115758.999936-1-prasad.kummari@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2024-09-19mtd: spi-nor: scale up timeout for full-chip eraseVenkatesh Yadav Abbarapu
This patch fixes timeout issues seen on large NOR flash. For full-chip erase, where we use the SPINOR_OP_CHIP_ERASE (0xc7) opcode. Use a different timeout for full-chip erase than for other commands. [Ported from Linux kernel commit 09b6a377687b ("mtd: spi-nor: scale up timeout for full-chip erase") ] Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
2024-09-19Merge tag 'u-boot-imx-next-20240919' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/22363 - Several updates to i.MX9 SOC and i.MX93 EVK. - Power domain fixes. - TRDC cleanup and update. - MAC address layout update. - Add support for the i.MX9301/9302 variants. - Add runtime detection of voltage mode. - Generalize some code for i.MX8M and i.MX9. - Add support for Comvetia imx6q-lxr board.
2024-09-19Merge tag 'fwu-next-19092024' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-tpm into next This PR contains various improvements in the A/B update logic for EFI - Read both copies of metadata, in case one of the is corrupted - Check the metadata version against the running firmware to make sure it's allowed - Limit the use of a revert capsule if the board is on a trial state and make sure it's not applied if the max counter has expired
2024-09-19fwu: print a message if empty capsule checks failSughosh Ganu
When dealing with processing of the empty capsule, the capsule gets applied only when the checks for the empty capsule pass. Print a message to highlight if empty capsule checks fail, and return an error value, similar to the normal capsules. Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org> Tested-by: Michal Simek <michal.simek@amd.com> Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-09-19fwu: do not allow capsule processing on exceeding Trial Counter thresholdSughosh Ganu
When in Trial State, the platform keeps a count of the number of times it has booted in the Trial State. Once the threshold of the maximum allowed count exceeds, the platform reverts to boot from a different bank on subsequent boot, thus coming out of the Trial State. It is expected that all the updated images would be accepted or rejected while the platform is in Trial State. Put in checks so that it is not possible to apply an empty capsule once the max Trial Count exceeds. Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org> Tested-by: Michal Simek <michal.simek@amd.com> Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-09-19fwu: add dependency checks for selecting FWU metadata versionSughosh Ganu
The FWU code supports both versions of the FWU metadata, i.e. v1 and v2. A platform can then select one of the two versions through a config symbol. Put a dependency in the FWU metadata version selection config symbol to ensure that both versions of the metadata cannot be enabled. Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org> Reviewed-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-09-19fwu: check all images for transitioning out of Trial StateSughosh Ganu
The platform transitions out of Trial State into the Regular State only when all the images in the update bank have been accepted. Check for this condition before transitioning out of Trial State. Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org> Tested-by: Michal Simek <michal.simek@amd.com> Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-09-19fwu: v1: do a version check for the metadataSughosh Ganu
Do a sanity check that the version of the FWU metadata that has been read aligns with the version enabled in the image. This allows to indicate an early failure as part of the FWU module initialisation. Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org> Tested-by: Michal Simek <michal.simek@amd.com> Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-09-19fwu: v2: try reading both copies of metadataSughosh Ganu
In the version 2 of the FWU metadata, the metadata is broken into two parts, a top-level structure, which provides information on the total size of the structure among other things. Try reading the primary partition first, and if that fails, try reading the secondary partition. This will help in the scenario where the primary metadata partition has been corrupted, but the secondary partition is intact. Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org> Tested-by: Michal Simek <michal.simek@amd.com> Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-09-19imx6q-lxr: Add board supportFabio Estevam
Add support for the Comvetia i.MX6Q LXR2 board, which is uses the Phytec PFLA02 SoM. Based on the original work from Stefano Babic <sbabic@denx.de>. The Phytec PFLA02 devicetrees are taken from kernel 6.11-rc7. The imx6q-lxr.dts has been submitted upstream: https://lore.kernel.org/linux-devicetree/20240913200906.1753458-3-festevam@gmail.com/ After it gets accepted in mainline (most likely in kernel 6.13), the lxr2 board can then be switched to OF_UPSTREAM and these device trees can be removed from U-Boot. Signed-off-by: Fabio Estevam <festevam@denx.de>
2024-09-19imx93_evk: add back Low drive mode ddr timing filePeng Fan
Add back low drive mode 1866mts ddr timing file, no need CONFIG_IMX9_LOW_DRIVE_MODE anymore, using runtime selection. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2024-09-19imx93_evk: Remove CONFIG_IMX9_LOW_DRIVE_MODE and ld defconfigPeng Fan
Remove unused CONFIG_IMX9_LOW_DRIVE_MODE kconfig and imx93_11x11_evk_ld_defconfig. Remove the ld timing file. The LD mode support will be added back with runtime detection later. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2024-09-19imx93_evk: spl: update pmic settingsPeng Fan
1. Use runtime voltage selection for LD/OD/ND mode. 2. According to latest PE/TE report, the voltages of VDD_SOC for LD and ND mode need add 50mv margin, so LD voltage is 0.75v->0.8v, ND voltage is 0.8v->0.85v. 3. Use TOFF_DEB to differentiate new trimmed pmic and old pmic Signed-off-by: Peng Fan <peng.fan@nxp.com>
2024-09-19imx9: trdc: introduce trdc_mbc_blk_numPeng Fan
Add trdc_mbc_blk_num to get num blks in a MBC mem slot, then drop the hardcoded value '40' for NIC OCRAM configuration. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2024-09-19imx9: trdc: cleanup codePeng Fan
Replace magic number with meaningful macros. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2024-09-19imx: Generalize fixup_thermal_tripsPeng Fan
i.MX8M and i.MX9 have duplicated fixup_thermal_trips, so move it to arch/arm/mach-imx/fdt.c to avoid duplicated code. The critial temperature point for i.MX9 set to "maxc - 5" back to give some margin. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2024-09-19imx93: Add Low performance parts 9302/9301 supportYe Li
Add support for iMX93 low performance parts 9302 and 9301 which restrict to low drive voltage only. The parts run A55 max speed at 900Mhz and M33 at 133Mhz, have NPU and A55 core1 (9301) disabled. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2024-09-19imx9: soc: Disable cpu1 for variants that only has one A55 corePeng Fan
Disale CPU1 for i.MX93 variants that only has one A55 core and update cooling maps. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2024-09-19imx: Generalize disable_cpu_nodesPeng Fan
disable_cpu_nodes could be reused by i.MX9, so move disable_cpu_nodes out from mach-imx/imx8m/soc.c to mach-imx/fdt.c and update disable_cpu_nodes to make it easy to support different socs. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2024-09-19imx8m: soc: Drop disable_pmu_cpu_nodesPeng Fan
i.MX8M use PPI for PMU interrupts, there is no reason to update interrupt-affinity for PMU even interrupt-affinity was wrongly added to device tree before. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2024-09-19imx9: Add 233Mhz DDR PLL frequencyYe Li
To support 1.866GTS LPDDR4x timing script, need to add 233Mhz freq to DDR PLL for second mission point at 933MTS. Otherwise DDR training will fail. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2024-09-19imx9: soc: Mask the wdog reset in src by default on i.mx9Jacky Bai
Normally, the wdog will be used for trigger external PMIC reset through the WDOG_ANY pin. If the PMIC chip has debounce logic for the reset signal, in some corner case the wdog can NOT trigger external PMIC reset if the SoC has been reset internal before the PMIC captures the WDOG_ANY pin reset, so need to keep the WDOG3-5 reset masked in the SRC to let the PMIC to do the reset safely. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2024-09-19imx9: clock: Update clock init function and sequenceYe Li
Since we use SPEED GRADE fuse to set A55 frequency, remove the set_arm_core_low_drive_clk function which has hard coded frequency. And adjust clock_init called sequence and split it to early and late functions. Set the authen register in early function, because CCF driver checks NS bit. Set bus and core clock in late function, because the fuse read and SoC type/rev depend on ELE. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2024-09-19imx9: soc: Add function to get target voltage modeYe Li
Replace the static CONFIG_IMX9_LOW_DRIVE_MODE with runtime target voltage mode by checking the part's SPEED GRADE fuse. SPL will configure to highest A55 speed which is indicated by the SPEED fuse and select corresponding voltage mode. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2024-09-19imx9: soc: Print ELE informationPeng Fan
The boot image includes Edgelock Enclave(ELE) Firmware. Print the information out to let user know which version firmware is being used. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2024-09-19imx9: soc: Change second Ethernet MAC fuse layoutYe Li
The second Ethernet MAC (eQOS) fuse layout is changed since i.MX93 A1 following other i.MX platforms, for example i.MX8MP. Order for A0: MAC1_ADDR[15:0] MAC1_ADDR[31:16] MAC1_ADDR[47:32] MAC2_ADDR[47:32] MAC2_ADDR[15:0] MAC2_ADDR[31:16] Order since A1: MAC1_ADDR[15:0] MAC1_ADDR[31:16] MAC1_ADDR[47:32] MAC2_ADDR[15:0] MAC2_ADDR[31:16] MAC2_ADDR[47:32] Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2024-09-19imx9: soc: Change FSB directly access to fuse APIPeng Fan
To support OSCCA enabled part which has disabled FSB access from SOC, change directly read from FSB to use fuse_read API. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2024-09-19imx9: soc: Print UID in big endian format for EL2GOYe Li
Print UID in big endian format and as one buffer of bytes, so customer can directly use it for EdgeLock 2GO. Before: UID: 0xf6c8ae93 0x0f46b326 0x10d61eb3 0x0583c2d2 Become: UID: 93aec8f626b3460fb31ed610d2c28305 Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2024-09-19imx9: soc: imx9: soc: Align UID endianness with ROMFrank Li
ROM use UID[0] and UID[1] as serial number with big endian when usb serial download. After update this, uuu(>1.6) can use below command to filter out devices when multi boards connected. uuu -ms <serial#> ... [sudo] uuu -lsusb can list known devices with serial# informaiton. Signed-off-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2024-09-19imx9: soc: Configure TRDC for M33 TCM accessYe Li
On OSCCA part, M33 TCM is used for ROM PATCH and protected by ELE ROM. So after release TRDC, we need to configure TRDC for M33 TCM, otherwise A55 can't access the TCM. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com>
2024-09-19imx9: soc: wait ssar when power on power domainPeng Fan
SSAR handshake done means power on finished, not ISO done. so correct the waiting mask. Fixes: 0256577a83b ("imx: imx9: Add MIX power init") Signed-off-by: Peng Fan <peng.fan@nxp.com>
2024-09-18Merge patch series "Fix various bugs"Tom Rini
Simon Glass <sjg@chromium.org> says: This series includes the patches needed to make make the EFI 'boot' test work. That test has now been split off into a separate series along with the EFI patches. This series fixes these problems: - sandbox memory-mapping conflict with PCI - the fix for that causes the mbr test to crash as it sets up pointers instead of addresses for its 'mmc' commands - the mmc and read commands which cast addresses to pointers - a tricky bug to do with USB keyboard and stdio - a few other minor things
2024-09-18test: mbr: Drop a duplicate testSimon Glass
The test currently runs twice as it is declared twice. Unwind this. Signed-off-by: Simon Glass <sjg@chromium.org>
2024-09-18test: mbr: Use RAM for the buffersSimon Glass
The normal approach with sandbox is to use a fixed memory address in the RAM, to avoid needing to create a map for transient local variables. Update this test to use this approach. Signed-off-by: Simon Glass <sjg@chromium.org>
2024-09-18test: mbr: Use a constant for the block sizeSimon Glass
It isn't that important to factor out constants in tests, but in this case we have 0x200 and 512 used. The commands don't use the constant as they use a block count ('1'). It doesn't create more code to use a constant, so create one. Signed-off-by: Simon Glass <sjg@chromium.org>
2024-09-18test: mbr: Unmap the buffers after useSimon Glass
This tests maps some local variables into sandbox's address space. Make sure to unmap them afterwards. Note that the normal approach with sandbox is to use a fixed memory address in the RAM, to avoid needing to create a map for transient local variables. Signed-off-by: Simon Glass <sjg@chromium.org> Fixes: 04291ee0aba ("cmd: mbr: Allow 4 MBR partitions without need...")
2024-09-18cmd: Fix memory-mapping in cmp commandSimon Glass
This unmaps a different address from what was mapped. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org>
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