summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2023-07-24configs: sama5d2: enable CONFIG_LTOEugen Hristev
arm-none-linux-gnueabihf-ld.bfd: u-boot-spl section `__u_boot_list' will not fit in region `.sram' arm-none-linux-gnueabihf-ld.bfd: region `.sram' overflowed by 100 bytes SPL is at limit so to stop seeing above error in built, enable link time optimizations CONFIG_LTO. Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Tested-by: Mihai Sain <mihai.sain@microchip.com>
2023-07-24configs: at91: sama5d2_icp_mmc: Enable CONFIG_LTOStefan Roese
Adding just a tiny bit more code for sama5d2_icp_mmc leads to a SRAM image overflow. Fix this by enabling LTO for this board, so that such changes still can be made to the common U-Boot code. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Pali Rohár <pali@kernel.org> Tested-by: Mihai Sain <mihai.sain@microchip.com> [eugen.hristev@microchip.com: restrict patch just to CONFIG_LTO] Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
2023-07-21Merge branch '2023-07-21-assorted-TI-platform-updates'Tom Rini
- The first half of a number of TI platform bugfixes and improvements, primarily around K3 platforms and splash screen support.
2023-07-21common: Kconfig: Fix CMD_BMP/BMP dependencySamuel Dionne-Riel
Using `default y` will not select BMP when CMD_BMP has been enabled, if it was already configured. By using `select`, if `CMD_BMP` is turned on, it will force the presence of `BMP`. Fixes: 072b0e16c4 ("common: Kconfig: Add BMP configs") Signed-off-by: Samuel Dionne-Riel <samuel@dionne-riel.com> Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
2023-07-21doc: board: ti: am62x_sk: Add A53 SPL DDR layoutNikhil M Jain
To understand usage of DDR in A53 SPL stage, add a table showing region and space used by major components of SPL. Signed-off-by: Nikhil M Jain <n-jain1@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2023-07-21configs: am62x_evm_a53: Add bloblist addressNikhil M Jain
Set bloblist address to 0x80D00000. Signed-off-by: Nikhil M Jain <n-jain1@ti.com> Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
2023-07-21common: spl: spl: Remove video driverNikhil M Jain
Use config SPL_VIDEO_REMOVE to remove video driver at SPL stage before jumping to next stage, in place of CONFIG_SPL_VIDEO, to allow user to remove video if required. Signed-off-by: Nikhil M Jain <n-jain1@ti.com> Reviewed-by: Devarsh Thakkar <devarsht@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-07-21drivers: video: Kconfig: Add config remove videoNikhil M Jain
This is required since user may want to either call the remove method of video driver and reset the display or not call the remove method to continue displaying until next stage. Signed-off-by: Nikhil M Jain <n-jain1@ti.com> Reviewed-by: Devarsh Thakkar <devarsht@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2023-07-21common: board_f: Pass frame buffer info from SPL to u-bootNikhil M Jain
U-boot proper can use frame buffer address passed from SPL to reserve the memory area used by framebuffer set in SPL so that splash image set in SPL continues to get displayed while u-boot proper is running. Put the framebuffer address and size in a bloblist to make them available at u-boot proper, if in u-boot proper CONFIG_VIDEO is defined. Signed-off-by: Nikhil M Jain <n-jain1@ti.com> Reviewed-by: Devarsh Thakkar <devarsht@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-07-21include: video: Reserve video using blobNikhil M Jain
Add method to reserve video framebuffer information using blob, received from previous stage. Signed-off-by: Nikhil M Jain <n-jain1@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-07-21board: ti: am62x: evm: Update function calls for splash screenNikhil M Jain
Use spl_dcache_enable, in place of setup_dram, arch_reserve_mmu to set up pagetable, initialise DRAM and enable Dcache to avoid multiple function calls. Check for CONFIG_SPL_VIDEO in place of CONFIG_SPL_VIDEO_TIDSS to prevent any build failure in case video config is not defined and video related functions are called. Check for CONFIG_SPL_SPLASH_SCREEN and CONFIG_SPL_BMP before calling splash_display to avoid compilation failure. Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
2023-07-21arch: arm: mach-k3: common: Return a pointer after setting page tableNikhil M Jain
In spl_dcache_enable after setting up page table, set gd->relocaddr pointer to tlb_addr, to get next location to reserve memory. Align tlb_addr with 64KB address. Signed-off-by: Nikhil M Jain <n-jain1@ti.com> Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
2023-07-21common: spl: spl: Update stack pointer addressNikhil M Jain
At SPL stage when stack is relocated, the stack pointer needs to be updated, the stack pointer may point to stack in on chip memory even though stack is relocated. Signed-off-by: Nikhil M Jain <n-jain1@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2023-07-21arm: mach-k3: am62a7: change some prints to debug printsBryan Brattlof
There is little need to print the devstat information or when we exit a function during a typical boot. Remove them to reduce the noise during typical operation Signed-off-by: Bryan Brattlof <bb@ti.com>
2023-07-21ram: k3-ddrss: do not touch ctrl regs during trainingBryan Brattlof
During LPDDR initialization we will loop through a series of frequency changes in order to train at the various operating frequencies. During this training, accessing the DRAM_CLASS bitfield could happen during a frequency change and cause the read to hang. Store the DRAM type into the main structure to avoid multiple readings while the independent phy is training. Signed-off-by: Bryan Brattlof <bb@ti.com>
2023-07-21arm: omap2: Fix warning in force_emif_self_refreshTom Rini
The function declaration for force_emif_self_refresh takes no parameters but does not specify this, only the prototype in the headers do. As clang will warn about this, correct it. Signed-off-by: Tom Rini <trini@konsulko.com>
2023-07-21configs: k2x_evm: Always include FIT loading supportAndrew Davis
Non-HS boards can use FIT images so include the env var commands for these unconditionally. Signed-off-by: Andrew Davis <afd@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com>
2023-07-21arm: mach-k3: am62: Fixup CPU core, gpu and pru nodes in fdtEmanuele Ghidoli
AM62x SoC is available in multiple variant: - CPU cores (Cortex-A) AM62x1 (1 core), AM62x2 (2 cores), AM62x4 (4 cores) - GPU AM625x with GPU, AM623x without GPU - PRU (Programmable RT unit) can be present or not on AM62x2/AM62x4 Remove the relevant FDT nodes by reading the actual configuration from the SoC registers, with that change is possible to have a single dts/dtb file handling the different variant at runtime. While removing GPU node and CPU nodes also the watchdog node in the same Module Domain is removed. A similar approach is implemented for example on i.MX8 and STM32MP1 SoC. Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com> Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
2023-07-21arm: mach-k3: am62: Add CTRLMMR_WKUP_JTAG_DEVICE_ID register definitionEmanuele Ghidoli
Add register address and relevant bitmasks and shifts. Allow reading these information: - device identification - number of cores (part of device identification) - features (currently: PRU / no PRU) - security - functional safety - speed grade - temperature grade - package Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com> Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com> Reviewed-by: Andrew Davis <afd@ti.com>
2023-07-21arm: k3: Fix ft_system_setup so it can be enabled on any SoCEmanuele Ghidoli
ft_system_setup cannot be enabled on SoC without msmc sram otherwise fdt_fixup_msmc_ram function fails causing system reset. Fix by moving fdt_fixup_msmc_ram to common_fdt.c file and creating SoC (AM654, J721E and J721S2) specific files for fdt fixups. This change was verified to not change anything on any existing board (all the J721S2, AM654 and J721E boards requires it, none of the remaining k3 boards require it). Fixes: 30e96a240156 ("arm: mach-k3: Move MSMC fixup to SoC level") Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com> Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
2023-07-21arm: dts: Fix build of am62a7 dtbsNishanth Menon
am62a7 should be built with CONFIG_SOC_K3_AM62A7 not CONFIG_SOC_K3_AM625 Fixes: 6bdfa69155d8 ("arm: dts: introduce am62a7 u-boot dtbs") Cc: Bryan Brattlof <bb@ti.com> Cc: Vignesh Raghavendra <vigneshr@ti.com> Cc: Francesco Dolcini <francesco@dolcini.it> Cc: Sjoerd Simons <sjoerd@collabora.com> Cc: Wadim Egorov <w.egorov@phytec.de> Reviewed-by: Bryan Brattlof <bb@ti.com> Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> Signed-off-by: Nishanth Menon <nm@ti.com>
2023-07-21arm: mach-k3: *: dev-data: Update to use ARRAY_SIZENishanth Menon
Instead of hard-coding the count of entries manually, use ARRAY_SIZE to keep the count updates appropriately. Cc: Bryan Brattlof <bb@ti.com> Suggested-by: Ravi Gunasekaran <r-gunasekaran@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
2023-07-21arm: mach-k3: am62a7_init: Open up FSS_DAT_REG3 firewallVignesh Raghavendra
On security enforced (HS-SE) devices ROM firewalls OSPI data region3 that is present in above 64bit region. Open this up in bootloader to allow Linux to access OSPI flashes in mmap mode. Without this kernel will crash when accessing this region due to firewall violations on HS-SE devices. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-07-21common: splash_source: Fix type casting errorsNikhil M Jain
During compilation splash_source puts out below warning for type conversion in splash_load_fit for bmp_load_addr and fit_header. Change their type to uintptr_t to fix the warnings. common/splash_source.c: In function ‘splash_load_fit’: common/splash_source.c:366:22: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] 366 | img_header = (struct legacy_img_hdr *)bmp_load_addr; | ^ common/splash_source.c:376:49: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] 376 | res = splash_storage_read_raw(location, (u32)fit_header, fit_size); | ^ common/splash_source.c:401:25: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] 401 | memmove((void *)bmp_load_addr, internal_splash_data, internal_splash_size); The above warnings are generated if CONFIG_FIT is enabled. Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
2023-07-21board: ti: am62x: evm: Include necessary header filesNikhil M Jain
At the time of compilation evm.c gives below warning for implicit declaration of enable_caches, to mitigate this include cpu_func.h. board/ti/am62x/evm.c: In function ‘spl_board_init’: board/ti/am62x/evm.c:90:9: warning: implicit declaration of function ‘enable_caches’ [-Wimplicit-function-declaration] 90 | enable_caches(); Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
2023-07-21Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxiTom Rini
For once this adds USB support for two SoCs: the H616 and the F1C100s series. The rest is support for LPDDR3 DRAM chips on H616 boards. Gitlab CI passed, and I booted that briefly on an H616 and an F1C200s board. I don't have an H616 board with LPDDR3 DRAM, but reportedly that works for Mikhail, and doesn't regress on my DDR3 boards.
2023-07-21Merge tag 'xilinx-for-v2023.10-rc1-v2' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2023.10-rc1 v2 axi_emac: - Change return value if RX packet is not ready cadence_qspi: - Enable flash reset for Versal NET dt: - Various DT syncups with Linux kernel - SOM - reserved pmufw memory location fpga: - Add load event mtd: - Add missing dependency for FLASH_CFI_MTD spi/nand: - Minor cleanup in Xilinx drivers versal-net: - Prioritize boot device in boot_targets - Wire mini ospi/qspi/emmc configurations watchdog: - Use new versal-wwdt property xilinx: - fix sparse warnings in various places ps7_init* - add missing headers - consolidate code around zynqmp_mmio_read/write - switch to amd.com email zynqmp_clk: - Add handling for gem rx/tsu clocks zynq_gem: - Configure mdio clock at run time zynq: - Enable fdt overlay support zynq_sdhci: - Call dll reset only for ZynqMP SOCs
2023-07-21event: Add fpga load eventChristian Taedcke
This enables implementing custom logic after a bitstream was loaded into the fpga. Signed-off-by: Christian Taedcke <christian.taedcke@weidmueller.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Link: https://lore.kernel.org/r/20230720072724.11516-1-christian.taedcke-oss@weidmueller.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-07-21clk: zynqmp: Add gem rx and tsu clocks to return registerAshok Reddy Soma
Add gem_tsu and gem0_rx till gem3_rx to return proper register from zynqmp_clk_get_register. Otherwise firmware won't be able to set clock for these due to incorrect register address. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20230720072859.3724-1-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-07-21clk: zynqmp: Add set_rate support for gem rx and tsu clksAshok Reddy Soma
gem0_rx till gem3_rx and gem_tsu are missing from set rate function. Add them, so that they can be set from pmu firmware via clock framework. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20230719084912.30209-1-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-07-21net: axi_emac: Change return value to -EAGAIN if RX is not readyMaksim Kiselev
If there is no incoming package than axiemac_recv will return -1 which in turn leads to printing `eth_rx: recv() returned error -1` error message in eth_rx function. But missing a package is not an fatal error, so return -EAGAIN in that case would be more suitable. Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com> Link: https://lore.kernel.org/r/20230719065337.69280-1-bigunclemax@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-07-21arm64: zynqmp: Remove clock-names from pcap nodeMichal Simek
Clock is not used in driver and also not described in binding. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/0a0fa0ba197fa4051a2c8a24e1451cefadce7517.1688992653.git.michal.simek@amd.com
2023-07-21arm64: zynqmp: Rename ams_ps/pl node namesMichal Simek
Fix child node names to be aligned with dt-binding available in the Linux kernel which requires names as ams-ps@ and ams-pl@. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/8f1451d614f654cb0d0da1e799e876c078fbf2c9.1688992653.git.michal.simek@amd.com
2023-07-21arm64: zynqmp: Remove interrupt/reg-names for AMSMichal Simek
These two properties are not described in DT binding and also not used by driver that's why remove them. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/b123c7e537dcf70802e828bbcd484a761a264186.1688992653.git.michal.simek@amd.com
2023-07-21arm64: zynqmp: remove snps, enable_guctl1_resume_quirk quirk for usbPiyush Mehta
To sync with the upstream code, removed 'snps,enable_guctl1_resume_quirk' quirk for usb. This quirk is no more available in linux after the xilinx release 2022.2. This functionality is taken care of by the 'snps,resume-hs-terminations' quirk. Signed-off-by: Piyush Mehta <piyush.mehta@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/4b7a132116bf0248cdb558e04de3b06b412c4a0f.1688992653.git.michal.simek@amd.com
2023-07-21arm64: zynqmp: add pmu interrupt-affinityRadhey Shyam Pandey
Explicitly specify interrupt affinity to avoid HW perfevents need to guess. This avoids the following error upon linux boot: armv8-pmu pmu: hw perfevents: no interrupt-affinity property, guessing. Reported-by: John Toomey <john.toomey@amd.com> Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/c2f55a10cf54c6004f5dfe2ea18bcb4cf04f5723.1688992653.git.michal.simek@amd.com
2023-07-21arm64: zynqmp: Sync node name address with reg (mailbox)Michal Simek
Address in node name should match with the first reg property in DT. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/47bea10bbc3c88727c1fe839ff20e15a0c79c339.1688992653.git.michal.simek@amd.com
2023-07-21arm64: zynqmp: Add L2 cache nodesRadhey Shyam Pandey
Linux kernel throws "cacheinfo: Unable to detect cache hierarchy for CPU 0" warning when booting on zu+ Soc. To fix it add the L2 cache node and let each CPU point to it. Reported-by: John Toomey <john.toomey@amd.com> Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/c8dfabab12c97922aaad7fa91be0cbc7e4021528.1688992653.git.michal.simek@amd.com
2023-07-21arm64: zynqmp: Fix usb reset over bootmode pins on zcu100Michal Simek
The commit a4180c369607 ("arm64: zynqmp: Add mode-pin GPIO controller DT node") added usb phy reset over bootmode pins by default on usb0 only. zcu100 is using usb0 as peripheral and usb1 as host. Unfortunately reset line is shared for both usb ulpi phys but usb_rst_b is connected to usb5744 hub which is used only in host mode. Especially this chip requires reset to operate properly that's why better assign gpio reset to usb1 instead of usb0. Without this change usb start crashed when runs. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/1ca80ec5bf7a595c03822f3e4e3683298205067a.1688992653.git.michal.simek@amd.com
2023-07-21arm64: zynqmp: Cover K24 revB/1 SOMMichal Simek
Extend compatible versions for K24 SOM. Changes are not affecting SW behavior that's why all versions are compatible to each other. Describing all revisions is done by purpose because user space SW is reading compatible string for logic around DT overlays and bitstreams. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/92eba01ac316e58bd2d3508b0e63bbfafbedbb73.1688992653.git.michal.simek@amd.com
2023-07-21arm64: zynqmp: Record compatible string for kv260 rev2Michal Simek
PCB rev2 compare to rev1 has some changes in PL side (IAS sensor AR1335 autofocus feature). PS side is completely unchanged. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/42f78dee8429eeac016d73de5c73af46fdaf4a98.1688992653.git.michal.simek@amd.com
2023-07-21arm64: zynqmp: Assign TSU clock frequency for KV and KD boardsHarini Katakam
Set TSU clock frequency as 250MHz (minimum when running at 1G) on KV and KD carrier cards to allow PTP functionality. Signed-off-by: Harini Katakam <harini.katakam@amd.com> Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/4b758d503ef545e4d25d3930b0eb0793f1c415d2.1688992653.git.michal.simek@amd.com
2023-07-21arm64: zynqmp: Increase reset assert time for TI SGMII PHYHarini Katakam
Increase reset assert time for TI SGMII PHY on KR260 CC starting 6.1 kernel. This PHY does not come out of reset with the existing 100us pulse width as per testing on multiple carrier cards. The reset is driven via a PCA9570 I2C expander. The expander driver was updated to an upstream version in 6.1 where gpio_chip _set was optimized. Delays in earlier kernels may have masked this issue. This is a safe workaround value for assert pulse width before the discussions are resolved with TI. Signed-off-by: Harini Katakam <harini.katakam@amd.com> Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/8fb9f17d43a43ef504c9f29006cd686cce8ac98b.1688992653.git.michal.simek@amd.com
2023-07-21arm64: zynqmp: Fix gpio comment about No of gpiosMichal Simek
There are total 174 gpios but from 0 - 173 that's why fix comment to reflect it. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/c7e94b334e7dd6297e0d3a36a6a3d04bd7e9e967.1688992653.git.michal.simek@amd.com
2023-07-21arm64: zynqmp: Assign TSU clock frequency for KR260Harini Katakam
Set TSU clock frequency as 250MHz (minimum when running at 1G) on KR260 CC to allow PTP functionality. Signed-off-by: Harini Katakam <harini.katakam@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/d065b5c2c6450910bf57d104d65946111493caaa.1688992653.git.michal.simek@amd.com
2023-07-21arm64: zynqmp: Update MALI 400 interrupt and clock namesParth Gajjar
Motivation for the commit is to utilize the upstream community device tree so that the either modified ARM Mali 400 driver or upstream lima driver can be used. Signed-off-by: Parth Gajjar <parth.gajjar@amd.com> Signed-off-by: Vishal Sagar <vishal.sagar@amd.com> Link: https://lore.kernel.org/r/1678181001-2327-2-git-send-email-parth.gajjar@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/89d046a9da5638e8b4918f80f3245d73ea46f99f.1688992653.git.michal.simek@amd.com
2023-07-21xilinx: dts: Fix open drain warning on Zynq, ZynqMP and VersalManikanta Guntupalli
Fix for below open drain warning on Zynq, ZynqMP and Versal reported by Linux. "enforced open drain please flag it properly in DT/ACPI DSDT/board file." Signed-off-by: Manikanta Guntupalli <manikanta.guntupalli@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/056b6f60f89fa2addb762669b80640cd5b31b001.1688992653.git.michal.simek@amd.com
2023-07-21arm: xilinx: Setting default i2c clock frequency to 400kHzVaralaxmi Bingi
Setting default i2c clock frequency for Zynq and ZynqMP to maximum rate of 400kHz. Current default value is 100kHz. Signed-off-by: Varalaxmi Bingi <varalaxmi.bingi@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/fb46fe911a68b79c8e4d150ca90c4e94eb5fb9e1.1688992653.git.michal.simek@amd.com
2023-07-21mtd: Add missing MTD dependency for cfi_mtdMichal Simek
cfi_mtd requires add_mtd_device() which is available only when MTD is enabled that's why record this dependency. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/76ae01ce2b2c988758b69e0f0cdcc21bf301c01e.1688472227.git.michal.simek@amd.com
2023-07-21mmc: zynq_sdhci: Dll reset only for ZynqMP platformAshok Reddy Soma
Dll reset is needed only for ZynqMP platforms, add condition in tuning to call arasan_zynqmp_dll_reset() just for ZynqMP platforms. On other platforms like Versal NET, If this condition is not added, we see PLM error messages when dll reset smc is called. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/d673ff3bdc5c236a7f0403c920e719684abd6059.1688991117.git.michal.simek@amd.com
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-06 19:09:00 +0000