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2023-03-29imx: sentinel: Update S400 API get info message structureYe Li
From Sentinel FW v0.0.9-9df0f503, the response message of get info API is changed to add OEM SRK and some states (IMEM, CSAL, TRNG). With old structure, we get failure from sentinel due to the buffer size can't fit with new response message. So update the API structure to fix the issue. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-03-29imx: imx8ulp: Update clocks to meet max rate restrictionsYe Li
Update PLL3/PLL4 PFD and USDHC clocks to meet maximum frequency restrictions. Detail clock rate changes in the patch: PLL3 PFD2: 389M -> 324M PLL3 PFD3: 336M -> 389M PLL3 PFD3: DIV1 336M -> 389M (OD), 194M (ND/LD) PLL3 PFD3: DIV2 336M -> 194M (OD), 97M (ND/LD) PLL4 PFD0: 792M -> 594M PLL4 PFD2: 792M -> 316.8M NIC_AP: 96M (ND) -> 192M, 48M (LD) -> 96M NIC_LPAV: 198 (ND) -> 192M, 99M (LD) -> 96M USDHC0: PLL3 PFD3 DIV1, 389M (OD), 194M (ND/LD) USDHC1: PLL3 PFD3 DIV2, 194M (OD), 97M (ND/LD) USDHC2: PLL3 PFD3 DIV2, 194M (OD), 97M (ND/LD) Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-03-29imx: imx8ulp: Configure XRDC PDAC and MSC for DBD owner=S400 onlyYe Li
This patch is used to support DBD owner fuse changed to S400 only. The XRDC PDAC2 for LPAV pbridge5 and MSC1/2/3 for GPIO and LPAV are not configured by S400 default setting. So these PDAC and MSC are invalid, only DBD owner can access the corresponding resources. We have to configure necessary PDAC and MSC for SPL before DDR initialization. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-03-29imx: imx8ulp: upower: make code cleanerPeng Fan
To clean the upower codes by aligning codes format, check err_code and add detail bits list for the memory magic number Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-03-29imx: imx8ulp: upower: replace magic number with macroPeng Fan
The swton indicates the logic switch, magic number 0xfff80 is hard to understand, so use macro. Some board design may not have MIPI_CSI voltage input connected per data sheet. In that case, the upower power on API may dead loop mu to wait response, however there is no response. So remove MIPI_CSI here, let linux power domain driver to runtime enable the power domain. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-03-29imx: imx8ulp: Clear dividers in PLL3DIV_PFD registersYe Li
At present, in cgc1_pll3_init we don't set the pll3pfd div values, just use the default 0. But on A1 part, ROM will set PLL3 pfd1div2 to 1 and pfd2div1 to 3. This finally causes some clocks' rate decreased, for example USDHC. So clear the PLL3DIV_PFD dividers to get correct rate. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-03-29imx: imx8ulp: Reconfigure MRC3 for SRAM0 accessYe Li
Some space in SRAM0 will be protected by S400 to allow RX SecPriv mode access only for boot purpose. Since SW will reuse the SRAM0 as SCMI buffer and SPL container loading buffer, need to reconfigure MRC3. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-03-29ddr: imx8ulp: Change DRAM timing save area to 0x20055000Ye Li
To align with ARM trusted firmware's change, adjust DRAM timing save area to new position 0x20055000. So we can release the space since 0x2006c000 for the NOBITS region of ARM trusted firmware Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com>
2023-03-29imx: imx8ulp: configure XRDC for DRAM access from S400Ye Li
Need to add DRAM access permission for S400, as S400 needs to access it When SPL calls image authentication Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-03-29imx: imx8ulp: Adjust handshake to sync TRDC and XRDC completionYe Li
To fit the DBD_EN fused part, we re-design the TRDC and XRDC assignment. M33 will be the TRDC owner and needs to configure TRDC. A35 is the XRDC owner, ATF will configure XRDC. The handshake between U-boot and M33 image is used to sync TRDC and XRDC configuration completion. Once the handshake is done, A35 and M33 can access the allowed resources in others domain. The handshake is needed when M33 is booted or DBD_EN fused, because both cases will enable the TRDC. If handshake is timeout, the boot will hang. We use SIM GPR0 to pass the info from SPL to u-boot, because before the handshake, u-boot can't access SEC SIM and FSB. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com>
2023-03-29imx: imx8ulp: Remove the TRDC configure from A35Ye Li
As M33 is responsible for TRDC configuration, the settings for A35 nonsecure world access and DMA0 access are moved to M33 image. So remove the codes to release TRDC and configure it. Just keep the configurations for reference. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com>
2023-03-29imx: imx8ulp: Set XRDC MRC4/5 for access DDR from APDYe Li
iMX8ULP A1 S400 ROM removes the setting for MRC4/5. So we have to set them in SPL to allow access to DDR from A35 and APD PER masters Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-03-29imx: imx8ulp: Limit the eMMC ROM API workaround to A0.1 partYe Li
Since A1 ROM has fixed the ROM API eMMC issue, we should only use the workaround for A0.1 part. Add a SOC revision check. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-03-29imx: imx8ulp: Get chip revision from SentinelYe Li
In both SPL and u-boot, after probing the S400 MU, get the chip revision, lifecycle and UID from Sentinel. Update get_cpu_rev to use the chip revision not hard coded it for A0 Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-03-29imx: imx8ulp: Fix MU device probe failureYe Li
Since latest DTS has added multiple MU nodes, using compatible string to find the device node is not proper. It finds the first node with the compatible string matched even the node is disabled. Signed-off-by: Ye Li <ye.li@nxp.com>
2023-03-28Merge tag 'u-boot-at91-2023.07-a' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-at91 into next First set of u-boot-at91 features for the 2023.07 cycle: This feature set includes the clock changes required for sam9x60 SoC to support USB host.
2023-03-27Revert "rockchip: Fix early use of bootph props"Tom Rini
While this change is correct for v2023.04 it is not correct for next (where this is right now) nor post-v2023.04. This reverts commit 8653e5d3b745925fced5fa6897c92f4a46ec2757. Signed-off-by: Tom Rini <trini@konsulko.com>
2023-03-27Merge branch 'master' into nextTom Rini
2023-03-27Prepare v2023.04-rc5v2023.04-rc5Tom Rini
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-03-27configs: Resync with savedefconfigTom Rini
Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
2023-03-27Merge branch '2023-03-27-rockchip-rk3399-fixes'Tom Rini
- A series of minor cleanups to DISTRO_DEFAULTS and BOOTSTD so that the rk3399 bootstd migration can be complete and functional now, and make future migrations easier.
2023-03-27rockchip: rk3399: Drop altbootcmdTom Rini
The defined altbootcmd was specific to distro_bootcmd which is not longer in use on these platforms, so drop it. Tested-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
2023-03-27rockchip: Use BOOTSTD_DEFAULTS if not DISTRO_DEFAULTSTom Rini
When we do not enable DISTRO_DEFAULTS (generally, to get distro_bootcmd) we instea do want to imply BOOTSTD_DEFAULTS so that when using bootstd the general distro boot functionality will still work. Signed-off-by: Tom Rini <trini@konsulko.com>
2023-03-27rockchip: Disable DISTRO_DEFAULTS for rk3399 boardsSimon Glass
These board have moved to standard boot but the old 'distro_bootcmd' command is still active. Disable DISTRO_DEFAULTS to fix this. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Vagrant Cascadian <vagrant@debian.org>
2023-03-27boot: Create a common BOOT_DEFAULTS for distro and bootstdSimon Glass
These two features use a lot of common options. Move them into a common CONFIG to reduce duplication. Use 'select' for most options since these are things that boards aren't supposed to override. For now it is not possible to disable BOOT_DEFAULTS but we may take another look later. Note that five options use 'imply' to match existing behaviour. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Rework a bit so we don't grow so many platforms unintentionally] Signed-off-by: Tom Rini <trini@konsulko.com>
2023-03-27lmb: Enable LMB if SYS_BOOT_RAMDISK_HIGHSimon Glass
Ramdisk relocation requires LMB, so enable it automatically to avoid build errors. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-03-27Move DISTRO_DEFAULTS into boot/Simon Glass
This relates to booting so move it in to that Kconfig file, before changing it. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-03-27rockchip: Drop bootstage stash in TPL and SPL for rockpro64Simon Glass
Unfortunately the IRAM used to stash the bootstage records in TPL becomes inaccessible after SPL runs. Presumably this is because of ATF taking it over. We could move the stash to another address in SPL, before passing it to U-Boot proper. But it seems easier to wait until we have support for standard passage[1] which should not be too far away. For now, disable it in TPL and SPL. [1] https://patchwork.ozlabs.org/project/uboot/cover/ 20220117150428.1580273-1-sjg@chromium.org/ Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Vagrant Cascadian <vagrant@debian.org>
2023-03-27Merge https://source.denx.de/u-boot/custodians/u-boot-x86Tom Rini
- x86: Bug fixes of previous BayTrail platform CONFIG_TEXT_BASE changes
2023-03-27configs: at91: sam9x60: Add required configs for the USB clockSergiu Moga
Add the configs required to use the SAM9X60's USB clock. Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> [claudiu.beznea: added CONFIG_AT91_SAM9X60_USB to sam9x60_curiosity_mmc1_defconfig] Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2023-03-27clk: at91: sam9x60: Add initial setup of UPLL and USBCK ratesSergiu Moga
In order for some of the functionalities, such as the USB clocks, to work properly we need some clocks to be properly initialised at the very beginning of booting. Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2023-03-27clk: at91: pmc: export clock setup to pmcClaudiu Beznea
Clock setup was intended for setting clocks at boot time on SAMA7G5, e.g. for root clocks like PLLs, that were used to feed IPs needed alive in u-boot (e.g. Ethernet clock feed by a PLL). Export this functionality to all at91 clocks as it may be necessary on other SoCs. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2023-03-27clk: at91: sam9x60: Register the required clocks for USBSergiu Moga
Register into DM the clocks required to properly enable USB functionality within the bootloader. Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2023-03-27clk: at91: Add support for sam9x60 USB clockSergiu Moga
Implement sam9x60 USB clock driver. This clock has three parents: PLLA, UPLL and MAINXTAL. The driver is aware of the three possible parents with the help of the two mux tables provied to the driver during the registration of the clock. Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2023-03-27x86: som-db5800-som-6867: Fix up adjustment of CONFIG_TEXT_BASESimon Glass
With recent CONFIG_TEXT_BASE changes, there are inconsistencies between several settings. Adjust CONFIG_SYS_MONITOR_LEN to allow more code space. Move the MRC cache out of the way too. Fixes: e23cae30801f ("x86: som-db5800-som-6867: Adjust CONFIG_TEXT_BASE") Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-03-27x86: dfi-bt700: Fix up adjustment of CONFIG_TEXT_BASESimon Glass
With recent CONFIG_TEXT_BASE changes, there are inconsistencies between several settings. Adjust CONFIG_SYS_MONITOR_LEN to allow more code space. Move the MRC cache out of the way too. Fixes: 5d1c8342aeaa ("x86: dfi-bt700: Adjust CONFIG_TEXT_BASE") Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-03-27x86: conga-qeval20-qa3-e3845: Fix up adjustment of CONFIG_TEXT_BASESimon Glass
With recent CONFIG_TEXT_BASE changes, there are inconsistencies between several settings. Adjust CONFIG_SYS_MONITOR_LEN to allow more code space. Move the MRC cache out of the way too. Fixes: 388f93f96354 ("x86: conga-qeval20-qa3-e3845: Adjust CONFIG_TEXT_BASE") Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
2023-03-27x86: bayleybay: Fix up adjustment of CONFIG_TEXT_BASESimon Glass
With recent CONFIG_TEXT_BASE changes, there are inconsistencies between several settings. Adjust CONFIG_SYS_MONITOR_LEN to allow more code space. Move the MRC cache out of the way too. Fixes: f38be3086837 ("x86: bayleybay: Adjust CONFIG_TEXT_BASE") Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-03-27x86: minnowmax: Fix up adjustment of CONFIG_TEXT_BASESimon Glass
With recent CONFIG_TEXT_BASE changes, there are inconsistencies between several settings. Adjust CONFIG_SYS_MONITOR_LEN to allow more code space. Move the MRC cache out of the way too. Add documentation on how to make this change safely. Fixes: 66e2c665f3b6 ("x86: minnowmax: Adjust CONFIG_TEXT_BASE") Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-03-25Merge tag 'efi-next-20230325' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-efi into next Pull request for efi-next-20230325 Documenation: * add man-page for efi command UEFI: * Let EFI app call ExitBootServices() before legacy booting kernel * Support zboot and bootm in the EFI app * Let efi command show configuration tables * Support booting a 64-bit kernel from 64-bit EFI app * Allocate device-tree copy from high memory * simplify efi_str_to_u16()
2023-03-25Merge tag 'efi-2023.04-rc5' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-efi Pull request for efi-2023.04-rc5 UEFI: * Create unique device paths for USB devices with the same vendor and product id.
2023-03-25cmd: bootefi: allocate device-tree copy from high memoryHeinrich Schuchardt
The bootefi command creates a copy of the device-tree within the first 127 MiB of memory. This may lead to overwriting previously loaded binaries (e.g. kernel, initrd). Linux EFI stub itself copies U-Boot's copy of the device-tree. This means there is not restriction for U-Boot to place the device-tree copy to any address. (Restrictions existed for 32bit ARM before Linux commit 7a1be318f579 ("ARM: 9012/1: move device tree mapping out of linear region") for legacy booting. Reported-by: Alexandre Ghiti <alexghiti@rivosinc.com> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Tested-by: Alexandre Ghiti <alexghiti@rivosinc.com>
2023-03-25efI: Allow packaging a kernel in the debugging scriptSimon Glass
Add an option to package a kernel into the debugging script used for EFI. The name of the kernel must be added to the script. By default it is assumed that the kernel is built in the /tmp/kernel directory. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-03-25efi: Support showing tablesSimon Glass
Add a command (for the app and payload) to display the tables provided by EFI. Note that for the payload the tables should always be present, so an error message is unnecessary and would bloat the code. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-03-25efi: Split out table-listing code into a new fileSimon Glass
This code is used with EFI_LOADER but is also useful (with some modifications) for the EFI app and payload. Move it into a shared file. Show the address of the table so it can be examined if needed. Also show the table name as unknown if necessary. Our list of GUIDs is fairly small. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-03-25doc: Add help for the efi commandSimon Glass
This command currently has no help. Add some. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-03-25efi: Include GUID names with EFI app and payloadSimon Glass
These are currently only available when running with EFI_LOADER. Expand this to include the app and payload, since it is useful to be able to decode things there. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-03-25efi: Add another tranch of GUIDsSimon Glass
Provide information about the GUIDs supplied by QEMU, so far as it is known. These values are used in the 'efi table' command as well as the printf format string %sU Signed-off-by: Simon Glass <sjg@chromium.org>
2023-03-25x86: Support zboot and bootm in the EFI appSimon Glass
These have been disabled due to the rudimentary support available. It is a little better now, so enable these options. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2023-03-25x86: Exit EFI boot services before starting kernelSimon Glass
When running the EFI app, we need to exit boot services before jumping to Linux. At some point it may be possible to jump to Linux and pass on the system table, and: * install the device-tree as configuration table * use LoadImage() to load the kernel image (e.g. from memory) * start the image with StartImage() This should allow the Linux efistub to be used. For now, this is not implemented. Signed-off-by: Simon Glass <sjg@chromium.org>
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